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r4583 Wednesday 29th April, 2009 at 00:24:28 UTC by Fabio Priuli
New round of number-to-tag conversions in CPU calls

[src/mess/drivers]	nc.c nes.c newbrain.c p2000t.c palm.c pasogo.c pce.c pcw.c pcw16.c pentagon.c pk8020.c pp01.c psx.c px4.c ql.c
[src/mess/machine]	nascom1.c nes.c nes_mmc.c ondra.c oric.c orion.c osborne1.c partner.c pc1251.c pc1350.c pc1401.c pc1403.c pc8801.c pce.c pdp1.c pecom.c pk8020.c pmd85.c pokemini.c pp01.c primo.c radio86.c
[src/mess/video]	odyssey2.c oric.c pc8801.c pdp1.c pecom.c primo.c

src/mess/video/pdp1.c

r4582	r4583
303	303	static void pdp1_draw_panel(running_machine *machine, bitmap_t *bitmap)
304	304	{
305	305	/* column 1: registers, test word, test address */
306		pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset+2*8, y_panel_pc_offset+8, cpu_get_reg(machine->cpu[0], PDP1_PC), 16);
307		pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset+2*8, y_panel_ma_offset+8, cpu_get_reg(machine->cpu[0], PDP1_MA), 16);
308		pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset, y_panel_mb_offset+8, cpu_get_reg(machine->cpu[0], PDP1_MB), 18);
309		pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset, y_panel_ac_offset+8, cpu_get_reg(machine->cpu[0], PDP1_AC), 18);
310		pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset, y_panel_io_offset+8, cpu_get_reg(machine->cpu[0], PDP1_IO), 18);
311		pdp1_draw_switch(machine, bitmap, x_panel_col1_offset, y_panel_ta_offset+8, cpu_get_reg(machine->cpu[0], PDP1_EXTEND_SW));
312		pdp1_draw_multipleswitch(machine, bitmap, x_panel_col1_offset+2*8, y_panel_ta_offset+8, cpu_get_reg(machine->cpu[0], PDP1_TA), 16);
313		pdp1_draw_multipleswitch(machine, bitmap, x_panel_col1_offset, y_panel_tw_offset+8, cpu_get_reg(machine->cpu[0], PDP1_TW), 18);
	306	pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset+2*8, y_panel_pc_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_PC), 16);
	307	pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset+2*8, y_panel_ma_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_MA), 16);
	308	pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset, y_panel_mb_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_MB), 18);
	309	pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset, y_panel_ac_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_AC), 18);
	310	pdp1_draw_multipleled(machine, bitmap, x_panel_col1_offset, y_panel_io_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_IO), 18);
	311	pdp1_draw_switch(machine, bitmap, x_panel_col1_offset, y_panel_ta_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_EXTEND_SW));
	312	pdp1_draw_multipleswitch(machine, bitmap, x_panel_col1_offset+2*8, y_panel_ta_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_TA), 16);
	313	pdp1_draw_multipleswitch(machine, bitmap, x_panel_col1_offset, y_panel_tw_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_TW), 18);
314	314
315	315	/* column 2: 1-bit indicators */
316		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_run_offset, cpu_get_reg(machine->cpu[0], PDP1_RUN));
317		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_cyc_offset, cpu_get_reg(machine->cpu[0], PDP1_CYC));
318		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_defer_offset, cpu_get_reg(machine->cpu[0], PDP1_DEFER));
	316	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_run_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_RUN));
	317	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_cyc_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_CYC));
	318	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_defer_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_DEFER));
319	319	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_hs_cyc_offset, 0);   /* not emulated */
320		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_brk_ctr_1_offset, cpu_get_reg(machine->cpu[0], PDP1_BRK_CTR) & 1);
321		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_brk_ctr_2_offset, cpu_get_reg(machine->cpu[0], PDP1_BRK_CTR) & 2);
322		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ov_offset, cpu_get_reg(machine->cpu[0], PDP1_OV));
323		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_rim_offset, cpu_get_reg(machine->cpu[0], PDP1_RIM));
324		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_sbm_offset, cpu_get_reg(machine->cpu[0], PDP1_SBM));
325		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_exd_offset, cpu_get_reg(machine->cpu[0], PDP1_EXD));
326		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ioh_offset, cpu_get_reg(machine->cpu[0], PDP1_IOH));
327		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ioc_offset, cpu_get_reg(machine->cpu[0], PDP1_IOC));
328		pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ios_offset, cpu_get_reg(machine->cpu[0], PDP1_IOS));
	320	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_brk_ctr_1_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_BRK_CTR) & 1);
	321	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_brk_ctr_2_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_BRK_CTR) & 2);
	322	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ov_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_OV));
	323	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_rim_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_RIM));
	324	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_sbm_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_SBM));
	325	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_exd_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_EXD));
	326	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ioh_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_IOH));
	327	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ioc_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_IOC));
	328	pdp1_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ios_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_IOS));
329	329
330	330	/* column 3: power, single step, single inst, sense, flags, instr... */
331	331	pdp1_draw_led(machine, bitmap, x_panel_col3_offset, y_panel_power_offset, 1);   /* always on */
332	332	pdp1_draw_switch(machine, bitmap, x_panel_col3_offset+8, y_panel_power_offset, 1);   /* always on */
333		pdp1_draw_led(machine, bitmap, x_panel_col3_offset, y_panel_sngl_step_offset, cpu_get_reg(machine->cpu[0], PDP1_SNGL_STEP));
334		pdp1_draw_switch(machine, bitmap, x_panel_col3_offset+8, y_panel_sngl_step_offset, cpu_get_reg(machine->cpu[0], PDP1_SNGL_STEP));
335		pdp1_draw_led(machine, bitmap, x_panel_col3_offset, y_panel_sngl_inst_offset, cpu_get_reg(machine->cpu[0], PDP1_SNGL_INST));
336		pdp1_draw_switch(machine, bitmap, x_panel_col3_offset+8, y_panel_sngl_inst_offset, cpu_get_reg(machine->cpu[0], PDP1_SNGL_INST));
337		pdp1_draw_multipleled(machine, bitmap, x_panel_col3_offset, y_panel_ss_offset+8, cpu_get_reg(machine->cpu[0], PDP1_SS), 6);
338		pdp1_draw_multipleswitch(machine, bitmap, x_panel_col3_offset, y_panel_ss_offset+2*8, cpu_get_reg(machine->cpu[0], PDP1_SS), 6);
339		pdp1_draw_multipleled(machine, bitmap, x_panel_col3_offset, y_panel_pf_offset+8, cpu_get_reg(machine->cpu[0], PDP1_PF), 6);
340		pdp1_draw_multipleled(machine, bitmap, x_panel_col3_offset, y_panel_ir_offset+8, cpu_get_reg(machine->cpu[0], PDP1_IR), 5);
	333	pdp1_draw_led(machine, bitmap, x_panel_col3_offset, y_panel_sngl_step_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_SNGL_STEP));
	334	pdp1_draw_switch(machine, bitmap, x_panel_col3_offset+8, y_panel_sngl_step_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_SNGL_STEP));
	335	pdp1_draw_led(machine, bitmap, x_panel_col3_offset, y_panel_sngl_inst_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_SNGL_INST));
	336	pdp1_draw_switch(machine, bitmap, x_panel_col3_offset+8, y_panel_sngl_inst_offset, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_SNGL_INST));
	337	pdp1_draw_multipleled(machine, bitmap, x_panel_col3_offset, y_panel_ss_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_SS), 6);
	338	pdp1_draw_multipleswitch(machine, bitmap, x_panel_col3_offset, y_panel_ss_offset+2*8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_SS), 6);
	339	pdp1_draw_multipleled(machine, bitmap, x_panel_col3_offset, y_panel_pf_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_PF), 6);
	340	pdp1_draw_multipleled(machine, bitmap, x_panel_col3_offset, y_panel_ir_offset+8, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_IR), 5);
341	341	}
342	342
343	343

src/mess/video/pc8801.c

r4582	r4583
298	298	}
299	299
300	300
301		if (rh5) memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xc000, 0xefff, 0, 0, rh5);
302		if (wh5) memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xc000, 0xefff, 0, 0, wh5);
303		if (rh6) memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xf000, 0xffff, 0, 0, rh6);
304		if (wh6) memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xf000, 0xffff, 0, 0, wh6);
	301	if (rh5) memory_install_read8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xc000, 0xefff, 0, 0, rh5);
	302	if (wh5) memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xc000, 0xefff, 0, 0, wh5);
	303	if (rh6) memory_install_read8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xf000, 0xffff, 0, 0, rh6);
	304	if (wh6) memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xf000, 0xffff, 0, 0, wh6);
305	305	}
306	306
307	307	WRITE8_HANDLER(pc88sr_disp_32)

src/mess/video/oric.c

r4582	r4583
121	121	{
122	122	/* attribute */
123	123	int attribute = c & 0x03f;
124		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	124	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
125	125
126	126	switch ((attribute>>3) & 0x03)
127	127	{
r4582	r4583
299	299	}
300	300
301	301	/* fetch data */
302		c = RAM ? RAM[read_addr] : memory_read_byte(cpu_get_address_space(screen->machine->cpu[0], ADDRESS_SPACE_PROGRAM), read_addr);
	302	c = RAM ? RAM[read_addr] : memory_read_byte(cputag_get_address_space(screen->machine, "maincpu", ADDRESS_SPACE_PROGRAM), read_addr);
303	303
304	304	/* if bits 6 and 5 are zero, the byte contains a serial attribute */
305		if ((c & ((1<<6) | (1<<5)))==0)
	305	if ((c & ((1 << 6) | (1 << 5))) == 0)
306	306	{
307		oric_vh_update_attribute(screen->machine,c);
	307	oric_vh_update_attribute(screen->machine, c);
308	308
309	309	/* display background colour when attribute has been found */
310		oric_vh_render_6pixels(bitmap,x,y,vh_state.active_foreground_colour, vh_state.active_background_colour, 0,(c & 0x080));
	310	oric_vh_render_6pixels(bitmap, x, y, vh_state.active_foreground_colour, vh_state.active_background_colour, 0, (c & 0x080));
311	311
312		if (y<200)
	312	if (y < 200)
313	313	{
314	314	/* is hires active? */
315		if (vh_state.mode & (1<<2))
	315	if (vh_state.mode & (1 << 2))
316	316	{
317	317	hires_active = 1;
318	318	}

src/mess/video/odyssey2.c

r4582	r4583
174	174	{
175	175	int i;
176	176
177		for ( i = 0; i < 24; i++ ) {
	177	for ( i = 0; i < 24; i++ )
	178	{
178	179	palette_set_color_rgb( machine, i, odyssey2_colors[i*3], odyssey2_colors[i*3+1], odyssey2_colors[i*3+2] );
179	180	}
180	181	}
r4582	r4583
188	189	case 0xa1:
189	190	data = control_status;
190	191	iff = 0;
191		cpu_set_input_line(space->machine->cpu[0], 0, CLEAR_LINE);
	192	cputag_set_input_line(space->machine, "maincpu", 0, CLEAR_LINE);
192	193	control_status &= ~ 0x08;
193		if ( video_screen_get_hpos( space->machine->primary_screen ) < I824X_START_ACTIVE_SCAN || video_screen_get_hpos( space->machine->primary_screen ) > I824X_END_ACTIVE_SCAN ) {
	194	if ( video_screen_get_hpos( space->machine->primary_screen ) < I824X_START_ACTIVE_SCAN || video_screen_get_hpos( space->machine->primary_screen ) > I824X_END_ACTIVE_SCAN )
	195	{
194	196	data |= 1;
195	197	}
196	198
r4582	r4583
214	216
215	217	case 0xa5:
216	218
217		if ((o2_vdc.s.control & VDC_CONTROL_REG_STROBE_XY)) {
	219	if ((o2_vdc.s.control & VDC_CONTROL_REG_STROBE_XY))
	220	{
218	221	x_beam_pos = video_screen_get_hpos( space->machine->primary_screen );
219		if ( x_beam_pos < I824X_START_ACTIVE_SCAN ) {
	222	if ( x_beam_pos < I824X_START_ACTIVE_SCAN )
	223	{
220	224	x_beam_pos = x_beam_pos - I824X_START_ACTIVE_SCAN + I824X_LINE_CLOCKS;
221		} else {
	225	}
	226	else
	227	{
222	228	x_beam_pos = x_beam_pos - I824X_START_ACTIVE_SCAN;
223	229	}
224	230	}
r4582	r4583
247	253	{
248	254	/* Toggling strobe bit, tuck away values */
249	255	x_beam_pos = video_screen_get_hpos( space->machine->primary_screen );
250		if ( x_beam_pos < I824X_START_ACTIVE_SCAN ) {
	256	if ( x_beam_pos < I824X_START_ACTIVE_SCAN )
	257	{
251	258	x_beam_pos = x_beam_pos - I824X_START_ACTIVE_SCAN + 228;
252		} else {
	259	}
	260	else
	261	{
253	262	x_beam_pos = x_beam_pos - I824X_START_ACTIVE_SCAN;
254	263	}
255	264
r4582	r4583
268	277	o2_vdc.reg[offset] = data;
269	278	}
270	279
271		WRITE8_HANDLER ( odyssey2_lum_w ) {
	280	WRITE8_HANDLER ( odyssey2_lum_w )
	281	{
272	282	lum = data;
273	283	}
274	284
275	285	READ8_HANDLER( odyssey2_t1_r )
276	286	{
277		if ( video_screen_get_vpos( space->machine->primary_screen ) > start_vpos && video_screen_get_vpos( space->machine->primary_screen ) < start_vblank ) {
278		if ( video_screen_get_hpos( space->machine->primary_screen ) >= I824X_START_ACTIVE_SCAN && video_screen_get_hpos( space->machine->primary_screen ) < I824X_END_ACTIVE_SCAN ) {
	287	if ( video_screen_get_vpos( space->machine->primary_screen ) > start_vpos && video_screen_get_vpos( space->machine->primary_screen ) < start_vblank )
	288	{
	289	if ( video_screen_get_hpos( space->machine->primary_screen ) >= I824X_START_ACTIVE_SCAN && video_screen_get_hpos( space->machine->primary_screen ) < I824X_END_ACTIVE_SCAN )
	290	{
279	291	return 1;
280	292	}
281	293	}
282	294	return 0;
283	295	}
284	296
285		static TIMER_CALLBACK( i824x_scanline_callback ) {
	297	static TIMER_CALLBACK( i824x_scanline_callback )
	298	{
286	299	UINT8   collision_map[160];
287	300	int      vpos = video_screen_get_vpos( machine->primary_screen );
288	301
289	302	if ( vpos < start_vpos )
290	303	return;
291	304
292		if ( vpos == start_vpos ) {
	305	if ( vpos == start_vpos )
	306	{
293	307	control_status &= ~0x08;
294	308	}
295	309
296		if ( vpos < start_vblank ) {
	310	if ( vpos < start_vblank )
	311	{
297	312	rectangle rect;
298	313	int   sprite_width[4] = { 8, 8, 8, 8 };
299	314	int i;
r4582	r4583
310	325	memset( collision_map, 0, sizeof( collision_map ) );
311	326
312	327	/* Display grid if enabled */
313		if ( o2_vdc.s.control & 0x08 ) {
	328	if ( o2_vdc.s.control & 0x08 )
	329	{
314	330	UINT16   color = ( o2_vdc.s.color & 7 ) | ( ( o2_vdc.s.color >> 3 ) & 0x08 ) | ( ( lum << 3 ) ^ 0x08 );
315	331	int      x_grid_offset = 8;
316	332	int    y_grid_offset = 24;
r4582	r4583
320	336	int      j, k, y;
321	337
322	338	/* Draw horizontal part of grid */
323		for ( j = 1, y = 0; y < 9; y++, j <<= 1 ) {
324		if ( y_grid_offset + y * height <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y_grid_offset + y * height + 3 ) {
325		for ( i = 0; i < 9; i++ ) {
326		if ( ( o2_vdc.s.hgrid[0][i] & j ) || ( o2_vdc.s.hgrid[1][i] & ( j >> 8 ) ) ) {
327		for ( k = 0; k < width + 2; k++ ) {
	339	for ( j = 1, y = 0; y < 9; y++, j <<= 1 )
	340	{
	341	if ( y_grid_offset + y * height <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y_grid_offset + y * height + 3 )
	342	{
	343	for ( i = 0; i < 9; i++ )
	344	{
	345	if ( ( o2_vdc.s.hgrid[0][i] & j ) || ( o2_vdc.s.hgrid[1][i] & ( j >> 8 ) ) )
	346	{
	347	for ( k = 0; k < width + 2; k++ )
	348	{
328	349	int px = x_grid_offset + i * width + k;
329	350	collision_map[ px ] |= COLLISION_HORIZ_GRID_DOTS;
330	351	*BITMAP_ADDR16( tmp_bitmap, vpos, I824X_START_ACTIVE_SCAN + px ) = color;
r4582	r4583
335	356	}
336	357
337	358	/* Draw vertical part of grid */
338		for( j = 1, y = 0; y < 8; y++, j <<= 1 ) {
339		if ( y_grid_offset + y * height <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y_grid_offset + ( y + 1 ) * height ) {
340		for ( i = 0; i < 10; i++ ) {
341		if ( o2_vdc.s.vgrid[i] & j ) {
342		for ( k = 0; k < w; k++ ) {
	359	for( j = 1, y = 0; y < 8; y++, j <<= 1 )
	360	{
	361	if ( y_grid_offset + y * height <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y_grid_offset + ( y + 1 ) * height )
	362	{
	363	for ( i = 0; i < 10; i++ )
	364	{
	365	if ( o2_vdc.s.vgrid[i] & j )
	366	{
	367	for ( k = 0; k < w; k++ )
	368	{
343	369	int px = x_grid_offset + i * width + k;
344	370
345	371	/* Check if we collide with an already drawn source object */
346		if ( collision_map[ px ] & o2_vdc.s.collision ) {
	372	if ( collision_map[ px ] & o2_vdc.s.collision )
	373	{
347	374	collision_status |= COLLISION_VERTICAL_GRID;
348	375	}
349	376	/* Check if an already drawn object would collide with us */
350		if ( COLLISION_VERTICAL_GRID & o2_vdc.s.collision && collision_map[ px ] ) {
	377	if ( COLLISION_VERTICAL_GRID & o2_vdc.s.collision && collision_map[ px ] )
	378	{
351	379	collision_status |= collision_map[ px ];
352	380	}
353	381	collision_map[ px ] |= COLLISION_VERTICAL_GRID;
r4582	r4583
360	388	}
361	389
362	390	/* Display objects if enabled */
363		if ( o2_vdc.s.control & 0x20 ) {
	391	if ( o2_vdc.s.control & 0x20 )
	392	{
364	393	/* Regular foreground objects */
365		for ( i = 0; i < ARRAY_LENGTH( o2_vdc.s.foreground ); i++ ) {
	394	for ( i = 0; i < ARRAY_LENGTH( o2_vdc.s.foreground ); i++ )
	395	{
366	396	int   y = o2_vdc.s.foreground[i].y;
367	397	int   height = 8 - ( ( ( y >> 1 ) + o2_vdc.s.foreground[i].ptr ) & 7 );
368	398
369		if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + height * 2 ) {
	399	if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + height * 2 )
	400	{
370	401	UINT16   color = 16 + ( ( o2_vdc.s.foreground[i].color & 0x0E ) >> 1 );
371	402	int      offset = ( o2_vdc.s.foreground[i].ptr | ( ( o2_vdc.s.foreground[i].color & 0x01 ) << 8 ) ) + ( y >> 1 ) + ( ( vpos - start_vpos - y ) >> 1 );
372	403	UINT8   chr = ((char*)o2_shape)[ offset & 0x1FF ];
373	404	int      x = o2_vdc.s.foreground[i].x;
374	405	UINT8   m;
375	406
376		for ( m = 0x80; m > 0; m >>= 1, x++ ) {
377		if ( chr & m ) {
378		if ( x >= 0 && x < 160 ) {
	407	for ( m = 0x80; m > 0; m >>= 1, x++ )
	408	{
	409	if ( chr & m )
	410	{
	411	if ( x >= 0 && x < 160 )
	412	{
379	413	/* Check if we collide with an already drawn source object */
380		if ( collision_map[ x ] & o2_vdc.s.collision ) {
	414	if ( collision_map[ x ] & o2_vdc.s.collision )
	415	{
381	416	collision_status |= COLLISION_CHARACTERS;
382	417	}
383	418	/* Check if an already drawn object would collide with us */
384		if ( COLLISION_CHARACTERS & o2_vdc.s.collision && collision_map[ x ] ) {
	419	if ( COLLISION_CHARACTERS & o2_vdc.s.collision && collision_map[ x ] )
	420	{
385	421	collision_status |= collision_map[ x ];
386	422	}
387	423	collision_map[ x ] |= COLLISION_CHARACTERS;
r4582	r4583
393	429	}
394	430
395	431	/* Quad objects */
396		for ( i = 0; i < ARRAY_LENGTH( o2_vdc.s.quad ); i++ ) {
	432	for ( i = 0; i < ARRAY_LENGTH( o2_vdc.s.quad ); i++ )
	433	{
397	434	int y = o2_vdc.s.quad[i].single[0].y;
398	435	int height = 8;
399	436
400		if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + height * 2 ) {
	437	if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + height * 2 )
	438	{
401	439	int   x = o2_vdc.s.quad[i].single[0].x;
402	440	int j;
403	441
404		for ( j = 0; j < ARRAY_LENGTH( o2_vdc.s.quad[0].single ); j++, x += 8 ) {
	442	for ( j = 0; j < ARRAY_LENGTH( o2_vdc.s.quad[0].single ); j++, x += 8 )
	443	{
405	444	int      char_height = 8 - ( ( ( y >> 1 ) + o2_vdc.s.quad[i].single[j].ptr ) & 7 );
406		if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + char_height * 2 ) {
	445	if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + char_height * 2 )
	446	{
407	447	UINT16 color = 16 + ( ( o2_vdc.s.quad[i].single[j].color & 0x0E ) >> 1 );
408	448	int   offset = ( o2_vdc.s.quad[i].single[j].ptr | ( ( o2_vdc.s.quad[i].single[j].color & 0x01 ) << 8 ) ) + ( y >> 1 ) + ( ( vpos - start_vpos - y ) >> 1 );
409	449	UINT8   chr = ((char*)o2_shape)[ offset & 0x1FF ];
410	450	UINT8   m;
411		for ( m = 0x80; m > 0; m >>= 1, x++ ) {
412		if ( chr & m ) {
413		if ( x >= 0 && x < 160 ) {
	451	for ( m = 0x80; m > 0; m >>= 1, x++ )
	452	{
	453	if ( chr & m )
	454	{
	455	if ( x >= 0 && x < 160 )
	456	{
414	457	/* Check if we collide with an already drawn source object */
415		if ( collision_map[ x ] & o2_vdc.s.collision ) {
	458	if ( collision_map[ x ] & o2_vdc.s.collision )
	459	{
416	460	collision_status |= COLLISION_CHARACTERS;
417	461	}
418	462	/* Check if an already drawn object would collide with us */
419		if ( COLLISION_CHARACTERS & o2_vdc.s.collision && collision_map[ x ] ) {
	463	if ( COLLISION_CHARACTERS & o2_vdc.s.collision && collision_map[ x ] )
	464	{
420	465	collision_status |= collision_map[ x ];
421	466	}
422	467	collision_map[ x ] |= COLLISION_CHARACTERS;
r4582	r4583
424	469	}
425	470	}
426	471	}
427		} else {
	472	}
	473	else
	474	{
428	475	x += 8;
429	476	}
430	477	}
r4582	r4583
432	479	}
433	480
434	481	/* Sprites */
435		for ( i = 0; i < ARRAY_LENGTH( o2_vdc.s.sprites ); i++ ) {
	482	for ( i = 0; i < ARRAY_LENGTH( o2_vdc.s.sprites ); i++ )
	483	{
436	484	int y = o2_vdc.s.sprites[i].y;
437	485	int height = 8;
438		if ( o2_vdc.s.sprites[i].color & 4 ) {
	486	if ( o2_vdc.s.sprites[i].color & 4 )
	487	{
439	488	/* Zoomed sprite */
440	489	sprite_width[i] = 16;
441		if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + height * 4 ) {
	490	if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + height * 4 )
	491	{
442	492	UINT16 color = 16 + ( ( o2_vdc.s.sprites[i].color >> 3 ) & 0x07 );
443	493	UINT8   chr = o2_vdc.s.shape[i][ ( ( vpos - start_vpos - y ) >> 2 ) ];
444	494	int      x = o2_vdc.s.sprites[i].x;
445	495	UINT8   m;
446	496
447		for ( m = 0x01; m > 0; m <<= 1, x += 2 ) {
448		if ( chr & m ) {
449		if ( x >= 0 && x < 160 ) {
	497	for ( m = 0x01; m > 0; m <<= 1, x += 2 )
	498	{
	499	if ( chr & m )
	500	{
	501	if ( x >= 0 && x < 160 )
	502	{
450	503	/* Check if we collide with an already drawn source object */
451		if ( collision_map[ x ] & o2_vdc.s.collision ) {
	504	if ( collision_map[ x ] & o2_vdc.s.collision )
	505	{
452	506	collision_status |= ( 1 << i );
453	507	}
454	508	/* Check if an already drawn object would collide with us */
455		if ( ( 1 << i ) & o2_vdc.s.collision && collision_map[ x ] ) {
	509	if ( ( 1 << i ) & o2_vdc.s.collision && collision_map[ x ] )
	510	{
456	511	collision_status |= collision_map[ x ];
457	512	}
458	513	collision_map[ x ] |= ( 1 << i );
459	514	*BITMAP_ADDR16( tmp_bitmap, vpos, I824X_START_ACTIVE_SCAN + x ) = color;
460	515	}
461		if ( x >= -1 && x < 159 ) {
	516	if ( x >= -1 && x < 159 )
	517	{
462	518	/* Check if we collide with an already drawn source object */
463		if ( collision_map[ x ] & o2_vdc.s.collision ) {
	519	if ( collision_map[ x ] & o2_vdc.s.collision )
	520	{
464	521	collision_status |= ( 1 << i );
465	522	}
466	523	/* Check if an already drawn object would collide with us */
467		if ( ( 1 << i ) & o2_vdc.s.collision && collision_map[ x ] ) {
	524	if ( ( 1 << i ) & o2_vdc.s.collision && collision_map[ x ] )
	525	{
468	526	collision_status |= collision_map[ x ];
469	527	}
470	528	collision_map[ x ] |= ( 1 << i );
r4582	r4583
473	531	}
474	532	}
475	533	}
476		} else {
	534	}
	535	else
	536	{
477	537	/* Regular sprite */
478		if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + height * 2 ) {
	538	if ( y <= ( vpos - start_vpos ) && ( vpos - start_vpos ) < y + height * 2 )
	539	{
479	540	UINT16 color = 16 + ( ( o2_vdc.s.sprites[i].color >> 3 ) & 0x07 );
480	541	UINT8   chr = o2_vdc.s.shape[i][ ( ( vpos - start_vpos - y ) >> 1 ) ];
481	542	int      x = o2_vdc.s.sprites[i].x;
482	543	UINT8   m;
483	544
484		for ( m = 0x01; m > 0; m <<= 1, x++ ) {
485		if ( chr & m ) {
486		if ( x >= 0 && x < 160 ) {
	545	for ( m = 0x01; m > 0; m <<= 1, x++ )
	546	{
	547	if ( chr & m )
	548	{
	549	if ( x >= 0 && x < 160 )
	550	{
487	551	/* Check if we collide with an already drawn source object */
488		if ( collision_map[ x ] & o2_vdc.s.collision ) {
	552	if ( collision_map[ x ] & o2_vdc.s.collision )
	553	{
489	554	collision_status |= ( 1 << i );
490	555	}
491	556	/* Check if an already drawn object would collide with us */
492		if ( ( 1 << i ) & o2_vdc.s.collision && collision_map[ x ] ) {
	557	if ( ( 1 << i ) & o2_vdc.s.collision && collision_map[ x ] )
	558	{
493	559	collision_status |= collision_map[ x ];
494	560	}
495	561	collision_map[ x ] |= ( 1 << i );
r4582	r4583
504	570	}
505	571
506	572	/* Check for start of VBlank */
507		if ( vpos == start_vblank ) {
	573	if ( vpos == start_vblank )
	574	{
508	575	control_status |= 0x08;
509		if ( ! iff ) {
510		cpu_set_input_line(machine->cpu[0], 0, ASSERT_LINE);
	576	if ( ! iff )
	577	{
	578	cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE);
511	579	iff = 1;
512	580	}
513	581	}
514	582	}
515	583
516		static TIMER_CALLBACK( i824x_hblank_callback ) {
	584	static TIMER_CALLBACK( i824x_hblank_callback )
	585	{
517	586	int vpos = video_screen_get_vpos( machine->primary_screen );
518	587
519	588	if ( vpos < start_vpos - 1 )
520	589	return;
521	590
522		if ( vpos < start_vblank - 1 ) {
	591	if ( vpos < start_vblank - 1 )
	592	{
523	593	control_status |= 0x01;
524	594	}
525	595	}
r4582	r4583
614	684	}
615	685	/* Noise poly is : L=16 W=2 10000000000100001 */
616	686	lfsr = ( lfsr >> 1 ) | ( ( ( lfsr & 0x01 ) ^ ( ( lfsr & 0x800 ) >> 11 ) ) << 15 );
617		if ( ! lfsr ) {
	687	if ( ! lfsr )
	688	{
618	689	lfsr = 0xFFFF;
619	690	}
620	691	/* Check if noise should be applied */
621		if ( o2_vdc.s.sound & 0x10 ) {
	692	if ( o2_vdc.s.sound & 0x10 )
	693	{
622	694	*buffer |= ( lfsr & 0x01 );
623	695	}
624	696	o2_vdc.s.shift3 = signal & 0xFF;
r4582	r4583
629	701	/* Throw an interrupt if enabled */
630	702	if( o2_vdc.s.control & 0x4 )
631	703	{
632		cpu_set_input_line(device->machine->cpu[0], 1, HOLD_LINE); /* Is this right? */
	704	cputag_set_input_line(device->machine, "maincpu", 1, HOLD_LINE); /* Is this right? */
633	705	}
634	706
635	707	/* Adjust volume */
r4582	r4583
662	734	UINT8   ram[1024];
663	735	} ef9341;
664	736
665		INLINE UINT16 ef9341_get_c_addr( void ) {
666		if ( ( ef9341.Y & 0x0C ) == 0x0C ) {
	737	INLINE UINT16 ef9341_get_c_addr( void )
	738	{
	739	if ( ( ef9341.Y & 0x0C ) == 0x0C )
	740	{
667	741	return 0x318 | ( ( ef9341.X & 0x38 ) << 2 ) | ( ef9341.X & 0x07 );
668	742	}
669		if ( ef9341.X & 0x20 ) {
	743	if ( ef9341.X & 0x20 )
	744	{
670	745	return 0x300 | ( ( ef9341.Y & 0x07 ) << 5 ) | ( ef9341.Y & 0x18 ) | ( ef9341.X & 0x07 );
671	746	}
672	747	return ( ef9341.Y << 5 ) | ef9341.X;
673	748	}
674	749
675		INLINE void ef9341_inc_c( void ) {
	750	INLINE void ef9341_inc_c( void )
	751	{
676	752	ef9341.X++;
677		if ( ef9341.X >= 40 ) {
	753	if ( ef9341.X >= 40 )
	754	{
678	755	ef9341.Y = ( ef9341.Y + 1 ) % 24;
679	756	}
680	757	}
681	758
682		void ef9341_w( int command, int b, UINT8 data ) {
	759	void ef9341_w( int command, int b, UINT8 data )
	760	{
683	761	logerror("ef9341 %s write, t%s, data %02X\n", command ? "command" : "data", b ? "B" : "A", data );
684	762
685		if ( command ) {
686		if ( b ) {
	763	if ( command )
	764	{
	765	if ( b )
	766	{
687	767	ef9341.TB = data;
688	768	ef9341.busy = 0x80;
689		switch( ef9341.TB & 0xE0 ) {
	769	switch( ef9341.TB & 0xE0 )
	770	{
690	771	case 0x00:   /* Begin row */
691	772	ef9341.X = 0;
692	773	ef9341.Y = ef9341.TA & 0x1F;
r4582	r4583
711	792	break;
712	793	}
713	794	ef9341.busy = 0;
714		} else {
	795	}
	796	else
	797	{
715	798	ef9341.TA = data;
716	799	}
717		} else {
718		if ( b ) {
	800	}
	801	else
	802	{
	803	if ( b )
	804	{
719	805	ef9341.TB = data;
720	806	ef9341.busy = 0x80;
721		switch ( ef9341.M & 0xE0 ) {
	807	switch ( ef9341.M & 0xE0 )
	808	{
722	809	case 0x00:   /* Write */
723	810	ef9341.ram[ ef9341_get_c_addr() ] = ef9341.TB;
724	811	ef9341_inc_c();
r4582	r4583
735	822	break;
736	823	}
737	824	ef9341.busy = 0;
738		} else {
	825	}
	826	else
	827	{
739	828	ef9341.TA = data;
740	829	}
741	830	}
742	831	}
743	832
744		UINT8 ef9341_r( int command, int b ) {
	833	UINT8 ef9341_r( int command, int b )
	834	{
745	835	UINT8   data = 0xFF;
746	836
747	837	logerror("ef9341 %s read, t%s\n", command ? "command" : "data", b ? "B" : "A" );
748		if ( command ) {
749		if ( b ) {
	838	if ( command )
	839	{
	840	if ( b )
	841	{
750	842	data = 0xFF;
751		} else {
	843	}
	844	else
	845	{
752	846	data = ef9341.busy;
753	847	}
754		} else {
755		if ( b ) {
	848	}
	849	else
	850	{
	851	if ( b )
	852	{
756	853	data = ef9341.TB;
757	854	ef9341.busy = 0x80;
758		} else {
	855	}
	856	else
	857	{
759	858	data = ef9341.TA;
760	859	}
761	860	}

src/mess/video/primo.c

r4582	r4583
23	23	UINT16 *scanline = BITMAP_ADDR16(bitmap, primo_scanline, 0);
24	24
25	25	/* address of current line in Primo video memory */
26		const UINT8* primo_video_ram_line = memory_get_read_ptr(cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM), primo_video_memory_base + 32*primo_scanline);
	26	const UINT8* primo_video_ram_line = memory_get_read_ptr(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), primo_video_memory_base + 32 * primo_scanline);
27	27
28	28	for (x=0; x<256; x+=8)
29	29	{

src/mess/video/pecom.c

r4582	r4583
71	71	{
72	72	driver_state->dma = 0;
73	73
74		cpu_set_input_line(device->machine->cpu[0], CDP1802_INPUT_LINE_DMAOUT, HOLD_LINE);
	74	cputag_set_input_line(device->machine, "maincpu", CDP1802_INPUT_LINE_DMAOUT, HOLD_LINE);
75	75	}
76	76	else
77	77	{

src/mess/machine/pdp1.c

r4582	r4583
194	194	MACHINE_START( pdp1 )
195	195	{
196	196	UINT8 *dst;
197		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	197	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
198	198
199	199	static const unsigned char fontdata6x8[pdp1_fontdata_size] =
200	200	{   /* ASCII characters */
r4582	r4583
526	526	tape_reader.rcl = 0;
527	527	if (tape_reader.rcp)
528	528	{
529		cpu_set_reg(machine->cpu[0], PDP1_IO, tape_reader.rb);   /* transfer reader buffer to IO */
	529	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), PDP1_IO, tape_reader.rb);   /* transfer reader buffer to IO */
530	530	pdp1_pulse_iot_done();
531	531	}
532	532	else
r4582	r4583
921	921	{
922	922	io_status &= ~io_st_tyi;
923	923	if (USE_SBS)
924		cpu_set_input_line_and_vector(device->machine->cpu[0], 0, CLEAR_LINE, 0);   /* interrupt it, baby */
	924	cputag_set_input_line_and_vector(device->machine, "maincpu", 0, CLEAR_LINE, 0);   /* interrupt it, baby */
925	925	}
926	926	}
927	927
r4582	r4583
991	991	{
992	992	io_status |= io_st_pen;
993	993
994		cpu_set_reg(device->machine->cpu[0], PDP1_PF3, 1);
	994	cpu_set_reg(cputag_get_cpu(device->machine, "maincpu"), PDP1_PF3, 1);
995	995	}
996	996
997	997	if (nac)
r4582	r4583
1131	1131	{
1132	1132	if ((parallel_drum.wfb >= 1) && (parallel_drum.wfb <= 22))
1133	1133	{
1134		drum_write(parallel_drum.wfb-1, dc, (signed)memory_read_dword_32be(cpu_get_address_space(device->machine->cpu[0], ADDRESS_SPACE_PROGRAM),parallel_drum.wcl<<2));
	1134	drum_write(parallel_drum.wfb-1, dc, (signed)memory_read_dword_32be(cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM),parallel_drum.wcl<<2));
1135	1135	}
1136	1136
1137	1137	if ((parallel_drum.rfb >= 1) && (parallel_drum.rfb <= 22))
1138	1138	{
1139		memory_write_dword_32be(cpu_get_address_space(device->machine->cpu[0], ADDRESS_SPACE_PROGRAM),parallel_drum.wcl<<2, drum_read(parallel_drum.rfb-1, dc));
	1139	memory_write_dword_32be(cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM),parallel_drum.wcl<<2, drum_read(parallel_drum.rfb-1, dc));
1140	1140	}
1141	1141
1142	1142	parallel_drum.wc = (parallel_drum.wc+1) & 07777;
r4582	r4583
1145	1145	if (parallel_drum.wc)
1146	1146	delay = attotime_add(delay, PARALLEL_DRUM_WORD_TIME);
1147	1147	} while (parallel_drum.wc);
1148		cpu_adjust_icount(device->machine->cpu[0],-cpu_attotime_to_clocks(device->machine->cpu[0], delay));
	1148	cpu_adjust_icount(cputag_get_cpu(device->machine, "maincpu"),-cputag_attotime_to_clocks(device->machine, "maincpu", delay));
1149	1149	/* if no error, skip */
1150		cpu_set_reg(device->machine->cpu[0], PDP1_PC, cpu_get_reg(device->machine->cpu[0], PDP1_PC)+1);
	1150	cpu_set_reg(cputag_get_cpu(device->machine, "maincpu"), PDP1_PC, cpu_get_reg(cputag_get_cpu(device->machine, "maincpu"), PDP1_PC)+1);
1151	1151	}
1152	1152
1153	1153	void iot_dra(const device_config *device, int op2, int nac, int mb, int *io, int ac)
r4582	r4583
1274	1274	typewriter.tb = (i << 4) + j;
1275	1275	io_status |= io_st_tyi;
1276	1276	#if USE_SBS
1277		cpu_set_input_line_and_vector(machine->cpu[0], 0, ASSERT_LINE, 0);   /* interrupt it, baby */
	1277	cputag_set_input_line_and_vector(machine, "maincpu", 0, ASSERT_LINE, 0);   /* interrupt it, baby */
1278	1278	#endif
1279		cpu_set_reg(machine->cpu[0], PDP1_PF1, 1);
	1279	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), PDP1_PF1, 1);
1280	1280	pdp1_typewriter_drawchar(machine, typewriter.tb);   /* we want to echo input */
1281	1281	break;
1282	1282	}
r4582	r4583
1427	1427	pdp1_pulse_start_clear();   /* pulse Start Clear line */
1428	1428	cpu_set_reg(device, PDP1_PC, (  cpu_get_reg(device, PDP1_TA) & 0170000)
1429	1429	|  (cpu_get_reg(device, PDP1_PC) & 0007777));   /* transfer ETA to EPC */
1430		/*cpu_set_reg(machine->cpu[0], PDP1_MA, cpu_get_reg(machine->cpu[0], PDP1_PC));*/
	1430	/*cpu_set_reg(cputag_get_cpu(machine, "maincpu"), PDP1_MA, cpu_get_reg(cputag_get_cpu(machine, "maincpu"), PDP1_PC));*/
1431	1431	cpu_set_reg(device, PDP1_EXD, cpu_get_reg(device, PDP1_EXTEND_SW));
1432	1432	cpu_set_reg(device, PDP1_OV, 0);      /* right??? */
1433	1433	cpu_set_reg(device, PDP1_RUN, 0);

src/mess/machine/pokemini.c

r4582	r4583
193	193	{
194	194	//logerror("Triggering IRQ with vector %02x\n", vector );
195	195	/* Trigger interrupt and set vector */
196		cpu_set_input_line_and_vector( machine->cpu[0], 0, ASSERT_LINE, vector );
	196	cputag_set_input_line_and_vector( machine, "maincpu", 0, ASSERT_LINE, vector );
197	197	}
198	198	else
199	199	{
200		cpu_set_input_line( machine->cpu[0], 0, CLEAR_LINE );
	200	cputag_set_input_line( machine, "maincpu", 0, CLEAR_LINE );
201	201	}
202	202	}
203	203
r4582	r4583
491	491	int index = data & 0x07;
492	492	int cycles = ( pm_reg[0x19] & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
493	493
494		timer_adjust_periodic(timers.timer1, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	494	timer_adjust_periodic(timers.timer1, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
495	495	}
496	496
497	497	/* Check for prescaler change for the high counter */
r4582	r4583
500	500	int index = ( data >> 4 ) & 0x07;
501	501	int cycles = ( pm_reg[0x19] & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
502	502
503		timer_adjust_periodic(timers.timer1_hi, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	503	timer_adjust_periodic(timers.timer1_hi, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
504	504	}
505	505
506	506	/* Check if timer1 low should be enabled */
r4582	r4583
541	541	int index = pm_reg[0x18] & 0x07;
542	542	int cycles = ( data & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
543	543
544		timer_adjust_periodic(timers.timer1, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	544	timer_adjust_periodic(timers.timer1, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
545	545	}
546	546
547	547	/* Check for prescaler change for the low counter */
r4582	r4583
550	550	int index = ( pm_reg[0x18] >> 4 ) & 0x07;
551	551	int cycles = ( data & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
552	552
553		timer_adjust_periodic(timers.timer1_hi, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	553	timer_adjust_periodic(timers.timer1_hi, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
554	554	}
555	555
556	556	{
r4582	r4583
620	620	int index = data & 0x07;
621	621	int cycles = ( pm_reg[0x1B] & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
622	622
623		timer_adjust_periodic(timers.timer2, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	623	timer_adjust_periodic(timers.timer2, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
624	624	}
625	625
626	626	/* Check for prescaler change for the high counter */
r4582	r4583
629	629	int index = ( data >> 4 ) & 0x07;
630	630	int cycles = ( pm_reg[0x1B] & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
631	631
632		timer_adjust_periodic(timers.timer2_hi, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	632	timer_adjust_periodic(timers.timer2_hi, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
633	633	}
634	634
635	635	/* Check if timer2 low should be enabled */
r4582	r4583
666	666	int index = pm_reg[0x1A] & 0x07;
667	667	int cycles = ( data & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
668	668
669		timer_adjust_periodic(timers.timer2, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	669	timer_adjust_periodic(timers.timer2, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
670	670
671	671	if ( ( pm_reg[0x1A] & 0x08 ) && ( pm_reg[0x38] & 0x04 ) &&
672	672	( ( ( pm_reg[0x19] & 0x10 ) && ( data & 0x01 ) ) ||
r4582	r4583
686	686	int index = ( pm_reg[0x1A] >> 4 ) & 0x07;
687	687	int cycles = ( data & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
688	688
689		timer_adjust_periodic(timers.timer2_hi, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	689	timer_adjust_periodic(timers.timer2_hi, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
690	690
691	691	if ( ( pm_reg[0x1A] & 0x80 ) && ( pm_reg[0x39] & 0x04 ) && ! ( pm_reg[0x38] & 0x80 ) &&
692	692	( ( ( pm_reg[0x19] & 0x10 ) && ( data & 0x02 ) ) ||
r4582	r4583
720	720	int index = data & 0x07;
721	721	int cycles = ( pm_reg[0x1D] & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
722	722
723		timer_adjust_periodic(timers.timer3, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	723	timer_adjust_periodic(timers.timer3, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
724	724	}
725	725
726	726	/* Check for prescaler change for the high counter */
r4582	r4583
729	729	int index = ( data >> 4 ) & 0x07;
730	730	int cycles = ( pm_reg[0x1D] & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
731	731
732		timer_adjust_periodic(timers.timer3_hi, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	732	timer_adjust_periodic(timers.timer3_hi, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
733	733	}
734	734
735	735	/* Check if timer2 low should be enabled */
r4582	r4583
766	766	int index = pm_reg[0x1C] & 0x07;
767	767	int cycles = ( data & 0x01 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
768	768
769		timer_adjust_periodic(timers.timer3, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	769	timer_adjust_periodic(timers.timer3, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
770	770
771	771	if ( ( pm_reg[0x1C] & 0x08 ) && ( pm_reg[0x48] & 0x04 ) &&
772	772	( ( ( pm_reg[0x19] & 0x10 ) && ( data & 0x01 ) ) ||
r4582	r4583
786	786	int index = ( pm_reg[0x1C] >> 4 ) & 0x07;
787	787	int cycles = ( data & 0x02 ) ? timer_to_cycles_slow[index] : timer_to_cycles_fast[index];
788	788
789		timer_adjust_periodic(timers.timer3_hi, attotime_zero, 0, cpu_clocks_to_attotime(space->machine->cpu[0], cycles));
	789	timer_adjust_periodic(timers.timer3_hi, attotime_zero, 0, cputag_clocks_to_attotime(space->machine, "maincpu", cycles));
790	790
791	791	if ( ( pm_reg[0x1C] & 0x80 ) && ( pm_reg[0x49] & 0x04 ) && ! ( pm_reg[0x48] & 0x80 ) &&
792	792	( ( ( pm_reg[0x19] & 0x10 ) && ( data & 0x02 ) ) ||
r4582	r4583
1437	1437
1438	1438	static TIMER_CALLBACK( pokemini_prc_counter_callback )
1439	1439	{
1440		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1440	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1441	1441	prc.count++;
1442	1442
1443	1443	/* Check for overflow */
r4582	r4583
1601	1601	/* Set up the PRC */
1602	1602	prc.max_frame_count = 2;
1603	1603	prc.count_timer = timer_alloc(machine,  pokemini_prc_counter_callback, NULL );
1604		timer_adjust_periodic( prc.count_timer, attotime_zero, 0, cpu_clocks_to_attotime(machine->cpu[0], 55640 / 65) );
	1604	timer_adjust_periodic( prc.count_timer, attotime_zero, 0, cputag_clocks_to_attotime(machine, "maincpu", 55640 / 65) );
1605	1605	}
1606	1606

src/mess/machine/pc1350.c

r4582	r4583
118	118
119	119	MACHINE_START( pc1350 )
120	120	{
121		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	121	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
122	122
123	123	timer_set(machine, ATTOTIME_IN_SEC(1), NULL, 0, pc1350_power_up);
124	124

src/mess/machine/radio86.c

r4582	r4583
137	137	READ8_DEVICE_HANDLER(radio86_dma_read_byte)
138	138	{
139	139	UINT8 result;
140		result = memory_read_byte(cpu_get_address_space(device->machine->cpu[0], ADDRESS_SPACE_PROGRAM),offset);
	140	result = memory_read_byte(cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM), offset);
141	141	return result;
142	142	}
143	143
r4582	r4583
172	172
173	173	READ8_HANDLER (radio_io_r )
174	174	{
175		return memory_read_byte(cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM),(offset << 8) + offset);
	175	return memory_read_byte(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), (offset << 8) + offset);
176	176	}
177	177
178	178	WRITE8_HANDLER(radio_io_w )
179	179	{
180		memory_write_byte(cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM),(offset << 8) + offset,data);
	180	memory_write_byte(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), (offset << 8) + offset,data);
181	181	}
182	182
183	183	MACHINE_RESET( radio86 )

src/mess/machine/pmd85.c

r4582	r4583
35	35
36	36	static void pmd851_update_memory(running_machine *machine)
37	37	{
38		const address_space* space = cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM);
	38	const address_space* space = cputag_get_address_space(machine, "maincpu",ADDRESS_SPACE_PROGRAM);
39	39
40	40	if (pmd85_startup_mem_map)
41	41	{
r4582	r4583
78	78
79	79	static void pmd852a_update_memory(running_machine *machine)
80	80	{
81		const address_space* space = cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM);
	81	const address_space* space = cputag_get_address_space(machine, "maincpu",ADDRESS_SPACE_PROGRAM);
82	82
83	83	if (pmd85_startup_mem_map)
84	84	{
r4582	r4583
150	150
151	151	static void alfa_update_memory(running_machine *machine)
152	152	{
153		const address_space* space = cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM);
	153	const address_space* space = cputag_get_address_space(machine, "maincpu",ADDRESS_SPACE_PROGRAM);
154	154
155	155	if (pmd85_startup_mem_map)
156	156	{
r4582	r4583
182	182
183	183	static void mato_update_memory(running_machine *machine)
184	184	{
185		const address_space* space = cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM);
	185	const address_space* space = cputag_get_address_space(machine, "maincpu",ADDRESS_SPACE_PROGRAM);
186	186
187	187	if (pmd85_startup_mem_map)
188	188	{
r4582	r4583
206	206
207	207	static void c2717_update_memory(running_machine *machine)
208	208	{
209		const address_space* space = cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM);
	209	const address_space* space = cputag_get_address_space(machine, "maincpu",ADDRESS_SPACE_PROGRAM);
210	210
211	211	UINT8 *mem = memory_region(machine, "maincpu");
212	212	if (pmd85_startup_mem_map)
r4582	r4583
899	899	pmd85_common_driver_init(machine);
900	900	}
901	901
902		static TIMER_CALLBACK( setup_machine_state ) {
	902	static TIMER_CALLBACK( setup_machine_state )
	903	{
903	904	device_config *pit8253 = (device_config*)devtag_get_device(machine, "pit8253");
904	905
905	906	pit8253_gate_w(pit8253, 0, 1);
906	907	pit8253_gate_w(pit8253, 1, 1);
907	908	pit8253_gate_w(pit8253, 2, 1);
908		if (pmd85_model!=MATO) {
	909	if (pmd85_model!=MATO)
	910	{
909	911	msm8251_connect(devtag_get_device(machine, "uart"), &pmd85_cassette_serial_connection);
910	912	}
911	913	}
r4582	r4583
934	936
935	937	timer_set(machine,  attotime_zero, NULL, 0, setup_machine_state );
936	938
937		memory_set_direct_update_handler(cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM), pmd85_opbaseoverride);
	939	memory_set_direct_update_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), pmd85_opbaseoverride);
938	940	}

src/mess/machine/oric.c

r4582	r4583
82	82	/* any irq set? */
83	83	if ((oric_irqs & 0x0f)!=0)
84	84	{
85		cpu_set_input_line(machine->cpu[0],0, HOLD_LINE);
	85	cputag_set_input_line(machine, "maincpu", 0, HOLD_LINE);
86	86	}
87	87	else
88	88	{
89		cpu_set_input_line(machine->cpu[0],0, CLEAR_LINE);
	89	cputag_set_input_line(machine, "maincpu", 0, CLEAR_LINE);
90	90	}
91	91	}
92	92
r4582	r4583
162	162	/* this port is also used to read printer data */
163	163	static READ8_DEVICE_HANDLER ( oric_via_in_a_func )
164	164	{
165		const address_space *space = cpu_get_address_space( device->machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	165	const address_space *space = cputag_get_address_space( device->machine, "maincpu", ADDRESS_SPACE_PROGRAM );
166	166
167	167	/*logerror("port a read\r\n"); */
168	168
r4582	r4583
464	464	static void oric_install_apple2_interface(running_machine *machine)
465	465	{
466	466	const device_config *fdc = devtag_get_device(machine, "fdc");
467		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	467	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
468	468
469	469	memory_install_read8_handler(space, 0x0300, 0x030f, 0, 0, oric_IO_r);
470	470	memory_install_read8_device_handler(space, fdc, 0x0310, 0x031f, 0, 0, applefdc_r);
r4582	r4583
479	479	static void oric_enable_memory(running_machine *machine, int low, int high, int rd, int wr)
480	480	{
481	481	int i;
482		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	482	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
483	483	for (i = low; i <= high; i++)
484	484	{
485	485	switch(i) {
r4582	r4583
558	558	static void oric_install_apple2_v2_interface(running_machine *machine)
559	559	{
560	560	const device_config *fdc = devtag_get_device(machine, "fdc");
561		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	561	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
562	562
563	563	memory_install_read8_handler(space, 0x0300, 0x030f, 0, 0, oric_IO_r);
564	564	memory_install_read8_device_handler(space, fdc, 0x0310, 0x031f, 0, 0, applefdc_r);
r4582	r4583
748	748	wd17xx_reset(fdc);
749	749	break;
750	750	case 0x0a:
751		logerror("jasmin overlay ram w: %02x PC: %04x\n",data,cpu_get_pc(space->machine->cpu[0]));
	751	logerror("jasmin overlay ram w: %02x PC: %04x\n", data, cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")));
752	752	port_3fa_w = data;
753	753	oric_jasmin_set_mem_0x0c000(space->machine);
754	754	break;
755	755	case 0x0b:
756		logerror("jasmin romdis w: %02x PC: %04x\n",data,cpu_get_pc(space->machine->cpu[0]));
	756	logerror("jasmin romdis w: %02x PC: %04x\n", data, cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")));
757	757	port_3fb_w = data;
758	758	oric_jasmin_set_mem_0x0c000(space->machine);
759	759	break;
r4582	r4583
774	774
775	775	static void oric_install_jasmin_interface(running_machine *machine)
776	776	{
777		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	777	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
778	778	/* romdis */
779	779	port_3fb_w = 1;
780	780	oric_jasmin_set_mem_0x0c000(machine);
r4582	r4583
1026	1026
1027	1027	static void oric_install_microdisc_interface(running_machine *machine)
1028	1028	{
1029		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	1029	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
1030	1030
1031	1031	memory_install_read8_handler(space, 0x0300, 0x030f, 0, 0, oric_IO_r);
1032	1032	memory_install_read8_handler(space, 0x0310, 0x031f, 0, 0, oric_microdisc_r);
r4582	r4583
1117	1117	MACHINE_RESET( oric )
1118	1118	{
1119	1119	int disc_interface_id = input_port_read(machine, "FLOPPY") & 0x07;
1120		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	1120	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
1121	1121
1122	1122	switch (disc_interface_id)
1123	1123	{
r4582	r4583
1208	1208	{
1209	1209	if ((offset & 0x0f)!=0x0d)
1210	1210	{
1211		logerror("via 0 r: %04x %04x\n",offset, (unsigned) cpu_get_reg(space->machine->cpu[0], REG_GENPC));
	1211	logerror("via 0 r: %04x %04x\n",offset, (unsigned) cpu_get_reg(cputag_get_cpu(space->machine, "maincpu"), REG_GENPC));
1212	1212	}
1213	1213	}
1214	1214	/* it is repeated */
r4582	r4583
1227	1227
1228	1228	case ORIC_FLOPPY_INTERFACE_MICRODISC:
1229	1229	{
1230		if ((offset>=0x010) && (offset<=0x01f))
	1230	if ((offset >= 0x010) && (offset <= 0x01f))
1231	1231	{
1232	1232	oric_microdisc_w(offset, data);
1233	1233	return;
r4582	r4583
1237	1237
1238	1238	case ORIC_FLOPPY_INTERFACE_JASMIN:
1239	1239	{
1240		if ((offset>=0x0f4) && (offset<=0x0ff))
	1240	if ((offset >= 0x0f4) && (offset <= 0x0ff))
1241	1241	{
1242		oric_jasmin_w(offset,data);
	1242	oric_jasmin_w(offset, data);
1243	1243	return;
1244	1244	}
1245	1245
r4582	r4583
1249	1249	#endif
1250	1250	if (enable_logging)
1251	1251	{
1252		logerror("via 0 w: %04x %02x %04x\n",offset,data,(unsigned) cpu_get_reg(space->machine->cpu[0], REG_GENPC));
	1252	logerror("via 0 w: %04x %02x %04x\n", offset, data,(unsigned) cpu_get_reg(cputag_get_cpu(space->machine, "maincpu"), REG_GENPC));
1253	1253	}
1254	1254
1255		via_w(via_0, offset & 0x0f,data);
	1255	via_w(via_0, offset & 0x0f, data);
1256	1256	}
1257	1257
1258	1258
r4582	r4583
1331	1331	{
1332	1332	read8_space_func rh;
1333	1333	write8_space_func wh;
1334		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	1334	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
1335	1335
1336	1336	struct telestrat_mem_block *mem_block = &telestrat_blocks[telestrat_bank_selection];
1337	1337

src/mess/machine/orion.c

r4582	r4583
97	97	ppi8255_w((device_config*)devtag_get_device(space->machine, "ppi8255_1"), offset & 3, data);
98	98	}
99	99
100		static void orion_set_video_mode(running_machine *machine, int width) {
	100	static void orion_set_video_mode(running_machine *machine, int width)
	101	{
101	102	rectangle visarea;
102	103
103	104	visarea.min_x = 0;
r4582	r4583
109	110
110	111	WRITE8_HANDLER ( orion128_video_mode_w )
111	112	{
112		if ((data & 0x80)!=(orion128_video_mode & 0x80)) {
113		if ((data & 0x80)==0x80) {
114		if (orion_video_mode_mask == 31) {
	113	if ((data & 0x80)!=(orion128_video_mode & 0x80))
	114	{
	115	if ((data & 0x80)==0x80)
	116	{
	117	if (orion_video_mode_mask == 31)
	118	{
115	119	orion128_video_width = SCREEN_WIDTH_512;
116	120	orion_set_video_mode(space->machine,512);
117		} else {
	121	}
	122	else
	123	{
118	124	orion128_video_width = SCREEN_WIDTH_480;
119	125	orion_set_video_mode(space->machine,480);
120	126	}
121		} else {
	127	}
	128	else
	129	{
122	130	orion128_video_width = SCREEN_WIDTH_384;
123	131	orion_set_video_mode(space->machine,384);
124	132	}
r4582	r4583
129	137
130	138	WRITE8_HANDLER ( orion128_video_page_w )
131	139	{
132		if (orion128_video_page != data) {
133		if ((data & 0x80)!=(orion128_video_page & 0x80)) {
134		if ((data & 0x80)==0x80) {
135		if (orion_video_mode_mask == 31) {
	140	if (orion128_video_page != data)
	141	{
	142	if ((data & 0x80)!=(orion128_video_page & 0x80))
	143	{
	144	if ((data & 0x80)==0x80)
	145	{
	146	if (orion_video_mode_mask == 31)
	147	{
136	148	orion128_video_width = SCREEN_WIDTH_512;
137	149	orion_set_video_mode(space->machine,512);
138		} else {
	150	}
	151	else
	152	{
139	153	orion128_video_width = SCREEN_WIDTH_480;
140	154	orion_set_video_mode(space->machine,480);
141	155	}
142		} else {
	156	}
	157	else
	158	{
143	159	orion128_video_width = SCREEN_WIDTH_384;
144	160	orion_set_video_mode(space->machine,384);
145	161	}
r4582	r4583
151	167
152	168	WRITE8_HANDLER ( orion128_memory_page_w )
153	169	{
154		if (data!=orion128_memory_page ) {
	170	if (data!=orion128_memory_page )
	171	{
155	172	memory_set_bankptr(space->machine, 1, mess_ram + (data & 3) * 0x10000);
156	173	orion128_memory_page = (data & 3);
157	174	}
r4582	r4583
194	211	if (device_load_basicdsk_floppy (image) != INIT_PASS)
195	212	return INIT_FAIL;
196	213
197		if (size==800*1024) {
	214	if (size==800*1024)
	215	{
198	216	basicdsk_set_geometry (image, 80, 2, 5, 1024, 1, 0, FALSE);
199		} else {
	217	}
	218	else
	219	{
200	220	basicdsk_set_geometry (image, 80, 2, 9, 512, 1, 0, FALSE);
201	221	}
202	222	return INIT_PASS;
r4582	r4583
214	234	{
215	235	const device_config *fdc = devtag_get_device(space->machine, "wd1793");
216	236
217		switch(offset) {
	237	switch(offset)
	238	{
218	239	case 0x0   :
219	240	case 0x10 : return wd17xx_status_r(fdc,0);
220	241	case 0x1    :
r4582	r4583
231	252	{
232	253	const device_config *fdc = devtag_get_device(space->machine, "wd1793");
233	254
234		switch(offset) {
	255	switch(offset)
	256	{
235	257	case 0x0   :
236	258	case 0x10 : wd17xx_command_w(fdc,0,data); break;
237	259	case 0x1    :
r4582	r4583
247	269	}
248	270	static READ8_HANDLER ( orionz80_floppy_rtc_r )
249	271	{
250		if ((offset >= 0x60) && (offset <= 0x6f)) {
	272	if ((offset >= 0x60) && (offset <= 0x6f))
	273	{
251	274	return mc146818_port_r(space,offset-0x60);
252		} else {
	275	}
	276	else
	277	{
253	278	return orion128_floppy_r(space,offset);
254	279	}
255	280	}
256	281
257	282	static WRITE8_HANDLER ( orionz80_floppy_rtc_w )
258	283	{
259		if ((offset >= 0x60) && (offset <= 0x6f)) {
	284	if ((offset >= 0x60) && (offset <= 0x6f))
	285	{
260	286	mc146818_port_w(space,offset-0x60,data);
261		} else {
	287	}
	288	else
	289	{
262	290	orion128_floppy_w(space,offset,data);
263	291	}
264	292	}
r4582	r4583
283	311	WRITE8_HANDLER ( orionz80_sound_w )
284	312	{
285	313	const device_config *speaker = devtag_get_device(space->machine, "speaker");
286		if (orion_speaker==0) {
	314	if (orion_speaker == 0)
	315	{
287	316	orion_speaker = data;
288		} else {
	317	}
	318	else
	319	{
289	320	orion_speaker = 0 ;
290	321	}
291	322	speaker_level_w(speaker,orion_speaker);
r4582	r4583
303	334	{
304	335	UINT8 bank_select;
305	336	UINT8 segment_select;
306		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	337	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
307	338
308	339	bank_select = (orionz80_dispatcher & 0x0c) >> 2;
309	340	segment_select = orionz80_dispatcher & 0x03;
310	341
311	342	memory_install_write8_handler(space, 0x0000, 0x3fff, 0, 0, SMH_BANK1);
312		if ((orionz80_dispatcher & 0x80)==0) { // dispatcher on
	343	if ((orionz80_dispatcher & 0x80)==0)
	344	{ // dispatcher on
313	345	memory_set_bankptr(machine, 1, mess_ram + 0x10000 * bank_select + segment_select * 0x4000 );
314		} else { // dispatcher off
	346	}
	347	else
	348	{ // dispatcher off
315	349	memory_set_bankptr(machine, 1, mess_ram + 0x10000 * orionz80_memory_page);
316	350	}
317	351
318	352	memory_set_bankptr(machine, 2, mess_ram + 0x4000 + 0x10000 * orionz80_memory_page);
319	353
320		if ((orionz80_dispatcher & 0x20) == 0) {
	354	if ((orionz80_dispatcher & 0x20) == 0)
	355	{
321	356	memory_install_write8_handler(space, 0xf400, 0xf4ff, 0, 0, orion128_system_w);
322	357	memory_install_write8_handler(space, 0xf500, 0xf5ff, 0, 0, orion128_romdisk_w);
323	358	memory_install_write8_handler(space, 0xf700, 0xf7ff, 0, 0, orionz80_floppy_rtc_w);
r4582	r4583
335	370	memory_set_bankptr(machine, 3, mess_ram + 0xf000);
336	371	memory_set_bankptr(machine, 5, memory_region(machine, "maincpu") + 0xf800);
337	372
338		} else {
	373	}
	374	else
	375	{
339	376	/* if it is full memory access */
340	377	memory_set_bankptr(machine, 3, mess_ram + 0xf000 + 0x10000 * orionz80_memory_page);
341	378	memory_set_bankptr(machine, 4, mess_ram + 0xf400 + 0x10000 * orionz80_memory_page);
r4582	r4583
357	394
358	395	MACHINE_RESET ( orionz80 )
359	396	{
360		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	397	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
361	398
362	399	memory_install_write8_handler(space, 0x0000, 0x3fff, 0, 0, SMH_UNMAP);
363	400	memory_install_write8_handler(space, 0x4000, 0xefff, 0, 0, SMH_BANK2);
r4582	r4583
396	433
397	434	INTERRUPT_GEN( orionz80_interrupt )
398	435	{
399		if ((orionz80_dispatcher & 0x40)==0x40) {
	436	if ((orionz80_dispatcher & 0x40)==0x40)
	437	{
400	438	cpu_set_input_line(device, 0, HOLD_LINE);
401	439	}
402	440	}
403	441
404		READ8_HANDLER ( orionz80_io_r ) {
405		if (offset == 0xFFFD) {
	442	READ8_HANDLER ( orionz80_io_r )
	443	{
	444	if (offset == 0xFFFD)
	445	{
406	446	return ay8910_r (devtag_get_device(space->machine, "ay8912"), 0);
407	447	}
408	448	return 0xff;
409	449	}
410	450
411		WRITE8_HANDLER ( orionz80_io_w ) {
412		switch (offset & 0xff) {
	451	WRITE8_HANDLER ( orionz80_io_w )
	452	{
	453	switch (offset & 0xff)
	454	{
413	455	case 0xf8 : orion128_video_mode_w(space,0,data);break;
414	456	case 0xf9 : orionz80_memory_page_w(space,0,data);break;
415	457	case 0xfa : orion128_video_page_w(space,0,data);break;
r4582	r4583
417	459	case 0xfe : orionz80_sound_fe_w(space,0,data);break;
418	460	case 0xff : orionz80_sound_w(space,0,data);break;
419	461	}
420		switch(offset) {
	462	switch(offset)
	463	{
421	464	case 0xfffd : ay8910_address_w(devtag_get_device(space->machine, "ay8912"), 0, data);
422	465	break;
423	466	case 0xbffd :
r4582	r4583
453	496
454	497	static void orionpro_bank_switch(running_machine *machine)
455	498	{
456		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	499	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
457	500	int page = orionpro_page & 7; // we have only 8 pages
458	501	int is128 = (orionpro_dispatcher & 0x80) ? 1 : 0;
459		if (is128==1) {
	502	if (is128==1)
	503	{
460	504	page = orionpro_128_page & 7;
461	505	}
462	506	memory_install_write8_handler(space, 0x0000, 0x1fff, 0, 0, SMH_BANK1);
r4582	r4583
469	513	memory_install_write8_handler(space, 0xf800, 0xffff, 0, 0, SMH_BANK8);
470	514
471	515
472		if ((orionpro_dispatcher & 0x01)==0x00) {   // RAM0 segment disabled
	516	if ((orionpro_dispatcher & 0x01)==0x00)
	517	{   // RAM0 segment disabled
473	518	memory_set_bankptr(machine, 1, mess_ram + 0x10000 * page);
474	519	memory_set_bankptr(machine, 2, mess_ram + 0x10000 * page + 0x2000);
475		} else {
	520	}
	521	else
	522	{
476	523	memory_set_bankptr(machine, 1, mess_ram + (orionpro_ram0_segment & 31) * 0x4000);
477	524	memory_set_bankptr(machine, 2, mess_ram + (orionpro_ram0_segment & 31) * 0x4000 + 0x2000);
478	525	}
479		if ((orionpro_dispatcher & 0x10)==0x10) {   // ROM1 enabled
	526	if ((orionpro_dispatcher & 0x10)==0x10)
	527	{   // ROM1 enabled
480	528	memory_install_write8_handler(space, 0x0000, 0x1fff, 0, 0, SMH_UNMAP);
481	529	memory_set_bankptr(machine, 1, memory_region(machine, "maincpu") + 0x20000);
482	530	}
483		if ((orionpro_dispatcher & 0x08)==0x08) {   // ROM2 enabled
	531	if ((orionpro_dispatcher & 0x08)==0x08)
	532	{   // ROM2 enabled
484	533	memory_install_write8_handler(space, 0x2000, 0x3fff, 0, 0, SMH_UNMAP);
485	534	memory_set_bankptr(machine, 2, memory_region(machine, "maincpu") + 0x22000 + (orionpro_rom2_segment & 7) * 0x2000);
486	535	}
487	536
488		if ((orionpro_dispatcher & 0x02)==0x00) {   // RAM1 segment disabled
	537	if ((orionpro_dispatcher & 0x02)==0x00)
	538	{   // RAM1 segment disabled
489	539	memory_set_bankptr(machine, 3, mess_ram + 0x10000 * page + 0x4000);
490		} else {
	540	}
	541	else
	542	{
491	543	memory_set_bankptr(machine, 3, mess_ram + (orionpro_ram1_segment & 31) * 0x4000);
492	544	}
493	545
494		if ((orionpro_dispatcher & 0x04)==0x00) {   // RAM2 segment disabled
	546	if ((orionpro_dispatcher & 0x04)==0x00)
	547	{   // RAM2 segment disabled
495	548	memory_set_bankptr(machine, 4, mess_ram + 0x10000 * page + 0x8000);
496		} else {
	549	}
	550	else
	551	{
497	552	memory_set_bankptr(machine, 4, mess_ram + (orionpro_ram2_segment & 31) * 0x4000);
498	553	}
499	554
500	555	memory_set_bankptr(machine, 5, mess_ram + 0x10000 * page + 0xc000);
501	556
502		if (is128) {
	557	if (is128)
	558	{
503	559	memory_set_bankptr(machine, 6, mess_ram + 0x10000 * 0 + 0xf000);
504	560
505	561	memory_install_write8_handler(space, 0xf400, 0xf4ff, 0, 0, orion128_system_w);
r4582	r4583
519	575
520	576
521	577	memory_set_bankptr(machine, 8, mess_ram + 0x10000 * 0 + 0xf800);
522		} else {
523		if ((orionpro_dispatcher & 0x40)==0x40) {   // FIX F000 enabled
	578	}
	579	else
	580	{
	581	if ((orionpro_dispatcher & 0x40)==0x40)
	582	{   // FIX F000 enabled
524	583	memory_set_bankptr(machine, 6, mess_ram + 0x10000 * 0 + 0xf000);
525	584	memory_set_bankptr(machine, 7, mess_ram + 0x10000 * 0 + 0xf400);
526	585	memory_set_bankptr(machine, 8, mess_ram + 0x10000 * 0 + 0xf800);
527		} else {
	586	}
	587	else
	588	{
528	589	memory_set_bankptr(machine, 6, mess_ram + 0x10000 * page + 0xf000);
529	590	memory_set_bankptr(machine, 7, mess_ram + 0x10000 * page + 0xf400);
530	591	memory_set_bankptr(machine, 8, mess_ram + 0x10000 * page + 0xf800);
r4582	r4583
563	624	orionpro_pseudo_color = 0;
564	625	}
565	626
566		READ8_HANDLER ( orionpro_io_r ) {
	627	READ8_HANDLER ( orionpro_io_r )
	628	{
567	629	const device_config *fdc = devtag_get_device(space->machine, "wd1793");
568	630
569		switch (offset & 0xff) {
	631	switch (offset & 0xff)
	632	{
570	633	case 0x00 : return 0x56;
571	634	case 0x04 : return orionpro_ram0_segment;
572	635	case 0x05 : return orionpro_ram1_segment;
r4582	r4583
588	651	case 0x2a : return orion128_romdisk_r(space,2);
589	652	case 0x2b : return orion128_romdisk_r(space,3);
590	653	}
591		if (offset == 0xFFFD) {
	654	if (offset == 0xFFFD)
	655	{
592	656	return ay8910_r (devtag_get_device(space->machine, "ay8912"), 0);
593	657	}
594	658	return 0xff;
595	659	}
596	660
597		WRITE8_HANDLER ( orionpro_io_w ) {
	661	WRITE8_HANDLER ( orionpro_io_w )
	662	{
598	663	const device_config *fdc = devtag_get_device(space->machine, "wd1793");
599	664
600		switch (offset & 0xff) {
	665	switch (offset & 0xff)
	666	{
601	667	case 0x04 : orionpro_ram0_segment = data; orionpro_bank_switch(space->machine); break;
602	668	case 0x05 : orionpro_ram1_segment = data; orionpro_bank_switch(space->machine); break;
603	669	case 0x06 : orionpro_ram2_segment = data; orionpro_bank_switch(space->machine); break;
r4582	r4583
625	691	case 0xfe : orionz80_sound_fe_w(space,0,data);break;
626	692	case 0xff : orionz80_sound_w(space,0,data);break;
627	693	}
628		switch(offset) {
	694	switch(offset)
	695	{
629	696	case 0xfffd : ay8910_address_w(devtag_get_device(space->machine, "ay8912"), 0, data);
630	697	break;
631	698	case 0xbffd :
r4582	r4583
633	700	break;
634	701	}
635	702	}
636
	703

src/mess/machine/nascom1.c

r4582	r4583
316	316	switch (mess_ram_size)
317	317	{
318	318	case 1 * 1024:
319		memory_install_readwrite8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM),
	319	memory_install_readwrite8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM),
320	320	0x1400, 0x9000, 0, 0, SMH_NOP, SMH_NOP);
321	321	break;
322	322
323	323	case 16 * 1024:
324		memory_install_readwrite8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM),
	324	memory_install_readwrite8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM),
325	325	0x1400, 0x4fff, 0, 0, SMH_BANK1, SMH_BANK1);
326		memory_install_readwrite8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM),
	326	memory_install_readwrite8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM),
327	327	0x5000, 0xafff, 0, 0, SMH_NOP, SMH_NOP);
328	328	memory_set_bankptr(machine, 1, mess_ram);
329	329	break;
330	330
331	331	case 32 * 1024:
332		memory_install_readwrite8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM),
	332	memory_install_readwrite8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM),
333	333	0x1400, 0x8fff, 0, 0, SMH_BANK1, SMH_BANK1);
334		memory_install_readwrite8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM),
	334	memory_install_readwrite8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM),
335	335	0x9000, 0xafff, 0, 0, SMH_NOP, SMH_NOP);
336	336	memory_set_bankptr(machine, 1, mess_ram);
337	337	break;
338	338
339	339	case 40 * 1024:
340		memory_install_readwrite8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM),
	340	memory_install_readwrite8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM),
341	341	0x1400, 0xafff, 0, 0, SMH_BANK1, SMH_BANK1);
342	342	memory_set_bankptr(machine, 1, mess_ram);
343	343	break;

src/mess/machine/osborne1.c

r4582	r4583
243	243
244	244	if ( osborne1.pia_1_irq_state )
245	245	{
246		cpu_set_input_line(machine->cpu[0], 0, ASSERT_LINE );
	246	cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE );
247	247	}
248	248	else
249	249	{
250		cpu_set_input_line(machine->cpu[0], 0, CLEAR_LINE );
	250	cputag_set_input_line(machine, "maincpu", 0, CLEAR_LINE );
251	251	}
252	252	}
253	253
r4582	r4583
349	349
350	350	static TIMER_CALLBACK(osborne1_video_callback)
351	351	{
352		const address_space* space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	352	const address_space* space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
353	353	const device_config *speaker = devtag_get_device(space->machine, "beep");
354	354	const device_config *pia_1 = devtag_get_device(space->machine, "pia_1");
355	355	int y = video_screen_get_vpos(machine->primary_screen);
r4582	r4583
491	491
492	492	MACHINE_RESET( osborne1 )
493	493	{
494		const address_space* space = cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM);
	494	const address_space* space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
495	495	/* Initialize memory configuration */
496	496	osborne1_bankswitch_w( space, 0x00, 0 );
497	497
r4582	r4583
541	541	{
542	542	/* Enable ROM and I/O when IRQ is acknowledged */
543	543	UINT8   old_bankswitch = osborne1.bankswitch;
544		const address_space* space = cpu_get_address_space(device->machine->cpu[0],ADDRESS_SPACE_PROGRAM);
	544	const address_space* space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
545	545
546	546	osborne1_bankswitch_w( space, 0, 0 );
547	547	osborne1.bankswitch = old_bankswitch;

src/mess/machine/primo.c

r4582	r4583
49	49
50	50	static void primo_update_memory(running_machine *machine)
51	51	{
52		const address_space* space = cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM);
	52	const address_space* space = cputag_get_address_space(machine, "maincpu",ADDRESS_SPACE_PROGRAM);
53	53	switch (primo_port_FD & 0x03)
54	54	{
55	55	case 0x00:   /* Original ROM */
r4582	r4583
247	247	if (input_port_read(machine, "MEMORY_EXPANSION"))
248	248	primo_port_FD = 0x00;
249	249	primo_update_memory(machine);
250		cpu_set_clockscale(machine->cpu[0], input_port_read(machine, "CPU_CLOCK") ? 1.5 : 1.0);
	250	cpu_set_clockscale(cputag_get_cpu(machine, "maincpu"), input_port_read(machine, "CPU_CLOCK") ? 1.5 : 1.0);
251	251	}
252	252
253	253	MACHINE_RESET( primoa )
r4582	r4583
278	278
279	279	/* Z80 registers */
280	280
281		cpu_set_reg(machine->cpu[0], Z80_BC, snapshot_data[4] + snapshot_data[5]*256);
282		cpu_set_reg(machine->cpu[0], Z80_DE, snapshot_data[6] + snapshot_data[7]*256);
283		cpu_set_reg(machine->cpu[0], Z80_HL, snapshot_data[8] + snapshot_data[9]*256);
284		cpu_set_reg(machine->cpu[0], Z80_AF, snapshot_data[10] + snapshot_data[11]*256);
285		cpu_set_reg(machine->cpu[0], Z80_BC2, snapshot_data[12] + snapshot_data[13]*256);
286		cpu_set_reg(machine->cpu[0], Z80_DE2, snapshot_data[14] + snapshot_data[15]*256);
287		cpu_set_reg(machine->cpu[0], Z80_HL2, snapshot_data[16] + snapshot_data[17]*256);
288		cpu_set_reg(machine->cpu[0], Z80_AF2, snapshot_data[18] + snapshot_data[19]*256);
289		cpu_set_reg(machine->cpu[0], Z80_PC, snapshot_data[20] + snapshot_data[21]*256);
290		cpu_set_reg(machine->cpu[0], Z80_SP, snapshot_data[22] + snapshot_data[23]*256);
291		cpu_set_reg(machine->cpu[0], Z80_I, snapshot_data[24]);
292		cpu_set_reg(machine->cpu[0], Z80_R, snapshot_data[25]);
293		cpu_set_reg(machine->cpu[0], Z80_IX, snapshot_data[26] + snapshot_data[27]*256);
294		cpu_set_reg(machine->cpu[0], Z80_IY, snapshot_data[28] + snapshot_data[29]*256);
	281	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_BC, snapshot_data[4] + snapshot_data[5]*256);
	282	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_DE, snapshot_data[6] + snapshot_data[7]*256);
	283	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_HL, snapshot_data[8] + snapshot_data[9]*256);
	284	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_AF, snapshot_data[10] + snapshot_data[11]*256);
	285	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_BC2, snapshot_data[12] + snapshot_data[13]*256);
	286	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_DE2, snapshot_data[14] + snapshot_data[15]*256);
	287	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_HL2, snapshot_data[16] + snapshot_data[17]*256);
	288	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_AF2, snapshot_data[18] + snapshot_data[19]*256);
	289	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_PC, snapshot_data[20] + snapshot_data[21]*256);
	290	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_SP, snapshot_data[22] + snapshot_data[23]*256);
	291	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_I, snapshot_data[24]);
	292	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_R, snapshot_data[25]);
	293	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_IX, snapshot_data[26] + snapshot_data[27]*256);
	294	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_IY, snapshot_data[28] + snapshot_data[29]*256);
295	295
296	296
297	297	/* IO ports */
r4582	r4583
306	306	/* memory */
307	307
308	308	for (i=0; i<0xc000; i++)
309		memory_write_byte(cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM), i+0x4000, snapshot_data[i+38]);
	309	memory_write_byte(cputag_get_address_space(machine, "maincpu",ADDRESS_SPACE_PROGRAM), i+0x4000, snapshot_data[i+38]);
310	310	}
311	311
312	312	SNAPSHOT_LOAD( primo )
r4582	r4583
352	352	start_addr = quickload_data[2] + quickload_data[3]*256;
353	353
354	354	for (i=4; i<quickload_size; i++)
355		memory_write_byte(cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM), start_addr+i-4, quickload_data[i]);
	355	memory_write_byte(cputag_get_address_space(machine, "maincpu",ADDRESS_SPACE_PROGRAM), start_addr+i-4, quickload_data[i]);
356	356
357		cpu_set_reg(machine->cpu[0], Z80_PC, start_addr);
	357	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), Z80_PC, start_addr);
358	358
359	359	logerror ("Quickload .pp l: %04x r: %04x s: %04x\n", load_addr, start_addr, quickload_size-4);
360	360	}

src/mess/machine/pc1401.c

r4582	r4583
143	143	DRIVER_INIT( pc1401 )
144	144	{
145	145	int i;
146		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	146	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
147	147	UINT8 *gfx=memory_region(machine, "gfx1");
148	148	#if 0
149	149	char sucker[]={

src/mess/machine/nes.c

r4582	r4583
72	72
73	73	static void init_nes_core (running_machine *machine)
74	74	{
75		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	75	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
76	76
77	77	/* We set these here in case they weren't set in the cart loader */
78	78	nes.rom = memory_region(machine, "maincpu");

src/mess/machine/nes_mmc.c

r4582	r4583
95	95
96	96	static TIMER_CALLBACK(nes_irq_callback)
97	97	{
98		cpu_set_input_line(machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	98	cputag_set_input_line(machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
99	99	timer_adjust_oneshot(nes_irq_timer, attotime_never, 0);
100	100	}
101	101
r4582	r4583
645	645	if (IRQ_enable && !blanked && (IRQ_count == 0) && priorCount)
646	646	{
647	647	logerror("irq fired, scanline: %d (MAME %d, beam pos: %d)\n", scanline, video_screen_get_vpos(device->machine->primary_screen), video_screen_get_hpos(device->machine->primary_screen));
648		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
649		//         timer_adjust_oneshot(nes_irq_timer, cpu_clocks_to_attotime(device->machine->cpu[0], 4), 0);
	648	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
	649	//         timer_adjust_oneshot(nes_irq_timer, cputag_clocks_to_attotime(device->machine, "maincpu", 4), 0);
650	650	}
651	651	}
652	652	}
r4582	r4583
852	852	if (scanline == IRQ_count)
853	853	{
854	854	if (IRQ_enable)
855		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	855	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
856	856
857	857	IRQ_status = 0xff;
858	858	}
r4582	r4583
1608	1608	{
1609	1609	if (IRQ_count <= 114)
1610	1610	{
1611		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	1611	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1612	1612	}
1613	1613	IRQ_count -= 114;
1614	1614	}
r4582	r4583
1752	1752	{
1753	1753	if ((IRQ_count & 0x0f) == 0x00)
1754	1754	/* rollover every 0x10 */
1755		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	1755	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1756	1756	}
1757	1757	else if (IRQ_mode & 0x04)
1758	1758	{
1759	1759	if ((IRQ_count & 0x0ff) == 0x00)
1760	1760	/* rollover every 0x100 */
1761		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	1761	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1762	1762	}
1763	1763	else if (IRQ_mode & 0x02)
1764	1764	{
1765	1765	if ((IRQ_count & 0x0fff) == 0x000)
1766	1766	/* rollover every 0x1000 */
1767		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	1767	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1768	1768	}
1769	1769	else if (IRQ_count == 0)
1770	1770	/* rollover at 0x10000 */
1771		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	1771	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1772	1772	}
1773	1773	}
1774	1774	else
r4582	r4583
1987	1987	/* Increment & check the IRQ scanline counter */
1988	1988	if (IRQ_enable && (IRQ_count == 0x7fff))
1989	1989	{
1990		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	1990	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1991	1991	}
1992	1992	}
1993	1993
r4582	r4583
2046	2046	static void fds_irq ( const device_config *device, int scanline, int vblank, int blanked )
2047	2047	{
2048	2048	if (IRQ_enable_latch)
2049		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	2049	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
2050	2050
2051	2051	/* Increment & check the IRQ scanline counter */
2052	2052	if (IRQ_enable)
2053	2053	{
2054	2054	if (IRQ_count <= 114)
2055	2055	{
2056		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	2056	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
2057	2057	IRQ_enable = 0;
2058	2058	nes_fds.status0 |= 0x01;
2059	2059	}
r4582	r4583
2166	2166	{
2167	2167	IRQ_count = IRQ_count_latch;
2168	2168	IRQ_enable = IRQ_enable_latch;
2169		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	2169	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
2170	2170	}
2171	2171	}
2172	2172
r4582	r4583
2844	2844	{
2845	2845	if (--IRQ_count == 0)
2846	2846	{
2847		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	2847	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
2848	2848	}
2849	2849	}
2850	2850	}
r4582	r4583
2918	2918	/* Check if IRQ is being enabled */
2919	2919	if ( ! IRQ_enable && ( data & 0x02 ) ) {
2920	2920	IRQ_enable = 1;
2921		timer_adjust_oneshot(nes_irq_timer, cpu_clocks_to_attotime(space->machine->cpu[0], 24576), 0);
	2921	timer_adjust_oneshot(nes_irq_timer, cputag_clocks_to_attotime(space->machine, "maincpu", 24576), 0);
2922	2922	}
2923	2923	if ( ! ( data & 0x02 ) ) {
2924	2924	IRQ_enable = 0;
r4582	r4583
3304	3304	if (IRQ_enable)
3305	3305	{
3306	3306	if (--IRQ_count == 0)
3307		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	3307	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
3308	3308	}
3309	3309	}
3310	3310
r4582	r4583
3384	3384	{
3385	3385	if (IRQ_count <= 114)
3386	3386	{
3387		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	3387	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
3388	3388	}
3389	3389	IRQ_count -= 114;
3390	3390	}
r4582	r4583
4411	4411	if (IRQ_enable && !blanked && (IRQ_count == 0) && priorCount)
4412	4412	{
4413	4413	logerror("irq fired, scanline: %d (MAME %d, beam pos: %d)\n", scanline, video_screen_get_vpos(device->machine->primary_screen), video_screen_get_hpos(device->machine->primary_screen));
4414		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	4414	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
4415	4415	}
4416	4416	}
4417	4417	}
r4582	r4583
4932	4932	if (IRQ_enable && !blanked && (IRQ_count == 0) && priorCount)
4933	4933	{
4934	4934	logerror("irq fired, scanline: %d (MAME %d, beam pos: %d)\n", scanline, video_screen_get_vpos(device->machine->primary_screen), video_screen_get_hpos(device->machine->primary_screen));
4935		cpu_set_input_line(device->machine->cpu[0], M6502_IRQ_LINE, HOLD_LINE);
	4935	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
4936	4936	}
4937	4937	}
4938	4938	}
r4582	r4583
4949	4949	*/
4950	4950	int mapper_reset (running_machine *machine, int mapperNum)
4951	4951	{
4952		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	4952	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
4953	4953	nes_state *state = machine->driver_data;
4954	4954	int err = 0;
4955	4955	const mmc *mapper;

src/mess/machine/ondra.c

r4582	r4583
48	48	{
49	49	UINT8 *mem = memory_region(machine, "maincpu");
50	50	if (ondra_bank1_status==0) {
51		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x3fff, 0, 0, SMH_UNMAP);
	51	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0000, 0x3fff, 0, 0, SMH_UNMAP);
52	52	memory_set_bankptr(machine, 1, mem + 0x010000);
53	53	} else {
54		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x3fff, 0, 0, SMH_BANK1);
	54	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0000, 0x3fff, 0, 0, SMH_BANK1);
55	55	memory_set_bankptr(machine, 1, mess_ram + 0x0000);
56	56	}
57	57	memory_set_bankptr(machine, 2, mess_ram + 0x4000);
58	58	if (ondra_bank2_status==0) {
59		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xe000, 0xffff, 0, 0, SMH_BANK3);
60		memory_install_read8_handler (cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xe000, 0xffff, 0, 0, SMH_BANK3);
	59	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xe000, 0xffff, 0, 0, SMH_BANK3);
	60	memory_install_read8_handler (cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xe000, 0xffff, 0, 0, SMH_BANK3);
61	61	memory_set_bankptr(machine, 3, mess_ram + 0xe000);
62	62	} else {
63		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xe000, 0xffff, 0, 0, SMH_UNMAP);
64		memory_install_read8_handler (cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xe000, 0xffff, 0, 0, ondra_keyboard_r);
	63	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xe000, 0xffff, 0, 0, SMH_UNMAP);
	64	memory_install_read8_handler (cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xe000, 0xffff, 0, 0, ondra_keyboard_r);
65	65	}
66	66	}
67	67
r4582	r4583
84	84
85	85	static TIMER_CALLBACK(nmi_check_callback)
86	86	{
87		if ((input_port_read(machine, "NMI") & 1)==1) {
88		cpu_set_input_line(machine->cpu[0], INPUT_LINE_NMI, PULSE_LINE);
	87	if ((input_port_read(machine, "NMI") & 1) == 1)
	88	{
	89	cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE);
89	90	}
90	91	}
91	92

src/mess/machine/pc8801.c

r4582	r4583
122	122	}
123	123	if (level >= 0 && level<interrupt_level_reg)
124	124	{
125		cpu_set_input_line(machine->cpu[0], 0, HOLD_LINE);
	125	cputag_set_input_line(machine, "maincpu", 0, HOLD_LINE);
126	126	}
127	127	}
128	128
r4582	r4583
170	170
171	171	static void pc8801_init_interrupt(running_machine *machine)
172	172	{
173		interrupt_level_reg=0;
174		interrupt_mask_reg=0xf8;
175		interrupt_trig_reg=0x0;
176		cpu_set_irq_callback(machine->cpu[0],pc8801_interrupt_callback);
177		timer_pulse(machine, ATTOTIME_IN_HZ(600),NULL, 0,pc8801_timer_interrupt);
	173	interrupt_level_reg = 0;
	174	interrupt_mask_reg = 0xf8;
	175	interrupt_trig_reg = 0x0;
	176	cpu_set_irq_callback(cputag_get_cpu(machine, "maincpu"), pc8801_interrupt_callback);
	177	timer_pulse(machine, ATTOTIME_IN_HZ(600), NULL, 0, pc8801_timer_interrupt);
178	178	}
179	179
180	180	WRITE8_HANDLER(pc88sr_outport_30)
r4582	r4583
394	394	if(ext_w==NULL)
395	395	{
396	396	/* read only mode */
397		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x5fff, 0, 0, SMH_NOP);
398		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x6000, 0x7fff, 0, 0, SMH_NOP);
	397	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0000, 0x5fff, 0, 0, SMH_NOP);
	398	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x6000, 0x7fff, 0, 0, SMH_NOP);
399	399	}
400	400	else
401	401	{
402	402	/* r/w mode */
403		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x5fff, 0, 0, SMH_BANK1);
404		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x6000, 0x7fff, 0, 0, SMH_BANK2);
	403	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0000, 0x5fff, 0, 0, SMH_BANK1);
	404	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x6000, 0x7fff, 0, 0, SMH_BANK2);
405	405	if(ext_w!=ext_r) logerror("differnt between read and write bank of extension memory.\n");
406	406	}
407	407	}
r4582	r4583
411	411	if(RAMmode)
412	412	{
413	413	/* RAM */
414		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x5fff, 0, 0, SMH_BANK1);
415		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x6000, 0x7fff, 0, 0, SMH_BANK2);
	414	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0000, 0x5fff, 0, 0, SMH_BANK1);
	415	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x6000, 0x7fff, 0, 0, SMH_BANK2);
416	416	memory_set_bankptr(machine, 1, pc8801_mainRAM + 0x0000);
417	417	memory_set_bankptr(machine, 2, pc8801_mainRAM + 0x6000);
418	418	}
r4582	r4583
420	420	{
421	421	/* ROM */
422	422	/* write through to main RAM */
423		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x5fff, 0, 0, pc8801_writemem1);
424		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x6000, 0x7fff, 0, 0, pc8801_writemem2);
	423	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0000, 0x5fff, 0, 0, pc8801_writemem1);
	424	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x6000, 0x7fff, 0, 0, pc8801_writemem2);
425	425	if(ROMmode)
426	426	{
427	427	/* N-BASIC */
r4582	r4583
443	443	}
444	444
445	445	/* 0x8000 to 0xffff */
446		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x8000, 0x83ff, 0, 0, (RAMmode || ROMmode) ? SMH_BANK3 : pc8801_read_textwindow);
447		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x8000, 0x83ff, 0, 0, (RAMmode || ROMmode) ? SMH_BANK3 : pc8801_write_textwindow);
	446	memory_install_read8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x8000, 0x83ff, 0, 0, (RAMmode || ROMmode) ? SMH_BANK3 : pc8801_read_textwindow);
	447	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x8000, 0x83ff, 0, 0, (RAMmode || ROMmode) ? SMH_BANK3 : pc8801_write_textwindow);
448	448
449	449	memory_set_bankptr(machine, 4, pc8801_mainRAM + 0x8400);
450	450
r4582	r4583
455	455	}
456	456	else
457	457	{
458		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xc000, 0xefff, 0, 0, SMH_BANK5);
459		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xc000, 0xefff, 0, 0, SMH_BANK5);
460		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xf000, 0xffff, 0, 0, SMH_BANK6);
461		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xf000, 0xffff, 0, 0, SMH_BANK6);
	458	memory_install_read8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xc000, 0xefff, 0, 0, SMH_BANK5);
	459	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xc000, 0xefff, 0, 0, SMH_BANK5);
	460	memory_install_read8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xf000, 0xffff, 0, 0, SMH_BANK6);
	461	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xf000, 0xffff, 0, 0, SMH_BANK6);
462	462
463	463	memory_set_bankptr(machine, 5, pc8801_mainRAM + 0xc000);
464	464	if(maptvram)
r4582	r4583
805	805	/* callback for /INT output from FDC */
806	806	static NEC765_INTERRUPT( pc8801_fdc_interrupt )
807	807	{
808		cpu_set_input_line(device->machine->cpu[1], 0, state ? HOLD_LINE : CLEAR_LINE);
	808	cputag_set_input_line(device->machine, "sub", 0, state ? HOLD_LINE : CLEAR_LINE);
809	809	}
810	810
811	811	/* callback for /DRQ output from FDC */
r4582	r4583
825	825	{
826	826	use_5FD = (input_port_read(machine, "DSW2") & 0x80) != 0x00;
827	827	if (!use_5FD)
828		cpu_suspend(machine->cpu[1], SUSPEND_REASON_DISABLE, 1);
	828	cputag_suspend(machine, "sub", SUSPEND_REASON_DISABLE, 1);
829	829	else
830		cpu_resume(machine->cpu[1], SUSPEND_REASON_DISABLE);
831		cpu_set_input_line_vector(machine->cpu[1],0,0);
	830	cputag_resume(machine, "sub", SUSPEND_REASON_DISABLE);
	831	cpu_set_input_line_vector(cputag_get_cpu(machine, "sub"), 0, 0);
832	832	floppy_drive_set_motor_state(image_from_devtype_and_index(machine, IO_FLOPPY, 0), 1);
833	833	floppy_drive_set_motor_state(image_from_devtype_and_index(machine, IO_FLOPPY, 1), 1);
834	834	floppy_drive_set_ready_state(image_from_devtype_and_index(machine, IO_FLOPPY, 0), 1,0);

src/mess/machine/pc1403.c

r4582	r4583
126	126	void pc1403_outc(const device_config *device, int data)
127	127	{
128	128	pc1403_portc = data;
129		//    logerror("%g pc %.4x outc %.2x\n", attotime_to_double(timer_get_time(device->machine)), cpu_get_pc(device->machine->cpu[0]), data);
	129	//    logerror("%g pc %.4x outc %.2x\n", attotime_to_double(timer_get_time(device->machine)), cpu_get_pc(cputag_get_cpu(device->machine, "maincpu")), data);
130	130	}
131	131
132	132
r4582	r4583
172	172	DRIVER_INIT( pc1403 )
173	173	{
174	174	int i;
175		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	175	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
176	176	UINT8 *gfx=memory_region(machine, "gfx1");
177	177
178	178	for (i=0; i<128; i++) gfx[i]=i;
r4582	r4583
192	192	memory_install_write8_handler(space, 0x8000, 0xdfff, 0, 0, SMH_NOP);
193	193	}
194	194	}
195

src/mess/machine/partner.c

r4582	r4583
146	146
147	147	static void partner_iomap_bank(running_machine *machine,UINT8 *rom)
148	148	{
149		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	149	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
150	150	switch(partner_win_mem_page) {
151	151	case 2 :
152	152	// FDD
r4582	r4583
163	163	}
164	164	static void partner_bank_switch(running_machine *machine)
165	165	{
166		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	166	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
167	167	UINT8 *rom = memory_region(machine, "maincpu");
168	168
169	169	memory_install_write8_handler(space, 0x0000, 0x07ff, 0, 0, SMH_BANK1);
r4582	r4583
378	378
379	379	static WRITE8_DEVICE_HANDLER(partner_dma_write_byte)
380	380	{
381		memory_write_byte(cpu_get_address_space(device->machine->cpu[0], ADDRESS_SPACE_PROGRAM),offset,data);
	381	memory_write_byte(cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM), offset, data);
382	382	}
383	383
384	384	static READ8_DEVICE_HANDLER ( partner_wd17xx_data_r )

src/mess/machine/pp01.c

r4582	r4583
15	15	/* Driver initialization */
16	16	DRIVER_INIT(pp01)
17	17	{
18		memset(mess_ram,0,64*1024);
	18	memset(mess_ram, 0, 64 * 1024);
19	19	}
20	20
21	21
22	22	MACHINE_RESET( pp01 )
23	23	{
24	24	UINT8 *mem = memory_region(machine, "maincpu");
25		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x3fff, 0, 0, SMH_UNMAP);
	25	memory_install_write8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0000, 0x3fff, 0, 0, SMH_UNMAP);
26	26
27	27	memory_set_bankptr(machine, 1, mem + 0x010000);
28	28	memory_set_bankptr(machine, 2, mess_ram + 0x4000);

src/mess/machine/pecom.c

r4582	r4583
37	37	MACHINE_RESET( pecom )
38	38	{
39	39	UINT8 *rom = memory_region(machine, "maincpu");
40		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	40	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
41	41
42	42	pecom_state *state = machine->driver_data;
43	43
r4582	r4583
63	63	WRITE8_HANDLER( pecom_bank_w )
64	64	{
65	65	const device_config *cdp1869 = devtag_get_device(space->machine, CDP1869_TAG);
66		const address_space *space2 = cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	66	const address_space *space2 = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
67	67	UINT8 *rom = memory_region(space->machine, "maincpu");
68		memory_install_write8_handler(cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x3fff, 0, 0, SMH_BANK1);
	68	memory_install_write8_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0000, 0x3fff, 0, 0, SMH_BANK1);
69	69	memory_set_bankptr(space->machine, 1, mess_ram + 0x0000);
70	70
71		if (data==2) {
	71	if (data==2)
	72	{
72	73	memory_install_read8_device_handler (space2, cdp1869, 0xf000, 0xf7ff, 0, 0, cdp1869_charram_r);
73	74	memory_install_write8_device_handler(space2, cdp1869, 0xf000, 0xf7ff, 0, 0, cdp1869_charram_w);
74	75	memory_install_read8_device_handler (space2, cdp1869, 0xf800, 0xffff, 0, 0, cdp1869_pageram_r);
75	76	memory_install_write8_device_handler(space2, cdp1869, 0xf800, 0xffff, 0, 0, cdp1869_pageram_w);
76		} else {
	77	}
	78	else
	79	{
77	80	memory_install_write8_handler(space2, 0xf000, 0xf7ff, 0, 0, SMH_UNMAP);
78	81	memory_install_write8_handler(space2, 0xf800, 0xffff, 0, 0, SMH_UNMAP);
79	82	memory_install_read8_handler (space2, 0xf000, 0xf7ff, 0, 0, SMH_BANK3);
r4582	r4583
94	97	Address is available on address bus during reading of value from port, and that is
95	98	used to determine keyboard line reading
96	99	*/
97		UINT16 addr = cpu_get_reg(space->machine->cpu[0],CDP1802_R0 + cpu_get_reg(space->machine->cpu[0],CDP1802_X));
	100	UINT16 addr = cpu_get_reg(cputag_get_cpu(space->machine, "maincpu"), CDP1802_R0 + cpu_get_reg(cputag_get_cpu(space->machine, "maincpu"), CDP1802_X));
98	101	/* just in case somone is reading non existing ports */
99	102	if (addr<0x7cca || addr>0x7ce3) return 0;
100	103	return input_port_read(space->machine, keynames[addr - 0x7cca]) & 0x03;
r4582	r4583
119	122	double valcas = cassette_input(cassette_device_image(device->machine));
120	123	UINT8 val = input_port_read(device->machine, "CNT");
121	124
122		if ((val & 0x04)==0x04 && pecom_prev_caps_state==0) {
	125	if ((val & 0x04)==0x04 && pecom_prev_caps_state==0)
	126	{
123	127	pecom_caps_state = (pecom_caps_state==4) ? 0 : 4; // Change CAPS state
124	128	}
125	129	pecom_prev_caps_state = val & 0x04;
126		if (valcas!=0.0) { // If there is any cassette signal
	130	if (valcas!=0.0)
	131	{ // If there is any cassette signal
127	132	val = (val & 0x0D); // remove EF2 from SHIFT
128	133	flags -= EF2;
129	134	if ( valcas > 0.00) flags += EF2;
r4582	r4583
150	155
151	156	case CDP1802_STATE_CODE_S2_DMA:
152	157	// DMA acknowledge clears the DMAOUT request
153		cpu_set_input_line(device->machine->cpu[0], CDP1802_INPUT_LINE_DMAOUT, CLEAR_LINE);
	158	cputag_set_input_line(device->machine, "maincpu", CDP1802_INPUT_LINE_DMAOUT, CLEAR_LINE);
154	159	break;
155	160	case CDP1802_STATE_CODE_S3_INTERRUPT:
156	161	break;
157	162	}
158	163	}
	164
159	165	CDP1802_INTERFACE( pecom64_cdp1802_config )
160	166	{
161	167	pecom64_mode_r,

src/mess/machine/pce.c

r4582	r4583
199	199	/* Check for Street fighter 2 */
200	200	if ( size == PCE_ROM_MAXSIZE )
201	201	{
202		memory_install_write8_handler(cpu_get_address_space(image->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x01ff0, 0x01ff3, 0, 0, pce_sf2_banking_w );
	202	memory_install_write8_handler(cputag_get_address_space(image->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x01ff0, 0x01ff3, 0, 0, pce_sf2_banking_w );
203	203	}
204	204
205	205	/* Check for Populous */
r4582	r4583
207	207	{
208	208	cartridge_ram = auto_malloc( 0x8000 );
209	209	memory_set_bankptr( image->machine, 2, cartridge_ram );
210		memory_install_write8_handler(cpu_get_address_space(image->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x080000, 0x087FFF, 0, 0, pce_cartridge_ram_w );
	210	memory_install_write8_handler(cputag_get_address_space(image->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x080000, 0x087FFF, 0, 0, pce_cartridge_ram_w );
211	211	}
212	212
213	213	/* Check for CD system card */
r4582	r4583
220	220	pce_sys3_card = 1;
221	221	cartridge_ram = auto_malloc( 0x30000 );
222	222	memory_set_bankptr( image->machine, 4, cartridge_ram );
223		memory_install_write8_handler(cpu_get_address_space(image->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0D0000, 0x0FFFFF, 0, 0, pce_cartridge_ram_w );
	223	memory_install_write8_handler(cputag_get_address_space(image->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0D0000, 0x0FFFFF, 0, 0, pce_cartridge_ram_w );
224	224	}
225	225	}
226	226	return 0;
r4582	r4583
863	863
864	864	if ( pce_cd.regs[0x02] & pce_cd.regs[0x03] & ( PCE_CD_IRQ_TRANSFER_DONE | PCE_CD_IRQ_TRANSFER_READY ) )
865	865	{
866		cpu_set_input_line(machine->cpu[0], 1, ASSERT_LINE );
	866	cputag_set_input_line(machine, "maincpu", 1, ASSERT_LINE );
867	867	}
868	868	else
869	869	{
870		cpu_set_input_line(machine->cpu[0], 1, CLEAR_LINE );
	870	cputag_set_input_line(machine, "maincpu", 1, CLEAR_LINE );
871	871	}
872	872	}
873	873
r4582	r4583
1078	1078	if ( pce_cd.scsi_IO )
1079	1079	{
1080	1080	pce_cd.scsi_ACK = 1;
1081		timer_set(machine, cpu_clocks_to_attotime(machine->cpu[0], 15), NULL, 0, pce_cd_clear_ack );
	1081	timer_set(machine, cputag_clocks_to_attotime(machine, "maincpu", 15), NULL, 0, pce_cd_clear_ack );
1082	1082	}
1083	1083	}
1084	1084	return data;

src/mess/machine/pc1251.c

r4582	r4583
121	121	DRIVER_INIT( pc1251 )
122	122	{
123	123	int i;
124		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	124	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
125	125	UINT8 *gfx = memory_region(machine, "gfx1");
126	126	for (i=0; i<128; i++) gfx[i]=i;
127	127

src/mess/machine/pk8020.c

r4582	r4583
21	21
22	22	MACHINE_RESET( pk8020 )
23	23	{
24		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	24	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
25	25
26	26	memory_install_read8_handler (space, 0x0000, 0x1fff, 0, 0, SMH_BANK1);
27	27	memory_install_write8_handler(space, 0x0000, 0x7fff, 0, 0, SMH_UNMAP);

src/mess/drivers/nc.c

r4582	r4583
304	304	(((nc_irq_status & nc_irq_mask) & 0x3f)!=0)
305	305	)
306	306	{
307		logerror("int set %02x\n",nc_irq_status & nc_irq_mask);
	307	logerror("int set %02x\n", nc_irq_status & nc_irq_mask);
308	308	/* set int */
309		cpu_set_input_line(machine->cpu[0], 0, HOLD_LINE);
	309	cputag_set_input_line(machine, "maincpu", 0, HOLD_LINE);
310	310	}
311	311	else
312	312	{
313	313	/* clear int */
314		cpu_set_input_line(machine->cpu[0], 0, CLEAR_LINE);
	314	cputag_set_input_line(machine, "maincpu", 0, CLEAR_LINE);
315	315	}
316	316	}
317	317
r4582	r4583
338	338
339	339	static void nc_refresh_memory_bank_config(running_machine *machine, int bank)
340	340	{
341		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	341	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
342	342	int mem_type;
343	343	int mem_bank;
344	344	read8_space_func read_handler;
r4582	r4583
533	533	case NC_TYPE_1xx:
534	534	{
535	535	LOG(("nmi triggered\n"));
536		cpu_set_input_line(machine->cpu[0], INPUT_LINE_NMI, PULSE_LINE);
	536	cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE);
537	537	}
538	538	break;
539	539
540	540	case NC_TYPE_200:
541	541	{
542		nc_irq_status |=(1<<4);
	542	nc_irq_status |= (1 << 4);
543	543	nc_update_interrupts(machine);
544	544	}
545	545	break;
r4582	r4583
872	872	is cleared this will not cause another nmi */
873	873	/* I'll emulate it like this to be sure */
874	874
875		if (state!=previous_alarm_state)
	875	if (state != previous_alarm_state)
876	876	{
877	877	if (state)
878	878	{
879	879	/* I'll pulse it because if I used hold-line I'm not sure
880	880	it would clear - to be checked */
881		cpu_set_input_line(device->machine->cpu[0], INPUT_LINE_NMI, PULSE_LINE);
	881	cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE);
882	882	}
883	883	}
884	884
r4582	r4583
887	887
888	888	static void nc100_txrdy_callback(const device_config *device, int state)
889	889	{
890		nc_irq_latch &= ~(1<<1);
	890	nc_irq_latch &= ~(1 << 1);
891	891
892	892	/* uart on? */
893		if ((nc_uart_control & (1<<3))==0)
	893	if ((nc_uart_control & (1 << 3)) == 0)
894	894	{
895	895	if (state)
896	896	{
897	897	logerror("tx ready\n");
898		nc_irq_latch |= (1<<1);
	898	nc_irq_latch |= (1 << 1);
899	899	}
900	900	}
901	901
r4582	r4583
1454	1454	}
1455	1455
1456	1456	/* bit 5 is used in disk interface */
1457		LOG_DEBUG(("bit 5: PC: %04x %02x\n",cpu_get_pc(space->machine->cpu[0]), data & (1<<5)));
	1457	LOG_DEBUG(("bit 5: PC: %04x %02x\n", cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")), data & (1 << 5)));
1458	1458	}
1459	1459
1460	1460
r4582	r4583
1473	1473	static WRITE8_HANDLER(nc200_memory_card_wait_state_w)
1474	1474	{
1475	1475	const device_config *fdc = devtag_get_device(space->machine, "nec765");
1476		LOG_DEBUG(("nc200 memory card wait state: PC: %04x %02x\n",cpu_get_pc(space->machine->cpu[0]),data));
	1476	LOG_DEBUG(("nc200 memory card wait state: PC: %04x %02x\n", cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")), data));
1477	1477	#if 0
1478		floppy_drive_set_motor_state(0,1);
1479		floppy_drive_set_ready_state(0,1,1);
	1478	floppy_drive_set_motor_state(0, 1);
	1479	floppy_drive_set_ready_state(0, 1, 1);
1480	1480	#endif
1481	1481	nec765_set_tc_state(fdc, (data & 0x01));
1482	1482	}
r4582	r4583
1486	1486	/* bit 0 seems to be the same as nc100 */
1487	1487	static WRITE8_HANDLER(nc200_poweroff_control_w)
1488	1488	{
1489		LOG_DEBUG(("nc200 power off: PC: %04x %02x\n",cpu_get_pc(space->machine->cpu[0]),data));
	1489	LOG_DEBUG(("nc200 power off: PC: %04x %02x\n", cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")), data));
1490	1490
1491		nc200_video_set_backlight(((data^(1<<2))>>2) & 0x01);
	1491	nc200_video_set_backlight(((data ^ (1 << 2)) >> 2) & 0x01);
1492	1492	}
1493	1493
1494	1494	static ADDRESS_MAP_START(nc200_io, ADDRESS_SPACE_IO, 8)

src/mess/drivers/pentagon.c

r4582	r4583
16	16
17	17	static DIRECT_UPDATE_HANDLER( pentagon_direct )
18	18	{
19		UINT16 pc = cpu_get_reg(space->machine->cpu[0], REG_GENPCBASE);
20		if (betadisk_is_active()) {
21		if (pc >= 0x4000) {
	19	UINT16 pc = cpu_get_reg(cputag_get_cpu(space->machine, "maincpu"), REG_GENPCBASE);
	20	if (betadisk_is_active())
	21	{
	22	if (pc >= 0x4000)
	23	{
22	24	ROMSelection = ((spectrum_128_port_7ffd_data>>4) & 0x01) ? 1 : 0;
23	25	betadisk_disable();
24	26	memory_install_write8_handler(space, 0x0000, 0x3fff, 0, 0, SMH_UNMAP);
r4582	r4583
30	32	betadisk_enable();
31	33
32	34	}
33		if((address>=0x0000) && (address<=0x3fff)) {
	35	if((address>=0x0000) && (address<=0x3fff))
	36	{
34	37	memory_install_write8_handler(space, 0x0000, 0x3fff, 0, 0, SMH_UNMAP);
35	38	direct->raw = direct->decrypted =  memory_region(space->machine, "maincpu") + 0x010000 + (ROMSelection<<14);
36	39	memory_set_bankptr(space->machine, 1, direct->raw);
r4582	r4583
45	48
46	49	memory_set_bankptr(machine, 4, mess_ram + ((spectrum_128_port_7ffd_data & 0x07) * 0x4000));
47	50
48		if( betadisk_is_active() && !( spectrum_128_port_7ffd_data & 0x10 ) ) {
	51	if( betadisk_is_active() && !( spectrum_128_port_7ffd_data & 0x10 ) )
	52	{
49	53	/* GLUK */
50	54	ROMSelection = 2;
51	55	}
r4582	r4583
86	90
87	91	static MACHINE_RESET( pentagon )
88	92	{
89		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	93	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
90	94
91	95	memory_install_read8_handler(space, 0x0000, 0x3fff, 0, 0, SMH_BANK1);
92	96	memory_install_write8_handler(space, 0x0000, 0x3fff, 0, 0, SMH_UNMAP);

src/mess/drivers/nes.c

r4582	r4583
217	217
218	218	static void ppu_nmi(const device_config *device, int *ppu_regs)
219	219	{
220		cpu_set_input_line(device->machine->cpu[0], INPUT_LINE_NMI, PULSE_LINE);
	220	cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE);
221	221	}
222	222
223	223

src/mess/drivers/palm.c

r4582	r4583
91	91
92	92	static MACHINE_START( palm )
93	93	{
94		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
95		memory_install_read16_handler(space,0x000000,mess_ram_size-1,mess_ram_size-1,0,(read16_space_func)1);
96		memory_install_write16_handler(space,0x000000,mess_ram_size-1,mess_ram_size-1,0,(write16_space_func)1);
	94	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	95	memory_install_read16_handler (space, 0x000000, mess_ram_size - 1, mess_ram_size - 1, 0, (read16_space_func)1);
	96	memory_install_write16_handler(space, 0x000000, mess_ram_size - 1, mess_ram_size - 1, 0, (write16_space_func)1);
97	97	memory_set_bankptr(machine, 1, mess_ram);
98	98
99	99	state_save_register_global(machine, port_f_latch);
r4582	r4583
107	107	memset(mess_ram, 0, mess_ram_size);
108	108	memcpy(mess_ram, bios, 0x20000);
109	109
110		device_reset(machine->cpu[0]);
	110	device_reset(cputag_get_cpu(machine, "maincpu"));
111	111	}
112	112
113	113
r4582	r4583
137	137
138	138	static DRIVER_INIT( palm )
139	139	{
140		debug_cpu_set_dasm_override(machine->cpu[0], palm_dasm_override);
	140	debug_cpu_set_dasm_override(cputag_get_cpu(machine, "maincpu"), palm_dasm_override);
141	141	}
142	142
143	143	static const mc68328_interface palm_dragonball_iface =

src/mess/drivers/pcw16.c

r4582	r4583
131	131	/* any bits set excluding vsync */
132	132	if ((pcw16_system_status & (~0x04))!=0)
133	133	{
134		cpu_set_input_line(machine->cpu[0], 0, HOLD_LINE);
	134	cputag_set_input_line(machine, "maincpu", 0, HOLD_LINE);
135	135	}
136	136	else
137	137	{
138		cpu_set_input_line(machine->cpu[0], 0, CLEAR_LINE);
	138	cputag_set_input_line(machine, "maincpu", 0, CLEAR_LINE);
139	139	}
140	140	}
141	141
r4582	r4583
370	370
371	371	static void pcw16_set_bank_handlers(running_machine *machine, int bank, PCW16_RAM_TYPE type)
372	372	{
373		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	373	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
374	374	read8_space_func read_handler;
375	375	write8_space_func write_handler;
376	376
r4582	r4583
1010	1010	{
1011	1011	/* I'll pulse it because if I used hold-line I'm not sure
1012	1012	it would clear - to be checked */
1013		cpu_set_input_line(machine->cpu[0], INPUT_LINE_NMI, PULSE_LINE);
	1013	cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE);
1014	1014	}
1015	1015	}
1016	1016	}

src/mess/drivers/pasogo.c

r4582	r4583
420	420
421	421	static INTERRUPT_GEN( pasogo_interrupt )
422	422	{
423		//   cpu_set_input_line(machine->cpu[0], UPD7810_INTFE1, PULSE_LINE);
	423	//   cputag_set_input_line(machine, "maincpu", UPD7810_INTFE1, PULSE_LINE);
424	424	}
425	425
426	426	static IRQ_CALLBACK(pasogo_irq_callback)
r4582	r4583
430	430
431	431	static MACHINE_RESET( pasogo )
432	432	{
433		cpu_set_irq_callback(machine->cpu[0], pasogo_irq_callback);
	433	cpu_set_irq_callback(cputag_get_cpu(machine, "maincpu"), pasogo_irq_callback);
434	434	}
435	435
436	436	//static const unsigned i86_address_mask = 0x000fffff;
r4582	r4583
459	459
460	460	static PIC8259_SET_INT_LINE( pasogo_pic8259_set_int_line )
461	461	{
462		cpu_set_input_line(device->machine->cpu[0], 0, interrupt ? HOLD_LINE : CLEAR_LINE);
	462	cputag_set_input_line(device->machine, "maincpu", 0, interrupt ? HOLD_LINE : CLEAR_LINE);
463	463	}
464	464
465	465

src/mess/drivers/px4.c

r4582	r4583
232	232	static WRITE8_HANDLER( px4_bankr_w )
233	233	{
234	234	px4_state *px4 = space->machine->driver_data;
235		const address_space *space_program = cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	235	const address_space *space_program = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
236	236
237	237	logerror("%s: px4_bankr_w (0x%02x)\n", cpuexec_describe_context(space->machine), data);
238	238

src/mess/drivers/p2000t.c

r4582	r4583
209	209
210	210	static INTERRUPT_GEN( p2000_interrupt )
211	211	{
212		cpu_set_input_line(device->machine->cpu[0], 0, HOLD_LINE);
	212	cputag_set_input_line(device->machine, "maincpu", 0, HOLD_LINE);
213	213	}
214	214
215	215	/* Machine definition */

src/mess/drivers/pcw.c

r4582	r4583
150	150	((fdc_interrupt_code==1) && ((pcw_system_status & (1<<5))!=0))
151	151	)
152	152	{
153		cpu_set_input_line(machine->cpu[0], 0,HOLD_LINE);
	153	cputag_set_input_line(machine, "maincpu", 0,HOLD_LINE);
154	154	}
155	155	else
156	156	{
157		cpu_set_input_line(machine->cpu[0], 0,CLEAR_LINE);
	157	cputag_set_input_line(machine, "maincpu", 0,CLEAR_LINE);
158	158	}
159	159	}
160	160
r4582	r4583
194	194	{
195	195	/* I'll pulse it because if I used hold-line I'm not sure
196	196	it would clear - to be checked */
197		cpu_set_input_line(machine->cpu[0], INPUT_LINE_NMI, PULSE_LINE);
	197	cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE);
198	198	}
199	199	}
200	200	}
r4582	r4583
262	262
263	263	static void pcw_update_read_memory_block(running_machine *machine, int block, int bank)
264	264	{
265		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	265	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
266	266	memory_set_bankptr(machine, block + 1, mess_ram + ((bank * 0x4000) % mess_ram_size));
267	267
268	268	/* bank 3? */
r4582	r4583
488	488	/* yes */
489	489
490	490	/* clear nmi interrupt */
491		cpu_set_input_line(space->machine->cpu[0], INPUT_LINE_NMI, CLEAR_LINE);
	491	cputag_set_input_line(space->machine, "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
492	492	}
493	493
494	494	/* re-issue interrupt */
r4582	r4583
510	510	/* yes */
511	511
512	512	/* Clear NMI */
513		cpu_set_input_line(space->machine->cpu[0], INPUT_LINE_NMI, CLEAR_LINE);
	513	cputag_set_input_line(space->machine, "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
514	514
515	515	}
516	516
r4582	r4583
761	761	{
762	762	pcw_boot = 1;
763	763
764		cpu_set_input_line_vector(machine->cpu[0], 0,0x0ff);
	764	cpu_set_input_line_vector(cputag_get_cpu(machine, "maincpu"), 0, 0x0ff);
765	765
766	766
767	767	/* ram paging is actually undefined at power-on */
r4582	r4583
1079	1079	COMP( 1987, pcw9256,   pcw8256,   0,      pcw,     pcw,   pcw,   pcw_256k,   "Amstrad plc", "PCW9256",      GAME_NOT_WORKING)
1080	1080	COMP( 1987, pcw9512,   pcw8256,   0,      pcw9512,  pcw,   pcw,   pcw_512k,   "Amstrad plc", "PCW9512 (+)",   GAME_NOT_WORKING)
1081	1081	COMP( 1993, pcw10,       pcw8256,   0,      pcw9512,  pcw,   pcw,   pcw_512k,   "Amstrad plc", "PCW10",         GAME_NOT_WORKING)
1082

src/mess/drivers/ql.c

r4582	r4583
529	529	{
530	530	ql_state *state = machine->driver_data;
531	531
532		const address_space *program = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	532	const address_space *program = cputag_get_address_space(machine, M68008_TAG, ADDRESS_SPACE_PROGRAM);
533	533
534	534	/* configure ROM cartridge */
535	535
r4582	r4583
613	613	MDRV_DRIVER_DATA(ql_state)
614	614
615	615	// basic machine hardware
616
617	616	MDRV_CPU_ADD(M68008_TAG, M68008, X1/2)
618	617	MDRV_CPU_PROGRAM_MAP(ql_map, 0)
619	618

src/mess/drivers/newbrain.c

r4582	r4583
1042	1042
1043	1043	*/
1044	1044
1045		cpu_set_input_line(space->machine->cpu[2], INPUT_LINE_RESET, BIT(data, 5) ? HOLD_LINE : CLEAR_LINE);
	1045	cputag_set_input_line(space->machine, FDC_Z80_TAG, INPUT_LINE_RESET, BIT(data, 5) ? HOLD_LINE : CLEAR_LINE);
1046	1046
1047	1047	state->paging = BIT(data, 0);
1048	1048	state->a16 = BIT(data, 2);

src/mess/drivers/psx.c

r4582	r4583
371	371	{
372	372	if( address == 0x80030000 )
373	373	{
374		const device_config *cpu = space->machine->cpu[ 0 ];
	374	const device_config *cpu = cputag_get_cpu(space->machine, "maincpu");
375	375
376	376	memory_set_direct_update_handler( space, NULL );
377	377
r4582	r4583
396	396
397	397	static QUICKLOAD_LOAD( psx_exe_load )
398	398	{
399		const address_space *space = cpu_get_address_space( image->machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	399	const address_space *space = cputag_get_address_space( image->machine, "maincpu", ADDRESS_SPACE_PROGRAM );
400	400
401	401	exe_size = 0;
402	402	exe_buffer = malloc( quickload_size );

src/mess/drivers/pp01.c

r4582	r4583
26	26	/* Input ports */
27	27	static INPUT_PORTS_START( pp01 )
28	28	PORT_START("LINE0")
29		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U)
30		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A)
31		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T)
32		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L)
33		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W)
34		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F6") PORT_CODE(KEYCODE_F6)
35		PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F)
36		PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F7") PORT_CODE(KEYCODE_F7)
	29	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U)
	30	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A)
	31	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T)
	32	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L)
	33	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W)
	34	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F6") PORT_CODE(KEYCODE_F6)
	35	PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F)
	36	PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("F7") PORT_CODE(KEYCODE_F7)
37	37
38	38	INPUT_PORTS_END
39	39
40	40	/* Machine driver */
41	41	static MACHINE_DRIVER_START( pp01 )
42		/* basic machine hardware */
43		MDRV_CPU_ADD("maincpu", 8080, 2000000)
44		MDRV_CPU_PROGRAM_MAP(pp01_mem, 0)
45		MDRV_CPU_IO_MAP(pp01_io, 0)
	42	/* basic machine hardware */
	43	MDRV_CPU_ADD("maincpu", 8080, 2000000)
	44	MDRV_CPU_PROGRAM_MAP(pp01_mem, 0)
	45	MDRV_CPU_IO_MAP(pp01_io, 0)
46	46
47		MDRV_MACHINE_START( pp01 )
48		MDRV_MACHINE_RESET( pp01 )
	47	MDRV_MACHINE_START( pp01 )
	48	MDRV_MACHINE_RESET( pp01 )
49	49
50	50	/* video hardware */
51		MDRV_SCREEN_ADD("screen", RASTER)
52		MDRV_SCREEN_REFRESH_RATE(50)
53		MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
54		MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
55		MDRV_SCREEN_SIZE(256, 256)
56		MDRV_SCREEN_VISIBLE_AREA(0, 256-1, 0, 256-1)
57		MDRV_PALETTE_LENGTH(8)
58		MDRV_PALETTE_INIT(pp01)
	51	MDRV_SCREEN_ADD("screen", RASTER)
	52	MDRV_SCREEN_REFRESH_RATE(50)
	53	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
	54	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
	55	MDRV_SCREEN_SIZE(256, 256)
	56	MDRV_SCREEN_VISIBLE_AREA(0, 256-1, 0, 256-1)
	57	MDRV_PALETTE_LENGTH(8)
	58	MDRV_PALETTE_INIT(pp01)
59	59
60		MDRV_VIDEO_START(pp01)
61		MDRV_VIDEO_UPDATE(pp01)
	60	MDRV_VIDEO_START(pp01)
	61	MDRV_VIDEO_UPDATE(pp01)
62	62	MACHINE_DRIVER_END
63	63
64	64	static SYSTEM_CONFIG_START(pp01)
r4582	r4583
68	68	/* ROM definition */
69	69
70	70	ROM_START( pp01 )
71		ROM_REGION( 0x14000, "maincpu", ROMREGION_ERASEFF )
72		ROM_LOAD( "pp01.rom", 0x10000, 0x4000, CRC(d6ee4dd6) SHA1(acc162975f255bc8de5ca0fd8da11d1d7bd7fbfc) )
	71	ROM_REGION( 0x14000, "maincpu", ROMREGION_ERASEFF )
	72	ROM_LOAD( "pp01.rom", 0x10000, 0x4000, CRC(d6ee4dd6) SHA1(acc162975f255bc8de5ca0fd8da11d1d7bd7fbfc) )
73	73	ROM_END
74	74
75	75
r4582	r4583
77	77
78	78	/*    YEAR  NAME    PARENT  COMPAT  MACHINE     INPUT       INIT     CONFIG COMPANY                  FULLNAME   FLAGS */
79	79	COMP( 198?, pp01,    0,        0,      pp01,       pp01,       pp01,     pp01,     "ZVT",                "PP-01",    GAME_NOT_WORKING)
80

src/mess/drivers/pce.c

r4582	r4583
268	268	CONS( 1987, pce,    0,      0,      pce,    pce,     pce,   0,   "Nippon Electronic Company", "PC Engine", GAME_IMPERFECT_SOUND )
269	269	CONS( 1989, tg16,   pce,    0,      pce,    pce,     tg16,  0,   "Nippon Electronic Company", "TurboGrafx 16", GAME_IMPERFECT_SOUND )
270	270	CONS( 1989, sgx,    pce,    0,      sgx,    pce,     sgx,   0,   "Nippon Electronic Company", "SuperGrafx", GAME_IMPERFECT_SOUND )
271

src/mess/drivers/pk8020.c

r4582	r4583
45	45	/* Machine driver */
46	46	static MACHINE_DRIVER_START( pk8020 )
47	47	/* basic machine hardware */
48		MDRV_CPU_ADD("maincpu", 8080, 2500000)
49		MDRV_CPU_PROGRAM_MAP(pk8020_mem, 0)
50		MDRV_CPU_IO_MAP(pk8020_io, 0)
	48	MDRV_CPU_ADD("maincpu", 8080, 2500000)
	49	MDRV_CPU_PROGRAM_MAP(pk8020_mem, 0)
	50	MDRV_CPU_IO_MAP(pk8020_io, 0)
51	51
52		MDRV_MACHINE_RESET( pk8020 )
	52	MDRV_MACHINE_RESET( pk8020 )
53	53
54	54	/* video hardware */
55	55	MDRV_SCREEN_ADD("screen", RASTER)
r4582	r4583
62	62	MDRV_PALETTE_INIT(pk8020)
63	63
64	64	MDRV_VIDEO_START(pk8020)
65		MDRV_VIDEO_UPDATE(pk8020)
	65	MDRV_VIDEO_UPDATE(pk8020)
66	66	MACHINE_DRIVER_END
67	67
68	68	/* ROM definition */

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