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r4577 Monday 27th April, 2009 at 21:36:43 UTC by Fabio Priuli
A last round for today

[src/mess/drivers]	mac.c mephisto.c mk1.c mk2.c mpf1.c mtx.c
[src/mess/machine]	kaypro.c kc.c lisa.c lviv.c lynx.c mac.c mc10.c microtan.c mikro80.c msx.c msx_slot.c mtx.c mz700.c mz80.c
[src/mess/video]	kramermc.c mz80.c

src/mess/video/kramermc.c

r4576	r4577
30	30	VIDEO_UPDATE( kramermc )
31	31	{
32	32	int x,y;
33		const address_space *space = cpu_get_address_space(screen->machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	33	const address_space *space = cputag_get_address_space(screen->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
34	34
35	35	for(y = 0; y < 16; y++ )
36	36	{

src/mess/video/mz80.c

r4576	r4577
41	41	VIDEO_UPDATE( mz80k )
42	42	{
43	43	int x,y;
44		const address_space *space = cpu_get_address_space(screen->machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	44	const address_space *space = cputag_get_address_space(screen->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
45	45	mz80k_vertical = mz80k_vertical ? 0 : 1;
46	46	mz80k_cursor_cnt++;
47	47	if (mz80k_cursor_cnt==64) mz80k_cursor_cnt = 0;

src/mess/machine/msx_slot.c

r4576	r4577
29	29
30	30	static void msx_cpu_setbank (running_machine *machine, int page, UINT8 *mem)
31	31	{
32		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
33		switch (page) {
	32	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	33	switch (page)
	34	{
34	35	case 1:
35	36	case 2:
36	37	case 3:
r4576	r4577
135	136
136	137	nsize = 0x10000; /* 64 kb */
137	138	mask = 3;
138		for (i=0; i<6; i++) {
139		if (size == nsize) {
	139	for (i=0; i<6; i++)
	140	{
	141	if (size == nsize)
	142	{
140	143	break;
141	144	}
142	145	mask = (mask << 1) | 1;
143	146	nsize <<= 1;
144	147	}
145		if (i == 6) {
	148	if (i == 6)
	149	{
146	150	logerror ("ram mapper: error: must be 64kb, 128kb, 256kb, 512kb, "
147	151	"1mb, 2mb or 4mb\n");
148	152	return 1;
r4576	r4577
152	156
153	157	#ifdef MONMSX
154	158	f = fopen ("/home/sean/msx/hack/monmsx.bin", "r");
155		if (f) {
	159	if (f)
	160	{
156	161	fseek (f, 6L, SEEK_SET);
157	162	fread (state->mem, 1, 6151 - 6, f);
158	163	fclose (f);
r4576	r4577
171	176	{
172	177	int i;
173	178
174		for (i=0; i<4; i++) {
	179	for (i=0; i<4; i++)
	180	{
175	181	msx1.ram_mapper[i] = 3 - i;
176	182	}
177	183	}
r4576	r4577
188	194
189	195	MSX_SLOT_INIT(msxdos2)
190	196	{
191		if (size != 0x10000) {
	197	if (size != 0x10000)
	198	{
192	199	logerror ("msxdos2: error: rom file must be 64kb\n");
193	200	return 1;
194	201	}
r4576	r4577
206	213
207	214	MSX_SLOT_MAP(msxdos2)
208	215	{
209		if (page != 1) {
	216	if (page != 1)
	217	{
210	218	msx_cpu_setbank (machine, page * 2 + 1, msx1.empty);
211	219	msx_cpu_setbank (machine, page * 2 + 2, msx1.empty);
212		} else {
	220	}
	221	else
	222	{
213	223	msx_cpu_setbank (machine, 3, state->mem + state->banks[0] * 0x4000);
214	224	msx_cpu_setbank (machine, 4, state->mem + state->banks[0] * 0x4000 + 0x2000);
215	225	}
r4576	r4577
217	227
218	228	MSX_SLOT_WRITE(msxdos2)
219	229	{
220		if (addr == 0x6000) {
	230	if (addr == 0x6000)
	231	{
221	232	state->banks[0] = val & 3;
222	233	slot_msxdos2_map (machine, state, 1);
223	234	}
r4576	r4577
227	238	{
228	239	int banks;
229	240
230		if (size > 0x200000) {
	241	if (size > 0x200000)
	242	{
231	243	logerror ("konami: warning: truncating to 2mb\n");
232	244	size = 0x200000;
233	245	return 1;
234	246	}
235	247	banks = size / 0x2000;
236		if (size != banks * 0x2000 || (~(banks - 1) % banks)) {
	248	if (size != banks * 0x2000 || (~(banks - 1) % banks))
	249	{
237	250	logerror ("konami: error: must be a 2 power of 8kb\n");
238	251	return 1;
239	252	}
r4576	r4577
254	267
255	268	MSX_SLOT_MAP(konami)
256	269	{
257		switch (page) {
	270	switch (page)
	271	{
258	272	case 0:
259	273	msx_cpu_setbank (machine, 1, state->mem);
260	274	msx_cpu_setbank (machine, 2, state->mem + state->banks[1] * 0x2000);
r4576	r4577
275	289
276	290	MSX_SLOT_WRITE(konami)
277	291	{
278		switch (addr) {
	292	switch (addr)
	293	{
279	294	case 0x6000:
280	295	state->banks[1] = val & state->bank_mask;
281	296	slot_konami_map (machine, state, 1);
282		if (msx1.state[0] == state) {
	297	if (msx1.state[0] == state)
	298	{
283	299	slot_konami_map (machine, state, 0);
284	300	}
285	301	break;
286	302	case 0x8000:
287	303	state->banks[2] = val & state->bank_mask;
288	304	slot_konami_map (machine, state, 2);
289		if (msx1.state[3] == state) {
	305	if (msx1.state[3] == state)
	306	{
290	307	slot_konami_map (machine, state, 3);
291	308	}
292	309	break;
293	310	case 0xa000:
294	311	state->banks[3] = val & state->bank_mask;
295	312	slot_konami_map (machine, state, 2);
296		if (msx1.state[3] == state) {
	313	if (msx1.state[3] == state)
	314	{
297	315	slot_konami_map (machine, state, 3);
298	316	}
299	317	}
r4576	r4577
303	321	{
304	322	int banks;
305	323
306		if (size > 0x200000) {
	324	if (size > 0x200000)
	325	{
307	326	logerror ("konami_scc: warning: truncating to 2mb\n");
308	327	size = 0x200000;
309	328	return 1;
310	329	}
311	330	banks = size / 0x2000;
312		if (size != banks * 0x2000 || (~(banks - 1) % banks)) {
	331	if (size != banks * 0x2000 || (~(banks - 1) % banks))
	332	{
313	333	logerror ("konami_scc: error: must be a 2 power of 8kb\n");
314	334	return 1;
315	335	}
r4576	r4577
332	352
333	353	static READ8_HANDLER (konami_scc_bank5)
334	354	{
335		if (offset & 0x80) {
	355	if (offset & 0x80)
	356	{
336	357	#if 0
337		if ((offset & 0xff) >= 0xe0) {
	358	if ((offset & 0xff) >= 0xe0)
	359	{
338	360	/* write 0xff to deformation register */
339	361	}
340	362	#endif
341	363	return 0xff;
342	364	}
343		else {
	365	else
	366	{
344	367	return k051649_waveform_r (devtag_get_device(space->machine, "k051649"), offset & 0x7f);
345	368	}
346	369	}
347	370
348	371	MSX_SLOT_MAP(konami_scc)
349	372	{
350		switch (page) {
	373	switch (page)
	374	{
351	375	case 0:
352	376	msx_cpu_setbank (machine, 1, state->mem + state->banks[2] * 0x2000);
353	377	msx_cpu_setbank (machine, 2, state->mem + state->banks[3] * 0x2000);
r4576	r4577
359	383	case 2:
360	384	msx_cpu_setbank (machine, 5, state->mem + state->banks[2] * 0x2000);
361	385	msx_cpu_setbank (machine, 6, state->mem + state->banks[3] * 0x2000);
362		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x9800, 0x9fff, 0, 0,
	386	memory_install_read8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x9800, 0x9fff, 0, 0,
363	387	state->cart.scc.active ? konami_scc_bank5 : SMH_BANK7);
364	388	break;
365	389	case 3:
r4576	r4577
370	394
371	395	MSX_SLOT_WRITE(konami_scc)
372	396	{
373		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
374		if (addr >= 0x5000 && addr < 0x5800) {
	397	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	398	if (addr >= 0x5000 && addr < 0x5800)
	399	{
375	400	state->banks[0] = val & state->bank_mask;
376	401	slot_konami_scc_map (machine, state, 1);
377		if (msx1.state[3] == state) {
	402	if (msx1.state[3] == state)
	403	{
378	404	slot_konami_scc_map (machine, state, 3);
379	405	}
380	406	}
381		else if (addr >= 0x7000 && addr < 0x7800) {
	407	else if (addr >= 0x7000 && addr < 0x7800)
	408	{
382	409	state->banks[1] = val & state->bank_mask;
383	410	slot_konami_scc_map (machine, state, 1);
384		if (msx1.state[3] == state) {
	411	if (msx1.state[3] == state)
	412	{
385	413	slot_konami_scc_map (machine, state, 3);
386	414	}
387	415	}
388		else if (addr >= 0x9000 && addr < 0x9800) {
	416	else if (addr >= 0x9000 && addr < 0x9800)
	417	{
389	418	state->banks[2] = val & state->bank_mask;
390	419	state->cart.scc.active = ((val & 0x3f) == 0x3f);
391	420	slot_konami_scc_map (machine, state, 2);
392		if (msx1.state[0] == state) {
	421	if (msx1.state[0] == state)
	422	{
393	423	slot_konami_scc_map (machine, state, 0);
394	424	}
395	425	}
396		else if (state->cart.scc.active && addr >= 0x9800 && addr < 0xa000) {
	426	else if (state->cart.scc.active && addr >= 0x9800 && addr < 0xa000)
	427	{
397	428	const device_config *k051649 = devtag_get_device(space->machine, "k051649");
398	429	int offset = addr & 0xff;
399	430
400		if (offset < 0x80) {
	431	if (offset < 0x80)
	432	{
401	433	k051649_waveform_w (k051649, offset, val);
402	434	}
403		else if (offset < 0xa0) {
	435	else if (offset < 0xa0)
	436	{
404	437	offset &= 0xf;
405		if (offset < 0xa) {
	438	if (offset < 0xa)
	439	{
406	440	k051649_frequency_w (k051649, offset, val);
407	441	}
408		else if (offset < 0xf) {
	442	else if (offset < 0xf)
	443	{
409	444	k051649_volume_w (k051649, offset - 0xa, val);
410	445	}
411		else {
	446	else
	447	{
412	448	k051649_keyonoff_w (k051649, 0, val);
413	449	}
414	450	}
415	451	#if 0
416		else if (offset >= 0xe0) {
	452	else if (offset >= 0xe0)
	453	{
417	454	/* deformation register */
418	455	}
419	456	#endif
420	457	}
421		else if (addr >= 0xb000 && addr < 0xb800) {
	458	else if (addr >= 0xb000 && addr < 0xb800)
	459	{
422	460	state->banks[3] = val & state->bank_mask;
423	461	slot_konami_scc_map (machine, state, 2);
424		if (msx1.state[0] == state) {
	462	if (msx1.state[0] == state)
	463	{
425	464	slot_konami_scc_map (machine, state, 0);
426	465	}
427	466	}
r4576	r4577
431	470	{
432	471	int banks;
433	472
434		if (size > 0x200000) {
	473	if (size > 0x200000)
	474	{
435	475	logerror ("ascii8: warning: truncating to 2mb\n");
436	476	size = 0x200000;
437	477	return 1;
438	478	}
439	479	banks = size / 0x2000;
440		if (size != banks * 0x2000 || (~(banks - 1) % banks)) {
	480	if (size != banks * 0x2000 || (~(banks - 1) % banks))
	481	{
441	482	logerror ("ascii8: error: must be a 2 power of 8kb\n");
442	483	return 1;
443	484	}
r4576	r4577
458	499
459	500	MSX_SLOT_MAP(ascii8)
460	501	{
461		switch (page) {
	502	switch (page)
	503	{
462	504	case 0:
463	505	msx_cpu_setbank (machine, 1, msx1.empty);
464	506	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
481	523	{
482	524	int bank;
483	525
484		if (addr >= 0x6000 && addr < 0x8000) {
	526	if (addr >= 0x6000 && addr < 0x8000)
	527	{
485	528	bank = (addr / 0x800) & 3;
486	529
487	530	state->banks[bank] = val & state->bank_mask;
488		if (bank <= 1) {
	531	if (bank <= 1)
	532	{
489	533	slot_ascii8_map (machine, state, 1);
490	534	}
491		else if (msx1.state[2] == state) {
	535	else if (msx1.state[2] == state)
	536	{
492	537	slot_ascii8_map (machine, state, 2);
493	538	}
494	539	}
r4576	r4577
498	543	{
499	544	int banks;
500	545
501		if (size > 0x400000) {
	546	if (size > 0x400000)
	547	{
502	548	logerror ("ascii16: warning: truncating to 4mb\n");
503	549	size = 0x400000;
504	550	}
505	551	banks = size / 0x4000;
506		if (size != banks * 0x4000 || (~(banks - 1) % banks)) {
	552	if (size != banks * 0x4000 || (~(banks - 1) % banks))
	553	{
507	554	logerror ("ascii16: error: must be a 2 power of 16kb\n");
508	555	return 1;
509	556	}
r4576	r4577
527	574	{
528	575	UINT8 *mem;
529	576
530		switch (page) {
	577	switch (page)
	578	{
531	579	case 0:
532	580	msx_cpu_setbank (machine, 1, msx1.empty);
533	581	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
550	598
551	599	MSX_SLOT_WRITE(ascii16)
552	600	{
553		if (addr >= 0x6000 && addr < 0x6800) {
	601	if (addr >= 0x6000 && addr < 0x6800)
	602	{
554	603	state->banks[0] = val & state->bank_mask;
555	604	slot_ascii16_map (machine, state, 1);
556	605	}
557		else if (addr >= 0x7000 && addr < 0x7800) {
	606	else if (addr >= 0x7000 && addr < 0x7800)
	607	{
558	608	state->banks[1] = val & state->bank_mask;
559		if (msx1.state[2] == state) {
	609	if (msx1.state[2] == state)
	610	{
560	611	slot_ascii16_map (machine, state, 2);
561	612	}
562	613	}
r4576	r4577
568	619	int banks;
569	620
570	621	state->cart.sram.mem = auto_malloc (0x2000);
571		if (size > 0x100000) {
	622	if (size > 0x100000)
	623	{
572	624	logerror ("ascii8_sram: warning: truncating to 1mb\n");
573	625	size = 0x100000;
574	626	return 1;
575	627	}
576	628	banks = size / 0x2000;
577		if (size != banks * 0x2000 || (~(banks - 1) % banks)) {
	629	if (size != banks * 0x2000 || (~(banks - 1) % banks))
	630	{
578	631	logerror ("ascii8_sram: error: must be a 2 power of 8kb\n");
579	632	return 1;
580	633	}
r4576	r4577
585	638	state->bank_mask = banks - 1;
586	639	state->cart.sram.sram_mask = banks;
587	640	state->cart.sram.empty_mask = ~(banks | (banks - 1));
588		if (!state->sramfile) {
	641	if (!state->sramfile)
	642	{
589	643	state->sramfile = sramfile;
590	644	}
591	645
r4576	r4577
603	657	{
604	658	int bank = state->banks[bankno];
605	659
606		if (bank & state->cart.sram.empty_mask) {
	660	if (bank & state->cart.sram.empty_mask)
	661	{
607	662	return msx1.empty;
608	663	}
609		else if (bank & state->cart.sram.sram_mask) {
	664	else if (bank & state->cart.sram.sram_mask)
	665	{
610	666	return state->cart.sram.mem;
611	667	}
612		else {
	668	else
	669	{
613	670	return state->mem + (bank & state->bank_mask) * 0x2000;
614	671	}
615	672	}
616	673
617	674	MSX_SLOT_MAP(ascii8_sram)
618	675	{
619		switch (page) {
	676	switch (page)
	677	{
620	678	case 0:
621	679	msx_cpu_setbank (machine, 1, msx1.empty);
622	680	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
639	697	{
640	698	int bank;
641	699
642		if (addr >= 0x6000 && addr < 0x8000) {
	700	if (addr >= 0x6000 && addr < 0x8000)
	701	{
643	702	bank = (addr / 0x800) & 3;
644	703
645	704	state->banks[bank] = val;
646		if (bank <= 1) {
	705	if (bank <= 1)
	706	{
647	707	slot_ascii8_sram_map (machine, state, 1);
648	708	}
649		else if (msx1.state[2] == state) {
	709	else if (msx1.state[2] == state)
	710	{
650	711	slot_ascii8_sram_map (machine, state, 2);
651	712	}
652	713	}
653		if (addr >= 0x8000 && addr < 0xc000) {
	714	if (addr >= 0x8000 && addr < 0xc000)
	715	{
654	716	bank = addr < 0xa000 ? 2 : 3;
655	717	if (!(state->banks[bank] & state->cart.sram.empty_mask) &&
656		(state->banks[bank] & state->cart.sram.sram_mask)) {
	718	(state->banks[bank] & state->cart.sram.sram_mask))
	719	{
657	720	state->cart.sram.mem[addr & 0x1fff] = val;
658	721	}
659	722	}
r4576	r4577
664	727	file_error filerr;
665	728	mame_file *f;
666	729
667		if (!state->sramfile) {
	730	if (!state->sramfile)
	731	{
668	732	logerror ("ascii8_sram: error: no sram filename provided\n");
669	733	return 1;
670	734	}
r4576	r4577
672	736	filerr = mame_fopen(SEARCHPATH_MEMCARD, state->sramfile, OPEN_FLAG_READ, &f);
673	737	if (filerr == FILERR_NONE)
674	738	{
675		if (mame_fread (f, state->cart.sram.mem, 0x2000) == 0x2000) {
	739	if (mame_fread (f, state->cart.sram.mem, 0x2000) == 0x2000)
	740	{
676	741	mame_fclose (f);
677	742	logerror ("ascii8_sram: info: sram loaded\n");
678	743	return 0;
r4576	r4577
693	758	file_error filerr;
694	759	mame_file *f;
695	760
696		if (!state->sramfile) {
	761	if (!state->sramfile)
	762	{
697	763	return 0;
698	764	}
699	765
r4576	r4577
719	785
720	786	state->cart.sram.mem = auto_malloc (0x4000);
721	787
722		if (size > 0x200000) {
	788	if (size > 0x200000)
	789	{
723	790	logerror ("ascii16_sram: warning: truncating to 2mb\n");
724	791	size = 0x200000;
725	792	}
726	793	banks = size / 0x4000;
727		if (size != banks * 0x4000 || (~(banks - 1) % banks)) {
	794	if (size != banks * 0x4000 || (~(banks - 1) % banks))
	795	{
728	796	logerror ("ascii16_sram: error: must be a 2 power of 16kb\n");
729	797	return 1;
730	798	}
r4576	r4577
736	804	state->bank_mask = banks - 1;
737	805	state->cart.sram.sram_mask = banks;
738	806	state->cart.sram.empty_mask = ~(banks | (banks - 1));
739		if (!state->sramfile) {
	807	if (!state->sramfile)
	808	{
740	809	state->sramfile = sramfile;
741	810	}
742	811
r4576	r4577
754	823	{
755	824	int bank = state->banks[bankno];
756	825
757		if (bank & state->cart.sram.empty_mask) {
	826	if (bank & state->cart.sram.empty_mask)
	827	{
758	828	return msx1.empty;
759	829	}
760		else if (bank & state->cart.sram.sram_mask) {
	830	else if (bank & state->cart.sram.sram_mask)
	831	{
761	832	return state->cart.sram.mem;
762	833	}
763		else {
	834	else
	835	{
764	836	return state->mem + (bank & state->bank_mask) * 0x4000;
765	837	}
766	838	}
r4576	r4577
769	841	{
770	842	UINT8 *mem;
771	843
772		switch (page) {
	844	switch (page)
	845	{
773	846	case 0:
774	847	msx_cpu_setbank (machine, 1, msx1.empty);
775	848	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
792	865
793	866	MSX_SLOT_WRITE(ascii16_sram)
794	867	{
795		if (addr >= 0x6000 && addr < 0x6800) {
	868	if (addr >= 0x6000 && addr < 0x6800)
	869	{
796	870	state->banks[0] = val;
797	871	slot_ascii16_sram_map (machine, state, 1);
798	872	}
799		else if (addr >= 0x7000 && addr < 0x7800) {
	873	else if (addr >= 0x7000 && addr < 0x7800)
	874	{
800	875	state->banks[1] = val;
801		if (msx1.state[2] == state) {
	876	if (msx1.state[2] == state)
	877	{
802	878	slot_ascii16_sram_map (machine, state, 2);
803	879	}
804	880	}
805		else if (addr >= 0x8000 && addr < 0xc000) {
	881	else if (addr >= 0x8000 && addr < 0xc000)
	882	{
806	883	if (!(state->banks[1] & state->cart.sram.empty_mask) &&
807		(state->banks[1] & state->cart.sram.sram_mask)) {
	884	(state->banks[1] & state->cart.sram.sram_mask))
	885	{
808	886	int offset, i;
809	887
810	888	offset = addr & 0x07ff;
811		for (i=0; i<8; i++) {
	889	for (i=0; i<8; i++)
	890	{
812	891	state->cart.sram.mem[offset] = val;
813	892	offset += 0x0800;
814	893	}
r4576	r4577
822	901	mame_file *f;
823	902	UINT8 *p;
824	903
825		if (!state->sramfile) {
	904	if (!state->sramfile)
	905	{
826	906	logerror ("ascii16_sram: error: no sram filename provided\n");
827	907	return 1;
828	908	}
r4576	r4577
832	912	{
833	913	p = state->cart.sram.mem;
834	914
835		if (mame_fread (f, state->cart.sram.mem, 0x200) == 0x200) {
	915	if (mame_fread (f, state->cart.sram.mem, 0x200) == 0x200)
	916	{
836	917	int /*offset,*/ i;
837	918
838	919	mame_fclose (f);
839	920
840	921	//offset = 0;
841		for (i=0; i<7; i++) {
	922	for (i=0; i<7; i++)
	923	{
842	924	memcpy (p + 0x800, p, 0x800);
843	925	p += 0x800;
844	926	}
r4576	r4577
862	944	file_error filerr;
863	945	mame_file *f;
864	946
865		if (!state->sramfile) {
	947	if (!state->sramfile)
	948	{
866	949	return 0;
867	950	}
868	951
r4576	r4577
883	966
884	967	MSX_SLOT_INIT(rtype)
885	968	{
886		if (!(size == 0x60000 || size == 0x80000)) {
	969	if (!(size == 0x60000 || size == 0x80000))
	970	{
887	971	logerror ("rtype: error: rom file should be exactly 384kb\n");
888	972	return 1;
889	973	}
r4576	r4577
904	988	{
905	989	UINT8 *mem;
906	990
907		switch (page) {
	991	switch (page)
	992	{
908	993	case 0:
909	994	msx_cpu_setbank (machine, 1, msx1.empty);
910	995	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
927	1012
928	1013	MSX_SLOT_WRITE(rtype)
929	1014	{
930		if (addr >= 0x7000 && addr < 0x8000) {
	1015	if (addr >= 0x7000 && addr < 0x8000)
	1016	{
931	1017	int data ;
932	1018
933		if (val & 0x10) {
	1019	if (val & 0x10)
	1020	{
934	1021	data = 0x10 | (val & 7);
935	1022	}
936		else {
	1023	else
	1024	{
937	1025	data = val & 0x0f;
938	1026	}
939	1027	state->banks[0] = data;
940		if (msx1.state[2] == state) {
	1028	if (msx1.state[2] == state)
	1029	{
941	1030	slot_rtype_map (machine, state, 2);
942	1031	}
943	1032	}
r4576	r4577
948	1037	UINT8 *p;
949	1038	static const char sramfile[] = "GameMaster2";
950	1039
951		if (size != 0x20000) {
	1040	if (size != 0x20000)
	1041	{
952	1042	logerror ("gmaster2: error: rom file should be 128kb\n");
953	1043	return 1;
954	1044	}
r4576	r4577
959	1049	p = auto_malloc (0x4000);
960	1050	memset (p, 0, 0x4000);
961	1051	state->cart.sram.mem = p;
962		if (!state->sramfile) {
	1052	if (!state->sramfile)
	1053	{
963	1054	state->sramfile = sramfile;
964	1055	}
965	1056
r4576	r4577
970	1061	{
971	1062	int i;
972	1063
973		for (i=0; i<4; i++) {
	1064	for (i=0; i<4; i++)
	1065	{
974	1066	state->banks[i] = i;
975	1067	}
976	1068	}
977	1069
978	1070	MSX_SLOT_MAP(gmaster2)
979	1071	{
980		switch (page) {
	1072	switch (page)
	1073	{
981	1074	case 0:
982	1075	case 1:
983	1076	msx_cpu_setbank (machine, 1 + page * 2, state->mem); /* bank 0 is hardwired */
984		if (state->banks[1] > 15) {
	1077	if (state->banks[1] > 15)
	1078	{
985	1079	msx_cpu_setbank (machine, 2 + page * 2, state->cart.sram.mem +
986	1080	(state->banks[1] - 16) * 0x2000);
987	1081	}
988		else {
	1082	else
	1083	{
989	1084	msx_cpu_setbank (machine, 2 + page * 2, state->mem + state->banks[1] * 0x2000);
990	1085	}
991	1086	break;
992	1087	case 2:
993	1088	case 3:
994		if (state->banks[2] > 15) {
	1089	if (state->banks[2] > 15)
	1090	{
995	1091	msx_cpu_setbank (machine, 5 + page * 2, state->cart.sram.mem +
996	1092	(state->banks[2] - 16) * 0x2000);
997	1093	}
998		else {
	1094	else
	1095	{
999	1096	msx_cpu_setbank (machine, 5 + page * 2, state->mem + state->banks[2] * 0x2000);
1000	1097	}
1001		if (state->banks[3] > 15) {
	1098	if (state->banks[3] > 15)
	1099	{
1002	1100	msx_cpu_setbank (machine, 6 + page * 2, state->cart.sram.mem +
1003	1101	(state->banks[3] - 16) * 0x2000);
1004	1102	}
1005		else {
	1103	else
	1104	{
1006	1105	msx_cpu_setbank (machine, 6 + page * 2, state->mem + state->banks[3] * 0x2000);
1007	1106	}
1008	1107	break;
r4576	r4577
1011	1110
1012	1111	MSX_SLOT_WRITE(gmaster2)
1013	1112	{
1014		if (addr >= 0x6000 && addr < 0x7000) {
1015		if (val & 0x10) {
	1113	if (addr >= 0x6000 && addr < 0x7000)
	1114	{
	1115	if (val & 0x10)
	1116	{
1016	1117	val = val & 0x20 ? 17 : 16;
1017	1118	}
1018		else {
	1119	else
	1120	{
1019	1121	val = val & 15;
1020	1122	}
1021	1123	state->banks[1] = val;
1022	1124	slot_gmaster2_map (machine, state, 1);
1023		if (msx1.state[0] == state) {
	1125	if (msx1.state[0] == state)
	1126	{
1024	1127	slot_gmaster2_map (machine, state, 0);
1025	1128	}
1026	1129	}
1027		else if (addr >= 0x8000 && addr < 0x9000) {
1028		if (val & 0x10) {
	1130	else if (addr >= 0x8000 && addr < 0x9000)
	1131	{
	1132	if (val & 0x10)
	1133	{
1029	1134	val = val & 0x20 ? 17 : 16;
1030	1135	}
1031		else {
	1136	else
	1137	{
1032	1138	val = val & 15;
1033	1139	}
1034	1140	state->banks[2] = val;
1035	1141	slot_gmaster2_map (machine, state, 2);
1036		if (msx1.state[3] == state) {
	1142	if (msx1.state[3] == state)
	1143	{
1037	1144	slot_gmaster2_map (machine, state, 3);
1038	1145	}
1039	1146	}
1040		else if (addr >= 0xa000 && addr < 0xb000) {
1041		if (val & 0x10) {
	1147	else if (addr >= 0xa000 && addr < 0xb000)
	1148	{
	1149	if (val & 0x10)
	1150	{
1042	1151	val = val & 0x20 ? 17 : 16;
1043	1152	}
1044		else {
	1153	else
	1154	{
1045	1155	val = val & 15;
1046	1156	}
1047	1157	state->banks[3] = val;
1048	1158	slot_gmaster2_map (machine, state, 2);
1049		if (msx1.state[3] == state) {
	1159	if (msx1.state[3] == state)
	1160	{
1050	1161	slot_gmaster2_map (machine, state, 3);
1051	1162	}
1052	1163	}
1053		else if (addr >= 0xb000 && addr < 0xc000) {
	1164	else if (addr >= 0xb000 && addr < 0xc000)
	1165	{
1054	1166	addr &= 0x0fff;
1055		switch (state->banks[3]) {
	1167	switch (state->banks[3])
	1168	{
1056	1169	case 16:
1057	1170	state->cart.sram.mem[addr] = val;
1058	1171	state->cart.sram.mem[addr + 0x1000] = val;
r4576	r4577
1075	1188	filerr = mame_fopen(SEARCHPATH_MEMCARD, state->sramfile, OPEN_FLAG_READ, &f);
1076	1189	if (filerr == FILERR_NONE)
1077	1190	{
1078		if (mame_fread (f, p + 0x1000, 0x2000) == 0x2000) {
	1191	if (mame_fread (f, p + 0x1000, 0x2000) == 0x2000)
	1192	{
1079	1193	memcpy (p, p + 0x1000, 0x1000);
1080	1194	memcpy (p + 0x3000, p + 0x2000, 0x1000);
1081	1195	mame_fclose (f);
r4576	r4577
1115	1229
1116	1230	MSX_SLOT_INIT(diskrom)
1117	1231	{
1118		if (size != 0x4000) {
	1232	if (size != 0x4000)
	1233	{
1119	1234	logerror ("diskrom: error: the diskrom should be 16kb\n");
1120	1235	return 1;
1121	1236	}
r4576	r4577
1136	1251	static READ8_HANDLER (msx_diskrom_page1_r)
1137	1252	{
1138	1253	const device_config *fdc = devtag_get_device(space->machine, "wd179x");
1139		switch (offset) {
	1254	switch (offset)
	1255	{
1140	1256	case 0: return wd17xx_status_r (fdc, 0);
1141	1257	case 1: return wd17xx_track_r (fdc, 0);
1142	1258	case 2: return wd17xx_sector_r (fdc, 0);
r4576	r4577
1150	1266	static READ8_HANDLER (msx_diskrom_page2_r)
1151	1267	{
1152	1268	const device_config *fdc = devtag_get_device(space->machine, "wd179x");
1153		if (offset >= 0x7f8) {
1154		switch (offset) {
	1269	if (offset >= 0x7f8)
	1270	{
	1271	switch (offset)
	1272	{
1155	1273	case 0x7f8:
1156	1274	return wd17xx_status_r (fdc, 0);
1157	1275	case 0x7f9:
r4576	r4577
1166	1284	return msx1.state[2]->mem[offset + 0x3800];
1167	1285	}
1168	1286	}
1169		else {
	1287	else
	1288	{
1170	1289	return 0xff;
1171	1290	}
1172	1291	}
1173	1292
1174	1293	MSX_SLOT_MAP(diskrom)
1175	1294	{
1176		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
1177		switch (page) {
	1295	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	1296	switch (page)
	1297	{
1178	1298	case 0:
1179	1299	msx_cpu_setbank (machine, 1, msx1.empty);
1180	1300	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
1199	1319	MSX_SLOT_WRITE(diskrom)
1200	1320	{
1201	1321	const device_config *fdc = devtag_get_device(machine, "wd179x");
1202		if (addr >= 0xa000 && addr < 0xc000) {
	1322	if (addr >= 0xa000 && addr < 0xc000)
	1323	{
1203	1324	addr -= 0x4000;
1204	1325	}
1205		switch (addr) {
	1326	switch (addr)
	1327	{
1206	1328	case 0x7ff8:
1207	1329	wd17xx_command_w (fdc, 0, val);
1208	1330	break;
r4576	r4577
1221	1343	break;
1222	1344	case 0x7ffd:
1223	1345	wd17xx_set_drive (fdc,val & 1);
1224		if ((state->mem[0x3ffd] ^ val) & 0x40) {
	1346	if ((state->mem[0x3ffd] ^ val) & 0x40)
	1347	{
1225	1348	set_led_status (0, !(val & 0x40));
1226	1349	}
1227	1350	state->mem[0x3ffd] = (val | 0x7c) & ~0x04;
r4576	r4577
1231	1354
1232	1355	MSX_SLOT_INIT(diskrom2)
1233	1356	{
1234		if (size != 0x4000) {
	1357	if (size != 0x4000)
	1358	{
1235	1359	logerror ("diskrom2: error: the diskrom2 should be 16kb\n");
1236	1360	return 1;
1237	1361	}
r4576	r4577
1252	1376	static READ8_HANDLER (msx_diskrom2_page1_r)
1253	1377	{
1254	1378	const device_config *fdc = devtag_get_device(space->machine, "wd179x");
1255		switch (offset) {
	1379	switch (offset)
	1380	{
1256	1381	case 0: return wd17xx_status_r(fdc, 0);
1257	1382	case 1: return wd17xx_track_r(fdc, 0);
1258	1383	case 2: return wd17xx_sector_r(fdc, 0);
r4576	r4577
1266	1391	static  READ8_HANDLER (msx_diskrom2_page2_r)
1267	1392	{
1268	1393	const device_config *fdc = devtag_get_device(space->machine, "wd179x");
1269		if (offset >= 0x7b8) {
1270		switch (offset) {
	1394	if (offset >= 0x7b8)
	1395	{
	1396	switch (offset)
	1397	{
1271	1398	case 0x7b8:
1272	1399	return wd17xx_status_r (fdc, 0);
1273	1400	case 0x7b9:
r4576	r4577
1282	1409	return msx1.state[2]->mem[offset + 0x3800];
1283	1410	}
1284	1411	}
1285		else {
	1412	else
	1413	{
1286	1414	return 0xff;
1287	1415	}
1288	1416	}
1289	1417
1290	1418	MSX_SLOT_MAP(diskrom2)
1291	1419	{
1292		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
1293		switch (page) {
	1420	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	1421	switch (page)
	1422	{
1294	1423	case 0:
1295	1424	msx_cpu_setbank (machine, 1, msx1.empty);
1296	1425	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
1314	1443	MSX_SLOT_WRITE(diskrom2)
1315	1444	{
1316	1445	const device_config *fdc = devtag_get_device(machine, "wd179x");
1317		if (addr >= 0xa000 && addr < 0xc000) {
	1446	if (addr >= 0xa000 && addr < 0xc000)
	1447	{
1318	1448	addr -= 0x4000;
1319	1449	}
1320		switch (addr) {
	1450	switch (addr)
	1451	{
1321	1452	case 0x7fb8:
1322	1453	wd17xx_command_w (fdc, 0, val);
1323	1454	break;
r4576	r4577
1334	1465	wd17xx_set_side (fdc,val & 1);
1335	1466	state->mem[0x3fbc] = val | 0xfe;
1336	1467	wd17xx_set_drive (fdc,val & 1);
1337		if ((state->mem[0x3fbc] ^ val) & 0x40) {
	1468	if ((state->mem[0x3fbc] ^ val) & 0x40)
	1469	{
1338	1470	set_led_status (0, !(val & 0x40));
1339	1471	}
1340	1472	state->mem[0x3fbc] = (val | 0x7c) & ~0x04;
r4576	r4577
1344	1476
1345	1477	MSX_SLOT_INIT(synthesizer)
1346	1478	{
1347		if (size != 0x8000) {
	1479	if (size != 0x8000)
	1480	{
1348	1481	logerror ("synthesizer: error: rom file must be 32kb\n");
1349	1482	return 1;
1350	1483	}
r4576	r4577
1362	1495
1363	1496	MSX_SLOT_MAP(synthesizer)
1364	1497	{
1365		switch (page) {
	1498	switch (page)
	1499	{
1366	1500	case 0:
1367	1501	msx_cpu_setbank (machine, 1, msx1.empty);
1368	1502	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
1383	1517
1384	1518	MSX_SLOT_WRITE(synthesizer)
1385	1519	{
1386		if (addr >= 0x4000 && addr < 0x8000 && !(addr & 0x0010)) {
	1520	if (addr >= 0x4000 && addr < 0x8000 && !(addr & 0x0010))
	1521	{
1387	1522	dac_data_w (devtag_get_device(machine, "dac"), val);
1388	1523	}
1389	1524	}
1390	1525
1391	1526	MSX_SLOT_INIT(majutsushi)
1392	1527	{
1393		if (size != 0x20000) {
	1528	if (size != 0x20000)
	1529	{
1394	1530	logerror ("majutsushi: error: rom file must be 128kb\n");
1395	1531	return 1;
1396	1532	}
r4576	r4577
1406	1542	{
1407	1543	int i;
1408	1544
1409		for (i=0; i<4; i++) {
	1545	for (i=0; i<4; i++)
	1546	{
1410	1547	state->banks[i] = i;
1411	1548	}
1412	1549	}
1413	1550
1414	1551	MSX_SLOT_MAP(majutsushi)
1415	1552	{
1416		switch (page) {
	1553	switch (page)
	1554	{
1417	1555	case 0:
1418	1556	msx_cpu_setbank (machine, 1, state->mem + state->banks[0] * 0x2000);
1419	1557	msx_cpu_setbank (machine, 2, state->mem + state->banks[1] * 0x2000);
r4576	r4577
1435	1573
1436	1574	MSX_SLOT_WRITE(majutsushi)
1437	1575	{
1438		if (addr >= 0x5000 && addr < 0x6000) {
	1576	if (addr >= 0x5000 && addr < 0x6000)
	1577	{
1439	1578	dac_data_w (devtag_get_device(machine, "dac"), val);
1440	1579	}
1441		else if (addr >= 0x6000 && addr < 0x8000) {
	1580	else if (addr >= 0x6000 && addr < 0x8000)
	1581	{
1442	1582	state->banks[1] = val & 0x0f;
1443	1583	slot_majutsushi_map (machine, state, 1);
1444		if (msx1.state[0] == state) {
	1584	if (msx1.state[0] == state)
	1585	{
1445	1586	slot_konami_map (machine, state, 0);
1446	1587	}
1447	1588	}
1448		else if (addr >= 0x8000 && addr < 0xc000) {
	1589	else if (addr >= 0x8000 && addr < 0xc000)
	1590	{
1449	1591	state->banks[addr < 0xa000 ? 2 : 3] = val & 0x0f;
1450	1592	slot_majutsushi_map (machine, state, 2);
1451		if (msx1.state[3] == state) {
	1593	if (msx1.state[3] == state)
	1594	{
1452	1595	slot_konami_map (machine, state, 3);
1453	1596	}
1454	1597	}
r4576	r4577
1460	1603	UINT8 *p;
1461	1604	int banks;
1462	1605
1463		if (size > 0x400000) {
	1606	if (size > 0x400000)
	1607	{
1464	1608	logerror ("fmpac: warning: truncating rom to 4mb\n");
1465	1609	size = 0x400000;
1466	1610	}
1467	1611	banks = size / 0x4000;
1468		if (size != banks * 0x4000 || (~(banks - 1) % banks)) {
	1612	if (size != banks * 0x4000 || (~(banks - 1) % banks))
	1613	{
1469	1614	logerror ("fmpac: error: must be a 2 power of 16kb\n");
1470	1615	return 1;
1471	1616	}
1472	1617
1473		if (!strncmp ((char*)mem + 0x18, "PAC2", 4)) {
	1618	if (!strncmp ((char*)mem + 0x18, "PAC2", 4))
	1619	{
1474	1620	state->cart.fmpac.sram_support = 1;
1475	1621	p = auto_malloc (0x4000);
1476	1622	memset (p, 0, 0x2000);
1477	1623	memset (p + 0x2000, 0xff, 0x2000);
1478	1624	state->cart.fmpac.mem = p;
1479	1625	}
1480		else {
	1626	else
	1627	{
1481	1628	state->cart.fmpac.sram_support = 0;
1482	1629	state->cart.fmpac.mem = NULL;
1483	1630	}
r4576	r4577
1486	1633	state->size = size;
1487	1634	state->mem = mem;
1488	1635	state->bank_mask = banks - 1;
1489		if (!state->sramfile) {
	1636	if (!state->sramfile)
	1637	{
1490	1638	state->sramfile = sramfile;
1491	1639	}
1492	1640
r4576	r4577
1501	1649	state->cart.fmpac.sram_active = 0;
1502	1650	state->cart.fmpac.opll_active = 0;
1503	1651	msx1.opll_active = 0;
1504		for (i=0; i<=state->bank_mask; i++) {
	1652	for (i=0; i<=state->bank_mask; i++)
	1653	{
1505	1654	state->mem[0x3ff6 + i * 0x4000] = 0;
1506	1655	}
1507	1656
r4576	r4577
1517	1666
1518	1667	MSX_SLOT_MAP(fmpac)
1519	1668	{
1520		if (page == 1) {
1521		if (state->cart.fmpac.sram_active) {
	1669	if (page == 1)
	1670	{
	1671	if (state->cart.fmpac.sram_active)
	1672	{
1522	1673	msx_cpu_setbank (machine, 3, state->cart.fmpac.mem);
1523	1674	msx_cpu_setbank (machine, 4, state->cart.fmpac.mem + 0x2000);
1524	1675	}
1525		else {
	1676	else
	1677	{
1526	1678	msx_cpu_setbank (machine, 3, state->mem + state->banks[0] * 0x4000);
1527	1679	msx_cpu_setbank (machine, 4, state->mem + state->banks[0] * 0x4000 + 0x2000);
1528	1680	}
1529	1681	}
1530		else {
	1682	else
	1683	{
1531	1684	msx_cpu_setbank (machine, page * 2 + 1, msx1.empty);
1532	1685	msx_cpu_setbank (machine, page * 2 + 2, msx1.empty);
1533	1686	}
r4576	r4577
1535	1688
1536	1689	MSX_SLOT_WRITE(fmpac)
1537	1690	{
1538		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	1691	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
1539	1692	int i, data;
1540	1693
1541		if (addr >= 0x4000 && addr < 0x6000 && state->cart.fmpac.sram_support) {
1542		if (state->cart.fmpac.sram_active || addr >= 0x5ffe) {
	1694	if (addr >= 0x4000 && addr < 0x6000 && state->cart.fmpac.sram_support)
	1695	{
	1696	if (state->cart.fmpac.sram_active || addr >= 0x5ffe)
	1697	{
1543	1698	state->cart.fmpac.mem[addr & 0x1fff] = val;
1544	1699	}
1545	1700
r4576	r4577
1548	1703	state->cart.fmpac.mem[0x1fff] == 0x69);
1549	1704	}
1550	1705
1551		switch (addr) {
	1706	switch (addr)
	1707	{
1552	1708	case 0x7ff4:
1553		if (state->cart.fmpac.opll_active) {
	1709	if (state->cart.fmpac.opll_active)
	1710	{
1554	1711	ym2413_w (devtag_get_device(space->machine, "ay8910"), 0, val);
1555	1712	}
1556	1713	break;
1557	1714	case 0x7ff5:
1558		if (state->cart.fmpac.opll_active) {
	1715	if (state->cart.fmpac.opll_active)
	1716	{
1559	1717	ym2413_w (devtag_get_device(space->machine, "ay8910"), 1, val);
1560	1718	}
1561	1719	break;
1562	1720	case 0x7ff6:
1563	1721	data = val & 0x11;
1564		for (i=0; i<=state->bank_mask; i++) {
	1722	for (i=0; i<=state->bank_mask; i++)
	1723	{
1565	1724	state->mem[0x3ff6 + i * 0x4000] = data;
1566	1725	}
1567	1726	state->cart.fmpac.mem[0x3ff6] = data;
1568	1727	state->cart.fmpac.opll_active = val & 1;
1569		if ((msx1.opll_active ^ val) & 1) {
	1728	if ((msx1.opll_active ^ val) & 1)
	1729	{
1570	1730	logerror ("FM-PAC: OPLL %sactivated\n", val & 1 ? "" : "de");
1571	1731	}
1572	1732	msx1.opll_active = val & 1;
r4576	r4577
1588	1748	mame_file *f;
1589	1749	char buf[PAC_HEADER_LEN];
1590	1750
1591		if (!state->cart.fmpac.sram_support) {
	1751	if (!state->cart.fmpac.sram_support)
	1752	{
1592	1753	logerror ("Your fmpac.rom does not support sram\n");
1593	1754	return 1;
1594	1755	}
1595	1756
1596		if (!state->sramfile) {
	1757	if (!state->sramfile)
	1758	{
1597	1759	logerror ("No sram filename provided\n");
1598	1760	return 1;
1599	1761	}
r4576	r4577
1603	1765	{
1604	1766	if ((mame_fread (f, buf, PAC_HEADER_LEN) == PAC_HEADER_LEN) &&
1605	1767	!strncmp (buf, PAC_HEADER, PAC_HEADER_LEN) &&
1606		mame_fread (f, state->cart.fmpac.mem, 0x1ffe)) {
	1768	mame_fread (f, state->cart.fmpac.mem, 0x1ffe))
	1769	{
1607	1770	logerror ("fmpac: info: sram loaded\n");
1608	1771	mame_fclose (f);
1609	1772	return 0;
1610	1773	}
1611		else {
	1774	else
	1775	{
1612	1776	logerror ("fmpac: warning: failed to load sram\n");
1613	1777	mame_fclose (f);
1614	1778	return 1;
r4576	r4577
1624	1788	file_error filerr;
1625	1789	mame_file *f;
1626	1790
1627		if (!state->cart.fmpac.sram_support || !state->sramfile) {
	1791	if (!state->cart.fmpac.sram_support || !state->sramfile)
	1792	{
1628	1793	return 0;
1629	1794	}
1630	1795
r4576	r4577
1632	1797	if (filerr == FILERR_NONE)
1633	1798	{
1634	1799	if ((mame_fwrite (f, PAC_HEADER, PAC_HEADER_LEN) == PAC_HEADER_LEN) &&
1635		(mame_fwrite (f, state->cart.fmpac.mem, 0x1ffe) == 0x1ffe)) {
	1800	(mame_fwrite (f, state->cart.fmpac.mem, 0x1ffe) == 0x1ffe))
	1801	{
1636	1802	logerror ("fmpac: info: sram saved\n");
1637	1803	mame_fclose (f);
1638	1804	return 0;
1639	1805	}
1640		else {
	1806	else
	1807	{
1641	1808	logerror ("fmpac: warning: sram save to file failed\n");
1642	1809	mame_fclose (f);
1643	1810	return 1;
r4576	r4577
1651	1818
1652	1819	MSX_SLOT_INIT(superloadrunner)
1653	1820	{
1654		if (size != 0x20000) {
	1821	if (size != 0x20000)
	1822	{
1655	1823	logerror ("superloadrunner: error: rom file should be exactly "
1656	1824	"128kb\n");
1657	1825	return 1;
r4576	r4577
1672	1840
1673	1841	MSX_SLOT_MAP(superloadrunner)
1674	1842	{
1675		if (page == 2) {
	1843	if (page == 2)
	1844	{
1676	1845	UINT8 *mem = state->mem +
1677	1846	(msx1.superloadrunner_bank & state->bank_mask) * 0x4000;
1678	1847
1679	1848	msx_cpu_setbank (machine, 5, mem);
1680	1849	msx_cpu_setbank (machine, 6, mem + 0x2000);
1681	1850	}
1682		else {
	1851	else
	1852	{
1683	1853	msx_cpu_setbank (machine, page * 2 + 1, msx1.empty);
1684	1854	msx_cpu_setbank (machine, page * 2 + 2, msx1.empty);
1685	1855	}
r4576	r4577
1687	1857
1688	1858	MSX_SLOT_INIT(crossblaim)
1689	1859	{
1690		if (size != 0x10000) {
	1860	if (size != 0x10000)
	1861	{
1691	1862	logerror ("crossblaim: error: rom file should be exactly 64kb\n");
1692	1863	return 1;
1693	1864	}
r4576	r4577
1709	1880
1710	1881	/* This might look odd, but it's what happens on the real cartridge */
1711	1882
1712		switch (page) {
	1883	switch (page)
	1884	{
1713	1885	case 0:
1714	1886	if (state->banks[0] < 2){
1715	1887	mem = state->mem + state->banks[0] * 0x4000;
1716	1888	msx_cpu_setbank (machine, 1, mem);
1717	1889	msx_cpu_setbank (machine, 2, mem + 0x2000);
1718		} else {
	1890	}
	1891	else
	1892	{
1719	1893	msx_cpu_setbank (machine, 1, msx1.empty);
1720	1894	msx_cpu_setbank (machine, 2, msx1.empty);
1721	1895	}
r4576	r4577
1734	1908	mem = state->mem + state->banks[0] * 0x4000;
1735	1909	msx_cpu_setbank (machine, 7, mem);
1736	1910	msx_cpu_setbank (machine, 8, mem + 0x2000);
1737		} else {
	1911	}
	1912	else
	1913	{
1738	1914	msx_cpu_setbank (machine, 7, msx1.empty);
1739	1915	msx_cpu_setbank (machine, 8, msx1.empty);
1740	1916	}
r4576	r4577
1748	1924	if (!block) block = 1;
1749	1925	state->banks[0] = block;
1750	1926
1751		if (msx1.state[0] == state) {
	1927	if (msx1.state[0] == state)
	1928	{
1752	1929	slot_crossblaim_map (machine, state, 0);
1753	1930	}
1754		if (msx1.state[2] == state) {
	1931	if (msx1.state[2] == state)
	1932	{
1755	1933	slot_crossblaim_map (machine, state, 2);
1756	1934	}
1757		if (msx1.state[3] == state) {
	1935	if (msx1.state[3] == state)
	1936	{
1758	1937	slot_crossblaim_map (machine, state, 3);
1759	1938	}
1760	1939	}
r4576	r4577
1763	1942	{
1764	1943	int banks;
1765	1944
1766		if (size > 0x200000) {
	1945	if (size > 0x200000)
	1946	{
1767	1947	logerror ("korean-80in1: warning: truncating to 2mb\n");
1768	1948	size = 0x200000;
1769	1949	}
1770	1950	banks = size / 0x2000;
1771		if (size != banks * 0x2000 || (~(banks - 1) % banks)) {
	1951	if (size != banks * 0x2000 || (~(banks - 1) % banks))
	1952	{
1772	1953	logerror ("korean-80in1: error: must be a 2 power of 8kb\n");
1773	1954	return 1;
1774	1955	}
r4576	r4577
1784	1965	{
1785	1966	int i;
1786	1967
1787		for (i=0; i<4; i++) {
	1968	for (i=0; i<4; i++)
	1969	{
1788	1970	state->banks[i] = i;
1789	1971	}
1790	1972	}
1791	1973
1792	1974	MSX_SLOT_MAP(korean80in1)
1793	1975	{
1794		switch (page) {
	1976	switch (page)
	1977	{
1795	1978	case 0:
1796	1979	msx_cpu_setbank (machine, 1, msx1.empty);
1797	1980	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
1814	1997	{
1815	1998	int bank;
1816	1999
1817		if (addr >= 0x4000 && addr < 0x4004) {
	2000	if (addr >= 0x4000 && addr < 0x4004)
	2001	{
1818	2002	bank = addr & 3;
1819	2003
1820	2004	state->banks[bank] = val & state->bank_mask;
1821		if (bank <= 1) {
	2005	if (bank <= 1)
	2006	{
1822	2007	slot_korean80in1_map (machine, state, 1);
1823	2008	}
1824		else if (msx1.state[2] == state) {
	2009	else if (msx1.state[2] == state)
	2010	{
1825	2011	slot_korean80in1_map (machine, state, 2);
1826	2012	}
1827	2013	}
r4576	r4577
1831	2017	{
1832	2018	int banks;
1833	2019
1834		if (size > 0x100000) {
	2020	if (size > 0x100000)
	2021	{
1835	2022	logerror ("korean-90in1: warning: truncating to 1mb\n");
1836	2023	size = 0x100000;
1837	2024	}
1838	2025	banks = size / 0x4000;
1839		if (size != banks * 0x4000 || (~(banks - 1) % banks)) {
	2026	if (size != banks * 0x4000 || (~(banks - 1) % banks))
	2027	{
1840	2028	logerror ("korean-90in1: error: must be a 2 power of 16kb\n");
1841	2029	return 1;
1842	2030	}
r4576	r4577
1860	2048	mem = state->mem +
1861	2049	((msx1.korean90in1_bank & mask) & state->bank_mask) * 0x4000;
1862	2050
1863		switch (page) {
	2051	switch (page)
	2052	{
1864	2053	case 0:
1865	2054	msx_cpu_setbank (machine, 1, msx1.empty);
1866	2055	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
1870	2059	msx_cpu_setbank (machine, 4, mem + 0x2000);
1871	2060	break;
1872	2061	case 2:
1873		switch (msx1.korean90in1_bank & 0xc0) {
	2062	switch (msx1.korean90in1_bank & 0xc0)
	2063	{
1874	2064	case 0x80: /* 32 kb mode */
1875	2065	mem += 0x4000;
1876	2066	default: /* ie. 0x00 and 0x40: same memory as page 1 */
r4576	r4577
1893	2083	{
1894	2084	int banks;
1895	2085
1896		if (size > 0x400000) {
	2086	if (size > 0x400000)
	2087	{
1897	2088	logerror ("korean-126in1: warning: truncating to 4mb\n");
1898	2089	size = 0x400000;
1899	2090	}
1900	2091	banks = size / 0x4000;
1901		if (size != banks * 0x4000 || (~(banks - 1) % banks)) {
	2092	if (size != banks * 0x4000 || (~(banks - 1) % banks))
	2093	{
1902	2094	logerror ("korean-126in1: error: must be a 2 power of 16kb\n");
1903	2095	return 1;
1904	2096	}
r4576	r4577
1922	2114	{
1923	2115	UINT8 *mem;
1924	2116
1925		switch (page) {
	2117	switch (page)
	2118	{
1926	2119	case 0:
1927	2120	msx_cpu_setbank (machine, 1, msx1.empty);
1928	2121	msx_cpu_setbank (machine, 2, msx1.empty);
r4576	r4577
1945	2138
1946	2139	MSX_SLOT_WRITE(korean126in1)
1947	2140	{
1948		if (addr >= 0x4000 && addr < 0x4002) {
	2141	if (addr >= 0x4000 && addr < 0x4002)
	2142	{
1949	2143	int bank = addr & 1;
1950	2144	state->banks[bank] = val & state->bank_mask;
1951		if (bank == 0) {
	2145	if (bank == 0)
	2146	{
1952	2147	slot_korean126in1_map (machine, state, 1);
1953	2148	}
1954		else if (msx1.state[2] == state) {
	2149	else if (msx1.state[2] == state)
	2150	{
1955	2151	slot_korean126in1_map (machine, state, 2);
1956	2152	}
1957	2153	}
r4576	r4577
1976	2172	{
1977	2173	int i;
1978	2174
1979		for (i=0; i<4; i++) {
	2175	for (i=0; i<4; i++)
	2176	{
1980	2177	state->banks[i] = i;
1981	2178	state->cart.sccp.ram_mode[i] = 0;
1982	2179	state->cart.sccp.banks_saved[i] = i;
r4576	r4577
1991	2188	int reg;
1992	2189
1993	2190
1994		if (offset >= 0x7e0) {
	2191	if (offset >= 0x7e0)
	2192	{
1995	2193	return msx1.state[2]->mem[
1996	2194	msx1.state[2]->banks[2] * 0x2000 + 0x1800 + offset];
1997	2195	}
1998	2196
1999	2197	reg = offset & 0xff;
2000	2198
2001		if (reg < 0x80) {
	2199	if (reg < 0x80)
	2200	{
2002	2201	return k051649_waveform_r (devtag_get_device(space->machine, "k051649"), reg);
2003	2202	}
2004		else if (reg < 0xa0) {
	2203	else if (reg < 0xa0)
	2204	{
2005	2205	/* nothing */
2006	2206	}
2007		else if (reg < 0xc0) {
	2207	else if (reg < 0xc0)
	2208	{
2008	2209	/* read wave 5 */
2009	2210	return k051649_waveform_r (devtag_get_device(space->machine, "k051649"), 0x80 + (reg & 0x1f));
2010	2211	}
2011	2212	#if 0
2012		else if (reg < 0xe0) {
	2213	else if (reg < 0xe0)
	2214	{
2013	2215	/* write 0xff to deformation register */
2014	2216	}
2015	2217	#endif
r4576	r4577
2021	2223	{
2022	2224	int reg;
2023	2225
2024		if (offset >= 0x7e0) {
	2226	if (offset >= 0x7e0)
	2227	{
2025	2228	return msx1.state[2]->mem[
2026	2229	msx1.state[2]->banks[3] * 0x2000 + 0x1800 + offset];
2027	2230	}
2028	2231
2029	2232	reg = offset & 0xff;
2030	2233
2031		if (reg < 0xa0) {
	2234	if (reg < 0xa0)
	2235	{
2032	2236	return k051649_waveform_r (devtag_get_device(space->machine, "k051649"), reg);
2033	2237	}
2034	2238	#if 0
2035		else if (reg >= 0xc0 && reg < 0xe0) {
	2239	else if (reg >= 0xc0 && reg < 0xe0)
	2240	{
2036	2241	/* write 0xff to deformation register */
2037	2242	}
2038	2243	#endif
r4576	r4577
2042	2247
2043	2248	MSX_SLOT_MAP(soundcartridge)
2044	2249	{
2045		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
2046		switch (page) {
	2250	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	2251	switch (page)
	2252	{
2047	2253	case 0:
2048	2254	msx_cpu_setbank (machine, 1, state->mem + state->banks[2] * 0x2000);
2049	2255	msx_cpu_setbank (machine, 2, state->mem + state->banks[3] * 0x2000);
r4576	r4577
2069	2275
2070	2276	MSX_SLOT_WRITE(soundcartridge)
2071	2277	{
2072		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	2278	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
2073	2279	int i;
2074	2280
2075		if (addr < 0x4000) {
	2281	if (addr < 0x4000)
	2282	{
2076	2283	return;
2077	2284	}
2078		else if (addr < 0x6000) {
2079		if (state->cart.sccp.ram_mode[0]) {
	2285	else if (addr < 0x6000)
	2286	{
	2287	if (state->cart.sccp.ram_mode[0])
	2288	{
2080	2289	state->mem[state->banks[0] * 0x2000 + (addr & 0x1fff)] = val;
2081	2290	}
2082		else if (addr >= 0x5000 && addr < 0x5800) {
	2291	else if (addr >= 0x5000 && addr < 0x5800)
	2292	{
2083	2293	state->banks[0] = val & state->bank_mask;
2084	2294	state->cart.sccp.banks_saved[0] = val;
2085	2295	slot_soundcartridge_map (machine, state, 1);
2086		if (msx1.state[3] == state) {
	2296	if (msx1.state[3] == state)
	2297	{
2087	2298	slot_soundcartridge_map (machine, state, 3);
2088	2299	}
2089	2300	}
2090	2301	}
2091		else if (addr < 0x8000) {
2092		if (state->cart.sccp.ram_mode[1]) {
	2302	else if (addr < 0x8000)
	2303	{
	2304	if (state->cart.sccp.ram_mode[1])
	2305	{
2093	2306	state->mem[state->banks[1] * 0x2000 + (addr & 0x1fff)] = val;
2094	2307	}
2095		else if (addr >= 0x7000 && addr < 0x7800) {
	2308	else if (addr >= 0x7000 && addr < 0x7800)
	2309	{
2096	2310	state->banks[1] = val & state->bank_mask;
2097	2311	state->cart.sccp.banks_saved[1] = val;
2098		if (msx1.state[3] == state) {
	2312	if (msx1.state[3] == state)
	2313	{
2099	2314	slot_soundcartridge_map (machine, state, 3);
2100	2315	}
2101	2316	slot_soundcartridge_map (machine, state, 1);
2102	2317	}
2103	2318	}
2104		else if (addr < 0xa000) {
2105		if (state->cart.sccp.ram_mode[2]) {
	2319	else if (addr < 0xa000)
	2320	{
	2321	if (state->cart.sccp.ram_mode[2])
	2322	{
2106	2323	state->mem[state->banks[2] * 0x2000 + (addr & 0x1fff)] = val;
2107	2324	}
2108		else if (addr >= 0x9000 && addr < 0x9800) {
	2325	else if (addr >= 0x9000 && addr < 0x9800)
	2326	{
2109	2327	state->banks[2] = val & state->bank_mask;
2110	2328	state->cart.sccp.banks_saved[2] = val;
2111	2329	state->cart.sccp.scc_active =
2112	2330	(((val & 0x3f) == 0x3f) && !(state->cart.sccp.mode & 0x20));
2113	2331
2114	2332	slot_soundcartridge_map (machine, state, 2);
2115		if (msx1.state[0] == state) {
	2333	if (msx1.state[0] == state)
	2334	{
2116	2335	slot_soundcartridge_map (machine, state, 0);
2117	2336	}
2118	2337	}
2119		else if (addr >= 0x9800 && state->cart.sccp.scc_active) {
	2338	else if (addr >= 0x9800 && state->cart.sccp.scc_active)
	2339	{
2120	2340	const device_config *k051649 = devtag_get_device(space->machine, "k051649");
2121	2341	int offset = addr & 0xff;
2122	2342
2123		if (offset < 0x80) {
	2343	if (offset < 0x80)
	2344	{
2124	2345	k051649_waveform_w (k051649, offset, val);
2125	2346	}
2126		else if (offset < 0xa0) {
	2347	else if (offset < 0xa0)
	2348	{
2127	2349	offset &= 0xf;
2128	2350
2129		if (offset < 0xa) {
	2351	if (offset < 0xa)
	2352	{
2130	2353	k051649_frequency_w (k051649, offset, val);
2131	2354	}
2132		else if (offset < 0x0f) {
	2355	else if (offset < 0x0f)
	2356	{
2133	2357	k051649_volume_w (k051649, offset - 0xa, val);
2134	2358	}
2135		else if (offset == 0x0f) {
	2359	else if (offset == 0x0f)
	2360	{
2136	2361	k051649_keyonoff_w (k051649, 0, val);
2137	2362	}
2138	2363	}
2139	2364	#if 0
2140		else if (offset < 0xe0) {
	2365	else if (offset < 0xe0)
	2366	{
2141	2367	/* write to deformation register */
2142	2368	}
2143	2369	#endif
2144	2370	}
2145	2371	}
2146		else if (addr < 0xbffe) {
2147		if (state->cart.sccp.ram_mode[3]) {
	2372	else if (addr < 0xbffe)
	2373	{
	2374	if (state->cart.sccp.ram_mode[3])
	2375	{
2148	2376	state->mem[state->banks[3] * 0x2000 + (addr & 0x1fff)] = val;
2149	2377	}
2150		else if (addr >= 0xb000 && addr < 0xb800) {
	2378	else if (addr >= 0xb000 && addr < 0xb800)
	2379	{
2151	2380	state->cart.sccp.banks_saved[3] = val;
2152	2381	state->banks[3] = val & state->bank_mask;
2153	2382	state->cart.sccp.sccp_active =
2154	2383	(val & 0x80) && (state->cart.sccp.mode & 0x20);
2155	2384	slot_soundcartridge_map (machine, state, 2);
2156		if (msx1.state[0] == state) {
	2385	if (msx1.state[0] == state)
	2386	{
2157	2387	slot_soundcartridge_map (machine, state, 0);
2158	2388	}
2159	2389	}
2160		else if (addr >= 0xb800 && state->cart.sccp.sccp_active) {
	2390	else if (addr >= 0xb800 && state->cart.sccp.sccp_active)
	2391	{
2161	2392	const device_config *k051649 = devtag_get_device(space->machine, "k051649");
2162	2393	int offset = addr & 0xff;
2163	2394
2164		if (offset < 0xa0) {
	2395	if (offset < 0xa0)
	2396	{
2165	2397	k052539_waveform_w (k051649, offset, val);
2166	2398	}
2167		else if (offset < 0xc0) {
	2399	else if (offset < 0xc0)
	2400	{
2168	2401	offset &= 0x0f;
2169	2402
2170		if (offset < 0x0a) {
	2403	if (offset < 0x0a)
	2404	{
2171	2405	k051649_frequency_w (k051649, offset, val);
2172	2406	}
2173		else if (offset < 0x0f) {
	2407	else if (offset < 0x0f)
	2408	{
2174	2409	k051649_volume_w (k051649, offset - 0x0a, val);
2175	2410	}
2176		else if (offset == 0x0f) {
	2411	else if (offset == 0x0f)
	2412	{
2177	2413	k051649_keyonoff_w (k051649, 0, val);
2178	2414	}
2179	2415	}
2180	2416	#if 0
2181		else if (offset < 0xe0) {
	2417	else if (offset < 0xe0)
	2418	{
2182	2419	/* write to deformation register */
2183	2420	}
2184	2421	#endif
2185	2422	}
2186	2423	}
2187		else if (addr < 0xc000) {
	2424	else if (addr < 0xc000)
	2425	{
2188	2426	/* write to mode register */
2189		if ((state->cart.sccp.mode ^ val) & 0x20) {
	2427	if ((state->cart.sccp.mode ^ val) & 0x20)
	2428	{
2190	2429	logerror ("soundcartrige: changed to %s mode\n",
2191	2430	val & 0x20 ? "scc+" : "scc");
2192	2431	}
2193	2432	state->cart.sccp.mode = val;
2194		if (val & 0x10) {
	2433	if (val & 0x10)
	2434	{
2195	2435	/* all ram mode */
2196		for (i=0; i<4; i++) {
	2436	for (i=0; i<4; i++)
	2437	{
2197	2438	state->cart.sccp.ram_mode[i] = 1;
2198	2439	}
2199	2440	}
2200		else {
	2441	else
	2442	{
2201	2443	state->cart.sccp.ram_mode[0] = val & 1;
2202	2444	state->cart.sccp.ram_mode[1] = val & 2;
2203	2445	state->cart.sccp.ram_mode[2] = (val & 4) && (val & 0x20);

src/mess/machine/microtan.c

r4576	r4577
156	156	/* The 6502 IRQ line is active low and probably driven
157	157	by open collector outputs (guess). Since MAME/MESS use
158	158	a non-0 value for ASSERT_LINE we OR the signals here */
159		cpu_set_input_line(machine->cpu[0], 0, via_0_irq_line | via_1_irq_line | kbd_irq_line);
	159	cputag_set_input_line(machine, "maincpu", 0, via_0_irq_line | via_1_irq_line | kbd_irq_line);
160	160	}
161	161
162	162	static const device_config *cassette_device_image(running_machine *machine)
r4576	r4577
388	388	/* This callback is called one clock cycle after BFF2 is written (delayed nmi) */
389	389	static TIMER_CALLBACK(microtan_pulse_nmi)
390	390	{
391		cpu_set_input_line(machine->cpu[0], INPUT_LINE_NMI, PULSE_LINE);
	391	cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE);
392	392	}
393	393
394	394	WRITE8_HANDLER ( microtan_bffx_w )
r4576	r4577
404	404	break;
405	405	case 1: /* BFF1: write delayed NMI */
406	406	LOG(("microtan_bff1_w: %d <- %02x (delayed NMI)\n", offset, data));
407		timer_set(space->machine, cpu_clocks_to_attotime(space->machine->cpu[0], 8), NULL, 0, microtan_pulse_nmi);
	407	timer_set(space->machine, cputag_clocks_to_attotime(space->machine, "maincpu", 8), NULL, 0, microtan_pulse_nmi);
408	408	break;
409	409	case 2: /* BFF2: write keypad column write (what is this meant for?) */
410	410	LOG(("microtan_bff2_w: %d <- %02x (keypad column)\n", offset, data));
r4576	r4577
702	702	LOG(("microtan_snapshot_copy: PC:%02X%02X P:%02X A:%02X X:%02X Y:%02X SP:1%02X",
703	703	snapshot_buff[base+1], snapshot_buff[base+0], snapshot_buff[base+2], snapshot_buff[base+3],
704	704	snapshot_buff[base+4], snapshot_buff[base+5], snapshot_buff[base+6]);
705		cpu_set_reg(machine->cpu[0], M6502_PC, snapshot_buff[base+0] + 256 * snapshot_buff[base+1]));
706		cpu_set_reg(machine->cpu[0], M6502_P, snapshot_buff[base+2]);
707		cpu_set_reg(machine->cpu[0], M6502_A, snapshot_buff[base+3]);
708		cpu_set_reg(machine->cpu[0], M6502_X, snapshot_buff[base+4]);
709		cpu_set_reg(machine->cpu[0], M6502_Y, snapshot_buff[base+5]);
710		cpu_set_reg(machine->cpu[0], M6502_S, snapshot_buff[base+6]);
	705	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), M6502_PC, snapshot_buff[base+0] + 256 * snapshot_buff[base+1]));
	706	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), M6502_P, snapshot_buff[base+2]);
	707	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), M6502_A, snapshot_buff[base+3]);
	708	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), M6502_X, snapshot_buff[base+4]);
	709	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), M6502_Y, snapshot_buff[base+5]);
	710	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), M6502_S, snapshot_buff[base+6]);
711	711	}
712	712
713	713	static void microtan_snapshot_copy(running_machine *machine, UINT8 *snapshot_buff, int snapshot_size)
714	714	{
715	715	UINT8 *RAM = memory_region(machine, "maincpu");
716		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	716	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
717	717	const device_config *via_0 = devtag_get_device(machine, "via6522_0");
718	718	const device_config *via_1 = devtag_get_device(machine, "via6522_1");
719	719	const device_config *ay8910 = devtag_get_device(machine, "ay8910.1");
r4576	r4577
869	869	{
870	870	UINT8 *dst = memory_region(machine, "gfx2");
871	871	int i;
872		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	872	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
873	873
874	874	for (i = 0; i < 256; i++)
875	875	{

src/mess/machine/mac.c

r4576	r4577
226	226	static void mac_install_memory(running_machine *machine, offs_t memory_begin, offs_t memory_end,
227	227	offs_t memory_size, void *memory_data, int is_rom, int bank)
228	228	{
229		const address_space* space = cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM);
	229	const address_space* space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
230	230	offs_t memory_mask;
231	231	read16_space_func rh;
232	232	write16_space_func wh;
r4576	r4577
290	290
291	291	if (last_taken_interrupt != -1)
292	292	{
293		cpu_set_input_line(machine->cpu[0], last_taken_interrupt, CLEAR_LINE);
	293	cputag_set_input_line(machine, "maincpu", last_taken_interrupt, CLEAR_LINE);
294	294	last_taken_interrupt = -1;
295	295	}
296	296
297	297	if (take_interrupt != -1)
298	298	{
299		cpu_set_input_line(machine->cpu[0], take_interrupt, ASSERT_LINE);
	299	cputag_set_input_line(machine, "maincpu", take_interrupt, ASSERT_LINE);
300	300	last_taken_interrupt = take_interrupt;
301	301	}
302	302	}
r4576	r4577
910	910	scc_set_status(scc, 0x02);
911	911	}
912	912
913		//cpu_set_input_line(machine->cpu[0], 2, ASSERT_LINE);
	913	//cputag_set_input_line(machine, "maincpu", 2, ASSERT_LINE);
914	914	set_scc_interrupt(machine, 1);
915	915	}
916	916
r4576	r4577
1770	1770	static void mac_via_irq(const device_config *device, int state)
1771	1771	{
1772	1772	/* interrupt the 68k (level 1) */
1773		//cpu_set_input_line(machine->cpu[0], 1, state);
	1773	//cputag_set_input_line(machine, "maincpu", 1, state);
1774	1774	set_via_interrupt(device->machine, state);
1775	1775	}
1776	1776
r4576	r4577
1843	1843
1844	1844	static READ8_DEVICE_HANDLER(mac_via2_in_a)
1845	1845	{
1846		logerror("VIA2 IN A (PC %x)\n", cpu_get_pc(device->machine->cpu[0]));
	1846	logerror("VIA2 IN A (PC %x)\n", cpu_get_pc(cputag_get_cpu(device->machine, "maincpu")));
1847	1847
1848	1848	return 0;
1849	1849	}
1850	1850
1851	1851	static READ8_DEVICE_HANDLER(mac_via2_in_b)
1852	1852	{
1853		logerror("VIA2 IN B (PC %x)\n", cpu_get_pc(device->machine->cpu[0]));
	1853	logerror("VIA2 IN B (PC %x)\n", cpu_get_pc(cputag_get_cpu(device->machine, "maincpu")));
1854	1854
1855	1855	return 0;
1856	1856	}
1857	1857
1858	1858	static WRITE8_DEVICE_HANDLER(mac_via2_out_a)
1859	1859	{
1860		logerror("VIA2 OUT A: %02x (PC %x)\n", data, cpu_get_pc(device->machine->cpu[0]));
	1860	logerror("VIA2 OUT A: %02x (PC %x)\n", data, cpu_get_pc(cputag_get_cpu(device->machine, "maincpu")));
1861	1861	}
1862	1862
1863	1863	static WRITE8_DEVICE_HANDLER(mac_via2_out_b)
1864	1864	{
1865		logerror("VIA2 OUT B: %02x (PC %x)\n", data, cpu_get_pc(device->machine->cpu[0]));
	1865	logerror("VIA2 OUT B: %02x (PC %x)\n", data, cpu_get_pc(cputag_get_cpu(device->machine, "maincpu")));
1866	1866	}
1867	1867
1868	1868	/* *************************************************************************
r4576	r4577
1960	1960	// classic will fail RAM test and try to boot appletalk if RAM is not all zero
1961	1961	memset(mess_ram, 0, mess_ram_size);
1962	1962
1963		memory_set_direct_update_handler(cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM), overlay_opbaseoverride);
	1963	memory_set_direct_update_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), overlay_opbaseoverride);
1964	1964	mac_overlay = 1;
1965	1965	}
1966	1966
r4576	r4577
1969	1969
1970	1970	inquiry_timeout = timer_alloc(machine, inquiry_timeout_func, NULL);
1971	1971
1972		debug_cpu_set_dasm_override(machine->cpu[0], mac_dasm_override);
	1972	debug_cpu_set_dasm_override(cputag_get_cpu(machine, "maincpu"), mac_dasm_override);
1973	1973
1974	1974	/* save state stuff */
1975	1975	state_save_register_global(machine, mac_overlay);
r4576	r4577
3057	3057	logerror("mac_trace_trap: %s at 0x%08x: %s\n",cpu_name_local, addr, buf);
3058	3058	}
3059	3059	#endif
3060
3061
3062

src/mess/machine/msx.c

r4576	r4577
299	299
300	300	void msx_vdp_interrupt(running_machine *machine, int i)
301	301	{
302		cpu_set_input_line (machine->cpu[0], 0, (i ? HOLD_LINE : CLEAR_LINE));
	302	cputag_set_input_line (machine, "maincpu", 0, (i ? HOLD_LINE : CLEAR_LINE));
303	303	}
304	304
305	305	static void msx_ch_reset_core (running_machine *machine)
r4576	r4577
473	473
474	474	memset (&msx1, 0, sizeof (MSX));
475	475	/* LOAD_DEVICE is called before DRIVER_INIT */
476		for (i=0; i<MSX_MAX_CARTS; i++) {
	476	for (i=0; i<MSX_MAX_CARTS; i++)
	477	{
477	478	msx1.cart_state[i] = cart_state[i];
478	479	}
479	480
480		cpu_set_input_line_vector (machine->cpu[0], 0, 0xff);
	481	cpu_set_input_line_vector (cputag_get_cpu(machine, "maincpu"), 0, 0xff);
481	482
482	483	msx_memory_init (machine);
483	484
484		z80_set_cycle_tables( machine->cpu[0], cc_op, cc_cb, cc_ed, cc_xy, cc_xycb, cc_ex );
	485	z80_set_cycle_tables( cputag_get_cpu(machine, "maincpu"), cc_op, cc_cb, cc_ed, cc_xy, cc_xycb, cc_ex );
485	486	}
486	487
487	488	INTERRUPT_GEN( msx2_interrupt )

src/mess/machine/mz700.c

r4576	r4577
670	670	/* port EB */
671	671	WRITE8_HANDLER( mz800_ramaddr_w )
672	672	{
673		mz800_ramaddr = (cpu_get_reg(space->machine->cpu[0], Z80_BC) & 0xff00) | (data & 0xff);
	673	mz800_ramaddr = (cpu_get_reg(cputag_get_cpu(space->machine, "maincpu"), Z80_BC) & 0xff00) | (data & 0xff);
674	674	LOG(1,"mz800_ramaddr_w",("%04X\n", mz800_ramaddr),space->machine);
675	675	}
676	676

src/mess/machine/lisa.c

r4576	r4577
224	224
225	225	/*if (RSIR)
226	226	// serial interrupt
227		cpu_set_input_line_and_vector(machine->cpu[0], M68K_IRQ_6, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	227	cputag_set_input_line_and_vector(machine, "maincpu", M68K_IRQ_6, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
228	228	else if (int0)
229	229	// external interrupt
230		cpu_set_input_line_and_vector(machine->cpu[0], M68K_IRQ_5, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	230	cputag_set_input_line_and_vector(machine, "maincpu", M68K_IRQ_5, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
231	231	else if (int1)
232	232	// external interrupt
233		cpu_set_input_line_and_vector(machine->cpu[0], M68K_IRQ_4, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	233	cputag_set_input_line_and_vector(machine, "maincpu", M68K_IRQ_4, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
234	234	else if (int2)
235	235	// external interrupt
236		cpu_set_input_line_and_vector(machine->cpu[0], M68K_IRQ_3, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	236	cputag_set_input_line_and_vector(machine, "maincpu", M68K_IRQ_3, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
237	237	else*/ if (KBIR)
238	238	/* COPS VIA interrupt */
239		cpu_set_input_line_and_vector(machine->cpu[0], M68K_IRQ_2, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	239	cputag_set_input_line_and_vector(machine, "maincpu", M68K_IRQ_2, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
240	240	else if (FDIR || VTIR)
241	241	/* floppy disk or VBl */
242		cpu_set_input_line_and_vector(machine->cpu[0], M68K_IRQ_1, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	242	cputag_set_input_line_and_vector(machine, "maincpu", M68K_IRQ_1, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
243	243	else
244	244	/* clear all interrupts */
245		cpu_set_input_line_and_vector(machine->cpu[0], M68K_IRQ_1, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR);
	245	cputag_set_input_line_and_vector(machine, "maincpu", M68K_IRQ_1, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR);
246	246	}
247	247
248	248	static void set_parity_error_pending(running_machine *machine, int value)
r4576	r4577
252	252	parity_error_pending = value;
253	253	if (parity_error_pending)
254	254	{
255		cpu_set_input_line_and_vector(machine->cpu[0], M68K_IRQ_7, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	255	cputag_set_input_line_and_vector(machine, "maincpu", M68K_IRQ_7, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
256	256	}
257	257	else
258	258	{
259		cpu_set_input_line(machine->cpu[0], M68K_IRQ_7, CLEAR_LINE);
	259	cputag_set_input_line(machine, "maincpu", M68K_IRQ_7, CLEAR_LINE);
260	260	}
261	261	#else
262	262	/* work-around... */
263	263	if ((! parity_error_pending) && value)
264	264	{
265	265	parity_error_pending = 1;
266		cpu_set_input_line_and_vector(machine->cpu[0], M68K_IRQ_7, PULSE_LINE, M68K_INT_ACK_AUTOVECTOR);
	266	cputag_set_input_line_and_vector(machine, "maincpu", M68K_IRQ_7, PULSE_LINE, M68K_INT_ACK_AUTOVECTOR);
267	267	}
268	268	else if (parity_error_pending && (! value))
269	269	{
r4576	r4577
426	426	#if 0
427	427	if (keycode == NMIcode)
428	428	{   /* generate NMI interrupt */
429		cpu_set_input_line(machine->cpu[0], M68K_IRQ_7, PULSE_LINE);
430		cpu_set_input_line_vector(machine->cpu[0], M68K_IRQ_7, M68K_INT_ACK_AUTOVECTOR);
	429	cputag_set_input_line(machine, "maincpu", M68K_IRQ_7, PULSE_LINE);
	430	cpu_set_input_line_vector(cputag_get_cpu(machine, "maincpu"), M68K_IRQ_7, M68K_INT_ACK_AUTOVECTOR);
431	431	}
432	432	#endif
433	433	COPS_queue_data(machine, & keycode, 1);
r4576	r4577
969	969
970	970	}
971	971
972		if (cpu_get_reg(space->machine->cpu[0], M68K_SR) & 0x2000)
	972	if (cpu_get_reg(cputag_get_cpu(space->machine, "maincpu"), M68K_SR) & 0x2000)
973	973	/* supervisor mode -> force register file 0 */
974	974	the_seg = 0;
975	975
r4576	r4577
1139	1139
1140	1140	videoROM_ptr = memory_region(machine, "gfx1");
1141	1141
1142		memory_set_direct_update_handler(cpu_get_address_space(machine->cpu[0],ADDRESS_SPACE_PROGRAM), lisa_OPbaseoverride);
1143		memory_set_direct_update_handler(cpu_get_address_space(machine->cpu[1],ADDRESS_SPACE_PROGRAM), lisa_fdc_OPbaseoverride);
	1142	memory_set_direct_update_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), lisa_OPbaseoverride);
	1143	memory_set_direct_update_handler(cputag_get_address_space(machine, "fdccpu",  ADDRESS_SPACE_PROGRAM), lisa_fdc_OPbaseoverride);
1144	1144
1145		device_set_info_fct(machine->cpu[0], CPUINFO_FCT_M68K_RESET_CALLBACK, (genf *)/*lisa_reset_instr_callback*/NULL);
	1145	devtag_set_info_fct(machine, "maincpu", CPUINFO_FCT_M68K_RESET_CALLBACK, (genf *)/*lisa_reset_instr_callback*/NULL);
1146	1146
1147	1147	/* init MMU */
1148	1148
r4576	r4577
1499	1499	}
1500	1500	}
1501	1501
1502		if (cpu_get_reg(space->machine->cpu[0], M68K_SR) & 0x2000)
	1502	if (cpu_get_reg(cputag_get_cpu(space->machine, "maincpu"), M68K_SR) & 0x2000)
1503	1503	/* supervisor mode -> force register file 0 */
1504	1504	the_seg = 0;
1505	1505
r4576	r4577
1603	1603	if ((time_in_frame >= 364) && (time_in_frame <= 375))
1604	1604	{
1605	1605	answer = videoROM_ptr[videoROM_address|0x80] << 8;
1606		logerror("reading1 %06X=%04x PC=%06x time=%d\n", address, answer, cpu_get_pc(space->machine->cpu[0]), time_in_frame);
	1606	logerror("reading1 %06X=%04x PC=%06x time=%d\n", address, answer, cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")), time_in_frame);
1607	1607	}
1608	1608	else
1609	1609	{
1610	1610	answer = videoROM_ptr[videoROM_address] << 8;
1611		logerror("reading2 %06X=%04x PC=%06x time=%d\n", address, answer, cpu_get_pc(space->machine->cpu[0]), time_in_frame);
	1611	logerror("reading2 %06X=%04x PC=%06x time=%d\n", address, answer, cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")), time_in_frame);
1612	1612	}
1613	1613	}
1614	1614
r4576	r4577
1707	1707	}
1708	1708	}
1709	1709
1710		if (cpu_get_reg(space->machine->cpu[0], M68K_SR) & 0x2000)
	1710	if (cpu_get_reg(cputag_get_cpu(space->machine, "maincpu"), M68K_SR) & 0x2000)
1711	1711	/* supervisor mode -> force register file 0 */
1712	1712	the_seg = 0;
1713	1713
r4576	r4577
1869	1869	seg &= ~2;
1870	1870	break;
1871	1871	case 0x0010:   /* SETUP register SET */
1872		logerror("setup SET PC=%x\n", cpu_get_pc(machine->cpu[0]));
	1872	logerror("setup SET PC=%x\n", cpu_get_pc(cputag_get_cpu(machine, "maincpu")));
1873	1873	setup = 1;
1874	1874	break;
1875	1875	case 0x0012:   /* SETUP register RESET */
1876		logerror("setup UNSET PC=%x\n", cpu_get_pc(machine->cpu[0]));
	1876	logerror("setup UNSET PC=%x\n", cpu_get_pc(cputag_get_cpu(machine, "maincpu")));
1877	1877	setup = 0;
1878	1878	break;
1879	1879	case 0x001A:   /* Enable Vertical Retrace Interrupt */
1880		logerror("enable retrace PC=%x\n", cpu_get_pc(machine->cpu[0]));
	1880	logerror("enable retrace PC=%x\n", cpu_get_pc(cputag_get_cpu(machine, "maincpu")));
1881	1881	VTMSK = 1;
1882	1882	break;
1883	1883	case 0x0018:   /* Disable Vertical Retrace Interrupt */
1884		logerror("disable retrace PC=%x\n", cpu_get_pc(machine->cpu[0]));
	1884	logerror("disable retrace PC=%x\n", cpu_get_pc(cputag_get_cpu(machine, "maincpu")));
1885	1885	VTMSK = 0;
1886	1886	set_VTIR(machine, 2);
1887	1887	break;
r4576	r4577
2017	2017	else
2018	2018	answer |= 0x04;
2019	2019	/* huh... we need to emulate some other bits */
2020		logerror("read status PC=%x val=%x\n", cpu_get_pc(space->machine->cpu[0]),answer);
	2020	logerror("read status PC=%x val=%x\n", cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")), answer);
2021	2021
2022	2022	break;
2023	2023	}

src/mess/machine/lynx.c

r4576	r4577
785	785	int i; int o;int colors;
786	786
787	787	blitter.memory_accesses = 0;
788		blitter.mem = memory_get_read_ptr(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000);
	788	blitter.mem = memory_get_read_ptr(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0000);
789	789
790	790	blitter.xoff   = GET_WORD(suzy.data, 0x04);
791	791	blitter.yoff   = GET_WORD(suzy.data, 0x06);
r4576	r4577
886	886	}
887	887
888	888	if (0)
889		timer_set(machine, cpu_clocks_to_attotime(machine->cpu[0], blitter.memory_accesses*20), NULL, 0, lynx_blitter_timer);
	889	timer_set(machine, cputag_clocks_to_attotime(machine, "maincpu", blitter.memory_accesses*20), NULL, 0, lynx_blitter_timer);
890	890	}
891	891
892	892
r4576	r4577
1005	1005	case 0x92:   /* Better check this with docs! */
1006	1006	if (!attotime_compare(blitter.time, attotime_zero))
1007	1007	{
1008		if (cpu_attotime_to_clocks(space->machine->cpu[0], attotime_sub(timer_get_time(space->machine), blitter.time)) > blitter.memory_accesses * 20)
	1008	if (cputag_attotime_to_clocks(space->machine, "maincpu", attotime_sub(timer_get_time(space->machine), blitter.time)) > blitter.memory_accesses * 20)
1009	1009	{
1010	1010	suzy.data[offset] &= ~0x01; //blitter finished
1011	1011	blitter.time = attotime_zero;
r4576	r4577
1361	1361
1362	1362	static void lynx_timer_signal_irq(running_machine *machine, int which)
1363	1363	{
1364		if ( ( lynx_timer[which].cntrl1 & 0x80 ) && ( which != 4 ) ) { // irq flag handling later
	1364	if ( ( lynx_timer[which].cntrl1 & 0x80 ) && ( which != 4 ) )
	1365	{ // irq flag handling later
1365	1366	mikey.data[0x81] |= ( 1 << which );
1366		cpu_set_input_line(machine->cpu[0], M65SC02_IRQ_LINE, ASSERT_LINE);
	1367	cputag_set_input_line(machine, "maincpu", M65SC02_IRQ_LINE, ASSERT_LINE);
1367	1368	}
1368		switch ( which ) {
	1369	switch ( which )
	1370	{
1369	1371	case 0:
1370	1372	lynx_timer_count_down( machine, 2 );
1371	1373	lynx_line++;
r4576	r4577
1392	1394
1393	1395	void lynx_timer_count_down(running_machine *machine, int which)
1394	1396	{
1395		if ( ( lynx_timer[which].cntrl1 & 0x0f ) == 0x0f ) {
1396		if ( lynx_timer[which].counter > 0 ) {
	1397	if ( ( lynx_timer[which].cntrl1 & 0x0f ) == 0x0f )
	1398	{
	1399	if ( lynx_timer[which].counter > 0 )
	1400	{
1397	1401	lynx_timer[which].counter--;
1398	1402	return;
1399	1403	}
1400		if ( lynx_timer[which].counter == 0 ) {
	1404	if ( lynx_timer[which].counter == 0 )
	1405	{
1401	1406	lynx_timer[which].cntrl2 |= 8;
1402	1407	lynx_timer_signal_irq(machine, which);
1403		if ( lynx_timer[which].cntrl1 & 0x10 ) {
	1408	if ( lynx_timer[which].cntrl1 & 0x10 )
	1409	{
1404	1410	lynx_timer[which].counter = lynx_timer[which].bakup;
1405		} else {
	1411	}
	1412	else
	1413	{
1406	1414	lynx_timer[which].counter--;
1407	1415	}
1408	1416	return;
r4576	r4577
1544	1552	if (uart.serctl & 0x80)
1545	1553	{
1546	1554	mikey.data[0x81] |= 0x10;
1547		cpu_set_input_line(machine->cpu[0], M65SC02_IRQ_LINE, ASSERT_LINE);
	1555	cputag_set_input_line(machine, "maincpu", M65SC02_IRQ_LINE, ASSERT_LINE);
1548	1556	}
1549	1557	}
1550	1558
r4576	r4577
1700	1708	mikey.data[0x81] &= ~data; // clear interrupt source
1701	1709	logerror("mikey write %.2x %.2x\n", offset, data);
1702	1710	if (!mikey.data[0x81])
1703		cpu_set_input_line(space->machine->cpu[0], M65SC02_IRQ_LINE, CLEAR_LINE);
	1711	cputag_set_input_line(space->machine, "maincpu", M65SC02_IRQ_LINE, CLEAR_LINE);
1704	1712	break;
1705	1713
1706	1714	/* Is this correct? */
r4576	r4577
1803	1811	static void lynx_reset(running_machine *machine)
1804	1812	{
1805	1813	int i;
1806		lynx_memory_config_w(cputag_get_address_space(machine,"maincpu",ADDRESS_SPACE_PROGRAM), 0, 0);
	1814	lynx_memory_config_w(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0, 0);
1807	1815
1808		cpu_set_input_line(machine->cpu[0], M65SC02_IRQ_LINE, CLEAR_LINE);
	1816	cputag_set_input_line(machine, "maincpu", M65SC02_IRQ_LINE, CLEAR_LINE);
1809	1817
1810	1818	memset(&suzy, 0, sizeof(suzy));
1811	1819	memset(&mikey, 0, sizeof(mikey));
r4576	r4577
1839	1847
1840	1848	static STATE_POSTLOAD( lynx_postload )
1841	1849	{
1842		lynx_memory_config_w( cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0, lynx_memory_config);
	1850	lynx_memory_config_w( cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0, lynx_memory_config);
1843	1851	}
1844	1852
1845	1853	MACHINE_START( lynx )

src/mess/machine/kaypro.c

r4576	r4577
28	28
29	29	static WRITE8_DEVICE_HANDLER( kaypro_interrupt )
30	30	{
31		cpu_set_input_line(device->machine->cpu[0], 0, data);
	31	cputag_set_input_line(device->machine, "maincpu", 0, data);
32	32	}
33	33
34	34	static READ8_DEVICE_HANDLER( pio_system_r )
r4576	r4577
248	248	/* when sio devcb'ed like pio is, change to use pio's int handler */
249	249	static void kaypro_int_sio(const device_config *device, int state)
250	250	{
251		cpu_set_input_line(device->machine->cpu[0], 0, state);
	251	cputag_set_input_line(device->machine, "maincpu", 0, state);
252	252	}
253	253
254	254	const z80sio_interface kaypro_sio_intf =
r4576	r4577
337	337	{
338	338	case WD17XX_DRQ_CLR:
339	339	case WD17XX_IRQ_CLR:
340		cpu_set_input_line(device->machine->cpu[0], INPUT_LINE_NMI, 0);
	340	cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_NMI, 0);
341	341	break;
342	342	case WD17XX_DRQ_SET:
343	343	case WD17XX_IRQ_SET:
344		if (cpu_get_reg(device->machine->cpu[0], Z80_HALT))
345		cpu_set_input_line(device->machine->cpu[0], INPUT_LINE_NMI, PULSE_LINE);
	344	if (cpu_get_reg(cputag_get_cpu(device->machine, "maincpu"), Z80_HALT))
	345	cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE);
346	346	break;
347	347	}
348	348	}

src/mess/machine/lviv.c

r4576	r4577
163	163
164	164	WRITE8_HANDLER ( lviv_io_w )
165	165	{
166		const address_space *cpuspace = cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	166	const address_space *cpuspace = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
167	167	if (startup_mem_map)
168	168	{
169	169	startup_mem_map = 0;
r4576	r4577
221	221
222	222	MACHINE_RESET( lviv )
223	223	{
224		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
	224	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
225	225	memory_set_direct_update_handler(space, lviv_directoverride);
226	226
227	227	lviv_video_ram = mess_ram + 0xc000;
r4576	r4577
266	266	/* Set registers */
267	267	lo = data[0x14112] & 0x0ff;
268	268	hi = data[0x14111] & 0x0ff;
269		cpu_set_reg(machine->cpu[0], I8085_BC, (hi << 8) | lo);
	269	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), I8085_BC, (hi << 8) | lo);
270	270	lo = data[0x14114] & 0x0ff;
271	271	hi = data[0x14113] & 0x0ff;
272		cpu_set_reg(machine->cpu[0], I8085_DE, (hi << 8) | lo);
	272	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), I8085_DE, (hi << 8) | lo);
273	273	lo = data[0x14116] & 0x0ff;
274	274	hi = data[0x14115] & 0x0ff;
275		cpu_set_reg(machine->cpu[0], I8085_HL, (hi << 8) | lo);
	275	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), I8085_HL, (hi << 8) | lo);
276	276	lo = data[0x14118] & 0x0ff;
277	277	hi = data[0x14117] & 0x0ff;
278		cpu_set_reg(machine->cpu[0], I8085_AF, (hi << 8) | lo);
	278	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), I8085_AF, (hi << 8) | lo);
279	279	lo = data[0x14119] & 0x0ff;
280	280	hi = data[0x1411a] & 0x0ff;
281		cpu_set_reg(machine->cpu[0], I8085_SP, (hi << 8) | lo);
	281	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), I8085_SP, (hi << 8) | lo);
282	282	lo = data[0x1411b] & 0x0ff;
283	283	hi = data[0x1411c] & 0x0ff;
284		cpu_set_reg(machine->cpu[0], I8085_PC, (hi << 8) | lo);
	284	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), I8085_PC, (hi << 8) | lo);
285	285
286	286	/* Memory dump */
287	287	memcpy (mess_ram, data+0x0011, 0xc000);
r4576	r4577
297	297
298	298	static void dump_registers(running_machine *machine)
299	299	{
300		logerror("PC   = %04x\n", (unsigned) cpu_get_reg(machine->cpu[0], I8085_PC));
301		logerror("SP   = %04x\n", (unsigned) cpu_get_reg(machine->cpu[0], I8085_SP));
302		logerror("AF   = %04x\n", (unsigned) cpu_get_reg(machine->cpu[0], I8085_AF));
303		logerror("BC   = %04x\n", (unsigned) cpu_get_reg(machine->cpu[0], I8085_BC));
304		logerror("DE   = %04x\n", (unsigned) cpu_get_reg(machine->cpu[0], I8085_DE));
305		logerror("HL   = %04x\n", (unsigned) cpu_get_reg(machine->cpu[0], I8085_HL));
	300	logerror("PC   = %04x\n", (unsigned) cpu_get_reg(cputag_get_cpu(machine, "maincpu"), I8085_PC));
	301	logerror("SP   = %04x\n", (unsigned) cpu_get_reg(cputag_get_cpu(machine, "maincpu"), I8085_SP));
	302	logerror("AF   = %04x\n", (unsigned) cpu_get_reg(cputag_get_cpu(machine, "maincpu"), I8085_AF));
	303	logerror("BC   = %04x\n", (unsigned) cpu_get_reg(cputag_get_cpu(machine, "maincpu"), I8085_BC));
	304	logerror("DE   = %04x\n", (unsigned) cpu_get_reg(cputag_get_cpu(machine, "maincpu"), I8085_DE));
	305	logerror("HL   = %04x\n", (unsigned) cpu_get_reg(cputag_get_cpu(machine, "maincpu"), I8085_HL));
306	306	}
307	307
308	308	static int lviv_verify_snapshot (UINT8 * data, UINT32 size)

src/mess/machine/mc10.c

r4576	r4577
42	42	mc10_bfff = 0x00;
43	43	mc10_keyboard_strobe = 0x00;
44	44
45		memory_install_readwrite8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM),
	45	memory_install_readwrite8_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM),
46	46	0x4000,   0x4000 + mess_ram_size - 1,   0, 0, SMH_BANK1, SMH_BANK1);
47	47	memory_set_bankptr(machine, 1, mess_ram);
48	48

src/mess/machine/mtx.c

r4576	r4577
220	220	/* set ram bank, for invalid pages a nop-handler will be installed */
221	221	if (ram_page >= mess_ram_size/0x8000)
222	222	{
223		memory_install_readwrite8_handler(cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x4000, 0x7fff, 0, 0, SMH_NOP, SMH_NOP);
224		memory_install_readwrite8_handler(cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x8000, 0xbfff, 0, 0, SMH_NOP, SMH_NOP);
	223	memory_install_readwrite8_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x4000, 0x7fff, 0, 0, SMH_NOP, SMH_NOP);
	224	memory_install_readwrite8_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x8000, 0xbfff, 0, 0, SMH_NOP, SMH_NOP);
225	225	}
226	226	else if (ram_page + 1 == mess_ram_size/0x8000)
227	227	{
228		memory_install_readwrite8_handler(cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x4000, 0x7fff, 0, 0, SMH_NOP, SMH_NOP);
229		memory_install_readwrite8_handler(cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x8000, 0xbfff, 0, 0, SMH_BANK4, SMH_BANK4);
	228	memory_install_readwrite8_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x4000, 0x7fff, 0, 0, SMH_NOP, SMH_NOP);
	229	memory_install_readwrite8_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x8000, 0xbfff, 0, 0, SMH_BANK4, SMH_BANK4);
230	230	memory_set_bank(space->machine, 4, ram_page);
231	231	}
232	232	else
233	233	{
234		memory_install_readwrite8_handler(cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x4000, 0x7fff, 0, 0, SMH_BANK3, SMH_BANK3);
235		memory_install_readwrite8_handler(cpu_get_address_space(space->machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x8000, 0xbfff, 0, 0, SMH_BANK4, SMH_BANK4);
	234	memory_install_readwrite8_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x4000, 0x7fff, 0, 0, SMH_BANK3, SMH_BANK3);
	235	memory_install_readwrite8_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x8000, 0xbfff, 0, 0, SMH_BANK4, SMH_BANK4);
236	236	memory_set_bank(space->machine, 3, ram_page);
237	237	memory_set_bank(space->machine, 4, ram_page);
238	238	}
r4576	r4577
267	267
268	268	/* install handlers for dart interface */
269	269	device = devtag_get_device(machine, "z80dart");
270		space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_IO);
	270	space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_IO);
271	271	memory_install_readwrite8_device_handler(space, device, 0x0c, 0x0d, 0, 0, z80dart_d_r, z80dart_d_w);
272	272	memory_install_readwrite8_device_handler(space, device, 0x0e, 0x0f, 0, 0, z80dart_c_r, z80dart_c_w);
273	273	}

src/mess/machine/mikro80.c

r4576	r4577
60	60	{
61	61	}
62	62
63		static READ8_DEVICE_HANDLER( mikro80_8255_portb_device_r ) { return mikro80_8255_portb_r(cpu_get_address_space(device->machine->cpu[0], ADDRESS_SPACE_PROGRAM), offset); }
64		static READ8_DEVICE_HANDLER( mikro80_8255_portc_device_r ) { return mikro80_8255_portc_r(cpu_get_address_space(device->machine->cpu[0], ADDRESS_SPACE_PROGRAM), offset); }
65		static WRITE8_DEVICE_HANDLER( mikro80_8255_porta_device_w ) { mikro80_8255_porta_w(cpu_get_address_space(device->machine->cpu[0], ADDRESS_SPACE_PROGRAM), offset, data); }
	63	static READ8_DEVICE_HANDLER( mikro80_8255_portb_device_r ) { return mikro80_8255_portb_r(cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM), offset); }
	64	static READ8_DEVICE_HANDLER( mikro80_8255_portc_device_r ) { return mikro80_8255_portc_r(cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM), offset); }
	65	static WRITE8_DEVICE_HANDLER( mikro80_8255_porta_device_w ) { mikro80_8255_porta_w(cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM), offset, data); }
66	66
67	67	const ppi8255_interface mikro80_ppi8255_interface =
68	68	{

src/mess/machine/mz80.c

r4576	r4577
84	84
85	85	static PIT8253_OUTPUT_CHANGED( pit_out2_changed )
86	86	{
87		cpu_set_input_line(device->machine->cpu[0], 0, HOLD_LINE);
	87	cputag_set_input_line(device->machine, "maincpu", 0, HOLD_LINE);
88	88	}
89	89
90	90	const ppi8255_interface mz80k_8255_int =

src/mess/machine/kc.c

r4576	r4577
150	150	#if 0
151	151	static void kc85_disc_hw_ctc_interrupt(int state)
152	152	{
153		cpu_set_input_line(machine->cpu[1], 0, state);
	153	cputag_set_input_line(machine, "disc", 0, state);
154	154	}
155	155	#endif
156	156
r4576	r4577
235	235
236	236	static TIMER_CALLBACK(kc85_disk_reset_timer_callback)
237	237	{
238		cpu_set_reg(machine->cpu[1], REG_GENPC, 0x0f000);
239		cpu_set_reg(machine->cpu[0], REG_GENPC, 0x0f000);
	238	cpu_set_reg(cputag_get_cpu(machine, "disc"), REG_GENPC, 0x0f000);
	239	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), REG_GENPC, 0x0f000);
240	240	}
241	241
242	242	static void kc_disc_interface_init(running_machine *machine)
r4576	r4577
244	244	timer_set(machine, attotime_zero, NULL, 0, kc85_disk_reset_timer_callback);
245	245
246	246	/* hold cpu at reset */
247		cpu_set_input_line(machine->cpu[1], INPUT_LINE_RESET, ASSERT_LINE);
	247	cputag_set_input_line(machine, "disc", INPUT_LINE_RESET, ASSERT_LINE);
248	248	}
249	249
250	250	/*****************/
r4576	r4577
1132	1132
1133	1133	static void kc85_4_update_0x08000(running_machine *machine)
1134	1134	{
1135		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1135	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1136	1136	unsigned char *ram_page;
1137	1137
1138	1138	if (kc85_pio_data[1] & (1<<5))
r4576	r4577
1201	1201	/* update status of memory area 0x0000-0x03fff */
1202	1202	static void kc85_4_update_0x00000(running_machine *machine)
1203	1203	{
1204		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1204	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1205	1205
1206	1206	/* access ram? */
1207	1207	if (kc85_pio_data[0] & (1<<1))
r4576	r4577
1244	1244	/* update status of memory area 0x4000-0x07fff */
1245	1245	static void kc85_4_update_0x04000(running_machine *machine)
1246	1246	{
1247		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1247	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1248	1248	read8_space_func rh;
1249	1249	write8_space_func wh;
1250	1250
r4576	r4577
1295	1295	/* update memory address 0x0c000-0x0e000 */
1296	1296	static void kc85_4_update_0x0c000(running_machine *machine)
1297	1297	{
1298		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1298	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1299	1299	read8_space_func rh;
1300	1300
1301	1301	if (kc85_86_data & (1<<7))
r4576	r4577
1337	1337	/* update memory address 0x0e000-0x0ffff */
1338	1338	static void kc85_4_update_0x0e000(running_machine *machine)
1339	1339	{
1340		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1340	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1341	1341	read8_space_func rh;
1342	1342
1343	1343	if (kc85_pio_data[0] & (1<<0))
r4576	r4577
1453	1453	/* update memory region 0x0c000-0x0e000 */
1454	1454	static void kc85_3_update_0x0c000(running_machine *machine)
1455	1455	{
1456		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1456	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1457	1457	read8_space_func rh;
1458	1458
1459	1459	if (kc85_pio_data[0] & (1<<7))
r4576	r4577
1476	1476	/* update memory address 0x0e000-0x0ffff */
1477	1477	static void kc85_3_update_0x0e000(running_machine *machine)
1478	1478	{
1479		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1479	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1480	1480	read8_space_func rh;
1481	1481
1482	1482	if (kc85_pio_data[0] & (1<<0))
r4576	r4577
1501	1501	for write operations */
1502	1502	static void kc85_3_update_0x00000(running_machine *machine)
1503	1503	{
1504		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1504	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1505	1505	read8_space_func rh;
1506	1506	write8_space_func wh;
1507	1507
r4576	r4577
1551	1551	/* SMH_BANK3 is used for read, SMH_BANK8 is used for write */
1552	1552	static void kc85_3_update_0x08000(running_machine *machine)
1553	1553	{
1554		const address_space *space = cpu_get_address_space( machine->cpu[0], ADDRESS_SPACE_PROGRAM );
	1554	const address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
1555	1555	read8_space_func rh;
1556	1556	write8_space_func wh;
1557	1557	unsigned char *ram_page;
r4576	r4577
1699	1699
1700	1700	static TIMER_CALLBACK(kc85_reset_timer_callback)
1701	1701	{
1702		cpu_set_reg(machine->cpu[0], REG_GENPC, 0x0f000);
	1702	cpu_set_reg(cputag_get_cpu(machine, "maincpu"), REG_GENPC, 0x0f000);
1703	1703	}
1704	1704
1705	1705	READ8_HANDLER ( kc85_pio_data_r )
r4576	r4577
1738	1738
1739	1739	static void kc85_pio_interrupt(const device_config *device, int state)
1740	1740	{
1741		cpu_set_input_line(device->machine->cpu[0], 0, state);
	1741	cputag_set_input_line(device->machine, "maincpu", 0, state);
1742	1742	}
1743	1743
1744	1744	static void kc85_ctc_interrupt(const device_config *device, int state)
1745	1745	{
1746		cpu_set_input_line(device->machine->cpu[0], 1, state);
	1746	cputag_set_input_line(device->machine, "maincpu", 1, state);
1747	1747	}
1748	1748
1749	1749	/* callback for ardy output from PIO */

src/mess/drivers/mac.c

r4576	r4577
68	68
69	69	static READ8_HANDLER(mac_asc_r)
70	70	{
71		logerror("ASC: Read @ %x (PC %x)\n", offset, cpu_get_pc(space->machine->cpu[0]));
	71	logerror("ASC: Read @ %x (PC %x)\n", offset, cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")));
72	72
73	73	return mac_asc_regs[offset];
74	74	}
75	75
76	76	static WRITE8_HANDLER(mac_asc_w)
77	77	{
78		logerror("ASC: %02x to %x (PC %x)\n", data, offset, cpu_get_pc(space->machine->cpu[0]));
	78	logerror("ASC: %02x to %x (PC %x)\n", data, offset, cpu_get_pc(cputag_get_cpu(space->machine, "maincpu")));
79	79
80	80	mac_asc_regs[offset] = data;
81	81	}
r4576	r4577
448	448	COMP( 1987,   macse,    0,      0,   macse,  macplus,  macse,          macse,      "Apple Computer",   "Macintosh SE",  0 )
449	449	COMP( 1990,   macclasc, 0,      0,   macse,  macplus,  macclassic,          macse,      "Apple Computer",   "Macintosh Classic",  GAME_NOT_WORKING )
450	450	COMP( 1990,   maclc,    0,      0,  maclc,    macplus,  maclc,      maclc,      "Apple Computer",   "Macintosh LC",  GAME_NOT_WORKING )
451

src/mess/drivers/mk1.c

r4576	r4577
164	164
165	165	static void mk1_interrupt( const device_config *device, UINT16 addr, int level )
166	166	{
167		cpu_set_input_line_vector(device->machine->cpu[0], 0, addr );
168		cpu_set_input_line(device->machine->cpu[0], 0, level ? F8_INT_INTR : F8_INT_NONE );
	167	cpu_set_input_line_vector(cputag_get_cpu(device->machine, "maincpu"), 0, addr );
	168	cputag_set_input_line(device->machine,"maincpu", 0, level ? F8_INT_INTR : F8_INT_NONE );
169	169	}
170	170
171	171

src/mess/drivers/mpf1.c

r4576	r4577
63	63	{
64	64	// halt-LED; the red one, is turned on when the processor is halted
65	65	// TODO: processor seems to halt, but restarts(?) at 0x0000 after a while -> fix
66		led_halt = (UINT8) device_get_info_int(machine->cpu[0], CPUINFO_INT_REGISTER + Z80_HALT);
	66	led_halt = (UINT8) devtag_get_info_int(machine, "maincpu", CPUINFO_INT_REGISTER + Z80_HALT);
67	67	set_led_status(1, led_tone);
68	68	}
69	69
r4576	r4577
368	368	The next statement converts this to the following assignment: (which is compatible with draw_led())
369	369	bit      7 6 5 4 3 2 1 0
370	370	segment  p g f e d c b a */
371		if( data | ( cpu_get_pc(device->machine->cpu[0]) != 0x63C ) )
	371	if( data | ( cpu_get_pc(cputag_get_cpu(device->machine, "maincpu")) != 0x63C ) )
372	372	{
373	373	data = ( (data & 0x08) >> 3 ) |
374	374	( (data & 0x10) >> 3 ) |
r4576	r4577
435	435
436	436	static TIMER_CALLBACK( irq0_callback )
437	437	{
438		irq0_line_hold( machine->cpu[0] );
	438	irq0_line_hold( cputag_get_cpu(machine, "maincpu") );
439	439	}
440	440
441	441	static MACHINE_RESET( mpf1 )

src/mess/drivers/mk2.c

r4576	r4577
155	155	dac_data_w(dac_device,newdata&1?80:0);
156	156	mk2_led[4]|=newdata;
157	157
158		cpu_set_input_line( device->machine->cpu[0], M6502_IRQ_LINE, (newdata & 0x80) ? CLEAR_LINE : ASSERT_LINE );
	158	cputag_set_input_line( device->machine, "maincpu", M6502_IRQ_LINE, (newdata & 0x80) ? CLEAR_LINE : ASSERT_LINE );
159	159	}
160	160
161	161

src/mess/drivers/mtx.c

r4576	r4577
240	240
241	241	static void mtx_ctc_interrupt(const device_config *device, int state)
242	242	{
243		cpu_set_input_line(device->machine->cpu[0], 0, state);
	243	cputag_set_input_line(device->machine, "maincpu", 0, state);
244	244	}
245	245
246	246

src/mess/drivers/mephisto.c

r4576	r4577
175	175	static TIMER_CALLBACK( update_nmi )
176	176	{
177	177	const device_config *speaker = devtag_get_device(machine, "beep");
178		cpu_set_input_line(machine->cpu[0], INPUT_LINE_NMI,PULSE_LINE);
	178	cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI,PULSE_LINE);
179	179	// dac_data_w(0,led_status&64?128:0);
180	180	beep_set_state(speaker,led_status&64?1:0);
181	181	}
r4576	r4577
185	185	lcd_shift_counter=3;
186	186	// timer_pulse(machine, ATTOTIME_IN_HZ(60), NULL, 0, update_leds);
187	187	timer_pulse(machine, ATTOTIME_IN_HZ(600), NULL, 0, update_nmi);
188		// cpu_set_input_line(machine->cpu[0], M65C02_IRQ_LINE,CLEAR_LINE);
	188	// cputag_set_input_line(machine, "maincpu", M65C02_IRQ_LINE,CLEAR_LINE);
189	189	//beep_set_frequency(0, 4000);
190	190	}
191	191
192	192
193	193	static MACHINE_RESET( mephisto )
194	194	{
195		lcd_shift_counter=3;
	195	lcd_shift_counter = 3;
196	196	}
197	197
198	198

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