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r4375 Tuesday 3rd March, 2009 at 10:51:49 UTC by Dirk Best
[MZ700] Memory mapping rewrite, mz800 updates, cleanups

[src/mess/drivers]	mz700.c
[src/mess/includes]	mz700.h
[src/mess/machine]	mz700.c
[src/mess/video]	mz700.c

src/mess/video/mz700.c

r4374	r4375
37	37
38	38	for (i = 0; i < 8; i++)
39	39	colortable_palette_set_color(machine->colortable, i, MAKE_RGB((i & 2) ? 0xff : 0x00, (i & 4) ? 0xff : 0x00, (i & 1) ? 0xff : 0x00));
40
	40
41	41	for (i = 0; i < 256; i++)
42	42	{
43	43	colortable_entry_set_value(machine->colortable, i*2, i & 7);
r4374	r4375
55	55	for(offs = 0; offs < 40*25; offs++)
56	56	{
57	57	int sx, sy, code, color;
58		sy = (offs / 40) * 8;
	58
	59	sy = (offs / 40) * 8;
59	60	sx = (offs % 40) * 8;
	61
60	62	color = colorram[offs];
61	63	code = videoram[offs] | (color & 0x80) << 1;
62		drawgfx(bitmap, screen->machine->gfx[0], code, color, 0, 0, sx, sy, cliprect, TRANSPARENCY_NONE, 0);
	64
	65	drawgfx_opaque(bitmap, cliprect, screen->machine->gfx[0], code, color, 0, 0, sx, sy);
63	66	}
64	67
65	68	return 0;
66	69	}
	70
	71
	72	/***************************************************************************
	73	MZ-800
	74	***************************************************************************/
	75
	76	VIDEO_START( mz800 )
	77	{
	78	mz_state *mz = machine->driver_data;
	79	gfx_element_set_source(machine->gfx[0], mz->cgram);
	80	}
	81
	82	VIDEO_UPDATE( mz800 )
	83	{
	84	mz_state *mz = screen->machine->driver_data;
	85
	86	bitmap_fill(bitmap, cliprect, get_black_pen(screen->machine));
	87
	88	if (mz->mz700_mode)
	89	return VIDEO_UPDATE_CALL(mz700);
	90	else
	91	{
	92	if (mz->hires_mode)
	93	{
	94
	95	}
	96	else
	97	{
	98	int x, y;
	99	UINT8 *start_addr = videoram;
	100
	101	for (x = 0; x < 40; x++)
	102	{
	103	for (y = 0; y < 200; y++)
	104	{
	105	*BITMAP_ADDR16(bitmap, y, x * 8 + 0) = BIT(start_addr[x * 8 + y], 0);
	106	*BITMAP_ADDR16(bitmap, y, x * 8 + 1) = BIT(start_addr[x * 8 + y], 1);
	107	*BITMAP_ADDR16(bitmap, y, x * 8 + 2) = BIT(start_addr[x * 8 + y], 2);
	108	*BITMAP_ADDR16(bitmap, y, x * 8 + 3) = BIT(start_addr[x * 8 + y], 3);
	109	*BITMAP_ADDR16(bitmap, y, x * 8 + 4) = BIT(start_addr[x * 8 + y], 4);
	110	*BITMAP_ADDR16(bitmap, y, x * 8 + 5) = BIT(start_addr[x * 8 + y], 5);
	111	*BITMAP_ADDR16(bitmap, y, x * 8 + 6) = BIT(start_addr[x * 8 + y], 6);
	112	*BITMAP_ADDR16(bitmap, y, x * 8 + 7) = BIT(start_addr[x * 8 + y], 7);
	113	}
	114	}
	115	}
	116
	117	return 0;
	118	}
	119	}
	120
	121	/***************************************************************************
	122	CGRAM
	123	***************************************************************************/
	124
	125	WRITE8_HANDLER( mz800_cgram_w )
	126	{
	127	mz_state *mz = space->machine->driver_data;
	128	mz->cgram[offset] = data;
	129
	130	gfx_element_mark_dirty(space->machine->gfx[0], offset/8);
	131	}

src/mess/includes/mz700.h

r4374	r4375
14	14
15	15	#include "machine/8255ppi.h"
16	16	#include "machine/pit8253.h"
	17	#include "machine/z80pio.h"
17	18
18	19
19		typedef struct _mz700_state mz700_state;
20		struct _mz700_state
	20	typedef struct _mz_state mz_state;
	21	struct _mz_state
21	22	{
	23	int mz700;            /* 1 if running on an mz700 */
	24
	25	const device_config *pit;
	26	const device_config *ppi;
	27
22	28	int cursor_timer;
23	29	int other_timer;
	30
	31	int intmsk;   /* PPI8255 pin PC2 */
	32
	33	int mz700_ram_lock;      /* 1 if ram lock is active */
	34	int mz700_ram_vram;      /* 1 if vram is banked in */
	35
	36	/* mz800 specific */
	37	UINT8 *cgram;
	38
	39	int mz700_mode;         /* 1 if in mz700 mode */
	40	int mz800_ram_lock;      /* 1 if lock is active */
	41	int mz800_ram_monitor;   /* 1 if monitor rom banked in */
	42
	43	int hires_mode;         /* 1 if in 640x200 mode */
	44	int screen;          /* screen designation */
24	45	};
25	46
26	47
27	48	/*----------- defined in machine/mz700.c -----------*/
28	49
29	50	extern const struct pit8253_config mz700_pit8253_config;
	51	extern const struct pit8253_config mz800_pit8253_config;
30	52	extern const ppi8255_interface mz700_ppi8255_interface;
	53	extern const z80pio_interface mz800_z80pio_config;
31	54
32	55	DRIVER_INIT( mz700 );
	56	DRIVER_INIT( mz800 );
	57	MACHINE_START( mz700 );
33	58
34		WRITE8_HANDLER( mz700_bank_w );
	59	/* bank switching */
	60	WRITE8_HANDLER( mz700_bank_0_w );
	61	WRITE8_HANDLER( mz800_bank_0_w );
	62	WRITE8_HANDLER( mz_bank_1_w );
	63	WRITE8_HANDLER( mz_bank_2_w );
	64	WRITE8_HANDLER( mz_bank_3_w );
	65	WRITE8_HANDLER( mz_bank_4_w );
	66	WRITE8_HANDLER( mz_bank_5_w );
	67	WRITE8_HANDLER( mz_bank_6_w );
35	68
	69	/* bankswitching, mz800 only */
	70	READ8_HANDLER( mz800_bank_0_r );
	71	READ8_HANDLER( mz800_bank_1_r );
	72
	73
36	74	READ8_HANDLER( mz800_crtc_r );
37		READ8_HANDLER( mz800_bank_r );
38	75	READ8_HANDLER( mz800_ramdisk_r );
39	76
40	77	WRITE8_HANDLER( mz800_write_format_w );
41	78	WRITE8_HANDLER( mz800_read_format_w );
42	79	WRITE8_HANDLER( mz800_display_mode_w );
43	80	WRITE8_HANDLER( mz800_scroll_border_w );
44		WRITE8_HANDLER( mz800_bank_w );
45	81	WRITE8_HANDLER( mz800_ramdisk_w );
46	82	WRITE8_HANDLER( mz800_ramaddr_w );
47	83	WRITE8_HANDLER( mz800_palette_w );
48	84
49		DRIVER_INIT( mz800 );
50	85
51
52	86	/*----------- defined in video/mz700.c -----------*/
53	87
54	88	PALETTE_INIT( mz700 );
55	89	VIDEO_UPDATE( mz700 );
	90	VIDEO_START( mz800 );
	91	VIDEO_UPDATE( mz800 );
	92	WRITE8_HANDLER( mz800_cgram_w );
56	93
57	94
58	95	#endif /* MZ700_H_ */

src/mess/machine/mz700.c

r4374	r4375
9	9	*
10	10	*****************************************************************************/
11	11
12		/* Core includes */
13	12	#include "driver.h"
14
15		/* Components */
	13	#include "includes/mz700.h"
16	14	#include "cpu/z80/z80.h"
17	15	#include "machine/pit8253.h"
18	16	#include "machine/8255ppi.h"
19		#include "sound/speaker.h"
	17	#include "machine/z80pio.h"
20	18	#include "machine/74145.h"
21
22		#include "includes/mz700.h"
23
24		/* Devices */
	19	#include "machine/ctronics.h"
	20	#include "sound/speaker.h"
25	21	#include "devices/cassette.h"
26	22
27	23
28	24	#ifndef VERBOSE
29		#define VERBOSE
	25	#define VERBOSE 1
30	26	#endif
31	27
32	28	#define LOG(N,M,A,mac)   \
r4374	r4375
56	52	};
57	53
58	54
59		static int pio_port_c_output;
60
61	55	static PIT8253_OUTPUT_CHANGED( pit_out0_changed );
62	56	static PIT8253_OUTPUT_CHANGED( pit_out1_changed );
63	57	static PIT8253_OUTPUT_CHANGED( pit_irq_2 );
r4374	r4375
65	59	const struct pit8253_config mz700_pit8253_config =
66	60	{
67	61	{
68		/* clockin     irq callback     */
69		{ 1108800.0,  pit_out0_changed },
70		{   15611.0,  pit_out1_changed },
71		{        0,  pit_irq_2        },
	62	/* clockin              callback */
	63	{ XTAL_17_73447MHz/20, pit_out0_changed },
	64	{             15611.0, pit_out1_changed },
	65	{                  0, pit_irq_2        },
72	66	}
73	67	};
74	68
	69	const struct pit8253_config mz800_pit8253_config =
	70	{
	71	{
	72	/* clockin              callback */
	73	{ XTAL_17_73447MHz/16, pit_out0_changed },
	74	{             15611.0, pit_out1_changed },
	75	{                  0, pit_irq_2        },
	76	}
	77	};
75	78
	79
	80	/***************************************************************************
	81	INITIALIZATIoN
	82	***************************************************************************/
	83
76	84	DRIVER_INIT( mz700 )
77	85	{
78		videoram_size = 0x5000;
	86	mz_state *mz = machine->driver_data;
	87	mz->mz700 = TRUE;
	88	mz->mz700_mode = TRUE;
	89
	90	videoram_size = 0x800;
79	91	videoram = auto_malloc(videoram_size);
80	92	colorram = auto_malloc(0x800);
	93	}
81	94
82		mz700_bank_w(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 4, 0);
	95	DRIVER_INIT( mz800 )
	96	{
	97	mz_state *mz = machine->driver_data;
	98	mz->mz700 = FALSE;
	99	mz->mz700_mode = FALSE;
	100
	101	/* video ram */
	102	videoram_size = 0x4000;
	103	videoram = auto_malloc(videoram_size);
	104	colorram = videoram + 0x800;
	105
	106	/* character generator ram */
	107	mz->cgram = auto_malloc(0x1000);
83	108	}
84	109
	110	MACHINE_START( mz700 )
	111	{
	112	mz_state *mz = machine->driver_data;
85	113
	114	mz->pit = devtag_get_device(machine, PIT8253, "pit8253");
	115	mz->ppi = devtag_get_device(machine, PPI8255, "ppi8255");
	116
	117	/* reset memory map to defaults */
	118	mz_bank_4_w(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0, 0);
	119	}
	120
	121
	122	/***************************************************************************
	123	MMIO
	124	***************************************************************************/
	125
	126	READ8_HANDLER( mz700_e008_r )
	127	{
	128	mz_state *mz = space->machine->driver_data;
	129	UINT8 data = 0;
	130
	131	data |= mz->other_timer;
	132	data |= input_port_read(space->machine, "JOY");
	133	data |= video_screen_get_hblank(space->machine->primary_screen);
	134
	135	LOG(1, "mz700_e008_r", ("%02X\n", data), space->machine);
	136
	137	return data;
	138	}
	139
	140
	141	/***************************************************************************
	142	BANK SWITCHING
	143	***************************************************************************/
	144
	145	READ8_HANDLER( mz800_bank_0_r )
	146	{
	147	const address_space *spc = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	148	mz_state *mz = space->machine->driver_data;
	149
	150	/* switch in cgrom */
	151	memory_install_readwrite8_handler(spc, 0x1000, 0x1fff, 0, 0, SMH_BANK(2), SMH_NOP);
	152	memory_set_bankptr(space->machine, 2, memory_region(space->machine, "monitor") + 0x1000);
	153
	154	if (mz->mz700_mode)
	155	{
	156	/* cgram from 0xc000 to 0xcfff */
	157	memory_install_readwrite8_handler(spc, 0xc000, 0xcfff, 0, 0, SMH_BANK(6), mz800_cgram_w);
	158	memory_set_bankptr(space->machine, 6, mz->cgram);
	159	}
	160	else
	161	{
	162	if (mz->hires_mode)
	163	{
	164	/* vram from 0x8000 to 0xbfff */
	165	memory_install_readwrite8_handler(spc, 0x8000, 0xbfff, 0, 0, SMH_BANK(4), SMH_BANK(4));
	166	memory_set_bankptr(space->machine, 4, videoram);
	167	}
	168	else
	169	{
	170	/* vram from 0x8000 to 0x9fff */
	171	memory_install_readwrite8_handler(spc, 0x8000, 0x9fff, 0, 0, SMH_BANK(4), SMH_BANK(4));
	172	memory_set_bankptr(space->machine, 4, videoram);
	173
	174	/* ram from 0xa000 to 0xbfff */
	175	memory_install_readwrite8_handler(spc, 0xa000, 0xbfff, 0, 0, SMH_BANK(5), SMH_BANK(5));
	176	memory_set_bankptr(space->machine, 5, mess_ram + 0xa000);
	177	}
	178	}
	179
	180	return 0xff;
	181	}
	182
	183	WRITE8_HANDLER( mz700_bank_0_w )
	184	{
	185	const address_space *spc = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	186
	187	memory_install_readwrite8_handler(spc, 0x0000, 0x0fff, 0, 0, SMH_BANK(1), SMH_BANK(1));
	188	memory_set_bankptr(space->machine, 1, mess_ram);
	189	}
	190
	191	WRITE8_HANDLER( mz800_bank_0_w )
	192	{
	193	const address_space *spc = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	194
	195	memory_install_readwrite8_handler(spc, 0x0000, 0x7fff, 0, 0, SMH_BANK(1), SMH_BANK(1));
	196	memory_set_bankptr(space->machine, 1, mess_ram);
	197	}
	198
	199	READ8_HANDLER( mz800_bank_1_r )
	200	{
	201	const address_space *spc = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	202	mz_state *mz = space->machine->driver_data;
	203
	204	/* switch in ram from 0x1000 to 0x1fff */
	205	memory_install_readwrite8_handler(spc, 0x1000, 0x1fff, 0x1000, 0, SMH_BANK(2), SMH_BANK(2));
	206	memory_set_bankptr(space->machine, 2, mess_ram + 0x1000);
	207
	208	if (mz->mz700_mode)
	209	{
	210	/* ram from 0xc000 to 0xcfff */
	211	memory_install_readwrite8_handler(spc, 0xc000, 0xcfff, 0, 0, SMH_BANK(6), SMH_BANK(6));
	212	memory_set_bankptr(space->machine, 6, mess_ram + 0xc000);
	213	}
	214	else
	215	{
	216	/* ram from 0x8000 to 0xbfff */
	217	memory_install_readwrite8_handler(spc, 0x8000, 0xbfff, 0, 0, SMH_BANK(4), SMH_BANK(4));
	218	memory_set_bankptr(space->machine, 4, mess_ram + 0x8000);
	219	}
	220
	221	return 0xff;
	222	}
	223
	224	WRITE8_HANDLER( mz_bank_1_w )
	225	{
	226	const address_space *spc = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	227	mz_state *mz = space->machine->driver_data;
	228
	229	if (mz->mz700_mode)
	230	{
	231	/* switch in ram when not locked */
	232	if (!mz->mz700_ram_lock)
	233	{
	234	memory_install_readwrite8_handler(spc, 0xd000, 0xffff, 0, 0, SMH_BANK(7), SMH_BANK(7));
	235	memory_set_bankptr(space->machine, 7, mess_ram + 0xd000);
	236	mz->mz700_ram_vram = FALSE;
	237	}
	238	}
	239	else
	240	{
	241	/* switch in ram when not locked */
	242	if (!mz->mz800_ram_lock)
	243	{
	244	memory_install_readwrite8_handler(spc, 0xe000, 0xffff, 0, 0, SMH_BANK(8), SMH_BANK(8));
	245	memory_set_bankptr(space->machine, 8, mess_ram + 0xe000);
	246	mz->mz800_ram_monitor = FALSE;
	247	}
	248	}
	249	}
	250
	251	WRITE8_HANDLER( mz_bank_2_w )
	252	{
	253	const address_space *spc = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	254
	255	memory_install_readwrite8_handler(spc, 0x0000, 0x0fff, 0, 0, SMH_BANK(1), SMH_NOP);
	256	memory_set_bankptr(space->machine, 1, memory_region(space->machine, "monitor"));
	257	}
	258
	259	WRITE8_HANDLER( mz_bank_3_w )
	260	{
	261	const address_space *spc = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	262	mz_state *mz = space->machine->driver_data;
	263
	264	if (mz->mz700_mode)
	265	{
	266	if (!mz->mz700_ram_lock)
	267	{
	268	/* switch in videoram */
	269	memory_install_readwrite8_handler(spc, 0xd000, 0xd7ff, 0, 0, SMH_BANK(7), SMH_BANK(7));
	270	memory_set_bankptr(space->machine, 7, videoram);
	271
	272	/* switch in colorram */
	273	memory_install_readwrite8_handler(spc, 0xd800, 0xdfff, 0, 0, SMH_BANK(9), SMH_BANK(9));
	274	memory_set_bankptr(space->machine, 9, colorram);
	275
	276	mz->mz700_ram_vram = TRUE;
	277
	278	/* switch in memory mapped i/o devices */
	279	if (mz->mz700)
	280	{
	281	memory_install_readwrite8_device_handler(spc, mz->ppi, 0xe000, 0xfff3, 0, 0x1ff0, ppi8255_r, ppi8255_w);
	282	memory_install_readwrite8_device_handler(spc, mz->pit, 0xe004, 0xfff7, 0, 0x1ff0, pit8253_r, pit8253_w);
	283	memory_install_read8_handler(spc, 0xe008, 0xfff8, 0, 0x1ff0, mz700_e008_r);
	284	memory_install_write8_device_handler(spc, mz->pit, 0xe008, 0xfff8, 0, 0x1ff0, pit8253_gate_w);
	285	}
	286	else
	287	{
	288	memory_install_readwrite8_device_handler(spc, mz->ppi, 0xe000, 0xe003, 0, 0, ppi8255_r, ppi8255_w);
	289	memory_install_readwrite8_device_handler(spc, mz->pit, 0xe004, 0xe007, 0, 0, pit8253_r, pit8253_w);
	290	memory_install_read8_handler(spc, 0xe008, 0xe008, 0, 0, mz700_e008_r);
	291	memory_install_write8_device_handler(spc, mz->pit, 0xe008, 0xe008, 0, 0, pit8253_gate_w);
	292	}
	293	}
	294	}
	295	else
	296	{
	297	if (!mz->mz800_ram_lock)
	298	{
	299	/* switch in mz800 monitor rom if not locked */
	300	memory_install_readwrite8_handler(spc, 0xe000, 0xffff, 0, 0, SMH_BANK(8), SMH_NOP);
	301	memory_set_bankptr(space->machine, 8, memory_region(space->machine, "monitor") + 0x2000);
	302	mz->mz800_ram_monitor = TRUE;
	303	}
	304	}
	305	}
	306
	307	WRITE8_HANDLER( mz_bank_4_w )
	308	{
	309	const address_space *spc = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	310	mz_state *mz = space->machine->driver_data;
	311
	312	if (mz->mz700_mode)
	313	{
	314	mz->mz700_ram_lock = FALSE;      /* reset lock */
	315	mz_bank_2_w(space, 0, 0);   /* switch in monitor rom */
	316	mz_bank_3_w(space, 0, 0);   /* switch in videoram, colorram, and mmio */
	317
	318	/* rest is ram is always ram in mz700 mode */
	319	memory_install_readwrite8_handler(spc, 0x1000, 0xcfff, 0, 0, SMH_BANK(2), SMH_BANK(2));
	320	memory_set_bankptr(space->machine, 2, mess_ram + 0x1000);
	321	}
	322	else
	323	{
	324	/* monitor rom and cgrom */
	325	memory_install_readwrite8_handler(spc, 0x0000, 0x1fff, 0, 0, SMH_BANK(1), SMH_NOP);
	326	memory_set_bankptr(space->machine, 1, memory_region(space->machine, "monitor"));
	327
	328	/* ram from 0x2000 to 0x7fff */
	329	memory_install_readwrite8_handler(spc, 0x2000, 0x7fff, 0, 0, SMH_BANK(3), SMH_BANK(3));
	330	memory_set_bankptr(space->machine, 3, mess_ram);
	331
	332	if (mz->hires_mode)
	333	{
	334	/* vram from 0x8000 to 0xbfff */
	335	memory_install_readwrite8_handler(spc, 0x8000, 0xbfff, 0, 0, SMH_BANK(4), SMH_BANK(4));
	336	memory_set_bankptr(space->machine, 4, videoram);
	337	}
	338	else
	339	{
	340	/* vram from 0x8000 to 0x9fff */
	341	memory_install_readwrite8_handler(spc, 0x8000, 0x9fff, 0, 0, SMH_BANK(4), SMH_BANK(4));
	342	memory_set_bankptr(space->machine, 4, videoram);
	343
	344	/* ram from 0xa000 to 0xbfff */
	345	memory_install_readwrite8_handler(spc, 0xa000, 0xbfff, 0, 0, SMH_BANK(5), SMH_BANK(5));
	346	memory_set_bankptr(space->machine, 5, mess_ram + 0xa000);
	347	}
	348
	349	/* ram from 0xc000 to 0xdfff */
	350	memory_install_readwrite8_handler(spc, 0xc000, 0xdfff, 0, 0, SMH_BANK(6), SMH_BANK(6));
	351	memory_set_bankptr(space->machine, 6, mess_ram + 0xc000);
	352
	353	/* mz800 monitor rom from 0xe000 to 0xffff */
	354	memory_install_readwrite8_handler(spc, 0xe000, 0xffff, 0, 0, SMH_BANK(8), SMH_NOP);
	355	memory_set_bankptr(space->machine, 8, memory_region(space->machine, "monitor") + 0x2000);
	356	mz->mz800_ram_monitor = TRUE;
	357
	358	mz->mz800_ram_lock = FALSE; /* reset lock? */
	359	}
	360	}
	361
	362	WRITE8_HANDLER( mz_bank_5_w )
	363	{
	364	const address_space *spc = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	365	mz_state *mz = space->machine->driver_data;
	366
	367	if (mz->mz700_mode)
	368	{
	369	/* prevent access from 0xd000 to 0xffff */
	370	mz->mz700_ram_lock = TRUE;
	371	memory_install_readwrite8_handler(spc, 0xd000, 0xffff, 0, 0, SMH_NOP, SMH_NOP);
	372	}
	373	else
	374	{
	375	/* prevent access from 0xe000 to 0xffff */
	376	mz->mz800_ram_lock = TRUE;
	377	memory_install_readwrite8_handler(spc, 0xe000, 0xffff, 0, 0, SMH_NOP, SMH_NOP);
	378	}
	379	}
	380
	381	WRITE8_HANDLER( mz_bank_6_w )
	382	{
	383	mz_state *mz = space->machine->driver_data;
	384
	385	if (mz->mz700_mode)
	386	{
	387	mz->mz700_ram_lock = FALSE;
	388
	389	/* restore access */
	390	if (mz->mz700_ram_vram)
	391	mz_bank_3_w(space, 0, 0);
	392	else
	393	mz_bank_1_w(space, 0, 0);
	394	}
	395	else
	396	{
	397	mz->mz800_ram_lock = FALSE;
	398
	399	/* restore access from 0xe000 to 0xffff */
	400	if (mz->mz800_ram_monitor)
	401	mz_bank_3_w(space, 0, 0);
	402	else
	403	mz_bank_1_w(space, 0, 0);
	404	}
	405	}
	406
	407
86	408	/************************ PIT ************************************************/
87	409
88	410	/* Timer 0 is the clock for the speaker output */
89	411	static PIT8253_OUTPUT_CHANGED( pit_out0_changed )
90	412	{
91	413	const device_config *speaker = devtag_get_device(device->machine, SOUND, "speaker");
92		speaker_level_w( speaker, state ? 1 : 0 );
	414	speaker_level_w(speaker, state ? 1 : 0);
93	415	}
94	416
95	417
96	418	/* Timer 1 is the clock for timer 2 clock input */
97	419	static PIT8253_OUTPUT_CHANGED( pit_out1_changed )
98	420	{
99		pit8253_set_clock_signal( device, 2, state );
	421	pit8253_set_clock_signal(device, 2, state);
100	422	}
101	423
102	424
103	425	/* timer 2 is the AM/PM (12 hour) interrupt */
104	426	static PIT8253_OUTPUT_CHANGED( pit_irq_2 )
105	427	{
106		/* INTMSK: interrupt enabled? */
107		if (pio_port_c_output & 0x04)
108		cpu_set_input_line(device->machine->cpu[0], 0, HOLD_LINE);
	428	mz_state *mz = device->machine->driver_data;
	429
	430	if (mz->intmsk)
	431	cputag_set_input_line(device->machine, "maincpu", 0, ASSERT_LINE);
109	432	}
110	433
111		/************************ PIO ************************************************/
112	434
	435	/***************************************************************************
	436	8255 PPI
	437	***************************************************************************/
	438
113	439	static READ8_DEVICE_HANDLER( pio_port_b_r )
114	440	{
115	441	int key_line = ttl74145_r(device, 0, 0);
r4374	r4375
141	467	static READ8_DEVICE_HANDLER( pio_port_c_r )
142	468	{
143	469	const device_config *cas = devtag_get_device(device->machine, CASSETTE, "cassette");
144		mz700_state *mz700 = device->machine->driver_data;
145		UINT8 data = pio_port_c_output & 0x0f;
	470	mz_state *mz = device->machine->driver_data;
	471	UINT8 data = 0;
146	472
147	473	/* note: this is actually connected to Q output of the motor-control flip-flop (see below) */
148	474	if ((cassette_get_state(cas) & CASSETTE_MASK_UISTATE) != CASSETTE_STOPPED)
r4374	r4375
151	477	if (cassette_input(cas) > 0.0038)
152	478	data |= 0x20;       /* set the RDATA status */
153	479
154		data |= mz700->cursor_timer << 6;
	480	data |= mz->cursor_timer << 6;
155	481	data |= video_screen_get_vblank(device->machine->primary_screen) << 7;
156	482
157	483	LOG(2,"mz700_pio_port_c_r",("%02X\n", data),device->machine);
r4374	r4375
205	531	LOG(2,"mz700_pio_port_c_w",("%02X\n", data),device->machine);
206	532
207	533	cassette_output(devtag_get_device(device->machine, CASSETTE, "cassette"), (data & 0x02) ? +1.0 : -1.0);
208
209		pio_port_c_output = data;
210	534	}
211	535
212		/************************ MMIO ***********************************************/
213	536
214		READ8_HANDLER( mz700_e008_r )
215		{
216		mz700_state *mz700 = space->machine->driver_data;
217		UINT8 data = 0;
	537	/******************************************************************************
	538	*   Sharp MZ800
	539	*
	540	*
	541	******************************************************************************/
218	542
219		data |= mz700->other_timer;
220		data |= input_port_read(space->machine, "JOY");   /* get joystick ports */
221		data |= video_screen_get_hblank(space->machine->primary_screen);
	543	static UINT16 mz800_ramaddr = 0;
	544	//static UINT8 mz800_display_mode = 0;
	545	//static UINT8 mz800_port_e8 = 0;
	546	static UINT8 mz800_palette[4];
	547	static UINT8 mz800_palette_bank;
222	548
223		LOG(1, "mz700_e008_r", ("%02X\n", data), space->machine);
224	549
225		return data;
226		}
	550	/***************************************************************************
	551	Z80 PIO
	552	***************************************************************************/
227	553
228
229		/************************ BANK ***********************************************/
230
231		/* BANK1 0000-0FFF */
232		static void bank1_RAM(running_machine *machine, UINT8 *mem)
	554	static void mz800_z80pio_irq(const device_config *device, int which)
233	555	{
234		memory_set_bankptr(machine, 1, &mem[0x00000]);
235		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x0fff, 0, 0, SMH_BANK1);
236		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x0fff, 0, 0, SMH_BANK1);
	556	cputag_set_input_line(device->machine, "maincpu", 0, which);
237	557	}
238	558
239		static void bank1_ROM(running_machine *machine, UINT8 *mem)
	559	static READ8_DEVICE_HANDLER( mz800_z80pio_port_a_r )
240	560	{
241		memory_set_bankptr(machine, 1, &mem[0x10000]);
242		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x0fff, 0, 0, SMH_BANK1);
243		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x0000, 0x0fff, 0, 0, SMH_UNMAP);
244		}
	561	const device_config *printer = devtag_get_device(device->machine, CENTRONICS, "centronics");
	562	UINT8 result = 0;
245	563
	564	result |= centronics_busy_r(printer);
	565	result |= centronics_pe_r(printer) << 1;
	566	result |= video_screen_get_hblank(device->machine->primary_screen) << 5;
246	567
247		/* BANK2 1000-1FFF */
248		static void bank2_RAM(running_machine *machine, UINT8 *mem)
249		{
250		memory_set_bankptr(machine, 2, &mem[0x01000]);
251		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x1000, 0x1fff, 0, 0, SMH_BANK2);
252		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x1000, 0x1fff, 0, 0, SMH_BANK2);
	568	return result;
253	569	}
254	570
255		static void bank2_ROM(running_machine *machine, UINT8 *mem)
	571	static WRITE8_DEVICE_HANDLER( mz800_z80pio_port_a_w )
256	572	{
257		memory_set_bankptr(machine, 2, &mem[0x11000]);
258		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x1000, 0x1fff, 0, 0, SMH_BANK2);
259		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x1000, 0x1fff, 0, 0, SMH_UNMAP);
260		}
	573	const device_config *printer = devtag_get_device(device->machine, CENTRONICS, "centronics");
261	574
262
263		/* BANK3 8000-9FFF */
264		static void bank3_RAM(running_machine *machine, UINT8 *mem)
265		{
266		memory_set_bankptr(machine, 3, &mem[0x08000]);
267		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x8000, 0x9fff, 0, 0, SMH_BANK3);
268		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x8000, 0x9fff, 0, 0, SMH_BANK3);
	575	centronics_prime_w(printer, BIT(data, 6));
	576	centronics_strobe_w(printer, BIT(data, 7));
269	577	}
270	578
271		static void bank3_VID(running_machine *machine, UINT8 *mem)
	579	static WRITE8_DEVICE_HANDLER( mz800_printer_data_w )
272	580	{
273		memory_set_bankptr(machine, 3, videoram);
274		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x8000, 0x9fff, 0, 0, SMH_BANK3);
275		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x8000, 0x9fff, 0, 0, SMH_BANK3);
	581	const device_config *printer = devtag_get_device(device->machine, CENTRONICS, "centronics");
	582	centronics_data_w(printer, 0, data);
276	583	}
277	584
278
279		/* BANK4 A000-BFFF */
280		static void bank4_RAM(running_machine *machine, UINT8 *mem)
	585	const z80pio_interface mz800_z80pio_config =
281	586	{
282		memory_set_bankptr(machine, 4, &mem[0x0a000]);
283		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xA000, 0xBFFF, 0, 0, SMH_BANK4);
284		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xA000, 0xBFFF, 0, 0, SMH_BANK4);
285		}
	587	mz800_z80pio_irq,
	588	mz800_z80pio_port_a_r,
	589	NULL,
	590	mz800_z80pio_port_a_w,
	591	mz800_printer_data_w,
	592	NULL,
	593	NULL,
	594	};
286	595
287		static void bank4_VID(running_machine *machine, UINT8 *mem)
288		{
289		memory_set_bankptr(machine, 4, videoram + 0x2000);
290		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xA000, 0xBFFF, 0, 0, SMH_BANK4);
291		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xA000, 0xBFFF, 0, 0, SMH_BANK4);
292		}
293	596
294	597
295		/* BANK7 C000-CFFF */
296		static void bank5_RAM(running_machine *machine, UINT8 *mem)
297		{
298		memory_set_bankptr(machine, 5, &mem[0x0c000]);
299		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xC000, 0xCFFF, 0, 0, SMH_BANK5);
300		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xC000, 0xCFFF, 0, 0, SMH_BANK5);
301		}
302	598
303
304		/* BANK6 D000-D7FF */
305		static void bank6_NOP(running_machine *machine, UINT8 *mem)
306		{
307		memory_set_bankptr(machine, 6, &mem[0x0d000]);
308		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD000, 0xD7FF, 0, 0, SMH_NOP);
309		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD000, 0xD7FF, 0, 0, SMH_NOP);
310		}
311
312		static void bank6_RAM(running_machine *machine, UINT8 *mem)
313		{
314		memory_set_bankptr(machine, 6, &mem[0x0d000]);
315		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD000, 0xD7FF, 0, 0, SMH_BANK6);
316		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD000, 0xD7FF, 0, 0, SMH_BANK6);
317		}
318
319		static void bank6_VIO(running_machine *machine, UINT8 *mem)
320		{
321		memory_set_bankptr(machine, 6, videoram);
322		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD000, 0xD7FF, 0, 0, SMH_BANK6);
323		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD000, 0xD7FF, 0, 0, SMH_BANK6);
324		}
325
326
327		/* BANK9 D800-DFFF */
328		static void bank7_NOP(running_machine *machine, UINT8 *mem)
329		{
330		memory_set_bankptr(machine, 7, &mem[0x0d800]);
331		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD800, 0xDFFF, 0, 0, SMH_NOP);
332		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD800, 0xDFFF, 0, 0, SMH_NOP);
333		}
334
335		static void bank7_RAM(running_machine *machine, UINT8 *mem)
336		{
337		memory_set_bankptr(machine, 7, &mem[0x0d800]);
338		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD800, 0xDFFF, 0, 0, SMH_BANK7);
339		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD800, 0xDFFF, 0, 0, SMH_BANK7);
340		}
341
342		static void bank7_VIO(running_machine *machine, UINT8 *mem)
343		{
344		memory_set_bankptr(machine, 7, colorram);
345		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD800, 0xDFFF, 0, 0, SMH_BANK7);
346		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xD800, 0xDFFF, 0, 0, SMH_BANK7);
347		}
348
349
350		/* BANK8 E000-FFFF */
351		static void bank8_NOP(running_machine *machine, UINT8 *mem)
352		{
353		memory_set_bankptr(machine, 8, &mem[0x0e000]);
354		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xE000, 0xFFFF, 0, 0, SMH_NOP);
355		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xE000, 0xFFFF, 0, 0, SMH_NOP);
356
357		}
358
359		static void bank8_RAM(running_machine *machine, UINT8 *mem)
360		{
361		memory_set_bankptr(machine, 8, &mem[0x0e000]);
362		memory_install_read8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xE000, 0xFFFF, 0, 0, SMH_BANK8);
363		memory_install_write8_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0xE000, 0xFFFF, 0, 0, SMH_BANK8);
364		}
365
366		static void bank8_VIO(const address_space *space, UINT8 *mem)
367		{
368		const device_config *pit = devtag_get_device(space->machine, PIT8253, "pit8253");
369		const device_config *ppi = devtag_get_device(space->machine, PPI8255, "ppi8255");
370
371		memory_set_bankptr(space->machine, 8, &mem[0x16000]);
372		memory_install_readwrite8_device_handler(space, ppi, 0xe000, 0xfff3, 0, 0x1ff0, ppi8255_r, ppi8255_w);
373		memory_install_readwrite8_device_handler(space, pit, 0xe004, 0xfff7, 0, 0x1ff0, pit8253_r, pit8253_w);
374		memory_install_read8_handler(space, 0xe008, 0xfff8, 0, 0x1ff0, mz700_e008_r);
375		memory_install_write8_device_handler(space, pit, 0xe008, 0xfff8, 0, 0x1ff0, pit8253_gate_w);
376		}
377
378
379		WRITE8_HANDLER ( mz700_bank_w )
380		{
381		static int mz700_locked = 0;
382		static int vio_mode = 0;
383		static int vio_lock = 0;
384		UINT8 *mem = memory_region(space->machine, "maincpu");
385
386		switch (offset)
387		{
388		case 0: /* 0000-0FFF RAM */
389		LOG(1,"mz700_bank_w",("0: 0000-0FFF RAM\n"),space->machine);
390		bank1_RAM(space->machine, mem);
391		mz700_locked = 0;
392		break;
393
394		case 1: /* D000-FFFF RAM */
395		LOG(1,"mz700_bank_w",("1: D000-FFFF RAM\n"),space->machine);
396		bank6_RAM(space->machine, mem);
397		bank7_RAM(space->machine, mem);
398		bank8_RAM(space->machine, mem);
399		mz700_locked = 0;
400		vio_mode = 1;
401		break;
402
403		case 2: /* 0000-0FFF ROM */
404		LOG(1,"mz700_bank_w",("2: 0000-0FFF ROM\n"),space->machine);
405		bank1_ROM(space->machine, mem);
406		mz700_locked = 0;
407		break;
408
409		case 3: /* D000-FFFF videoram, memory mapped io */
410		LOG(1,"mz700_bank_w",("3: D000-FFFF videoram, memory mapped io\n"),space->machine);
411		bank6_VIO(space->machine, mem);
412		bank7_VIO(space->machine, mem);
413		bank8_VIO(space, mem);
414		mz700_locked = 0;
415		vio_mode = 3;
416		break;
417
418		case 4: /* 0000-0FFF ROM   D000-FFFF videoram, memory mapped io */
419		LOG(1,"mz700_bank_w",("4: 0000-0FFF ROM; D000-FFFF videoram, memory mapped io\n"),space->machine);
420		bank1_ROM(space->machine, mem);
421		bank6_VIO(space->machine, mem);
422		bank7_VIO(space->machine, mem);
423		bank8_VIO(space, mem);
424		mz700_locked = 0;
425		vio_mode = 3;
426		break;
427
428		case 5: /* 0000-0FFF no chg D000-FFFF locked */
429		LOG(1,"mz700_bank_w",("5: D000-FFFF locked\n"),space->machine);
430		if (mz700_locked == 0)
431		{
432		vio_lock = vio_mode;
433		mz700_locked = 1;
434		bank6_NOP(space->machine, mem);
435		bank7_NOP(space->machine, mem);
436		bank8_NOP(space->machine, mem);
437		}
438		break;
439
440		case 6: /* 0000-0FFF no chg D000-FFFF unlocked */
441		LOG(1,"mz700_bank_w",("6: D000-FFFF unlocked\n"),space->machine);
442		if (mz700_locked == 1)
443		mz700_bank_w(space, vio_lock, 0); /* old config for D000-DFFF */
444		break;
445		}
446		}
447
448		/******************************************************************************
449		*   Sharp MZ800
450		*
451		*
452		******************************************************************************/
453
454		static UINT16 mz800_ramaddr = 0;
455		static UINT8 mz800_display_mode = 0;
456		static UINT8 mz800_port_e8 = 0;
457		static UINT8 mz800_palette[4];
458		static UINT8 mz800_palette_bank;
459
460	599	/* port CE */
461	600	READ8_HANDLER( mz800_crtc_r )
462	601	{
r4374	r4375
465	604	return data;
466	605	}
467	606
468		/* port E0 - E9 */
469		READ8_HANDLER( mz800_bank_r )
470		{
471		UINT8 *mem = memory_region(space->machine, "maincpu");
472		UINT8 data = 0xff;
473	607
474		switch (offset)
475		{
476		case 0: /* 1000-1FFF PCG ROM */
477		LOG(1,"mz800_bank_r",("0: 1000-1FFF PCG ROM"),space->machine);
478		bank2_ROM(space->machine, mem);
479		if ((mz800_display_mode & 0x08) == 0)
480		{
481		if (VERBOSE>=1) logerror("; 8000-9FFF videoram");
482		bank3_VID(space->machine, mem);
483		if (mz800_display_mode & 0x04)
484		{
485		if (VERBOSE>=1) logerror("; A000-BFFF videoram");
486		/* 640x480 mode so A000-BFFF is videoram too */
487		bank4_VID(space->machine, mem);
488		}
489		else
490		{
491		if (VERBOSE>=1) logerror("; A000-BFFF RAM");
492		bank4_RAM(space->machine, mem);
493		}
494		}
495		else
496		{
497		if (VERBOSE>=1) logerror("; C000-CFFF PCG RAM");
498		/* make C000-CFFF PCG RAM */
499		bank5_RAM(space->machine, mem);
500		}
501		if (VERBOSE>=1) logerror("\n");
502		break;
503
504		case 1: /* make 1000-1FFF and C000-CFFF RAM */
505		LOG(1,"mz800_bank_r",("1: 1000-1FFF RAM"),space->machine);
506		bank2_RAM(space->machine, mem);
507		if ((mz800_display_mode & 0x08) == 0)
508		{
509		if (VERBOSE>=1) logerror("; 8000-9FFF RAM; A000-BFFF RAM");
510		/* make 8000-BFFF RAM */
511		bank3_RAM(space->machine, mem);
512		bank4_RAM(space->machine, mem);
513		}
514		else
515		{
516		if (VERBOSE>=1) logerror("; C000-CFFF RAM");
517		/* make C000-CFFF RAM */
518		bank5_RAM(space->machine, mem);
519		}
520		if (VERBOSE>=1) logerror("\n");
521		break;
522
523		case 8: /* get MZ700 enable bit 7 ? */
524		data = mz800_port_e8;
525		break;
526		}
527		return data;
528		}
529
530	608	/* port EA */
531	609	READ8_HANDLER( mz800_ramdisk_r )
532	610	{
r4374	r4375
558	636	*/
559	637	WRITE8_HANDLER( mz800_display_mode_w )
560	638	{
561		UINT8 *mem = memory_region(space->machine, "maincpu");
562		LOG(1,"mz800_display_mode_w",("%02X\n", data),space->machine);
563		mz800_display_mode = data;
564		if ((mz800_display_mode & 0x08) == 0)
565		{
566		bank8_RAM(space->machine, mem);
567		}
	639	mz_state *mz = space->machine->driver_data;
	640
	641	mz->mz700_mode = BIT(data, 3);
	642	mz->hires_mode = BIT(data, 2);
	643	mz->screen = data & 0x03;
	644
	645	/* change memory maps if we switched mode */
	646	//   if (BIT(data, 3) != mz->mz700_mode)
	647	//   {
	648	//      logerror("mz800_display_mode_w: switching mode to %s\n", (BIT(data, 3) ? "mz700" : "mz800"));
	649	//      mz->mz700_mode = BIT(data, 3);
	650	//      mz_bank_4_w(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0, 0);
	651	//   }
568	652	}
569	653
570	654	/* port CF */
r4374	r4375
573	657	LOG(1,"mz800_scroll_border_w",("%02X\n", data),space->machine);
574	658	}
575	659
576		/* port E0-E9 */
577		WRITE8_HANDLER ( mz800_bank_w )
578		{
579		static int mz800_locked = 0;
580		static int vio_mode = 0;
581		static int vio_lock = 0;
582		UINT8 *mem = memory_region(space->machine, "maincpu");
583
584		switch (offset)
585		{
586		case 0: /* 0000-0FFF RAM */
587		LOG(1,"mz800_bank_w",("0: 0000-0FFF RAM\n"),space->machine);
588		bank1_RAM(space->machine, mem);
589		mz800_locked = 0;
590		break;
591
592		case 1: /* D000-FFFF RAM */
593		LOG(1,"mz800_bank_w",("1: D000-FFFF RAM\n"),space->machine);
594		bank6_RAM(space->machine, mem);
595		bank7_RAM(space->machine, mem);
596		bank8_RAM(space->machine, mem);
597		mz800_locked = 0;
598		vio_mode = 1;
599		break;
600
601		case 2: /* 0000-0FFF ROM */
602		LOG(1,"mz800_bank_w",("2: 0000-0FFF ROM\n"),space->machine);
603		bank1_ROM(space->machine, mem);
604		mz800_locked = 0;
605		break;
606
607		case 3: /* D000-FFFF videoram, memory mapped io */
608		LOG(1,"mz800_bank_w",("3: D000-FFFF videoram, memory mapped io\n"),space->machine);
609		bank6_VIO(space->machine, mem);
610		bank7_VIO(space->machine, mem);
611		bank8_VIO(space, mem);
612		mz800_locked = 0;
613		vio_mode = 3;
614		break;
615
616		case 4: /* 0000-0FFF ROM    D000-FFFF videoram, memory mapped io */
617		LOG(1,"mz800_bank_w",("4: 0000-0FFF ROM; D000-FFFF videoram, memory mapped io\n"),space->machine);
618		bank1_ROM(space->machine, mem);
619		bank6_VIO(space->machine, mem);
620		bank7_VIO(space->machine, mem);
621		bank8_VIO(space, mem);
622		mz800_locked = 0;
623		vio_mode = 3;
624		break;
625
626		case 5: /* 0000-0FFF no chg D000-FFFF locked */
627		LOG(1,"mz800_bank_w",("5: D000-FFFF locked\n"),space->machine);
628		if (mz800_locked == 0)
629		{
630		vio_lock = vio_mode;
631		mz800_locked = 1;
632		bank6_NOP(space->machine, mem);
633		bank7_NOP(space->machine, mem);
634		bank8_NOP(space->machine, mem);
635		}
636		break;
637
638		case 6: /* 0000-0FFF no chg D000-FFFF unlocked */
639		LOG(1,"mz800_bank_w",("6: D000-FFFF unlocked\n"),space->machine);
640		if (mz800_locked == 1)
641		mz800_bank_w(space, vio_lock, 0); /* old config for D000-DFFF */
642		break;
643
644		case 8: /* set MZ700 enable bit 7 ? */
645		mz800_port_e8 = data;
646		if (mz800_port_e8 & 0x80)
647		{
648		bank6_VIO(space->machine, mem);
649		bank7_VIO(space->machine, mem);
650		bank8_VIO(space, mem);
651		}
652		else
653		{
654		bank6_RAM(space->machine, mem);
655		bank7_RAM(space->machine, mem);
656		bank8_RAM(space->machine, mem);
657		}
658		break;
659		}
660		}
661
662	660	/* port EA */
663	661	WRITE8_HANDLER( mz800_ramdisk_w )
664	662	{
r4374	r4375
692	690	mz800_palette[idx] = val;
693	691	}
694	692	}
695
696
697		DRIVER_INIT( mz800 )
698		{
699		UINT8 *mem = memory_region(machine, "maincpu");
700		const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
701
702		videoram_size = 0x5000;
703		videoram = auto_malloc(videoram_size);
704		colorram = auto_malloc(0x800);
705
706		mem[0x10001] = 0x4a;
707		mem[0x10002] = 0x00;
708		memcpy(&mem[0x00000], &mem[0x10000], 0x02000);
709
710		mem = memory_region(machine, "user1");
711		memset(&mem[0x00000], 0xff, 0x10000);
712
713		mz800_display_mode_w(space, 0, 0x08);   /* set MZ700 mode */
714		mz800_bank_r(space, 1);
715		mz800_bank_w(space, 4, 0);
716		}

src/mess/drivers/mz700.c

r4374	r4375
68	68	#include "cpu/z80/z80.h"
69	69	#include "machine/8255ppi.h"
70	70	#include "machine/pit8253.h"
	71	#include "machine/z80pio.h"
71	72	#include "machine/74145.h"
	73	#include "machine/ctronics.h"
	74	#include "sound/sn76496.h"
72	75	#include "sound/speaker.h"
73	76	#include "sound/wave.h"
74	77	#include "devices/cassette.h"
r4374	r4375
81	84
82	85	static TIMER_DEVICE_CALLBACK( ne556_cursor_callback )
83	86	{
84		mz700_state *mz700 = timer->machine->driver_data;
85		mz700->cursor_timer ^= 1;
	87	mz_state *mz = timer->machine->driver_data;
	88	mz->cursor_timer ^= 1;
86	89	}
87	90
88	91	static TIMER_DEVICE_CALLBACK( ne556_other_callback )
89	92	{
90		mz700_state *mz700 = timer->machine->driver_data;
91		mz700->other_timer ^= 1;
	93	mz_state *mz = timer->machine->driver_data;
	94	mz->other_timer ^= 1;
92	95	}
93	96
94	97
r4374	r4375
96	99	ADDRESS MAPS
97	100	***************************************************************************/
98	101
99		static ADDRESS_MAP_START( mz700_mem, ADDRESS_SPACE_PROGRAM, 8)
100		AM_RANGE(0x0000, 0x0fff) AM_RAMBANK(1)
101		AM_RANGE(0x1000, 0xcfff) AM_RAM
102		AM_RANGE(0xd000, 0xd7ff) AM_RAMBANK(6)
103		AM_RANGE(0xd800, 0xdfff) AM_RAMBANK(7)
104		AM_RANGE(0xe000, 0xffff) AM_RAMBANK(8)
	102	static ADDRESS_MAP_START( mz700_mem, ADDRESS_SPACE_PROGRAM, 8 )
105	103	ADDRESS_MAP_END
106	104
107		static ADDRESS_MAP_START(mz700_io, ADDRESS_SPACE_IO, 8)
108		AM_RANGE(0xe0, 0xe6) AM_WRITE(mz700_bank_w)
	105	static ADDRESS_MAP_START( mz700_io, ADDRESS_SPACE_IO, 8 )
	106	ADDRESS_MAP_GLOBAL_MASK(0xff)
	107	AM_RANGE(0xe0, 0xe0) AM_WRITE(mz700_bank_0_w)
	108	AM_RANGE(0xe1, 0xe1) AM_WRITE(mz_bank_1_w)
	109	AM_RANGE(0xe2, 0xe2) AM_WRITE(mz_bank_2_w)
	110	AM_RANGE(0xe3, 0xe3) AM_WRITE(mz_bank_3_w)
	111	AM_RANGE(0xe4, 0xe4) AM_WRITE(mz_bank_4_w)
	112	AM_RANGE(0xe5, 0xe5) AM_WRITE(mz_bank_5_w)
	113	AM_RANGE(0xe6, 0xe6) AM_WRITE(mz_bank_6_w)
109	114	ADDRESS_MAP_END
110	115
111		static ADDRESS_MAP_START(mz800_mem, ADDRESS_SPACE_PROGRAM, 8)
112		AM_RANGE(0x0000, 0x0fff) AM_RAMBANK(1)
113		AM_RANGE(0x1000, 0x1fff) AM_RAMBANK(2)
114		AM_RANGE(0x2000, 0x7fff) AM_RAM
115		AM_RANGE(0x8000, 0x9fff) AM_RAMBANK(3)
116		AM_RANGE(0xa000, 0xbfff) AM_RAMBANK(4)
117		AM_RANGE(0xc000, 0xcfff) AM_RAMBANK(5)
118		AM_RANGE(0xd000, 0xd7ff) AM_RAMBANK(6)
119		AM_RANGE(0xd800, 0xdfff) AM_RAMBANK(7)
120		AM_RANGE(0xe000, 0xffff) AM_RAMBANK(8)
	116	static ADDRESS_MAP_START( mz800_mem, ADDRESS_SPACE_PROGRAM, 8 )
121	117	ADDRESS_MAP_END
122	118
123		static ADDRESS_MAP_START(mz800_io, ADDRESS_SPACE_IO, 8)
	119	static ADDRESS_MAP_START( mz800_io, ADDRESS_SPACE_IO, 8 )
	120	ADDRESS_MAP_GLOBAL_MASK(0xff)
124	121	AM_RANGE(0xcc, 0xcc) AM_WRITE( mz800_write_format_w )
125	122	AM_RANGE(0xcd, 0xcd) AM_WRITE( mz800_read_format_w )
126	123	AM_RANGE(0xce, 0xce) AM_READWRITE( mz800_crtc_r, mz800_display_mode_w )
127	124	AM_RANGE(0xcf, 0xcf) AM_WRITE( mz800_scroll_border_w )
128	125	AM_RANGE(0xd0, 0xd3) AM_DEVREADWRITE(PPI8255, "ppi8255", ppi8255_r, ppi8255_w)
129	126	AM_RANGE(0xd4, 0xd7) AM_DEVREADWRITE(PIT8253, "pit8253", pit8253_r, pit8253_w)
130		AM_RANGE(0xe0, 0xe9) AM_READWRITE( mz800_bank_r, mz800_bank_w )
	127	AM_RANGE(0xe0, 0xe0) AM_READWRITE(mz800_bank_0_r, mz800_bank_0_w)
	128	AM_RANGE(0xe1, 0xe1) AM_READWRITE(mz800_bank_1_r, mz_bank_1_w)
	129	AM_RANGE(0xe2, 0xe2) AM_WRITE(mz_bank_2_w)
	130	AM_RANGE(0xe3, 0xe3) AM_WRITE(mz_bank_3_w)
	131	AM_RANGE(0xe4, 0xe4) AM_WRITE(mz_bank_4_w)
	132	AM_RANGE(0xe5, 0xe5) AM_WRITE(mz_bank_5_w)
	133	AM_RANGE(0xe6, 0xe6) AM_WRITE(mz_bank_6_w)
131	134	AM_RANGE(0xea, 0xea) AM_READWRITE( mz800_ramdisk_r, mz800_ramdisk_w )
132	135	AM_RANGE(0xeb, 0xeb) AM_WRITE( mz800_ramaddr_w )
133		AM_RANGE(0xf0, 0xf0) AM_WRITE( mz800_palette_w )
	136	AM_RANGE(0xf0, 0xf0) AM_READ_PORT("atari_joy1") AM_WRITE(mz800_palette_w)
	137	AM_RANGE(0xf1, 0xf1) AM_READ_PORT("atari_joy2")
	138	AM_RANGE(0xf2, 0xf2) AM_DEVWRITE(SOUND, "sn76489n", sn76496_w)
	139	AM_RANGE(0xfc, 0xfd) AM_DEVREADWRITE(Z80PIO, "z80pio", z80pio_c_r, z80pio_c_w)
	140	AM_RANGE(0xfe, 0xff) AM_DEVREADWRITE(Z80PIO, "z80pio", z80pio_d_r, z80pio_d_w)
134	141	ADDRESS_MAP_END
135	142
136	143
r4374	r4375
247	254	PORT_BIT(0x10, 0x00, IPT_JOYSTICK_RIGHT)   PORT_8WAY
248	255	INPUT_PORTS_END
249	256
	257	static INPUT_PORTS_START( mz800 )
	258	PORT_INCLUDE(mz700)
250	259
	260	PORT_MODIFY("JOY")
	261	PORT_BIT(0x1f, 0x00, IPT_UNUSED)
	262
	263	PORT_START("atari_joy1")
	264	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP)    PORT_PLAYER(1) PORT_8WAY
	265	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN)  PORT_PLAYER(1) PORT_8WAY
	266	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT)  PORT_PLAYER(1) PORT_8WAY
	267	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_PLAYER(1) PORT_8WAY
	268	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_BUTTON1)        PORT_PLAYER(1)
	269	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_BUTTON2)        PORT_PLAYER(1)
	270
	271	PORT_START("atari_joy2")
	272	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP)    PORT_PLAYER(2) PORT_8WAY
	273	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN)  PORT_PLAYER(2) PORT_8WAY
	274	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT)  PORT_PLAYER(2) PORT_8WAY
	275	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_PLAYER(2) PORT_8WAY
	276	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_BUTTON1)        PORT_PLAYER(2)
	277	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_BUTTON2)        PORT_PLAYER(2)
	278
	279	PORT_START("system_settings")
	280	PORT_DIPNAME(0x01, 0x00, "Mode selection")
	281	PORT_DIPLOCATION("SW:4")
	282	PORT_DIPSETTING(0x01, "MZ-700")
	283	PORT_DIPSETTING(0x00, "MZ-800")
	284	PORT_DIPNAME(0x06, 0x06, "Printer selection")
	285	PORT_DIPLOCATION("SW:3,2")
	286	PORT_DIPSETTING(0x06, "MZ printer")
	287	PORT_DIPSETTING(0x00, "Centronics printer")
	288	PORT_DIPNAME(0x08, 0x08, "Cassette polarity")
	289	PORT_DIPLOCATION("SW:1")
	290	PORT_DIPSETTING(0x08, DEF_STR(Unknown))
	291	PORT_DIPSETTING(0x00, DEF_STR(Unknown))
	292	INPUT_PORTS_END
	293
	294
251	295	/***************************************************************************
252	296	GFX LAYOUT
253	297	***************************************************************************/
r4374	r4375
264	308	};
265	309
266	310	static GFXDECODE_START( mz700 )
267		GFXDECODE_ENTRY( "gfx1", 0, char_layout, 0, 256 )
	311	GFXDECODE_ENTRY("cgrom", 0, char_layout, 0, 256)
268	312	GFXDECODE_END
269	313
	314	static GFXDECODE_START( mz800 )
	315	GFXDECODE_ENTRY(NULL, 0, char_layout, 0, 256)
	316	GFXDECODE_END
270	317
	318
271	319	/***************************************************************************
272	320	MACHINE DRIVERS
273	321	***************************************************************************/
r4374	r4375
286	334	MDRV_CPU_PROGRAM_MAP(mz700_mem, 0)
287	335	MDRV_CPU_IO_MAP(mz700_io, 0)
288	336
	337	MDRV_MACHINE_START(mz700)
	338
289	339	/* video hardware */
290	340	MDRV_SCREEN_ADD("screen", RASTER)
291	341	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
r4374	r4375
304	354	MDRV_SOUND_ADD("speaker", SPEAKER, 0)
305	355	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
306	356
307		MDRV_DRIVER_DATA(mz700_state)
	357	MDRV_DRIVER_DATA(mz_state)
308	358
309	359	/* ne556 timers */
310	360	MDRV_TIMER_ADD_PERIODIC("cursor", ne556_cursor_callback, HZ(1.5))
r4374	r4375
326	376	MDRV_CPU_MODIFY("maincpu")
327	377	MDRV_CPU_PROGRAM_MAP(mz800_mem, 0)
328	378	MDRV_CPU_IO_MAP(mz800_io, 0)
	379
	380	MDRV_GFXDECODE(mz800)
	381	MDRV_VIDEO_START(mz800)
	382	MDRV_VIDEO_UPDATE(mz800)
	383
	384	MDRV_SOUND_ADD("sn76489n", SN76489, XTAL_17_73447MHz/5)
	385	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	386
	387	/* devices */
	388	MDRV_DEVICE_REMOVE("pit8253", PIT8253)
	389	MDRV_PIT8253_ADD("pit8253", mz800_pit8253_config)
	390	MDRV_Z80PIO_ADD("z80pio", mz800_z80pio_config)
	391	MDRV_CENTRONICS_ADD("centronics", standard_centronics)
329	392	MACHINE_DRIVER_END
330	393
331	394
r4374	r4375
334	397	***************************************************************************/
335	398
336	399	ROM_START( mz700 )
337		ROM_REGION(0x18000, "maincpu", 0)
338		ROM_LOAD("1z-013a.rom", 0x10000, 0x1000, CRC(4c6c6b7b) SHA1(ef8f7399e86c1dc638a5cb83efdb73369c2b5735))
339		ROM_REGION(0x1000, "gfx1", 0)
	400	ROM_REGION(0x1000, "monitor", 0)
	401	ROM_LOAD("1z-013a.rom", 0x0000, 0x1000, CRC(4c6c6b7b) SHA1(ef8f7399e86c1dc638a5cb83efdb73369c2b5735))
	402	ROM_REGION(0x1000, "cgrom", 0)
340	403	ROM_LOAD("mz700fon.int", 0x0000, 0x1000, CRC(42b9e8fb) SHA1(5128ad179a702f8e0bd9910a58bad8fbe4c20167))
341	404	ROM_END
342	405
343	406	ROM_START( mz700j )
344		ROM_REGION(0x18000, "maincpu", 0)
345		ROM_LOAD("1z-013a.rom", 0x10000, 0x1000, CRC(4c6c6b7b) SHA1(ef8f7399e86c1dc638a5cb83efdb73369c2b5735))
346		ROM_REGION(0x1000, "gfx1", 0)
	407	ROM_REGION(0x1000, "monitor", 0)
	408	ROM_LOAD("1z-013a.rom", 0x0000, 0x1000, CRC(4c6c6b7b) SHA1(ef8f7399e86c1dc638a5cb83efdb73369c2b5735))
	409	ROM_REGION(0x1000, "cgrom", 0)
347	410	ROM_LOAD("mz700fon.jap", 0x0000, 0x1000, CRC(425eedf5) SHA1(bd2cc750f2d2f63e50a59786668509e81a276e32))
348	411	ROM_END
349	412
350	413	ROM_START( mz800 )
351		ROM_REGION(0x18000, "maincpu", 0)
352		ROM_LOAD("mz800h.rom",  0x10000, 0x2000, BAD_DUMP CRC(0c281675) SHA1(0adb6201f114f96f06a50de07d1c1ca2bcb4cf43))
353		ROM_REGION(0x10000, "user1", ROMREGION_ERASEFF)
354		/* RAMDISK */
355		ROM_REGION(0x1000, "gfx1", 0)
356		ROM_LOAD("mz700fon.int", 0x0000, 0x1000, CRC(42b9e8fb) SHA1(5128ad179a702f8e0bd9910a58bad8fbe4c20167))
	414	ROM_REGION(0x4000, "monitor", 0)
	415	ROM_LOAD("mz800.rom", 0x0000, 0x4000, CRC(600d17e1) SHA1(950ce4b51429916f8036e41ba6130fac149b36e4))
357	416	ROM_END
358	417
359	418
360	419	/***************************************************************************
	420	SYSTEM CONFIGS
	421	***************************************************************************/
	422
	423	static SYSTEM_CONFIG_START( mz700 )
	424	CONFIG_RAM_DEFAULT(64 * 1024) /* 64KB RAM */
	425	SYSTEM_CONFIG_END
	426
	427
	428	/***************************************************************************
361	429	GAME DRIVERS
362	430	***************************************************************************/
363	431
364	432	/*    YEAR  NAME      PARENT    COMPAT  MACHINE   INPUT     INIT    CONFIG  COMPANY      FULLNAME */
365		COMP( 1982, mz700,     0,      0,      mz700,     mz700,   mz700,   0,      "Sharp",     "MZ-700", 0 )
366		COMP( 1982, mz700j,   mz700,   0,      mz700,     mz700,   mz700,   0,      "Sharp",     "MZ-700 (Japan)", 0 )
367		COMP( 1982, mz800,     mz700,   0,      mz800,     mz700,   mz800,   0,      "Sharp",     "MZ-800", GAME_NOT_WORKING )
	433	COMP( 1982, mz700,     0,      0,      mz700,     mz700,   mz700,   mz700,   "Sharp",     "MZ-700", 0 )
	434	COMP( 1982, mz700j,   mz700,   0,      mz700,     mz700,   mz700,   mz700,   "Sharp",     "MZ-700 (Japan)", 0 )
	435	COMP( 1982, mz800,     0,      0,      mz800,     mz800,   mz800,   mz700,   "Sharp",     "MZ-800", GAME_NOT_WORKING )

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