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r4151 Saturday 17th January, 2009 at 10:15:01 UTC by Wilbert Pol
Improved implementations for undocumented instructions 63, 67, 6f, 73, 77, 7b, 7f, 9c, 9e, ab, e3, e7, ef, f3, f7, fb, and ff in the n2a3 cpu core.
[src/emu/cpu/m6502]ill02.h tn2a03.c

src/emu/cpu/m6502/tn2a03.c
r4150r4151
4545OP(e1) { int tmp; RD_IDX; SBC_NES;     } /* 6 SBC IDX */
4646OP(71) { int tmp; RD_IDY_P; ADC_NES;     } /* 5 ADC IDY page penalty */
4747OP(f1) { int tmp; RD_IDY_P; SBC_NES;     } /* 5 SBC IDY page penalty */
48OP(63) { int tmp; RD_IDX; WB_EA; RRA_NES; WB_EA;   } /* 7 RRA IDX */
49OP(73) { int tmp; RD_IDY_NP; WB_EA; RRA_NES; WB_EA; } /* 7 RRA IDY */
50OP(e3) { int tmp; RD_IDX; WB_EA; ISB_NES; WB_EA;   } /* 7 ISB IDX */
51OP(f3) { int tmp; RD_IDY_NP; WB_EA; ISB_NES; WB_EA; } /* 7 ISB IDY */
4852OP(65) { int tmp; RD_ZPG; ADC_NES;     } /* 3 ADC ZPG */
4953OP(e5) { int tmp; RD_ZPG; SBC_NES;     } /* 3 SBC ZPG */
5054OP(75) { int tmp; RD_ZPX; ADC_NES;     } /* 4 ADC ZPX */
5155OP(f5) { int tmp; RD_ZPX; SBC_NES;     } /* 4 SBC ZPX */
56OP(67) { int tmp; RD_ZPG; WB_EA; RRA_NES; WB_EA;    } /* 5 RRA ZPG */
57OP(77) { int tmp; RD_ZPX; WB_EA; RRA_NES; WB_EA;    } /* 6 RRA ZPX */
58OP(e7) { int tmp; RD_ZPG; WB_EA; ISB_NES; WB_EA;    } /* 5 ISB ZPG */
59OP(f7) { int tmp; RD_ZPX; WB_EA; ISB_NES; WB_EA;    } /* 6 ISB ZPX */
5260OP(69) { int tmp; RD_IMM; ADC_NES;     } /* 2 ADC IMM */
5361OP(e9) { int tmp; RD_IMM; SBC_NES;     } /* 2 SBC IMM */
5462OP(79) { int tmp; RD_ABY_P; ADC_NES;     } /* 4 ADC ABY page penalty */
5563OP(f9) { int tmp; RD_ABY_P; SBC_NES;     } /* 4 SBC ABY page penalty */
5664OP(6b) { int tmp; RD_IMM; ARR_NES; WB_ACC; } /* 2 ARR IMM */
65OP(7b) { int tmp; RD_ABY_NP; WB_EA; RRA_NES; WB_EA; } /* 7 RRA ABY */
66OP(ab) { int tmp; RD_IMM; OAL_NES;                  } /* 2 OAL IMM */
5767OP(eb) { int tmp; RD_IMM; SBC_NES;        } /* 2 SBC IMM */
68OP(fb) { int tmp; RD_ABY_NP; WB_EA; ISB_NES; WB_EA; } /* 7 ISB ABY */
69OP(9c) { int tmp; EA_ABX_NP; SYH_NES; WB_EA;     } /* 5 SYH ABX */
5870OP(6d) { int tmp; RD_ABS; ADC_NES;     } /* 4 ADC ABS */
5971OP(ed) { int tmp; RD_ABS; SBC_NES;     } /* 4 SBC ABS */
6072OP(7d) { int tmp; RD_ABX_P; ADC_NES;     } /* 4 ADC ABX page penalty */
6173OP(fd) { int tmp; RD_ABX_P; SBC_NES;     } /* 4 SBC ABX page penalty */
74OP(9e) { int tmp; EA_ABY_NP; SXH_NES; WB_EA;    } /* 5 SXH ABY */
75OP(6f) { int tmp; RD_ABS; WB_EA; RRA_NES; WB_EA;    } /* 6 RRA ABS */
76OP(7f) { int tmp; RD_ABX_NP; WB_EA; RRA_NES; WB_EA; } /* 7 RRA ABX */
77OP(ef) { int tmp; RD_ABS; WB_EA; ISB_NES; WB_EA;    } /* 6 ISB ABS */
78OP(ff) { int tmp; RD_ABX_NP; WB_EA; ISB_NES; WB_EA; } /* 7 ISB ABX */
6279
80
6381static void (*const insn2a03[0x100])(m6502_Regs *cpustate) = {
6482   m6502_00,m6502_01,m6502_02,m6502_03,m6502_04,m6502_05,m6502_06,m6502_07,
6583   m6502_08,m6502_09,m6502_0a,m6502_0b,m6502_0c,m6502_0d,m6502_0e,m6502_0f,
r4150r4151
7391   m6502_48,m6502_49,m6502_4a,m6502_4b,m6502_4c,m6502_4d,m6502_4e,m6502_4f,
7492   m6502_50,m6502_51,m6502_52,m6502_53,m6502_54,m6502_55,m6502_56,m6502_57,
7593   m6502_58,m6502_59,m6502_5a,m6502_5b,m6502_5c,m6502_5d,m6502_5e,m6502_5f,
76   m6502_60,n2a03_61,m6502_62,m6502_63,m6502_64,n2a03_65,m6502_66,m6502_67,
77   m6502_68,n2a03_69,m6502_6a,n2a03_6b,m6502_6c,n2a03_6d,m6502_6e,m6502_6f,
78   m6502_70,n2a03_71,m6502_72,m6502_73,m6502_74,n2a03_75,m6502_76,m6502_77,
79   m6502_78,n2a03_79,m6502_7a,m6502_7b,m6502_7c,n2a03_7d,m6502_7e,m6502_7f,
94   m6502_60,n2a03_61,m6502_62,n2a03_63,m6502_64,n2a03_65,m6502_66,n2a03_67,
95   m6502_68,n2a03_69,m6502_6a,n2a03_6b,m6502_6c,n2a03_6d,m6502_6e,n2a03_6f,
96   m6502_70,n2a03_71,m6502_72,n2a03_73,m6502_74,n2a03_75,m6502_76,n2a03_77,
97   m6502_78,n2a03_79,m6502_7a,n2a03_7b,m6502_7c,n2a03_7d,m6502_7e,n2a03_7f,
8098   m6502_80,m6502_81,m6502_82,m6502_83,m6502_84,m6502_85,m6502_86,m6502_87,
8199   m6502_88,m6502_89,m6502_8a,m6502_8b,m6502_8c,m6502_8d,m6502_8e,m6502_8f,
82100   m6502_90,m6502_91,m6502_92,m6502_93,m6502_94,m6502_95,m6502_96,m6502_97,
83   m6502_98,m6502_99,m6502_9a,m6502_9b,m6502_9c,m6502_9d,m6502_9e,m6502_9f,
101   m6502_98,m6502_99,m6502_9a,m6502_9b,n2a03_9c,m6502_9d,n2a03_9e,m6502_9f,
84102   m6502_a0,m6502_a1,m6502_a2,m6502_a3,m6502_a4,m6502_a5,m6502_a6,m6502_a7,
85   m6502_a8,m6502_a9,m6502_aa,m6502_ab,m6502_ac,m6502_ad,m6502_ae,m6502_af,
103   m6502_a8,m6502_a9,m6502_aa,n2a03_ab,m6502_ac,m6502_ad,m6502_ae,m6502_af,
86104   m6502_b0,m6502_b1,m6502_b2,m6502_b3,m6502_b4,m6502_b5,m6502_b6,m6502_b7,
87105   m6502_b8,m6502_b9,m6502_ba,m6502_bb,m6502_bc,m6502_bd,m6502_be,m6502_bf,
88106   m6502_c0,m6502_c1,m6502_c2,m6502_c3,m6502_c4,m6502_c5,m6502_c6,m6502_c7,
89107   m6502_c8,m6502_c9,m6502_ca,m6502_cb,m6502_cc,m6502_cd,m6502_ce,m6502_cf,
90108   m6502_d0,m6502_d1,m6502_d2,m6502_d3,m6502_d4,m6502_d5,m6502_d6,m6502_d7,
91109   m6502_d8,m6502_d9,m6502_da,m6502_db,m6502_dc,m6502_dd,m6502_de,m6502_df,
92   m6502_e0,n2a03_e1,m6502_e2,m6502_e3,m6502_e4,n2a03_e5,m6502_e6,m6502_e7,
93   m6502_e8,n2a03_e9,m6502_ea,n2a03_eb,m6502_ec,n2a03_ed,m6502_ee,m6502_ef,
94   m6502_f0,n2a03_f1,m6502_f2,m6502_f3,m6502_f4,n2a03_f5,m6502_f6,m6502_f7,
95   m6502_f8,n2a03_f9,m6502_fa,m6502_fb,m6502_fc,n2a03_fd,m6502_fe,m6502_ff
110   m6502_e0,n2a03_e1,m6502_e2,n2a03_e3,m6502_e4,n2a03_e5,m6502_e6,n2a03_e7,
111   m6502_e8,n2a03_e9,m6502_ea,n2a03_eb,m6502_ec,n2a03_ed,m6502_ee,n2a03_ef,
112   m6502_f0,n2a03_f1,m6502_f2,n2a03_f3,m6502_f4,n2a03_f5,m6502_f6,n2a03_f7,
113   m6502_f8,n2a03_f9,m6502_fa,n2a03_fb,m6502_fc,n2a03_fd,m6502_fe,n2a03_ff
96114};
src/emu/cpu/m6502/ill02.h
r4150r4151
280280         P|=F_V;                              \
281281   }
282282
283/* N2A03 *******************************************************
284 *  ISB increment and subtract with carry
285 ***************************************************************/
286#define ISB_NES                                       \
287   tmp = (UINT8)(tmp+1);                              \
288   SBC_NES
289
290/* N2A03 *******************************************************
291 * RRA  rotate right and add with carry
292 *  C -> [7][6][5][4][3][2][1][0] -> C
293 ***************************************************************/
294#define RRA_NES                                       \
295   tmp |= (P & F_C) << 8;                              \
296   P = (P & ~F_C) | (tmp & F_C);                        \
297   tmp = (UINT8)(tmp >> 1);                           \
298   ADC_NES
299
300/* N2A03 *******************************************************
301 *  OAL load accumulator and index X
302 ***************************************************************/
303#define OAL_NES                                       \
304   A = X = (UINT8)((A|0xff)&tmp);                        \
305   SET_NZ(A)
306
307/* N2A03 *******************************************************
308 * SXH  store index X high
309 * logical and index X with memory[PC+1] and store the result
310 *
311 * This instruction writes to an odd address when crossing
312 * a page boundary. The one known test case can be explained
313 * with a shift of Y. More testing will be needed to determine
314 * if this is correct.
315 *
316 ***************************************************************/
317#define SXH_NES                                       \
318   if ( Y && Y > EAL )                                 \
319      EAH |= ( Y << 1 );                              \
320   tmp = X & (EAH+1)
321
322/* N2A03 *******************************************************
323 * SYH  store index Y and (high + 1)
324 * logical and index Y with memory[PC+1] + 1 and store the result
325 *
326 * This instruction writs to an odd address when crossing a
327 * a page boundary. The one known test case can be explained
328 * with a shoft of X. More testing will be needed to determine
329 * if this is correct.
330 *
331 ***************************************************************/
332#define SYH_NES                                       \
333   if ( X && X > EAL )                                 \
334      EAH |= ( X << 1 );                              \
335   tmp = Y & (EAH+1)
336
283337#endif /* __ILL02_H__ */

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