MESS SVN History

15994 Revisions

r2865 Tuesday 17th June, 2008 at 22:46:34 UTC by Nathan Woods
Updated to MAME 0.125u6 core

[docs]	messnew.txt
[src/emu]	emuopts.c emuopts.h inptport.c render.h rendersw.c ui.c video.c video.h
[src/emu/audio]	generic.c generic.h
[src/emu/cpu]	cpu.mak drcbec.c drcbex64.c drcbex86.c drcuml.c vtlb.c* vtlb.h*
[src/emu/cpu/cop400]	cop420ds.c
[src/emu/cpu/mips]	mips3.c mips3com.c mips3com.h mips3drc.c mips3fe.c
[src/emu/cpu/powerpc]	ppccom.c ppccom.h ppcdrc.c
[src/emu/debug]	debugcmd.c
[src/mame]	mamedriv.c
[src/mame/audio]	atarijsa.c atarijsa.h dcs.c harddriv.c
[src/mame/drivers]	aleck64.c armedf.c atarig1.c atarig42.c atarigx2.c atarisy1.c atarisy2.c ataxx.c atetris.c bagman.c batman.c beathead.c blstroid.c bnstars.c cps1.c crystal.c cshooter.c cyberbal.c darius.c darkhors.c dcheese.c ddenlovr.c ddragon3.c dec0.c dec8.c deco156.c deco32.c deco_mlc.c decocass.c dietgo.c dynax.c embargo.c enigma2.c eolith.c eolith16.c eprom.c equites.c ertictac.c ettrivia.c exerion.c exidy440.c exprraid.c exterm.c f-32.c fantland.c fcombat.c fgoal.c filetto.c findout.c firebeat.c firetrap.c flkatck.c flstory.c flyball.c foodf.c freekick.c fromanc2.c fromance.c funkybee.c funkyjet.c fuukifg3.c gaelco2.c galaxold.c galpani3.c gamecstl.c gameplan.c gaplus.c gauntlet.c gcpinbal.c genesis.c getrivia.c gijoe.c goal92.c gomoku.c goodejan.c gottlieb.c gpworld.c grchamp.c gridlee.c groundfx.c gstriker.c gsword.c gticlub.c guab.c gunbustr.c gundealr.c hal21.c halleys.c hanaawas.c harddriv.c hitme.c hnayayoi.c homedata.c homerun.c hornet.c hshavoc.c igs_blit.c imolagp.c inufuku.c irobot.c itech32.c itech8.c jack.c jackal.c jalmah.c jchan.c jcross.c jedi.c kaneko16.c karnov.c kinst.c kinstb.c klax.c koikoi.c konamigv.c konamigx.c kopunch.c ksys573.c laserbat.c lastfght.c lazercmd.c leland.c lemmings.c lethal.c lethalj.c liberate.c liberatr.c limenko.c littlerb.c looping.c lordgun.c lsasquad.c lvcards.c m92.c mediagx.c megadriv.c megaplay.c megatech.c midvunit.c midzeus.c missb2.c model1.c model2.c ms32.c namcos1.c namcos21.c namcos22.c namcos23.c neogeo.c ninjaw.c nss.c offtwall.c onetwo.c overdriv.c pktgaldx.c pokechmp.c puckpkmn.c pushman.c raiden.c rampart.c rohga.c sbrkout.c seattle.c segac2.c segae.c segae.h segaorun.c segas16a.c segas16b.c segas18.c segas24.c segaxbd.c skullxbo.c sprint8.c srmp6.c starwars.c stv.c system16.c system18.c taito_z.c taitowlf.c tank8.c tecmosys.c thunderj.c timelimt.c toobin.c topshoot.c topspeed.c triplhnt.c vegas.c vindictr.c wgp.c wilytowr.c xexex.c xybots.c
[src/mame/includes]	dcheese.h dec0.h genesis.h gstriker.h itech32.h n64.h namcos1.h neogeo.h slapstic.h sprint8.h tank8.h triplhnt.h
[src/mame/machine]	asic65.c asic65.h atarigen.c atarigen.h balsente.c cps2crpt.c dec0.c decocass.c decoprot.c fd1089.c fd1089.h fddebug.c gaelco2.c galaxold.c gaplus.c harddriv.c irobot.c kaneko16.c konamigx.c konamigx.h konppc.c leland.c lsasquad.c midwayic.c midwayic.h midwunit.c model3.c n64.c namco50.c namco50.h namcoio.c namcos1.c pckeybrd.c pckeybrd.h pcshare.c pcshare.h rainbow.c s16fd.c s24fd.c scudsp.c scudsp.h segaic16.c slapstic.c snes.c toaplan1.c vertigo.c
[src/mame/video]	atari.c atarirle.c cps1.c dcheese.c decocass.c exidy440.c fgoal.c gstriker.c irobot.c itech32.c itech8.c konamigx.c lazercmd.c lethal.c lethalj.c lordgun.c m92.c mystwarr.c n64.c neogeo.c raiden.c rockola.c snes.c sprint8.c stvvdp2.c tank8.c triplhnt.c victory.c
[src/mess/drivers]	ip22.c n64.c pcw16.c saturn.c
[src/mess/machine]	pc.c
[src/mess/osd/windows]	tapedlg.c
[src/mess/tools/messtest]	testmess.c
[src/osd/windows]	drawgdi.c window.c

src/mame/audio/atarijsa.c
r2864	r2865
50	50	static UINT8 last_ctl;
51	51
52	52	static int cpu_num;
53		static ~~UINT8~~ test_port;
	53	static const char *test_port;
54	54	static UINT16 test_mask;
55	55
56	56	static UINT8 has_pokey;
r2864	r2865
104	104	*
105	105	*************************************/
106	106
107		void atarijsa_init(running_machine *machine, int testport, int testmask)
	107	void atarijsa_init(running_machine machine, const char testport, int testmask)
108	108	{
109	109	int i;
110	110	UINT8 *rgn;
r2864	r2865
221	221	0x01 = coin 1
222	222	*/
223	223	result = input_port_read(machine, "JSAI");
224		if (!(input_port_read~~_indexed~~(machine, test_port) & test_mask)) result ^= 0x80;
	224	if (!(input_port_read(machine, test_port) & test_mask)) result ^= 0x80;
225	225	if (atarigen_cpu_to_sound_ready) result ^= 0x40;
226	226	if (atarigen_sound_to_cpu_ready) result ^= 0x20;
227	227	if (!has_tms5220 \|\| tms5220_ready_r()) result ^= 0x10;
r2864	r2865
348	348	0x01 = coin 1
349	349	*/
350	350	result = input_port_read(machine, "JSAII");
351		if (!(input_port_read~~_indexed~~(machine, test_port) & test_mask)) result ^= 0x80;
	351	if (!(input_port_read(machine, test_port) & test_mask)) result ^= 0x80;
352	352	if (atarigen_cpu_to_sound_ready) result ^= 0x40;
353	353	if (atarigen_sound_to_cpu_ready) result ^= 0x20;
354	354	break;
r2864	r2865
467	467	0x01 = coin R (active high)
468	468	*/
469	469	result = input_port_read(machine, "JSAIII");
470		if (!(input_port_read~~_indexed~~(machine, test_port) & test_mask)) result ^= 0x90;
	470	if (!(input_port_read(machine, test_port) & test_mask)) result ^= 0x90;
471	471	if (atarigen_cpu_to_sound_ready) result ^= 0x40;
472	472	if (atarigen_sound_to_cpu_ready) result ^= 0x20;
473	473	break;
r2864	r2865
604	604	0x01 = coin R (active high)
605	605	*/
606	606	result = input_port_read(machine, "JSAIII");
607		if (!(input_port_read~~_indexed~~(machine, test_port) & test_mask)) result ^= 0x90;
	607	if (!(input_port_read(machine, test_port) & test_mask)) result ^= 0x90;
608	608	if (atarigen_cpu_to_sound_ready) result ^= 0x40;
609	609	if (atarigen_sound_to_cpu_ready) result ^= 0x20;
610	610	break;

src/mame/audio/atarijsa.h
r2864	r2865
5	5	****************************************************************************/
6	6
7	7
8		void atarijsa_init(running_machine *machine, int testport, int testmask);
	8	void atarijsa_init(running_machine machine, const char testport, int testmask);
9	9	void atarijsa3_init_adpcm(int region);
10	10	void atarijsa_reset(void);
11	11

src/mame/audio/harddriv.c
r2864	r2865
178	178	// D13 = Test Switch
179	179	// D12 = 5220 Ready Flag (0=Ready)
180	180	logerror("%06X:hdsnd68k_status_r(%04X)\n", activecpu_get_previouspc(), offset);
181		return (mainflag << 15) \| (soundflag << 14) \| 0x2000 \| 0;//((input_port_read~~_indexed~~(machine, 0) & 0x0020) << 8) \| 0;
	181	return (mainflag << 15) \| (soundflag << 14) \| 0x2000 \| 0;//((input_port_read(machine, "IN0") & 0x0020) << 8) \| 0;
182	182	}
183	183
184	184

src/mame/audio/dcs.c
r2864	r2865
1301	1301	dmadac_enable(0, dcs.channels, DSIO_MUTE);
1302	1302
1303	1303	/* bit 0 resets the FIFO */
1304		midway_ioasic_fifo_reset_w(DSIO_EMPTY_FIFO ^ 1);
	1304	midway_ioasic_fifo_reset_w(machine, DSIO_EMPTY_FIFO ^ 1);
1305	1305	break;
1306	1306
1307	1307	/* offset 2 controls RAM pages */
r2864	r2865
1372	1372
1373	1373	/* offset 3 controls FIFO reset */
1374	1374	case 3:
1375		midway_ioasic_fifo_reset_w(1);
	1375	midway_ioasic_fifo_reset_w(machine, 1);
1376	1376	break;
1377	1377	}
1378	1378	}

src/mame/machine/rainbow.c
r2864	r2865
48	48	*************************************************************************/
49	49
50	50	#include "driver.h"
51		#include "deprecat.h"
52	51	#include "includes/cchip.h"
53	52
54	53	static UINT8* CRAM[8];
r2864	r2865
714	713	}
715	714	}
716	715
717		static void request_goalin_data(void)
	716	static void request_goalin_data(running_machine *machine)
718	717	{
719		int n = mame_rand(Machine) % 15;
	718	int n = mame_rand(machine) % 15;
720	719
721	720	CRAM[1][0x14B] = 0x00; /* x coordinates */
722	721	CRAM[1][0x14D] = 0x10;
r2864	r2865
751	750
752	751	if (CRAM[1][0x149] == 1)
753	752	{
754		request_goalin_data();
	753	request_goalin_data(machine);
755	754
756	755	CRAM[1][0x149] = 0xFF;
757	756	}

src/mame/machine/scudsp.c
r2864	r2865
50	50
51	51	******************************************************************************************/
52	52	#include "driver.h"
53		#include "deprecat.h"
54	53	#include "machine/scudsp.h"
55	54	#include "osd_cpu.h"
56	55	#include "sound/scsp.h"
r2864	r2865
314	313	return 0;
315	314	}
316	315
317		void dsp_prg_ctrl(UINT32 data)
	316	void dsp_prg_ctrl(running_machine *machine, UINT32 data)
318	317	{
319	318	if(LEF) dsp_reg.pc = (data & 0xff);
320	319	if(EXF) dsp_execute_program();
321	320	if(EF && (!(stv_scu[40] & 0x0020)))
322		cpunum_set_input_line_and_vector(Machine, 0, 0xa, HOLD_LINE , 0x45);
	321	cpunum_set_input_line_and_vector(machine, 0, 0xa, HOLD_LINE , 0x45);
323	322	}
324	323
325	324	void dsp_prg_data(UINT32 data)

src/mame/machine/scudsp.h
r2864	r2865
1	1	/SCU DSP stuff/
2	2
3		extern void dsp_prg_ctrl(UINT32 data);
	3	extern void dsp_prg_ctrl(running_machine *machine, UINT32 data);
4	4	extern void dsp_prg_data(UINT32 data);
5	5	extern void dsp_ram_addr_ctrl(UINT32 data);
6	6	extern void dsp_ram_addr_w(UINT32 data);

src/mame/machine/fd1089.c
r2864	r2865
1116	1116
1117	1117
1118	1118	/* 317-???? FD1089A */
1119		static const UINT8 key_~~alexkidd~~[0x2000] =
	1119	static const UINT8 key_0021[0x2000] =
1120	1120	{
1121	1121	/* data */
1122	1122	0x2b,0xe7,0x6e,0x6f,0x8b,0xcd,0xd8,0x4a,0x23,0x8e,0x30,0x97,0x93,0xe4,0x9b,0x92,
r2864	r2865
6845	6845	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
6846	6846	};
6847	6847
	6848	/* 317-xxxx FD1089A - Partial table. */
	6849	static UINT8 key_wb35[0x2000] =
	6850	{
	6851	/* data */
	6852	0x54,0x36,0xF5,0x8c,0x1a,0xe3,0x2f,0x3a,0x90,0x09,0x3e,0xde,0x33,0x8f,0x63,0x02,
	6853	0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
	6854	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6855	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6856	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6857	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6858	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6859	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6860	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6861	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6862	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6863	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6864	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6865	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6866	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6867	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6868	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6869	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6870	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6871	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6872	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6873	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6874	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6875	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6876	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6877	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6878	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6879	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6880	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6881	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6882	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6883	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6884	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6885	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6886	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6887	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6888	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6889	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6890	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6891	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6892	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6893	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6894	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6895	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6896	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6897	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6898	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6899	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6900	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6901	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6902	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6903	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6904	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6905	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6906	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6907	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6908	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6909	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6910	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6911	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6912	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6913	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6914	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6915	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6916	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6917	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6918	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6919	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6920	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6921	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6922	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6923	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6924	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6925	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6926	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6927	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6928	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6929	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6930	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6931	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6932	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6933	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6934	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6935	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6936	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6937	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6938	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6939	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6940	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6941	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	6942	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7186	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7199	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7200	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7201	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7205	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7206	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7207	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7208	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7220	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7221	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7226	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7227	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7228	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7229	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7230	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7249	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7254	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7255	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7256	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7257	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7258	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7259	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7260	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7268	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7269	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7283	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7287	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7288	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7289	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7290	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7311	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7312	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7313	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7314	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7315	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7316	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7317	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7318	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7319	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7320	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7321	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7331	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7344	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7345	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7346	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7347	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7348	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7349	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7350	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7351	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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	7354	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7355	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7356	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7357	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7358	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7359	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7360	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7361	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7362	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7363	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7364	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7365	0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
	7366	};
6849	7367
6850
6851
6852	7368	struct parameters
6853	7369	{
6854	7370	int xor;
r2864	r2865
7092	7608	sys16_decrypt(key_0018,FD1089A);
7093	7609	}
7094	7610
7095		void fd1089_decrypt_~~alexkidd~~(void)
	7611	void fd1089_decrypt_0021(void)
7096	7612	{
7097		sys16_decrypt(key_~~alexkidd~~,FD1089A);
	7613	sys16_decrypt(key_0021,FD1089A);
7098	7614	}
7099	7615
7100	7616	void fd1089_decrypt_0022(void)
r2864	r2865
7146	7662	{
7147	7663	sys16_decrypt(key_5021,FD1089B);
7148	7664	}
	7665
	7666	void fd1089_decrypt_wb35(void)
	7667	{
	7668	sys16_decrypt(key_wb35,FD1089A);
	7669	}
	7670

src/mame/machine/fd1089.h
r2864	r2865
1		void *fd1089_get_decrypted_base(void);
2		void fd1089_decrypt_0013A(void);
3		void fd1089_decrypt_0018(void);
4		void fd1089_decrypt_alexkidd(void);
5		void fd1089_decrypt_0022(void);
6		void fd1089_decrypt_0024(void);
7		void fd1089_decrypt_0027(void);
8		void fd1089_decrypt_0028(void);
9		void fd1089_decrypt_0033(void);
10		void fd1089_decrypt_0034(void);
11		void fd1089_decrypt_0037(void);
12		void fd1089_decrypt_0167(void);
13		void fd1089_decrypt_0168(void);
14		void fd1089_decrypt_5021(void);
	1	void *fd1089_get_decrypted_base(void);
	2	void fd1089_decrypt_0013A(void);
	3	void fd1089_decrypt_0018(void);
	4	void fd1089_decrypt_0021(void);
	5	void fd1089_decrypt_0022(void);
	6	void fd1089_decrypt_0024(void);
	7	void fd1089_decrypt_0027(void);
	8	void fd1089_decrypt_0028(void);
	9	void fd1089_decrypt_0033(void);
	10	void fd1089_decrypt_0034(void);
	11	void fd1089_decrypt_0037(void);
	12	void fd1089_decrypt_0167(void);
	13	void fd1089_decrypt_0168(void);
	14	void fd1089_decrypt_5021(void);
	15	void fd1089_decrypt_wb35(void);

src/mame/machine/s16fd.c
r2864	r2865
9	9	*/
10	10
11	11	#include "driver.h"
12		#include "deprecat.h"
13	12
14	13	#include "cpu/m68000/m68000.h"
15	14	#include "machine/fd1094.h"
r2864	r2865
195	194
196	195
197	196	/* startup function, to be called from DRIVER_INIT (once on startup) */
198		void fd1094_driver_init(void (set_decrypted)(UINT8 ))
	197	void fd1094_driver_init(running_machine machine, void (set_decrypted)(UINT8 *))
199	198	{
200	199	int i;
201	200
r2864	r2865
218	217
219	218	#ifdef ENABLE_DEBUGGER
220	219	/* key debugging */
221		if (Machine->debug_mode && memory_region(REGION_USER2) != NULL)
	220	if (machine->debug_mode && memory_region(REGION_USER2) != NULL)
222	221	{
223		void fd1094_init_debugging(int, int, int, void (*changed)(void));
224		fd1094_init_debugging(REGION_CPU1, REGION_USER1, REGION_USER2, key_changed);
	222	void fd1094_init_debugging(running_machine , int, int, int, void (changed)(void));
	223	fd1094_init_debugging(machine, REGION_CPU1, REGION_USER1, REGION_USER2, key_changed);
225	224	}
226	225	#endif
227	226
228	227	state_save_register_global(fd1094_selected_state);
229	228	state_save_register_global(fd1094_state);
230		state_save_register_postload(Machine, fd1094_postload, NULL);
	229	state_save_register_postload(machine, fd1094_postload, NULL);
231	230	}

src/mame/machine/asic65.c
r2864	r2865
5	5	*************************************/
6	6
7	7	#include "driver.h"
8		#include "deprecat.h"
9	8	#include "includes/atarig42.h"
10	9	#include "cpu/tms32010/tms32010.h"
11	10	#include "asic65.h"
r2864	r2865
124	123	*
125	124	*************************************/
126	125
127		void asic65_config(int asictype)
	126	void asic65_config(running_machine *machine, int asictype)
128	127	{
129	128	asic65_type = asictype;
130	129	if (asic65_type == ASIC65_ROMBASED)
131		asic65_cpunum = mame_find_cpu_index(Machine, "asic65");
	130	asic65_cpunum = mame_find_cpu_index(machine, "asic65");
132	131	}
133	132
134	133
r2864	r2865
139	138	*
140	139	*************************************/
141	140
142		void asic65_reset(int state)
	141	void asic65_reset(running_machine *machine, int state)
143	142	{
144	143	/* rom-based means reset and clear states */
145	144	if (asic65_type == ASIC65_ROMBASED)
146		cpunum_set_input_line(Machine, asic65_cpunum, INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
	145	cpunum_set_input_line(machine, asic65_cpunum, INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
147	146
148	147	/* otherwise, do it manually */
149	148	else
150	149	{
151		cpunum_suspend(mame_find_cpu_index(Machine, "asic65"), SUSPEND_REASON_DISABLE, 1);
	150	cpunum_suspend(mame_find_cpu_index(machine, "asic65"), SUSPEND_REASON_DISABLE, 1);
152	151
153	152	/* if reset is being signalled, clear everything */
154	153	if (state && !asic65_reset_state)
r2864	r2865
158	157	else if (!state && asic65_reset_state)
159	158	{
160	159	if (asic65_command != -1)
161		asic65_data_w(Machine, 1, asic65_command, 0xffff);
	160	asic65_data_w(machine, 1, asic65_command, 0xffff);
162	161	}
163	162
164	163	/* update the state */

src/mame/machine/asic65.h
r2864	r2865
9	9	#define ASIC65_GUARDIANS 2
10	10	#define ASIC65_ROMBASED 3
11	11
12		void asic65_config(int asictype);
13		void asic65_reset(int state);
	12	void asic65_config(running_machine *machine, int asictype);
	13	void asic65_reset(running_machine *machine, int state);
14	14	WRITE16_HANDLER( asic65_data_w );
15	15	READ16_HANDLER( asic65_r );
16	16	READ16_HANDLER( asic65_io_r );

src/mame/machine/decocass.c
r2864	r2865
181	181	WRITE8_HANDLER( decocass_quadrature_decoder_reset_w )
182	182	{
183	183	/* just latch the analog controls here */
184		decocass_quadrature_decoder[0] = input_port_read_indexed(machine,3);
185		decocass_quadrature_decoder[1] = input_port_read_indexed(machine,4);
186		decocass_quadrature_decoder[2] = input_port_read_indexed(machine,5);
187		decocass_quadrature_decoder[3] = input_port_read_indexed(machine,6);
	184	decocass_quadrature_decoder[0] = input_port_read(machine, "AN0");
	185	decocass_quadrature_decoder[1] = input_port_read(machine, "AN1");
	186	decocass_quadrature_decoder[2] = input_port_read(machine, "AN2");
	187	decocass_quadrature_decoder[3] = input_port_read(machine, "AN3");
188	188	}
189	189
190	190	WRITE8_HANDLER( decocass_adc_w )
r2864	r2865
204	204	READ8_HANDLER( decocass_input_r )
205	205	{
206	206	UINT8 data = 0xff;
	207	static const char *portnames[] = { "IN0", "IN1", "IN2" };
	208
207	209	switch (offset & 7)
208	210	{
209	211	case 0: case 1: case 2:
210		data = input_port_read~~_indexed~~(machine, offset & 7);
	212	data = input_port_read(machine, portnames[offset & 7]);
211	213	break;
212	214	case 3: case 4: case 5: case 6:
213	215	data = decocass_quadrature_decoder[(offset & 7) - 3];

src/mame/machine/konppc.c
r2864	r2865
1	1	/* Konami PowerPC-based 3D games common functions */
2	2
3	3	#include "driver.h"
4		#include "deprecat.h"
5	4	#include "cpu/sharc/sharc.h"
6	5	#include "video/voodoo.h"
7	6	#include "konppc.h"
r2864	r2865
198	197	return dsp_comm_ppc[board][offset];
199	198	}
200	199
201		static void dsp_comm_sharc_w(int board, int offset, UINT32 data)
	200	static void dsp_comm_sharc_w(running_machine *machine, int board, int offset, UINT32 data)
202	201	{
203	202	if (offset >= 2)
204	203	{
r2864	r2865
210	209	case CGBOARD_TYPE_ZR107:
211	210	case CGBOARD_TYPE_GTICLUB:
212	211	{
213		//cpunum_set_input_line(Machine, 2, SHARC_INPUT_FLAG0, ASSERT_LINE);
	212	//cpunum_set_input_line(machine, 2, SHARC_INPUT_FLAG0, ASSERT_LINE);
214	213	cpuintrf_push_context(2);
215	214	sharc_set_flag_input(0, ASSERT_LINE);
216	215	cpuintrf_pop_context();
r2864	r2865
218	217	if (offset == 1)
219	218	{
220	219	if (data & 0x03)
221		cpunum_set_input_line(Machine, 2, INPUT_LINE_IRQ2, ASSERT_LINE);
	220	cpunum_set_input_line(machine, 2, INPUT_LINE_IRQ2, ASSERT_LINE);
222	221	}
223	222	break;
224	223	}
r2864	r2865
303	302
304	303	WRITE32_HANDLER( cgboard_0_comm_sharc_w )
305	304	{
306		dsp_comm_sharc_w(0, offset, data);
	305	dsp_comm_sharc_w(machine, 0, offset, data);
307	306	}
308	307
309	308	READ32_HANDLER( cgboard_0_shared_sharc_r )
r2864	r2865
323	322
324	323	WRITE32_HANDLER( cgboard_1_comm_sharc_w )
325	324	{
326		dsp_comm_sharc_w(1, offset, data);
	325	dsp_comm_sharc_w(machine, 1, offset, data);
327	326	}
328	327
329	328	READ32_HANDLER( cgboard_1_shared_sharc_r )

src/mame/machine/irobot.c
r2864	r2865
5	5	***************************************************************************/
6	6
7	7	#include "driver.h"
8		#include "deprecat.h"
9	8	#include "profiler.h"
10	9	#include "cpu/m6809/m6809.h"
11	10	#include "irobot.h"
r2864	r2865
27	26
28	27	#define IR_CPU_STATE \
29	28	logerror(\
30		"pc: %4x, scanline: %d\n", activecpu_get_previouspc(), video_screen_get_vpos(Machine->primary_screen))
	29	"pc: %4x, scanline: %d\n", activecpu_get_previouspc(), video_screen_get_vpos(machine->primary_screen))
31	30
32	31
33	32	UINT8 irobot_vg_clear;
r2864	r2865
51	50	UINT8 irobot_bufsel;
52	51	UINT8 irobot_alphamap;
53	52
54		static void irmb_run(void);
	53	static void irmb_run(running_machine *machine);
55	54
56	55
57	56	/***********************************************************************/
r2864	r2865
118	117	irvg_running=1;
119	118	}
120	119	if ((data & 0x10) && !(irobot_statwr & 0x10))
121		irmb_run();
	120	irmb_run(machine);
122	121	irobot_statwr = data;
123	122	}
124	123
r2864	r2865
226	225	{
227	226
228	227	if (irobot_control_num == 0)
229		return input_port_read~~_indexed~~(machine, 5);
	228	return input_port_read(machine, "AN0");
230	229	else if (irobot_control_num == 1)
231		return input_port_read~~_indexed~~(machine, 6);
	230	return input_port_read(machine, "AN1");
232	231	return 0;
233	232
234	233	}
r2864	r2865
575	574
576	575
577	576	/* Run mathbox */
578		static void irmb_run(void)
	577	static void irmb_run(running_machine *machine)
579	578	{
580	579	const irmb_ops *prevop = &mbops[0];
581	580	const irmb_ops *curop = &mbops[0];
r2864	r2865
862	861	timer_adjust_oneshot(irmb_timer, attotime_mul(ATTOTIME_IN_NSEC(200), icount), 0);
863	862	}
864	863	#else
865		cpunum_set_input_line(Machine, 0, M6809_FIRQ_LINE, ASSERT_LINE);
	864	cpunum_set_input_line(machine, 0, M6809_FIRQ_LINE, ASSERT_LINE);
866	865	#endif
867	866	irmb_running=1;
868	867	}

src/mame/machine/leland.c
r2864	r2865
128	128
129	129	READ8_HANDLER( cerberus_dial_1_r )
130	130	{
131		int original = input_port_read_indexed(machine, 0);
132		int modified = dial_compute_value(input_port_read_indexed(machine, 4), 0);
	131	int original = input_port_read(machine, "IN0");
	132	int modified = dial_compute_value(input_port_read(machine, "AN0"), 0);
133	133	return (original & 0xc0) \| ((modified & 0x80) >> 2) \| (modified & 0x1f);
134	134	}
135	135
136	136
137	137	READ8_HANDLER( cerberus_dial_2_r )
138	138	{
139		int original = input_port_read_indexed(machine, 2);
140		int modified = dial_compute_value(input_port_read_indexed(machine, 5), 1);
	139	int original = input_port_read(machine, "IN0");
	140	int modified = dial_compute_value(input_port_read(machine, "AN1"), 1);
141	141	return (original & 0xc0) \| ((modified & 0x80) >> 2) \| (modified & 0x1f);
142	142	}
143	143
r2864	r2865
181	181
182	182	static void update_dangerz_xy(running_machine *machine)
183	183	{
184		UINT8 newy = input_port_read_indexed(machine, 4);
185		UINT8 newx = input_port_read_indexed(machine, 5);
	184	UINT8 newy = input_port_read(machine, "AN0");
	185	UINT8 newx = input_port_read(machine, "AN1");
186	186	int deltay = newy - dial_last_input[0];
187	187	int deltax = newx - dial_last_input[1];
188	188
r2864	r2865
235	235
236	236	READ8_HANDLER( redline_pedal_1_r )
237	237	{
238		int pedal = input_port_read~~_indexed~~(machine, 0);
	238	int pedal = input_port_read(machine, "IN0");
239	239	return redline_pedal_value[pedal >> 5] \| 0x0f;
240	240	}
241	241
242	242
243	243	READ8_HANDLER( redline_pedal_2_r )
244	244	{
245		int pedal = input_port_read~~_indexed~~(machine, 2);
	245	int pedal = input_port_read(machine, "IN2");
246	246	return redline_pedal_value[pedal >> 5] \| 0x0f;
247	247	}
248	248
249	249
250	250	READ8_HANDLER( redline_wheel_1_r )
251	251	{
252		return dial_compute_value(input_port_read~~_indexed~~(machine, 4), 0);
	252	return dial_compute_value(input_port_read(machine, "AN0"), 0);
253	253	}
254	254
255	255
256	256	READ8_HANDLER( redline_wheel_2_r )
257	257	{
258		return dial_compute_value(input_port_read~~_indexed~~(machine, 5), 1);
	258	return dial_compute_value(input_port_read(machine, "AN1"), 1);
259	259	}
260	260
261	261
r2864	r2865
268	268
269	269	READ8_HANDLER( offroad_wheel_1_r )
270	270	{
271		return dial_compute_value(input_port_read~~_indexed~~(machine, 7), 0);
	271	return dial_compute_value(input_port_read(machine, "AN3"), 0);
272	272	}
273	273
274	274
275	275	READ8_HANDLER( offroad_wheel_2_r )
276	276	{
277		return dial_compute_value(input_port_read~~_indexed~~(machine, 8), 1);
	277	return dial_compute_value(input_port_read(machine, "AN4"), 1);
278	278	}
279	279
280	280
281	281	READ8_HANDLER( offroad_wheel_3_r )
282	282	{
283		return dial_compute_value(input_port_read~~_indexed~~(machine, 9), 2);
	283	return dial_compute_value(input_port_read(machine, "AN5"), 2);
284	284	}
285	285
286	286
r2864	r2865
293	293
294	294	READ8_HANDLER( ataxx_trackball_r )
295	295	{
296		return dial_compute_value(input_port_read_indexed(machine, 3 + offset), offset);
	296	static const char *tracknames[] = { "AN0", "AN1", "AN2", "AN3" };
	297
	298	return dial_compute_value(input_port_read(machine, tracknames[offset]), offset);
297	299	}
298	300
299	301
r2864	r2865
306	308
307	309	READ8_HANDLER( indyheat_wheel_r )
308	310	{
309		return dial_compute_value(input_port_read_indexed(machine, 3 + offset), offset);
	311	static const char *tracknames[] = { "AN0", "AN1", "AN2" };
	312
	313	return dial_compute_value(input_port_read(machine, tracknames[offset]), offset);
310	314	}
311	315
312	316
r2864	r2865
333	337
334	338	WRITE8_HANDLER( indyheat_analog_w )
335	339	{
	340	static const char *tracknames[] = { "AN3", "AN4", "AN5" };
	341
336	342	switch (offset)
337	343	{
338	344	case 3:
339		analog_result = input_port_read~~_indexed~~(machine, ~~6 +~~ data);
	345	analog_result = input_port_read(machine, tracknames[data]);
340	346	break;
341	347
342	348	case 0:
r2864	r2865
492	498	INTERRUPT_GEN( leland_master_interrupt )
493	499	{
494	500	/* check for coins here */
495		if ((input_port_read~~_indexed~~(machine, 1) & 0x0e) != 0x0e)
	501	if ((input_port_read(machine, "IN1") & 0x0e) != 0x0e)
496	502	cpunum_set_input_line(machine, 0, INPUT_LINE_NMI, ASSERT_LINE);
497	503	}
498	504
r2864	r2865
843	849
844	850	READ8_HANDLER( ataxx_eeprom_r )
845	851	{
846		int port = input_port_read~~_indexed~~(machine, 2);
	852	int port = input_port_read(machine, "IN2");
847	853	if (LOG_EEPROM) logerror("%04X:EE read\n", safe_activecpu_get_pc());
848	854	return (port & ~0x01) \| eeprom_read_bit();
849	855	}
r2864	r2865
1107	1113
1108	1114	WRITE8_HANDLER( leland_master_analog_key_w )
1109	1115	{
	1116	static const char *portnames[] = { "AN0", "AN1", "AN2", "AN3", "AN4", "AN5" };
	1117
1110	1118	switch (offset)
1111	1119	{
1112	1120	case 0x00: /* FD = analog port trigger */
1113	1121	break;
1114	1122
1115	1123	case 0x01: /* FE = analog port select/bankswitch */
1116		analog_result = input_port_read~~_indexed~~(machine, (data & 15~~) + 4~~);
	1124	analog_result = input_port_read(machine, portnames[data & 15]);
1117	1125
1118	1126	/* update top board banking for some games */
1119	1127	if (LOG_BANKSWITCHING_M)
r2864	r2865
1144	1152	switch (offset)
1145	1153	{
1146	1154	case 0x00: /* /GIN0 */
1147		result = input_port_read~~_indexed~~(machine, 0);
	1155	result = input_port_read(machine, "IN0");
1148	1156	break;
1149	1157
1150	1158	case 0x01: /* /GIN1 */
1151		result = input_port_read~~_indexed~~(machine, 1);
	1159	result = input_port_read(machine, "IN1");
1152	1160	if (cpunum_get_reg(1, Z80_HALT))
1153	1161	result ^= 0x01;
1154	1162	break;
r2864	r2865
1164	1172	break;
1165	1173
1166	1174	case 0x10: /* /GIN0 */
1167		result = input_port_read~~_indexed~~(machine, 2);
	1175	result = input_port_read(machine, "IN2");
1168	1176	break;
1169	1177
1170	1178	case 0x11: /* /GIN1 */
1171		result = input_port_read~~_indexed~~(machine, 3);
	1179	result = input_port_read(machine, "IN3");
1172	1180	if (LOG_EEPROM) logerror("%04X:EE read\n", safe_activecpu_get_pc());
1173	1181	result = (result & ~0x01) \| eeprom_read_bit();
1174	1182	break;
r2864	r2865
1227	1235	switch (offset)
1228	1236	{
1229	1237	case 0x06: /* /GIN0 */
1230		result = input_port_read~~_indexed~~(machine, 0);
	1238	result = input_port_read(machine, "IN0");
1231	1239	break;
1232	1240
1233	1241	case 0x07: /* /SLVBLK */
1234		result = input_port_read~~_indexed~~(machine, 1);
	1242	result = input_port_read(machine, "IN1");
1235	1243	if (cpunum_get_reg(1, Z80_HALT))
1236	1244	result ^= 0x01;
1237	1245	break;

src/mame/machine/midwayic.c
r2864	r2865
108	108	*
109	109	*************************************/
110	110
111		static void generate_serial_data(int upper)
	111	static void generate_serial_data(running_machine *machine, int upper)
112	112	{
113		int year = atoi(Machine->gamedrv->year), month = 12, day = 11;
	113	int year = atoi(machine->gamedrv->year), month = 12, day = 11;
114	114	UINT32 serial_number, temp;
115	115	UINT8 serial_digit[9];
116	116
r2864	r2865
127	127	serial_digit[7] = (serial_number / 10) % 10;
128	128	serial_digit[8] = (serial_number / 1) % 10;
129	129
130		serial.data[12] = mame_rand(Machine) & 0xff;
131		serial.data[13] = mame_rand(Machine) & 0xff;
	130	serial.data[12] = mame_rand(machine) & 0xff;
	131	serial.data[13] = mame_rand(machine) & 0xff;
132	132
133	133	serial.data[14] = 0; /* ??? */
134	134	serial.data[15] = 0; /* ??? */
r2864	r2865
182	182	}
183	183
184	184
185		void midway_serial_pic_init(int upper)
	185	void midway_serial_pic_init(running_machine *machine, int upper)
186	186	{
187	187	serial_register_state();
188		generate_serial_data(upper);
	188	generate_serial_data(machine, upper);
189	189	}
190	190
191	191
r2864	r2865
282	282	}
283	283
284	284
285		void midway_serial_pic2_init(int upper, int yearoffs)
	285	void midway_serial_pic2_init(running_machine *machine, int upper, int yearoffs)
286	286	{
287	287	serial_register_state();
288	288	pic_register_state();
r2864	r2865
291	291	pic.time_just_written = 0;
292	292	pic.time_write_timer = timer_alloc(reset_timer, NULL);
293	293	memset(pic.default_nvram, 0xff, sizeof(pic.default_nvram));
294		generate_serial_data(upper);
	294	generate_serial_data(machine, upper);
295	295	}
296	296
297	297
r2864	r2865
340	340	}
341	341
342	342
343		void midway_serial_pic2_w(UINT8 data)
	343	void midway_serial_pic2_w(running_machine *machine, UINT8 data)
344	344	{
345	345	static FILE *nvramlog;
346	346	if (LOG_NVRAM && !nvramlog)
r2864	r2865
391	391	if (!pic.time_just_written)
392	392	{
393	393	mame_system_time systime;
394		mame_get_base_datetime(Machine, &systime);
	394	mame_get_base_datetime(machine, &systime);
395	395
396	396	pic.buffer[pic.total++] = make_bcd(systime.local_time.second);
397	397	pic.buffer[pic.total++] = make_bcd(systime.local_time.minute);
r2864	r2865
569	569	static UINT16 ioasic_fifo_status_r(void);
570	570	static void ioasic_input_empty(int state);
571	571	static void ioasic_output_full(int state);
572		static void update_ioasic_irq(void);
	572	static void update_ioasic_irq(running_machine *machine);
573	573	static void cage_irq_handler(running_machine *machine, int state);
574	574
575	575
r2864	r2865
589	589	}
590	590
591	591
592		void midway_ioasic_init(int shuffle, int upper, int yearoffs, void (irq_callback)(running_machine , int))
	592	void midway_ioasic_init(running_machine machine, int shuffle, int upper, int yearoffs, void (irq_callback)(running_machine *, int))
593	593	{
594	594	static const UINT8 shuffle_maps[][16] =
595	595	{
r2864	r2865
607	607	ioasic_register_state();
608	608
609	609	/* do we have a DCS2 sound chip connected? (most likely) */
610		ioasic.has_dcs = (mame_find_cpu_index(Machine, "dcs2") != -1 \|\| mame_find_cpu_index(Machine, "dsio") != -1 \|\| mame_find_cpu_index(Machine, "denver") != -1);
611		ioasic.has_cage = (mame_find_cpu_index(Machine, "cage") != -1);
612		ioasic.dcs_cpu = mame_find_cpu_index(Machine, "dcs2");
	610	ioasic.has_dcs = (mame_find_cpu_index(machine, "dcs2") != -1 \|\| mame_find_cpu_index(machine, "dsio") != -1 \|\| mame_find_cpu_index(machine, "denver") != -1);
	611	ioasic.has_cage = (mame_find_cpu_index(machine, "cage") != -1);
	612	ioasic.dcs_cpu = mame_find_cpu_index(machine, "dcs2");
613	613	if (ioasic.dcs_cpu == (UINT8)-1)
614		ioasic.dcs_cpu = mame_find_cpu_index(Machine, "dsio");
	614	ioasic.dcs_cpu = mame_find_cpu_index(machine, "dsio");
615	615	if (ioasic.dcs_cpu == (UINT8)-1)
616		ioasic.dcs_cpu = mame_find_cpu_index(Machine, "denver");
	616	ioasic.dcs_cpu = mame_find_cpu_index(machine, "denver");
617	617	ioasic.shuffle_type = shuffle;
618	618	ioasic.shuffle_map = &shuffle_maps[shuffle][0];
619	619	ioasic.auto_ack = 0;
620	620	ioasic.irq_callback = irq_callback;
621	621
622	622	/* initialize the PIC */
623		midway_serial_pic2_init(upper, yearoffs);
	623	midway_serial_pic2_init(machine, upper, yearoffs);
624	624
625	625	/* reset the chip */
626		midway_ioasic_reset();
	626	midway_ioasic_reset(machine);
627	627	ioasic.reg[IOASIC_SOUNDCTL] = 0x0001;
628	628
629	629	/* configure the fifo */
r2864	r2865
632	632	dcs_set_fifo_callbacks(ioasic_fifo_r, ioasic_fifo_status_r);
633	633	dcs_set_io_callbacks(ioasic_output_full, ioasic_input_empty);
634	634	}
635		midway_ioasic_fifo_reset_w(1);
	635	midway_ioasic_fifo_reset_w(machine, 1);
636	636
637	637	/* configure the CAGE IRQ */
638	638	if (ioasic.has_cage)
r2864	r2865
652	652	}
653	653
654	654
655		void midway_ioasic_reset(void)
	655	void midway_ioasic_reset(running_machine *machine)
656	656	{
657	657	ioasic.shuffle_active = 0;
658	658	ioasic.sound_irq_state = 0x0080;
659	659	ioasic.reg[IOASIC_INTCTL] = 0;
660	660	if (ioasic.has_dcs)
661		midway_ioasic_fifo_reset_w(1);
662		update_ioasic_irq();
	661	midway_ioasic_fifo_reset_w(machine, 1);
	662	update_ioasic_irq(machine);
663	663	midway_serial_pic_reset_w(1);
664	664	}
665	665
666	666
667		static void update_ioasic_irq(void)
	667	static void update_ioasic_irq(running_machine *machine)
668	668	{
669	669	UINT16 fifo_state = ioasic_fifo_status_r();
670	670	UINT16 irqbits = 0x2000;
r2864	r2865
685	685	{
686	686	ioasic.irq_state = new_state;
687	687	if (ioasic.irq_callback)
688		(*ioasic.irq_callback)(Machine, ioasic.irq_state ? ASSERT_LINE : CLEAR_LINE);
	688	(*ioasic.irq_callback)(machine, ioasic.irq_state ? ASSERT_LINE : CLEAR_LINE);
689	689	}
690	690	}
691	691
r2864	r2865
698	698	ioasic.sound_irq_state \|= 0x0040;
699	699	if (reason & CAGE_IRQ_REASON_BUFFER_EMPTY)
700	700	ioasic.sound_irq_state \|= 0x0080;
701		update_ioasic_irq();
	701	update_ioasic_irq(machine);
702	702	}
703	703
704	704
r2864	r2865
709	709	ioasic.sound_irq_state \|= 0x0080;
710	710	else
711	711	ioasic.sound_irq_state &= ~0x0080;
712		update_ioasic_irq();
	712	update_ioasic_irq(Machine);
713	713	}
714	714
715	715
r2864	r2865
720	720	ioasic.sound_irq_state \|= 0x0040;
721	721	else
722	722	ioasic.sound_irq_state &= ~0x0040;
723		update_ioasic_irq();
	723	update_ioasic_irq(Machine);
724	724	}
725	725
726	726
r2864	r2865
741	741	/* fetch the data from the buffer and update the IOASIC state */
742	742	result = ioasic.fifo[ioasic.fifo_out++ % FIFO_SIZE];
743	743	ioasic.fifo_bytes--;
744		update_ioasic_irq();
	744	update_ioasic_irq(Machine);
745	745
746	746	if (LOG_FIFO && (ioasic.fifo_bytes < 4 \|\| ioasic.fifo_bytes >= FIFO_SIZE - 4))
747	747	logerror("fifo_r(%04X): FIFO bytes = %d!\n", result, ioasic.fifo_bytes);
r2864	r2865
796	796	}
797	797
798	798
799		void midway_ioasic_fifo_reset_w(int state)
	799	void midway_ioasic_fifo_reset_w(running_machine *machine, int state)
800	800	{
801	801	/* on the high state, reset the FIFO data */
802	802	if (state)
r2864	r2865
805	805	ioasic.fifo_out = 0;
806	806	ioasic.fifo_bytes = 0;
807	807	ioasic.force_fifo_full = 0;
808		update_ioasic_irq();
	808	update_ioasic_irq(machine);
809	809	}
810	810	if (LOG_FIFO)
811	811	logerror("%08X:fifo_reset(%d)\n", safe_activecpu_get_pc(), state);
812	812	}
813	813
814	814
815		void midway_ioasic_fifo_w(UINT16 data)
	815	void midway_ioasic_fifo_w(running_machine *machine, UINT16 data)
816	816	{
817	817	/* if we have room, add it to the FIFO buffer */
818	818	if (ioasic.fifo_bytes < FIFO_SIZE)
819	819	{
820	820	ioasic.fifo[ioasic.fifo_in++ % FIFO_SIZE] = data;
821	821	ioasic.fifo_bytes++;
822		update_ioasic_irq();
	822	update_ioasic_irq(machine);
823	823	if (LOG_FIFO && (ioasic.fifo_bytes < 4 \|\| ioasic.fifo_bytes >= FIFO_SIZE - 4))
824	824	logerror("fifo_w(%04X): FIFO bytes = %d!\n", data, ioasic.fifo_bytes);
825	825	}
r2864	r2865
832	832	}
833	833
834	834
835		void midway_ioasic_fifo_full_w(UINT16 data)
	835	void midway_ioasic_fifo_full_w(running_machine *machine, UINT16 data)
836	836	{
837	837	if (LOG_FIFO)
838	838	logerror("fifo_full_w(%04X)\n", data);
839	839	ioasic.force_fifo_full = 1;
840		update_ioasic_irq();
	840	update_ioasic_irq(machine);
841	841	dcs_fifo_notify(ioasic.fifo_bytes, FIFO_SIZE);
842	842	}
843	843
r2864	r2865
992	992	{
993	993	/* we're in loopback mode -- copy to the input */
994	994	ioasic.reg[IOASIC_UARTIN] = (newreg & 0x00ff) \| 0x1000;
995		update_ioasic_irq();
	995	update_ioasic_irq(machine);
996	996	}
997	997	else if (PRINTF_DEBUG)
998	998	mame_printf_debug("%c", data & 0xff);
r2864	r2865
1015	1015	}
1016	1016
1017	1017	/* FIFO reset? */
1018		midway_ioasic_fifo_reset_w(~newreg & 4);
	1018	midway_ioasic_fifo_reset_w(machine, ~newreg & 4);
1019	1019	break;
1020	1020
1021	1021	case IOASIC_SOUNDOUT:
r2864	r2865
1032	1032
1033	1033	case IOASIC_PICOUT:
1034	1034	if (ioasic.shuffle_type == MIDWAY_IOASIC_VAPORTRX)
1035		midway_serial_pic2_w(newreg ^ 0x0a);
	1035	midway_serial_pic2_w(machine, newreg ^ 0x0a);
1036	1036	else if (ioasic.shuffle_type == MIDWAY_IOASIC_SFRUSHRK)
1037		midway_serial_pic2_w(newreg ^ 0x05);
	1037	midway_serial_pic2_w(machine, newreg ^ 0x05);
1038	1038	else
1039		midway_serial_pic2_w(newreg);
	1039	midway_serial_pic2_w(machine, newreg);
1040	1040	break;
1041	1041
1042	1042	case IOASIC_INTCTL:
r2864	r2865
1048	1048	/* bit 14 = LED? */
1049	1049	if ((oldreg ^ newreg) & 0x3ff6)
1050	1050	logerror("IOASIC int control = %04X\n", data);
1051		update_ioasic_irq();
	1051	update_ioasic_irq(machine);
1052	1052	break;
1053	1053
1054	1054	default:

src/mame/machine/midwayic.h
r2864	r2865
6	6
7	7
8	8	/* 1st generation Midway serial PIC */
9		void midway_serial_pic_init(int upper);
	9	void midway_serial_pic_init(running_machine *machine, int upper);
10	10	void midway_serial_pic_reset_w(int state);
11	11	UINT8 midway_serial_pic_status_r(void);
12	12	UINT8 midway_serial_pic_r(void);
r2864	r2865
14	14
15	15
16	16	/* 2nd generation Midway serial/NVRAM/RTC PIC */
17		void midway_serial_pic2_init(int upper, int yearoffs);
	17	void midway_serial_pic2_init(running_machine *machine, int upper, int yearoffs);
18	18	void midway_serial_pic2_set_default_nvram(const UINT8 *nvram);
19	19	UINT8 midway_serial_pic2_status_r(void);
20	20	UINT8 midway_serial_pic2_r(void);
21		void midway_serial_pic2_w(UINT8 data);
	21	void midway_serial_pic2_w(running_machine *machine, UINT8 data);
22	22	NVRAM_HANDLER( midway_serial_pic2 );
23	23
24	24
25	25	/* I/O ASIC connected to 2nd generation PIC */
26		void midway_ioasic_init(int shuffle, int upper, int yearoffs, void (irq_callback)(running_machine , int));
	26	void midway_ioasic_init(running_machine machine, int shuffle, int upper, int yearoffs, void (irq_callback)(running_machine *, int));
27	27	void midway_ioasic_set_auto_ack(int auto_ack);
28	28	void midway_ioasic_set_shuffle_state(int state);
29		void midway_ioasic_reset(void);
30		void midway_ioasic_fifo_w(UINT16 data);
31		void midway_ioasic_fifo_reset_w(int state);
32		void midway_ioasic_fifo_full_w(UINT16 data);
	29	void midway_ioasic_reset(running_machine *machine);
	30	void midway_ioasic_fifo_w(running_machine *machine, UINT16 data);
	31	void midway_ioasic_fifo_reset_w(running_machine *machine, int state);
	32	void midway_ioasic_fifo_full_w(running_machine *machine, UINT16 data);
33	33	READ32_HANDLER( midway_ioasic_r );
34	34	WRITE32_HANDLER( midway_ioasic_w );
35	35	READ32_HANDLER( midway_ioasic_packed_r );

src/mame/machine/konamigx.c
r2864	r2865
7	7	*/
8	8
9	9	#include "driver.h"
10		#include "deprecat.h"
11	10	#include "video/konamiic.h"
12	11	#include "machine/konamigx.h"
13	12
r2864	r2865
208	207	cliprect->max_y = maxy;
209	208	}
210	209
211		INLINE void K053936GP_copyroz32clip( bitmap_t dst_bitmap, bitmap_t src_bitmap,
	210	INLINE void K053936GP_copyroz32clip( running_machine *machine,
	211	bitmap_t dst_bitmap, bitmap_t src_bitmap,
212	212	const rectangle dst_cliprect, const rectangle src_cliprect,
213	213	UINT32 _startx,UINT32 _starty,int _incxx,int _incxy,int _incyx,int _incyy,
214	214	int tilebpp, int blend, int clip )
r2864	r2865
257	257	ecx = tx = -tx;
258	258
259	259	tilebpp = (tilebpp-1) & 7;
260		pal_base = Machine->pens;
	260	pal_base = machine->pens;
261	261	cmask = colormask[tilebpp];
262	262
263	263	src_pitch = src_bitmap->rowpixels;
r2864	r2865
358	358	}
359	359
360	360	// adpoted from generic K053936_zoom_draw()
361		static void K053936GP_zoom_draw(int chip, UINT16 ctrl, UINT16 linectrl,
	361	static void K053936GP_zoom_draw(running_machine *machine,
	362	int chip, UINT16 ctrl, UINT16 linectrl,
362	363	bitmap_t bitmap, const rectangle cliprect, tilemap *tmap,
363	364	int tilebpp, int blend)
364	365	{
r2864	r2865
397	398	startx -= K053936_offset[chip][0] * incxx;
398	399	starty -= K053936_offset[chip][0] * incxy;
399	400
400		K053936GP_copyroz32clip(bitmap, src_bitmap, &my_clip, src_cliprect,
	401	K053936GP_copyroz32clip(machine,
	402	bitmap, src_bitmap, &my_clip, src_cliprect,
401	403	startx<<5, starty<<5, incxx<<5, incxy<<5, 0, 0,
402	404	tilebpp, blend, clip);
403	405	y++;
r2864	r2865
421	423	startx -= K053936_offset[chip][0] * incxx;
422	424	starty -= K053936_offset[chip][0] * incxy;
423	425
424		K053936GP_copyroz32clip(bitmap, src_bitmap, cliprect, src_cliprect,
	426	K053936GP_copyroz32clip(machine,
	427	bitmap, src_bitmap, cliprect, src_cliprect,
425	428	startx<<5, starty<<5, incxx<<5, incxy<<5, incyx<<5, incyy<<5,
426	429	tilebpp, blend, clip);
427	430	}
428	431	}
429	432
430		void K053936GP_0_zoom_draw(bitmap_t bitmap, const rectangle cliprect,
	433	void K053936GP_0_zoom_draw(running_machine machine, bitmap_t bitmap, const rectangle *cliprect,
431	434	tilemap *tmap, int tilebpp, int blend)
432	435	{
433		K053936GP_zoom_draw(0,K053936_0_ctrl,K053936_0_linectrl,bitmap,cliprect,tmap,tilebpp,blend);
	436	K053936GP_zoom_draw(machine, 0,K053936_0_ctrl,K053936_0_linectrl,bitmap,cliprect,tmap,tilebpp,blend);
434	437	}
435	438
436		void K053936GP_1_zoom_draw(bitmap_t bitmap, const rectangle cliprect,
	439	void K053936GP_1_zoom_draw(running_machine machine, bitmap_t bitmap, const rectangle *cliprect,
437	440	tilemap *tmap, int tilebpp, int blend)
438	441	{
439		K053936GP_zoom_draw(1,K053936_1_ctrl,K053936_1_linectrl,bitmap,cliprect,tmap,tilebpp,blend);
	442	K053936GP_zoom_draw(machine, 1,K053936_1_ctrl,K053936_1_linectrl,bitmap,cliprect,tmap,tilebpp,blend);
440	443	}
441	444
442	445
r2864	r2865
457	460	pri : 0 = topmost, 255 = backmost (pixel priority)
458	461	*/
459	462
460		INLINE void zdrawgfxzoom32GP( bitmap_t bitmap, const gfx_element gfx, const rectangle *cliprect,
	463	INLINE void zdrawgfxzoom32GP( running_machine *machine,
	464	bitmap_t bitmap, const gfx_element gfx, const rectangle *cliprect,
461	465	UINT32 code, UINT32 color, int flipx, int flipy, int sx, int sy,
462	466	int scalex, int scaley, int alpha, int drawmode, int zcode, int pri)
463	467	{
r2864	r2865
522	526	src_fh = 16;
523	527	src_base = gfx->gfxdata + (code % gfx->total_elements) * gfx->char_modulo;
524	528
525		pal_base = Machine->pens + gfx->color_base + (color % gfx->total_colors) * granularity;
526		shd_base = Machine->shadow_table;
	529	pal_base = machine->pens + gfx->color_base + (color % gfx->total_colors) * granularity;
	530	shd_base = machine->shadow_table;
527	531
528	532	dst_ptr = bitmap->base;
529	533	dst_pitch = bitmap->rowpixels;
r2864	r2865
1192	1196	K053247_dy = offsy;
1193	1197	}
1194	1198
1195		void konamigx_mixer_init(int objdma)
	1199	void konamigx_mixer_init(running_machine *machine, int objdma)
1196	1200	{
1197	1201	gx_objdma = 0;
1198	1202	gx_primode = 0;
r2864	r2865
1212	1216	else
1213	1217	gx_spriteram = K053247_ram;
1214	1218
1215		palette_set_shadow_dRGB32(Machine, 3,-80,-80,-80, 0);
	1219	palette_set_shadow_dRGB32(machine, 3,-80,-80,-80, 0);
1216	1220	K054338_invert_alpha(1);
1217	1221	}
1218	1222
r2864	r2865
1631	1635	l = sub1flags & 0xf;
1632	1636
1633	1637	if (offs == -2)
1634		K053936GP_0_zoom_draw(bitmap, cliprect, sub1, l, k);
	1638	K053936GP_0_zoom_draw(machine, bitmap, cliprect, sub1, l, k);
1635	1639	else
1636	1640	K053250_draw(machine, bitmap, cliprect, 0, vcblk[4]<<l, 0, 0);
1637	1641	}
r2864	r2865
1660	1664	l = sub2flags & 0xf;
1661	1665
1662	1666	if (offs == -3)
1663		K053936GP_1_zoom_draw(bitmap, cliprect, sub2, l, k);
	1667	K053936GP_1_zoom_draw(machine, bitmap, cliprect, sub2, l, k);
1664	1668	else
1665	1669	K053250_draw(machine, bitmap, cliprect, 1, vcblk[5]<<l, 0, 0);
1666	1670	}
r2864	r2865
1811	1815
1812	1816	if (nozoom) { scaley = scalex = 0x10000; } else { scalex = zw << 12; scaley = zh << 12; };
1813	1817
1814		zdrawgfxzoom32GP(bitmap, K053247_gfx, cliprect,
	1818	zdrawgfxzoom32GP(machine,
	1819	bitmap, K053247_gfx, cliprect,
1815	1820	temp,
1816	1821	color,
1817	1822	temp1,temp2,

src/mame/machine/toaplan1.c
r2864	r2865
4	4	***************************************************************************/
5	5
6	6	#include "driver.h"
7		#include "deprecat.h"
8	7	#include "cpu/m68000/m68000.h"
9	8	#include "cpu/tms32010/tms32010.h"
10	9	#include "includes/toaplan1.h"
r2864	r2865
112	111	}
113	112
114	113
115		static void demonwld_dsp(int enable)
	114	static void demonwld_dsp(running_machine *machine, int enable)
116	115	{
117	116	demonwld_dsp_on = enable;
118	117	if (enable)
119	118	{
120	119	logerror("Turning DSP on and 68000 off\n");
121		cpunum_set_input_line(Machine, 2, INPUT_LINE_HALT, CLEAR_LINE);
122		cpunum_set_input_line(Machine, 2, 0, ASSERT_LINE); /* TMS32010 INT */
123		cpunum_set_input_line(Machine, 0, INPUT_LINE_HALT, ASSERT_LINE);
	120	cpunum_set_input_line(machine, 2, INPUT_LINE_HALT, CLEAR_LINE);
	121	cpunum_set_input_line(machine, 2, 0, ASSERT_LINE); /* TMS32010 INT */
	122	cpunum_set_input_line(machine, 0, INPUT_LINE_HALT, ASSERT_LINE);
124	123	}
125	124	else
126	125	{
127	126	logerror("Turning DSP off\n");
128		cpunum_set_input_line(Machine, 2, 0, CLEAR_LINE); /* TMS32010 INT */
129		cpunum_set_input_line(Machine, 2, INPUT_LINE_HALT, ASSERT_LINE);
	127	cpunum_set_input_line(machine, 2, 0, CLEAR_LINE); /* TMS32010 INT */
	128	cpunum_set_input_line(machine, 2, INPUT_LINE_HALT, ASSERT_LINE);
130	129	}
131	130	}
132	131	static STATE_POSTLOAD( demonwld_restore_dsp )
133	132	{
134		demonwld_dsp(demonwld_dsp_on);
	133	demonwld_dsp(machine, demonwld_dsp_on);
135	134	}
136	135
137	136	WRITE16_HANDLER( demonwld_dsp_ctrl_w )
r2864	r2865
144	143	{
145	144	switch (data)
146	145	{
147		case 0x00: demonwld_dsp(1); break; /* Enable the INT line to the DSP */
148		case 0x01: demonwld_dsp(0); break; /* Inhibit the INT line to the DSP */
	146	case 0x00: demonwld_dsp(machine, 1); break; /* Enable the INT line to the DSP */
	147	case 0x01: demonwld_dsp(machine, 0); break; /* Inhibit the INT line to the DSP */
149	148	default: logerror("68000:%04x Writing unknown command %08x to %08x\n",activecpu_get_previouspc() ,data ,0xe0000a + offset); break;
150	149	}
151	150	}

src/mame/machine/konamigx.h
r2864	r2865
21	21	void K053936GP_set_offset(int chip, int xoffs, int yoffs);
22	22	void K053936GP_clip_enable(int chip, int status);
23	23	void K053936GP_set_cliprect(int chip, int minx, int maxx, int miny, int maxy);
24		void K053936GP_0_zoom_draw(bitmap_t bitmap, const rectangle cliprect, tilemap *tmap, int tilebpp, int blend);
25		void K053936GP_1_zoom_draw(bitmap_t bitmap, const rectangle cliprect, tilemap *tmap, int tilebpp, int blend);
	24	void K053936GP_0_zoom_draw(running_machine machine, bitmap_t bitmap, const rectangle cliprect, tilemap tmap, int tilebpp, int blend);
	25	void K053936GP_1_zoom_draw(running_machine machine, bitmap_t bitmap, const rectangle cliprect, tilemap tmap, int tilebpp, int blend);
26	26
27	27
28	28
r2864	r2865
88	88	tilemap *sub2, int sub2flags,
89	89	int mixerflags);
90	90
91		void konamigx_mixer_init(int objdma);
	91	void konamigx_mixer_init(running_machine *machine, int objdma);
92	92	void konamigx_mixer_primode(int mode);
93	93
94	94

src/mame/machine/namcoio.c
r2864	r2865
898	898
899	899	switch (io[chipnum].type)
900	900	{
901		case NAMCOIO_50XX: return namco_50xx_read();
902		case NAMCOIO_50XX_2: return namco_50xx_2_read();
	901	case NAMCOIO_50XX: return namco_50xx_read(machine);
	902	case NAMCOIO_50XX_2: return namco_50xx_2_read(machine);
903	903	case NAMCOIO_51XX: return namcoio_51XX_read(machine, chipnum);
904	904	case NAMCOIO_53XX_DIGDUG: return namcoio_53XX_digdug_read(machine, chipnum);
905	905	case NAMCOIO_53XX_POLEPOS: return namcoio_53XX_polepos_read(machine, chipnum);
r2864	r2865
916	916
917	917	switch (io[chipnum].type)
918	918	{
919		case NAMCOIO_50XX: namco_50xx_write(data); break;
920		case NAMCOIO_50XX_2: namco_50xx_2_write(data); break;
	919	case NAMCOIO_50XX: namco_50xx_write(machine, data); break;
	920	case NAMCOIO_50XX_2: namco_50xx_2_write(machine, data); break;
921	921	case NAMCOIO_51XX: namcoio_51XX_write(machine,chipnum,data); break;
922	922	case NAMCOIO_52XX: namcoio_52XX_write(data); break;
923	923	case NAMCOIO_54XX: namco_54xx_write(data); break;
r2864	r2865
928	928	}
929	929
930	930
931		static void namco_06xx_read_request(int chipnum)
	931	static void namco_06xx_read_request(running_machine *machine, int chipnum)
932	932	{
933	933	LOG(("requesting read to chip %d\n",chipnum%3));
934	934
935	935	switch (io[chipnum].type)
936	936	{
937		case NAMCOIO_50XX: namco_50xx_read_request(); break;
938		case NAMCOIO_50XX_2: namco_50xx_2_read_request(); break;
	937	case NAMCOIO_50XX: namco_50xx_read_request(machine); break;
	938	case NAMCOIO_50XX_2: namco_50xx_2_read_request(machine); break;
939	939	default:
940	940	logerror("%04x: custom IO type %d read_request unsupported\n",activecpu_get_pc(),io[chipnum].type);
941	941	break;
r2864	r2865
995	995	return customio_command[chip];
996	996	}
997	997
998		static void namco_06xx_ctrl_w(int chip,int data)
	998	static void namco_06xx_ctrl_w(running_machine *machine, int chip,int data)
999	999	{
1000	1000	LOG(("%04x: 06XX #%d command %02x\n",activecpu_get_pc(),chip,data));
1001	1001
r2864	r2865
1020	1020	{
1021	1021	switch (customio_command[chip] & 0xf)
1022	1022	{
1023		case 0x1: namco_06xx_read_request(4*chip + 0); break;
1024		case 0x2: namco_06xx_read_request(4*chip + 1); break;
1025		case 0x4: namco_06xx_read_request(4*chip + 2); break;
1026		case 0x8: namco_06xx_read_request(4*chip + 3); break;
	1023	case 0x1: namco_06xx_read_request(machine, 4*chip + 0); break;
	1024	case 0x2: namco_06xx_read_request(machine, 4*chip + 1); break;
	1025	case 0x4: namco_06xx_read_request(machine, 4*chip + 2); break;
	1026	case 0x8: namco_06xx_read_request(machine, 4*chip + 3); break;
1027	1027	default:
1028	1028	logerror("%04x: 06XX #%d read in unsupported mode %02x\n",activecpu_get_pc(),chip,customio_command[chip]);
1029	1029	}
r2864	r2865
1039	1039	WRITE8_HANDLER( namco_06xx_1_data_w ) { namco_06xx_data_w(machine,1,offset,data); }
1040	1040	READ8_HANDLER( namco_06xx_0_ctrl_r ) { return namco_06xx_ctrl_r(0); }
1041	1041	READ8_HANDLER( namco_06xx_1_ctrl_r ) { return namco_06xx_ctrl_r(1); }
1042		WRITE8_HANDLER( namco_06xx_0_ctrl_w ) { namco_06xx_ctrl_w(0,data); }
1043		WRITE8_HANDLER( namco_06xx_1_ctrl_w ) { namco_06xx_ctrl_w(1,data); }
	1042	WRITE8_HANDLER( namco_06xx_0_ctrl_w ) { namco_06xx_ctrl_w(machine, 0,data); }
	1043	WRITE8_HANDLER( namco_06xx_1_ctrl_w ) { namco_06xx_ctrl_w(machine, 1,data); }

src/mame/machine/gaplus.c
r2864	r2865
38	38	switch (offset)
39	39	{
40	40	case 0:
41		return input_port_read~~_indexed~~(machine, 4 ); /* cabinet & test mode */
	41	return input_port_read(machine, "IN2"); /* cabinet & test mode */
42	42	break;
43	43	case 2:
44	44	return 0x0f;
r2864	r2865
52	52	switch (offset)
53	53	{
54	54	case 0:
55		return input_port_read~~_indexed~~(machine, 4 ); /* cabinet & test mode */
	55	return input_port_read(machine, "IN2"); /* cabinet & test mode */
56	56	break;
57	57	case 1:
58	58	return 0x0f;

src/mame/machine/fddebug.c
r2864	r2865
256	256	FUNCTION PROTOTYPES
257	257	***************************************************************************/
258	258
259		static void set_default_key_params(void);
260		static void load_overlay_file(void);
261		static void save_overlay_file(void);
	259	static void set_default_key_params(running_machine *machine);
	260	static void load_overlay_file(running_machine *machine);
	261	static void save_overlay_file(running_machine *machine);
262	262	static void fd1094_regenerate_key(void);
263	263
264	264	static int instruction_hook(offs_t curpc);
r2864	r2865
479	479	fd1094_init_debugging - set up debugging
480	480	-----------------------------------------------*/
481	481
482		void fd1094_init_debugging(int cpureg, int keyreg, int statreg, void (*changed)(void))
	482	void fd1094_init_debugging(running_machine machine, int cpureg, int keyreg, int statreg, void (changed)(void))
483	483	{
484	484	/* set the key changed callback */
485	485	key_changed = changed;
r2864	r2865
514	514	set_constraint(&constraints[constcount++], 0x000006, FD1094_STATE_RESET, 0x0000, 0xc001);
515	515
516	516	/* determine the key parameters */
517		set_default_key_params();
	517	set_default_key_params(machine);
518	518
519	519	/* read the key overlay file */
520		load_overlay_file();
	520	load_overlay_file(machine);
521	521
522	522	/* add some commands */
523	523	debug_console_register_command("fdsave", CMDFLAG_NONE, 0, 0, 0, execute_fdsave);
r2864	r2865
552	552	name, set some defaults
553	553	-----------------------------------------------*/
554	554
555		static void set_default_key_params(void)
	555	static void set_default_key_params(running_machine *machine)
556	556	{
557	557	static const struct
558	558	{
r2864	r2865
568	568
569	569	/* look for a matching game and set the key appropriately */
570	570	for (keynum = 0; keynum < ARRAY_LENGTH(default_keys); keynum++)
571		if (strcmp(Machine->gamedrv->name, default_keys[keynum].gamename) == 0)
	571	if (strcmp(machine->gamedrv->name, default_keys[keynum].gamename) == 0)
572	572	{
573	573	fd1094_global = default_keys[keynum].global;
574	574	fd1094_seed = default_keys[keynum].seed;
r2864	r2865
583	583	file
584	584	-----------------------------------------------*/
585	585
586		static void load_overlay_file(void)
	586	static void load_overlay_file(running_machine *machine)
587	587	{
588	588	char filename[20];
589	589	file_error filerr;
r2864	r2865
591	591	int pcaddr;
592	592
593	593	/* determine the filename and open the file */
594		sprintf(filename, "%s.kov", Machine->gamedrv->name);
	594	sprintf(filename, "%s.kov", machine->gamedrv->name);
595	595	filerr = mame_fopen(SEARCHPATH_RAW, filename, OPEN_FLAG_READ, &file);
596	596	if (filerr == FILERR_NONE)
597	597	{
r2864	r2865
613	613	file
614	614	-----------------------------------------------*/
615	615
616		static void save_overlay_file(void)
	616	static void save_overlay_file(running_machine *machine)
617	617	{
618	618	char filename[20];
619	619	file_error filerr;
r2864	r2865
621	621	int pcaddr;
622	622
623	623	/* determin the filename and open the file */
624		sprintf(filename, "%s.kov", Machine->gamedrv->name);
	624	sprintf(filename, "%s.kov", machine->gamedrv->name);
625	625	filerr = mame_fopen(SEARCHPATH_RAW, filename, OPEN_FLAG_WRITE \| OPEN_FLAG_CREATE, &file);
626	626	if (filerr == FILERR_NONE)
627	627	{
r2864	r2865
748	748
749	749	static void execute_fdsave(int ref, int params, const char **param)
750	750	{
751		save_overlay_file();
	751	save_overlay_file(Machine);
752	752	debug_console_printf("File saved\n");
753	753	}
754	754

src/mame/machine/namcos1.c
r2864	r2865
542	542	it happens to work correctly also using the standard handling for 0058.
543	543	The schematics don't show A11 being used, so I go for this handling.
544	544	*/
	545
545	546	op = (offset & 0x70) >> 4;
546	547
547	548	if (op == key_reg) return key_id;
r2864	r2865
1209	1210	namcos1_driver_init(&tankfrce_specific);
1210	1211	}
1211	1212
	1213	// Inputs are multiplexed, somehow
	1214	READ8_HANDLER( tankfrc4_input_r )
	1215	{
	1216
	1217	switch (offset)
	1218	{
	1219	case 0:
	1220	return mame_rand(machine);
	1221
	1222	case 1:
	1223	return mame_rand(machine);
	1224
	1225	}
	1226	return 0x00;
	1227
	1228	}
	1229
	1230	DRIVER_INIT( tankfrc4 )
	1231	{
	1232	static const struct namcos1_specific tankfrce_specific=
	1233	{
	1234	key_type3_r,key_type3_w, 185, 5,-1, 1,-1, 2,-1
	1235	};
	1236	namcos1_driver_init(&tankfrce_specific);
	1237
	1238	memory_install_read8_handler(machine, 3, ADDRESS_SPACE_PROGRAM, 0x1400, 0x1401, 0, 0, tankfrc4_input_r);
	1239	}
	1240
1212	1241	/*******************************************************************************
1213	1242	* Dangerous Seed specific (CUS308) *
1214	1243	*******************************************************************************/

src/mame/machine/segaic16.c
r2864	r2865
5	5	***************************************************************************/
6	6
7	7	#include "driver.h"
8		#include "deprecat.h"
9	8	#include "segaic16.h"
10	9	#include "video/resnet.h"
11	10
r2864	r2865
641	640	}
642	641
643	642
644		static void timer_interrupt_ack(int which)
	643	static void timer_interrupt_ack(running_machine *machine, int which)
645	644	{
646	645	if (compare_timer[which].timer_ack)
647		(*compare_timer[which].timer_ack)(Machine);
	646	(*compare_timer[which].timer_ack)(machine);
648	647	}
649	648
650	649
651		static UINT16 compare_timer_r(int which, offs_t offset, UINT16 mem_mask)
	650	static UINT16 compare_timer_r(running_machine *machine, int which, offs_t offset, UINT16 mem_mask)
652	651	{
653	652	offset &= 0xf;
654	653	if (LOG_COMPARE) logerror("%06X:compare%d_r(%X) = %04X\n", activecpu_get_pc(), which, offset, compare_timer[which].regs[offset]);
r2864	r2865
663	662	case 0x6: return compare_timer[which].regs[2];
664	663	case 0x7: return compare_timer[which].regs[7];
665	664	case 0x9:
666		case 0xd: timer_interrupt_ack(which); break;
	665	case 0xd: timer_interrupt_ack(machine, which); break;
667	666	}
668	667	return 0xffff;
669	668	}
670	669
671	670
672		static void compare_timer_w(int which, offs_t offset, UINT16 data, UINT16 mem_mask)
	671	static void compare_timer_w(running_machine *machine, int which, offs_t offset, UINT16 data, UINT16 mem_mask)
673	672	{
674	673	offset &= 0xf;
675	674	if (LOG_COMPARE) logerror("%06X:compare%d_w(%X) = %04X\n", activecpu_get_pc(), which, offset, data);
r2864	r2865
683	682	case 0x8:
684	683	case 0xc: COMBINE_DATA(&compare_timer[which].regs[8]); break;
685	684	case 0x9:
686		case 0xd: timer_interrupt_ack(which); break;
	685	case 0xd: timer_interrupt_ack(machine, which); break;
687	686	case 0xa:
688	687	case 0xe: COMBINE_DATA(&compare_timer[which].regs[10]); break;
689	688	case 0xb:
r2864	r2865
696	695	}
697	696
698	697
699		READ16_HANDLER( segaic16_compare_timer_0_r ) { return compare_timer_r(0, offset, mem_mask); }
700		READ16_HANDLER( segaic16_compare_timer_1_r ) { return compare_timer_r(1, offset, mem_mask); }
701		WRITE16_HANDLER( segaic16_compare_timer_0_w ) { compare_timer_w(0, offset, data, mem_mask); }
702		WRITE16_HANDLER( segaic16_compare_timer_1_w ) { compare_timer_w(1, offset, data, mem_mask); }
	698	READ16_HANDLER( segaic16_compare_timer_0_r ) { return compare_timer_r(machine, 0, offset, mem_mask); }
	699	READ16_HANDLER( segaic16_compare_timer_1_r ) { return compare_timer_r(machine, 1, offset, mem_mask); }
	700	WRITE16_HANDLER( segaic16_compare_timer_0_w ) { compare_timer_w(machine, 0, offset, data, mem_mask); }
	701	WRITE16_HANDLER( segaic16_compare_timer_1_w ) { compare_timer_w(machine, 1, offset, data, mem_mask); }

src/mame/machine/pckeybrd.c
r2864	r2865
17	17	*/
18	18
19	19	#include "driver.h"
20		#include "deprecat.h"
21	20	#include "machine/pckeybrd.h"
22	21
23	22	#ifdef MESS
r2864	r2865
318	317
319	318
320	319
321		void at_keyboard_init(AT_KEYBOARD_TYPE type)
	320	void at_keyboard_init(running_machine *machine, AT_KEYBOARD_TYPE type)
322	321	{
323	322	int i;
324	323
r2864	r2865
343	342	{
344	343	char buf[40];
345	344	sprintf(buf, "pc_keyboard_%d", i);
346		keyboard.ports[i] = input_port_by_tag(Machine->portconfig, buf);
	345	keyboard.ports[i] = input_port_by_tag(machine->portconfig, buf);
347	346	}
348	347
349	348	#ifdef MESS

src/mame/machine/n64.c
r2864	r2865
27	27	static UINT32 mi_interrupt = 0;
28	28	static UINT32 mi_intr_mask = 0;
29	29
30		void signal_rcp_interrupt(int interrupt)
	30	void signal_rcp_interrupt(running_machine *machine, int interrupt)
31	31	{
32	32	if (mi_intr_mask & interrupt)
33	33	{
34	34	mi_interrupt \|= interrupt;
35	35
36		cpunum_set_input_line(Machine, 0, INPUT_LINE_IRQ0, ASSERT_LINE);
	36	cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ0, ASSERT_LINE);
37	37	}
38	38	}
39	39
40		void clear_rcp_interrupt(int interrupt)
	40	void clear_rcp_interrupt(running_machine *machine, int interrupt)
41	41	{
42	42	mi_interrupt &= ~interrupt;
43	43
44	44	//if (!mi_interrupt)
45	45	{
46		cpunum_set_input_line(Machine, 0, INPUT_LINE_IRQ0, CLEAR_LINE);
	46	cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ0, CLEAR_LINE);
47	47	}
48	48	}
49	49
r2864	r2865
75	75	case 0x00/4: // MI_INIT_MODE_REG
76	76	if (data & 0x0800)
77	77	{
78		clear_rcp_interrupt(DP_INTERRUPT);
	78	clear_rcp_interrupt(machine, DP_INTERRUPT);
79	79	}
80	80	break;
81	81
r2864	r2865
223	223
224	224	if (cpunum_get_info_int(1, CPUINFO_INT_REGISTER + RSP_SR) & RSP_STATUS_INTR_BREAK)
225	225	{
226		signal_rcp_interrupt(SP_INTERRUPT);
	226	signal_rcp_interrupt(Machine, SP_INTERRUPT);
227	227	}
228	228	}
229	229	}
r2864	r2865
336	336	}
337	337	if (data & 0x00000008) // clear interrupt
338	338	{
339		clear_rcp_interrupt(SP_INTERRUPT);
	339	clear_rcp_interrupt(machine, SP_INTERRUPT);
340	340	}
341	341	if (data & 0x00000010) // set interrupt
342	342	{
343		signal_rcp_interrupt(SP_INTERRUPT);
	343	signal_rcp_interrupt(machine, SP_INTERRUPT);
344	344	}
345	345	if (data & 0x00000020)
346	346	{
r2864	r2865
491	491	UINT32 dp_status = 0;
492	492
493	493
494		void dp_full_sync(void)
	494	void dp_full_sync(running_machine *machine)
495	495	{
496		signal_rcp_interrupt(DP_INTERRUPT);
	496	signal_rcp_interrupt(machine, DP_INTERRUPT);
497	497	}
498	498
499	499	READ32_HANDLER( n64_dp_reg_r )
r2864	r2865
657	657	break;
658	658
659	659	case 0x10/4: // VI_CURRENT_REG
660		clear_rcp_interrupt(VI_INTERRUPT);
	660	clear_rcp_interrupt(machine, VI_INTERRUPT);
661	661	break;
662	662
663	663	case 0x14/4: // VI_BURST_REG
r2864	r2865
735	735	static int audio_fifo_rpos = 0;
736	736	static int audio_fifo_num = 0;
737	737
738		static void audio_fifo_push(UINT32 address, UINT32 length)
	738	static void audio_fifo_push(running_machine *machine, UINT32 address, UINT32 length)
739	739	{
740	740	AUDIO_DMA *current;
741	741
r2864	r2865
765	765
766	766	if (! (ai_status & 0x40000000))
767	767	{
768		signal_rcp_interrupt(AI_INTERRUPT);
	768	signal_rcp_interrupt(machine, AI_INTERRUPT);
769	769	start_audio_dma();
770	770	}
771	771	}
772	772
773		static void audio_fifo_pop(void)
	773	static void audio_fifo_pop(running_machine *machine)
774	774	{
775	775	audio_fifo_rpos++;
776	776	audio_fifo_num--;
r2864	r2865
788	788	if (audio_fifo_num < AUDIO_DMA_DEPTH)
789	789	{
790	790	ai_status &= ~0x80000001; // FIFO not full
791		signal_rcp_interrupt(AI_INTERRUPT);
	791	signal_rcp_interrupt(machine, AI_INTERRUPT);
792	792	}
793	793	}
794	794
r2864	r2865
832	832
833	833	static TIMER_CALLBACK( audio_timer_callback )
834	834	{
835		audio_fifo_pop();
	835	audio_fifo_pop(machine);
836	836
837	837	// keep playing if there's another DMA queued
838	838	if (audio_fifo_get_top() != NULL)
839	839	{
840	840	start_audio_dma();
841		signal_rcp_interrupt(AI_INTERRUPT);
	841	signal_rcp_interrupt(machine, AI_INTERRUPT);
842	842	}
843	843	else
844	844	{
r2864	r2865
890	890	case 0x04/4: // AI_LEN_REG
891	891	// mame_printf_debug("ai_len = %08X at %08X\n", data, activecpu_get_pc());
892	892	ai_len = data & 0x3ffff; // Hardware v2.0 has 18 bits, v1.0 has 15 bits
893		audio_fifo_push(ai_dram_addr, ai_len);
	893	audio_fifo_push(machine, ai_dram_addr, ai_len);
894	894	break;
895	895
896	896	case 0x08/4: // AI_CONTROL_REG
r2864	r2865
899	899	break;
900	900
901	901	case 0x0c/4:
902		clear_rcp_interrupt(AI_INTERRUPT);
	902	clear_rcp_interrupt(machine, AI_INTERRUPT);
903	903	break;
904	904
905	905	case 0x10/4: // AI_DACRATE_REG
r2864	r2865
985	985	}
986	986	}
987	987
988		signal_rcp_interrupt(PI_INTERRUPT);
	988	signal_rcp_interrupt(machine, PI_INTERRUPT);
989	989	break;
990	990	}
991	991
r2864	r2865
1016	1016	pi_dram_addr += 1;
1017	1017	}
1018	1018	}
1019		signal_rcp_interrupt(PI_INTERRUPT);
	1019	signal_rcp_interrupt(machine, PI_INTERRUPT);
1020	1020
1021	1021	if (pi_first_dma)
1022	1022	{
r2864	r2865
1033	1033	{
1034	1034	if (data & 0x2)
1035	1035	{
1036		clear_rcp_interrupt(PI_INTERRUPT);
	1036	clear_rcp_interrupt(machine, PI_INTERRUPT);
1037	1037	}
1038	1038	break;
1039	1039	}
r2864	r2865
1483	1483	}
1484	1484
1485	1485	si_status \|= 0x1000;
1486		signal_rcp_interrupt(SI_INTERRUPT);
	1486	signal_rcp_interrupt(machine, SI_INTERRUPT);
1487	1487	}
1488	1488
1489	1489	READ32_HANDLER( n64_si_reg_r )
r2864	r2865
1522	1522
1523	1523	case 0x18/4: // SI_STATUS_REG
1524	1524	si_status &= ~0x1000;
1525		clear_rcp_interrupt(SI_INTERRUPT);
	1525	clear_rcp_interrupt(machine, SI_INTERRUPT);
1526	1526	break;
1527	1527
1528	1528	default:
r2864	r2865
1569	1569	}
1570	1570	*/
1571	1571
1572		signal_rcp_interrupt(SI_INTERRUPT);
	1572	signal_rcp_interrupt(machine, SI_INTERRUPT);
1573	1573	}
1574	1574
1575	1575	//static UINT16 crc_seed = 0x3f;
1576	1576
1577		void n64_machine_reset(void)
	1577	void n64_machine_reset(running_machine *machine)
1578	1578	{
1579	1579	int i;
1580	1580	//UINT32 pif_rom = (UINT32)memory_region(REGION_USER1);
r2864	r2865
1642	1642	audio_timer = timer_alloc(audio_timer_callback, NULL);
1643	1643	timer_adjust_oneshot(audio_timer, attotime_never, 0);
1644	1644
1645		cpunum_set_input_line(Machine, 1, INPUT_LINE_HALT, ASSERT_LINE);
	1645	cpunum_set_input_line(machine, 1, INPUT_LINE_HALT, ASSERT_LINE);
1646	1646
1647	1647	// bootcode differs between CIC-chips, so we can use its checksum to detect the CIC-chip
1648	1648	boot_checksum = 0;

src/mame/machine/pckeybrd.h
r2864	r2865
19	19	AT_KEYBOARD_TYPE_MF2
20	20	} AT_KEYBOARD_TYPE;
21	21
22		void at_keyboard_init(AT_KEYBOARD_TYPE type);
	22	void at_keyboard_init(running_machine *machine, AT_KEYBOARD_TYPE type);
23	23
24	24	void at_keyboard_polling(void);
25	25	int at_keyboard_read(void);

src/mame/machine/model3.c
r2864	r2865
5	5	*/
6	6
7	7	#include "driver.h"
8		#include "deprecat.h"
9	8	#include "includes/model3.h"
10	9
11	10	static int m3_step;
r2864	r2865
288	287	/*****************************************************************************/
289	288	/* Epson RTC-72421 */
290	289
291		static UINT8 rtc_get_reg(int reg)
	290	static UINT8 rtc_get_reg(running_machine *machine, int reg)
292	291	{
293	292	mame_system_time systime;
294	293
295		mame_get_current_datetime(Machine, &systime);
	294	mame_get_current_datetime(machine, &systime);
296	295
297	296	switch(reg)
298	297	{
r2864	r2865
354	353	{
355	354	int reg = offset;
356	355	UINT32 data;
357		data = rtc_get_reg(reg) << 24;
	356	data = rtc_get_reg(machine, reg) << 24;
358	357	data \|= 0x30000; /* these bits are set to pass the battery voltage test */
359	358	return data;
360	359	}

src/mame/machine/balsente.c
r2864	r2865
7	7	***************************************************************************/
8	8
9	9	#include "driver.h"
10		#include "deprecat.h"
11	10	#include "cpu/m6809/m6809.h"
12	11	#include "balsente.h"
13	12	#include "sound/cem3394.h"
r2864	r2865
18	17
19	18	/* local prototypes */
20	19	static void poly17_init(void);
21		static void counter_set_out(int which, int gate);
	20	static void counter_set_out(running_machine *machine, int which, int gate);
22	21	static TIMER_CALLBACK( counter_callback );
23	22	static TIMER_CALLBACK( clock_counter_0_ff );
24	23	static void update_grudge_steering(running_machine *machine);
r2864	r2865
392	391	*
393	392	*************************************/
394	393
395		static void m6850_update_io(void)
	394	static void m6850_update_io(running_machine *machine)
396	395	{
397	396	UINT8 new_state;
398	397
r2864	r2865
448	447	/* apply the change */
449	448	if (new_state && !(m6850_status & 0x80))
450	449	{
451		cpunum_set_input_line(Machine, 0, M6809_FIRQ_LINE, ASSERT_LINE);
	450	cpunum_set_input_line(machine, 0, M6809_FIRQ_LINE, ASSERT_LINE);
452	451	m6850_status \|= 0x80;
453	452	}
454	453	else if (!new_state && (m6850_status & 0x80))
455	454	{
456		cpunum_set_input_line(Machine, 0, M6809_FIRQ_LINE, CLEAR_LINE);
	455	cpunum_set_input_line(machine, 0, M6809_FIRQ_LINE, CLEAR_LINE);
457	456	m6850_status &= ~0x80;
458	457	}
459	458
r2864	r2865
466	465	/* apply the change */
467	466	if (new_state && !(m6850_sound_status & 0x80))
468	467	{
469		cpunum_set_input_line(Machine, 1, INPUT_LINE_NMI, ASSERT_LINE);
	468	cpunum_set_input_line(machine, 1, INPUT_LINE_NMI, ASSERT_LINE);
470	469	m6850_sound_status \|= 0x80;
471	470	}
472	471	else if (!new_state && (m6850_sound_status & 0x80))
473	472	{
474		cpunum_set_input_line(Machine, 1, INPUT_LINE_NMI, CLEAR_LINE);
	473	cpunum_set_input_line(machine, 1, INPUT_LINE_NMI, CLEAR_LINE);
475	474	m6850_sound_status &= ~0x80;
476	475	}
477	476	}
r2864	r2865
501	500
502	501	/* clear the overrun and receive buffer full bits */
503	502	m6850_status &= ~0x21;
504		m6850_update_io();
	503	m6850_update_io(machine);
505	504	}
506	505
507	506	return result;
r2864	r2865
513	512	/* set the output data byte and indicate that we're ready to go */
514	513	m6850_output = param;
515	514	m6850_data_ready = 1;
516		m6850_update_io();
	515	m6850_update_io(machine);
517	516	}
518	517
519	518
r2864	r2865
521	520	{
522	521	/* indicate that the transmit buffer is no longer empty and update the I/O state */
523	522	m6850_status &= ~0x02;
524		m6850_update_io();
	523	m6850_update_io(machine);
525	524
526	525	/* set a timer for 500usec later to actually transmit the data */
527	526	/* (this is very important for several games, esp Snacks'n Jaxson) */
r2864	r2865
537	536	m6850_control = data;
538	537
539	538	/* re-update since interrupt enables could have been modified */
540		m6850_update_io();
	539	m6850_update_io(machine);
541	540	}
542	541
543	542	/* output register is at offset 1; set a timer to synchronize the CPUs */
r2864	r2865
570	569
571	570	/* clear the overrun and receive buffer full bits */
572	571	m6850_sound_status &= ~0x21;
573		m6850_update_io();
	572	m6850_update_io(machine);
574	573	}
575	574
576	575	return result;
r2864	r2865
591	590	}
592	591
593	592	/* re-update since interrupt enables could have been modified */
594		m6850_update_io();
	593	m6850_update_io(machine);
595	594	}
596	595
597	596
r2864	r2865
720	719	*
721	720	*************************************/
722	721
723		static void counter_set_gate(int which, int gate)
	722	static void counter_set_gate(running_machine *machine, int which, int gate)
724	723	{
725	724	int oldgate = counter[which].gate;
726	725
r2864	r2865
740	739	/* mode 1 waits for the gate to trigger the counter */
741	740	if (counter[which].mode == 1)
742	741	{
743		counter_set_out(which, 0);
	742	counter_set_out(machine, which, 0);
744	743
745	744	/* add one to the count; technically, OUT goes low on the next clock pulse */
746	745	/* and then starts counting down; it's important that we don't count the first one */
r2864	r2865
753	752	}
754	753
755	754
756		static void counter_set_out(int which, int out)
	755	static void counter_set_out(running_machine *machine, int which, int out)
757	756	{
758	757	/* OUT on counter 2 is hooked to the /INT line on the Z80 */
759	758	if (which == 2)
760		cpunum_set_input_line(Machine, 1, 0, out ? ASSERT_LINE : CLEAR_LINE);
	759	cpunum_set_input_line(machine, 1, 0, out ? ASSERT_LINE : CLEAR_LINE);
761	760
762	761	/* OUT on counter 0 is hooked to the GATE line on counter 1 */
763	762	else if (which == 0)
764		counter_set_gate(1, !out);
	763	counter_set_gate(machine, 1, !out);
765	764
766	765	/* remember the out state */
767	766	counter[which].out = out;
r2864	r2865
777	776	/* set the state of the OUT line */
778	777	/* mode 0 and 1: when firing, transition OUT to high */
779	778	if (counter[param].mode == 0 \|\| counter[param].mode == 1)
780		counter_set_out(param, 1);
	779	counter_set_out(machine, param, 1);
781	780
782	781	/* no other modes handled currently */
783	782	}
r2864	r2865
840	839
841	840	/* if the counter is in mode 0, a write here will reset the OUT state */
842	841	if (counter[which].mode == 0)
843		counter_set_out(which, 0);
	842	counter_set_out(machine, which, 0);
844	843
845	844	/* write the LSB */
846	845	if (counter[which].writebyte == 0)
r2864	r2865
869	868
870	869	/* if the counter is in mode 1, a write here will set the OUT state */
871	870	if (counter[which].mode == 1)
872		counter_set_out(which, 1);
	871	counter_set_out(machine, which, 1);
873	872	}
874	873	break;
875	874
r2864	r2865
880	879
881	880	/* if the counter was in mode 0, a write here will reset the OUT state */
882	881	if (((counter[which].mode >> 1) & 7) == 0)
883		counter_set_out(which, 0);
	882	counter_set_out(machine, which, 0);
884	883
885	884	/* set the mode */
886	885	counter[which].mode = (data >> 1) & 7;
887	886
888	887	/* if the counter is in mode 0, a write here will reset the OUT state */
889	888	if (counter[which].mode == 0)
890		counter_set_out(which, 0);
	889	counter_set_out(machine, which, 0);
891	890	break;
892	891	}
893	892	}
r2864	r2865
1012	1011	}
1013	1012
1014	1013	/* set the actual gate afterwards, since we need to know the old value above */
1015		counter_set_gate(0, (data >> 1) & 1);
	1014	counter_set_gate(machine, 0, (data >> 1) & 1);
1016	1015
1017	1016	/* bits D2 and D4 control the clear/reset flags on the flip-flop that feeds counter 0 */
1018	1017	if (!(data & 0x04)) set_counter_0_ff(machine, 1);
1019	1018	if (!(data & 0x10)) set_counter_0_ff(machine, 0);
1020	1019
1021	1020	/* bit 5 clears the NMI interrupt; recompute the I/O state now */
1022		m6850_update_io();
	1021	m6850_update_io(machine);
1023	1022	}
1024	1023
1025	1024

src/mame/machine/snes.c
r2864	r2865
13	13	#define __MACHINE_SNES_C
14	14
15	15	#include "driver.h"
16		#include "deprecat.h"
17	16	#include "includes/snes.h"
18	17	#include "cpu/g65816/g65816.h"
19	18	#ifdef MESS
r2864	r2865
62	61	} joypad[4];
63	62
64	63	// utility function - latches the H/V counters. Used by IRQ, writes to WRIO, etc.
65		static void snes_latch_counters(void)
	64	static void snes_latch_counters(running_machine *machine)
66	65	{
67		snes_ppu.beam.current_horz = video_screen_get_hpos(Machine->primary_screen) / snes_htmult;
68		snes_ppu.beam.latch_vert = video_screen_get_vpos(Machine->primary_screen);
	66	snes_ppu.beam.current_horz = video_screen_get_hpos(machine->primary_screen) / snes_htmult;
	67	snes_ppu.beam.latch_vert = video_screen_get_vpos(machine->primary_screen);
69	68	snes_ppu.beam.latch_horz = snes_ppu.beam.current_horz;
70	69	snes_ram[STAT78] \|= 0x40; // indicate we latched
71	70	read_ophct = read_opvct = 0; // clear read flags
r2864	r2865
82	81	timer_adjust_oneshot(snes_nmi_timer, attotime_never, 0);
83	82	}
84	83
85		static void snes_hirq_tick(void)
	84	static void snes_hirq_tick(running_machine *machine)
86	85	{
87	86	// latch the counters and pull IRQ
88	87	// (don't need to switch to the 65816 context, we don't do anything dependant on it)
89		snes_latch_counters();
	88	snes_latch_counters(machine);
90	89	snes_ram[TIMEUP] = 0x80; /* Indicate that irq occured */
91		cpunum_set_input_line(Machine, 0, G65816_LINE_IRQ, HOLD_LINE );
	90	cpunum_set_input_line(machine, 0, G65816_LINE_IRQ, HOLD_LINE );
92	91
93	92	// don't happen again
94	93	timer_adjust_oneshot(snes_hirq_timer, attotime_never, 0);
r2864	r2865
96	95
97	96	static TIMER_CALLBACK( snes_hirq_tick_callback )
98	97	{
99		snes_hirq_tick();
	98	snes_hirq_tick(machine);
100	99	}
101	100
102	101	static TIMER_CALLBACK( snes_scanline_tick )
r2864	r2865
117	116	{
118	117	snes_ram[TIMEUP] = 0x80; /* Indicate that irq occured */
119	118	// IRQ latches the counters, do it now
120		snes_latch_counters();
	119	snes_latch_counters(machine);
121	120	cpunum_set_input_line(machine, 0, G65816_LINE_IRQ, HOLD_LINE );
122	121	}
123	122	}
r2864	r2865
141	140	// printf("HIRQ @ %d, %d\n", pixel*snes_htmult, snes_ppu.beam.current_vert);
142	141	if (pixel == 0)
143	142	{
144		snes_hirq_tick();
	143	snes_hirq_tick(machine);
145	144	}
146	145	else
147	146	{
r2864	r2865
176	175	{
177	176	int i;
178	177
179		joypad[0].low = input_port_read_indexed(machine, 0 );
180		joypad[0].high = input_port_read_indexed(machine, 1 );
181		joypad[1].low = input_port_read_indexed(machine, 2 );
182		joypad[1].high = input_port_read_indexed(machine, 3 );
183		joypad[2].low = input_port_read_indexed(machine, 4 );
184		joypad[2].high = input_port_read_indexed(machine, 5 );
185		joypad[3].low = input_port_read_indexed(machine, 6 );
186		joypad[3].high = input_port_read_indexed(machine, 7 );
	178	joypad[0].low = input_port_read(machine, "PAD1L");
	179	joypad[0].high = input_port_read(machine, "PAD1H");
	180	joypad[1].low = input_port_read(machine, "PAD2L");
	181	joypad[1].high = input_port_read(machine, "PAD2H");
	182	joypad[2].low = input_port_read(machine, "PAD3L");
	183	joypad[2].high = input_port_read(machine, "PAD3H");
	184	joypad[3].low = input_port_read(machine, "PAD4L");
	185	joypad[3].high = input_port_read(machine, "PAD4H");
187	186
188	187	// avoid sending signals that could crash games
189	188	for (i = 0; i < 4; i++)
r2864	r2865
729	728	return snes_ram[offset];
730	729	}
731	730	case SLHV: /* Software latch for H/V counter */
732		snes_latch_counters();
	731	snes_latch_counters(machine);
733	732	return 0x0; /* Return value is meaningless */
734	733	case ROAMDATA: /* Read data from OAM (DR) */
735	734	{
r2864	r2865
953	952	#ifndef MESS
954	953	case 0x4100: /* NSS Dip-Switches */
955	954	#ifdef MAME_DEBUG
956		return input_port_read_~~ind~~e~~xed~~(machine, 12);
	955	return input_port_read_safe(machine, "DEBUG1", 0);
957	956	#else
958		return input_port_read~~_indexed~~(machine, 9);
	957	return input_port_read(machine, "DSW");
959	958	#endif /* MAME_DEBUG */
960	959	// case 0x4101: //PC: a104 - a10e - a12a //only nss_actr
961	960	// case 0x420c: //PC: 9c7d - 8fab //only nss_ssoc
r2864	r2865
1384	1383	if (!(snes_ram[WRIO] & 0x80) && (data & 0x80))
1385	1384	{
1386	1385	// external latch
1387		snes_latch_counters();
	1386	snes_latch_counters(machine);
1388	1387	}
1389	1388	case WRMPYA: /* Multiplier A */
1390	1389	break;

src/mame/machine/vertigo.c
r2864	r2865
108	108	static PIT8253_OUTPUT_CHANGED( v_irq3_w )
109	109	{
110	110	if (state)
111		cpunum_set_input_line(Machine, 1, INPUT_LINE_IRQ0, ASSERT_LINE);
	111	cpunum_set_input_line(device->machine, 1, INPUT_LINE_IRQ0, ASSERT_LINE);
112	112
113	113	update_irq_encoder(INPUT_LINE_IRQ3, state);
114	114	}

src/mame/machine/pcshare.c
r2864	r2865
38	38	static TIMER_CALLBACK( pc_keyb_timer );
39	39
40	40
41		void init_pc_common(UINT32 flags, void (*set_keyb_int_func)(int))
	41	void init_pc_common(running_machine machine, UINT32 flags, void (set_keyb_int_func)(int))
42	42	{
43	43	/* PC-XT keyboard */
44	44	if (flags & PCCOMMON_KEYBOARD_AT)
45		at_keyboard_init(AT_KEYBOARD_TYPE_AT);
	45	at_keyboard_init(machine, AT_KEYBOARD_TYPE_AT);
46	46	else
47		at_keyboard_init(AT_KEYBOARD_TYPE_PC);
	47	at_keyboard_init(machine, AT_KEYBOARD_TYPE_PC);
48	48	at_keyboard_set_scan_code_set(1);
49	49
50	50	set_keyb_int = set_keyb_int_func;

src/mame/machine/pcshare.h
r2864	r2865
4	4	#define PCCOMMON_KEYBOARD_PC 0
5	5	#define PCCOMMON_KEYBOARD_AT 1
6	6
7		void init_pc_common(UINT32 flags, void (*set_keyb_int_func)(int));
	7	void init_pc_common(running_machine machine, UINT32 flags, void (set_keyb_int_func)(int));
8	8
9	9	void pc_keyboard(void);
10	10	UINT8 pc_keyb_read(void);

src/mame/machine/atarigen.c
r2864	r2865
8	8
9	9
10	10	#include "driver.h"
11		#include "deprecat.h"
12	11	#include "atarigen.h"
13	12	#include "slapstic.h"
14	13	#include "cpu/m6502/m6502.h"
r2864	r2865
536	535	slapstic and sets the chip number.
537	536	---------------------------------------------------------------*/
538	537
539		void atarigen_slapstic_init(int cpunum, offs_t base, offs_t mirror, int chipnum)
	538	void atarigen_slapstic_init(running_machine *machine, int cpunum, offs_t base, offs_t mirror, int chipnum)
540	539	{
541	540	/* reset in case we have no state */
542	541	atarigen_slapstic_num = chipnum;
r2864	r2865
546	545	if (chipnum != 0)
547	546	{
548	547	/* initialize the slapstic */
549		slapstic_init(chipnum);
	548	slapstic_init(machine, chipnum);
550	549
551	550	/* install the memory handlers */
552		atarigen_slapstic = memory_install_readwrite16_handler(Machine, cpunum, ADDRESS_SPACE_PROGRAM, base, base + 0x7fff, 0, mirror, atarigen_slapstic_r, atarigen_slapstic_w);
	551	atarigen_slapstic = memory_install_readwrite16_handler(machine, cpunum, ADDRESS_SPACE_PROGRAM, base, base + 0x7fff, 0, mirror, atarigen_slapstic_r, atarigen_slapstic_w);
553	552
554	553	/* allocate memory for a copy of bank 0 */
555	554	atarigen_slapstic_bank0 = auto_malloc(0x2000);

src/mame/machine/atarigen.h
r2864	r2865
134	134	SLAPSTIC HANDLING
135	135	---------------------------------------------------------------*/
136	136
137		void atarigen_slapstic_init(int cpunum, offs_t base, offs_t mirror, int chipnum);
	137	void atarigen_slapstic_init(running_machine *machine, int cpunum, offs_t base, offs_t mirror, int chipnum);
138	138	void atarigen_slapstic_reset(void);
139	139
140	140	WRITE16_HANDLER( atarigen_slapstic_w );

src/mame/machine/midwunit.c
r2864	r2865
434	434	/* printf("in=%04X%04X out=%04X%04X\n", umk3_palette[3], umk3_palette[2], umk3_palette[1], umk3_palette[0]); */
435	435	}
436	436
437		static void init_mk3_common(void)
	437	static void init_mk3_common(running_machine *machine)
438	438	{
439	439	/* common init */
440	440	init_wunit_generic();
441	441
442	442	/* serial prefixes 439, 528 */
443		midway_serial_pic_init(528);
	443	midway_serial_pic_init(machine, 528);
444	444	}
445	445
446	446	DRIVER_INIT( mk3 )
447	447	{
448		init_mk3_common();
	448	init_mk3_common(machine);
449	449	}
450	450
451	451	DRIVER_INIT( mk3r20 )
452	452	{
453		init_mk3_common();
	453	init_mk3_common(machine);
454	454	}
455	455
456	456	DRIVER_INIT( mk3r10 )
457	457	{
458		init_mk3_common();
	458	init_mk3_common(machine);
459	459	}
460	460
461	461	DRIVER_INIT( umk3 )
462	462	{
463		init_mk3_common();
	463	init_mk3_common(machine);
464	464	umk3_palette = memory_install_write16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0106a060, 0x0106a09f, 0, 0, umk3_palette_hack_w);
465	465	}
466	466
467	467	DRIVER_INIT( umk3r11 )
468	468	{
469		init_mk3_common();
	469	init_mk3_common(machine);
470	470	umk3_palette = memory_install_write16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0106a060, 0x0106a09f, 0, 0, umk3_palette_hack_w);
471	471	}
472	472
r2864	r2865
479	479	init_wunit_generic();
480	480
481	481	/* serial prefixes 438, 528 */
482		midway_serial_pic_init(528);
	482	midway_serial_pic_init(machine, 528);
483	483	}
484	484
485	485
r2864	r2865
491	491	init_wunit_generic();
492	492
493	493	/* serial prefixes 459, 470, 528 */
494		midway_serial_pic_init(528);
	494	midway_serial_pic_init(machine, 528);
495	495	}
496	496
497	497
r2864	r2865
555	555	memory_install_write16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x01800000, 0x0180000f, 0, 0, wwfmania_io_0_w);
556	556
557	557	/* serial prefixes 430, 528 */
558		midway_serial_pic_init(528);
	558	midway_serial_pic_init(machine, 528);
559	559	}
560	560
561	561
r2864	r2865
567	567	init_wunit_generic();
568	568
569	569	/* serial prefixes 465, 528 */
570		midway_serial_pic_init(528);
	570	midway_serial_pic_init(machine, 528);
571	571	}
572	572
573	573
r2864	r2865
600	600	dcs_init();
601	601
602	602	/* serial prefixes 419, 420 */
603		midway_serial_pic_init(419);
	603	midway_serial_pic_init(machine, 419);
604	604	}
605	605
606	606

src/mame/machine/namco50.c
r2864	r2865
130	130	***************************************************************************/
131	131
132	132	#include "driver.h"
133		#include "deprecat.h"
134	133	#include "namco50.h"
135	134	#include "cpu/mb88xx/mb88xx.h"
136	135
r2864	r2865
258	257	cpunum_set_input_line(machine, param, 0, CLEAR_LINE);
259	258	}
260	259
261		static void namco_50xx_irq_set(int cpunum)
	260	static void namco_50xx_irq_set(running_machine *machine, int cpunum)
262	261	{
263		cpunum_set_input_line(Machine, cpunum, 0, ASSERT_LINE);
	262	cpunum_set_input_line(machine, cpunum, 0, ASSERT_LINE);
264	263
265	264	// The execution time of one instruction is ~4us, so we must make sure to
266	265	// give the cpu time to poll the /IRQ input before we clear it.
r2864	r2865
270	269	timer_set(ATTOTIME_IN_USEC(21), NULL, cpunum, namco_50xx_irq_clear);
271	270	}
272	271
273		void namco_50xx_write(UINT8 data)
	272	void namco_50xx_write(running_machine *machine, UINT8 data)
274	273	{
275		int cpunum = mame_find_cpu_index(Machine, CPUTAG_50XX);
	274	int cpunum = mame_find_cpu_index(machine, CPUTAG_50XX);
276	275
277	276	if (cpunum == -1)
278	277	return;
279	278
280	279	timer_call_after_resynch(NULL, data, namco_50xx_latch_callback);
281	280
282		namco_50xx_irq_set(cpunum);
	281	namco_50xx_irq_set(machine, cpunum);
283	282	}
284	283
285		void namco_50xx_2_write(UINT8 data)
	284	void namco_50xx_2_write(running_machine *machine, UINT8 data)
286	285	{
287		int cpunum = mame_find_cpu_index(Machine, CPUTAG_50XX_2);
	286	int cpunum = mame_find_cpu_index(machine, CPUTAG_50XX_2);
288	287
289	288	if (cpunum == -1)
290	289	return;
291	290
292	291	timer_call_after_resynch(NULL, data, namco_50xx_2_latch_callback);
293	292
294		namco_50xx_irq_set(cpunum);
	293	namco_50xx_irq_set(machine, cpunum);
295	294	}
296	295
297	296
298		void namco_50xx_read_request(void)
	297	void namco_50xx_read_request(running_machine *machine)
299	298	{
300		int cpunum = mame_find_cpu_index(Machine, CPUTAG_50XX);
	299	int cpunum = mame_find_cpu_index(machine, CPUTAG_50XX);
301	300
302	301	if (cpunum == -1)
303	302	return;
304	303
305	304	timer_call_after_resynch(NULL, 0, namco_50xx_readrequest_callback);
306	305
307		namco_50xx_irq_set(cpunum);
	306	namco_50xx_irq_set(machine, cpunum);
308	307	}
309	308
310		void namco_50xx_2_read_request(void)
	309	void namco_50xx_2_read_request(running_machine *machine)
311	310	{
312		int cpunum = mame_find_cpu_index(Machine, CPUTAG_50XX_2);
	311	int cpunum = mame_find_cpu_index(machine, CPUTAG_50XX_2);
313	312
314	313	if (cpunum == -1)
315	314	return;
316	315
317	316	timer_call_after_resynch(NULL, 0, namco_50xx_2_readrequest_callback);
318	317
319		namco_50xx_irq_set(cpunum);
	318	namco_50xx_irq_set(machine, cpunum);
320	319	}
321	320
322	321
323		UINT8 namco_50xx_read(void)
	322	UINT8 namco_50xx_read(running_machine *machine)
324	323	{
325	324	UINT8 res = portO[0];
326	325
327		namco_50xx_read_request();
	326	namco_50xx_read_request(machine);
328	327
329	328	return res;
330	329	}
331	330
332		UINT8 namco_50xx_2_read(void)
	331	UINT8 namco_50xx_2_read(running_machine *machine)
333	332	{
334	333	UINT8 res = portO[1];
335	334
336		namco_50xx_2_read_request();
	335	namco_50xx_2_read_request(machine);
337	336
338	337	return res;
339	338	}

src/mame/machine/namco50.h
r2864	r2865
12	12	ADDRESS_MAP_EXTERN( namco_50xx_2_map_data, 8 );
13	13	ADDRESS_MAP_EXTERN( namco_50xx_2_map_io, 8 );
14	14
15		UINT8 namco_50xx_read(void);
16		void namco_50xx_read_request(void);
17		void namco_50xx_write(UINT8 data);
	15	UINT8 namco_50xx_read(running_machine *machine);
	16	void namco_50xx_read_request(running_machine *machine);
	17	void namco_50xx_write(running_machine *machine, UINT8 data);
18	18
19		UINT8 namco_50xx_2_read(void);
20		void namco_50xx_2_read_request(void);
21		void namco_50xx_2_write(UINT8 data);
	19	UINT8 namco_50xx_2_read(running_machine *machine);
	20	void namco_50xx_2_read_request(running_machine *machine);
	21	void namco_50xx_2_write(running_machine *machine, UINT8 data);
22	22
23	23	#endif /* NAMCO54_H */

src/mame/machine/gaelco2.c
r2864	r2865
194	194	/* bit 6 is EEPROM data (DOUT) */
195	195	/* bit 7 is EEPROM ready */
196	196	/* bits 0-5, COINSW, STARTSW & Service */
197		return (1 << 7) \| (eeprom_read_bit() << 6) \| (input_port_read~~_indexed~~(machine, 2) & 0x3f);
	197	return (1 << 7) \| (eeprom_read_bit() << 6) \| (input_port_read(machine, "COIN") & 0x3f);
198	198	}
199	199
200	200	WRITE16_HANDLER( gaelco2_eeprom_cs_w )

src/mame/machine/decoprot.c
r2864	r2865
128	128	{
129	129	switch (offset<<1) {
130	130	case 0x110: /* Player input */
131		return input_port_read~~_indexed~~(machine, 0);
	131	return input_port_read(machine, "IN0");
132	132
133	133	case 0x36c: /* Coins */
134	134	case 0x334: /* Probably also, c6, 2c0, 2e0, 4b2, 46a, 4da, rohga is 44c */
135		return input_port_read~~_indexed~~(machine, 1);
	135	return input_port_read(machine, "IN1");
136	136	case 0x0dc:
137		return input_port_read~~_indexed~~(machine, 1)<<4;
	137	return input_port_read(machine, "IN1")<<4;
138	138
139	139	case 0x494: /* Dips */
140		return input_port_read~~_indexed~~(machine, 2);
	140	return input_port_read(machine, "DSW1_2");
141	141
142	142	case 0x244:
143	143	return deco16_prot_ram[0];
r2864	r2865
360	360
361	361	/* Player 1 & 2 controls, read in IRQ then written back to protection device */
362	362	case 0x50: /* written to 9e byte */
363		return input_port_read~~_indexed~~(machine, 0);
	363	return input_port_read(machine, "IN0");
364	364	case 0x6f8: /* written to 76 byte */
365		return (input_port_read~~_indexed~~(machine, 0)>>8)\|(input_port_read~~_indexed~~(machine, 0)<<8); /* byte swap IN0 */
	365	return (input_port_read(machine, "IN0")>>8)\|(input_port_read(machine, "IN0")<<8); /* byte swap IN0 */
366	366
367	367	case 0x5c: /* After coin insert, high 0x8000 bit set starts game */
368	368	return deco16_prot_ram[0x3b];
r2864	r2865
372	372	return ((deco16_prot_ram[0x9e/2]&0xff00)>>8) \| ((deco16_prot_ram[0x9e/2]&0x00ff)<<8);
373	373
374	374	case 0xac: /* Dip switches */
375		return input_port_read~~_indexed~~(machine, 2);
	375	return input_port_read(machine, "DSW");
376	376	case 0xc2:
377		return input_port_read~~_indexed~~(machine, 2) ^ deco16_prot_ram[0x2c/2];
	377	return input_port_read(machine, "DSW") ^ deco16_prot_ram[0x2c/2];
378	378
379	379	case 0x5d4: /* The state of the dips last frame */
380	380	return deco16_prot_ram[0x34/2];
r2864	r2865
386	386	return (((deco16_prot_ram[0]&0xfff0)>>0) \| ((deco16_prot_ram[0]&0x000c)>>2) \| ((deco16_prot_ram[0]&0x0003)<<2)) & (~deco16_prot_ram[0x36/2]);
387	387
388	388	case 0x76a: /* Coins */
389		return input_port_read~~_indexed~~(machine, 1);
	389	return input_port_read(machine, "IN1");
390	390
391	391	case 0x284: /* Bit shifting with inverted mask register */
392	392	return (((deco16_prot_ram[0x40/2]&0xfff0)>>0) \| ((deco16_prot_ram[0x40/2]&0x0007)<<1) \| ((deco16_prot_ram[0x40/2]&0x0008)>>3)) & (~deco16_prot_ram[0x36/2]);
r2864	r2865
400	400	return (((deco16_prot_ram[0x6a/2]&0x00f0)<<4) \| ((deco16_prot_ram[0x6a/2]&0x0f00)<<4) \| ((deco16_prot_ram[0x6a/2]&0x0007)<<5) \| ((deco16_prot_ram[0x6a/2]&0x0008)<<1)) & (~deco16_prot_ram[0x36/2]);
401	401
402	402	case 0x7d6: /* XOR IN0 */
403		return input_port_read~~_indexed~~(machine, 0) ^ deco16_prot_ram[0x2c/2];
	403	return input_port_read(machine, "IN0") ^ deco16_prot_ram[0x2c/2];
404	404	case 0x4b4:
405	405	return ((deco16_prot_ram[0x32/2]&0x00f0)<<8) \| ((deco16_prot_ram[0x32/2]&0x000e)<<7) \| ((deco16_prot_ram[0x32/2]&0x0001)<<11);
406	406	}
r2864	r2865
461	461
462	462	switch (offset*2) {
463	463	case 0xac: /* Dip switches */
464		return input_port_read~~_indexed~~(machine, 2);
	464	return input_port_read(machine, "DSW");
465	465	case 0xc2: /* Dip switches */
466		return input_port_read~~_indexed~~(machine, 2) ^ deco16_prot_ram[0x2c/2];
	466	return input_port_read(machine, "DSW") ^ deco16_prot_ram[0x2c/2];
467	467	case 0x46: /* Coins */
468		return input_port_read~~_indexed~~(machine, 1) ^ deco16_prot_ram[0x2c/2];
	468	return input_port_read(machine, "IN1") ^ deco16_prot_ram[0x2c/2];
469	469	case 0x50: /* Player 1 & 2 input ports */
470		return input_port_read~~_indexed~~(machine, 0);
	470	return input_port_read(machine, "IN0");
471	471	case 0x63c: /* Player 1 & 2 input ports */
472		return input_port_read~~_indexed~~(machine, 0) ^ deco16_prot_ram[0x2c/2];
	472	return input_port_read(machine, "IN0") ^ deco16_prot_ram[0x2c/2];
473	473
474	474	case 0x5f4:
475	475	return deco16_prot_ram[0x18/2];
r2864	r2865
644	644	return deco16_prot_ram[15];
645	645
646	646	case 0x36: /* Dip switches */
647		return input_port_read~~_indexed~~(machine, 2);
	647	return input_port_read(machine, "DSW");
648	648
649	649	case 0x1c8: /* Coins */
650		return input_port_read~~_indexed~~(machine, 1);
	650	return input_port_read(machine, "IN1");
651	651
652	652	case 0x22c: /* Player 1 & 2 input ports */
653		return input_port_read~~_indexed~~(machine, 0);
	653	return input_port_read(machine, "IN0");
654	654	}
655	655
656	656	logerror("Protection PC %06x: warning - read unmapped memory address %04x\n",activecpu_get_pc(),offset);
r2864	r2865
740	740	return ((deco16_prot_ram[0x78e>>1]>>4)&0xff00) \| (deco16_prot_ram[0x78e>>1]&0x000f) \| ((deco16_prot_ram[0x78e>>1]<<8)&0xf000);
741	741
742	742	case 0x00c >> 1: /* Player 1 & Player 2 joysticks & fire buttons */
743		return (input_port_read~~_indexed~~(machine, 0) + (input_port_read~~_indexed~~(machine, 1) << 8));
	743	return (input_port_read(machine, "P1") + (input_port_read(machine, "P2") << 8));
744	744	case 0x778 >> 1: /* Credits */
745		return input_port_read~~_indexed~~(machine, 2);
	745	return input_port_read(machine, "IN0");
746	746	case 0x382 >> 1: /* DIPS */
747		return (input_port_read~~_indexed~~(machine, 3) + (input_port_read~~_indexed~~(machine, 4) << 8));
	747	return (input_port_read(machine, "DSWA") + (input_port_read(machine, "DSWB") << 8));
748	748	}
749	749
750	750	if (activecpu_get_pc()!=0xc0ea)
751		logerror("CPU #0 PC %06x: warning - read unmapped control address %06x (ctrl %04x)\n",activecpu_get_pc(),offset<<1, input_port_read~~_indexed~~(machine, 0));
	751	logerror("CPU #0 PC %06x: warning - read unmapped control address %06x (ctrl %04x)\n", activecpu_get_pc(), offset<<1, input_port_read(machine, "P1"));
752	752
753	753	return 0;
754	754	}
r2864	r2865
857	857
858	858	switch (offset) {
859	859	case 0x88/2: /* Player 1 & 2 input ports */
860		return input_port_read~~_indexed~~(machine, 0);
	860	return input_port_read(machine, "IN0");
861	861	case 0x36c/2:
862		return input_port_read~~_indexed~~(machine, 1);
	862	return input_port_read(machine, "IN1");
863	863	case 0x44c/2:
864
865		return ((input_port_read_indexed(machine, 1)&0x7)<<13)\|((input_port_read_indexed(machine, 1)&0x8)<<9);
	864	return ((input_port_read(machine, "IN1") & 0x7)<<13)\|((input_port_read(machine, "IN1") & 0x8)<<9);
866	865	case 0x292/2: /* Dips */
867		return input_port_read~~_indexed~~(machine, 2);
	866	return input_port_read(machine, "DSW1_2");
868	867
869	868	case 0x44/2:
870	869	return ((((DECO_PORT(0x2c)&0x000f)<<12)) ^ deco16_xor) & (~deco16_mask);
r2864	r2865
1241	1240	switch (offset)
1242	1241	{
1243	1242	case 0x582: /* Player 1 & Player 2 */
1244		return input_port_read~~_indexed~~(machine, 0);
	1243	return input_port_read(machine, "IN0");
1245	1244	case 0x04c: /* Coins/VBL */
1246		return input_port_read~~_indexed~~(machine, 1);
	1245	return input_port_read(machine, "IN1");
1247	1246	case 0x672: /* Dip switches */
1248		return input_port_read~~_indexed~~(machine, 2);
	1247	return input_port_read(machine, "DSW1_2");
1249	1248
1250	1249	case 0x13a:
1251	1250	return ((DECO_PORT(0x190)&0x00f0)<<8) \| ((DECO_PORT(0x190)&0x0003)<<10) \| ((DECO_PORT(0x190)&0x000c)<<6);
r2864	r2865
1303	1302
1304	1303	/*********************************************************************************/
1305	1304
1306		// case 0x582: return input_port_read_indexed(machine, 0); /* IN0 */
1307		// case 0x672: return input_port_read_indexed(machine, 1); /* IN1 */
	1305	// case 0x582: return input_port_read(machine, "IN0"); /* IN0 */
	1306	// case 0x672: return input_port_read(machine, "IN1"); /* IN1 */
1308	1307	// case 0x04c: return eeprom_read_bit();
1309	1308
1310	1309	case 0x468:
r2864	r2865
1652	1651	/* Special case inputs, because this is the only game with an eprom */
1653	1652	switch (addr)
1654	1653	{
1655		case 0x582: return (input_port_read_indexed(machine, 0)<<16) \| 0xffff; /* IN0 */
1656		case 0x672: return (input_port_read_indexed(machine, 1)<<16) \| 0xffff; /* IN1 */
	1654	case 0x582: return (input_port_read(machine, "IN0")<<16) \| 0xffff; /* IN0 */
	1655	case 0x672: return (input_port_read(machine, "IN1")<<16) \| 0xffff; /* IN1 */
1657	1656	case 0x04c: return (eeprom_read_bit()<<16) \| 0xffff;
1658	1657	}
1659	1658
r2864	r2865
1728	1727	{
1729	1728	switch (offset * 2)
1730	1729	{
1731		case 0x298: return input_port_read_indexed(machine,0);
1732		case 0x342: return input_port_read_indexed(machine,1);
1733		case 0x506: return input_port_read_indexed(machine,2);
	1730	case 0x298: return input_port_read(machine, "IN0");
	1731	case 0x342: return input_port_read(machine, "IN1");
	1732	case 0x506: return input_port_read(machine, "DSW");
1734	1733	}
1735	1734
1736		logerror("Protection PC %06x: warning - read unmapped memory address %04x\n",activecpu_get_pc(),offset<<1);
	1735	logerror("Protection PC %06x: warning - read unmapped memory address %04x\n", activecpu_get_pc(), offset<<1);
1737	1736
1738	1737	return 0;
1739	1738	}
r2864	r2865
1755	1754	const UINT16* prot_ram=deco16_prot_ram;
1756	1755	switch (offset * 2)
1757	1756	{
1758		case 0x5b2: return input_port_read_indexed(machine,0);
1759		case 0x44c: return input_port_read_indexed(machine,1);
1760		case 0x042: return input_port_read_indexed(machine,2);
	1757	case 0x5b2: return input_port_read(machine, "IN0");
	1758	case 0x44c: return input_port_read(machine, "DSW");
	1759	case 0x042: return input_port_read(machine, "IN1");
1761	1760
1762	1761	case 0x510: return DECO_PORT(0);
1763	1762	case 0x51a: return DECO_PORT(2);
1764	1763	}
1765	1764
1766		logerror("Protection PC %06x: warning - read unmapped memory address %04x\n",activecpu_get_pc(),offset<<1);
	1765	logerror("Protection PC %06x: warning - read unmapped memory address %04x\n", activecpu_get_pc(), offset<<1);
1767	1766
1768	1767	return 0;
1769	1768	}

src/mame/machine/s24fd.c
r2864	r2865
152	152	}
153	153
154	154	/* startup function, to be called from DRIVER_INIT (once on startup) */
155		void s24_fd1094_driver_init(void)
	155	void s24_fd1094_driver_init(running_machine *machine)
156	156	{
157	157	int i;
158	158
r2864	r2865
179	179
180	180	state_save_register_global(fd1094_selected_state);
181	181	state_save_register_global(fd1094_state);
182		state_save_register_postload(Machine, s24_fd1094_postload, NULL);
	182	state_save_register_postload(machine, s24_fd1094_postload, NULL);
183	183	}

src/mame/machine/galaxold.c
r2864	r2865
15	15	static int irq_line;
16	16	static emu_timer *int_timer;
17	17
18		static UINT8 kingball_speech_dip;
19		static UINT8 kingball_sound;
20
21	18	static UINT8 _4in1_bank;
22		static UINT8 gmgalax_selected_game;
23	19
24
25	20	static void galaxold_7474_9M_2_callback(void)
26	21	{
27	22	/* Q bar clocks the other flip-flop,
r2864	r2865
220	215	}
221	216
222	217
223
224		/* Hack? If $b003 is high, we'll check our "fake" speech dipswitch (marked as SLAM) */
225		static READ8_HANDLER( kingball_IN0_r )
226		{
227		if (kingball_speech_dip)
228		return (input_port_read_indexed(machine, 0) & ~0x40) \| ((input_port_read_indexed(machine, 3) & 0x01) << 6);
229		else
230		return input_port_read_indexed(machine, 0);
231		}
232
233		static READ8_HANDLER( kingball_IN1_r )
234		{
235		/* bit 5 is the NOISE line from the sound circuit. The code just verifies
236		that it's working, doesn't actually use return value, so we can just use
237		rand() */
238
239		return (input_port_read_indexed(machine, 1) & ~0x20) \| (mame_rand(machine) & 0x20);
240		}
241
242		WRITE8_HANDLER( kingball_speech_dip_w )
243		{
244		kingball_speech_dip = data;
245		}
246
247		WRITE8_HANDLER( kingball_sound1_w )
248		{
249		kingball_sound = (kingball_sound & ~0x01) \| data;
250		}
251
252		WRITE8_HANDLER( kingball_sound2_w )
253		{
254		kingball_sound = (kingball_sound & ~0x02) \| (data << 1);
255		soundlatch_w (machine, 0, kingball_sound \| 0xf0);
256		}
257
258
259	218	READ8_HANDLER( scramblb_protection_1_r )
260	219	{
261	220	switch (activecpu_get_pc())
r2864	r2865
280	239	}
281	240
282	241
283		static READ8_HANDLER( azurian_IN1_r )
284		{
285		return (input_port_read_indexed(machine, 1) & ~0x40) \| ((input_port_read_indexed(machine, 3) & 0x01) << 6);
286		}
287
288		static READ8_HANDLER( azurian_IN2_r )
289		{
290		return (input_port_read_indexed(machine, 2) & ~0x04) \| ((input_port_read_indexed(machine, 3) & 0x02) << 1);
291		}
292
293
294	242	WRITE8_HANDLER( _4in1_bank_w )
295	243	{
296	244	_4in1_bank = data & 0x03;
r2864	r2865
300	248
301	249	READ8_HANDLER( _4in1_input_port_1_r )
302	250	{
303		return (input_port_read_indexed(machine, 1) & ~0xc0) \| (input_port_read_indexed(machine, 3+_4in1_bank) & 0xc0);
	251	static const char *portnames[] = { "FAKE1", "FAKE2", "FAKE3", "FAKE4" };
	252
	253	return (input_port_read(machine, "IN1") & ~0xc0) \| (input_port_read(machine, portnames[_4in1_bank]) & 0xc0);
304	254	}
305	255
306	256	READ8_HANDLER( _4in1_input_port_2_r )
307	257	{
308		return (input_port_read_indexed(machine, 2) & 0x04) \| (input_port_read_indexed(machine, 3+_4in1_bank) & ~0xc4);
309		}
	258	static const char *portnames[] = { "FAKE1", "FAKE2", "FAKE3", "FAKE4" };
310	259
311
312		static void gmgalax_select_game(int game)
313		{
314		gmgalax_selected_game = game;
315
316		memory_set_bank(1, game);
317
318		galaxold_gfxbank_w(Machine, 0, gmgalax_selected_game);
	260	return (input_port_read(machine, "DSW0") & 0x04) \| (input_port_read(machine, portnames[_4in1_bank]) & ~0xc4);
319	261	}
320	262
321		READ8_HANDLER( gmgalax_input_port_0_r )
322		{
323		return input_port_read_indexed(machine, gmgalax_selected_game ? 3 : 0);
324		}
325	263
326		READ8_HANDLER( gmgalax_input_port_1_r )
327		{
328		return input_port_read_indexed(machine, gmgalax_selected_game ? 4 : 1);
329		}
330
331		READ8_HANDLER( gmgalax_input_port_2_r )
332		{
333		return input_port_read_indexed(machine, gmgalax_selected_game ? 5 : 2);
334		}
335
336
337	264	DRIVER_INIT( pisces )
338	265	{
339	266	/* the coin lockout was replaced */
r2864	r2865
352	279	memory_install_read8_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x3035, 0x3035, 0, 0, dingo_3035_r);
353	280	}
354	281
355		DRIVER_INIT( kingball )
356		{
357		memory_install_read8_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0xa000, 0xa000, 0, 0, kingball_IN0_r);
358		memory_install_read8_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0xa800, 0xa800, 0, 0, kingball_IN1_r);
359	282
360		state_save_register_global(kingball_speech_dip);
361		state_save_register_global(kingball_sound);
362		}
363
364
365	283	static UINT8 decode_mooncrst(UINT8 data,offs_t addr)
366	284	{
367	285	UINT8 res;
r2864	r2865
473	391	}
474	392	}
475	393
476		DRIVER_INIT( azurian )
477		{
478		DRIVER_INIT_CALL(pisces);
479
480		memory_install_read8_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x6800, 0x6800, 0, 0, azurian_IN1_r);
481		memory_install_read8_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x7000, 0x7000, 0, 0, azurian_IN2_r);
482		}
483
484	394	DRIVER_INIT( 4in1 )
485	395	{
486	396	offs_t i, len = memory_region_length(REGION_CPU1);
r2864	r2865
508	418	/* Doesn't actually use the bank, but it mustn't have a coin lock! */
509	419	memory_install_write8_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x6002, 0x6002, 0, 0, galaxold_gfxbank_w);
510	420	}
511
512		DRIVER_INIT( gmgalax )
513		{
514		/* games are banked at 0x0000 - 0x3fff */
515		UINT8 *RAM=memory_region(REGION_CPU1);
516		memory_configure_bank(1, 0, 2, &RAM[0x10000], 0x4000);
517
518		state_save_register_global(gmgalax_selected_game);
519
520		gmgalax_select_game(input_port_read_indexed(machine, 6) & 0x01);
521		}
522
523		INTERRUPT_GEN( gmgalax_vh_interrupt )
524		{
525		// reset the cpu if the selected game changed
526		int new_game = input_port_read_indexed(machine, 6) & 0x01;
527
528		if (gmgalax_selected_game != new_game)
529		{
530		gmgalax_select_game(new_game);
531
532		/* Ghost Muncher never clears this */
533		galaxold_stars_enable_w(machine, 0, 0);
534
535		cpunum_set_input_line(machine, 0, INPUT_LINE_RESET, ASSERT_LINE);
536		}
537		}

src/mame/machine/harddriv.c
r2864	r2865
350	350	.....
351	351	0x8000 = SW1 #1
352	352	*/
353		int temp = input_port_read~~_indexed~~(machine, 0);
	353	int temp = input_port_read(machine, "IN0");
354	354	if (atarigen_get_hblank(machine->primary_screen)) temp ^= 0x0002;
355	355	temp ^= 0x0018; /* both EOCs always high for now */
356	356	return temp;
r2864	r2865
359	359
360	360	READ16_HANDLER( hdc68k_port1_r )
361	361	{
362		UINT16 result = input_port_read~~_indexed~~(machine, 1);
	362	UINT16 result = input_port_read(machine, "a80000");
363	363	UINT16 diff = result ^ hdc68k_last_port1;
364	364
365	365	/* if a new shifter position is selected, use it */
r2864	r2865
387	387
388	388	READ16_HANDLER( hda68k_port1_r )
389	389	{
390		UINT16 result = input_port_read~~_indexed~~(machine, 1);
	390	UINT16 result = input_port_read(machine, "a80000");
391	391
392	392	/* merge in the wheel edge latch bit */
393	393	if (hdc68k_wheel_edge)
r2864	r2865
400	400	READ16_HANDLER( hdc68k_wheel_r )
401	401	{
402	402	/* grab the new wheel value and upconvert to 12 bits */
403		UINT16 new_wheel = input_port_read~~_indexed~~(machine, 10) << 4;
	403	UINT16 new_wheel = input_port_read(machine, "12BADC0") << 4;
404	404
405	405	/* hack to display the wheel position */
406	406	if (input_code_pressed(KEYCODE_LSHIFT))
r2864	r2865
445	445
446	446	WRITE16_HANDLER( hd68k_adc_control_w )
447	447	{
	448	static const char *adc8names[] = { "8BADC0", "8BADC1", "8BADC2", "8BADC3", "8BADC4", "8BADC5", "8BADC6", "8BADC7" };
	449	static const char *adc12names[] = { "12BADC0", "12BADC1", "12BADC2", "12BADC3" };
	450
448	451	COMBINE_DATA(&adc_control);
449	452
450	453	/* handle a write to the 8-bit ADC address select */
451	454	if (adc_control & 0x08)
452	455	{
453	456	adc8_select = adc_control & 0x07;
454		adc8_data = input_port_read~~_indexed~~(machine, ~~2 +~~ adc8_select);
	457	adc8_data = input_port_read(machine, adc8names[adc8_select]);
455	458	}
456	459
457	460	/* handle a write to the 12-bit ADC address select */
458	461	if (adc_control & 0x40)
459	462	{
460	463	adc12_select = (adc_control >> 4) & 0x03;
461		adc12_data = input_port_read~~_indexed~~(machine, 1~~0 +~~ adc12_select) << 4;
	464	adc12_data = input_port_read(machine, adc12names[adc12_select]) << 4;
462	465	}
463	466
464	467	/* bit 7 selects which byte of the 12 bit data to read */
r2864	r2865
1470	1473	break;
1471	1474
1472	1475	case 4: /* ASIC65 reset */
1473		asic65_reset(!val);
	1476	asic65_reset(machine, !val);
1474	1477	break;
1475	1478
1476	1479	case 7: /* LED */
r2864	r2865
1613	1616	switch (offset & 7)
1614	1617	{
1615	1618	case 2: /* ASIC65 reset */
1616		asic65_reset(!val);
	1619	asic65_reset(machine, !val);
1617	1620	break;
1618	1621
1619	1622	default:

src/mame/machine/dec0.c
r2864	r2865
7	7	*******************************************************************************/
8	8
9	9	#include "driver.h"
10		#include "deprecat.h"
11	10	#include "dec0.h"
12	11	#include "cpu/h6280/h6280.h"
13	12
r2864	r2865
20	19	switch (offset<<1)
21	20	{
22	21	case 0: /* Player 1 & 2 joystick & buttons */
23		return (input_port_read~~_indexed~~(machine, 0) + (input_port_read~~_indexed~~(machine, 1) << 8));
	22	return (input_port_read(machine, "IN0") + (input_port_read(machine, "IN1") << 8));
24	23
25	24	case 2: /* Credits, start buttons */
26		return input_port_read~~_indexed~~(machine, 2);
	25	return input_port_read(machine, "IN2");
27	26
28	27	case 4: /* Byte 4: Dipswitch bank 2, Byte 5: Dipswitch Bank 1 */
29		return (input_port_read~~_indexed~~(machine, 3) + (input_port_read~~_indexed~~(machine, 4) << 8));
	28	return (input_port_read(machine, "DSW0") + (input_port_read(machine, "DSW1") << 8));
30	29
31	30	case 8: /* Intel 8751 mc, Bad Dudes & Heavy Barrel only */
32		//logerror("CPU #0 PC %06x: warning - read unmapped memory address %06x\n",activecpu_get_pc(),0x30c000+offset);
	31	//logerror("CPU #0 PC %06x: warning - read unmapped memory address %06x\n", activecpu_get_pc(), 0x30c000+offset);
33	32	return i8751_return;
34	33	}
35	34
36		logerror("CPU #0 PC %06x: warning - read unmapped memory address %06x\n",activecpu_get_pc(),0x30c000+offset);
	35	logerror("CPU #0 PC %06x: warning - read unmapped memory address %06x\n", activecpu_get_pc(), 0x30c000+offset);
37	36	return ~0;
38	37	}
39	38
r2864	r2865
44	43	switch (offset<<1)
45	44	{
46	45	case 0: /* Player 1 rotary */
47		return ~(1 << (input_port_read~~_indexed~~(machine, 5) * 12 / 256));
	46	return ~(1 << (input_port_read(machine, "AN0") * 12 / 256));
48	47
49	48	case 8: /* Player 2 rotary */
50		return ~(1 << (input_port_read~~_indexed~~(machine, 6) * 12 / 256));
	49	return ~(1 << (input_port_read(machine, "AN1") * 12 / 256));
51	50
52	51	default:
53		logerror("Unknown rotary read at 300000 %02x\n",offset);
	52	logerror("Unknown rotary read at 300000 %02x\n", offset);
54	53	}
55	54
56	55	return 0;
r2864	r2865
63	62	switch (offset<<1)
64	63	{
65	64	case 0: /* Player 1 Joystick + start, Player 2 Joystick + start */
66		return (input_port_read~~_indexed~~(machine, 0) + (input_port_read~~_indexed~~(machine, 1) << 8));
	65	return (input_port_read(machine, "IN0") + (input_port_read(machine, "IN1") << 8));
67	66
68	67	case 2: /* Dipswitches */
69		return (input_port_read~~_indexed~~(machine, 3) + (input_port_read~~_indexed~~(machine, 4) << 8));
	68	return (input_port_read(machine, "DSW0") + (input_port_read(machine, "DSW1") << 8));
70	69
71	70	case 4: /* Player 1 rotary */
72		return ~(1 << (input_port_read~~_indexed~~(machine, 5) * 12 / 256));
	71	return ~(1 << (input_port_read(machine, "AN0") * 12 / 256));
73	72
74	73	case 6: /* Player 2 rotary */
75		return ~(1 << (input_port_read~~_indexed~~(machine, 6) * 12 / 256));
	74	return ~(1 << (input_port_read(machine, "AN1") * 12 / 256));
76	75
77	76	case 8: /* Credits, start buttons */
78		return input_port_read~~_indexed~~(machine, 2);
	77	return input_port_read(machine, "IN2");
79	78
80	79	case 12:
81	80	return 0; /* ?? watchdog ?? */
82	81	}
83	82
84		logerror("PC %06x unknown control read at %02x\n",activecpu_get_pc(),0x180000+offset);
	83	logerror("PC %06x unknown control read at %02x\n", activecpu_get_pc(), 0x180000+offset);
85	84	return ~0;
86	85	}
87	86
r2864	r2865
92	91	switch (offset<<1)
93	92	{
94	93	case 0: /* Dip Switches */
95		return (input_port_read~~_indexed~~(machine, 3) + (input_port_read~~_indexed~~(machine, 4) << 8));
	94	return (input_port_read(machine, "DSW0") + (input_port_read(machine, "DSW1") << 8));
96	95
97	96	case 2: /* Player 1 & Player 2 joysticks & fire buttons */
98		return (input_port_read~~_indexed~~(machine, 0) + (input_port_read~~_indexed~~(machine, 1) << 8));
	97	return (input_port_read(machine, "IN0") + (input_port_read(machine, "IN1") << 8));
99	98
100	99	case 4: /* Credits */
101		return input_port_read~~_indexed~~(machine, 2);
	100	return input_port_read(machine, "IN2");
102	101	}
103	102
104		logerror("Unknown control read at 30c000 %d\n",offset);
	103	logerror("Unknown control read at 30c000 %d\n", offset);
105	104	return ~0;
106	105	}
107	106
r2864	r2865
115	114	case 6: return 0x2;
116	115	}
117	116
118		logerror("%04x, Unknown protection read at 30c000 %d\n",activecpu_get_pc(),offset);
	117	logerror("%04x, Unknown protection read at 30c000 %d\n", activecpu_get_pc(), offset);
119	118	return 0;
120	119	}
121	120
r2864	r2865
471	470	}
472	471	#endif
473	472
474		void dec0_i8751_write(int data)
	473	void dec0_i8751_write(running_machine *machine, int data)
475	474	{
476	475	/* Writes to this address cause an IRQ to the i8751 microcontroller */
477	476	if (GAME==1) hbarrel_i8751_write(data);
478	477	if (GAME==2) baddudes_i8751_write(data);
479	478	if (GAME==3) birdtry_i8751_write(data);
480	479
481		cpunum_set_input_line(Machine, 0,5,HOLD_LINE);
	480	cpunum_set_input_line(machine, 0,5,HOLD_LINE);
482	481
483	482	/* Simulate the processing time of the i8751, time value is guessed
484	483	if (i8751_timer)

src/mame/machine/lsasquad.c
r2864	r2865
181	181
182	182	READ8_HANDLER( lsasquad_mcu_status_r )
183	183	{
184		int res = input_port_read~~_indexed~~(machine, 3);
	184	int res = input_port_read(machine, "MCU?");
185	185
186	186	/* bit 0 = when 1, mcu is ready to receive data from main cpu */
187	187	/* bit 1 = when 0, mcu has sent data to the main cpu */

src/mame/machine/kaneko16.c
r2864	r2865
342	342
343	343	// execute the command:
344	344
345		kaneko16_mcu_ram[param1 / 2] = ~input_port_read~~_indexed~~(machine, 4); // DSW
	345	kaneko16_mcu_ram[param1 / 2] = ~input_port_read(machine, "DSW1"); // DSW
346	346	kaneko16_mcu_ram[param2 / 2] = 0xffff; // ? -1 / anything else
347	347
348	348	calc3_mcu_command_offset = param3 / 2; // where next command will be written?
r2864	r2865
616	616
617	617	case 0x03: // DSW
618	618	{
619		kaneko16_mcu_ram[mcu_offset] = input_port_read~~_indexed~~(machine, 4);
	619	kaneko16_mcu_ram[mcu_offset] = input_port_read(machine, "DSW1");
620	620	logerror("PC=%06X : MCU executed command: %04X %04X (read DSW)\n", activecpu_get_pc(), mcu_command, mcu_offset*2);
621	621	}
622	622	break;
r2864	r2865
743	743
744	744	case 0x03: // DSW
745	745	{
746		kaneko16_mcu_ram[mcu_offset] = input_port_read~~_indexed~~(machine, 4);
	746	kaneko16_mcu_ram[mcu_offset] = input_port_read(machine, "DSW1");
747	747	logerror("PC=%06X : MCU executed command: %04X %04X (read DSW)\n", activecpu_get_pc(), mcu_command, mcu_offset*2);
748	748	}
749	749	break;
r2864	r2865
851	851
852	852	case 0x03: // DSW
853	853	{
854		kaneko16_mcu_ram[mcu_offset] = input_port_read~~_indexed~~(machine, 4);
	854	kaneko16_mcu_ram[mcu_offset] = input_port_read(machine, "DSW1");
855	855	}
856	856	break;
857	857

src/mame/machine/cps2crpt.c
r2864	r2865
111	111	*******************************************************************************/
112	112
113	113	#include "driver.h"
114		#include "deprecat.h"
115	114	#include "cpu/m68000/m68kmame.h"
116	115	#include "ui.h"
117	116	#include "includes/cps1.h"
r2864	r2865
631	630
632	631
633	632
634		static void cps2_decrypt(const UINT32 *master_key, UINT32 upper_limit)
	633	static void cps2_decrypt(running_machine machine, const UINT32 master_key, UINT32 upper_limit)
635	634	{
636	635	UINT16 rom = (UINT16 )memory_region(REGION_CPU1);
637	636	int length = memory_region_length(REGION_CPU1);
r2864	r2865
674	673	{
675	674	char loadingMessage[256]; // for displaying with UI
676	675	sprintf(loadingMessage, "Decrypting %d%%", i*100/0x10000);
677		ui_set_startup_text(Machine, loadingMessage,FALSE);
	676	ui_set_startup_text(machine, loadingMessage,FALSE);
678	677	}
679	678
680	679
r2864	r2865
971	970	if (strcmp(k->name, gamename) == 0)
972	971	{
973	972	// we have a proper key so use it to decrypt
974		cps2_decrypt(k->keys, k->upper_limit ? k->upper_limit : 0x400000);
	973	cps2_decrypt(machine, k->keys, k->upper_limit ? k->upper_limit : 0x400000);
975	974
976	975	break;
977	976	}

src/mame/machine/slapstic.c
r2864	r2865
179	179	*************************************************************************/
180	180
181	181	#include "driver.h"
182		#include "deprecat.h"
183	182	#include "slapstic.h"
184	183	#include "cpu/m68000/m68000.h"
185	184
r2864	r2865
810	809	*
811	810	*************************************/
812	811
813		void slapstic_init(int chip)
	812	void slapstic_init(running_machine *machine, int chip)
814	813	{
815	814	/* only a small number of chips are known to exist */
816	815	if (chip < 101 \|\| chip > 118)
r2864	r2865
825	824	slapstic_reset();
826	825
827	826	/* see if we're 68k or 6502/6809 based */
828		access_68k = (Machine->config->cpu[0].type == CPU_M68000 \|\|
829		Machine->config->cpu[0].type == CPU_M68010);
	827	access_68k = (machine->config->cpu[0].type == CPU_M68000 \|\|
	828	machine->config->cpu[0].type == CPU_M68010);
830	829
831	830	/* save state */
832	831	state_save_register_item("slapstic", 0, state);

src/mame/mamedriv.c
r2864	r2865
396	396	DRIVER( legion ) /* (c) 1986 */
397	397	DRIVER( legiono ) /* (c) 1986 */
398	398	DRIVER( terraf ) /* (c) 1987 */
	399	DRIVER( terrafb ) /* (c) 1987 */
399	400	DRIVER( terrafa ) /* (c) 1987 */
400	401	DRIVER( terrafu ) /* (c) 1987 Nichibutsu USA */
401	402	DRIVER( kodure ) /* (c) 1987 (Japan) */
r2864	r2865
3419	3420	DRIVER( tetris3 ) /* (c) 1988 (FD1094, decrypted) S16A */
3420	3421	DRIVER( timesca1 ) /* (c) 1987 (FD1089B, decrypted) */
3421	3422	DRIVER( wb31 ) /* (c) 1988 Sega / Westone (FD1094, decrypted) */
	3423	DRIVER( wb35 ) /* (c) 1988 Sega / Westone (FD1089A, decrypted) */
3422	3424	DRIVER( pshot16a ) /* (c) 1988 */
3423	3425
3424	3426	/* System 16B */
r2864	r2865
3553	3555	DRIVER( toutrun ) /* (c) 1987 (FD1094, decrypted) */
3554	3556	DRIVER( toutrun2 ) /* (c) 1987 (FD1094, decrypted) */
3555	3557	DRIVER( toutrun1 ) /* (c) 1987 (protected) */
	3558	DRIVER( toutrunu ) /* (c) 1987 (FD1094, decrypted) */
3556	3559	DRIVER( shangon ) /* (c) 1987 (protected) */
3557	3560	DRIVER( shangon3 ) /* (c) 1987 (FD1089B, decrypted) */
3558	3561	DRIVER( shangon2 ) /* (c) 1987 (FD1089B, decrypted) */
r2864	r2865
5848	5851	DRIVER( ctribe ) /* TA-0028 (c) 1990 (US) */
5849	5852	DRIVER( ctribe1 ) /* TA-0028 (c) 1990 (US) - Set 1? */
5850	5853	DRIVER( ctribeb ) /* bootleg */
	5854	DRIVER( ctribb2 ) /* bootleg */
5851	5855	DRIVER( blockout ) /* TA-0029 (c) 1989 + California Dreams */
5852	5856	DRIVER( blckout2 ) /* TA-0029 (c) 1989 + California Dreams */
5853	5857	DRIVER( blckoutj ) /* TA-0029 (c) 1989 + California Dreams (Japan) */
r2864	r2865
7488	7492	DRIVER( crysbios )
7489	7493	DRIVER( crysking ) /* 2001 Brezzasoft. Crystal of the kings */
7490	7494	DRIVER( evosocc ) /* 2001 Evoga. Evolution Soccer */
7491		DRIVER( topbladv )
	7495	DRIVER( topbladv ) /* 2002 Sonokong. Top Blade V */
7492	7496	DRIVER( officeye )
7493	7497
7494	7498	/* Bell Fruit Cobra Hardware */
r2864	r2865
7789	7793	DRIVER( lottof2 ) /* (c) 1993 HAR */
7790	7794	DRIVER( fredmem ) /* (c) 1994 Coastal Amusements */
7791	7795	DRIVER( fredmeus ) /* (c) 1994 Coastal Amusements */
7792		DRIVER( fredmeuk ) /* (c) 1994 Coastal Amusements */
	7796	DRIVER( fredmeuk ) /* (c) 1994 Coastal Amusements */
7793	7797	DRIVER( fredmemj ) /* (c) 1994 Coastal Amusements */
7794		DRIVER( fredmemc ) /* (c) 1994 Coastal Amusements */
7795		DRIVER( fredmesp ) /* (c) 1994 Coastal Amusements */
7796		DRIVER( cecmatch ) /* (c) 1993 Coastal Amusements */
	7798	DRIVER( fredmemc ) /* (c) 1994 Coastal Amusements */
	7799	DRIVER( fredmesp ) /* (c) 1994 Coastal Amusements */
	7800	DRIVER( cecmatch ) /* (c) 1993 Coastal Amusements */
7797	7801	DRIVER( f15se ) /* (c) 1991 Microprose */
7798	7802	DRIVER( f15se21 ) /* (c) 1991 Microprose */
7799	7803	DRIVER( botss ) /* (c) 1992 Microprose */
r2864	r2865
7853	7857	DRIVER( pntnpuzl ) /* Century? */
7854	7858	DRIVER( trucocl ) /* (c) 1991 Miky SRL */
7855	7859	DRIVER( ertictac ) /* (c) 1992 Sisteme */
7856		DRIVER( poizone ) /* (c) 1990 Sisteme */
	7860	DRIVER( poizone ) /* (c) 1990 Sisteme */
7857	7861	DRIVER( ssfindo ) /* (c) 1999 Icarus */
7858	7862	DRIVER( ppcar ) /* (c) 1999 Icarus */
7859	7863	DRIVER( imolagp ) /* (c) 1981 Leante Games */
r2864	r2865
8057	8061	DRIVER( 2mindril ) /* (c) 1993 Taito */
8058	8062	DRIVER( koikoi ) /* (c) 1983 Kiwako */
8059	8063	DRIVER( good ) /* (c) 1983 Kiwako */
8060		DRIVER( filetto )
	8064	DRIVER( filetto ) /* (c) 1990 Novamatic */
8061	8065	DRIVER( quizo ) /* (c) 1985 Seoul Coin Corp. */
8062	8066	DRIVER( quizoa ) /* (c) 1985 Seoul Coin Corp. */
8063	8067	DRIVER( gstream ) /* (c) 2002, Oriental Soft Japan */
r2864	r2865
8082	8086	DRIVER( pebe0014 ) /* (c) 1994 IGT - International Gaming Technology */
8083	8087	DRIVER( peke1012 ) /* (c) 1994 IGT - International Gaming Technology */
8084	8088	DRIVER( peps0014 ) /* (c) 1996 IGT - International Gaming Technology */
8085		DRIVER( peps0022 ) /* (c) 1996 IGT - International Gaming Technology */
8086		DRIVER( peps0043 ) /* (c) 1996 IGT - International Gaming Technology */
8087		DRIVER( peps0045 ) /* (c) 1996 IGT - International Gaming Technology */
8088		DRIVER( peps0308 ) /* (c) 1996 IGT - International Gaming Technology */
	8089	DRIVER( peps0022 ) /* (c) 1996 IGT - International Gaming Technology */
	8090	DRIVER( peps0043 ) /* (c) 1996 IGT - International Gaming Technology */
	8091	DRIVER( peps0045 ) /* (c) 1996 IGT - International Gaming Technology */
	8092	DRIVER( peps0308 ) /* (c) 1996 IGT - International Gaming Technology */
8089	8093	DRIVER( peps0615 ) /* (c) 1996 IGT - International Gaming Technology */
8090	8094	DRIVER( peps0716 ) /* (c) 1996 IGT - International Gaming Technology */
8091	8095	DRIVER( pexp0019 ) /* (c) 1995 IGT - International Gaming Technology */
r2864	r2865
8097	8101	DRIVER( jongkyo ) /* (c) 1985 Kiwako */
8098	8102	DRIVER( gtipoker ) /* (c) 1983 GTI Inc */
8099	8103	DRIVER( gamecstl ) /* MAME based bootleg */
8100		DRIVER( drw80pkr )
8101		DRIVER( blazlaz )
8102		DRIVER( paranoia )
8103		DRIVER( vcombat ) /* (c) 1993 VR8 Inc. */
8104		DRIVER( shadfgtr ) /* (c) 1989 Sega? */
8105		DRIVER( blackt96 )
	8104	DRIVER( drw80pkr ) /* (c) 1983 IGT */
	8105	DRIVER( blazlaz ) /* (c) 1989 Hudson Soft */
	8106	DRIVER( paranoia ) /* (c) 1990 Naxat Soft */
	8107	DRIVER( vcombat ) /* (c) 1993 VR8 Inc. */
	8108	DRIVER( shadfgtr ) /* (c) 1989 Sega? */
	8109	DRIVER( blackt96 ) /* (c) 1996 D.G.R.M. of Korea */
8106	8110
8107	8111	/* H8/3048 italian gambling games */
8108	8112	DRIVER( laperla ) /* (c) 2002 Nazionale Elettronica */
r2864	r2865
8129	8133	DRIVER( grandprx ) /* (c) 4fun */
8130	8134
8131	8135	/* Astro Corp. */
8132		DRIVER( showhand )
	8136	DRIVER( showhand ) /* (c) 1999? Astro Corp. */
8133	8137
8134	8138	#endif /* DRIVER_RECURSIVE */

src/mame/includes/namcos1.h
r2864	r2865
41	41	DRIVER_INIT( soukobdx );
42	42	DRIVER_INIT( puzlclub );
43	43	DRIVER_INIT( tankfrce );
	44	DRIVER_INIT( tankfrc4 );
44	45
45
46	46	/----------- defined in video/namcos1.c -----------/
47	47
48	48	READ8_HANDLER( namcos1_videoram_r );

src/mame/includes/itech32.h
r2864	r2865
14	14
15	15	/----------- defined in drivers/itech32.c -----------/
16	16
17		void itech32_update_interrupts(int vint, int xint, int qint);
	17	void itech32_update_interrupts(running_machine *machine, int vint, int xint, int qint);
18	18
19	19
20	20	/----------- defined in video/itech32.c -----------/

src/mame/includes/tank8.h
r2864	r2865
30	30
31	31	/----------- defined in drivers/tank8.c -----------/
32	32
33		void tank8_set_collision(int index);
	33	void tank8_set_collision(running_machine *machine, int index);
34	34
35	35
36	36	/----------- defined in video/tank8.c -----------/

src/mame/includes/gstriker.h
r2864	r2865
61	61	UINT16* vram;
62	62	UINT16 pal_base;
63	63	UINT8 gfx_region;
	64	UINT8 transpen;
64	65
65	66	} tCG10103;
66	67
r2864	r2865
72	73	VIDEO_UPDATE( gstriker );
73	74	VIDEO_START( gstriker );
74	75	VIDEO_START( twrldc94 );
75
	76	VIDEO_START( vgoalsoc );
76	77	#endif

src/mame/includes/neogeo.h
r2864	r2865
44	44
45	45	void neogeo_set_display_position_interrupt_control(UINT16 data);
46	46	void neogeo_set_display_counter_msb(UINT16 data);
47		void neogeo_set_display_counter_lsb(UINT16 data);
48		void neogeo_acknowledge_interrupt(UINT16 data);
	47	void neogeo_set_display_counter_lsb(running_machine *machine, UINT16 data);
	48	void neogeo_acknowledge_interrupt(running_machine *machine, UINT16 data);
49	49	void neogeo_set_main_cpu_bank_address(UINT32 bank_address);
50	50	READ16_HANDLER( neogeo_unmapped_r );
51	51

src/mame/includes/n64.h
r2864	r2865
59	59	extern UINT32 n64_vi_origin;
60	60	extern UINT32 n64_vi_control;
61	61
62		extern void dp_full_sync(void);
63		extern void signal_rcp_interrupt(int interrupt);
64		extern void clear_rcp_interrupt(int interrupt);
	62	extern void dp_full_sync(running_machine *machine);
	63	extern void signal_rcp_interrupt(running_machine *machine, int interrupt);
	64	extern void clear_rcp_interrupt(running_machine *machine, int interrupt);
65	65
66	66
67	67	/* read/write handlers for the N64 subsystems */
r2864	r2865
84	84	extern READ32_HANDLER( n64_pif_ram_r );
85	85	extern WRITE32_HANDLER( n64_pif_ram_w );
86	86
87		void n64_machine_reset(void);
	87	void n64_machine_reset(running_machine *machine);
88	88
89	89	#endif

src/mame/includes/dcheese.h
r2864	r2865
7	7
8	8	/----------- defined in drivers/dcheese.c -----------/
9	9
10		void dcheese_signal_irq(int which);
	10	void dcheese_signal_irq(running_machine *machine, int which);
11	11
12	12
13	13	/----------- defined in video/dcheese.c -----------/

src/mame/includes/sprint8.h
r2864	r2865
1	1	/----------- defined in drivers/sprint8.c -----------/
2	2
3		void sprint8_set_collision(int n);
	3	void sprint8_set_collision(running_machine *machine, int n);
4	4
5	5
6	6	/----------- defined in video/sprint8.c -----------/

src/mame/includes/dec0.h
r2864	r2865
63	63	DRIVER_INIT( hbarrelw );
64	64	DRIVER_INIT( birdtry );
65	65
66		extern void dec0_i8751_write(int data);
	66	extern void dec0_i8751_write(running_machine *machine, int data);
67	67	extern void dec0_i8751_reset(void);
68	68	READ8_HANDLER( hippodrm_prot_r );
69	69	WRITE8_HANDLER( hippodrm_prot_w );

src/mame/includes/genesis.h
r2864	r2865
21	21	extern UINT16 *genesis_68k_ram;
22	22	extern MACHINE_START( genesis );
23	23	extern MACHINE_RESET( genesis );
24		extern READ16_HANDLER ( megaplay_genesis_io_r );
25	24	extern WRITE16_HANDLER ( genesis_io_w );
26	25	extern UINT16 *genesis_io_ram;
27	26	extern READ16_HANDLER(genesis_ctrl_r);
r2864	r2865
31	30	extern WRITE8_HANDLER ( genesis_z80_w );
32	31	extern WRITE16_HANDLER(genesis_ctrl_w);
33	32	extern WRITE16_HANDLER ( genesis_68k_to_z80_w );
34		extern READ16_HANDLER ( genesis_io_r );
35	33	extern READ16_HANDLER ( genesis_68k_to_z80_r );
36	34	extern INTERRUPT_GEN( genesis_vblank_interrupt );
37	35	extern void genesis_irq2_interrupt(running_machine *machine, int state);
r2864	r2865
56	54
57	55	READ16_HANDLER ( genesis_vdp_r );
58	56	WRITE16_HANDLER( genesis_vdp_w );
59
60		/* Generic Input Ports */
61		#define GENESIS_PORTS \
62		PORT_START \
63		\
64		PORT_START /* Player 1 Controls - part 1 */ \
65		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) \
66		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) \
67		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) \
68		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) \
69		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) \
70		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) \
71		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) \
72		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) \
73		\
74		PORT_START /* Player 1 Controls - part 2 */ \
75		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) \
76		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) \
77		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED ) \
78		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED ) \
79		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) \
80		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) \
81		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) \
82		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) \
83		\
84		PORT_START /* Player 2 Controls - part 1 */ \
85		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) \
86		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) \
87		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2) \
88		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2) \
89		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) \
90		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) \
91		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) \
92		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) \
93		\
94		PORT_START /* Player 2 Controls - part 2 */ \
95		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) \
96		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) \
97		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED ) \
98		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED ) \
99		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) \
100		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 ) \
101		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) \
102		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) \
103
104

src/mame/includes/triplhnt.h
r2864	r2865
17	17
18	18	/----------- defined in drivers/triplhnt.c -----------/
19	19
20		void triplhnt_set_collision(int data);
	20	void triplhnt_set_collision(running_machine *machine, int data);
21	21
22	22
23	23	/----------- defined in audio/triplhnt.c -----------/

src/mame/includes/slapstic.h
r2864	r2865
11	11
12	12	/----------- defined in machine/slapstic.c -----------/
13	13
14		void slapstic_init(int chip);
	14	void slapstic_init(running_machine *machine, int chip);
15	15	void slapstic_reset(void);
16	16
17	17	int slapstic_bank(void);

src/mame/video/fgoal.c
r2864	r2865
51	51
52	52	/* draw color overlay foreground and background */
53	53
54		if (fgoal_player == 1 && (input_port_read~~_indexed~~(screen->machine, 1) & 0x40))
	54	if (fgoal_player == 1 && (input_port_read(screen->machine, "IN1") & 0x40))
55	55	{
56	56	drawgfxzoom(fgbitmap, screen->machine->gfx[0],
57	57	0, (fgoal_player << 2) \| current_color,

src/mame/video/stvvdp2.c
r2864	r2865
82	82	#include "driver.h"
83	83	#include "eminline.h"
84	84	#include "profiler.h"
85		#include "deprecat.h"
86	85	#include "includes/stv.h"
87	86
88	87	UINT32* stv_vdp2_regs;
r2864	r2865
5259	5258	stv_rbg_cache_data.is_cache_dirty = 3;
5260	5259	memset( &stv_vdp2_layer_data_placement, 0, sizeof(stv_vdp2_layer_data_placement));
5261	5260
5262		refresh_palette_data(Machine);
	5261	refresh_palette_data(machine);
5263	5262	}
5264	5263
5265	5264	static int stv_vdp2_start (running_machine *machine)

src/mame/video/itech32.c
r2864	r2865
462	462	*
463	463	*************************************/
464	464
465		static void update_interrupts(int fast)
	465	static void update_interrupts(running_machine *machine, int fast)
466	466	{
467	467	int scanline_state = 0, blitter_state = 0;
468	468
r2864	r2865
471	471	if (VIDEO_INTSTATE & VIDEO_INTENABLE & VIDEOINT_BLITTER)
472	472	blitter_state = 1;
473	473
474		itech32_update_interrupts(-1, blitter_state, scanline_state);
	474	itech32_update_interrupts(machine, -1, blitter_state, scanline_state);
475	475	}
476	476
477	477
r2864	r2865
485	485	VIDEO_INTSTATE \|= VIDEOINT_SCANLINE;
486	486
487	487	/* update the interrupt state */
488		update_interrupts(0);
	488	update_interrupts(machine, 0);
489	489	}
490	490
491	491
r2864	r2865
1195	1195	*
1196	1196	*************************************/
1197	1197
1198		static void handle_video_command(void)
	1198	static void handle_video_command(running_machine *machine)
1199	1199	{
1200	1200	/* only 6 known commands */
1201	1201	switch (VIDEO_COMMAND)
r2864	r2865
1271	1271
1272	1272	/* tell the processor we're done */
1273	1273	VIDEO_INTSTATE \|= VIDEOINT_BLITTER;
1274		update_interrupts(1);
	1274	update_interrupts(machine, 1);
1275	1275	}
1276	1276
1277	1277
r2864	r2865
1293	1293	{
1294	1294	case 0x02/2: /* VIDEO_INTACK */
1295	1295	VIDEO_INTSTATE = old & ~data;
1296		update_interrupts(1);
	1296	update_interrupts(machine, 1);
1297	1297	break;
1298	1298
1299	1299	case 0x04/2: /* VIDEO_TRANSFER */
r2864	r2865
1318	1318	break;
1319	1319
1320	1320	case 0x08/2: /* VIDEO_COMMAND */
1321		handle_video_command();
	1321	handle_video_command(machine);
1322	1322	break;
1323	1323
1324	1324	case 0x0a/2: /* VIDEO_INTENABLE */
1325		update_interrupts(1);
	1325	update_interrupts(machine, 1);
1326	1326	break;
1327	1327
1328	1328	case 0x24/2: /* VIDEO_LEFTCLIP */

src/mame/video/tank8.c
r2864	r2865
196	196
197	197	static TIMER_CALLBACK( tank8_collision_callback )
198	198	{
199		tank8_set_collision(param);
	199	tank8_set_collision(machine, param);
200	200	}
201	201
202	202

src/mame/video/cps1.c
r2864	r2865
86	86	Quiz Tonosama no Yabou 2 1995 ? ? ? ?
87	87	Pnickies 1994 ? ? ? CPS-B-21? DL-0921-10014? ?
88	88	Pang 3 1995 94916-10 CP1B1F,CP1B8K,CP1B9KA 92631C-6 CPS-B-21 DL-0921-10014 C632 IOC1
89		Megaman the Power Battle 1995 91634B-2 RCM63B BPRG1 IOB1 ? CPS-B-21 DL-0921-10014 C632 IOC1
	89	Megaman the Power Battle 1995 91634B-2 RCM63B BPRG1 IOB1 92631C-6 CPS-B-21 DL-0921-10014 C632 IOC1
90	90
91	91	@actually CPS-B-01, the original number was scratched out and "04" stamped over it
92	92	*denotes Suicide Battery

src/mame/video/lethalj.c
r2864	r2865
35	35
36	36	INLINE void get_crosshair_xy(running_machine machine, int player, int x, int *y)
37	37	{
	38	static const char *gunnames[] = { "LIGHT0_X", "LIGHT0_Y", "LIGHT1_X", "LIGHT1_Y" };
38	39	const rectangle *visarea = video_screen_get_visible_area(machine->primary_screen);
39	40	int width = visarea->max_x + 1 - visarea->min_x;
40	41	int height = visarea->max_y + 1 - visarea->min_y;
41	42
42		x = ((input_port_read_indexed(machine, 2 + player 2) & 0xff) * width) / 255;
43		y = ((input_port_read_indexed(machine, 3 + player 2) & 0xff) * height) / 255;
	43	x = ((input_port_read(machine, gunnames[player 2]) & 0xff) * width) / 255;
	44	y = ((input_port_read(machine, gunnames[1 + player 2]) & 0xff) * height) / 255;
44	45	}
45	46
46	47

src/mame/video/itech8.c
r2864	r2865
459	459	READ8_HANDLER( itech8_blitter_r )
460	460	{
461	461	int result = blitter_data[offset / 2];
	462	static const char *portnames[] = { "AN_C", "AN_D", "AN_E", "AN_F" };
462	463
463	464	/* debugging */
464	465	if (FULL_LOGGING) logerror("%04x:blitter_r(%02x)\n", activecpu_get_previouspc(), offset / 2);
r2864	r2865
478	479
479	480	/* a read from offsets 12-15 return input port values */
480	481	if (offset >= 12 && offset <= 15)
481		result = input_port_read~~_indexed~~(machine, ~~3 +~~ offset - 12);
	482	result = input_port_read(machine, portnames[offset - 12]);
482	483
483	484	return result;
484	485	}

src/mame/video/gstriker.c
r2864	r2865
449	449	for (x=0;x<xnum;x++)
450	450	{
451	451	// Hack to handle horizontal wrapping
452		drawgfxzoom(screen, machine->gfx[CG10103_cur_chip->gfx_region], tile, color+CG10103_cur_chip->pal_base, flipx, flipy, xp>>16, ypos>>16, cliprect, TRANSPARENCY_PEN, 0x0, xfact, yfact);
453		drawgfxzoom(screen, machine->gfx[CG10103_cur_chip->gfx_region], tile, color+CG10103_cur_chip->pal_base, flipx, flipy, (xp>>16) - 0x200, ypos>>16, cliprect, TRANSPARENCY_PEN, 0x0, xfact, yfact);
	452	drawgfxzoom(screen, machine->gfx[CG10103_cur_chip->gfx_region], tile, color+CG10103_cur_chip->pal_base, flipx, flipy, xp>>16, ypos>>16, cliprect, TRANSPARENCY_PEN, CG10103_cur_chip->transpen, xfact, yfact);
	453	drawgfxzoom(screen, machine->gfx[CG10103_cur_chip->gfx_region], tile, color+CG10103_cur_chip->pal_base, flipx, flipy, (xp>>16) - 0x200, ypos>>16, cliprect, TRANSPARENCY_PEN, CG10103_cur_chip->transpen, xfact, yfact);
454	454	xp += xstep;
455	455	tile++;
456	456	}
r2864	r2865
514	514	CG10103[numchip].gfx_region = gfx_region;
515	515	}
516	516
	517	static void CG10103_set_transpen(int numchip, int transpen)
	518	{
	519	CG10103[numchip].transpen = transpen;
	520	}
517	521
518	522
519	523	/* VIDEO UPDATE/START ********************************************/
r2864	r2865
578	582	CG10103_init(1);
579	583	CG10103_set_gfx_region(0, 2);
580	584	CG10103_set_pal_base(0, 0x10);
	585	CG10103_set_transpen(0, 0x0);
581	586	}
582	587
583	588	VIDEO_START(twrldc94)
r2864	r2865
600	605	CG10103_init(1);
601	606	CG10103_set_gfx_region(0, 2);
602	607	CG10103_set_pal_base(0, 0x60);
	608	CG10103_set_transpen(0, 0x0);
603	609	}
604	610
	611	VIDEO_START(vgoalsoc)
	612	{
	613	// Palette bases are hardcoded, but should be probably extracted from the mixer registers
	614
	615	// Initalize the chip for the score plane
	616	VS920A_init(1);
	617	VS920A_set_gfx_region(0, 0);
	618	VS920A_set_pal_base(0, 0x30);
	619	tilemap_set_transparent_pen(VS920A_get_tilemap(0), 0xf);
	620
	621	// Initalize the chip for the screen plane
	622	MB60553_init(1);
	623	MB60553_set_gfx_region(0, 1);
	624	MB60553_set_pal_base(0, 0x20);
	625	tilemap_set_transparent_pen(MB60553_get_tilemap(0), 0xf);
	626
	627	// Initialize the sprite generator
	628	CG10103_init(1);
	629	CG10103_set_gfx_region(0, 2);
	630	CG10103_set_pal_base(0, 0x00);
	631	CG10103_set_transpen(0, 0xf);
	632	}

src/mame/video/lazercmd.c
r2864	r2865
32	32	int xbit, ybit, size;
33	33
34	34	size = 2;
35		if (input_port_read~~_indexed~~(machine, 2) & 0x40)
	35	if (input_port_read(machine, "DSW") & 0x40)
36	36	{
37	37	size = 4;
38	38	}
r2864	r2865
57	57	{
58	58	int i,x,y;
59	59
60		int video_inverted = input_port_read~~_indexed~~(screen->machine, 2) & 0x20;
	60	int video_inverted = input_port_read(screen->machine, "DSW") & 0x20;
61	61
62	62	/* The first row of characters are invisible */
63	63	for (i = 0; i < (VERT_RES - 1) * HORZ_RES; i++)

src/mame/video/lordgun.c
r2864	r2865
186	186	0x1B3,0x1B4,0x1B5,0x1B6,0x1B7,0x1B8,0x1B9,0x1BA,0x1BB,0x1BC,0x1BD,0x1BE,0x1BF,0x1BF
187	187	};
188	188
	189
	190	static const char *gunnames[] = { "LIGHT0_X", "LIGHT1_X", "LIGHT0_Y", "LIGHT1_Y" };
	191
189	192	static void lorddgun_calc_gun_scr(running_machine *machine, int i)
190	193	{
191		int x = input_port_read_indexed(machine, 5+i) - 0x3c;
	194	int x = input_port_read(machine, gunnames[i]) - 0x3c;
	195
192	196	if ( (x < 0) \|\| (x > sizeof(lordgun_gun_x_table)/sizeof(lordgun_gun_x_table[0])) )
193	197	x = 0;
194	198
195	199	lordgun_gun[i].scr_x = lordgun_gun_x_table[x];
196		lordgun_gun[i].scr_y = input_port_read~~_indexed~~(machine, 7+i);
	200	lordgun_gun[i].scr_y = input_port_read(machine, gunnames[i+2]);
197	201	}
198	202
199	203	void lordgun_update_gun(running_machine *machine, int i)
200	204	{
201	205	const rectangle *visarea = video_screen_get_visible_area(machine->primary_screen);
202	206
203		lordgun_gun[i].hw_x = input_port_read_indexed(machine, 5+i);
204		lordgun_gun[i].hw_y = input_port_read_indexed(machine, 7+i);
	207	lordgun_gun[i].hw_x = input_port_read(machine, gunnames[i]);
	208	lordgun_gun[i].hw_y = input_port_read(machine, gunnames[i+2]);
205	209
206	210	lorddgun_calc_gun_scr(machine, i);
207	211

src/mame/video/atarirle.c
r2864	r2865
19	19	***************************************************************************/
20	20
21	21	#include "driver.h"
22		#include "deprecat.h"
	22	//#include "deprecat.h"
23	23	#include "atarirle.h"
24	24
25	25

src/mame/video/snes.c
r2864	r2865
1443	1443	* Stop drawing if exceeded 32 objects and
1444	1444	* enforcing that limit is enabled */
1445	1445	range_over++;
1446		if( range_over == 32 ) //&& (input_port_read~~_indexed~~(machine, 16 ) & 0x10) )
	1446	if( range_over == 32 ) //&& (input_port_read(machine, "INTERNAL") & 0x01) )
1447	1447	{
1448	1448	/* Set the flag in STAT77 register */
1449	1449	snes_ram[STAT77] \|= 0x40;
r2864	r2865
1984	1984
1985	1985	if( !debug_options.input_count-- )
1986	1986	{
1987		UINT8 toggles = input_port_read_~~ind~~e~~xed~~(machine, 10 );
	1987	UINT8 toggles = input_port_read_safe(machine, "DEBUG2", 0);
1988	1988	if( toggles & 0x1 )
1989	1989	debug_options.bg_disabled[0] = !debug_options.bg_disabled[0];
1990	1990	if( toggles & 0x2 )
r2864	r2865
2001	2001	debug_options.bg_disabled[5] = !debug_options.bg_disabled[5];
2002	2002	if( toggles & 0x80 )
2003	2003	debug_options.windows_disabled = !debug_options.windows_disabled;
2004		toggles = input_port_read_~~ind~~e~~xed~~(machine, 11 );
	2004	toggles = input_port_read_safe(machine, "DEBUG3", 0);
2005	2005	if( toggles & 0x4 )
2006	2006	debug_options.transparency_disabled = !debug_options.transparency_disabled;
2007	2007	debug_options.input_count = 5;
r2864	r2865
2111	2111	}
2112	2112	/* Just for testing, draw as many tiles as possible */
2113	2113	{
2114		UINT8 adjust = input_port_read_indexed(machine, 1 );
2115		UINT8 dip = input_port_read_indexed(machine, 9 );
2116		UINT8 inp = input_port_read_indexed(machine, 11 );
	2114	UINT8 adjust = input_port_read(machine, "PAD1H");
	2115	UINT8 dip = input_port_read_safe(machine, "DEBUG1", 0);
	2116	UINT8 inp = input_port_read_safe(machine, "DEBUG3", 0);
2117	2117	UINT8 dt = 1 << ((dip & 0x3) - 1);
2118	2118	UINT8 dm = 1 << (((dip & 0xc) >> 2) - 1);
2119	2119	if( dt )

src/mame/video/rockola.c
r2864	r2865
7	7	***************************************************************************/
8	8
9	9	#include "driver.h"
10		#include "deprecat.h"
11	10
12	11
13	12	UINT8 *rockola_videoram2;

src/mame/video/sprint8.c
r2864	r2865
162	162
163	163	static TIMER_CALLBACK( sprint8_collision_callback )
164	164	{
165		sprint8_set_collision(param);
	165	sprint8_set_collision(machine, param);
166	166	}
167	167
168	168

src/mame/video/raiden.c
r2864	r2865
100	100	}
101	101	}
102	102
	103	WRITE16_HANDLER( raidena_control_w )
	104	{
	105	/* raidena uses 0x40 instead of 0x02 */
	106
	107	/* Flipscreen */
	108	if (offset==3 && ACCESSING_BITS_0_7) {
	109	flipscreen=data&0x40;
	110	tilemap_set_flip(ALL_TILEMAPS,flipscreen ? (TILEMAP_FLIPY \| TILEMAP_FLIPX) : 0);
	111	}
	112	}
	113
103	114	static void draw_sprites(running_machine machine, bitmap_t bitmap,const rectangle *cliprect,int pri_mask)
104	115	{
105	116	int offs,fx,fy,x,y,color,sprite;

src/mame/video/victory.c
r2864	r2865
5	5	***************************************************************************/
6	6
7	7	#include "driver.h"
8		#include "deprecat.h"
9	8	#include "victory.h"
10	9
11	10
r2864	r2865
55	54
56	55	/* function prototypes */
57	56	static int command2(void);
58		static int command3(void);
59		static int command4(void);
60		static int command5(void);
	57	static int command3(running_machine *machine);
	58	static int command4(running_machine *machine);
	59	static int command5(running_machine *machine);
61	60	static int command6(void);
62		static int command7(void);
	61	static int command7(running_machine *machine);
63	62
64	63
65	64
r2864	r2865
232	231	if (micro.cmdlo == 5)
233	232	{
234	233	if (LOG_MICROCODE) logerror(" Command 5 triggered by write to IH\n");
235		command5();
	234	command5(machine);
236	235	}
237	236	break;
238	237
r2864	r2865
262	261	if (micro.cmdlo == 3)
263	262	{
264	263	if (LOG_MICROCODE) logerror(" Command 3 triggered by write to X\n");
265		command3();
	264	command3(machine);
266	265	}
267	266	break;
268	267
r2864	r2865
272	271	if (micro.cmdlo == 4)
273	272	{
274	273	if (LOG_MICROCODE) logerror(" Command 4 triggered by write to Y\n");
275		command4();
	274	command4(machine);
276	275	}
277	276	break;
278	277
r2864	r2865
292	291	else if (micro.cmdlo == 7)
293	292	{
294	293	if (LOG_MICROCODE) logerror(" Command 7 triggered by write to B\n");
295		command7();
	294	command7(machine);
296	295	}
297	296	break;
298	297
r2864	r2865
585	584	*
586	585	*************************************/
587	586
588		static int command3(void)
	587	static int command3(running_machine *machine)
589	588	{
590	589	/*
591	590	Actual microcode:
r2864	r2865
674	673	rram[dstoffs + 0] ^= src >> shift;
675	674	rram[dstoffs + 1] ^= src << nshift;
676	675	}
677		if (fgcoll) victory_update_irq(Machine);
	676	if (fgcoll) victory_update_irq(machine);
678	677	}
679	678	}
680	679	}
r2864	r2865
692	691	*
693	692	*************************************/
694	693
695		static int command4(void)
	694	static int command4(running_machine *machine)
696	695	{
697	696	/*
698	697	Actual microcode:
r2864	r2865
734	733	case 0: break;
735	734	case 1: break;
736	735	case 2: keep_going = command2(); break;
737		case 3: keep_going = command3(); break;
	736	case 3: keep_going = command3(machine); break;
738	737	case 4: micro.pc = micro.yp << 1; keep_going = 1; break;
739		case 5: keep_going = command5(); break;
	738	case 5: keep_going = command5(machine); break;
740	739	case 6: keep_going = command6(); break;
741		case 7: keep_going = command7(); break;
	740	case 7: keep_going = command7(machine); break;
742	741	}
743	742	} while (keep_going);
744	743
r2864	r2865
755	754	*
756	755	*************************************/
757	756
758		static int command5(void)
	757	static int command5(running_machine *machine)
759	758	{
760	759	/*
761	760	Actual microcode:
r2864	r2865
874	873	}
875	874	acc &= 0xff;
876	875	}
877		if (fgcoll) victory_update_irq(Machine);
	876	if (fgcoll) victory_update_irq(machine);
878	877	}
879	878
880	879	micro.xp = x;
r2864	r2865
941	940	*
942	941	*************************************/
943	942
944		static int command7(void)
	943	static int command7(running_machine *machine)
945	944	{
946	945	/*
947	946	Actual microcode:
r2864	r2865
1004	1003	rram[addr + 0] ^= micro.r >> shift;
1005	1004	rram[addr + 1] ^= micro.r << nshift;
1006	1005	}
1007		if (fgcoll) victory_update_irq(Machine);
	1006	if (fgcoll) victory_update_irq(machine);
1008	1007	}
1009	1008
1010	1009	count_states(4);

src/mame/video/exidy440.c
r2864	r2865
445	445	{
446	446	int i;
447	447
448		int beamx = ((input_port_read_indexed(screen->machine, 4) & 0xff) * (HBSTART - HBEND)) >> 8;
449		int beamy = ((input_port_read_indexed(screen->machine, 5) & 0xff) * (VBSTART - VBEND)) >> 8;
	448	int beamx = ((input_port_read(screen->machine, "AN0") & 0xff) * (HBSTART - HBEND)) >> 8;
	449	int beamy = ((input_port_read(screen->machine, "AN1") & 0xff) * (VBSTART - VBEND)) >> 8;
450	450
451	451	/* The timing of this FIRQ is very important. The games look for an FIRQ
452	452	and then wait about 650 cycles, clear the old FIRQ, and wait a

src/mame/video/lethal.c
r2864	r2865
10	10	#include "driver.h"
11	11	#include "video/konamiic.h"
12	12
13		#define GUNX( a ) ( ( input_port_read_indexed(machine, a ) * 287 ) / 0xff )
14		#define GUNY( a ) ( ( input_port_read_indexed(machine, a ) * 223 ) / 0xff )
15	13
16	14	static int sprite_colorbase;
17	15	static int layer_colorbase[4];

src/mame/video/atari.c
r2864	r2865
7	7	******************************************************************************/
8	8
9	9	#include "driver.h"
10		#include "deprecat.h"
11	10	#include "includes/atari.h"
12	11	#include "video/gtia.h"
13	12

src/mame/video/decocass.c
r2864	r2865
607	607	int scrollx, scrolly_l, scrolly_r;
608	608	rectangle clip;
609	609
610		if (0xc0 != (input_port_read~~_indexed~~(screen->machine, 2) & 0xc0)) /* coin slots assert an NMI */
	610	if (0xc0 != (input_port_read(screen->machine, "IN2") & 0xc0)) /* coin slots assert an NMI */
611	611	cpunum_set_input_line(screen->machine, 0, INPUT_LINE_NMI, ASSERT_LINE);
612	612
613	613	if (0 == (watchdog_flip & 0x04))

src/mame/video/mystwarr.c
r2864	r2865
172	172
173	173	K055673_vh_start(machine, REGION_GFX2, 1, -61, -22, gaiapols_sprite_callback); // stage2 brick walls
174	174
175		konamigx_mixer_init(0);
	175	konamigx_mixer_init(machine, 0);
176	176
177	177	K056832_set_LayerOffset(0, -2+2-1, 0-1);
178	178	K056832_set_LayerOffset(1, 0+2, 0);
r2864	r2865
214	214
215	215	K055673_vh_start(machine, REGION_GFX2, 0, -42, -22, gaiapols_sprite_callback);
216	216
217		konamigx_mixer_init(0);
	217	konamigx_mixer_init(machine, 0);
218	218
219	219	konamigx_mixer_primode(1);
220	220
r2864	r2865
245	245
246	246	K055673_vh_start(machine, REGION_GFX2, 0, -48, -24, mystwarr_sprite_callback);
247	247
248		konamigx_mixer_init(0);
	248	konamigx_mixer_init(machine, 0);
249	249
250	250	K056832_set_LayerOffset(0, -2-3, 0);
251	251	K056832_set_LayerOffset(1, 0-3, 0);
r2864	r2865
273	273
274	274	K055673_vh_start(machine, REGION_GFX2, 1, -51, -22, metamrph_sprite_callback);
275	275
276		konamigx_mixer_init(0);
	276	konamigx_mixer_init(machine, 0);
277	277
278	278	// other reference, floor at first boss
279	279	K056832_set_LayerOffset(0, -2+4, 0); // text
r2864	r2865
299	299
300	300	K055673_vh_start(machine, REGION_GFX2, 1, -62, -23, metamrph_sprite_callback);
301	301
302		konamigx_mixer_init(0);
	302	konamigx_mixer_init(machine, 0);
303	303
304	304	K056832_set_LayerOffset(0, -2+1, 0);
305	305	K056832_set_LayerOffset(1, 0+1, 0);
r2864	r2865
322	322
323	323	K055673_vh_start(machine, REGION_GFX2, 0, -58, -23, martchmp_sprite_callback);
324	324
325		konamigx_mixer_init(0);
	325	konamigx_mixer_init(machine, 0);
326	326
327	327	K056832_set_LayerOffset(0, -2-4, 0);
328	328	K056832_set_LayerOffset(1, 0-4, 0);

src/mame/video/irobot.c
r2864	r2865
5	5	***************************************************************************/
6	6
7	7	#include "driver.h"
8		#include "deprecat.h"
9	8	#include "irobot.h"
10	9
11	10	#define BITMAP_WIDTH 256

src/mame/video/neogeo.c
r2864	r2865
843	843	case 0x02: set_videoram_modulo(data); break;
844	844	case 0x03: set_video_control(data); break;
845	845	case 0x04: neogeo_set_display_counter_msb(data); break;
846		case 0x05: neogeo_set_display_counter_lsb(data); break;
847		case 0x06: neogeo_acknowledge_interrupt(data); break;
	846	case 0x05: neogeo_set_display_counter_lsb(machine, data); break;
	847	case 0x06: neogeo_acknowledge_interrupt(machine, data); break;
848	848	case 0x07: break; /* unknown, see get_video_control */
849	849	}
850	850	}

src/mame/video/konamigx.c
r2864	r2865
140	140	> so, well, the top bits of the code are suspicious
141	141	*/
142	142
143		static void _gxcommoninitnosprites(void)
	143	static void _gxcommoninitnosprites(running_machine *machine)
144	144	{
145	145	int i;
146	146
147	147	K054338_vh_start();
148	148	K055555_vh_start();
149	149
150		konamigx_mixer_init(0);
	150	konamigx_mixer_init(machine, 0);
151	151
152	152	for (i = 0; i < 8; i++)
153	153	{
r2864	r2865
176	176
177	177	gx_rozenable = 0;
178	178
179		_gxcommoninitnosprites();
	179	_gxcommoninitnosprites(machine);
180	180	}
181	181
182	182
r2864	r2865
227	227	K056832_vh_start(machine, REGION_GFX1, K056832_BPP_8, 0, NULL, konamigx_alpha_tile_callback, 0);
228	228	K055673_vh_start(machine, REGION_GFX2, K055673_LAYOUT_LE2, -53, -23, konamigx_type2_sprite_callback);
229	229
230		_gxcommoninitnosprites();
	230	_gxcommoninitnosprites(machine);
231	231	}
232	232
233	233	VIDEO_START(dragoonj)
r2864	r2865
235	235	K056832_vh_start(machine, REGION_GFX1, K056832_BPP_5, 1, NULL, konamigx_type2_tile_callback, 0);
236	236	K055673_vh_start(machine, REGION_GFX2, K055673_LAYOUT_RNG, -53, -23, konamigx_dragoonj_sprite_callback);
237	237
238		_gxcommoninitnosprites();
	238	_gxcommoninitnosprites(machine);
239	239
240	240	K056832_set_LayerOffset(0, -2+1, 0);
241	241	K056832_set_LayerOffset(1, 0+1, 0);
r2864	r2865
248	248	K056832_vh_start(machine, REGION_GFX1, K056832_BPP_8, 1, NULL, konamigx_type2_tile_callback, 0);
249	249	K055673_vh_start(machine, REGION_GFX2, K055673_LAYOUT_LE2, -46, -23, konamigx_le2_sprite_callback);
250	250
251		_gxcommoninitnosprites();
	251	_gxcommoninitnosprites(machine);
252	252
253	253	konamigx_mixer_primode(-1); // swapped layer B and C priorities?
254	254	}
r2864	r2865
300	300	{
301	301	K055673_vh_start(machine, REGION_GFX2, K055673_LAYOUT_GX6, -48, -23, konamigx_salmndr2_sprite_callback);
302	302
303		_gxcommoninitnosprites();
	303	_gxcommoninitnosprites(machine);
304	304	}
305	305	else
306	306	{
r2864	r2865
313	313	K056832_vh_start(machine, REGION_GFX1, K056832_BPP_5, 0, NULL, konamigx_type2_tile_callback, 0);
314	314	K055673_vh_start(machine, REGION_GFX2, K055673_LAYOUT_GX6, -53, -23, konamigx_type2_sprite_callback);
315	315
316		_gxcommoninitnosprites();
	316	_gxcommoninitnosprites(machine);
317	317
318	318	K056832_set_LayerOffset(0, -2+1, 0);
319	319	K056832_set_LayerOffset(1, 0+1, 0);
r2864	r2865
333	333	K056832_vh_start(machine, REGION_GFX1, K056832_BPP_6, 0, NULL, konamigx_type2_tile_callback, 0);
334	334	K055673_vh_start(machine, REGION_GFX2, K055673_LAYOUT_GX, -53, -23, konamigx_type2_sprite_callback);
335	335
336		_gxcommoninitnosprites();
	336	_gxcommoninitnosprites(machine);
337	337
338	338	K056832_set_LayerOffset(0, -2+1, 0);
339	339	K056832_set_LayerOffset(1, 0+1, 0);

src/mame/video/n64.c
r2864	r2865
3	3	*/
4	4
5	5	#include "driver.h"
	6	#include "deprecat.h"
6	7	#include "includes/n64.h"
7	8
8	9	#define LOG_RDP_EXECUTION 0
r2864	r2865
3003	3004
3004	3005	static void rdp_sync_full(UINT32 w1, UINT32 w2)
3005	3006	{
3006		dp_full_sync();
	3007	dp_full_sync(Machine);
3007	3008	}
3008	3009
3009	3010	static void rdp_set_key_gb(UINT32 w1, UINT32 w2)

src/mame/video/m92.c
r2864	r2865
60	60	UINT16 m92_vram_data,m92_spritecontrol;
61	61	UINT8 m92_game_kludge;
62	62
63		extern void m92_sprite_interrupt(void);
	63	extern void m92_sprite_interrupt(running_machine *machine);
64	64	UINT8 m92_sprite_buffer_busy;
65	65	static int m92_palette_bank;
66	66
r2864	r2865
70	70	{
71	71	m92_sprite_buffer_busy = 1;
72	72	if (m92_game_kludge!=2) /* Major Title 2 doesn't like this interrupt!? */
73		m92_sprite_interrupt();
	73	m92_sprite_interrupt(machine);
74	74	}
75	75
76	76	WRITE16_HANDLER( m92_spritecontrol_w )

src/mame/video/dcheese.c
r2864	r2865
88	88
89	89	static TIMER_CALLBACK( blitter_scanline_callback )
90	90	{
91		dcheese_signal_irq(3);
	91	dcheese_signal_irq(machine, 3);
92	92	update_scanline_irq(machine);
93	93	}
94	94
95	95
96	96	static TIMER_CALLBACK( dcheese_signal_irq_callback )
97	97	{
98		dcheese_signal_irq(param);
	98	dcheese_signal_irq(machine, param);
99	99	}
100	100
101	101

src/mame/video/triplhnt.c
r2864	r2865
39	39
40	40	static TIMER_CALLBACK( triplhnt_hit_callback )
41	41	{
42		triplhnt_set_collision(param);
	42	triplhnt_set_collision(machine, param);
43	43	}
44	44
45	45

src/mame/drivers/deco_mlc.c
r2864	r2865
116	116
117	117	static READ32_HANDLER( avengrs_control_r )
118	118	{
119		return (input_port_read~~_indexed~~(machine, 1)<<16) \| (eeprom_read_bit()<<23) \| input_port_read~~_indexed~~(machine, 0);
	119	return (input_port_read(machine, "IN1")<<16) \| (eeprom_read_bit()<<23) \| input_port_read(machine, "IN0");
120	120	}
121	121
122	122	static READ32_HANDLER(test2_r)
123	123	{
124	124	// if (offset==0)
125		// return input_port_read~~_indexed~~(machine, 0); //0xffffffff;
	125	// return input_port_read(machine, "IN0"); //0xffffffff;
126	126	// logerror("%08x: Test2_r %d\n",activecpu_get_pc(),offset);
127	127	return mame_rand(machine); //0xffffffff;
128	128	}
r2864	r2865
330	330	/******************************************************************************/
331	331
332	332	static INPUT_PORTS_START( mlc )
333		PORT_START
	333	PORT_START_TAG("IN0")
334	334	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
335	335	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
336	336	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
348	348	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
349	349	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
350	350
351		PORT_START
	351	PORT_START_TAG("IN1")
352	352	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
353	353	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
354	354	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )

src/mame/drivers/crystal.c
r2864	r2865
639	639	UINT16 *srcline;
640	640	int y;
641	641	UINT16 head,tail;
	642	UINT32 width=video_screen_get_width(screen);
642	643
643	644	if(GetVidReg(0x8e)&1)
644	645	{
r2864	r2865
681	682
682	683	srcline=(UINT16 *) Visible;
683	684	for(y=0;y<240;y++)
684		memcpy(BITMAP_ADDR16(bitmap, y, 0), &srcline[y512], ~~320~~2);
	685	memcpy(BITMAP_ADDR16(bitmap, y, 0), &srcline[y512], width2);
685	686
686	687	return 0;
687	688	}
r2864	r2865
833	834	MDRV_SOUND_ROUTE(1, "right", 1.0)
834	835	MACHINE_DRIVER_END
835	836
	837	/*
	838	Top blade screen is 32 pixels wider
	839	*/
	840	static MACHINE_DRIVER_START( topbladv )
	841	MDRV_IMPORT_FROM(crystal)
	842
	843	MDRV_SCREEN_MODIFY("main")
	844	MDRV_SCREEN_SIZE(320+32, 240)
	845	MDRV_SCREEN_VISIBLE_AREA(0, 319+32, 0, 239)
	846
	847	MACHINE_DRIVER_END
	848
836	849	ROM_START( crysbios )
837	850	ROM_REGION( 0x20000, REGION_CPU1, 0 ) // bios
838	851	ROM_LOAD("mx27l1000.u14", 0x000000, 0x020000, CRC(BEFF39A9) SHA1(b6f6dda58d9c82273f9422c1bd623411e58982cb) )
r2864	r2865
926	939	Rom[WORD_XOR_LE(0x974ED2/2)]=0x9001; //PUSH R0
927	940	}
928	941
	942	static DRIVER_INIT(topbladv)
	943	{
	944	UINT16 Rom=(UINT16) memory_region(REGION_USER1);
	945
	946	Rom[WORD_XOR_LE(0x12d7a/2)]=0x90FC; //PUSH R7-R6-R5-R4-R3-R2
	947	Rom[WORD_XOR_LE(0x12d7c/2)]=0x9001; //PUSH R0
	948
	949	Rom[WORD_XOR_LE(0x2fe18/2)]=0x9001; //PUSH R0
	950	Rom[WORD_XOR_LE(0x2fe1a/2)]=0x9200; //PUSH SR
	951
	952	Rom[WORD_XOR_LE(0x18880/2)]=0x9001; //PUSH R0
	953	Rom[WORD_XOR_LE(0x18882/2)]=0x9200; //PUSH SR
	954
	955	Rom[WORD_XOR_LE(0xDACE/2)]=0x901C; //PUSH R4-R3-R2
	956	Rom[WORD_XOR_LE(0xDAD0/2)]=0x9001; //PUSH R0
	957
	958	}
	959
	960	static DRIVER_INIT(officeye)
	961	{
	962	UINT16 Rom=(UINT16) memory_region(REGION_USER1);
	963
	964	Rom[WORD_XOR_LE(0x9c9e/2)]=0x901C; //PUSH R4-R3-R2
	965	Rom[WORD_XOR_LE(0x9ca0/2)]=0x9001; //PUSH R0
	966
	967	Rom[WORD_XOR_LE(0x9EE4/2)]=0x907C; //PUSH R6-R5-R4-R3-R2
	968	Rom[WORD_XOR_LE(0x9EE6/2)]=0x9001; //PUSH R0
	969
	970	Rom[WORD_XOR_LE(0x4B2E0/2)]=0x9004; //PUSH R2
	971	Rom[WORD_XOR_LE(0x4B2E2/2)]=0x9001; //PUSH R0
	972
	973	/*
	974	Rom[WORD_XOR_LE(0x18880/2)]=0x9001; //PUSH R0
	975	Rom[WORD_XOR_LE(0x18882/2)]=0x9200; //PUSH SR
	976	*/
	977	}
	978
	979
	980
929	981	GAME( 2001, crysbios, 0, crystal, crystal, 0, ROT0, "Brezzasoft", "Crystal System BIOS", GAME_IS_BIOS_ROOT )
930	982	GAME( 2001, crysking, crysbios, crystal, crystal, crysking, ROT0, "Brezzasoft", "The Crystal of Kings", 0 )
931	983	GAME( 2001, evosocc, crysbios, crystal, crystal, evosocc, ROT0, "Evoga", "Evolution Soccer", 0 )
932		GAME( 2001, topbladv, crysbios, crystal, crystal, 0, ROT0, "unknown", "Top Blade V", GAME_NOT_WORKING ) // protection
	984	GAME( 2003, topbladv, crysbios, topbladv,crystal, topbladv, ROT0, "SonoKong / Expotato", "Top Blade V", GAME_NOT_WORKING ) // protection
	985	GAME( 2001, officeye, 0, crystal, crystal, officeye, ROT0, "Danbi", "Office Yeo In Cheon Ha (version 1.2)", GAME_NOT_WORKING ) // protection
933	986
934		GAME( 2001, officeye, 0, crystal, crystal, 0, ROT0, "unknown", "Office Yeo In Cheon Ha", GAME_NOT_WORKING ) // protection
935
936

src/mame/drivers/eprom.c
r2864	r2865
90	90
91	91	static READ16_HANDLER( special_port1_r )
92	92	{
93		int result = input_port_read~~_indexed~~(machine, 1);
	93	int result = input_port_read(machine, "260010");
94	94
95	95	if (atarigen_sound_to_cpu_ready) result ^= 0x0004;
96	96	if (atarigen_cpu_to_sound_ready) result ^= 0x0008;
r2864	r2865
103	103	static READ16_HANDLER( adc_r )
104	104	{
105	105	static int last_offset;
106		int result = input_port_read_indexed(machine, 2 + (last_offset & 3));
	106	static const char *adcnames[] = { "ADC0", "ADC1", "ADC2", "ADC3" };
	107	int result = input_port_read(machine, adcnames[last_offset & 3]);
	108
107	109	last_offset = offset;
108	110	return result;
109	111	}
r2864	r2865
242	244	*************************************/
243	245
244	246	static INPUT_PORTS_START( eprom )
245		PORT_START /* 26000 */
	247	PORT_START_TAG("260000") /* 260000 */
246	248	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
247	249	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
248	250	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
r2864	r2865
250	252	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
251	253	PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNUSED )
252	254
253		PORT_START /* 26010 */
	255	PORT_START_TAG("260010") /* 260010 */
254	256	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_VBLANK )
255	257	PORT_SERVICE( 0x0002, IP_ACTIVE_LOW )
256	258	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNUSED ) /* Input buffer full (@260030) */
r2864	r2865
263	265	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
264	266	PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNUSED )
265	267
266		PORT_START /* ADC0 @ 0x260020 */
	268	PORT_START_TAG("ADC0") /* ADC0 @ 0x260020 */
267	269	PORT_BIT( 0x00ff, 0x0080, IPT_AD_STICK_Y ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
268	270	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
269	271
270		PORT_START /* ADC1 @ 0x260022 */
	272	PORT_START_TAG("ADC1") /* ADC1 @ 0x260022 */
271	273	PORT_BIT( 0x00ff, 0x0080, IPT_AD_STICK_X ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(1)
272	274	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
273	275
274		PORT_START /* ADC0 @ 0x260024 */
	276	PORT_START_TAG("ADC2") /* ADC0 @ 0x260024 */
275	277	PORT_BIT( 0x00ff, 0x0080, IPT_AD_STICK_Y ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
276	278	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
277	279
278		PORT_START /* ADC1 @ 0x260026 */
	280	PORT_START_TAG("ADC3") /* ADC1 @ 0x260026 */
279	281	PORT_BIT( 0x00ff, 0x0080, IPT_AD_STICK_X ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(2)
280	282	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
281	283
r2864	r2865
284	286
285	287
286	288	static INPUT_PORTS_START( klaxp )
287		PORT_START /* 26000 */
	289	PORT_START_TAG("260000") /* 260000 */
288	290	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
289	291	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
290	292	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
r2864	r2865
295	297	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
296	298	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
297	299
298		PORT_START /* 26010 */
	300	PORT_START_TAG("260010") /* 260010 */
299	301	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_VBLANK )
300	302	PORT_SERVICE( 0x0002, IP_ACTIVE_LOW )
301	303	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNUSED ) /* Input buffer full (@260030) */
r2864	r2865
316	318
317	319
318	320	static INPUT_PORTS_START( guts )
319		PORT_START /* 26000 */
	321	PORT_START_TAG("260000") /* 260000 */
320	322	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
321	323	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
322	324	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
r2864	r2865
324	326	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
325	327	PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNUSED )
326	328
327		PORT_START /* 26010 */
	329	PORT_START_TAG("260010") /* 260010 */
328	330	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_VBLANK )
329	331	PORT_SERVICE( 0x0002, IP_ACTIVE_LOW )
330	332	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNUSED ) /* Input buffer full (@260030) */
r2864	r2865
337	339	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
338	340	PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNUSED )
339	341
340		PORT_START /* ADC0 @ 0x260020 */
	342	PORT_START_TAG("ADC0") /* ADC0 @ 0x260020 */
341	343	PORT_BIT( 0x00ff, 0x0080, IPT_AD_STICK_Y ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
342	344	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
343	345
344		PORT_START /* ADC1 @ 0x260022 */
	346	PORT_START_TAG("ADC1") /* ADC1 @ 0x260022 */
345	347	PORT_BIT( 0x00ff, 0x0080, IPT_AD_STICK_X ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) PORT_REVERSE
346	348	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
347	349
348		PORT_START /* ADC0 @ 0x260024 */
	350	PORT_START_TAG("ADC2") /* ADC0 @ 0x260024 */
349	351	PORT_BIT( 0x00ff, 0x0080, IPT_AD_STICK_Y ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
350	352	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
351	353
352		PORT_START /* ADC1 @ 0x260026 */
	354	PORT_START_TAG("ADC3") /* ADC1 @ 0x260026 */
353	355	PORT_BIT( 0x00ff, 0x0080, IPT_AD_STICK_X ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2) PORT_REVERSE
354	356	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
355	357
r2864	r2865
724	726	static DRIVER_INIT( eprom )
725	727	{
726	728	atarigen_eeprom_default = NULL;
727		atarijsa_init(machine, 1, 0x0002);
	729	atarijsa_init(machine, "260010", 0x0002);
728	730
729	731	/* install CPU synchronization handlers */
730	732	sync_data = memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x16cc00, 0x16cc01, 0, 0, sync_r, sync_w);
r2864	r2865
735	737	static DRIVER_INIT( klaxp )
736	738	{
737	739	atarigen_eeprom_default = NULL;
738		atarijsa_init(machine, 1, 0x0002);
	740	atarijsa_init(machine, "260010", 0x0002);
739	741	}
740	742
741	743
742	744	static DRIVER_INIT( guts )
743	745	{
744	746	atarigen_eeprom_default = NULL;
745		atarijsa_init(machine, 1, 0x0002);
	747	atarijsa_init(machine, "260010", 0x0002);
746	748	}
747	749
748	750

src/mame/drivers/cshooter.c
r2864	r2865
93	93
94	94	static UINT8 *mainram;
95	95
96		static void ar_coin_hack(void)
	96	static void ar_coin_hack(running_machine *machine)
97	97	{
98		if(input_port_read(Machine, "COIN") & 1)
	98	if(input_port_read(machine, "COIN") & 1)
99	99	{
100	100	if(coin_stat==0)
101	101	{
r2864	r2865
204	204	cpunum_set_input_line_and_vector(machine, 0, 0, HOLD_LINE, 0x10);
205	205
206	206	if(mainram!=NULL)
207		ar_coin_hack();
	207	ar_coin_hack(machine);
208	208
209	209	}
210	210

src/mame/drivers/fgoal.c
r2864	r2865
81	81	static TIMER_CALLBACK( interrupt_callback )
82	82	{
83	83	int scanline;
84		int coin = (input_port_read~~_indexed~~(machine, 1) & 2);
	84	int coin = (input_port_read(machine, "IN1") & 2);
85	85
86	86	cpunum_set_input_line(machine, 0, 0, ASSERT_LINE);
87	87
r2864	r2865
113	113
114	114	static READ8_HANDLER( fgoal_analog_r )
115	115	{
116		return input_port_read~~_indexed~~(machine, ~~2 +~~ fgoal_player); /* PCB can be jumpered to use a single dial */
	116	return input_port_read(machine, fgoal_player ? "PADDLE1" : "PADDLE0"); /* PCB can be jumpered to use a single dial */
117	117	}
118	118
119	119
120	120	static READ8_HANDLER( fgoal_switches_r )
121	121	{
122	122	if (video_screen_get_vpos(machine->primary_screen) & 0x80)
123		return input_port_read~~_indexed~~(machine, 1) \| 0x80;
	123	return input_port_read(machine, "IN1") \| 0x80;
124	124	else
125		return input_port_read~~_indexed~~(machine, 1);
	125	return input_port_read(machine, "IN1");
126	126	}
127	127
128	128
r2864	r2865
255	255
256	256	static INPUT_PORTS_START( fgoal )
257	257
258		PORT_START
	258	PORT_START_TAG("IN0")
259	259	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_TILT )
260	260	PORT_DIPNAME( 0x40, 0x40, "Display Coinage Settings" )
261	261	PORT_DIPSETTING( 0x00, DEF_STR( Off ))
r2864	r2865
280	280
281	281	/* extra credit score changes depending on player's performance */
282	282
283		PORT_START
	283	PORT_START_TAG("IN1")
284	284	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* 128V */
285	285	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Cabinet ))
286	286	PORT_DIPSETTING( 0x00, DEF_STR( Upright ))
r2864	r2865
300	300
301	301	/* game freezes when analog controls read $00 or $ff */
302	302
303		PORT_START
	303	PORT_START_TAG("PADDLE0")
304	304	PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(1, 254) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_CENTERDELTA(0) PORT_REVERSE PORT_PLAYER(1)
305	305
306		PORT_START
	306	PORT_START_TAG("PADDLE1")
307	307	PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(1, 254) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_CENTERDELTA(0) PORT_REVERSE PORT_PLAYER(2)
308	308
309	309	INPUT_PORTS_END

src/mame/drivers/hitme.c
r2864	r2865
68	68	static VIDEO_UPDATE(hitme)
69	69	{
70	70	/* the card width resistor comes from an input port, scaled to the range 0-25 kOhms */
71		double width_resist = input_port_read~~_indexed~~(screen->machine, 7) * 25000 / 100;
	71	double width_resist = input_port_read(screen->machine, "WIDTH") * 25000 / 100;
72	72	/* this triggers a oneshot for the following length of time */
73	73	double width_duration = 0.45 * 1000e-12 * width_resist;
74	74	/* the dot clock runs at the standard horizontal frequency * 320+16 clocks per scanline */
r2864	r2865
128	128
129	129	static UINT8 read_port_and_t0(running_machine *machine, int port)
130	130	{
131		UINT8 val = input_port_read_indexed(machine, port);
	131	static const char *portnames[] = { "IN0", "IN1", "IN2", "IN3" };
	132
	133	UINT8 val = input_port_read(machine, portnames[port]);
132	134	if (attotime_compare(timer_get_time(), timeout_time) > 0)
133	135	val ^= 0x80;
134	136	return val;
r2864	r2865
183	185	In fact, it is very important that our timing calculation timeout AFTER the sound
184	186	system's equivalent computation, or else we will hang notes.
185	187	*/
186		UINT8 raw_game_speed = input_port_read~~_indexed~~(machine, 6);
	188	UINT8 raw_game_speed = input_port_read(machine, "R3");
187	189	double resistance = raw_game_speed * 25000 / 100;
188	190	attotime duration = attotime_make(0, ATTOSECONDS_PER_SECOND * 0.45 * 6.8e-6 * resistance * (data+1));
189	191	timeout_time = attotime_add(timer_get_time(), duration);
r2864	r2865
223	225	AM_RANGE(0x1500, 0x15ff) AM_READ(hitme_port_1_r)
224	226	AM_RANGE(0x1600, 0x16ff) AM_READ(hitme_port_2_r)
225	227	AM_RANGE(0x1700, 0x17ff) AM_READ(hitme_port_3_r)
226		AM_RANGE(0x1800, 0x18ff) AM_READ(input_port_4_r)
227		AM_RANGE(0x1900, 0x19ff) AM_READ(input_port_5_r)
	228	AM_RANGE(0x1800, 0x18ff) AM_READ_PORT("IN4")
	229	AM_RANGE(0x1900, 0x19ff) AM_READ_PORT("IN5")
228	230	AM_RANGE(0x1d00, 0x1dff) AM_WRITE(output_port_0_w)
229	231	AM_RANGE(0x1e00, 0x1fff) AM_WRITE(output_port_1_w)
230	232	ADDRESS_MAP_END
r2864	r2865
235	237	AM_RANGE(0x15, 0x15) AM_READ(hitme_port_1_r)
236	238	AM_RANGE(0x16, 0x16) AM_READ(hitme_port_2_r)
237	239	AM_RANGE(0x17, 0x17) AM_READ(hitme_port_3_r)
238		AM_RANGE(0x18, 0x18) AM_READ(input_port_4_r)
239		AM_RANGE(0x19, 0x19) AM_READ(input_port_5_r)
	240	AM_RANGE(0x18, 0x18) AM_READ_PORT("IN4")
	241	AM_RANGE(0x19, 0x19) AM_READ_PORT("IN5")
240	242	AM_RANGE(0x1d, 0x1d) AM_WRITE(output_port_0_w)
241	243	AM_RANGE(0x1e, 0x1f) AM_WRITE(output_port_1_w)
242	244	ADDRESS_MAP_END
r2864	r2865
356	358	*************************************/
357	359
358	360	static INPUT_PORTS_START( hitme )
359		PORT_START
	361	PORT_START_TAG("IN0")
360	362	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) /* Start button */
361	363	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) /* Always high */
362	364	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Hblank */
r2864	r2865
366	368	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) /* P1 Bet button */
367	369	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Time out counter (TO) /
368	370
369		PORT_START
	371	PORT_START_TAG("IN1")
370	372	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
371	373	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) /* Always high */
372	374	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) /* Aux 2 dipswitch - Unused */
r2864	r2865
376	378	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) /* P2 Bet button */
377	379	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Time out counter (TO) /
378	380
379		PORT_START
	381	PORT_START_TAG("IN2")
380	382	PORT_DIPNAME( 0x01, 0x00, "Extra Hand On Natural" ) /* Aux 1 dipswitch */
381	383	PORT_DIPSETTING( 0x00, DEF_STR ( Off ) )
382	384	PORT_DIPSETTING( 0x01, DEF_STR ( On ) )
r2864	r2865
388	390	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3) /* P3 Bet button */
389	391	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Time out counter (TO) /
390	392
391		PORT_START
	393	PORT_START_TAG("IN3")
392	394	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* Time out counter (TOC1) */
393	395	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) /* Always high */
394	396	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) /* Aux 2 dipswitch - Unused*/
r2864	r2865
398	400	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4) /* P4 Bet button */
399	401	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Time out counter (TO) /
400	402
401		PORT_START
	403	PORT_START_TAG("IN4")
402	404	PORT_DIPNAME( 0x07, 0x07, "Number of Chips" )
403	405	PORT_DIPSETTING( 0x00, "5 Chips" )
404	406	PORT_DIPSETTING( 0x01, "10 Chips" )
r2864	r2865
410	412	PORT_DIPSETTING( 0x07, "40 Chips" )
411	413	PORT_BIT( 0xf8, IP_ACTIVE_HIGH, IPT_UNUSED )
412	414
413		PORT_START
	415	PORT_START_TAG("IN5")
414	416	PORT_DIPNAME( 0x07, 0x00, "Number of Hands" )
415	417	PORT_DIPSETTING( 0x00, "5 Hands" )
416	418	PORT_DIPSETTING( 0x01, "10 Hands" )
r2864	r2865
427	429	PORT_ADJUSTER(30, "Game Speed")
428	430
429	431	/* this is actually a variable resistor */
430		PORT_START
	432	PORT_START_TAG("WIDTH")
431	433	PORT_ADJUSTER(50, "Card Width")
432	434	INPUT_PORTS_END
433	435
434	436
435	437	static INPUT_PORTS_START( barricad )
436		PORT_START
	438	PORT_START_TAG("IN0")
437	439	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) /* Start button */
438	440	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) /* Always high */
439	441	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Hblank */
r2864	r2865
443	445	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
444	446	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Time out counter (TO) /
445	447
446		PORT_START
	448	PORT_START_TAG("IN1")
447	449	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
448	450	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) /* Always high */
449	451	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) /* Aux 2 dipswitch - Unused */
r2864	r2865
453	455	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(3)
454	456	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Time out counter (TO) /
455	457
456		PORT_START
	458	PORT_START_TAG("IN2")
457	459	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* ??? */
458	460	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) /* Always high */
459	461	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Hblank */
r2864	r2865
463	465	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(4)
464	466	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) /* Time out counter (TO) /
465	467
466		PORT_START
	468	PORT_START_TAG("IN3")
467	469	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* Time out counter (TOC1) */
468	470	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* Always high */
469	471	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* Aux 2 dipswitch - Unused*/
r2864	r2865
478	480	same dipswitch as hitme's chips, and speed is hitme's hands. The flyer
479	481	says 1-7 points per games, but it really can go to 8. */
480	482
481		PORT_START
	483	PORT_START_TAG("IN4")
482	484	PORT_DIPNAME( 0x07, 0x07, "Points Per Game" )
483	485	PORT_DIPSETTING( 0x00, "1 Point" )
484	486	PORT_DIPSETTING( 0x01, "2 Points" )
r2864	r2865
492	494	/* These are like lives, you lose a point if you crash. The last person with
493	495	points wins the game. */
494	496
495		PORT_START
	497	PORT_START_TAG("IN5")
496	498	PORT_DIPNAME( 0x07, 0x00, "Game Speed" )
497	499	PORT_DIPSETTING( 0x00, "Fast Fast" )
498	500	PORT_DIPSETTING( 0x01, "7" )

src/mame/drivers/rampart.c
r2864	r2865
536	536
537	537	atarigen_eeprom_default = compressed_default_eeprom;
538	538	memcpy(&rom[0x140000], &rom[0x40000], 0x8000);
539		atarigen_slapstic_init(0, 0x140000, 0x438000, 118);
	539	atarigen_slapstic_init(machine, 0, 0x140000, 0x438000, 118);
540	540	}
541	541
542	542

src/mame/drivers/segaxbd.c
r2864	r2865
61	61	*************************************/
62	62
63	63	extern void fd1094_machine_init(void);
64		extern void fd1094_driver_init(void (set_decrypted)(UINT8 ));
	64	extern void fd1094_driver_init(running_machine machine, void (set_decrypted)(UINT8 *));
65	65
66	66
67	67
r2864	r2865
71	71	*
72	72	*************************************/
73	73
74		static void xboard_generic_init(void)
	74	static void xboard_generic_init(running_machine *machine)
75	75	{
76	76	/* init the FD1094 */
77		fd1094_driver_init(NULL);
	77	fd1094_driver_init(machine, NULL);
78	78
79	79	/* set the default road priority */
80	80	xboard_set_road_priority(1);
r2864	r2865
1876	1876	ROM_LOAD32_BYTE( "mpr12418.96", 0x100001, 0x20000, CRC(ed1a0f2b) SHA1(1aa87292ca0465fa129d6be81d95dbb77332ecab) )
1877	1877	ROM_LOAD32_BYTE( "mpr12419.100", 0x100002, 0x20000, CRC(ce4568cb) SHA1(1ed66e74ce94d41593b498827d9cc243f775d4ba) )
1878	1878	ROM_LOAD32_BYTE( "mpr12420.104", 0x100003, 0x20000, CRC(679442eb) SHA1(f88ef0219497f955d8db6783f3636dad52928f46) )
1879		ROM_LOAD32_BYTE( "epr12413.93", 0x180000, 0x20000, CRC(2f1693df) SHA1(ba1e654a1b5fae661b0dae4a8ed04ff50fb546a2) )
1880		ROM_LOAD32_BYTE( "epr12414.97", 0x180001, 0x20000, CRC(c78f3d45) SHA1(665750907ed11c89c2ea5c410eac2808445131ae) )
	1879	ROM_LOAD32_BYTE( "epr12413.93", 0x180000, 0x20000, CRC(2f1693df) SHA1(ba1e654a1b5fae661b0dae4a8ed04ff50fb546a2) )
	1880	ROM_LOAD32_BYTE( "epr12414.97", 0x180001, 0x20000, CRC(c78f3d45) SHA1(665750907ed11c89c2ea5c410eac2808445131ae) )
1881	1881	ROM_LOAD32_BYTE( "epr12415.101", 0x180002, 0x20000, CRC(6080e9ed) SHA1(eb1b871453f76e6a65d20fa9d4bddc1c9f940b4d) )
1882	1882	ROM_LOAD32_BYTE( "epr12416.105", 0x180003, 0x20000, CRC(6f1f2769) SHA1(d00d26cd1052d4b46c432b6b69cb2d83179d52a6) )
1883	1883
r2864	r2865
1913	1913	*/
1914	1914	ROM_START( smgpu )
1915	1915	ROM_REGION( 0x80000, REGION_CPU1, 0 ) /* 68000 code */
1916		ROM_LOAD16_BYTE( "ep12561c.58", 0x00000, 0x20000, CRC(a5b0f3fe) SHA1(17103e56f822fdb52e72f597c01415ed375aa102) )
1917		ROM_LOAD16_BYTE( "ep12562c.63", 0x00001, 0x20000, CRC(799e55f4) SHA1(2e02cdc63bda47b087c81021018287cfa961c083) )
	1916	ROM_LOAD16_BYTE( "epr12561c.58", 0x00000, 0x20000, CRC(a5b0f3fe) SHA1(17103e56f822fdb52e72f597c01415ed375aa102) )
	1917	ROM_LOAD16_BYTE( "epr12562c.63", 0x00001, 0x20000, CRC(799e55f4) SHA1(2e02cdc63bda47b087c81021018287cfa961c083) )
1918	1918
1919	1919	ROM_REGION( 0x2000, REGION_USER1, 0 ) /* decryption key */
1920	1920	ROM_LOAD( "317-0125a.key", 0x0000, 0x2000, CRC(3ecdb120) SHA1(c484198e4509d79214e78d4a47e9a7e339f7a2ed) )
r2864	r2865
1967	1967	*/
1968	1968	ROM_START( smgpu1 )
1969	1969	ROM_REGION( 0x80000, REGION_CPU1, 0 ) /* 68000 code */
1970		ROM_LOAD16_BYTE( "ep12561b.63", 0x00000, 0x20000, CRC(80a32655) SHA1(fe1ffa8af9f1ca175ba90b24a0853329b08d19af) )
1971		ROM_LOAD16_BYTE( "ep12562b.58", 0x00001, 0x20000, CRC(d525f2a8) SHA1(f3241e11485c7428cd9f081ec6768fda39ae3250) )
	1970	ROM_LOAD16_BYTE( "epr12561b.58", 0x00000, 0x20000, CRC(80a32655) SHA1(fe1ffa8af9f1ca175ba90b24a0853329b08d19af) )
	1971	ROM_LOAD16_BYTE( "epr12562b.63", 0x00001, 0x20000, CRC(d525f2a8) SHA1(f3241e11485c7428cd9f081ec6768fda39ae3250) )
1972	1972
1973	1973	ROM_REGION( 0x2000, REGION_USER1, 0 ) /* decryption key */
1974	1974	ROM_LOAD( "317-0125a.key", 0x0000, 0x2000, CRC(3ecdb120) SHA1(c484198e4509d79214e78d4a47e9a7e339f7a2ed) )
r2864	r2865
2411	2411
2412	2412	static DRIVER_INIT( generic_xboard )
2413	2413	{
2414		xboard_generic_init();
	2414	xboard_generic_init(machine);
2415	2415	}
2416	2416
2417	2417
r2864	r2865
2424	2424
2425	2425	static DRIVER_INIT( aburner2 )
2426	2426	{
2427		xboard_generic_init();
	2427	xboard_generic_init(machine);
2428	2428	xboard_set_road_priority(0);
2429	2429
2430	2430	memory_install_write16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x140006, 0x140007, 0, 0x00fff0, aburner2_iochip_0_D_w);
r2864	r2865
2433	2433
2434	2434	static DRIVER_INIT( aburner )
2435	2435	{
2436		xboard_generic_init();
	2436	xboard_generic_init(machine);
2437	2437	xboard_set_road_priority(0);
2438	2438	}
2439	2439
2440	2440
2441	2441	static DRIVER_INIT( loffire )
2442	2442	{
2443		xboard_generic_init();
	2443	xboard_generic_init(machine);
2444	2444	adc_reverse[1] = adc_reverse[3] = 1;
2445	2445
2446	2446	/* install extra synchronization on core shared memory */
r2864	r2865
2450	2450
2451	2451	static DRIVER_INIT( smgp )
2452	2452	{
2453		xboard_generic_init();
	2453	xboard_generic_init(machine);
2454	2454	memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x2f0000, 0x2f3fff, 0, 0, smgp_excs_r, smgp_excs_w);
2455	2455	}
2456	2456
2457	2457
2458	2458	static DRIVER_INIT( gprider )
2459	2459	{
2460		xboard_generic_init();
	2460	xboard_generic_init(machine);
2461	2461	gprider_hack = 1;
2462	2462	}
2463	2463

src/mame/drivers/hornet.c
r2864	r2865
308	308	*/
309	309
310	310	#include "driver.h"
311		#include "deprecat.h"
312	311	#include "cpu/powerpc/ppc.h"
313	312	#include "cpu/sharc/sharc.h"
314	313	#include "machine/konppc.h"
r2864	r2865
463	462	}
464	463	}
465	464
466		static void K037122_tile_draw(int chip, bitmap_t bitmap, const rectangle cliprect)
	465	static void K037122_tile_draw(running_machine machine, int chip, bitmap_t bitmap, const rectangle *cliprect)
467	466	{
468		const rectangle *visarea = video_screen_get_visible_area(Machine->primary_screen);
	467	const rectangle *visarea = video_screen_get_visible_area(machine->primary_screen);
469	468
470	469	if (K037122_reg[chip][0xc] & 0x10000)
471	470	{
r2864	r2865
648	647	voodoo_update(0, bitmap, cliprect);
649	648
650	649	K037122_tile_update(screen->machine, 0);
651		K037122_tile_draw(0, bitmap, cliprect);
	650	K037122_tile_draw(screen->machine, 0, bitmap, cliprect);
652	651
653	652	draw_7segment_led(bitmap, 3, 3, led_reg0);
654	653	draw_7segment_led(bitmap, 9, 3, led_reg1);
r2864	r2865
666	665
667	666	/* TODO: tilemaps per screen */
668	667	K037122_tile_update(screen->machine, 0);
669		K037122_tile_draw(0, bitmap, cliprect);
	668	K037122_tile_draw(screen->machine, 0, bitmap, cliprect);
670	669	}
671	670	else if (screen == right_screen)
672	671	{
r2864	r2865
674	673
675	674	/* TODO: tilemaps per screen */
676	675	K037122_tile_update(screen->machine, 1);
677		K037122_tile_draw(1, bitmap, cliprect);
	676	K037122_tile_draw(screen->machine, 1, bitmap, cliprect);
678	677	}
679	678
680	679	draw_7segment_led(bitmap, 3, 3, led_reg0);
r2864	r2865
688	687	static READ8_HANDLER( sysreg_r )
689	688	{
690	689	UINT8 r = 0;
	690	static const char *portnames[] = { "IN0", "IN1", "IN2" };
691	691
692	692	switch (offset)
693	693	{
694	694	case 0:
695	695	case 1:
696	696	case 2:
697		r = input_port_read~~_indexed~~(machine, offset);
	697	r = input_port_read(machine, portnames[offset]);
698	698	break;
699	699
700	700	case 3:
r2864	r2865
702	702	break;
703	703
704	704	case 4:
705		r = input_port_read~~_indexed~~(machine, 3);
	705	r = input_port_read(machine, "DSW");
706	706	break;
707	707	}
708	708	return r;
r2864	r2865
837	837	/*****************************************************************************/
838	838
839	839	static INPUT_PORTS_START( hornet )
840		PORT_START
	840	PORT_START_TAG("IN0")
841	841	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
842	842	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
843	843	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
847	847	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
848	848	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
849	849
850		PORT_START
	850	PORT_START_TAG("IN1")
851	851	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
852	852	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
853	853	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
857	857	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
858	858	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
859	859
860		PORT_START
	860	PORT_START_TAG("IN2")
861	861	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
862	862	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
863	863	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Service Button") PORT_CODE(KEYCODE_7)
864	864	PORT_SERVICE_NO_TOGGLE( 0x10, IP_ACTIVE_LOW )
865	865	PORT_BIT( 0x0f, IP_ACTIVE_HIGH, IPT_UNUSED )
866	866
867		PORT_START
	867	PORT_START_TAG("DSW")
868	868	PORT_DIPNAME( 0x80, 0x00, "Test Mode" )
869	869	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
870	870	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
r2864	r2865
889	889	PORT_DIPNAME( 0x01, 0x01, "Monitor Type" )
890	890	PORT_DIPSETTING( 0x01, "24KHz" )
891	891	PORT_DIPSETTING( 0x00, "15KHz" )
892
893	892	INPUT_PORTS_END
894	893
895	894	static INPUT_PORTS_START( sscope )
896		PORT_START
	895	PORT_START_TAG("IN0")
897	896	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
898	897	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
899	898	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
902	901	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) // Gun trigger
903	902	PORT_BIT( 0x03, IP_ACTIVE_LOW, IPT_UNUSED )
904	903
905		PORT_START
	904	PORT_START_TAG("IN1")
906	905	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
907	906
908		PORT_START
	907	PORT_START_TAG("IN2")
909	908	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
910	909	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
911	910	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Service Button") PORT_CODE(KEYCODE_7)
912	911	PORT_SERVICE_NO_TOGGLE( 0x10, IP_ACTIVE_LOW )
913	912	PORT_BIT( 0x0f, IP_ACTIVE_HIGH, IPT_UNUSED )
914	913
915		PORT_START
	914	PORT_START_TAG("DSW")
916	915	PORT_DIPNAME( 0x80, 0x00, "Test Mode" )
917	916	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
918	917	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
r2864	r2865
937	936	PORT_DIPNAME( 0x01, 0x01, "Monitor Type" )
938	937	PORT_DIPSETTING( 0x01, "24KHz" )
939	938	PORT_DIPSETTING( 0x00, "15KHz" )
940
941	939	INPUT_PORTS_END
942	940
943	941	static const struct RF5C400interface rf5c400_interface =

src/mame/drivers/ddragon3.c
r2864	r2865
44	44	extern VIDEO_UPDATE( ddragon3 );
45	45	extern VIDEO_UPDATE( ctribe );
46	46
47		/* Read/Write Handlers */
	47	/*************************************
	48	*
	49	* Read/Write Handlers
	50	*
	51	*************************************/
48	52
49	53	static WRITE8_HANDLER( oki_bankswitch_w )
50	54	{
r2864	r2865
89	93	}
90	94	}
91	95
92		/* Memory Maps */
	96	/*************************************
	97	*
	98	* Memory Maps
	99	*
	100	*************************************/
93	101
94	102	static ADDRESS_MAP_START( readmem, ADDRESS_SPACE_PROGRAM, 16 )
95	103	AM_RANGE(0x000000, 0x07ffff) AM_READ(SMH_ROM)
r2864	r2865
199	207	AM_RANGE(0x9800, 0x9800) AM_WRITE(OKIM6295_data_0_w)
200	208	ADDRESS_MAP_END
201	209
202		/* Input Ports */
	210	/*************************************
	211	*
	212	* Game-specific port definitions
	213	*
	214	*************************************/
203	215
204	216	static INPUT_PORTS_START( ddragon3 )
205		PORT_START_TAG("IN1")
	217	PORT_START_TAG("IN0")
206	218	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
207	219	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
208	220	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
r2864	r2865
220	232	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
221	233	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
222	234
223		PORT_START
	235	PORT_START_TAG("IN1")
224	236	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
225	237	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
226	238	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )
227	239	PORT_BIT( 0x00f8, IP_ACTIVE_LOW, IPT_UNUSED )
228	240	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
229	241
230		PORT_START // DSW1&2
231		PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Coinage ) )
	242	PORT_START_TAG("IN2")
	243	PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2")
232	244	PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
233	245	PORT_DIPSETTING( 0x0001, DEF_STR( 2C_1C ) )
234	246	PORT_DIPSETTING( 0x0003, DEF_STR( 1C_1C ) )
235	247	PORT_DIPSETTING( 0x0002, DEF_STR( 1C_2C ) )
236		PORT_BIT( 0x000c, IP_ACTIVE_LOW, IPT_UNUSED )
237		PORT_DIPNAME( 0x0010, 0x0010, "Continue Discount" )
	248	PORT_DIPUNUSED_DIPLOC( 0x0004, 0x0004, "SW1:3" )
	249	PORT_DIPUNUSED_DIPLOC( 0x0008, 0x0008, "SW1:4" )
	250	PORT_DIPNAME( 0x0010, 0x0010, "Continue Discount" ) PORT_DIPLOCATION("SW1:5")
238	251	PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
239	252	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
240		PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Demo_Sounds ) )
	253	PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
241	254	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
242	255	PORT_DIPSETTING( 0x0020, DEF_STR( On ) )
243		PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Flip_Screen ) )
	256	PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:7")
244	257	PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
245	258	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
246		PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED )
247		PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Difficulty ) )
	259	PORT_DIPUNUSED_DIPLOC( 0x0080, 0x0080, "SW1:8" )
	260	PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
248	261	PORT_DIPSETTING( 0x0200, DEF_STR( Easy ) )
249	262	PORT_DIPSETTING( 0x0300, DEF_STR( Normal ) )
250	263	PORT_DIPSETTING( 0x0100, DEF_STR( Hard ) )
251	264	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
252		PORT_DIPNAME( 0x0400, 0x0400, "Player Vs. Player Damage" )
	265	PORT_DIPNAME( 0x0400, 0x0400, "Player Vs. Player Damage" ) PORT_DIPLOCATION("SW2:3")
253	266	PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
254	267	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
255		PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNUSED )
256		PORT_SERVICE( 0x1000, IP_ACTIVE_LOW )
257		PORT_DIPNAME( 0x2000, 0x2000, "Stage Clear Energy" )
	268	PORT_DIPUNUSED_DIPLOC( 0x0800, 0x0800, "SW2:4" )
	269	PORT_SERVICE_DIPLOC( 0x1000, IP_ACTIVE_LOW, "SW2:5" )
	270	PORT_DIPNAME( 0x2000, 0x2000, "Stage Clear Energy" ) PORT_DIPLOCATION("SW2:6")
258	271	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
259	272	PORT_DIPSETTING( 0x2000, "50" )
260		PORT_DIPNAME( 0x4000, 0x4000, "Starting Energy" )
	273	PORT_DIPNAME( 0x4000, 0x4000, "Starting Energy" ) PORT_DIPLOCATION("SW2:7")
261	274	PORT_DIPSETTING( 0x0000, "200" )
262	275	PORT_DIPSETTING( 0x4000, "230" )
263		PORT_DIPNAME( 0x8000, 0x0000, DEF_STR( Players ) )
	276	PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Players ) ) PORT_DIPLOCATION("SW2:8")
264	277	PORT_DIPSETTING( 0x8000, "2" )
265	278	PORT_DIPSETTING( 0x0000, "3" )
266	279
r2864	r2865
276	289	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
277	290	INPUT_PORTS_END
278	291
279		static INPUT_PORTS_START( ddrago3b )
280		PORT_START
	292	static INPUT_PORTS_START( ctribe )
	293	PORT_START_TAG("IN0")
281	294	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
282	295	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
283	296	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
284	297	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
285	298	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) // punch
286	299	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) // jump
287		PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) // kick
	300	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) // Unused in game but work on input test
288	301	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START1 )
289	302
290	303	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_COIN1 )
291	304	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_COIN2 )
292	305	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_SERVICE1 )
293		PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNUSED )
294		PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Flip_Screen ) )
	306	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_VBLANK )
	307	PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:7")
295	308	PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
296	309	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
297	310	PORT_BIT( 0xe000, IP_ACTIVE_LOW, IPT_UNUSED )
298	311
299		PORT_START
	312	PORT_START_TAG("IN1")
300	313	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
301	314	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
302	315	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
306	319	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
307	320	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START2 )
308	321
309		PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Coinage ) )
	322	PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2")
310	323	PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
311	324	PORT_DIPSETTING( 0x0100, DEF_STR( 2C_1C ) )
312	325	PORT_DIPSETTING( 0x0300, DEF_STR( 1C_1C ) )
313	326	PORT_DIPSETTING( 0x0200, DEF_STR( 1C_2C ) )
314		PORT_BIT( 0x0c00, IP_ACTIVE_LOW, IPT_UNUSED )
315		PORT_DIPNAME( 0x1000, 0x1000, "Continue Discount" )
	327	PORT_DIPUNUSED_DIPLOC( 0x0400, 0x0400, "SW1:3" )
	328	PORT_DIPUNUSED_DIPLOC( 0x0800, 0x0800, "SW1:4" )
	329	PORT_DIPNAME( 0x1000, 0x1000, "Continue Discount" ) PORT_DIPLOCATION("SW1:5")
316	330	PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
317	331	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
318		PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Demo_Sounds ) )
	332	PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
319	333	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
320	334	PORT_DIPSETTING( 0x2000, DEF_STR( On ) )
321		PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNUSED )
	335	PORT_DIPUNUSED_DIPLOC( 0x4000, 0x4000, "SW1:8" )
	336	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED )
322	337
323		PORT_START
	338	PORT_START_TAG("IN2")
324	339	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
325	340	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
326	341	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
r2864	r2865
330	345	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
331	346	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START3 )
332	347
333		PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Difficulty ) )
	348	PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
334	349	PORT_DIPSETTING( 0x0200, DEF_STR( Easy ) )
335	350	PORT_DIPSETTING( 0x0300, DEF_STR( Normal ) )
336	351	PORT_DIPSETTING( 0x0100, DEF_STR( Hard ) )
337	352	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
338		PORT_DIPNAME( 0x0400, 0x0400, "Player Vs. Player Damage" )
339		PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
340		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
341		PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNUSED )
342		PORT_SERVICE( 0x1000, IP_ACTIVE_LOW )
343		PORT_DIPNAME( 0x2000, 0x2000, "Stage Clear Energy" )
344		PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
345		PORT_DIPSETTING( 0x2000, "50" )
	353	PORT_DIPNAME( 0x0400, 0x0400, "Timer Speed" ) PORT_DIPLOCATION("SW2:3")
	354	PORT_DIPSETTING( 0x0400, DEF_STR( Normal ) )
	355	PORT_DIPSETTING( 0x0000, "Fast" )
	356	PORT_DIPUNUSED_DIPLOC( 0x0800, 0x0800, "SW2:4" )
	357	PORT_SERVICE_DIPLOC( 0x1000, IP_ACTIVE_LOW, "SW2:5" )
	358	PORT_DIPNAME( 0x2000, 0x2000, "Stage Clear Energy" ) PORT_CONDITION("IN3",0x0100,PORTCOND_EQUALS,0x0100) PORT_DIPLOCATION("SW2:6")
	359	PORT_DIPSETTING( 0x2000, "0" )
	360	PORT_DIPSETTING( 0x0000, "50" )
	361	PORT_DIPNAME( 0x2000, 0x2000, "Stage Clear Energy" ) PORT_CONDITION("IN3",0x0100,PORTCOND_EQUALS,0x0000) PORT_DIPLOCATION("SW2:6")
	362	PORT_DIPSETTING( 0x2000, "100" )
	363	PORT_DIPSETTING( 0x0000, "150" )
346	364	PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNUSED )
347	365
348		PORT_START
	366	PORT_START_TAG("IN3")
349	367	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
350
351		PORT_DIPNAME( 0x0100, 0x0100, "Starting Energy" )
352		PORT_DIPSETTING( 0x0000, "200" )
353		PORT_DIPSETTING( 0x0100, "230" )
354		PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Players ) )
355		PORT_DIPSETTING( 0x0200, "2" )
356		PORT_DIPSETTING( 0x0000, "3" )
357		PORT_BIT( 0xfc00, IP_ACTIVE_LOW, IPT_UNUSED )
358		INPUT_PORTS_END
359
360		static INPUT_PORTS_START( ctribe )
361		PORT_START
362		PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
363		PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
364		PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
365		PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
366		PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) // punch
367		PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) // jump
368		PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNUSED )
369		PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START1 )
370
371		PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_COIN1 )
372		PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_COIN2 )
373		PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_SERVICE1 )
374		PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_VBLANK )
375		PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:7")
376		PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
	368	PORT_DIPNAME( 0x0100, 0x0100, "More Stage Clear Energy" ) PORT_DIPLOCATION("SW2:7")
	369	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
377	370	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
378		PORT_BIT( 0xe000, IP_ACTIVE_LOW, IPT_UNUSED )
379
380		PORT_START
381		PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
382		PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
383		PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
384		PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
385		PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
386		PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
387		PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNUSED )
388		PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START2 )
389
390		PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2")
391		PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
392		PORT_DIPSETTING( 0x0100, DEF_STR( 2C_1C ) )
393		PORT_DIPSETTING( 0x0300, DEF_STR( 1C_1C ) )
394		PORT_DIPSETTING( 0x0200, DEF_STR( 1C_2C ) )
395		PORT_BIT( 0x0c00, IP_ACTIVE_LOW, IPT_UNUSED )
396		PORT_DIPNAME( 0x1000, 0x1000, "Continue Discount" ) PORT_DIPLOCATION("SW1:5")
397		PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
398		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
399		PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
400		PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
401		PORT_DIPSETTING( 0x2000, DEF_STR( On ) )
	371	PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Players ) ) PORT_DIPLOCATION("SW2:8")
	372	PORT_DIPSETTING( 0x0200, "2" )
	373	PORT_DIPSETTING( 0x0000, "3" )
402	374	PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNUSED )
	375	INPUT_PORTS_END
403	376
404		PORT_START
405		PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
406		PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
407		PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
408		PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
409		PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
410		PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
411		PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNUSED )
412		PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START3 )
	377	static INPUT_PORTS_START( ddrago3b )
	378	PORT_INCLUDE( ctribe )
413	379
414		PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
415		PORT_DIPSETTING( 0x0200, DEF_STR( Easy ) )
416		PORT_DIPSETTING( 0x0300, DEF_STR( Normal ) )
417		PORT_DIPSETTING( 0x0100, "Less than Difficult" )
418		PORT_DIPSETTING( 0x0000, "Difficult" )
419		PORT_DIPNAME( 0x0400, 0x0400, "Timer Speed" ) PORT_DIPLOCATION("SW2:3")
420		PORT_DIPSETTING( 0x0400, DEF_STR( Normal ) )
421		PORT_DIPSETTING( 0x0000, "Fast" )
	380	PORT_MODIFY("IN0")
422	381	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNUSED )
423		PORT_DIPNAME( 0x1000, 0x1000, "Test Mode" ) PORT_DIPLOCATION("SW2:5")
424		PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
	382
	383	PORT_MODIFY("IN2")
	384	PORT_DIPNAME( 0x0400, 0x0400, "Player Vs. Player Damage" ) PORT_DIPLOCATION("SW2:3")
	385	PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
425	386	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
426		PORT_DIPNAME( 0x6000, 0x6000, "Stage Clear Energy" ) PORT_DIPLOCATION("SW2:6,7")
427		PORT_DIPSETTING( 0x6000, "0" )
428		PORT_DIPSETTING( 0x4000, "50" )
429		PORT_DIPSETTING( 0x2000, "100" ) /* According to manual but doesn't work on real pcb. */
430		PORT_DIPSETTING( 0x0000, "150" ) /* According to manual but doesn't work on real pcb. */
431		PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED )
432	387
433		PORT_START
434		PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
435		PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNUSED )
436		PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Players ) ) PORT_DIPLOCATION("SW2:8")
437		PORT_DIPSETTING( 0x0200, "2" )
438		PORT_DIPSETTING( 0x0000, "3" )
439		PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNUSED )
	388	PORT_MODIFY("IN3")
	389	PORT_DIPNAME( 0x0100, 0x0100, "Starting Energy" ) PORT_DIPLOCATION("SW2:7")
	390	PORT_DIPSETTING( 0x0000, "200" )
	391	PORT_DIPSETTING( 0x0100, "230" )
440	392	INPUT_PORTS_END
441	393
442		/* Graphics Layouts */
	394	/*************************************
	395	*
	396	* Graphics Layouts
	397	*
	398	*************************************/
443	399
444	400	static const gfx_layout tile_layout =
445	401	{
r2864	r2865
466	422	328 / every tile takes 32 consecutive bytes */
467	423	};
468	424
469		/* Graphics Decode Info */
	425	/*************************************
	426	*
	427	* Graphics Decode Info
	428	*
	429	*************************************/
470	430
471	431	static GFXDECODE_START( ddragon3 )
472	432	GFXDECODE_ENTRY( REGION_GFX1, 0, tile_layout, 256, 32 )
473	433	GFXDECODE_ENTRY( REGION_GFX2, 0, sprite_layout, 0, 16 )
474	434	GFXDECODE_END
475	435
476		/* Sound Interfaces */
	436	/*************************************
	437	*
	438	* Sound Interfaces
	439	*
	440	*************************************/
477	441
478	442	static void dd3_ymirq_handler(running_machine *machine, int irq)
479	443	{
r2864	r2865
485	449	dd3_ymirq_handler
486	450	};
487	451
488		/* Interrupt Generators */
	452	/*************************************
	453	*
	454	* Interrupt Generators
	455	*
	456	*************************************/
489	457
490	458	static INTERRUPT_GEN( ddragon3_cpu_interrupt ) { /* 6:0x177e - 5:0x176a */
491	459	if( cpu_getiloops() == 0 ){
r2864	r2865
496	464	}
497	465	}
498	466
499		/* Machine Drivers */
	467	/*************************************
	468	*
	469	* Machine driver
	470	*
	471	*************************************/
500	472
501	473	static MACHINE_DRIVER_START( ddragon3 )
502	474	/* basic machine hardware */
r2864	r2865
504	476	MDRV_CPU_PROGRAM_MAP(readmem, writemem)
505	477	MDRV_CPU_VBLANK_INT_HACK(ddragon3_cpu_interrupt, 2)
506	478
507		MDRV_CPU_ADD_TAG("audio", Z80, 3579545) // Guess
	479	MDRV_CPU_ADD_TAG("audio", Z80, 3579545) // Guess (confirmed on bootleg)
508	480	/* audio CPU */
509	481	MDRV_CPU_PROGRAM_MAP(readmem_sound, writemem_sound)
510	482
511	483	/* video hardware */
512	484	MDRV_SCREEN_ADD("main", RASTER)
513		MDRV_SCREEN_REFRESH_RATE(60)
	485	MDRV_SCREEN_REFRESH_RATE(57)
514	486	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
515	487	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
516	488	MDRV_SCREEN_SIZE(408, 328)
r2864	r2865
525	497	/* sound hardware */
526	498	MDRV_SPEAKER_STANDARD_STEREO("left", "right")
527	499
528		MDRV_SOUND_ADD(YM2151, 3579545)
	500	MDRV_SOUND_ADD_TAG("ym2151", YM2151, 3579545) /* music */
529	501	MDRV_SOUND_CONFIG(ym2151_interface)
530		MDRV_SOUND_ROUTE(0, "left", 1.00) /* music */
531		MDRV_SOUND_ROUTE(1, "right", 1.00)
	502	MDRV_SOUND_ROUTE(0, "left", 0.50)
	503	MDRV_SOUND_ROUTE(1, "right", 0.50)
532	504
533		MDRV_SOUND_ADD(OKIM6295, 1~~122~~000)
	505	MDRV_SOUND_ADD_TAG("oki", OKIM6295, 1000000) /* sound fx */
534	506	MDRV_SOUND_CONFIG(okim6295_interface_region_1_pin7high) // clock frequency & pin 7 not verified
535		MDRV_SOUND_ROUTE(ALL_OUTPUTS, "left", 1.00) /* sound fx */
536		MDRV_SOUND_ROUTE(ALL_OUTPUTS, "right", 1.00)
	507	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "left", 1.50)
	508	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "right", 1.50)
537	509	MACHINE_DRIVER_END
538	510
539	511	static MACHINE_DRIVER_START( ddrago3b )
r2864	r2865
556	528	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
557	529
558	530	MDRV_VIDEO_UPDATE(ctribe)
	531
	532	MDRV_SOUND_MODIFY("ym2151")
	533	MDRV_SOUND_ROUTE(0, "left", 1.20)
	534	MDRV_SOUND_ROUTE(1, "right", 1.20)
	535
	536	MDRV_SOUND_MODIFY("oki")
	537	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "left", 0.80)
	538	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "right", 0.80)
559	539	MACHINE_DRIVER_END
560	540
561		/* ROMs */
	541	/*************************************
	542	*
	543	* ROM definition(s)
	544	*
	545	*************************************/
562	546
563	547	ROM_START( ddragon3 )
564	548	ROM_REGION( 0x80000, REGION_CPU1, 0 ) /* 64k for cpu code */
r2864	r2865
772	756	ROM_CONTINUE( 0x000000, 0x20000 )
773	757	ROM_END
774	758
775		/* Game Drivers */
	759	ROM_START( ctribb2 )
	760	ROM_REGION( 0x80000, REGION_CPU1, 0 ) /* 64k for cpu code */
	761	ROM_LOAD16_BYTE( "1.bin", 0x00001, 0x20000, CRC(9cfa997f) SHA1(ee49b4b9e9cd29616f244fdf3912ef743e2404ce) )
	762	ROM_LOAD16_BYTE( "3.bin", 0x00000, 0x20000, CRC(2ece8681) SHA1(17ee2ceb893e2eb08fa4cabcdebcec02bee16cda) )
	763	ROM_LOAD16_BYTE( "2.bin", 0x40001, 0x10000, CRC(8c2c6dbd) SHA1(b99b9be6e0bdc8340fedd258819c4df587926a84) )
	764	/* No EVEN rom! */
776	765
	766	ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* 64k for sound cpu code */
	767	ROM_LOAD( "6.bin", 0x00000, 0x10000, CRC(0101df2d) SHA1(35e1efa4a11c0f9d9db5ee057926e5de29c3a4c1) )
	768
	769	ROM_REGION( 0x200000, REGION_GFX1, ROMREGION_DISPOSE )
	770	ROM_LOAD( "7.bin", 0x000000, 0x40000, CRC(a8b773f1) SHA1(999e41dfeb3fb937da769c4a33bb29bf4076dc63) ) /* Background */
	771	ROM_LOAD( "8.bin", 0x040000, 0x40000, CRC(617530fc) SHA1(b9155ed0ae1437bf4d0b7a95e769bc05a820ecec) )
	772	ROM_LOAD( "11.bin", 0x080000, 0x40000, CRC(cef0a821) SHA1(c7a35048d5ebf3f09abf9d27f91d12adc03befeb) )
	773	ROM_LOAD( "12.bin", 0x0c0000, 0x40000, CRC(b84fda09) SHA1(3ae0c0ec6c398dea17e248b017ea3e2f6c3571e1) )
	774	ROM_LOAD( "9.bin", 0x100000, 0x20000, CRC(2719d7ce) SHA1(35275d32b584c477033037bc041a3687ecca412d) )
	775	ROM_LOAD( "10.bin", 0x140000, 0x20000, CRC(753a4f53) SHA1(c76a449ef29dde671196cda1f128b0b2d4839a97) )
	776	ROM_LOAD( "13.bin", 0x180000, 0x20000, CRC(59e01fe1) SHA1(67f5a4e9c9e9ebc6218b7c2ede0e5ff51682ee2f) )
	777	ROM_LOAD( "14.bin", 0x1c0000, 0x20000, CRC(a69ab4f3) SHA1(bc99c6a587c972cb5c9e719c53ef921a28f1498e) )
	778
	779	ROM_REGION( 0x400000, REGION_GFX2, ROMREGION_DISPOSE )
	780	ROM_LOAD( "34.bin", 0x000000, 0x20000, CRC(5b498f0e) SHA1(9d93ca1f44e1f04eb3b66db6027130683c9431a2) ) /* Sprites */
	781	ROM_LOAD( "33.bin", 0x020000, 0x20000, CRC(14d79049) SHA1(250c87aa238fc794cd0f07e3388b97137cc1228f) )
	782	ROM_LOAD( "32.bin", 0x040000, 0x20000, CRC(9631ea23) SHA1(de0a6595731d185ea18959bd04e3ac9e4261a8f8) )
	783	ROM_LOAD( "31.bin", 0x060000, 0x20000, CRC(0ca8d3b9) SHA1(c48e7c456acb9deb7f01c19ab9a66360af09a13d) )
	784	ROM_LOAD( "30.bin", 0x080000, 0x10000, CRC(972faddb) SHA1(f2b211e8f8301667e6c9a3ce9612e39b16e66a67) )
	785	ROM_LOAD( "29.bin", 0x100000, 0x20000, CRC(479ae8ea) SHA1(6bfbab5ed7ae7275be0c177c7e39cff19210c0ab) )
	786	ROM_LOAD( "28.bin", 0x120000, 0x20000, CRC(95598bbf) SHA1(2a155bbb09dc4efca6e1a6b847829f7ec09d323e) )
	787	ROM_LOAD( "27.bin", 0x140000, 0x20000, CRC(4a3d006d) SHA1(d32fa627e3a4683101aff233bfc8a016c78a1702) )
	788	ROM_LOAD( "26.bin", 0x160000, 0x20000, CRC(aa34a3cb) SHA1(9bcf5db3a89a300468e9300a9fc5fd33d1ba60de) )
	789	ROM_LOAD( "25.bin", 0x180000, 0x10000, CRC(eb3ab374) SHA1(db66cb7976c111fa76a3a211e96ad1d7b78ce0ad) )
	790	ROM_LOAD( "24.bin", 0x200000, 0x20000, CRC(d60bbff0) SHA1(b5e978b1d58f4d0ff05e51b728bb3ec06eea7d08) )
	791	ROM_LOAD( "23.bin", 0x220000, 0x20000, CRC(d9595c47) SHA1(323e572a022d5297c727dc8b1717269c5b9134b7) )
	792	ROM_LOAD( "22.bin", 0x240000, 0x20000, CRC(5a19a911) SHA1(d7ce955d3127b57ee560379055d71bacf3a9d6a1) )
	793	ROM_LOAD( "21.bin", 0x260000, 0x20000, CRC(071360f9) SHA1(8269115484f3ceb69c3b2a215f684dd31a366989) )
	794	ROM_LOAD( "20.bin", 0x280000, 0x10000, CRC(c602ac97) SHA1(44440739636b684c6dcac837f59664120c9ba5f3) )
	795	ROM_LOAD( "19.bin", 0x300000, 0x20000, CRC(8d22736a) SHA1(d17f92544efebbdf89ca9fd11ab7c16d2636f175) )
	796	ROM_LOAD( "18.bin", 0x320000, 0x20000, CRC(0f157822) SHA1(a1e16e4036b0c68c3f58cb0520f8120fe60b0dfa) )
	797	ROM_LOAD( "17.bin", 0x340000, 0x20000, CRC(7f48c824) SHA1(af6b48dbcf88cfcaecb8cec5dd9eb4c25f4bf9a8) )
	798	ROM_LOAD( "16.bin", 0x360000, 0x20000, CRC(cd1e9bd5) SHA1(1f956ab476b2c403c0dbf9e6169cfe2c51bb45ac) )
	799	ROM_LOAD( "15.bin", 0x380000, 0x10000, CRC(4da1d8e5) SHA1(568e9e8d00f1b1ca27c28df5fc0ffc74ad91da7e) )
	800
	801	ROM_REGION( 0x040000, REGION_SOUND1, 0 ) /* ADPCM Samples */
	802	ROM_LOAD( "5.bin", 0x000000, 0x20000, CRC(f92a7f4a) SHA1(3717ef64876be9ada378b449749918ce9072073a) )
	803	ROM_LOAD( "4.bin", 0x020000, 0x20000, CRC(1a3a0b39) SHA1(8847530027cf4be03ffbc6d78dee97b459d03a04) )
	804	ROM_END
	805
	806	/*************************************
	807	*
	808	* Game driver(s)
	809	*
	810	*************************************/
	811
777	812	GAME( 1990, ddragon3, 0, ddragon3, ddragon3, 0, ROT0, "Technos", "Double Dragon 3 - The Rosetta Stone (US)", GAME_SUPPORTS_SAVE )
778	813	GAME( 1990, ddrago3j, ddragon3, ddragon3, ddragon3, 0, ROT0, "Technos", "Double Dragon 3 - The Rosetta Stone (Japan)", GAME_SUPPORTS_SAVE )
779	814	GAME( 1990, ddrago3b, ddragon3, ddrago3b, ddrago3b, 0, ROT0, "bootleg", "Double Dragon 3 - The Rosetta Stone (bootleg)", GAME_SUPPORTS_SAVE )
780	815	GAME( 1990, ctribe, 0, ctribe, ctribe, 0, ROT0, "Technos", "The Combatribes (US)", GAME_SUPPORTS_SAVE )
781	816	GAME( 1990, ctribe1, ctribe, ctribe, ctribe, 0, ROT0, "Technos", "The Combatribes (US) - Set 1?", GAME_SUPPORTS_SAVE )
782	817	GAME( 1990, ctribeb, ctribe, ctribe, ctribe, 0, ROT0, "bootleg", "The Combatribes (bootleg)", GAME_SUPPORTS_SAVE )
	818	GAME( 1990, ctribb2, ctribe, ctribe, ctribe, 0, ROT0, "bootleg", "The Combatribes (Italian bootleg)", GAME_SUPPORTS_SAVE )

src/mame/drivers/exterm.c
r2864	r2865
139	139	UINT16 port;
140	140
141	141	/* Read the fake input port */
142		UINT8 trackball_pos = input_port_read~~_indexed~~(machine, ~~3 +~~ which);
	142	UINT8 trackball_pos = input_port_read(machine, which ? "DIAL1" : "DIAL0");
143	143
144	144	/* Calculate the change from the last position. */
145	145	UINT8 trackball_diff = trackball_old[which] - trackball_pos;
r2864	r2865
155	155	aimpos[which] = (aimpos[which] + trackball_diff) & 0x3f;
156	156
157	157	/* Combine it with the standard input bits */
158		port = which ? input_port_read~~_indexed~~(machine,1) : input_port_read~~_indexed~~(machine,0);
	158	port = which ? input_port_read(machine, "IN1") : input_port_read(machine, "IN0");
159	159
160	160	return (port & 0xc0ff) \| (aimpos[which] << 8);
161	161	}
r2864	r2865
371	371	*************************************/
372	372
373	373	static INPUT_PORTS_START( exterm )
374		PORT_START /* IN0 */
	374	PORT_START_TAG("IN0") /* IN0 */
375	375	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
376	376	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START1 )
377	377	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
384	384	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
385	385	PORT_SERVICE( 0x8000, IP_ACTIVE_LOW )
386	386
387		PORT_START /* IN1 */
	387	PORT_START_TAG("IN1") /* IN1 */
388	388	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN2 )
389	389	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START2 )
390	390	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
396	396	PORT_BIT( 0x3f00, IP_ACTIVE_LOW, IPT_SPECIAL) /* trackball data */
397	397	PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNUSED )
398	398
399		PORT_START /* DSW */
	399	PORT_START_TAG("DSW") /* DSW */
400	400	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unused ) ) /* According to the test screen */
401	401	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
402	402	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
425	425	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
426	426	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
427	427
428		PORT_START /* IN3, fake trackball input port */
	428	PORT_START_TAG("DIAL0") /* IN3, fake trackball input port */
429	429	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(1) PORT_CODE_DEC(KEYCODE_Z) PORT_CODE_INC(KEYCODE_X)
430	430
431		PORT_START /* IN4, fake trackball input port. */
	431	PORT_START_TAG("DIAL1") /* IN4, fake trackball input port. */
432	432	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(2) PORT_CODE_DEC(KEYCODE_N) PORT_CODE_INC(KEYCODE_M)
433	433	INPUT_PORTS_END
434	434

src/mame/drivers/mediagx.c
r2864	r2865
1119	1119
1120	1120	static void init_mediagx(running_machine *machine)
1121	1121	{
1122		init_pc_common(PCCOMMON_KEYBOARD_AT,mediagx_set_keyb_int);
	1122	init_pc_common(machine, PCCOMMON_KEYBOARD_AT,mediagx_set_keyb_int);
1123	1123	mc146818_init(MC146818_STANDARD);
1124	1124
1125	1125	pci_init();

src/mame/drivers/gaplus.c
r2864	r2865
162	162
163	163	***************************************************************************/
164	164
165		static READ8_HANDLER( in0_l ) { return input_port_read_indexed(machine, 0); } // P1 joystick
166		static READ8_HANDLER( in0_h ) { return input_port_read_indexed(machine, 0) >> 4; } // P2 joystick
167		static READ8_HANDLER( in1_l ) { return input_port_read_indexed(machine, 1); } // fire and start buttons
168		static READ8_HANDLER( in1_h ) { return input_port_read_indexed(machine, 1) >> 4; } // coins
169		static READ8_HANDLER( dipA_l ) { return input_port_read_indexed(machine, 2); } // dips A
170		static READ8_HANDLER( dipA_h ) { return input_port_read_indexed(machine, 2) >> 4; } // dips A
171		static READ8_HANDLER( dipB_l ) { return input_port_read_indexed(machine, 3); } // dips B
172		static READ8_HANDLER( dipB_h ) { return input_port_read_indexed(machine, 3) >> 4; } // dips B
	165	static READ8_HANDLER( in0_l ) { return input_port_read(machine, "IN0"); } // P1 joystick
	166	static READ8_HANDLER( in0_h ) { return input_port_read(machine, "IN0") >> 4; } // P2 joystick
	167	static READ8_HANDLER( in1_l ) { return input_port_read(machine, "IN1"); } // fire and start buttons
	168	static READ8_HANDLER( in1_h ) { return input_port_read(machine, "IN1") >> 4; } // coins
	169	static READ8_HANDLER( dipA_l ) { return input_port_read(machine, "DSW0"); } // dips A
	170	static READ8_HANDLER( dipA_h ) { return input_port_read(machine, "DSW0") >> 4; } // dips A
	171	static READ8_HANDLER( dipB_l ) { return input_port_read(machine, "DSW1"); } // dips B
	172	static READ8_HANDLER( dipB_h ) { return input_port_read(machine, "DSW1") >> 4; } // dips B
173	173	static WRITE8_HANDLER( out_lamps0 )
174	174	{
175	175	set_led_status(0,data & 1);
r2864	r2865
364	364
365	365	static INPUT_PORTS_START( gaplus )
366	366	/* The inputs are not memory mapped, they are handled by three I/O chips. */
367		PORT_START /* 56XX #0 pins 22-29 */
	367	PORT_START_TAG("IN0") /* 56XX #0 pins 22-29 */
368	368	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
369	369	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
370	370	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
r2864	r2865
374	374	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
375	375	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
376	376
377		PORT_START /* 56XX #0 pins 30-33 and 38-41 */
	377	PORT_START_TAG("IN1") /* 56XX #0 pins 30-33 and 38-41 */
378	378	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
379	379	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
380	380	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r2864	r2865
384	384	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
385	385	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
386	386
387		PORT_START /* 58XX #1 pins 30-33 and 38-41 */
	387	PORT_START_TAG("DSW0") /* 58XX #1 pins 30-33 and 38-41 */
388	388	PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Lives ) )
389	389	PORT_DIPSETTING( 0x80, "2" )
390	390	PORT_DIPSETTING( 0xc0, "3" )
r2864	r2865
407	407	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
408	408	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
409	409
410		PORT_START /* 58XX #1 pins 22-29 */
	410	PORT_START_TAG("DSW1") /* 58XX #1 pins 22-29 */
411	411	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
412	412	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
413	413	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
433	433	PORT_DIPSETTING( 0x05, "50k 150k and every 300k" )
434	434	PORT_DIPSETTING( 0x06, "50k 150k" )
435	435
436		PORT_START /* 62XX #2 pins 24-27 */
	436	PORT_START_TAG("IN2") /* 62XX #2 pins 24-27 */
437	437	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
438	438	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
439	439	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Cabinet ) )
r2864	r2865
444	444
445	445	/* identical to gaplus, but service mode is a dip switch instead of coming from edge connector */
446	446	static INPUT_PORTS_START( gapluso )
447		/* The inputs are not memory mapped, they are handled by three I/O chips. */
448		PORT_START /* 56XX #0 pins 22-29 */
449		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
450		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
451		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
452		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
453		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
454		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
455		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
456		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
	447	PORT_INCLUDE( gaplus )
457	448
458		PORT_START /* 56XX #0 pins 30-33 and 38-41 */
459		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
460		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
461		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
462		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
463		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
464		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
465		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
466		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
467
468		PORT_START /* 58XX #1 pins 30-33 and 38-41 */
469		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Lives ) )
470		PORT_DIPSETTING( 0x80, "2" )
471		PORT_DIPSETTING( 0xc0, "3" )
472		PORT_DIPSETTING( 0x40, "4" )
473		PORT_DIPSETTING( 0x00, "5" )
474		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) )
475		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
476		PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) )
477		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
478		PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) )
479		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
480		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
481		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
482		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unused ) )
483		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
484		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
485		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_B ) )
486		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
487		PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
488		PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
489		PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
490
491		PORT_START /* 58XX #1 pins 22-29 */
	449	PORT_MODIFY("DSW1")
492	450	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
493		PORT_DIPNAME( 0x70, 0x70, DEF_STR( Difficulty ) )
494		PORT_DIPSETTING( 0x70, "0 - Standard" )
495		PORT_DIPSETTING( 0x60, "1 - Easiest" )
496		PORT_DIPSETTING( 0x50, "2" )
497		PORT_DIPSETTING( 0x40, "3" )
498		PORT_DIPSETTING( 0x30, "4" )
499		PORT_DIPSETTING( 0x20, "5" )
500		PORT_DIPSETTING( 0x10, "6" )
501		PORT_DIPSETTING( 0x00, "7 - Hardest" )
502		PORT_DIPNAME( 0x08, 0x08, "Round Advance" )
503		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
504		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
505		PORT_DIPNAME( 0x07, 0x00, DEF_STR( Bonus_Life ) )
506		PORT_DIPSETTING( 0x00, "30k 70k and every 70k" )
507		PORT_DIPSETTING( 0x01, "30k 100k and every 100k" )
508		PORT_DIPSETTING( 0x02, "30k 100k and every 200k" )
509		PORT_DIPSETTING( 0x03, "50k 100k and every 100k" )
510		PORT_DIPSETTING( 0x04, "50k 100k and every 200k" )
511		PORT_DIPSETTING( 0x07, "50k 150k and every 150k" )
512		PORT_DIPSETTING( 0x05, "50k 150k and every 300k" )
513		PORT_DIPSETTING( 0x06, "50k 150k" )
514	451
515		PORT_START /* 62XX #2 pins 24-27 */
516		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
517		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
518		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Cabinet ) )
519		PORT_DIPSETTING( 0x04, DEF_STR( Upright ) )
520		PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
	452	PORT_MODIFY("IN2")
521	453	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) // doesn't seem to be used
522	454	INPUT_PORTS_END
523	455
524	456	/* identical to gaplus, but different bonus life settings */
525	457	static INPUT_PORTS_START( galaga3a )
526		/* The inputs are not memory mapped, they are handled by three I/O chips. */
527		PORT_START /* 56XX #0 pins 22-29 */
528		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
529		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
530		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
531		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
532		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
533		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
534		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
535		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
	458	PORT_INCLUDE( gaplus )
536	459
537		PORT_START /* 56XX #0 pins 30-33 and 38-41 */
538		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
539		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
540		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
541		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
542		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
543		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
544		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
545		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
546
547		PORT_START /* 58XX #1 pins 30-33 and 38-41 */
548		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Lives ) )
549		PORT_DIPSETTING( 0x80, "2" )
550		PORT_DIPSETTING( 0xc0, "3" )
551		PORT_DIPSETTING( 0x40, "4" )
552		PORT_DIPSETTING( 0x00, "5" )
553		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) )
554		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
555		PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) )
556		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
557		PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) )
558		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
559		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
560		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
561		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unused ) )
562		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
563		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
564		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_B ) )
565		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
566		PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
567		PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
568		PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
569
570		PORT_START /* 58XX #1 pins 22-29 */
571		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
572		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
573		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
574		PORT_DIPNAME( 0x70, 0x70, DEF_STR( Difficulty ) )
575		PORT_DIPSETTING( 0x70, "0 - Standard" )
576		PORT_DIPSETTING( 0x60, "1 - Easiest" )
577		PORT_DIPSETTING( 0x50, "2" )
578		PORT_DIPSETTING( 0x40, "3" )
579		PORT_DIPSETTING( 0x30, "4" )
580		PORT_DIPSETTING( 0x20, "5" )
581		PORT_DIPSETTING( 0x10, "6" )
582		PORT_DIPSETTING( 0x00, "7 - Hardest" )
583		PORT_DIPNAME( 0x08, 0x08, "Round Advance" )
584		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
585		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	460	PORT_MODIFY("DSW1")
586	461	PORT_DIPNAME( 0x07, 0x02, DEF_STR( Bonus_Life ) )
587	462	PORT_DIPSETTING( 0x02, "30k 80k and every 100k" )
588	463	PORT_DIPSETTING( 0x03, "30k 100k and every 100k" )
r2864	r2865
592	467	PORT_DIPSETTING( 0x06, "30k 150k" )
593	468	PORT_DIPSETTING( 0x00, "50k 150k and every 150k" )
594	469	PORT_DIPSETTING( 0x01, "50k 150k and every 200k" )
595
596		PORT_START /* 62XX #2 pins 24-27 */
597		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
598		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
599		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Cabinet ) )
600		PORT_DIPSETTING( 0x04, DEF_STR( Upright ) )
601		PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
602		PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
603	470	INPUT_PORTS_END
604	471
605	472	/* identical to gaplus, but different bonus life settings */
606	473	static INPUT_PORTS_START( galaga3m )
607		/* The inputs are not memory mapped, they are handled by three I/O chips. */
608		PORT_START /* 56XX #0 pins 22-29 */
609		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
610		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
611		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
612		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
613		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
614		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
615		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
616		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
	474	PORT_INCLUDE( gaplus )
617	475
618		PORT_START /* 56XX #0 pins 30-33 and 38-41 */
619		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
620		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
621		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
622		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
623		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
624		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
625		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
626		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
627
628		PORT_START /* 58XX #1 pins 30-33 and 38-41 */
629		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Lives ) )
630		PORT_DIPSETTING( 0x80, "2" )
631		PORT_DIPSETTING( 0xc0, "3" )
632		PORT_DIPSETTING( 0x40, "4" )
633		PORT_DIPSETTING( 0x00, "5" )
634		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) )
635		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
636		PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) )
637		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
638		PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) )
639		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
640		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
641		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
642		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unused ) )
643		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
644		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
645		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_B ) )
646		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
647		PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
648		PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
649		PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
650
651		PORT_START /* 58XX #1 pins 22-29 */
652		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
653		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
654		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
655		PORT_DIPNAME( 0x70, 0x70, DEF_STR( Difficulty ) )
656		PORT_DIPSETTING( 0x70, "0 - Standard" )
657		PORT_DIPSETTING( 0x60, "1 - Easiest" )
658		PORT_DIPSETTING( 0x50, "2" )
659		PORT_DIPSETTING( 0x40, "3" )
660		PORT_DIPSETTING( 0x30, "4" )
661		PORT_DIPSETTING( 0x20, "5" )
662		PORT_DIPSETTING( 0x10, "6" )
663		PORT_DIPSETTING( 0x00, "7 - Hardest" )
664		PORT_DIPNAME( 0x08, 0x08, "Round Advance" )
665		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
666		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	476	PORT_MODIFY("DSW1")
667	477	PORT_DIPNAME( 0x07, 0x00, DEF_STR( Bonus_Life ) )
668	478	PORT_DIPSETTING( 0x00, "30k 150k and every 600k" )
669	479	PORT_DIPSETTING( 0x01, "50k 150k and every 300k" )
r2864	r2865
673	483	PORT_DIPSETTING( 0x07, "100k 300k and every 600k" )
674	484	PORT_DIPSETTING( 0x05, "150k 400k and every 900k" )
675	485	PORT_DIPSETTING( 0x06, "150k 400k" )
676
677		PORT_START /* 62XX #2 pins 24-27 */
678		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
679		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
680		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Cabinet ) )
681		PORT_DIPSETTING( 0x04, DEF_STR( Upright ) )
682		PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
683		PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
684	486	INPUT_PORTS_END
685	487
686	488

src/mame/drivers/jedi.c
r2864	r2865
214	214
215	215	switch (state->a2d_select)
216	216	{
217		case 0: ret = input_port_read_indexed(machine, 2); break;
218		case 2: ret = input_port_read_indexed(machine, 3); break;
	217	case 0: ret = input_port_read(machine, "STICKY"); break;
	218	case 2: ret = input_port_read(machine, "STICKX"); break;
219	219	}
220	220
221	221	return ret;
r2864	r2865
309	309	*************************************/
310	310
311	311	static INPUT_PORTS_START( jedi )
312		PORT_START /* 0C00 */
	312	PORT_START_TAG("0c00") /* 0C00 */
313	313	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 )
314	314	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
315	315	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 )
r2864	r2865
319	319	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
320	320	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
321	321
322		PORT_START /* 0C01 */
	322	PORT_START_TAG("0c01") /* 0C01 */
323	323	PORT_BIT( 0x03, IP_ACTIVE_LOW, IPT_UNUSED )
324	324	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_TILT )
325	325	PORT_BIT( 0x18, IP_ACTIVE_LOW, IPT_UNUSED )
326	326	PORT_BIT( 0x60, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(jedi_audio_comm_stat_r, 0)
327	327	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_VBLANK )
328	328
329		PORT_START /* analog Y */
	329	PORT_START_TAG("STICKY") /* analog Y */
330	330	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10)
331	331
332		PORT_START /* analog X */
	332	PORT_START_TAG("STICKX") /* analog X */
333	333	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10)
334	334	INPUT_PORTS_END
335	335

src/mame/drivers/flkatck.c
r2864	r2865
60	60	int data = 0;
61	61
62	62	switch ((offset & 0x1c) >> 2){
63		case 0x00: ~~/* inputs + DIPSW #3 + coinsw */~~
	63	case 0x00:
64	64	if (offset & 0x02)
65		data = input_port_read~~_indexed~~(machine, ~~2 +~~ (offset & 0x01));
	65	data = input_port_read(machine, (offset & 0x01) ? "COIN" : "DSW3");
66	66	else
67		data = input_port_read~~_indexed~~(machine, ~~4 +~~ (offset & 0x01));
	67	data = input_port_read(machine, (offset & 0x01) ? "P2" : "P1");
68	68	break;
69		case 0x01: ~~/* DIPSW #1 & DIPSW #2 */~~
	69	case 0x01:
70	70	if (offset & 0x02)
71		data = input_port_read~~_indexed~~(machine, ~~1 -~~ (offset & 0x01));
	71	data = input_port_read(machine, (offset & 0x01) ? "DSW1" : "DSW2");
72	72	break;
73	73	}
74	74
r2864	r2865
150	150
151	151
152	152	static INPUT_PORTS_START( flkatck )
153		PORT_START /* DSW #1 */
	153	PORT_START_TAG("DSW1") /* DSW #1 */
154	154	PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
155	155	PORT_DIPSETTING( 0x02, DEF_STR( 4C_1C ) )
156	156	PORT_DIPSETTING( 0x05, DEF_STR( 3C_1C ) )
r2864	r2865
186	186	PORT_DIPSETTING( 0x90, DEF_STR( 1C_7C ) )
187	187	//PORT_DIPSETTING( 0x00, "Invalid" )
188	188
189		PORT_START /* DSW #2 */
	189	PORT_START_TAG("DSW2") /* DSW #2 */
190	190	PORT_DIPNAME( 0x03, 0x01, DEF_STR( Lives ) )
191	191	PORT_DIPSETTING( 0x03, "1" )
192	192	PORT_DIPSETTING( 0x02, "2" )
r2864	r2865
209	209	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
210	210	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
211	211
212		PORT_START /* DSW #3 */
	212	PORT_START_TAG("DSW3") /* DSW #3 */
213	213	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
214	214	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
215	215	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
222	222	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
223	223	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
224	224
225		PORT_START /* COINSW & START */
	225	PORT_START_TAG("COIN") /* COINSW & START */
226	226	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
227	227	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
228	228	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 ) /* service */
r2864	r2865
232	232	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
233	233	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
234	234
235		PORT_START /* PLAYER 1 INPUTS */
	235	PORT_START_TAG("P1") /* PLAYER 1 INPUTS */
236	236	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
237	237	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
238	238	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
242	242	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
243	243	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
244	244
245		PORT_START /* PLAYER 2 INPUTS */
	245	PORT_START_TAG("P2") /* PLAYER 2 INPUTS */
246	246	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
247	247	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
248	248	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)

src/mame/drivers/dynax.c
r2864	r2865
237	237	int res = 0x3f;
238	238
239	239	/* the game reads all rows at once (keyb = 0) to check if a key is pressed */
240		if (~keyb & 0x01) res &= input_port_read_indexed(machine, 3);
241		if (~keyb & 0x02) res &= input_port_read_indexed(machine, 4);
242		if (~keyb & 0x04) res &= input_port_read_indexed(machine, 5);
243		if (~keyb & 0x08) res &= input_port_read_indexed(machine, 6);
244		if (~keyb & 0x10) res &= input_port_read_indexed(machine, 7);
	240	if (~keyb & 0x01) res &= input_port_read(machine, "KEY0");
	241	if (~keyb & 0x02) res &= input_port_read(machine, "KEY1");
	242	if (~keyb & 0x04) res &= input_port_read(machine, "KEY2");
	243	if (~keyb & 0x08) res &= input_port_read(machine, "KEY3");
	244	if (~keyb & 0x10) res &= input_port_read(machine, "KEY4");
245	245
246	246	return res;
247	247	}
r2864	r2865
251	251	int res = 0x3f;
252	252
253	253	/* the game reads all rows at once (keyb = 0) to check if a key is pressed */
254		if (~keyb & 0x01) res &= input_port_read_indexed(machine, 8);
255		if (~keyb & 0x02) res &= input_port_read_indexed(machine, 9);
256		if (~keyb & 0x04) res &= input_port_read_indexed(machine, 10);
257		if (~keyb & 0x08) res &= input_port_read_indexed(machine, 11);
258		if (~keyb & 0x10) res &= input_port_read_indexed(machine, 12);
	254	if (~keyb & 0x01) res &= input_port_read(machine, "KEY5");
	255	if (~keyb & 0x02) res &= input_port_read(machine, "KEY6");
	256	if (~keyb & 0x04) res &= input_port_read(machine, "KEY7");
	257	if (~keyb & 0x08) res &= input_port_read(machine, "KEY8");
	258	if (~keyb & 0x10) res &= input_port_read(machine, "KEY9");
259	259
260	260	return res;
261	261	}
r2864	r2865
518	518	AM_RANGE( 0x50, 0x50 ) AM_WRITE ( dynax_rombank_w ) // BANK ROM Select hnkochou only
519	519	AM_RANGE( 0x60, 0x60 ) AM_READ ( hanamai_keyboard_0_r ) // P1
520	520	AM_RANGE( 0x61, 0x61 ) AM_READ ( hanamai_keyboard_1_r ) // P2
521		AM_RANGE( 0x62, 0x62 ) AM_READ ( ~~input_port_2_r~~ ) // Coins
	521	AM_RANGE( 0x62, 0x62 ) AM_READ_PORT ( "IN0" ) // Coins
522	522	AM_RANGE( 0x63, 0x63 ) AM_READ ( ret_ff ) // ?
523	523	AM_RANGE( 0x64, 0x64 ) AM_WRITE ( hanamai_keyboard_w ) // keyboard row select
524	524	AM_RANGE( 0x65, 0x65 ) AM_WRITE ( dynax_rombank_w ) // BANK ROM Select hanamai only
r2864	r2865
551	551	static ADDRESS_MAP_START( hnoridur_io_map, ADDRESS_SPACE_IO, 8 )
552	552	ADDRESS_MAP_GLOBAL_MASK(0xff)
553	553	AM_RANGE( 0x01, 0x07 ) AM_WRITE ( dynax_blitter_rev2_w ) // Blitter
554		// AM_RANGE( 0x10, 0x10 ) AM_WRITE ( SMH_NOP ) // CRT Controller
555		// AM_RANGE( 0x11, 0x11 ) AM_WRITE ( SMH_NOP ) // CRT Controller
	554	// AM_RANGE( 0x10, 0x10 ) AM_WRITE ( SMH_NOP ) // CRT Controller
	555	// AM_RANGE( 0x11, 0x11 ) AM_WRITE ( SMH_NOP ) // CRT Controller
556	556	AM_RANGE( 0x20, 0x20 ) AM_WRITE ( hanamai_keyboard_w ) // keyboard row select
557		AM_RANGE( 0x21, 0x21 ) AM_READ ( ~~input_port_2_r~~ ) // Coins
	557	AM_RANGE( 0x21, 0x21 ) AM_READ_PORT ( "IN0" ) // Coins
558	558	AM_RANGE( 0x22, 0x22 ) AM_READ ( hanamai_keyboard_1_r ) // P2
559	559	AM_RANGE( 0x23, 0x23 ) AM_READ ( hanamai_keyboard_0_r ) // P1
560		AM_RANGE( 0x24, 0x24 ) AM_READ ( input_port_1_r ) // DSW2
561		AM_RANGE( 0x25, 0x25 ) AM_READ ( input_port_14_r ) // DSW4
562		AM_RANGE( 0x26, 0x26 ) AM_READ ( input_port_13_r ) // DSW3
	560	AM_RANGE( 0x24, 0x24 ) AM_READ_PORT ( "DSW1" ) // DSW2
	561	AM_RANGE( 0x25, 0x25 ) AM_READ_PORT ( "DSW3" ) // DSW4
	562	AM_RANGE( 0x26, 0x26 ) AM_READ_PORT ( "DSW2" ) // DSW3
563	563	AM_RANGE( 0x30, 0x30 ) AM_WRITE ( adpcm_reset_w ) // MSM5205 reset
564	564	AM_RANGE( 0x32, 0x32 ) AM_WRITE ( adpcm_data_w ) // MSM5205 data
565	565	AM_RANGE( 0x34, 0x34 ) AM_WRITE ( YM2413_register_port_0_w ) // YM2413
r2864	r2865
610	610
611	611	static READ8_HANDLER( yarunara_input_r )
612	612	{
	613	static const char *keynames0[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
	614	static const char *keynames1[] = { "KEY5", "KEY6", "KEY7", "KEY8", "KEY9" };
	615
613	616	switch (offset)
614	617	{
615	618	case 0:
r2864	r2865
617	620	switch( yarunara_select )
618	621	{
619	622	case 0x00:
620		return input_port_read(machine, "IN2"); // coins
	623	return input_port_read(machine, "IN0"); // coins
621	624
622	625	case 0x02:
623	626	return 0xff; // bit 7 must be 1. Bit 2?
r2864	r2865
634	637	// player 2
635	638	case 0x01: //quiztvqq
636	639	case 0x81:
637		return input_port_read~~_indexed~~(machine, ~~3 + 5 +~~ yarunara_ip++);
	640	return input_port_read(machine, keynames1[yarunara_ip++]);
638	641
639	642	// player 1
640	643	case 0x02: //quiztvqq
641	644	case 0x82:
642		return input_port_read~~_indexed~~(machine, ~~3 +~~ yarunara_ip++);
	645	return input_port_read(machine, keynames0[yarunara_ip++]);
643	646
644	647	default:
645	648	return 0xff;
r2864	r2865
690	693	AM_RANGE( 0x49, 0x49 ) AM_WRITE ( dynax_extra_scrolly_w ) // screen scroll Y
691	694	AM_RANGE( 0x4a, 0x4a ) AM_WRITE ( yarunara_rombank_w ) // BANK ROM Select
692	695	AM_RANGE( 0x4b, 0x4b ) AM_WRITE ( dynax_vblank_ack_w ) // VBlank IRQ Ack
693		AM_RANGE( 0x4c, 0x4c ) AM_READ ( input_port_0_r ) // DSW 1
694		AM_RANGE( 0x4f, 0x4f ) AM_READ ( input_port_1_r ) // DSW 2
	696	AM_RANGE( 0x4c, 0x4c ) AM_READ_PORT ( "DSW0" ) // DSW 1
	697	AM_RANGE( 0x4f, 0x4f ) AM_READ_PORT ( "DSW1" ) // DSW 2
695	698	AM_RANGE( 0x50, 0x50 ) AM_WRITE ( yarunara_flipscreen_w )
696	699	AM_RANGE( 0x51, 0x51 ) AM_WRITE ( yarunara_layer_half_w ) // half of the interleaved layer to write to
697	700	AM_RANGE( 0x52, 0x52 ) AM_WRITE ( yarunara_layer_half2_w ) //
r2864	r2865
715	718	// AM_RANGE( 0x10, 0x10 ) AM_WRITE ( SMH_NOP ) // CRT Controller
716	719	// AM_RANGE( 0x11, 0x11 ) AM_WRITE ( SMH_NOP ) // CRT Controller
717	720	AM_RANGE( 0x20, 0x20 ) AM_WRITE ( hanamai_keyboard_w ) // keyboard row select
718		AM_RANGE( 0x21, 0x21 ) AM_READ ( ~~input_port_2_r~~ ) // Coins
	721	AM_RANGE( 0x21, 0x21 ) AM_READ_PORT ( "IN0" ) // Coins
719	722	AM_RANGE( 0x22, 0x22 ) AM_READ ( hanamai_keyboard_1_r ) // P2
720	723	AM_RANGE( 0x23, 0x23 ) AM_READ ( hanamai_keyboard_0_r ) // P1
721		AM_RANGE( 0x24, 0x24 ) AM_READ ( input_port_0_r ) // DSW2
722		AM_RANGE( 0x26, 0x26 ) AM_READ ( input_port_1_r ) // DSW3
	724	AM_RANGE( 0x24, 0x24 ) AM_READ_PORT ( "DSW0" ) // DSW2
	725	AM_RANGE( 0x26, 0x26 ) AM_READ_PORT ( "DSW1" ) // DSW3
723	726	AM_RANGE( 0x30, 0x30 ) AM_WRITE ( adpcm_reset_w ) // MSM5205 reset
724	727	AM_RANGE( 0x32, 0x32 ) AM_WRITE ( adpcm_data_w ) // MSM5205 data
725	728	AM_RANGE( 0x34, 0x34 ) AM_WRITE ( YM2413_register_port_0_w ) // YM2413
r2864	r2865
753	756	AM_RANGE( 0x01, 0x07 ) AM_WRITE ( dynax_blitter_rev2_w ) // Blitter
754	757	AM_RANGE( 0x10, 0x10 ) AM_READWRITE ( YM2203_status_port_0_r, YM2203_control_port_0_w ) // YM2203
755	758	AM_RANGE( 0x11, 0x11 ) AM_READWRITE ( YM2203_read_port_0_r, YM2203_write_port_0_w ) // 2 x DSW
756		// AM_RANGE( 0x12, 0x12 ) AM_WRITE ( SMH_NOP ) // CRT Controller
757		// AM_RANGE( 0x13, 0x13 ) AM_WRITE ( SMH_NOP ) // CRT Controller
758		AM_RANGE( 0x20, 0x20 ) AM_READ ( input_port_0_r ) // P1
759		AM_RANGE( 0x21, 0x21 ) AM_READ ( input_port_1_r ) // P2
760		AM_RANGE( 0x22, 0x22 ) AM_READ ( input_port_2_r ) // Coins
	759	// AM_RANGE( 0x12, 0x12 ) AM_WRITE ( SMH_NOP ) // CRT Controller
	760	// AM_RANGE( 0x13, 0x13 ) AM_WRITE ( SMH_NOP ) // CRT Controller
	761	AM_RANGE( 0x20, 0x20 ) AM_READ_PORT ( "P1" ) // P1
	762	AM_RANGE( 0x21, 0x21 ) AM_READ_PORT ( "P2" ) // P2
	763	AM_RANGE( 0x22, 0x22 ) AM_READ_PORT ( "IN0" ) // Coins
761	764	AM_RANGE( 0x23, 0x23 ) AM_READ ( ret_ff ) // ?
762	765	AM_RANGE( 0x30, 0x30 ) AM_WRITE ( dynax_layer_enable_w ) // Layers Enable
763	766	AM_RANGE( 0x31, 0x31 ) AM_WRITE ( dynax_rombank_w ) // BANK ROM Select
r2864	r2865
790	793	AM_RANGE( 0x15, 0x15 ) AM_WRITE ( dynax_coincounter_1_w ) //
791	794	AM_RANGE( 0x16, 0x17 ) AM_WRITE ( mjdialq2_layer_enable_w ) // Layers Enable
792	795	AM_RANGE( 0x41, 0x47 ) AM_WRITE ( dynax_blitter_rev2_w ) // Blitter
793		// AM_RANGE( 0x50, 0x50 ) AM_WRITE ( SMH_NOP ) // CRT Controller
794		// AM_RANGE( 0x51, 0x51 ) AM_WRITE ( SMH_NOP ) // CRT Controller
	796	// AM_RANGE( 0x50, 0x50 ) AM_WRITE ( SMH_NOP ) // CRT Controller
	797	// AM_RANGE( 0x51, 0x51 ) AM_WRITE ( SMH_NOP ) // CRT Controller
795	798	AM_RANGE( 0x60, 0x60 ) AM_WRITE ( hanamai_keyboard_w ) // keyboard row select
796		AM_RANGE( 0x61, 0x61 ) AM_READ ( ~~input_port_2_r~~ ) // Coins
	799	AM_RANGE( 0x61, 0x61 ) AM_READ_PORT ( "IN0" ) // Coins
797	800	AM_RANGE( 0x62, 0x62 ) AM_READ ( hanamai_keyboard_1_r ) // P2
798	801	AM_RANGE( 0x63, 0x63 ) AM_READ ( hanamai_keyboard_0_r ) // P1
799		AM_RANGE( 0x64, 0x64 ) AM_READ ( input_port_0_r ) // DSW
800		AM_RANGE( 0x67, 0x67 ) AM_READ ( input_port_1_r ) // DSW
	802	AM_RANGE( 0x64, 0x64 ) AM_READ_PORT ( "DSW0" ) // DSW
	803	AM_RANGE( 0x67, 0x67 ) AM_READ_PORT ( "DSW1" ) // DSW
801	804	AM_RANGE( 0x70, 0x70 ) AM_WRITE ( YM2413_register_port_0_w ) // YM2413
802	805	AM_RANGE( 0x71, 0x71 ) AM_WRITE ( YM2413_data_port_0_w ) //
803		// AM_RANGE( 0x80, 0x80 ) AM_WRITE ( SMH_NOP ) // IRQ ack?
	806	// AM_RANGE( 0x80, 0x80 ) AM_WRITE ( SMH_NOP ) // IRQ ack?
804	807	ADDRESS_MAP_END
805	808
806	809
r2864	r2865
813	816	AM_RANGE( 0x08, 0x08 ) AM_WRITE ( AY8910_write_port_0_w ) // AY8910
814	817	AM_RANGE( 0x0a, 0x0a ) AM_WRITE ( AY8910_control_port_0_w ) //
815	818	AM_RANGE( 0x10, 0x10 ) AM_WRITE ( hanamai_keyboard_w ) // keyboard row select
816		AM_RANGE( 0x11, 0x11 ) AM_READ ( ~~input_port_2_r~~ ) // Coins
	819	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT ( "IN0" ) // Coins
817	820	AM_RANGE( 0x12, 0x12 ) AM_READ ( hanamai_keyboard_1_r ) // P2
818	821	AM_RANGE( 0x13, 0x13 ) AM_READ ( hanamai_keyboard_0_r ) // P1
819		AM_RANGE( 0x14, 0x14 ) AM_READ ( input_port_0_r ) // DSW1
820		AM_RANGE( 0x15, 0x15 ) AM_READ ( input_port_1_r ) // DSW2
821		AM_RANGE( 0x16, 0x16 ) AM_READ ( input_port_13_r ) // DSW3
822		// AM_RANGE( 0x20, 0x21 ) AM_WRITE ( SMH_NOP ) // CRT Controller
	822	AM_RANGE( 0x14, 0x14 ) AM_READ_PORT ( "DSW0" ) // DSW1
	823	AM_RANGE( 0x15, 0x15 ) AM_READ_PORT ( "DSW1" ) // DSW2
	824	AM_RANGE( 0x16, 0x16 ) AM_READ_PORT ( "DSW2" ) // DSW3
	825	// AM_RANGE( 0x20, 0x21 ) AM_WRITE ( SMH_NOP ) // CRT Controller
823	826	AM_RANGE( 0x31, 0x37 ) AM_WRITE ( dynax_blitter_rev2_w ) // Blitter
824	827	AM_RANGE( 0x40, 0x40 ) AM_WRITE ( dynax_coincounter_0_w ) // Coin Counter
825	828	AM_RANGE( 0x50, 0x50 ) AM_WRITE ( dynax_flipscreen_w ) // Flip Screen
r2864	r2865
890	893	AM_RANGE( 0x50, 0x50 ) AM_WRITE ( jantouki_vblank_ack_w ) // VBlank IRQ Ack
891	894	AM_RANGE( 0x51, 0x51 ) AM_WRITE ( hanamai_keyboard_w ) // keyboard row select
892	895	AM_RANGE( 0x52, 0x52 ) AM_READ ( hanamai_keyboard_0_r ) // P1
893		AM_RANGE( 0x54, 0x54 ) AM_READ ( input_port_2_r ) // Coins
894		AM_RANGE( 0x55, 0x55 ) AM_READ ( input_port_0_r ) // DSW1
895		AM_RANGE( 0x56, 0x56 ) AM_READ ( input_port_1_r ) // DSW2
	896	AM_RANGE( 0x54, 0x54 ) AM_READ_PORT ( "IN0" ) // Coins
	897	AM_RANGE( 0x55, 0x55 ) AM_READ_PORT ( "DSW0" ) // DSW1
	898	AM_RANGE( 0x56, 0x56 ) AM_READ_PORT ( "DSW1" ) // DSW2
896	899	AM_RANGE( 0x58, 0x58 ) AM_WRITE ( dynax_coincounter_0_w ) // Coin Counter
897	900	AM_RANGE( 0x5b, 0x5b ) AM_WRITE ( dynax_blit2_palbank_w ) // Layers Palettes (High Bit)
898	901	AM_RANGE( 0x5d, 0x5d ) AM_WRITE ( dynax_blit_palbank_w ) //
r2864	r2865
957	960
958	961	static READ8_HANDLER( mjelctrn_keyboard_1_r )
959	962	{
960		return (hanamai_keyboard_1_r(machine,0) & 0x3f) \| (input_port_read~~_indexed~~(machine, 15) ? 0x40 : 0);
	963	return (hanamai_keyboard_1_r(machine, 0) & 0x3f) \| (input_port_read(machine, "FAKE") ? 0x40 : 0);
961	964	}
962	965
963	966	static READ8_HANDLER( mjelctrn_dsw_r )
964	967	{
965	968	int dsw = (keyb & 0xc0) >> 6;
966		if (dsw >= 2) dsw = dsw - 2 + 13; // 0-3 -> IN0,IN1,IN13,IN14
967		return input_port_read_indexed(machine, dsw);
	969	static const char *dswnames[] = { "DSW2", "DSW1", "DSW3", "DSW4" };
	970
	971	return input_port_read(machine, dswnames[dsw]);
968	972	}
969	973
970	974	static WRITE8_HANDLER( mjelctrn_blitter_ack_w )
r2864	r2865
991	995	// AM_RANGE( 0x66, 0x66 ) AM_WRITE ( dynax_extra_scrolly_w ) // screen scroll Y
992	996	AM_RANGE( 0x6a, 0x6a ) AM_WRITE ( hnoridur_rombank_w ) // BANK ROM Select
993	997	AM_RANGE( 0x80, 0x80 ) AM_WRITE ( hanamai_keyboard_w ) // keyboard row select
994		AM_RANGE( 0x81, 0x81 ) AM_READ ( ~~input_port_2_r~~ ) // Coins
	998	AM_RANGE( 0x81, 0x81 ) AM_READ_PORT ( "IN0" ) // Coins
995	999	AM_RANGE( 0x82, 0x82 ) AM_READ ( mjelctrn_keyboard_1_r ) // P2
996	1000	AM_RANGE( 0x83, 0x83 ) AM_READ ( hanamai_keyboard_0_r ) // P1
997	1001	AM_RANGE( 0x84, 0x84 ) AM_READ ( mjelctrn_dsw_r ) // DSW x 4
r2864	r2865
1030	1034	static READ8_HANDLER( htengoku_dsw_r )
1031	1035	{
1032	1036
1033		if (!(htengoku_dsw & 0x01)) return input_port_read_indexed(machine, 11);
1034		if (!(htengoku_dsw & 0x02)) return input_port_read_indexed(machine, 12);
1035		if (!(htengoku_dsw & 0x04)) return input_port_read_indexed(machine, 13);
1036		if (!(htengoku_dsw & 0x08)) return input_port_read_indexed(machine, 14);
1037		if (!(htengoku_dsw & 0x10)) return input_port_read_indexed(machine, 15);
	1037	if (!(htengoku_dsw & 0x01)) return input_port_read(machine, "DSW0");
	1038	if (!(htengoku_dsw & 0x02)) return input_port_read(machine, "DSW1");
	1039	if (!(htengoku_dsw & 0x04)) return input_port_read(machine, "DSW2");
	1040	if (!(htengoku_dsw & 0x08)) return input_port_read(machine, "DSW3");
	1041	if (!(htengoku_dsw & 0x10)) return input_port_read(machine, "DSW4");
1038	1042	logerror("%06x: warning, unknown bits read, htengoku_dsw = %02x\n", activecpu_get_pc(), htengoku_dsw);
1039	1043
1040	1044	return 0xff;
r2864	r2865
1059	1063
1060	1064	case 0xff: break; // CRT controller?
1061	1065	default:
1062		logerror("%04x: coins_w with select = %02x, data = %02x\n",activecpu_get_pc(),htengoku_select,data);
	1066	logerror("%04x: coins_w with select = %02x, data = %02x\n", activecpu_get_pc(), htengoku_select,data);
1063	1067	}
1064	1068	}
1065	1069
1066	1070	static READ8_HANDLER( htengoku_input_r )
1067	1071	{
	1072	static const char *keynames0[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
	1073	static const char *keynames1[] = { "KEY5", "KEY6", "KEY7", "KEY8", "KEY9" };
	1074
1068	1075	switch( htengoku_select )
1069	1076	{
1070		case 0x81: return input_port_read_indexed(machine, 1 + 5 + htengoku_ip++);
1071		case 0x82: return input_port_read_indexed(machine, 1 + htengoku_ip++);
	1077	case 0x81: return input_port_read(machine, keynames1[htengoku_ip++]);
	1078	case 0x82: return input_port_read(machine, keynames0[htengoku_ip++]);
1072	1079	case 0x0d: return 0xff; // unused
1073	1080	}
1074		logerror("%04x: input_r with select = %02x\n",activecpu_get_pc(),htengoku_select);
	1081	logerror("%04x: input_r with select = %02x\n", activecpu_get_pc(), htengoku_select);
1075	1082	return 0xff;
1076	1083	}
1077	1084
r2864	r2865
1079	1086	{
1080	1087	switch( htengoku_select )
1081	1088	{
1082		case 0x00: return input_port_read~~_indexed~~(machine, 0);
	1089	case 0x00: return input_port_read(machine, "IN0");
1083	1090	case 0x01: return 0xff; //?
1084	1091	case 0x02: return 0xbf \| ((htengoku_hopper && !(video_screen_get_frame_number(machine->primary_screen)%10)) ? 0 : (1<<6));; // bit 7 = blitter busy, bit 6 = hopper
1085	1092	case 0x03: return htengoku_coins;
1086	1093	}
1087		logerror("%04x: coin_r with select = %02x\n",activecpu_get_pc(),htengoku_select);
	1094	logerror("%04x: coin_r with select = %02x\n", activecpu_get_pc(), htengoku_select);
1088	1095	return 0xff;
1089	1096	}
1090	1097
r2864	r2865
1187	1194	break;
1188	1195	return;
1189	1196	}
1190		logerror("%04x: unmapped ip_sel=%02x written with %02x\n",activecpu_get_pc(),tenkai_ipsel,data);
	1197	logerror("%04x: unmapped ip_sel=%02x written with %02x\n", activecpu_get_pc(), tenkai_ipsel,data);
1191	1198	}
1192	1199
1193	1200	static READ8_HANDLER( tenkai_ip_r )
1194	1201	{
	1202	static const char *keynames0[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
	1203	// static const char *keynames1[] = { "KEY5", "KEY6", "KEY7", "KEY8", "KEY9" };
	1204
1195	1205	switch (offset)
1196	1206	{
1197	1207	case 0:
r2864	r2865
1199	1209	switch( tenkai_ipsel )
1200	1210	{
1201	1211	case 0x00:
1202		return input_port_read~~_indexed~~(machine, 5); // coins
	1212	return input_port_read(machine, "IN0"); // coins
1203	1213
1204	1214	default:
1205		logerror("%04x: unmapped ip_sel=%02x read from offs %x\n",activecpu_get_pc(),tenkai_ipsel,offset);
	1215	logerror("%04x: unmapped ip_sel=%02x read from offs %x\n", activecpu_get_pc(), tenkai_ipsel, offset);
1206	1216	return 0xff;
1207	1217	}
1208	1218	}
r2864	r2865
1217	1227	// player 2
1218	1228	case 0x81:
1219	1229	if (tenkai_ip >= 5)
1220		logerror("%04x: unmapped tenkai_ip=%02x read\n",activecpu_get_pc(),tenkai_ip);
1221		return 0xff;//input_port_read_indexed(machine, 6 + 5 + tenkai_ip++);
	1230	logerror("%04x: unmapped tenkai_ip=%02x read\n", activecpu_get_pc(), tenkai_ip);
	1231	return 0xff;//input_port_read(machine, keynames1[tenkai_ip++]);
1222	1232
1223	1233	// player 1
1224	1234	case 0x82:
1225	1235	if (tenkai_ip >= 5)
1226		logerror("%04x: unmapped tenkai_ip=%02x read\n",activecpu_get_pc(),tenkai_ip);
1227		return input_port_read_indexed(machine, 6 + tenkai_ip++);
	1236	logerror("%04x: unmapped tenkai_ip=%02x read\n", activecpu_get_pc(), tenkai_ip);
	1237	return input_port_read(machine, keynames0[tenkai_ip++]);
1228	1238
1229	1239	default:
1230		logerror("%04x: unmapped ip_sel=%02x read from offs %x\n",activecpu_get_pc(),tenkai_ipsel,offset);
	1240	logerror("%04x: unmapped ip_sel=%02x read from offs %x\n", activecpu_get_pc(), tenkai_ipsel, offset);
1231	1241	return 0xff;
1232	1242	}
1233	1243	}
r2864	r2865
1242	1252	}
1243	1253	static READ8_HANDLER( tenkai_dsw_r )
1244	1254	{
1245		if (~tenkai_dswsel & 0x01) return input_port_read_indexed(machine, 0);
1246		if (~tenkai_dswsel & 0x02) return input_port_read_indexed(machine, 1);
1247		if (~tenkai_dswsel & 0x04) return input_port_read_indexed(machine, 2);
1248		if (~tenkai_dswsel & 0x08) return input_port_read_indexed(machine, 3);
1249		if (~tenkai_dswsel & 0x10) return input_port_read_indexed(machine, 4);
	1255	if (~tenkai_dswsel & 0x01) return input_port_read(machine, "DSW0");
	1256	if (~tenkai_dswsel & 0x02) return input_port_read(machine, "DSW1");
	1257	if (~tenkai_dswsel & 0x04) return input_port_read(machine, "DSW2");
	1258	if (~tenkai_dswsel & 0x08) return input_port_read(machine, "DSW3");
	1259	if (~tenkai_dswsel & 0x10) return input_port_read(machine, "DSW4");
1250	1260	logerror("%04x: unmapped dsw %02x read\n",activecpu_get_pc(),tenkai_dswsel);
1251	1261	return 0xff;
1252	1262	}
r2864	r2865
1435	1445	***************************************************************************/
1436	1446
1437	1447	static INPUT_PORTS_START( MAHJONG_KEYS )
1438		// Keyboard 1
1439		PORT_START
	1448	/* Keyboard 1 */
	1449	PORT_START_TAG("KEY0")
1440	1450	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(1)
1441	1451	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(1)
1442	1452	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(1)
r2864	r2865
1444	1454	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(1)
1445	1455	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
1446	1456
1447		PORT_START
	1457	PORT_START_TAG("KEY1")
1448	1458	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(1)
1449	1459	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(1)
1450	1460	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(1)
r2864	r2865
1452	1462	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(1)
1453	1463	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1454	1464
1455		PORT_START
	1465	PORT_START_TAG("KEY2")
1456	1466	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(1)
1457	1467	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(1)
1458	1468	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(1)
r2864	r2865
1460	1470	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(1)
1461	1471	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1462	1472
1463		PORT_START
	1473	PORT_START_TAG("KEY3")
1464	1474	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(1)
1465	1475	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(1)
1466	1476	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(1)
r2864	r2865
1468	1478	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1469	1479	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1470	1480
1471		PORT_START
	1481	PORT_START_TAG("KEY4")
1472	1482	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(1) // "l"
1473	1483	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1474	1484	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1476	1486	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1477	1487	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1478	1488
1479		// Keyboard 2
1480		PORT_START
	1489	/* Keyboard 2 */
	1490	PORT_START_TAG("KEY5")
1481	1491	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
1482	1492	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
1483	1493	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2)
r2864	r2865
1485	1495	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
1486	1496	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1487	1497
1488		PORT_START
	1498	PORT_START_TAG("KEY6")
1489	1499	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2)
1490	1500	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2)
1491	1501	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
r2864	r2865
1493	1503	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
1494	1504	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1495	1505
1496		PORT_START
	1506	PORT_START_TAG("KEY7")
1497	1507	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
1498	1508	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
1499	1509	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
r2864	r2865
1501	1511	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
1502	1512	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1503	1513
1504		PORT_START
	1514	PORT_START_TAG("KEY8")
1505	1515	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
1506	1516	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
1507	1517	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
r2864	r2865
1509	1519	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1510	1520	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1511	1521
1512		PORT_START
	1522	PORT_START_TAG("KEY9")
1513	1523	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
1514	1524	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1515	1525	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1519	1529	INPUT_PORTS_END
1520	1530
1521	1531	static INPUT_PORTS_START( MAHJONG_KEYS_BET )
1522		// Keyboard 1
1523		PORT_START
	1532	/* Keyboard 1 */
	1533	PORT_START_TAG("KEY0")
1524	1534	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(1)
1525	1535	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(1)
1526	1536	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(1)
r2864	r2865
1528	1538	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(1)
1529	1539	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
1530	1540
1531		PORT_START
	1541	PORT_START_TAG("KEY1")
1532	1542	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(1)
1533	1543	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(1)
1534	1544	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(1)
r2864	r2865
1536	1546	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(1)
1537	1547	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(1)
1538	1548
1539		PORT_START
	1549	PORT_START_TAG("KEY2")
1540	1550	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(1)
1541	1551	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(1)
1542	1552	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(1)
r2864	r2865
1544	1554	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(1)
1545	1555	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1546	1556
1547		PORT_START
	1557	PORT_START_TAG("KEY3")
1548	1558	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(1)
1549	1559	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(1)
1550	1560	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(1)
r2864	r2865
1552	1562	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1553	1563	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1554	1564
1555		PORT_START
	1565	PORT_START_TAG("KEY4")
1556	1566	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(1) // "l"
1557	1567	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(1) // "t"
1558	1568	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(1) // "w"
r2864	r2865
1560	1570	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(1) // "b"
1561	1571	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(1) // "s"
1562	1572
1563		// Keyboard 2
1564		PORT_START
	1573	/* Keyboard 2 */
	1574	PORT_START_TAG("KEY5")
1565	1575	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
1566	1576	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
1567	1577	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2)
r2864	r2865
1569	1579	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
1570	1580	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1571	1581
1572		PORT_START
	1582	PORT_START_TAG("KEY6")
1573	1583	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2)
1574	1584	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2)
1575	1585	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
r2864	r2865
1577	1587	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
1578	1588	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2)
1579	1589
1580		PORT_START
	1590	PORT_START_TAG("KEY7")
1581	1591	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
1582	1592	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
1583	1593	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
r2864	r2865
1585	1595	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
1586	1596	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1587	1597
1588		PORT_START
	1598	PORT_START_TAG("KEY8")
1589	1599	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
1590	1600	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
1591	1601	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
r2864	r2865
1593	1603	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1594	1604	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1595	1605
1596		PORT_START
	1606	PORT_START_TAG("KEY9")
1597	1607	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
1598	1608	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
1599	1609	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
r2864	r2865
1603	1613	INPUT_PORTS_END
1604	1614
1605	1615	static INPUT_PORTS_START( HANAFUDA_KEYS )
1606		// Keyboard 1
1607		PORT_START
	1616	/* Keyboard 1 */
	1617	PORT_START_TAG("KEY0")
1608	1618	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
1609	1619	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD)
1610	1620	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1612	1622	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1613	1623	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
1614	1624
1615		PORT_START
	1625	PORT_START_TAG("KEY1")
1616	1626	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
1617	1627	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
1618	1628	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1620	1630	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1621	1631	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1622	1632
1623		PORT_START
	1633	PORT_START_TAG("KEY2")
1624	1634	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD)
1625	1635	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD)
1626	1636	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1628	1638	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1629	1639	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1630	1640
1631		PORT_START
	1641	PORT_START_TAG("KEY3")
1632	1642	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD)
1633	1643	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("8") PORT_CODE(KEYCODE_8_PAD)
1634	1644	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1636	1646	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1637	1647	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1638	1648
1639		PORT_START
	1649	PORT_START_TAG("KEY4")
1640	1650	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
1641	1651	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1642	1652	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1644	1654	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1645	1655	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1646	1656
1647		// Keyboard 2
1648		PORT_START
	1657	/* Keyboard 2 */
	1658	PORT_START_TAG("KEY5")
1649	1659	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
1650	1660	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
1651	1661	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2)
r2864	r2865
1653	1663	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
1654	1664	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1655	1665
1656		PORT_START
	1666	PORT_START_TAG("KEY6")
1657	1667	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2)
1658	1668	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2)
1659	1669	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
r2864	r2865
1661	1671	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
1662	1672	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1663	1673
1664		PORT_START
	1674	PORT_START_TAG("KEY7")
1665	1675	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
1666	1676	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
1667	1677	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
r2864	r2865
1669	1679	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
1670	1680	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1671	1681
1672		PORT_START
	1682	PORT_START_TAG("KEY8")
1673	1683	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
1674	1684	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
1675	1685	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
r2864	r2865
1677	1687	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1678	1688	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1679	1689
1680		PORT_START
	1690	PORT_START_TAG("KEY9")
1681	1691	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
1682	1692	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1683	1693	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1687	1697	INPUT_PORTS_END
1688	1698
1689	1699	static INPUT_PORTS_START( HANAFUDA_KEYS_BET )
1690		// Keyboard 1
1691		PORT_START
	1700	/* Keyboard 1 */
	1701	PORT_START_TAG("KEY0")
1692	1702	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
1693	1703	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD)
1694	1704	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1696	1706	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1697	1707	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
1698	1708
1699		PORT_START
	1709	PORT_START_TAG("KEY1")
1700	1710	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
1701	1711	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
1702	1712	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1704	1714	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1705	1715	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
1706	1716
1707		PORT_START
	1717	PORT_START_TAG("KEY2")
1708	1718	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD)
1709	1719	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD)
1710	1720	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1712	1722	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1713	1723	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1714	1724
1715		PORT_START
	1725	PORT_START_TAG("KEY3")
1716	1726	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD)
1717	1727	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("8") PORT_CODE(KEYCODE_8_PAD)
1718	1728	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1720	1730	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1721	1731	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1722	1732
1723		PORT_START
	1733	PORT_START_TAG("KEY4")
1724	1734	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(1) // "l"
1725	1735	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(1) // "t"
1726	1736	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(1) // "w"
r2864	r2865
1728	1738	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(1) // "b"
1729	1739	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(1) // "s"
1730	1740
1731		// Keyboard 2
1732		PORT_START
	1741	/* Keyboard 2 */
	1742	PORT_START_TAG("KEY5")
1733	1743	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
1734	1744	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
1735	1745	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2)
r2864	r2865
1737	1747	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
1738	1748	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1739	1749
1740		PORT_START
	1750	PORT_START_TAG("KEY6")
1741	1751	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2)
1742	1752	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2)
1743	1753	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
r2864	r2865
1745	1755	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
1746	1756	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2)
1747	1757
1748		PORT_START
	1758	PORT_START_TAG("KEY7")
1749	1759	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
1750	1760	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
1751	1761	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
r2864	r2865
1753	1763	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
1754	1764	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1755	1765
1756		PORT_START
	1766	PORT_START_TAG("KEY8")
1757	1767	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
1758	1768	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
1759	1769	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
r2864	r2865
1761	1771	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1762	1772	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1763	1773
1764		PORT_START
	1774	PORT_START_TAG("KEY9")
1765	1775	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
1766	1776	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
1767	1777	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
r2864	r2865
1822	1832	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1823	1833	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1824	1834
1825		PORT_START_TAG("IN2")
	1835	PORT_START_TAG("IN0")
1826	1836	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1827	1837	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1828	1838	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
r2864	r2865
1888	1898	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1889	1899	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1890	1900
1891		PORT_START_TAG("IN2")
	1901	PORT_START_TAG("IN0")
1892	1902	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN2 ) // Pay
1893	1903	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1894	1904	PORT_SERVICE_NO_TOGGLE(0x04, IP_ACTIVE_LOW ) // Test (there isn't a dip switch)
r2864	r2865
1951	1961	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1952	1962	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1953	1963
1954		PORT_START_TAG("IN2")
	1964	PORT_START_TAG("IN0")
1955	1965	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1956	1966	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1957	1967	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
r2864	r2865
1963	1973
1964	1974	PORT_INCLUDE( HANAFUDA_KEYS )
1965	1975
1966		PORT_START_TAG("IN13")
	1976	PORT_START_TAG("DSW2") /* IN13 */
1967	1977	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1968	1978	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1969	1979	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
1989	1999	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1990	2000	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1991	2001
1992		PORT_START_TAG("IN14")
	2002	PORT_START_TAG("DSW3") /* IN14 */
1993	2003	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1994	2004	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1995	2005	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
2018	2028
2019	2029
2020	2030	static INPUT_PORTS_START( sprtmtch )
2021		PORT_START_TAG("~~IN0~~")
	2031	PORT_START_TAG("P1")
2022	2032	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
2023	2033	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
2024	2034	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
r2864	r2865
2028	2038	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
2029	2039	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
2030	2040
2031		PORT_START_TAG("~~IN1~~")
	2041	PORT_START_TAG("P2")
2032	2042	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
2033	2043	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
2034	2044	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
r2864	r2865
2038	2048	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
2039	2049	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
2040	2050
2041		PORT_START_TAG("IN2")
	2051	PORT_START_TAG("IN0")
2042	2052	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(10)
2043	2053	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(10)
2044	2054	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
2148	2158	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2149	2159	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2150	2160
2151		PORT_START_TAG("IN2")
	2161	PORT_START_TAG("IN0")
2152	2162	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "17B"
2153	2163	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "18B"
2154	2164	PORT_SERVICE(0x04, IP_ACTIVE_LOW ) // Test (there isn't a dip switch)
r2864	r2865
2214	2224	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2215	2225	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2216	2226
2217		PORT_START_TAG("IN2")
	2227	PORT_START_TAG("IN0")
2218	2228	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "17B"
2219	2229	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "18B"
2220	2230	PORT_SERVICE_NO_TOGGLE(0x04, IP_ACTIVE_LOW) // Test (there isn't a dip switch)
r2864	r2865
2277	2287	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2278	2288	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
2279	2289
2280		PORT_START_TAG("IN2")
	2290	PORT_START_TAG("IN0")
2281	2291	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "17B"
2282	2292	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "18B"
2283	2293	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
r2864	r2865
2339	2349	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2340	2350	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
2341	2351
2342		PORT_START_TAG("IN2")
	2352	PORT_START_TAG("IN0")
2343	2353	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "17B"
2344	2354	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "18B"
2345	2355	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
r2864	r2865
2400	2410	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2401	2411	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
2402	2412
2403		PORT_START_TAG("IN2")
	2413	PORT_START_TAG("IN0")
2404	2414	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2405	2415	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2406	2416	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // Test, during boot
r2864	r2865
2410	2420	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
2411	2421	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2412	2422
2413		PORT_START_TAG("IN3")
	2423	/* Keyboard 1 */
	2424	PORT_START_TAG("KEY0")
2414	2425	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
2415	2426	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
2416	2427	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
r2864	r2865
2418	2429	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2419	2430	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_START1 )
2420	2431
2421		PORT_START_TAG("~~IN4~~")
	2432	PORT_START_TAG("KEY1")
2422	2433	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
2423		PORT_START_TAG("~~IN5~~")
	2434	PORT_START_TAG("KEY2")
2424	2435	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
2425		PORT_START_TAG("~~IN6~~")
	2436	PORT_START_TAG("KEY3")
2426	2437	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
2427		PORT_START_TAG("~~IN7~~")
	2438	PORT_START_TAG("KEY4")
2428	2439	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
2429	2440
2430		// Keyboard 2
2431		PORT_START_TAG("IN8")
	2441	/* Keyboard 2 */
	2442	PORT_START_TAG("KEY5")
2432	2443	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
2433	2444	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
2434	2445	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
r2864	r2865
2436	2447	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2437	2448	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_START2 )
2438	2449
2439		PORT_START_TAG("~~IN9~~")
	2450	PORT_START_TAG("KEY6")
2440	2451	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
2441		PORT_START_TAG("~~IN10~~")
	2452	PORT_START_TAG("KEY7")
2442	2453	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
2443		PORT_START_TAG("~~IN11~~")
	2454	PORT_START_TAG("KEY8")
2444	2455	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
2445		PORT_START_TAG("~~IN12~~")
	2456	PORT_START_TAG("KEY9")
2446	2457	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
2447	2458	INPUT_PORTS_END
2448	2459
r2864	r2865
2499	2510	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2500	2511	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
2501	2512
2502		PORT_START_TAG("IN2")
	2513	PORT_START_TAG("IN0")
2503	2514	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2504	2515	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2505	2516	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) // Test
r2864	r2865
2563	2574	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2564	2575	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
2565	2576
2566		PORT_START_TAG("IN2")
	2577	PORT_START_TAG("IN0")
2567	2578	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2568	2579	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2569	2580	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) // Test
r2864	r2865
2575	2586
2576	2587	PORT_INCLUDE( MAHJONG_KEYS )
2577	2588
2578		PORT_START_TAG("~~IN8~~")
	2589	PORT_START_TAG("DSW2")
2579	2590	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
2580	2591	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
2581	2592	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
2658	2669	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2659	2670	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2660	2671
2661		PORT_START_TAG("IN2")
	2672	PORT_START_TAG("IN0")
2662	2673	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2663	2674	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2664	2675	PORT_SERVICE_NO_TOGGLE(0x04, IP_ACTIVE_LOW )
r2864	r2865
2668	2679	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
2669	2680	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
2670	2681
2671		PORT_START_TAG("~~IN3~~")
	2682	PORT_START_TAG("KEY0")
2672	2683	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
2673	2684	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
2674	2685	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
r2864	r2865
2676	2687	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
2677	2688	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN)
2678	2689
2679		PORT_START_TAG("~~IN4~~")
	2690	PORT_START_TAG("KEY1")
2680	2691	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
2681	2692	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
2682	2693	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
r2864	r2865
2684	2695	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
2685	2696	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
2686	2697
2687		PORT_START_TAG("~~IN5~~")
	2698	PORT_START_TAG("KEY2")
2688	2699	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
2689	2700	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
2690	2701	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
r2864	r2865
2692	2703	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
2693	2704	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
2694	2705
2695		PORT_START_TAG("~~IN6~~")
	2706	PORT_START_TAG("KEY3")
2696	2707	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
2697	2708	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
2698	2709	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
r2864	r2865
2700	2711	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2701	2712	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
2702	2713
2703		PORT_START_TAG("~~IN7~~")
	2714	PORT_START_TAG("KEY4")
2704	2715	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2705	2716	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2706	2717	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
2711	2722
2712	2723
2713	2724	static INPUT_PORTS_START( mjelct3 )
2714		PORT_START_TAG("DSW2") // 7c21 (select = 00)
	2725	PORT_START_TAG("DSW2") /* 7c21 (select = 00) */
2715	2726	PORT_DIPNAME( 0x03, 0x03, "Difficulty?" )
2716	2727	PORT_DIPSETTING( 0x03, "0" ) // 20
2717	2728	PORT_DIPSETTING( 0x00, "1" ) // 32
r2864	r2865
2734	2745	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2735	2746	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2736	2747
2737		PORT_START_TAG("DSW1") // 7c20 (select = 40)
	2748	PORT_START_TAG("DSW1") /* 7c20 (select = 40) */
2738	2749	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate" )
2739	2750	PORT_DIPSETTING( 0x00, "50" )
2740	2751	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
2764	2775	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2765	2776	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2766	2777
2767		PORT_START_TAG("IN2")
	2778	PORT_START_TAG("IN0")
2768	2779	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE4 ) // Pay
2769	2780	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18B
2770	2781	PORT_SERVICE( 0x04, IP_ACTIVE_LOW ) // Test
r2864	r2865
2776	2787
2777	2788	PORT_INCLUDE( MAHJONG_KEYS_BET )
2778	2789
2779		PORT_START_TAG("DSW3") // 7c22 (select = 80)
	2790	PORT_START_TAG("DSW3") /* 7c22 (select = 80) */
2780	2791	PORT_DIPNAME( 0x07, 0x07, "YAKUMAN Bonus" )
2781	2792	PORT_DIPSETTING( 0x07, "Cut" )
2782	2793	PORT_DIPSETTING( 0x06, "1 T" )
r2864	r2865
2802	2813	PORT_DIPSETTING( 0x80, "None (Part 2)" )
2803	2814	PORT_DIPSETTING( 0x00, "Super Express (Part 3)" )
2804	2815
2805		PORT_START_TAG("DSW4") // 7c23 (select = c0)
	2816	PORT_START_TAG("DSW4") /* 7c23 (select = c0) */
2806	2817	PORT_DIPNAME( 0x01, 0x01, "Last Chance" )
2807	2818	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
2808	2819	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
2828	2839	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
2829	2840	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
2830	2841
2831		PORT_START_TAG("FAKE") // IN10 - Fake DSW
	2842	PORT_START_TAG("FAKE") /* IN10 - Fake DSW */
2832	2843	PORT_DIPNAME( 0xff, 0xff, "Allow Bets" )
2833	2844	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
2834	2845	PORT_DIPSETTING( 0xff, DEF_STR( On ) )
r2864	r2865
2836	2847
2837	2848
2838	2849	static INPUT_PORTS_START( mjelctrn )
2839		PORT_START_TAG("DSW2") // 7c21 (select = 00)
	2850	PORT_START_TAG("DSW2") /* 7c21 (select = 00) */
2840	2851	PORT_DIPNAME( 0x03, 0x03, "Difficulty?" )
2841	2852	PORT_DIPSETTING( 0x03, "0" ) // 20
2842	2853	PORT_DIPSETTING( 0x00, "1" ) // 32
r2864	r2865
2859	2870	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2860	2871	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2861	2872
2862		PORT_START_TAG("DSW1") // 7c20 (select = 40)
	2873	PORT_START_TAG("DSW1") /* 7c20 (select = 40) */
2863	2874	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate" )
2864	2875	PORT_DIPSETTING( 0x00, "50" )
2865	2876	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
2889	2900	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2890	2901	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2891	2902
2892		PORT_START_TAG("IN2")
	2903	PORT_START_TAG("IN0")
2893	2904	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE4 ) // Pay
2894	2905	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18B
2895	2906	PORT_SERVICE( 0x04, IP_ACTIVE_LOW ) // Test
r2864	r2865
2901	2912
2902	2913	PORT_INCLUDE( MAHJONG_KEYS_BET )
2903	2914
2904		PORT_START_TAG("DSW3") // 7c22 (select = 80)
	2915	PORT_START_TAG("DSW3") /* 7c22 (select = 80) */
2905	2916	PORT_DIPNAME( 0x07, 0x07, "YAKUMAN Bonus" )
2906	2917	PORT_DIPSETTING( 0x07, "Cut" )
2907	2918	PORT_DIPSETTING( 0x06, "1 T" )
r2864	r2865
2953	2964	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2954	2965	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2955	2966
2956		PORT_START_TAG("FAKE") // IN10 - Fake DSW
	2967	PORT_START_TAG("FAKE") /* IN10 - Fake DSW */
2957	2968	PORT_DIPNAME( 0xff, 0xff, "Allow Bets" )
2958	2969	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
2959	2970	PORT_DIPSETTING( 0xff, DEF_STR( On ) )
r2864	r2865
2961	2972
2962	2973
2963	2974	static INPUT_PORTS_START( majxtal7 )
2964		PORT_START_TAG("DSW2") // select = 00
	2975	PORT_START_TAG("DSW2") /* select = 00 */
2965	2976	PORT_DIPNAME( 0x03, 0x03, "Difficulty?" )
2966	2977	PORT_DIPSETTING( 0x03, "0" ) // 20
2967	2978	PORT_DIPSETTING( 0x00, "1" ) // 32
r2864	r2865
2984	2995	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2985	2996	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2986	2997
2987		PORT_START_TAG("DSW1") // select = 40
	2998	PORT_START_TAG("DSW1") /* select = 40 */
2988	2999	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate" )
2989	3000	PORT_DIPSETTING( 0x00, "50" )
2990	3001	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
3014	3025	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3015	3026	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3016	3027
3017		PORT_START_TAG("IN2")
	3028	PORT_START_TAG("IN0")
3018	3029	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE4 ) // Pay
3019	3030	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18B
3020	3031	PORT_SERVICE( 0x04, IP_ACTIVE_LOW ) // Test
r2864	r2865
3026	3037
3027	3038	PORT_INCLUDE( MAHJONG_KEYS_BET )
3028	3039
3029		PORT_START_TAG("DSW3") // select = 80
	3040	PORT_START_TAG("DSW3") /* select = 80 */
3030	3041	PORT_DIPNAME( 0x07, 0x07, "YAKUMAN Bonus" )
3031	3042	PORT_DIPSETTING( 0x07, "Cut" )
3032	3043	PORT_DIPSETTING( 0x06, "1 T" )
r2864	r2865
3052	3063	PORT_DIPSETTING( 0x80, "X-Tal" )
3053	3064	PORT_DIPSETTING( 0x00, "Diamond" )
3054	3065
3055		PORT_START_TAG("DSW4") // select = c0
	3066	PORT_START_TAG("DSW4") /* select = c0 */
3056	3067	PORT_DIPNAME( 0x01, 0x01, "Last Chance" )
3057	3068	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
3058	3069	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
3078	3089	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3079	3090	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3080	3091
3081		PORT_START_TAG("FAKE") // IN10 - Fake DSW
	3092	PORT_START_TAG("FAKE") /* IN10 - Fake DSW */
3082	3093	PORT_DIPNAME( 0xff, 0xff, DEF_STR( Unknown ) )
3083	3094	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
3084	3095	PORT_DIPSETTING( 0xff, DEF_STR( On ) )
3085	3096	INPUT_PORTS_END
3086	3097
3087	3098	static INPUT_PORTS_START( neruton )
3088		PORT_START_TAG("DSW2") //6a77 (select = 00)
	3099	PORT_START_TAG("DSW2") /* 6a77 (select = 00) */
3089	3100	PORT_DIPNAME( 0x07, 0x07, "Time Setting" )
3090	3101	PORT_DIPSETTING( 0x07, "08:30" )
3091	3102	PORT_DIPSETTING( 0x06, "09:00" )
r2864	r2865
3109	3120	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3110	3121	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
3111	3122
3112		PORT_START_TAG("DSW1") // 6a76 (select = 40)
	3123	PORT_START_TAG("DSW1") /* 6a76 (select = 40) */
3113	3124	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
3114	3125	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
3115	3126	PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
r2864	r2865
3134	3145	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3135	3146	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3136	3147
3137		PORT_START_TAG("IN2")
	3148	PORT_START_TAG("IN0")
3138	3149	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 17B
3139	3150	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18B
3140	3151	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // Test
r2864	r2865
3145	3156	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18A
3146	3157
3147	3158	PORT_INCLUDE( MAHJONG_KEYS )
	3159
	3160	/* 2008-06 FP: the following are needed to make happy the read handlers shared with mjelctrn*/
	3161	PORT_START_TAG("DSW3")
	3162	PORT_START_TAG("DSW4")
	3163	PORT_START_TAG("FAKE")
3148	3164	INPUT_PORTS_END
3149	3165
3150	3166
3151	3167	static INPUT_PORTS_START( tenkai )
3152		PORT_START // 0
	3168	PORT_START_TAG("DSW0")
3153	3169	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate" )
3154	3170	PORT_DIPSETTING( 0x00, "50" )
3155	3171	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
3178	3194	PORT_DIPSETTING( 0x40, "10" )
3179	3195	PORT_DIPSETTING( 0x00, "20" )
3180	3196
3181		PORT_START // 1
	3197	PORT_START_TAG("DSW1")
3182	3198	PORT_DIPNAME( 0x03, 0x03, "Unknown 1-0&1" )
3183	3199	PORT_DIPSETTING( 0x03, "1:1" )
3184	3200	PORT_DIPSETTING( 0x02, "1:2" )
r2864	r2865
3202	3218	PORT_DIPSETTING( 0x00, "1" )
3203	3219	PORT_DIPSETTING( 0x80, "2" )
3204	3220
3205		PORT_START // 2
	3221	PORT_START_TAG("DSW2")
3206	3222	PORT_DIPNAME( 0x01, 0x01, "Unknown 2-0" )
3207	3223	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3208	3224	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3228	3244	PORT_DIPSETTING( 0x80, "Start" )
3229	3245	PORT_DIPSETTING( 0x00, "Flip Flop" )
3230	3246
3231		PORT_START // 3
	3247	PORT_START_TAG("DSW3")
3232	3248	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
3233	3249	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3234	3250	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3254	3270	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3255	3271	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3256	3272
3257		PORT_START // 4 (top)
	3273	PORT_START_TAG("DSW4") /* (top) */
3258	3274	PORT_DIPNAME( 0x01, 0x01, "Credits Per Note" )
3259	3275	PORT_DIPSETTING( 0x01, "5" )
3260	3276	PORT_DIPSETTING( 0x00, "10" )
r2864	r2865
3280	3296	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3281	3297	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3282	3298
3283		PORT_START ~~// 5~~
	3299	PORT_START_TAG("IN0")
3284	3300	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE4 ) // Pay
3285	3301	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18B
3286	3302	PORT_SERVICE( 0x04, IP_ACTIVE_LOW ) // Test
r2864	r2865
3295	3311
3296	3312
3297	3313	static INPUT_PORTS_START( mjreach )
3298		PORT_START // 0
	3314	PORT_START_TAG("DSW0")
3299	3315	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate" )
3300	3316	PORT_DIPSETTING( 0x00, "50" )
3301	3317	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
3324	3340	PORT_DIPSETTING( 0x40, "10" )
3325	3341	PORT_DIPSETTING( 0x00, "20" )
3326	3342
3327		PORT_START // 1
	3343	PORT_START_TAG("DSW1")
3328	3344	PORT_DIPNAME( 0x03, 0x03, "Unknown 1-0&1" )
3329	3345	PORT_DIPSETTING( 0x03, "1:1" )
3330	3346	PORT_DIPSETTING( 0x02, "1:2" )
r2864	r2865
3348	3364	PORT_DIPSETTING( 0x00, "1" )
3349	3365	PORT_DIPSETTING( 0x80, "2" )
3350	3366
3351		PORT_START // 2
	3367	PORT_START_TAG("DSW2")
3352	3368	PORT_DIPNAME( 0x01, 0x01, "Unknown 2-0" )
3353	3369	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3354	3370	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3374	3390	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3375	3391	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3376	3392
3377		PORT_START // 3
	3393	PORT_START_TAG("DSW3")
3378	3394	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
3379	3395	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3380	3396	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3400	3416	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3401	3417	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3402	3418
3403		PORT_START // 4 (top)
	3419	PORT_START_TAG("DSW4") /* 4 (top) */
3404	3420	PORT_DIPNAME( 0x01, 0x01, "Credits Per Note" )
3405	3421	PORT_DIPSETTING( 0x01, "5" )
3406	3422	PORT_DIPSETTING( 0x00, "10" )
r2864	r2865
3425	3441	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3426	3442	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3427	3443
3428		PORT_START ~~// 5~~
	3444	PORT_START_TAG("IN0")
3429	3445	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE4 ) // Pay
3430	3446	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18B
3431	3447	PORT_SERVICE( 0x04, IP_ACTIVE_LOW ) // Test
r2864	r2865
3439	3455	INPUT_PORTS_END
3440	3456
3441	3457	static INPUT_PORTS_START( htengoku )
3442		PORT_START // IN0
	3458	PORT_START_TAG("IN0")
3443	3459	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE4 ) // medal out
3444	3460	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
3445	3461	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
r2864	r2865
3451	3467
3452	3468	PORT_INCLUDE( HANAFUDA_KEYS_BET )
3453	3469
3454		PORT_START // IN11 - DSW1
	3470	PORT_START_TAG("DSW0") /* IN11 - DSW1 */
3455	3471	PORT_DIPNAME( 0x01, 0x01, "Show Girls" )
3456	3472	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
3457	3473	PORT_DIPSETTING( 0x01, DEF_STR( Yes ) )
r2864	r2865
3477	3493	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3478	3494	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3479	3495
3480		PORT_START // IN12 - DSW2
	3496	PORT_START_TAG("DSW1") /* IN12 - DSW2 */
3481	3497	PORT_DIPNAME( 0x07, 0x05, "Payout Rate" )
3482	3498	PORT_DIPSETTING( 0x00, "Lowest" )
3483	3499	PORT_DIPSETTING( 0x01, "Lower" )
r2864	r2865
3502	3518	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3503	3519	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3504	3520
3505		PORT_START // IN13 - DSW3
	3521	PORT_START_TAG("DSW2") /* IN13 - DSW3 */
3506	3522	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
3507	3523	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
3508	3524	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r2864	r2865
3525	3541	PORT_DIPSETTING( 0x40, "3000" )
3526	3542	PORT_DIPSETTING( 0x00, "5000" )
3527	3543
3528		PORT_START // IN14 - DSW4
	3544	PORT_START_TAG("DSW3") /* IN14 - DSW4 */
3529	3545	PORT_DIPNAME( 0x03, 0x03, "Odds For Goko" )
3530	3546	PORT_DIPSETTING( 0x03, "100" )
3531	3547	PORT_DIPSETTING( 0x02, "200" )
r2864	r2865
3548	3564	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3549	3565	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3550	3566
3551		PORT_START // IN15 - DSWs top bits
	3567	PORT_START_TAG("DSW4") /* IN15 - DSWs top bits */
3552	3568	PORT_SERVICE( 0x01, IP_ACTIVE_LOW )
3553	3569	PORT_DIPNAME( 0x02, 0x02, "Set Clock" )
3554	3570	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )

src/mame/drivers/megadriv.c
r2864	r2865
370	370	megadrive_vdp_address &=0xffff;
371	371	}
372	372
373		static void write_cram_value(int offset, int data)
	373	static void write_cram_value(running_machine *machine, int offset, int data)
374	374	{
375	375	megadrive_vdp_cram[offset] = data;
376	376
r2864	r2865
381	381	r = ((data >> 1)&0x07);
382	382	g = ((data >> 5)&0x07);
383	383	b = ((data >> 9)&0x07);
384		palette_set_color_rgb(Machine,offset,pal3bit(r),pal3bit(g),pal3bit(b));
	384	palette_set_color_rgb(machine,offset,pal3bit(r),pal3bit(g),pal3bit(b));
385	385	megadrive_vdp_palette_lookup[offset] = (b<<2) \| (g<<7) \| (r<<12);
386	386	megadrive_vdp_palette_lookup_shadow[offset] = (b<<1) \| (g<<6) \| (r<<11);
387	387	megadrive_vdp_palette_lookup_highlight[offset] = ((b\|0x08)<<1) \| ((g\|0x08)<<6) \| ((r\|0x08)<<11);
r2864	r2865
389	389	}
390	390	}
391	391
392		static void vdp_cram_write(UINT16 data)
	392	static void vdp_cram_write(running_machine *machine, UINT16 data)
393	393	{
394	394	int offset;
395	395	offset = (megadrive_vdp_address&0x7e)>>1;
396	396
397		write_cram_value(offset,data);
	397	write_cram_value(machine, offset,data);
398	398
399	399	megadrive_vdp_address+=MEGADRIVE_REG0F_AUTO_INC;
400	400
r2864	r2865
402	402	}
403	403
404	404
405		static void megadriv_vdp_data_port_w(int data)
	405	static void megadriv_vdp_data_port_w(running_machine *machine, int data)
406	406	{
407	407	megadrive_vdp_command_pending = 0;
408	408
r2864	r2865
471	471	break;
472	472
473	473	case 0x0003:
474		vdp_cram_write(data);
	474	vdp_cram_write(machine, data);
475	475	break;
476	476
477	477	case 0x0004:
r2864	r2865
498	498
499	499
500	500
501		static void megadrive_vdp_set_register(int regnum, UINT8 value)
	501	static void megadrive_vdp_set_register(running_machine *machine, int regnum, UINT8 value)
502	502	{
503	503	megadrive_vdp_register[regnum] = value;
504	504
r2864	r2865
513	513	if (megadrive_irq4_pending)
514	514	{
515	515	if (MEGADRIVE_REG0_IRQ4_ENABLE)
516		cpunum_set_input_line(Machine, 0,4,HOLD_LINE);
	516	cpunum_set_input_line(machine, 0,4,HOLD_LINE);
517	517	else
518		cpunum_set_input_line(Machine, 0,4,CLEAR_LINE);
	518	cpunum_set_input_line(machine, 0,4,CLEAR_LINE);
519	519	}
520	520
521	521	/* ??? Fatal Rewind needs this but I'm not sure it's accurate behavior
r2864	r2865
530	530	if (megadrive_irq6_pending)
531	531	{
532	532	if (MEGADRIVE_REG01_IRQ6_ENABLE)
533		cpunum_set_input_line(Machine, 0,6,HOLD_LINE);
	533	cpunum_set_input_line(machine, 0,6,HOLD_LINE);
534	534	else
535		cpunum_set_input_line(Machine, 0,6,CLEAR_LINE);
	535	cpunum_set_input_line(machine, 0,6,CLEAR_LINE);
536	536	}
537	537
538	538	/* ??? */
r2864	r2865
660	660	}
661	661
662	662
663		static void megadrive_do_insta_68k_to_cram_dma(UINT32 source,UINT16 length)
	663	static void megadrive_do_insta_68k_to_cram_dma(running_machine *machine,UINT32 source,UINT16 length)
664	664	{
665	665	int count;
666	666
r2864	r2865
670	670	{
671	671	//if (megadrive_vdp_address>=0x80) return; // abandon
672	672
673		write_cram_value((megadrive_vdp_address&0x7e)>>1, vdp_get_word_from_68k_mem(source));
	673	write_cram_value(machine, (megadrive_vdp_address&0x7e)>>1, vdp_get_word_from_68k_mem(source));
674	674	source+=2;
675	675
676	676	if (source>0xffffff) source = 0xfe0000;
r2864	r2865
716	716	}
717	717
718	718	/* This can be simplified quite a lot.. */
719		static void handle_dma_bits(void)
	719	static void handle_dma_bits(running_machine *machine)
720	720	{
721	721
722	722	if (megadrive_vdp_code&0x20)
r2864	r2865
778	778
779	779	/* The 68k is frozen during this transfer, it should be safe to throw a few cycles away and do 'instant' DMA because the 68k can't detect it being in progress (can the z80?) */
780	780	//mame_printf_debug("68k->CRAM DMA transfer source %06x length %04x dest %04x enabled %01x\n", source, length, megadrive_vdp_address,MEGADRIVE_REG01_DMA_ENABLE);
781		if (MEGADRIVE_REG01_DMA_ENABLE) megadrive_do_insta_68k_to_cram_dma(source,length);
	781	if (MEGADRIVE_REG01_DMA_ENABLE) megadrive_do_insta_68k_to_cram_dma(machine,source,length);
782	782	}
783	783	else if (MEGADRIVE_REG17_DMATYPE==0x2)
784	784	{
r2864	r2865
848	848	}
849	849	}
850	850
851		static void megadriv_vdp_ctrl_port_w(int data)
	851	static void megadriv_vdp_ctrl_port_w(running_machine *machine, int data)
852	852	{
853	853	// logerror("write to vdp control port %04x\n",data);
854	854	megadrive_vram_fill_pending = 0; // ??
r2864	r2865
860	860	megadrive_vdp_command_part2 = data;
861	861
862	862	update_megadrive_vdp_code_and_address();
863		handle_dma_bits();
	863	handle_dma_bits(machine);
864	864
865	865	//logerror("VDP Write Part 2 setting Code %02x Address %04x\n",megadrive_vdp_code, megadrive_vdp_address);
866	866
r2864	r2865
874	874
875	875	if (regnum &0x20) mame_printf_debug("reg error\n");
876	876
877		megadrive_vdp_set_register(regnum&0x1f,value);
	877	megadrive_vdp_set_register(machine, regnum&0x1f,value);
878	878	megadrive_vdp_code = 0;
879	879	megadrive_vdp_address = 0;
880	880	}
r2864	r2865
905	905	data = (data&0xff00) \| data>>8;
906	906	// mame_printf_debug("8-bit write VDP data port access, offset %04x data %04x mem_mask %04x\n",offset,data,mem_mask);
907	907	}
908		megadriv_vdp_data_port_w(data);
	908	megadriv_vdp_data_port_w(machine, data);
909	909	break;
910	910
911	911	case 0x04:
912	912	case 0x06:
913	913	if ((!ACCESSING_BITS_8_15) \|\| (!ACCESSING_BITS_0_7)) mame_printf_debug("8-bit write VDP control port access, offset %04x data %04x mem_mask %04x\n",offset,data,mem_mask);
914		megadriv_vdp_ctrl_port_w(data);
	914	megadriv_vdp_ctrl_port_w(machine, data);
915	915	break;
916	916
917	917	case 0x08:
r2864	r2865
950	950	return megadrive_vdp_cram[(megadrive_vdp_address&0x7e)>>1];
951	951	}
952	952
953		static UINT16 megadriv_vdp_data_port_r(void)
	953	static UINT16 megadriv_vdp_data_port_r(running_machine *machine)
954	954	{
955	955	UINT16 retdata=0;
956	956
957		//return mame_rand(Machine);
	957	//return mame_rand(machine);
958	958
959	959	megadrive_vdp_command_pending = 0;
960	960
r2864	r2865
968	968
969	969	case 0x0001:
970	970	logerror("Attempting to READ from DATA PORT in VRAM WRITE MODE\n");
971		retdata = mame_rand(Machine);
	971	retdata = mame_rand(machine);
972	972	break;
973	973
974	974	case 0x0003:
975	975	logerror("Attempting to READ from DATA PORT in CRAM WRITE MODE\n");
976		retdata = mame_rand(Machine);
	976	retdata = mame_rand(machine);
977	977	break;
978	978
979	979	case 0x0004:
r2864	r2865
994	994
995	995	default:
996	996	logerror("Attempting to READ from DATA PORT in #UNDEFINED# MODE\n");
997		retdata = mame_rand(Machine);
	997	retdata = mame_rand(machine);
998	998	break;
999	999	}
1000	1000
r2864	r2865
1294	1294	case 0x00:
1295	1295	case 0x02:
1296	1296	if ((!ACCESSING_BITS_8_15) \|\| (!ACCESSING_BITS_0_7)) mame_printf_debug("8-bit VDP read data port access, offset %04x mem_mask %04x\n",offset,mem_mask);
1297		retvalue = megadriv_vdp_data_port_r();
	1297	retvalue = megadriv_vdp_data_port_r(machine);
1298	1298	break;
1299	1299
1300	1300	case 0x04:
r2864	r2865
1438	1438	/* pointers to our io data read/write functions */
1439	1439	static UINT8 (*megadrive_io_read_data_port_ptr)(int offset);
1440	1440	static void (*megadrive_io_write_data_port_ptr)(int offset, UINT16 data);
	1441
1441	1442	INPUT_PORTS_START( megadri6 )
1442		PORT_START /* Joypad 1 (6 button + start + mode) NOT READ DIRECTLY */
	1443	PORT_START_TAG("PAD1") /* Joypad 1 (6 button + start + mode) NOT READ DIRECTLY */
1443	1444	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1444	1445	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1445	1446	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1454	1455	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON8 ) PORT_PLAYER(1) PORT_NAME("P1 MODE") // mode
1455	1456
1456	1457
1457		PORT_START /* Joypad 1 (6 button + start + mode) NOT READ DIRECTLY */
	1458	PORT_START_TAG("PAD2") /* Joypad 2 (6 button + start + mode) NOT READ DIRECTLY */
1458	1459	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1459	1460	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1460	1461	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1468	1469	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON7 ) PORT_PLAYER(2) PORT_NAME("P2 Z") // z
1469	1470	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON8 ) PORT_PLAYER(2) PORT_NAME("P2 MODE") // mode
1470	1471
1471		PORT_START /* 3rd I/O port */
	1472	PORT_START_TAG("IN0") /* 3rd I/O port */
1472	1473
1473		PORT_START_TAG("RESET") /* Buttons on Genesis Console */
	1474	PORT_START_TAG("RESET") /* Buttons on Genesis Console */
1474	1475	PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_SERVICE1 ) PORT_NAME("Reset Button") PORT_IMPULSE(1) // reset, resets 68k (and..?)
1475	1476
1476		PORT_START_TAG("REGION") /* Buttons on Genesis Console */
	1477	PORT_START_TAG("REGION") /* Buttons on Genesis Console */
1477	1478	/* Region setting for Console */
1478	1479	PORT_DIPNAME( 0x000f, 0x0000, DEF_STR( Region ) )
1479	1480	PORT_DIPSETTING( 0x0000, "Use HazeMD Default Choice" )
r2864	r2865
1486	1487
1487	1488
1488	1489	INPUT_PORTS_START( ssf2ghw )
1489		PORT_START /* Joypad 1 (6 button + start + mode) NOT READ DIRECTLY */
	1490	PORT_START_TAG("PAD1") /* Joypad 1 (6 button + start + mode) NOT READ DIRECTLY */
1490	1491	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1491	1492	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1492	1493	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1501	1502	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNUSED )
1502	1503
1503	1504
1504		PORT_START /* Joypad 1 (6 button + start + mode) NOT READ DIRECTLY */
	1505	PORT_START_TAG("PAD2") /* Joypad 1 (6 button + start + mode) NOT READ DIRECTLY */
1505	1506	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1506	1507	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1507	1508	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1515	1516	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(2)
1516	1517	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNUSED )
1517	1518
1518		PORT_START /* 3rd I/O port */
	1519	PORT_START_TAG("IN0") /* 3rd I/O port */
1519	1520	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
1520	1521	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
1521	1522
1522		// PORT_START_TAG("RESET") /* Buttons on Genesis Console */
	1523	// PORT_START_TAG("RESET") /* Buttons on Genesis Console */
1523	1524	// PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_SERVICE1 ) PORT_NAME("Reset Button") PORT_IMPULSE(1) // reset, resets 68k (and..?)
1524	1525
1525		// PORT_START_TAG("REGION") /* Buttons on Genesis Console */
	1526	// PORT_START_TAG("REGION") /* Buttons on Genesis Console */
1526	1527	// /* Region setting for Console */
1527	1528	// PORT_DIPNAME( 0x000f, 0x0000, DEF_STR( Region ) )
1528	1529	// PORT_DIPSETTING( 0x0000, "Use HazeMD Default Choice" )
r2864	r2865
1616	1617	*/
1617	1618
1618	1619	INPUT_PORTS_START( megadriv )
1619		PORT_START /* Joypad 1 (3 button + start) NOT READ DIRECTLY */
	1620	PORT_START_TAG("PAD1") /* Joypad 1 (3 button + start) NOT READ DIRECTLY */
1620	1621	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1621	1622	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1622	1623	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1626	1627	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) PORT_NAME("P1 C") // c
1627	1628	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1) PORT_NAME("P1 START") // start
1628	1629
1629		PORT_START /* Joypad 2 (3 button + start) NOT READ DIRECTLY */
	1630	PORT_START_TAG("PAD2") /* Joypad 2 (3 button + start) NOT READ DIRECTLY */
1630	1631	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1631	1632	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1632	1633	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1636	1637	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) PORT_NAME("P2 C") // c
1637	1638	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2) PORT_NAME("P2 START") // start
1638	1639
1639		PORT_START /* 3rd I/O port */
	1640	PORT_START_TAG("IN0") /* 3rd I/O port */
1640	1641
1641		PORT_START_TAG("RESET") /* Buttons on Genesis Console */
	1642	PORT_START_TAG("RESET") /* Buttons on Genesis Console */
1642	1643	PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_SERVICE1 ) PORT_NAME("Reset Button") PORT_IMPULSE(1) // reset, resets 68k (and..?)
1643	1644
1644		PORT_START_TAG("REGION") /* Region setting for Console */
	1645	PORT_START_TAG("REGION") /* Region setting for Console */
1645	1646	/* Region setting for Console */
1646	1647	PORT_DIPNAME( 0x000f, 0x0000, DEF_STR( Region ) )
1647	1648	PORT_DIPSETTING( 0x0000, "Use HazeMD Default Choice" )
r2864	r2865
1652	1653
1653	1654
1654	1655	INPUT_PORTS_START( aladbl )
1655		PORT_START /* Joypad 1 (3 button + start) NOT READ DIRECTLY */
	1656	PORT_START_TAG("PAD1") /* Joypad 1 (3 button + start) NOT READ DIRECTLY */
1656	1657	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1657	1658	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1658	1659	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1662	1663	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) PORT_NAME("P1 Jump") // c
1663	1664	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START1 ) // start
1664	1665
1665		PORT_START /* Joypad 2 (3 button + start) NOT READ DIRECTLY - not used */
	1666	PORT_START_TAG("PAD2") /* Joypad 2 (3 button + start) NOT READ DIRECTLY - not used */
1666	1667	// PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1667	1668	// PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1668	1669	// PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1672	1673	// PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) PORT_NAME("P2 Jump") // c
1673	1674	// PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START2 ) // start
1674	1675
1675		PORT_START /* 3rd I/O port */
	1676	PORT_START_TAG("IN0") /* 3rd I/O port */
1676	1677
1677		// PORT_START_TAG("RESET") /* Buttons on Genesis Console */
	1678	// PORT_START_TAG("RESET") /* Buttons on Genesis Console */
1678	1679	// PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_SERVICE1 ) PORT_NAME("Reset Button") PORT_IMPULSE(1) // reset, resets 68k (and..?)
1679	1680
1680		// PORT_START_TAG("REGION") /* Region setting for Console */
	1681	// PORT_START_TAG("REGION") /* Region setting for Console */
1681	1682	// /* Region setting for Console */
1682	1683	// PORT_DIPNAME( 0x000f, 0x0000, DEF_STR( Region ) )
1683	1684	// PORT_DIPSETTING( 0x0000, "Use HazeMD Default Choice" )
r2864	r2865
1707	1708	PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1) /* needed to avoid credits getting mad */
1708	1709	INPUT_PORTS_END
1709	1710
	1711	#define MODE_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x800) >> 11 )
	1712	#define Z_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x400) >> 10 )
	1713	#define Y_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x200) >> 9 )
	1714	#define X_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x100) >> 8 )
1710	1715
1711		#define MODE_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x800) >> 11 )
1712		#define Z_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x400) >> 10 )
1713		#define Y_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x200) >> 9 )
1714		#define X_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x100) >> 8 )
1715
1716
1717	1716	#define START_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x80) >> 7 )
1718		#define C_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x40) >> 6 )
1719		#define B_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x20) >> 5 )
1720		#define A_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x10) >> 4 )
	1717	#define C_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x40) >> 6 )
	1718	#define B_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x20) >> 5 )
	1719	#define A_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x10) >> 4 )
1721	1720	#define RIGHT_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x08) >> 3 )
1722		#define LEFT_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x04) >> 2 )
1723		#define DOWN_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x02) >> 1 )
1724		#define UP_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x01) >> 0 )
1725		#define MD_RESET_BUTTON ( (input_port_read_safe(Machine, "RESET",0x00) & 0x01) >> 0 )
	1721	#define LEFT_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x04) >> 2 )
	1722	#define DOWN_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x02) >> 1 )
	1723	#define UP_BUTTON(player) ( (input_port_read_indexed(Machine, player) & 0x01) >> 0 )
	1724	#define MD_RESET_BUTTON ( (input_port_read_safe(Machine, "RESET", 0x00) & 0x01) >> 0 )
1726	1725
1727	1726	static UINT8 megadrive_io_data_regs[3];
1728	1727	static UINT8 megadrive_io_ctrl_regs[3];
r2864	r2865
4755	4754	/* default state of z80 = reset, with bus */
4756	4755	mame_printf_debug("Resetting Megadrive / Genesis\n");
4757	4756
4758		switch (input_port_read_safe(machine, "REGION",0x00))
	4757	switch (input_port_read_safe(machine, "REGION", 0x00))
4759	4758	{
4760	4759
4761	4760	case 1: // US

src/mame/drivers/galpani3.c
r2864	r2865
110	110
111	111	static INPUT_PORTS_START( galpani3 )
112	112
113		PORT_START // IN0 - Player Controls
	113	PORT_START_TAG("P1") /* IN0 - Player Controls */
114	114	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
115	115	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
116	116	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
120	120	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN ) // ?
121	121	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED )
122	122
123		PORT_START // IN1 - Player Controls
	123	PORT_START_TAG("P2") /* IN1 - Player Controls */
124	124	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
125	125	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
126	126	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
130	130	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN ) // ?
131	131	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED )
132	132
133		PORT_START // IN2 - Coins
	133	PORT_START_TAG("COIN") /* IN2 - Coins */
134	134	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
135	135	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
136	136	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
r2864	r2865
140	140	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SERVICE1 )
141	141	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED )
142	142
143		PORT_START // IN3 - DSW provided by the MCU - $200386.b <- $400200
	143	PORT_START_TAG("DSW") /* IN3 - DSW provided by the MCU - $200386.b <- $400200 */
144	144	PORT_DIPNAME( 0x0100, 0x0100, "Test Mode" )
145	145	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
146	146	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
215	215	{
216	216	case 0x03: // DSW
217	217	{
218		mcu_ram[mcu_offset] = input_port_read_indexed(machine, 3);
219		logerror("PC=%06X : MCU executed command: %04X %04X (read DSW)\n",activecpu_get_pc(),mcu_command,mcu_offset*2);
	218	mcu_ram[mcu_offset] = input_port_read(machine, "DSW");
	219	logerror("PC=%06X : MCU executed command: %04X %04X (read DSW)\n", activecpu_get_pc(), mcu_command, mcu_offset*2);
220	220	}
221	221	break;
222	222

src/mame/drivers/itech32.c
r2864	r2865
286	286	}
287	287
288	288
289		void itech32_update_interrupts(int vint, int xint, int qint)
	289	void itech32_update_interrupts(running_machine *machine, int vint, int xint, int qint)
290	290	{
291	291	int level = determine_irq_state(vint, xint, qint);
292	292
293	293	/* update it */
294	294	if (level)
295		cpunum_set_input_line(Machine, 0, level, ASSERT_LINE);
	295	cpunum_set_input_line(machine, 0, level, ASSERT_LINE);
296	296	else
297		cpunum_set_input_line(Machine, 0, 7, CLEAR_LINE);
	297	cpunum_set_input_line(machine, 0, 7, CLEAR_LINE);
298	298	}
299	299
300	300
301	301	static INTERRUPT_GEN( generate_int1 )
302	302	{
303	303	/* signal the NMI */
304		itech32_update_interrupts(1, -1, -1);
	304	itech32_update_interrupts(machine, 1, -1, -1);
305	305	if (FULL_LOGGING) logerror("------------ VBLANK (%d) --------------\n", video_screen_get_vpos(machine->primary_screen));
306	306	}
307	307
308	308
309	309	static WRITE16_HANDLER( int1_ack_w )
310	310	{
311		itech32_update_interrupts(0, -1, -1);
	311	itech32_update_interrupts(machine, 0, -1, -1);
312	312	}
313	313
314	314

src/mame/drivers/filetto.c
r2864	r2865
301	301	{
302	302	printf("Read Prototyping card [%02x] @ PC=%05x\n",offset,activecpu_get_pc());
303	303	if(offset == 1)
304		return input_port_read~~_indexed~~(machine, 1);
	304	return input_port_read(machine, "DSW");
305	305
306	306	return disk_data[offset];
307	307	}
r2864	r2865
565	565	AM_RANGE(0x02f8, 0x02ff) AM_RAM //Modem port
566	566
567	567	AM_RANGE(0x0310, 0x0311) AM_READWRITE(disk_iobank_r,disk_iobank_w) //Prototyping card (???)
568		AM_RANGE(0x0312, 0x0312) AM_READ~~(input~~_~~port_~~0_r)
	568	AM_RANGE(0x0312, 0x0312) AM_READ_PORT("IN0")
569	569
570	570	// AM_RANGE(0x0300, 0x031f) AM_RAM //Prototyping card (???)
571	571	AM_RANGE(0x0378, 0x037f) AM_RAM //printer (parallel) port
r2864	r2865
582	582	ADDRESS_MAP_END
583	583
584	584	static INPUT_PORTS_START( filetto )
585		PORT_START
	585	PORT_START_TAG("IN0")
586	586	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) //START1
587	587	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_2WAY PORT_PLAYER(1)
588	588	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_2WAY PORT_PLAYER(1)
r2864	r2865
602	602	DSW2
603	603	<unused>
604	604	*/
605		PORT_START
	605	PORT_START_TAG("DSW")
606	606	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
607	607	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
608	608	PORT_DIPSETTING( 0x00, DEF_STR( On ) )

src/mame/drivers/findout.c
r2864	r2865
66	66
67	67	static READ8_HANDLER( port1_r )
68	68	{
69		return input_port_read~~_indexed~~(machine, 1) \| (ticket_dispenser_0_r(machine, 0) >> 5);
	69	return input_port_read(machine, "IN0") \| (ticket_dispenser_0_r(machine, 0) >> 5);
70	70	}
71	71
72	72	static WRITE8_HANDLER( lamps_w )
r2864	r2865
230	230	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
231	231	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
232	232	\
233		PORT_START /* IN1 */\
	233	PORT_START_TAG("IN1") /* IN1 */\
234	234	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("1 Left A-Z") \
235	235	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("2 Right A-Z") \
236	236	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("3 Select Letter") \
r2864	r2865
251	251	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
252	252	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
253	253	\
254		PORT_START /* IN1 */\
	254	PORT_START_TAG("IN1") /* IN1 */\
255	255	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) \
256	256	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) \
257	257	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) \
r2864	r2865
262	262	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
263	263
264	264	static INPUT_PORTS_START( reelfun )
265		PORT_START
	265	PORT_START_TAG("DSWA")
266	266	PORT_DIPNAME( 0x07, 0x01, "Coinage Multiplier" )
267	267	PORT_DIPSETTING( 0x07, "7" )
268	268	PORT_DIPSETTING( 0x06, "6" )
r2864	r2865
292	292	INPUT_PORTS_END
293	293
294	294	static INPUT_PORTS_START( findout )
295		PORT_START /* DSW A */
	295	PORT_START_TAG("DSWA") /* DSW A */
296	296	PORT_DIPNAME( 0x07, 0x01, DEF_STR( Coinage ) )
297	297	PORT_DIPSETTING( 0x07, DEF_STR( 7C_1C ) )
298	298	PORT_DIPSETTING( 0x06, DEF_STR( 6C_1C ) )
r2864	r2865
322	322	INPUT_PORTS_END
323	323
324	324	static INPUT_PORTS_START( gt103 )
325		PORT_START /* DSW A */
	325	PORT_START_TAG("DSWA") /* DSW A */
326	326	PORT_DIPNAME( 0x07, 0x01, "Coinage Multiplier" )
327	327	PORT_DIPSETTING( 0x07, "7" )
328	328	PORT_DIPSETTING( 0x06, "6" )
r2864	r2865
352	352	INPUT_PORTS_END
353	353
354	354	static INPUT_PORTS_START( gt103a )
355		PORT_START_TAG ("DSWA")
	355	PORT_START_TAG("DSWA")
356	356	PORT_DIPNAME( 0x03, 0x01, "Questions" )
357	357	PORT_DIPSETTING( 0x00, "4" )
358	358	PORT_DIPSETTING( 0x01, "5" )
r2864	r2865
389	389	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
390	390	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
391	391
392		PORT_START /* IN1 */
	392	PORT_START_TAG("IN1") /* IN1 */
393	393	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
394	394	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
395	395	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 )
r2864	r2865
414	414	INPUT_PORTS_END
415	415
416	416	static INPUT_PORTS_START( gt507uk )
417		PORT_START /* DSW A */
	417	PORT_START_TAG("DSWA") /* DSW A */
418	418	PORT_DIPNAME( 0x01, 0x00, "If Ram Error" )
419	419	PORT_DIPSETTING( 0x01, "Freeze" )
420	420	PORT_DIPSETTING( 0x00, "Play" )

src/mame/drivers/deco32.c
r2864	r2865
329	329	{
330	330	/* Protection/IO chip 75, same as Lemmings & Robocop 2 */
331	331	switch (offset<<2) {
332		case 0x0a0: return input_port_read_indexed(machine, 0); /* Player 1 & 2 controls */
333		case 0x158: return input_port_read_indexed(machine, 1); /* Player 3 & 4 controls */
334		case 0xed4: return input_port_read_indexed(machine, 2); /* Misc */
	332	case 0x0a0: return input_port_read(machine, "IN0"); /* Player 1 & 2 controls */
	333	case 0x158: return input_port_read(machine, "IN1"); /* Player 3 & 4 controls */
	334	case 0xed4: return input_port_read(machine, "IN2"); /* Misc */
335	335	}
336	336
337	337	logerror("%08x: Unmapped protection read %04x\n",activecpu_get_pc(),offset<<2);
r2864	r2865
341	341	static READ32_HANDLER( captaven_soundcpu_r )
342	342	{
343	343	/* Top byte - top bit low == sound cpu busy, bottom word is dips */
344		return 0xffff0000 \| input_port_read~~_indexed~~(machine, 3);
	344	return 0xffff0000 \| input_port_read(machine, "DSW");
345	345	}
346	346
347	347	static READ32_HANDLER( fghthist_control_r )
348	348	{
349	349	switch (offset) {
350		case 0: return 0xffff0000 \| input_port_read_indexed(machine, 0);
351		case 1: return 0xffff0000 \| input_port_read_indexed(machine, 1); //check top bits??
	350	case 0: return 0xffff0000 \| input_port_read(machine, "IN0");
	351	case 1: return 0xffff0000 \| input_port_read(machine, "IN1"); //check top bits??
352	352	case 2: return 0xfffffffe \| eeprom_read_bit();
353	353	}
354	354
r2864	r2865
373	373	static READ32_HANDLER( dragngun_service_r )
374	374	{
375	375	// logerror("%08x:Read service\n",activecpu_get_pc());
376		return input_port_read~~_indexed~~(machine, 3);
	376	return input_port_read(machine, "IN2");
377	377	}
378	378
379	379	static READ32_HANDLER( lockload_gun_mirror_r )
r2864	r2865
381	381	//logerror("%08x:Read gun %d\n",activecpu_get_pc(),offset);
382	382	//return ((mame_rand(machine)%0xffff)<<16) \| mame_rand(machine)%0xffff;
383	383	if (offset) /* Mirror of player 1 and player 2 fire buttons */
384		return input_port_read_indexed(machine, 5) \| ((mame_rand(machine)%0xff)<<16);
385		return input_port_read_indexed(machine, 4) \| input_port_read_indexed(machine, 6) \| (input_port_read_indexed(machine, 6)<<16) \| (input_port_read_indexed(machine, 6)<<24); //((mame_rand(machine)%0xff)<<16);
	384	return input_port_read(machine, "IN4") \| ((mame_rand(machine)%0xff)<<16);
	385	return input_port_read(machine, "IN3") \| input_port_read(machine, "LIGHT0_X") \| (input_port_read(machine, "LIGHT0_X")<<16) \| (input_port_read(machine, "LIGHT0_X")<<24); //((mame_rand(machine)%0xff)<<16);
386	386	}
387	387
388	388	static READ32_HANDLER( dragngun_prot_r )
r2864	r2865
396	396	//definitely vblank in locked load
397	397
398	398	switch (offset<<1) {
399		case 0x140/2: return 0xffff0000 \| input_port_read_indexed(machine, 0); /* IN0 */
400		case 0xadc/2: return 0xffff0000 \| input_port_read_indexed(machine, 1) \| strobe; /* IN1 */
401		case 0x6a0/2: return 0xffff0000 \| input_port_read_indexed(machine, 2); /* IN2 (Dip switch) */
	399	case 0x140/2: return 0xffff0000 \| input_port_read(machine, "IN0"); /* IN0 */
	400	case 0xadc/2: return 0xffff0000 \| input_port_read(machine, "IN1") \| strobe; /* IN1 */
	401	case 0x6a0/2: return 0xffff0000 \| input_port_read(machine, "DSW"); /* IN2 (Dip switch) */
402	402	}
403	403	return 0xffffffff;
404	404	}
r2864	r2865
409	409	{
410	410	/* Ports 0-3 are read, but seem unused */
411	411	switch (dragngun_lightgun_port) {
412		case 4: return input_port_read_indexed(machine, 4); break;
413		case 5: return input_port_read_indexed(machine, 5); break;
414		case 6: return input_port_read_indexed(machine, 6); break;
415		case 7: return input_port_read_indexed(machine, 7); break;
	412	case 4: return input_port_read(machine, "LIGHT0_X"); break;
	413	case 5: return input_port_read(machine, "LIGHT1_X"); break;
	414	case 6: return input_port_read(machine, "LIGHT0_Y"); break;
	415	case 7: return input_port_read(machine, "LIGHT1_Y"); break;
416	416	}
417	417
418	418	// logerror("Illegal lightgun port %d read \n",dragngun_lightgun_port);
r2864	r2865
458	458	static READ32_HANDLER( tattass_prot_r )
459	459	{
460	460	switch (offset<<1) {
461		case 0x280: return input_port_read_indexed(machine, 0) << 16; /* IN0 */
462		case 0x4c4: return input_port_read_indexed(machine, 1) << 16; /* IN1 */
	461	case 0x280: return input_port_read(machine, "IN0") << 16;
	462	case 0x4c4: return input_port_read(machine, "IN1") << 16;
463	463	case 0x35a: return tattass_eprom_bit << 16;
464	464	}
465	465
r2864	r2865
621	621	{
622	622
623	623	switch (offset<<1) {
624		case 0x280: return input_port_read_indexed(machine, 0) << 16\| 0xffff; /* IN0 */
625		case 0x4c4: return input_port_read_indexed(machine, 1) << 16\| 0xffff; /* IN1 */
	624	case 0x280: return input_port_read(machine, "IN0") << 16\| 0xffff; /* IN0 */
	625	case 0x4c4: return input_port_read(machine, "IN1") << 16\| 0xffff; /* IN1 */
626	626	case 0x35a: return (eeprom_read_bit()<< 16) \| 0xffff; // Debug switch in low word??
627	627	}
628	628
r2864	r2865
1244	1244	*/
1245	1245
1246	1246	static INPUT_PORTS_START( captaven )
1247		PORT_START
	1247	PORT_START_TAG("IN0")
1248	1248	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1249	1249	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1250	1250	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1262	1262	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
1263	1263	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
1264	1264
1265		PORT_START
	1265	PORT_START_TAG("IN1")
1266	1266	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
1267	1267	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
1268	1268	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
r2864	r2865
1280	1280	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
1281	1281	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED )
1282	1282
1283		PORT_START
	1283	PORT_START_TAG("IN2")
1284	1284	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
1285	1285	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
1286	1286	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN3 )
r2864	r2865
1298	1298	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
1299	1299	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED )
1300	1300
1301		PORT_START /* Dip switch bank 1 */
	1301	PORT_START_TAG("DSW") /* Dip switch bank 1 */
1302	1302	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )
1303	1303	PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
1304	1304	PORT_DIPSETTING( 0x0001, DEF_STR( 2C_1C ) )
r2864	r2865
1350	1350	INPUT_PORTS_END
1351	1351
1352	1352	static INPUT_PORTS_START( fghthist )
1353		PORT_START
	1353	PORT_START_TAG("IN0")
1354	1354	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
1355	1355	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
1356	1356	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
r2864	r2865
1368	1368	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1369	1369	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
1370	1370
1371		PORT_START
	1371	PORT_START_TAG("IN1")
1372	1372	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
1373	1373	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
1374	1374	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
1388	1388	INPUT_PORTS_END
1389	1389
1390	1390	static INPUT_PORTS_START( dragngun )
1391		PORT_START
	1391	PORT_START_TAG("IN0")
1392	1392	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
1393	1393	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNUSED )
1394	1394	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
1406	1406	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
1407	1407	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
1408	1408
1409		PORT_START
	1409	PORT_START_TAG("IN1")
1410	1410	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
1411	1411	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
1412	1412	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
1424	1424	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
1425	1425	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED )
1426	1426
1427		PORT_START
	1427	PORT_START_TAG("DSW")
1428	1428	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED ) /* Would be a dipswitch, but only 1 present on board */
1429	1429	PORT_DIPNAME( 0x0100, 0x0000, "Reset" ) /* Behaves like Reset */
1430	1430	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
r2864	r2865
1451	1451	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
1452	1452	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
1453	1453
1454		PORT_START
	1454	PORT_START_TAG("IN2")
1455	1455	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_VBLANK )
1456	1456	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
1457	1457	PORT_SERVICE( 0x0004, IP_ACTIVE_LOW )
r2864	r2865
1461	1461	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN )
1462	1462	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
1463	1463
1464		PORT_START
	1464	PORT_START_TAG("LIGHT0_X")
1465	1465	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_SENSITIVITY(20) PORT_KEYDELTA(25) PORT_PLAYER(1)
1466	1466
1467		PORT_START
	1467	PORT_START_TAG("LIGHT1_X")
1468	1468	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_SENSITIVITY(20) PORT_KEYDELTA(25) PORT_PLAYER(2)
1469	1469
1470		PORT_START
	1470	PORT_START_TAG("LIGHT0_Y")
1471	1471	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(25) PORT_PLAYER(1)
1472	1472
1473		PORT_START
	1473	PORT_START_TAG("LIGHT1_Y")
1474	1474	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(25) PORT_PLAYER(2)
1475	1475	INPUT_PORTS_END
1476	1476
1477	1477	static INPUT_PORTS_START( lockload )
1478		PORT_START
	1478	PORT_START_TAG("IN0")
1479	1479	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
1480	1480	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNUSED )
1481	1481	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
1493	1493	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
1494	1494	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
1495	1495
1496		PORT_START
	1496	PORT_START_TAG("IN1")
1497	1497	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
1498	1498	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
1499	1499	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )
1500	1500	PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_SPECIAL ) //check //test BUTTON F2
1501	1501	PORT_BIT( 0xfff0, IP_ACTIVE_LOW, IPT_UNUSED )
1502	1502
1503		PORT_START
	1503	PORT_START_TAG("DSW")
1504	1504	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED ) /* Would be a dipswitch, but only 1 present on board */
1505	1505	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Free_Play ) )
1506	1506	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
r2864	r2865
1527	1527	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
1528	1528	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
1529	1529
1530		PORT_START
	1530	PORT_START_TAG("IN2")
1531	1531	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_VBLANK ) //IPT_VBLANK )
1532	1532	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNUSED )
1533	1533	PORT_SERVICE( 0x0004, IP_ACTIVE_LOW )
1534	1534	PORT_BIT( 0x00f8, IP_ACTIVE_LOW, IPT_UNUSED ) //check //test BUTTON F2
1535	1535
1536		PORT_START
	1536	PORT_START_TAG("IN3")
1537	1537	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) /* mirror of fire buttons */
1538	1538	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
1539	1539
1540		PORT_START
	1540	PORT_START_TAG("IN4")
1541	1541	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
1542	1542	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
1543	1543
1544		PORT_START
	1544	PORT_START_TAG("LIGHT0_X")
1545	1545	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(20) PORT_KEYDELTA(25) PORT_PLAYER(1)
1546	1546
1547		PORT_START
	1547	PORT_START_TAG("LIGHT0_Y")
1548	1548	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(20) PORT_KEYDELTA(25) PORT_PLAYER(1)
1549	1549
1550		PORT_START
	1550	PORT_START_TAG("LIGHT1_X")
1551	1551	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(20) PORT_KEYDELTA(25) PORT_PLAYER(2)
1552	1552
1553		PORT_START
	1553	PORT_START_TAG("LIGHT1_Y")
1554	1554	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(20) PORT_KEYDELTA(25) PORT_PLAYER(2)
1555	1555	INPUT_PORTS_END
1556	1556
1557	1557	static INPUT_PORTS_START( tattass )
1558		PORT_START
	1558	PORT_START_TAG("IN0")
1559	1559	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1560	1560	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1561	1561	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1573	1573	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1574	1574	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
1575	1575
1576		PORT_START
	1576	PORT_START_TAG("IN1")
1577	1577	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
1578	1578	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
1579	1579	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
1593	1593	INPUT_PORTS_END
1594	1594
1595	1595	static INPUT_PORTS_START( nslasher )
1596		PORT_START
	1596	PORT_START_TAG("IN0")
1597	1597	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1598	1598	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1599	1599	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1611	1611	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1612	1612	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
1613	1613
1614		PORT_START
	1614	PORT_START_TAG("IN1")
1615	1615	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
1616	1616	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
1617	1617	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
3277	3277
3278	3278	deco156_decrypt();
3279	3279
3280		soundlatch_setclearedvalue(0xff);
	3280	soundlatch_setclearedvalue(machine, 0xff);
3281	3281
3282	3282	/* The board for Night Slashers is very close to the Fighter's History and
3283	3283	Tattoo Assassins boards, but has an encrypted ARM cpu. */

src/mame/drivers/midzeus.c
r2864	r2865
1326	1326	static DRIVER_INIT( mk4 )
1327	1327	{
1328	1328	dcs2_init(machine, 0, 0);
1329		midway_ioasic_init(MIDWAY_IOASIC_STANDARD, 461/* or 474 */, 94, NULL);
	1329	midway_ioasic_init(machine, MIDWAY_IOASIC_STANDARD, 461/* or 474 */, 94, NULL);
1330	1330	midway_ioasic_set_shuffle_state(1);
1331	1331	}
1332	1332
r2864	r2865
1334	1334	static DRIVER_INIT( invasn )
1335	1335	{
1336	1336	dcs2_init(machine, 0, 0);
1337		midway_ioasic_init(MIDWAY_IOASIC_STANDARD, 468/* or 488 */, 94, NULL);
	1337	midway_ioasic_init(machine, MIDWAY_IOASIC_STANDARD, 468/* or 488 */, 94, NULL);
1338	1338	memory_install_readwrite32_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x9c0000, 0x9c0000, 0, 0, invasn_gun_r, invasn_gun_w);
1339	1339	}
1340	1340
r2864	r2865
1342	1342	static DRIVER_INIT( crusnexo )
1343	1343	{
1344	1344	dcs2_init(machine, 0, 0);
1345		midway_ioasic_init(MIDWAY_IOASIC_STANDARD, 472/* or 476,477,478,110 */, 99, NULL);
	1345	midway_ioasic_init(machine, MIDWAY_IOASIC_STANDARD, 472/* or 476,477,478,110 */, 99, NULL);
1346	1346	memory_configure_bank(1, 0, 3, memory_region(REGION_USER2), 0x400000*4);
1347	1347
1348	1348	memory_install_readwrite32_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x9b0004, 0x9b0007, 0, 0, crusnexo_leds_r, crusnexo_leds_w);
r2864	r2865
1353	1353	static DRIVER_INIT( thegrid )
1354	1354	{
1355	1355	dcs2_init(machine, 0, 0);
1356		midway_ioasic_init(MIDWAY_IOASIC_STANDARD, 474/* or 491 */, 99, NULL);
	1356	midway_ioasic_init(machine, MIDWAY_IOASIC_STANDARD, 474/* or 491 */, 99, NULL);
1357	1357	memory_configure_bank(1, 0, 3, memory_region(REGION_USER2), 0x400000*4);
1358	1358	}
1359	1359

src/mame/drivers/grchamp.c
r2864	r2865
42	42	***************************************************************************/
43	43
44	44	#include "driver.h"
45		#include "deprecat.h"
46	45	#include "cpu/z80/z80.h"
47	46	#include "sound/ay8910.h"
48	47	#include "grchamp.h"
r2864	r2865
79	78	static MACHINE_START( grchamp )
80	79	{
81	80	/* if the coin system is 1 way, lock Coin B (Page 40) */
82		if (input_port_read~~_indexed~~(machine, 1) & 0x10)
	81	if (input_port_read(machine, "DSWB") & 0x10)
83	82	coin_lockout_w(1, 1);
84	83	}
85	84
r2864	r2865
337	336	*
338	337	*************************************/
339	338
340		INLINE UINT8 get_pc3259_bits(grchamp_state *state, int offs)
	339	INLINE UINT8 get_pc3259_bits(running_machine machine, grchamp_state state, int offs)
341	340	{
342	341	int bits;
343	342
344	343	/* force a partial update to the current position */
345		video_screen_update_partial(Machine->primary_screen, video_screen_get_vpos(Machine->primary_screen));
	344	video_screen_update_partial(machine->primary_screen, video_screen_get_vpos(machine->primary_screen));
346	345
347	346	/* get the relevant 4 bits */
348	347	bits = (state->collide >> (offs*4)) & 0x0f;
r2864	r2865
355	354	static READ8_HANDLER( pc3259_0_r )
356	355	{
357	356	grchamp_state *state = machine->driver_data;
358		return get_pc3259_bits(state, 0);
	357	return get_pc3259_bits(machine, state, 0);
359	358	}
360	359
361	360
362	361	static READ8_HANDLER( pc3259_1_r )
363	362	{
364	363	grchamp_state *state = machine->driver_data;
365		return get_pc3259_bits(state, 1);
	364	return get_pc3259_bits(machine, state, 1);
366	365	}
367	366
368	367
369	368	static READ8_HANDLER( pc3259_2_r )
370	369	{
371	370	grchamp_state *state = machine->driver_data;
372		return get_pc3259_bits(state, 2);
	371	return get_pc3259_bits(machine, state, 2);
373	372	}
374	373
375	374
376	375	static READ8_HANDLER( pc3259_3_r )
377	376	{
378	377	grchamp_state *state = machine->driver_data;
379		return get_pc3259_bits(state, 3);
	378	return get_pc3259_bits(machine, state, 3);
380	379	}
381	380
382	381

src/mame/drivers/goodejan.c
r2864	r2865
79	79
80	80	switch(goodejan_mux_data)
81	81	{
82		case 1: ret = input_port_read_indexed(machine, 1); break;
83		case 2: ret = input_port_read_indexed(machine, 2); break;
84		case 4: ret = input_port_read_indexed(machine, 3); break;
85		case 8: ret = input_port_read_indexed(machine, 4); break;
86		case 0x10: ret = input_port_read_indexed(machine, 5); break;
	82	case 1: ret = input_port_read(machine, "KEY0"); break;
	83	case 2: ret = input_port_read(machine, "KEY1"); break;
	84	case 4: ret = input_port_read(machine, "KEY2"); break;
	85	case 8: ret = input_port_read(machine, "KEY3"); break;
	86	case 0x10: ret = input_port_read(machine, "KEY4"); break;
87	87	}
88	88
89	89	return ret;
r2864	r2865
126	126	static INPUT_PORTS_START( goodejan )
127	127	SEIBU_COIN_INPUTS /* coin inputs read through sound cpu */
128	128
129		PORT_START
	129	PORT_START_TAG("KEY0")
130	130	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
131	131	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
132	132	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
r2864	r2865
136	136	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
137	137	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
138	138
139		PORT_START
	139	PORT_START_TAG("KEY1")
140	140	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
141	141	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
142	142	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
r2864	r2865
146	146	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
147	147	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
148	148
149		PORT_START
	149	PORT_START_TAG("KEY2")
150	150	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
151	151	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
152	152	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
r2864	r2865
156	156	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
157	157	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
158	158
159		PORT_START
	159	PORT_START_TAG("KEY3")
160	160	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
161	161	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
162	162	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
r2864	r2865
166	166	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
167	167	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
168	168
169		PORT_START
	169	PORT_START_TAG("KEY4")
170	170	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE )
171	171	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE )
172	172	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP )
r2864	r2865
176	176	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
177	177	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
178	178
179		PORT_START
180		PORT_DIPNAME( 0x0001, 0x0001, "4" )
181		PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
182		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
183		PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
184		PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
185		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
186		PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
187		PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
188		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
189		PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
190		PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
191		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
192		PORT_DIPNAME( 0x0010, 0x0000, DEF_STR( Unknown ) ) // Freezes if off?
193		PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
194		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
195		PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
196		PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
197		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
198		PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
199		PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
200		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
201		PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
202		PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
203		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
204		PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) )
205		PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
206		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
207		PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
208		PORT_DIPSETTING( 0x0200, DEF_STR( Off ) )
209		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
210		PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
211		PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
212		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
213		PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
214		PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
215		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
216		PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
217		PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
218		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
219		PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
220		PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
221		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
222		PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
223		PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
224		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
225		PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
226		PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
227		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	179	PORT_START_TAG("DSW")
	180	PORT_DIPNAME( 0x0001, 0x0001, "4" )
	181	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
	182	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	183	PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
	184	PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
	185	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	186	PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
	187	PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
	188	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	189	PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
	190	PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
	191	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	192	PORT_DIPNAME( 0x0010, 0x0000, DEF_STR( Unknown ) ) // Freezes if off?
	193	PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
	194	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	195	PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
	196	PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
	197	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	198	PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
	199	PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
	200	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	201	PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
	202	PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
	203	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	204	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) )
	205	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
	206	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	207	PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
	208	PORT_DIPSETTING( 0x0200, DEF_STR( Off ) )
	209	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	210	PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
	211	PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
	212	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	213	PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
	214	PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
	215	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	216	PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
	217	PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
	218	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	219	PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
	220	PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
	221	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	222	PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
	223	PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
	224	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	225	PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
	226	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
	227	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
228	228	INPUT_PORTS_END
229	229
230	230

src/mame/drivers/aleck64.c
r2864	r2865
417	417
418	418	static INTERRUPT_GEN( n64_vblank )
419	419	{
420		signal_rcp_interrupt(VI_INTERRUPT);
	420	signal_rcp_interrupt(machine, VI_INTERRUPT);
421	421	}
422	422
423	423	static MACHINE_RESET( aleck64 )
424	424	{
425		n64_machine_reset();
	425	n64_machine_reset(machine);
426	426	}
427	427
428	428	static MACHINE_DRIVER_START( aleck64 )

src/mame/drivers/karnov.c
r2864	r2865
38	38	*******************************************************************************/
39	39
40	40	#include "driver.h"
41		#include "deprecat.h"
42	41	#include "sound/2203intf.h"
43	42	#include "sound/3812intf.h"
44	43
r2864	r2865
61	60	/******************************************************************************/
62	61
63	62	/* Emulation of the protected microcontroller - for coins & general protection */
64		static void karnov_i8751_w(int data)
	63	static void karnov_i8751_w(running_machine *machine, int data)
65	64	{
66	65	/* Pending coin operations may cause protection commands to be queued */
67	66	if (i8751_needs_ack) {
r2864	r2865
87	86
88	87	// if (!i8751_return && data!=0x300) logerror("CPU %04x - Unknown Write %02x intel\n",activecpu_get_pc(),data);
89	88
90		cpunum_set_input_line(Machine, 0,6,HOLD_LINE); /* Signal main cpu task is complete */
	89	cpunum_set_input_line(machine, 0,6,HOLD_LINE); /* Signal main cpu task is complete */
91	90	i8751_needs_ack=1;
92	91	}
93	92
94		static void wndrplnt_i8751_w(int data)
	93	static void wndrplnt_i8751_w(running_machine *machine, int data)
95	94	{
96	95	/* The last command hasn't been ACK'd (probably a conflict with coin command) */
97	96	if (i8751_needs_ack) {
r2864	r2865
141	140	if (data==0x501) i8751_return=0x6bf8;
142	141	if (data==0x500) i8751_return=0x4e75;
143	142
144		cpunum_set_input_line(Machine, 0,6,HOLD_LINE); /* Signal main cpu task is complete */
	143	cpunum_set_input_line(machine, 0,6,HOLD_LINE); /* Signal main cpu task is complete */
145	144	i8751_needs_ack=1;
146	145	}
147	146
148		static void chelnov_i8751_w(int data)
	147	static void chelnov_i8751_w(running_machine *machine, int data)
149	148	{
150	149	static int level;
151	150
r2864	r2865
251	250
252	251	// logerror("CPU %04x - Unknown Write %02x intel\n",activecpu_get_pc(),data);
253	252
254		cpunum_set_input_line(Machine, 0,6,HOLD_LINE); /* Signal main cpu task is complete */
	253	cpunum_set_input_line(machine, 0,6,HOLD_LINE); /* Signal main cpu task is complete */
255	254	i8751_needs_ack=1;
256	255	}
257	256
r2864	r2865
292	291	break;
293	292
294	293	case 6: /* SECREQ (Interrupt & Data to i8751) */
295		if (microcontroller_id==KARNOV \|\| microcontroller_id==KARNOVJ) karnov_i8751_w(data);
296		if (microcontroller_id==CHELNOV \|\| microcontroller_id==CHELNOVJ \|\| microcontroller_id==CHELNOVW) chelnov_i8751_w(data);
297		if (microcontroller_id==WNDRPLNT) wndrplnt_i8751_w(data);
	294	if (microcontroller_id==KARNOV \|\| microcontroller_id==KARNOVJ) karnov_i8751_w(machine, data);
	295	if (microcontroller_id==CHELNOV \|\| microcontroller_id==CHELNOVJ \|\| microcontroller_id==CHELNOVW) chelnov_i8751_w(machine, data);
	296	if (microcontroller_id==WNDRPLNT) wndrplnt_i8751_w(machine, data);
298	297	break;
299	298
300	299	case 8: /* HSHIFT (9 bits) - Top bit indicates video flip */
r2864	r2865
652	651	static int latch;
653	652
654	653	/* Coin input to the i8751 generates an interrupt to the main cpu */
655		if (input_port_read_indexed(machine, 3) == coin_mask) latch=1;
656		if (input_port_read_indexed(machine, 3) != coin_mask && latch) {
	654	if (input_port_read(machine, "FAKE") == coin_mask) latch=1;
	655	if (input_port_read(machine, "FAKE") != coin_mask && latch) {
657	656	if (i8751_needs_ack) {
658	657	/* i8751 is busy - queue the command */
659		i8751_coin_pending=input_port_read~~_indexed~~(machine, 3) \| 0x8000;
	658	i8751_coin_pending=input_port_read(machine, "FAKE") \| 0x8000;
660	659	} else {
661		i8751_return=input_port_read~~_indexed~~(machine, 3) \| 0x8000;
	660	i8751_return=input_port_read(machine, "FAKE") \| 0x8000;
662	661	cpunum_set_input_line(machine, 0,6,HOLD_LINE);
663	662	i8751_needs_ack=1;
664	663	}

src/mame/drivers/vegas.c
r2864	r2865
1345	1345	/* bit 0x01 seems to be used to reset the IOASIC */
1346	1346	if (!(data & 0x01))
1347	1347	{
1348		midway_ioasic_reset();
	1348	midway_ioasic_reset(machine);
1349	1349	dcs_reset_w(data & 0x01);
1350	1350	}
1351	1351
r2864	r2865
1473	1473
1474	1474	static WRITE32_HANDLER( asic_fifo_w )
1475	1475	{
1476		midway_ioasic_fifo_w(data);
	1476	midway_ioasic_fifo_w(machine, data);
1477	1477	}
1478	1478
1479	1479
r2864	r2865
1523	1523
1524	1524	static WRITE32_HANDLER( dcs3_fifo_full_w )
1525	1525	{
1526		midway_ioasic_fifo_full_w(data);
	1526	midway_ioasic_fifo_full_w(machine, data);
1527	1527	}
1528	1528
1529	1529
r2864	r2865
2461	2461	};
2462	2462
2463	2463	/* initialize the subsystems */
2464		midway_ioasic_init(ioasic, serialnum, 80, ioasic_irq);
	2464	midway_ioasic_init(machine, ioasic, serialnum, 80, ioasic_irq);
2465	2465	midway_ioasic_set_auto_ack(1);
2466	2466	smc91c94_init(&ethernet_intf);
2467	2467

src/mame/drivers/kopunch.c
r2864	r2865
18	18	{
19	19	if (cpu_getiloops() == 0)
20	20	{
21		if (~input_port_read~~_indexed~~(machine, 1) & 0x80) /* coin 1 */
	21	if (~input_port_read(machine, "IN1") & 0x80) /* coin 1 */
22	22	{
23	23	cpunum_set_input_line_and_vector(machine, 0,0,HOLD_LINE,0xf7); /* RST 30h */
24	24	return;
25	25	}
26		else if (~input_port_read~~_indexed~~(machine, 1) & 0x08) /* coin 2 */
	26	else if (~input_port_read(machine, "IN1") & 0x08) /* coin 2 */
27	27	{
28	28	cpunum_set_input_line_and_vector(machine, 0,0,HOLD_LINE,0xef); /* RST 28h */
29	29	return;
r2864	r2865
39	39	if (offset == 0)
40	40	return mame_rand(machine);
41	41	else
42		return (mame_rand(machine) & 0x07) \| input_port_read~~_indexed~~(machine, 1);
	42	return (mame_rand(machine) & 0x07) \| input_port_read(machine, "IN1");
43	43	}
44	44
45	45	static WRITE8_HANDLER( kopunch_lamp_w )
r2864	r2865
70	70	ADDRESS_MAP_END
71	71
72	72	static ADDRESS_MAP_START( kopunch_io_map, ADDRESS_SPACE_IO, 8 )
73		AM_RANGE(0x30, 0x30) AM_READ~~(input~~_~~port_~~0_r)
	73	AM_RANGE(0x30, 0x30) AM_READ_PORT("IN0")
74	74	AM_RANGE(0x31, 0x32) AM_READ(kopunch_in_r)
75	75	AM_RANGE(0x33, 0x33) AM_WRITENOP
76	76	AM_RANGE(0x34, 0x34) AM_WRITE(kopunch_coin_w)
r2864	r2865
79	79	AM_RANGE(0x37, 0x37) AM_WRITENOP
80	80	AM_RANGE(0x38, 0x38) AM_WRITE(kopunch_lamp_w)
81	81	AM_RANGE(0x39, 0x39) AM_WRITENOP
82		AM_RANGE(0x3a, 0x3a) AM_READ~~(input~~_~~port_2_r~~)
	82	AM_RANGE(0x3a, 0x3a) AM_READ_PORT("DSW")
83	83	AM_RANGE(0x3b, 0x3b) AM_WRITENOP
84	84	AM_RANGE(0x3c, 0x3c) AM_WRITE(kopunch_scroll_x_w)
85	85	AM_RANGE(0x3d, 0x3d) AM_WRITE(kopunch_scroll_y_w)
r2864	r2865
89	89
90	90
91	91	static INPUT_PORTS_START( kopunch )
92		PORT_START
	92	PORT_START_TAG("IN0")
93	93	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
94	94	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
95	95	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
r2864	r2865
99	99	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
100	100	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 )
101	101
102		PORT_START
	102	PORT_START_TAG("IN1")
103	103	PORT_BIT( 0x07, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* punch strength (high 3 bits) */
104	104	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(1)
105	105	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
r2864	r2865
107	107	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
108	108	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(1)
109	109
110		PORT_START
	110	PORT_START_TAG("DSW")
111	111	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
112	112	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
113	113	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
133	133	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
134	134	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
135	135
136		PORT_START
	136	PORT_START_TAG("IN2")
137	137	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_COCKTAIL
138	138	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_COCKTAIL
139	139	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_COCKTAIL

src/mame/drivers/enigma2.c
r2864	r2865
324	324	if (protection_data != 0xff)
325	325	ret = protection_data ^ 0x88;
326	326	else
327		ret = input_port_read~~_indexed~~(machine, 2);
	327	ret = input_port_read(machine, "DSW");
328	328	break;
329	329
330	330	case 0x02:
r2864	r2865
370	370
371	371	static WRITE8_HANDLER( enigma2_flip_screen_w )
372	372	{
373		engima2_flip_screen = ((data >> 5) & 0x01) && ((input_port_read~~_indexed~~(machine, 2) & 0x20) == 0x20);
	373	engima2_flip_screen = ((data >> 5) & 0x01) && ((input_port_read(machine, "DSW") & 0x20) == 0x20);
374	374	}
375	375
376	376
r2864	r2865
453	453
454	454
455	455	static INPUT_PORTS_START( enigma2 )
456		PORT_START
	456	PORT_START_TAG("IN0")
457	457	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
458	458	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
459	459	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START1 )
460	460	PORT_BIT( 0x78, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(p1_controls_r, 0)
461	461	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
462	462
463		PORT_START
	463	PORT_START_TAG("IN1")
464	464	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
465	465	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNUSED )
466	466	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
467	467	PORT_BIT( 0x78, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(p2_controls_r, 0)
468	468	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
469	469
470		PORT_START
	470	PORT_START_TAG("DSW")
471	471	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Lives ) )
472	472	PORT_DIPSETTING( 0x00, "3" )
473	473	PORT_DIPSETTING( 0x01, "4" )
r2864	r2865
507	507
508	508
509	509	static INPUT_PORTS_START( enigma2a )
510		PORT_START
	510	PORT_START_TAG("IN0")
511	511	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
512	512	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
513	513	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START1 )
r2864	r2865
515	515	PORT_BIT( 0x70, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(p1_controls_r, 0)
516	516	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
517	517
518		PORT_START
	518	PORT_START_TAG("IN1")
519	519	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
520	520	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNUSED )
521	521	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
r2864	r2865
523	523	PORT_BIT( 0x70, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(p2_controls_r, 0)
524	524	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
525	525
526		PORT_START
	526	PORT_START_TAG("DSW")
527	527	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Lives ) )
528	528	PORT_DIPSETTING( 0x00, "3" )
529	529	PORT_DIPSETTING( 0x01, "4" )

src/mame/drivers/segaorun.c
r2864	r2865
58	58	*************************************/
59	59
60	60	extern void fd1094_machine_init(void);
61		extern void fd1094_driver_init(void (set_decrypted)(UINT8 ));
	61	extern void fd1094_driver_init(running_machine machine, void (set_decrypted)(UINT8 *));
62	62
63	63	static READ16_HANDLER( misc_io_r );
64	64	static WRITE16_HANDLER( misc_io_w );
r2864	r2865
154	154	segaic16_memory_mapper_init(machine, 0, outrun_info, sound_data_w, NULL);
155	155
156	156	/* init the FD1094 */
157		fd1094_driver_init(segaic16_memory_mapper_set_decrypted);
	157	fd1094_driver_init(machine, segaic16_memory_mapper_set_decrypted);
158	158
159	159	/* reset the custom handlers and other pointers */
160	160	custom_io_r = NULL;
r2864	r2865
1192	1192	/**************************************************************************************************************************
1193	1193	**************************************************************************************************************************
1194	1194	**************************************************************************************************************************
1195		Turbo Outrun (Out Run upgrade set)
1196		CPU: FD1094 (317-0118)
1197		GAME BD 834-6919-12
1198		CPU BD 837-6905-12
1199		VIDEO BD 837-6906-02
	1195	Turbo Outrun (White cockpit/sitdown Deluxe version)
	1196	CPU: FD1094 (317-0109)
1200	1197	*/
1201	1198	ROM_START( toutrun )
1202	1199	ROM_REGION( 0x60000, REGION_CPU1, 0 ) /* 68000 code */
1203		ROM_LOAD16_BYTE( "epr-12513.133", 0x000000, 0x10000, CRC(ae8835a5) SHA1(09573964d4f42ac0f08be3682b73e3420df27c6d) )
1204		ROM_LOAD16_BYTE( "epr-12512.118", 0x000001, 0x10000, CRC(f90372ad) SHA1(b42dd8c580421b4d7ffacf8d3baa7b9fc9e392ef) )
1205		ROM_LOAD16_BYTE( "epr-12515.132", 0x020000, 0x10000, CRC(1f047df4) SHA1(c1c67847f1390e671c19f0b90c3cbfbc237d960b) )
1206		ROM_LOAD16_BYTE( "epr-12514.117", 0x020001, 0x10000, CRC(5539e9c3) SHA1(01046e3b836f66ba6d5c4be1611de48197aca67f) )
	1200	ROM_LOAD16_BYTE( "epr-12289.133", 0x000000, 0x10000, CRC(812fd035) SHA1(7bea9ba611333dfb86cfc2e2be8cff5f700b6f71) )
	1201	ROM_LOAD16_BYTE( "epr-12288.118", 0x000001, 0x10000, CRC(2f1151bb) SHA1(e91600d4f4e5d3d5a67cafb1ff34006f281434f1) )
	1202	ROM_LOAD16_BYTE( "epr-12291.132", 0x020000, 0x10000, CRC(8ca284d2) SHA1(93f71ec554ab000294aaa4de9ece0eecfcfe3c46) )
	1203	ROM_LOAD16_BYTE( "epr-12290.117", 0x020001, 0x10000, CRC(44dbf3cb) SHA1(ad867a66d97e9f5b9e14a8d05049581214a077bf) )
1207	1204	ROM_LOAD16_BYTE( "epr-12293.131", 0x040000, 0x10000, CRC(f4321eea) SHA1(64334acc82c14bb58b7d51719f34fd81cfb9fc6b) )
1208	1205	ROM_LOAD16_BYTE( "epr-12292.116", 0x040001, 0x10000, CRC(51d98af0) SHA1(6e7115706bfafb687faa23d55d4a8c8e498a4df2) )
1209	1206
1210	1207	ROM_REGION( 0x2000, REGION_USER1, 0 ) /* decryption key */
1211		ROM_LOAD( "317-0118.key", 0x0000, 0x2000, CRC(~~083d7d5~~6) SHA1(3153e444799~~8685~~9~~f60~~a2~~6fe~~9264ece~~a07e~~6~~e46~~9) )
	1208	ROM_LOAD( "317-0109.key", 0x0000, 0x2000, CRC(e12a6e78) SHA1(358325490fc93bb979e9a9a296ce639d331e8b52) )
1212	1209
1213	1210	ROM_REGION( 0x60000, REGION_CPU2, 0 ) /* second 68000 CPU */
1214	1211	ROM_LOAD16_BYTE( "opr-12295.76", 0x000000, 0x10000, CRC(d43a3a84) SHA1(362c98f62c205b6b40b7e8a4ba107745b547b984) )
r2864	r2865
1222	1219	ROM_LOAD( "opr-12325.104", 0x20000, 0x10000, CRC(1405137a) SHA1(367db88d36852e35c5e839f692be5ea8c8e072d2) )
1223	1220
1224	1221	ROM_REGION32_LE( 0x100000, REGION_GFX2, 0 ) /* sprites */
1225		/* Video BD 837-6906-2, Mask Roms twice the size as EPR/OPR counterparts */
1226		ROM_LOAD32_BYTE( "mpr-12336.9", 0x00000, 0x20000, CRC(dda465c7) SHA1(83acc12a387b004986f084f25964c15a9f88a41a) )
1227		ROM_LOAD32_BYTE( "mpr-12337.10", 0x00001, 0x20000, CRC(828233d1) SHA1(d73a200af4245d590e1fd3ac436723f99cc50452) )
1228		ROM_LOAD32_BYTE( "mpr-12338.11", 0x00002, 0x20000, CRC(46b4b5f4) SHA1(afeb2e5ac6792edafe7328993fe8dfcd4bce1924) )
1229		ROM_LOAD32_BYTE( "mpr-12339.12", 0x00003, 0x20000, CRC(0d7e3bab) SHA1(fdb603df55785ded593daf591ddd90f8f24e0d47) )
1230		ROM_LOAD32_BYTE( "mpr-12364.13", 0x80000, 0x20000, CRC(a4b83e65) SHA1(966d8c163cef0842abff54e1dba3f15248e73f68) )
1231		ROM_LOAD32_BYTE( "mpr-12365.14", 0x80001, 0x20000, CRC(4a80b2a9) SHA1(14b4fe71e102622a73c8dc0dbd0013cbbe6fcf9d) )
1232		ROM_LOAD32_BYTE( "mpr-12366.15", 0x80002, 0x20000, CRC(385cb3ab) SHA1(fec6d80d488bfe26524fa3a48b195a45a073e481) )
1233		ROM_LOAD32_BYTE( "mpr-12367.16", 0x80003, 0x20000, CRC(4930254a) SHA1(00f24be3bf02b143fa554f4d32e283bdac79af6a) )
	1222	ROM_LOAD32_BYTE( "opr-12307.9", 0x00000, 0x10000, CRC(437dcf09) SHA1(0022ee4d1c3698f77271e570cef98a8a1e5c5d6a) )
	1223	ROM_LOAD32_BYTE( "opr-12308.10", 0x00001, 0x10000, CRC(0de70cc2) SHA1(c03f8f8cda72daf64af2878bf254840ac6dd17eb) )
	1224	ROM_LOAD32_BYTE( "opr-12309.11", 0x00002, 0x10000, CRC(deb8c242) SHA1(c05d8ced4eafae52c4795fb1471cd66f5903d1aa) )
	1225	ROM_LOAD32_BYTE( "opr-12310.12", 0x00003, 0x10000, CRC(45cf157e) SHA1(5d0be2a374a53ea1fe0ba2bf9b2173e96de1eb51) )
	1226	ROM_LOAD32_BYTE( "opr-12311.13", 0x40000, 0x10000, CRC(ae2bd639) SHA1(64bb60ae7e3f87fbbce00106ba65c4e6fc1af0e4) )
	1227	ROM_LOAD32_BYTE( "opr-12312.14", 0x40001, 0x10000, CRC(626000e7) SHA1(4a7f9e76dd76a3dc56b8257149bc94be3f4f2e87) )
	1228	ROM_LOAD32_BYTE( "opr-12313.15", 0x40002, 0x10000, CRC(52870c37) SHA1(3a6836a46d94c0f9115800d206410252a1134c57) )
	1229	ROM_LOAD32_BYTE( "opr-12314.16", 0x40003, 0x10000, CRC(40c461ea) SHA1(7bed8f24112dc3c827fd087138fcf2700092aa59) )
	1230	ROM_LOAD32_BYTE( "opr-12315.17", 0x80000, 0x10000, CRC(3ff9a3a3) SHA1(0d90fe2669d03bd07a0d3b05934201778e28d54c) )
	1231	ROM_LOAD32_BYTE( "opr-12316.18", 0x80001, 0x10000, CRC(8a1e6dc8) SHA1(32f09ec504c2b6772815bad7380a2f738f11746a) )
	1232	ROM_LOAD32_BYTE( "opr-12317.19", 0x80002, 0x10000, CRC(77e382d4) SHA1(5b7912069a46043b7be989d82436add85497d318) )
	1233	ROM_LOAD32_BYTE( "opr-12318.20", 0x80003, 0x10000, CRC(d1afdea9) SHA1(813eccc88d5046992be5b5a0618d32127d16e30b) )
	1234	ROM_LOAD32_BYTE( "opr-12319.25", 0xc0000, 0x10000, CRC(df23baf9) SHA1(f9611391bb3b3b92203fa9f6dd461e3a6e863622) )
	1235	ROM_LOAD32_BYTE( "opr-12320.22", 0xc0001, 0x10000, CRC(7931e446) SHA1(9f2161a689ebad61f6653942e23d9c2bc6170d4a) )
	1236	ROM_LOAD32_BYTE( "opr-12321.23", 0xc0002, 0x10000, CRC(830bacd4) SHA1(5a4816969437ee1edca5845006c0b8e9ba365491) )
	1237	ROM_LOAD32_BYTE( "opr-12322.24", 0xc0003, 0x10000, CRC(8b812492) SHA1(bf1f9e059c093c0991c7caf1b01c739ed54b8357) )
1234	1238
1235	1239	ROM_REGION( 0x10000, REGION_GFX3, 0 ) /* road gfx (2 identical roms, 1 for each road) */
1236	1240	ROM_LOAD( "epr-12299.47", 0x0000, 0x8000, CRC(fc9bc41b) SHA1(9af73e096253cf2c4f283f227530110a4b37fcee) ) /* Manual shows both as EPR-12298 */
r2864	r2865
1379	1383	ROM_LOAD( "opr-12306.71", 0x50000, 0x10000, CRC(e49249fd) SHA1(ff36e4dba4e9d3d354e3dd528edeb50ad9c18ee4) )
1380	1384	ROM_END
1381	1385
	1386	/**************************************************************************************************************************
	1387	Turbo Outrun (Out Run upgrade set)
	1388	CPU: FD1094 (317-0118)
	1389	GAME BD 834-6919-12
	1390	CPU BD 837-6905-12
	1391	VIDEO BD 837-6906-02
	1392	*/
	1393	ROM_START( toutrunu )
	1394	ROM_REGION( 0x60000, REGION_CPU1, 0 ) /* 68000 code */
	1395	ROM_LOAD16_BYTE( "epr-12513.133", 0x000000, 0x10000, CRC(ae8835a5) SHA1(09573964d4f42ac0f08be3682b73e3420df27c6d) )
	1396	ROM_LOAD16_BYTE( "epr-12512.118", 0x000001, 0x10000, CRC(f90372ad) SHA1(b42dd8c580421b4d7ffacf8d3baa7b9fc9e392ef) )
	1397	ROM_LOAD16_BYTE( "epr-12515.132", 0x020000, 0x10000, CRC(1f047df4) SHA1(c1c67847f1390e671c19f0b90c3cbfbc237d960b) )
	1398	ROM_LOAD16_BYTE( "epr-12514.117", 0x020001, 0x10000, CRC(5539e9c3) SHA1(01046e3b836f66ba6d5c4be1611de48197aca67f) )
	1399	ROM_LOAD16_BYTE( "epr-12293.131", 0x040000, 0x10000, CRC(f4321eea) SHA1(64334acc82c14bb58b7d51719f34fd81cfb9fc6b) )
	1400	ROM_LOAD16_BYTE( "epr-12292.116", 0x040001, 0x10000, CRC(51d98af0) SHA1(6e7115706bfafb687faa23d55d4a8c8e498a4df2) )
1382	1401
	1402	ROM_REGION( 0x2000, REGION_USER1, 0 ) /* decryption key */
	1403	ROM_LOAD( "317-0118.key", 0x0000, 0x2000, CRC(083d7d56) SHA1(3153e44479986859f60a26fe9264ecea07e6e469) )
	1404
	1405	ROM_REGION( 0x60000, REGION_CPU2, 0 ) /* second 68000 CPU */
	1406	ROM_LOAD16_BYTE( "opr-12295.76", 0x000000, 0x10000, CRC(d43a3a84) SHA1(362c98f62c205b6b40b7e8a4ba107745b547b984) )
	1407	ROM_LOAD16_BYTE( "opr-12294.58", 0x000001, 0x10000, CRC(27cdcfd3) SHA1(4fe57db95b109ab1bb1326789e06a3d3aac311cc) )
	1408	ROM_LOAD16_BYTE( "opr-12297.75", 0x020000, 0x10000, CRC(1d9b5677) SHA1(fb6e33acc43fbc7a8d7ac44045439ecdf794fdeb) )
	1409	ROM_LOAD16_BYTE( "opr-12296.57", 0x020001, 0x10000, CRC(0a513671) SHA1(4c13ca3a6f0aa9d06ed80798b466cca0c966a265) )
	1410
	1411	ROM_REGION( 0x30000, REGION_GFX1, ROMREGION_DISPOSE ) /* tiles */
	1412	ROM_LOAD( "opr-12323.102", 0x00000, 0x10000, CRC(4de43a6f) SHA1(68909338e1f192ac2699c8a8d24c3f46502dd019) )
	1413	ROM_LOAD( "opr-12324.103", 0x10000, 0x10000, CRC(24607a55) SHA1(69033f2281cd42e88233c23d809b73607fe54853) )
	1414	ROM_LOAD( "opr-12325.104", 0x20000, 0x10000, CRC(1405137a) SHA1(367db88d36852e35c5e839f692be5ea8c8e072d2) )
	1415
	1416	ROM_REGION32_LE( 0x100000, REGION_GFX2, 0 ) /* sprites */
	1417	/* Video BD 837-6906-2, Mask Roms twice the size as EPR/OPR counterparts */
	1418	ROM_LOAD32_BYTE( "mpr-12336.9", 0x00000, 0x20000, CRC(dda465c7) SHA1(83acc12a387b004986f084f25964c15a9f88a41a) )
	1419	ROM_LOAD32_BYTE( "mpr-12337.10", 0x00001, 0x20000, CRC(828233d1) SHA1(d73a200af4245d590e1fd3ac436723f99cc50452) )
	1420	ROM_LOAD32_BYTE( "mpr-12338.11", 0x00002, 0x20000, CRC(46b4b5f4) SHA1(afeb2e5ac6792edafe7328993fe8dfcd4bce1924) )
	1421	ROM_LOAD32_BYTE( "mpr-12339.12", 0x00003, 0x20000, CRC(0d7e3bab) SHA1(fdb603df55785ded593daf591ddd90f8f24e0d47) )
	1422	ROM_LOAD32_BYTE( "mpr-12364.13", 0x80000, 0x20000, CRC(a4b83e65) SHA1(966d8c163cef0842abff54e1dba3f15248e73f68) )
	1423	ROM_LOAD32_BYTE( "mpr-12365.14", 0x80001, 0x20000, CRC(4a80b2a9) SHA1(14b4fe71e102622a73c8dc0dbd0013cbbe6fcf9d) )
	1424	ROM_LOAD32_BYTE( "mpr-12366.15", 0x80002, 0x20000, CRC(385cb3ab) SHA1(fec6d80d488bfe26524fa3a48b195a45a073e481) )
	1425	ROM_LOAD32_BYTE( "mpr-12367.16", 0x80003, 0x20000, CRC(4930254a) SHA1(00f24be3bf02b143fa554f4d32e283bdac79af6a) )
	1426
	1427	ROM_REGION( 0x10000, REGION_GFX3, 0 ) /* road gfx (2 identical roms, 1 for each road) */
	1428	ROM_LOAD( "epr-12299.47", 0x0000, 0x8000, CRC(fc9bc41b) SHA1(9af73e096253cf2c4f283f227530110a4b37fcee) ) /* Manual shows both as EPR-12298 */
	1429	ROM_LOAD( "epr-12298.11", 0x8000, 0x8000, CRC(fc9bc41b) SHA1(9af73e096253cf2c4f283f227530110a4b37fcee) )
	1430
	1431	ROM_REGION( 0x10000, REGION_CPU3, 0 ) /* sound CPU */
	1432	ROM_LOAD( "epr-12300.88", 0x00000, 0x10000, CRC(e8ff7011) SHA1(6eaf3aea507007ea31d507ed7825d905f4b8e7ab) )
	1433
	1434	ROM_REGION( 0x80000, REGION_SOUND1, ROMREGION_ERASEFF ) /* sound PCM data */
	1435	ROM_LOAD( "opr-12301.66", 0x00000, 0x10000, CRC(6e78ad15) SHA1(c31ddf434b459cd1a381d2a028beabddd4ed10d2) )
	1436	ROM_LOAD( "opr-12302.67", 0x10000, 0x10000, CRC(e72928af) SHA1(40e0b178958cfe97c097fe9d82b5de54bc27a29f) )
	1437	ROM_LOAD( "opr-12303.68", 0x20000, 0x10000, CRC(8384205c) SHA1(c1f9d52bc587eab5a97867198e9aa7c19e973429) )
	1438	ROM_LOAD( "opr-12304.69", 0x30000, 0x10000, CRC(e1762ac3) SHA1(855f06c082a17d90857e6efa3cf95b0eda0e634d) )
	1439	ROM_LOAD( "opr-12305.70", 0x40000, 0x10000, CRC(ba9ce677) SHA1(056781f92450c902e1d279a02bda28337815cba9) )
	1440	ROM_LOAD( "opr-12306.71", 0x50000, 0x10000, CRC(e49249fd) SHA1(ff36e4dba4e9d3d354e3dd528edeb50ad9c18ee4) )
	1441	ROM_END
	1442
	1443
1383	1444	/**************************************************************************************************************************
1384	1445	**************************************************************************************************************************
1385	1446	**************************************************************************************************************************
r2864	r2865
1759	1820	GAME( 1987, shangon2, shangon, shangon, shangon, shangon3, ROT0, "Sega", "Super Hang-On (mini ride-on, Rev A, FD1089B 317-0034)", 0 )
1760	1821	GAME( 1987, shangon1, shangon, shangon, shangon, shangon3, ROT0, "Sega", "Super Hang-On (mini ride-on?, FD1089B 317-0034)", GAME_NOT_WORKING ) /* bad program rom */
1761	1822	GAME( 1991, shangnle, shangon, shangon, shangon, shangon, ROT0, "Sega", "Limited Edition Hang-On", 0 )
1762		GAME( 1989, toutrun, 0, outrun, toutrun, outrun, ROT0, "Sega", "Turbo Out Run (~~Out Run u~~p~~grade~~, FD1094 317-0118)" , 0 )
	1823	GAME( 1989, toutrun, 0, outrun, toutrun1, outrun, ROT0, "Sega", "Turbo Out Run (cockpit, FD1094 317-0109)", 0 )
1763	1824	GAME( 1989, toutrun2, toutrun, outrun, toutrun1, outrun, ROT0, "Sega", "Turbo Out Run (upright, FD1094 317-unknown)", 0 )
1764	1825	GAME( 1989, toutrun1, toutrun, outrun, toutrun1, outrun, ROT0, "Sega", "Turbo Out Run (cockpit, FD1094 317-unknown)", GAME_NOT_WORKING ) /* FD1094 CPU not decrypted */
	1826	GAME( 1989, toutrunu, toutrun, outrun, toutrun, outrun, ROT0, "Sega", "Turbo Out Run (Out Run upgrade, FD1094 317-0118)" , 0 )

src/mame/drivers/koikoi.c
r2864	r2865
70	70
71	71	static READ8_HANDLER(input_r)
72	72	{
73		if(inputcnt<0){ return 0; }
	73	if(inputcnt<0)
	74	{
	75	return 0;
	76	}
	77
74	78	if(!inputcnt)
75	79	{
76		int key=input_port_read~~_indexed~~(machine,2);
	80	int key=input_port_read(machine, "IN1");
77	81	int keyval=0; //we must return 0 (0x2 in 2nd read) to clear 4 bit at $6600 and allow next read
78	82
79	83	if(key)
r2864	r2865
84	88	inputval=inputTab[keyval]&0x1f;
85	89	inputlen=inputTab[keyval]>>5;
86	90	}
	91
87	92	if(inputlen==++inputcnt) //return expected value
88	93	{
89	94	return inputval^0xff;
90	95	}
	96
91	97	if(inputcnt>4) //end of cycle
92	98	{
93	99	inputcnt=-1;
94	100	}
	101
95	102	return 0xff; //return 0^0xff
96	103	}
97	104
r2864	r2865
104	111	{
105	112	if(!offset)
106	113	{
107		return input_port_read~~_indexed~~(machine, 1)^ioram[4]; //coin
	114	return input_port_read(machine, "IN0")^ioram[4]; //coin
108	115	}
109	116	return 0;
110	117	}
r2864	r2865
121	128	static ADDRESS_MAP_START( readmem, ADDRESS_SPACE_PROGRAM, 8 )
122	129	AM_RANGE(0x0000, 0x2fff) AM_ROM
123	130	AM_RANGE(0x6000, 0x67ff) AM_RAM
124		AM_RANGE(0x8000, 0x8000) AM_READ~~( input~~_~~port_0_r~~ )
	131	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("DSW")
125	132	AM_RANGE(0x7000, 0x77ff) AM_READWRITE(vram_r, vram_w) AM_BASE(&videoram)
126	133	AM_RANGE(0x9000, 0x9007) AM_READWRITE(io_r, io_w)
127	134	ADDRESS_MAP_END
r2864	r2865
136	143	ADDRESS_MAP_END
137	144
138	145	static INPUT_PORTS_START( koikoi )
139		PORT_START /* DSW */
	146	PORT_START_TAG("DSW") /* DSW */
140	147	PORT_DIPNAME( 0x03, 0x01, "Timer C" )
141		PORT_DIPSETTING( 0x00, "50" )
142		PORT_DIPSETTING( 0x01, "70" )
143		PORT_DIPSETTING( 0x02, "90" )
144		PORT_DIPSETTING( 0x03, "110" )
	148	PORT_DIPSETTING( 0x00, "50" )
	149	PORT_DIPSETTING( 0x01, "70" )
	150	PORT_DIPSETTING( 0x02, "90" )
	151	PORT_DIPSETTING( 0x03, "110" )
145	152
146	153	PORT_DIPNAME( 0x0c, 0x04, "Timer M" )
147		PORT_DIPSETTING( 0x00, "120" )
148		PORT_DIPSETTING( 0x04, "150" )
149		PORT_DIPSETTING( 0x08, "180" )
150		PORT_DIPSETTING( 0x0c, "210" )
	154	PORT_DIPSETTING( 0x00, "120" )
	155	PORT_DIPSETTING( 0x04, "150" )
	156	PORT_DIPSETTING( 0x08, "180" )
	157	PORT_DIPSETTING( 0x0c, "210" )
151	158
152	159	PORT_DIPNAME( 0x10, 0x00, DEF_STR( Coin_A ) )
153		PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
154		PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
	160	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
	161	PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
155	162
156	163	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
157		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
158		PORT_DIPSETTING( 0x20, DEF_STR( On ) )
	164	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	165	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
159	166
160	167	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
161		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
162		PORT_DIPSETTING( 0x40, DEF_STR( On ) )
	168	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	169	PORT_DIPSETTING( 0x40, DEF_STR( On ) )
163	170
164	171	PORT_DIPNAME( 0x80, 0x00, "Test Mode" )
165		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
166		PORT_DIPSETTING( 0x80, DEF_STR( On ) )
	172	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	173	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
167	174
168		PORT_START /* IN0 */
	175	PORT_START_TAG("IN0") /* IN0 */
169	176	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN1 )
170	177	PORT_BIT( 0xbf, IP_ACTIVE_LOW, IPT_UNUSED )
171	178
172		PORT_START /* IN1 */
	179	PORT_START_TAG("IN1") /* IN1 */
173	180	PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_A) //1
174	181	PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_S) //2
175	182	PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_D) //3

src/mame/drivers/gticlub.c
r2864	r2865
35	35	*/
36	36
37	37	#include "driver.h"
38		#include "deprecat.h"
39	38	#include "machine/eeprom.h"
40	39	#include "cpu/powerpc/ppc.h"
41	40	#include "cpu/sharc/sharc.h"
r2864	r2865
146	145	0 /* reset_delay */
147	146	};
148	147
149		static void eeprom_handler(mame_file *file, int read_or_write)
	148	static void eeprom_handler(running_machine machine, mame_file file, int read_or_write)
150	149	{
151	150	if (read_or_write)
152	151	{
r2864	r2865
168	167	UINT8 eepdata[0x200];
169	168	memset(eepdata, 0xff, 0x200);
170	169
171		if (mame_stricmp(Machine->gamedrv->name, "slrasslt") == 0)
	170	if (mame_stricmp(machine->gamedrv->name, "slrasslt") == 0)
172	171	{
173	172	// magic number
174	173	eepdata[0x4] = 0x96;
r2864	r2865
211	210
212	211	switch (adc1038_adr)
213	212	{
214		case 0: adc1038_adc_data = input_port_read_indexed(machine, 4); break;
215		case 1: adc1038_adc_data = input_port_read_indexed(machine, 5); break;
216		case 2: adc1038_adc_data = input_port_read_indexed(machine, 6); break;
217		case 3: adc1038_adc_data = input_port_read_indexed(machine, 7); break;
	213	case 0: adc1038_adc_data = input_port_read(machine, "AN0"); break;
	214	case 1: adc1038_adc_data = input_port_read(machine, "AN1"); break;
	215	case 2: adc1038_adc_data = input_port_read(machine, "AN2"); break;
	216	case 3: adc1038_adc_data = input_port_read(machine, "AN3"); break;
218	217	case 4: adc1038_adc_data = 0x000; break;
219	218	case 5: adc1038_adc_data = 0x000; break;
220	219	case 6: adc1038_adc_data = 0x000; break;
r2864	r2865
256	255
257	256	switch (adc1038_adr)
258	257	{
259		case 0: adc1038_adc_data = input_port_read_indexed(machine, 4); break;
260		case 1: adc1038_adc_data = input_port_read_indexed(machine, 5); break;
261		case 2: adc1038_adc_data = input_port_read_indexed(machine, 6); break;
262		case 3: adc1038_adc_data = input_port_read_indexed(machine, 7); break;
	258	case 0: adc1038_adc_data = input_port_read(machine, "AN0"); break;
	259	case 1: adc1038_adc_data = input_port_read(machine, "AN1"); break;
	260	case 2: adc1038_adc_data = input_port_read(machine, "AN2"); break;
	261	case 3: adc1038_adc_data = input_port_read(machine, "AN3"); break;
263	262	case 4: adc1038_adc_data = 0x000; break;
264	263	case 5: adc1038_adc_data = 0x000; break;
265	264	case 6: adc1038_adc_data = 0x000; break;
r2864	r2865
275	274
276	275	static READ8_HANDLER( sysreg_r )
277	276	{
	277	static const char *portnames[] = { "IN0", "IN1", "IN2", "IN3" };
	278
278	279	switch (offset)
279	280	{
280	281	case 0:
281	282	case 1:
282	283	case 3:
283		return input_port_read~~_indexed~~(machine, offset);
	284	return input_port_read(machine, portnames[offset]);
284	285
285	286	case 2:
286	287	return adc1038_sars_r(machine) << 7;
r2864	r2865
372	373	if (data & 0x20)
373	374	{
374	375	// Thunder Hurricane breaks otherwise...
375		if (mame_stricmp(Machine->gamedrv->name, "thunderh") != 0)
	376	if (mame_stricmp(machine->gamedrv->name, "thunderh") != 0)
376	377	{
377		cpunum_set_input_line(Machine, 0, INPUT_LINE_IRQ2, ASSERT_LINE);
	378	cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ2, ASSERT_LINE);
378	379	timer_set(ATTOTIME_IN_USEC(1), NULL, 0, network_irq_clear);
379	380	}
380	381	}
381	382	// else
382		// cpunum_set_input_line(Machine, 0, INPUT_LINE_IRQ2, CLEAR_LINE);
	383	// cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ2, CLEAR_LINE);
383	384	break;
384	385	}
385	386	case 2: // Sub ID register
r2864	r2865
508	509
509	510	static NVRAM_HANDLER(gticlub)
510	511	{
511		eeprom_handler(file, read_or_write);
	512	eeprom_handler(machine, file, read_or_write);
512	513	}
513	514
514	515
515	516	static INPUT_PORTS_START( gticlub )
516		PORT_START
	517	PORT_START_TAG("IN0")
517	518	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) // View switch
518	519	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) // Shift Down
519	520	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) // Shift Up
r2864	r2865
521	522	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Service Button") PORT_CODE(KEYCODE_8)
522	523	PORT_BIT( 0x0b, IP_ACTIVE_LOW, IPT_UNKNOWN )
523	524
524		PORT_START
	525	PORT_START_TAG("IN1")
525	526	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
526	527
527		PORT_START
	528	PORT_START_TAG("IN2")
528	529	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
529	530
530		PORT_START
	531	PORT_START_TAG("IN3")
531	532	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
532	533	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
533	534	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
544	545	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
545	546	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
546	547
547		PORT_START /* mask default type sens delta min max */
	548	PORT_START_TAG("AN0") /* mask default type sens delta min max */
548	549	PORT_BIT( 0x3ff, 0x200, IPT_PADDLE ) PORT_MINMAX(0x000,0x3ff) PORT_SENSITIVITY(35) PORT_KEYDELTA(5)
549	550
550		PORT_START
	551	PORT_START_TAG("AN1")
551	552	PORT_BIT( 0x3ff, 0x000, IPT_PEDAL ) PORT_MINMAX(0x000,0x3ff) PORT_SENSITIVITY(35) PORT_KEYDELTA(5)
552	553
553		PORT_START
	554	PORT_START_TAG("AN2")
554	555	PORT_BIT( 0x3ff, 0x000, IPT_PEDAL2 ) PORT_MINMAX(0x000,0x3ff) PORT_SENSITIVITY(35) PORT_KEYDELTA(5)
555	556
556		PORT_START
	557	PORT_START_TAG("AN3")
557	558	PORT_BIT( 0x3ff, 0x000, IPT_PEDAL3 ) PORT_MINMAX(0x000,0x3ff) PORT_SENSITIVITY(35) PORT_KEYDELTA(5)
558	559
559	560	INPUT_PORTS_END
560	561
561	562	static INPUT_PORTS_START( slrasslt )
562		PORT_START
	563	PORT_START_TAG("IN0")
563	564	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 ) // View Shift
564	565	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) // Trigger
565	566	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) // Missile
566	567	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) // Power Up
567	568
568		PORT_START
	569	PORT_START_TAG("IN1")
569	570	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
570	571	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
571	572	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
572	573	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
573	574
574		PORT_START
	575	PORT_START_TAG("IN2")
575	576	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
576	577
577		PORT_START
	578	PORT_START_TAG("IN3")
578	579	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
579	580	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Service Button") PORT_CODE(KEYCODE_8)
580	581	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
592	593	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
593	594	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
594	595
595		PORT_START
	596	PORT_START_TAG("AN0")
596	597	PORT_BIT( 0x3ff, 0x000, IPT_AD_STICK_Y ) PORT_MINMAX(0x000,0x3ff) PORT_SENSITIVITY(35) PORT_KEYDELTA(5)
597	598
598		PORT_START
	599	PORT_START_TAG("AN1")
599	600	PORT_BIT( 0x3ff, 0x000, IPT_AD_STICK_X ) PORT_MINMAX(0x000,0x3ff) PORT_SENSITIVITY(35) PORT_KEYDELTA(5) PORT_REVERSE
600	601
601	602	INPUT_PORTS_END
602	603
603	604	static INPUT_PORTS_START( thunderh )
604		PORT_START
	605	PORT_START_TAG("IN0")
605	606	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
606	607	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
607	608	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
611	612	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
612	613	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
613	614
614		PORT_START
	615	PORT_START_TAG("IN1")
615	616	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
616	617	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
617	618	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
621	622	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
622	623	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
623	624
624		PORT_START
	625	PORT_START_TAG("IN2")
625	626	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
626	627
627		PORT_START
	628	PORT_START_TAG("IN3")
628	629	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
629	630	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Service Button") PORT_CODE(KEYCODE_8)
630	631	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
645	646	INPUT_PORTS_END
646	647
647	648	static INPUT_PORTS_START( hangplt )
648		PORT_START
	649	PORT_START_TAG("IN0")
649	650	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
650	651	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
651	652	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
653	654	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
654	655	PORT_BIT( 0x07, IP_ACTIVE_LOW, IPT_UNKNOWN )
655	656
656		PORT_START
	657	PORT_START_TAG("IN1")
657	658	PORT_BIT( 0x8f, IP_ACTIVE_LOW, IPT_UNKNOWN )
658	659	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) // Push limit switch
659	660	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) // Pull limit switch
660	661
661		PORT_START
	662	PORT_START_TAG("IN2")
662	663	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
663	664
664		PORT_START
	665	PORT_START_TAG("IN3")
665	666	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
666	667	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Service Button") PORT_CODE(KEYCODE_8)
667	668	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )

src/mame/drivers/foodf.c
r2864	r2865
202	202
203	203	static READ16_HANDLER( analog_r )
204	204	{
205		return input_port_read_indexed(machine, whichport);
	205	static const char *portnames[] = { "STICK0_X", "STICK1_X", "STICK0_Y", "STICK1_Y" };
	206
	207	return input_port_read(machine, portnames[whichport]);
206	208	}
207	209
208	210
r2864	r2865
262	264	*************************************/
263	265
264	266	static INPUT_PORTS_START( foodf )
265		PORT_START /* IN0 */
	267	PORT_START_TAG("STICK0_X") /* IN0 */
266	268	PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(1)
267	269
268		PORT_START /* IN1 */
	270	PORT_START_TAG("STICK1_X") /* IN1 */
269	271	PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE PORT_COCKTAIL PORT_PLAYER(2)
270	272
271		PORT_START /* IN2 */
	273	PORT_START_TAG("STICK0_Y") /* IN2 */
272	274	PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(1)
273	275
274		PORT_START /* IN3 */
	276	PORT_START_TAG("STICK1_Y") /* IN3 */
275	277	PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE PORT_COCKTAIL PORT_PLAYER(2)
276	278
277		PORT_START /* IN4 */
	279	PORT_START_TAG("IN0") /* IN4 */
278	280	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
279	281	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
280	282	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r2864	r2865
284	286	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
285	287	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
286	288
287		PORT_START /* SW1 */
	289	PORT_START_TAG("DSW") /* SW1 */
288	290	PORT_DIPNAME( 0x07, 0x00, "Bonus Coins" )
289	291	PORT_DIPSETTING( 0x00, DEF_STR( None ) )
290	292	PORT_DIPSETTING( 0x05, "1 for every 2" )
r2864	r2865
353	355
354	356	static READ8_HANDLER( pot_r )
355	357	{
356		return (input_port_read~~_indexed~~(machine, 5) >> offset) << 7;
	358	return (input_port_read(machine, "DSW") >> offset) << 7;
357	359	}
358	360
359	361	static const struct POKEYinterface pokey_interface =

src/mame/drivers/armedf.c
r2864	r2865
15	15	Armed Formation
16	16	(c)1988 Nichibutsu
17	17
	18	Based on the notes below I suspect several of the supported sets are
	19	actually bootlegs.
	20
18	21	68000 + Z80
19	22
20	23	TODO:
21	24	- simulate the mcu/blitter (particularly needed in terrafu and legion)
	25	-- or figure out which chip it is, decap it, and emulate it.
22	26
23	27
	28
	29
24	30	Stephh's notes (based on the games M68000 code and some tests) :
25	31
26	32	1a) 'legion'
r2864	r2865
201	207	/* bit 12 seems to handle screen flipping */
202	208	flip_screen_set(armedf_vreg & 0x1000);
203	209
	210
204	211	if ((armedf_vreg & 0x4000) && !(armedf_vreg & 0x0100))
205	212	{
206	213	int i;
r2864	r2865
212	219	//logerror("vreg WIPE TX\n");
213	220	}
214	221	//logerror("VReg = %04x\n", armedf_vreg);
	222
215	223	}
216	224
217	225	static WRITE16_HANDLER( kodure_io_w )
r2864	r2865
273	281	AM_RANGE(0x0c0000, 0x0c0001) AM_WRITE(terraf_fg_scroll_msb_arm_w) /* written between two consecutive writes to 7c008 */
274	282	ADDRESS_MAP_END
275	283
	284	/* the same for now */
	285	static ADDRESS_MAP_START( terrafb_map, ADDRESS_SPACE_PROGRAM, 16 )
	286	AM_RANGE(0x000000, 0x04ffff) AM_ROM
	287	AM_RANGE(0x060000, 0x0603ff) AM_RAM AM_BASE(&spriteram16) AM_SIZE(&spriteram_size)
	288	AM_RANGE(0x060400, 0x063fff) AM_RAM
	289	AM_RANGE(0x064000, 0x064fff) AM_RAM_WRITE(paletteram16_xxxxRRRRGGGGBBBB_word_w) AM_BASE(&paletteram16)
	290	AM_RANGE(0x068000, 0x069fff) AM_RAM_WRITE(armedf_text_videoram_w) AM_BASE(&terraf_text_videoram)
	291	AM_RANGE(0x06a000, 0x06a9ff) AM_RAM
	292	AM_RANGE(0x06c000, 0x06c9ff) AM_RAM
	293	AM_RANGE(0x070000, 0x070fff) AM_RAM_WRITE(armedf_fg_videoram_w) AM_BASE(&armedf_fg_videoram)
	294	AM_RANGE(0x074000, 0x074fff) AM_RAM_WRITE(armedf_bg_videoram_w) AM_BASE(&armedf_bg_videoram)
	295	AM_RANGE(0x078000, 0x078001) AM_READ(input_port_0_word_r)
	296	AM_RANGE(0x078002, 0x078003) AM_READ(input_port_1_word_r)
	297	AM_RANGE(0x078004, 0x078005) AM_READ(input_port_2_word_r)
	298	AM_RANGE(0x078006, 0x078007) AM_READ(input_port_3_word_r)
	299	AM_RANGE(0x07c000, 0x07c001) AM_WRITE(terraf_io_w)
	300	AM_RANGE(0x07c002, 0x07c003) AM_WRITE(armedf_bg_scrollx_w)
	301	AM_RANGE(0x07c004, 0x07c005) AM_WRITE(armedf_bg_scrolly_w)
	302	AM_RANGE(0x07c006, 0x07c007) AM_WRITE(terraf_fg_scrollx_w) /* not use in terrafu, 0x07c008 neither */
	303	AM_RANGE(0x07c008, 0x07c009) AM_WRITE(terraf_fg_scrolly_w) /* written twice, lsb and msb */
	304	AM_RANGE(0x07c00a, 0x07c00b) AM_WRITE(sound_command_w)
	305	AM_RANGE(0x07c00c, 0x07c00d) AM_WRITE(SMH_NOP) /* Watchdog ? cycle 0000 -> 0100 -> 0200 back to 0000 */
	306	AM_RANGE(0x07c00e, 0x07c00f) AM_WRITE(armedf_mcu_cmd) /* MCU Command ? */
	307	AM_RANGE(0x0c0000, 0x0c0001) AM_WRITE(terraf_fg_scroll_msb_arm_w) /* written between two consecutive writes to 7c008 */
	308	ADDRESS_MAP_END
	309
276	310	static ADDRESS_MAP_START( kodure_map, ADDRESS_SPACE_PROGRAM, 16 )
277	311	AM_RANGE(0x000000, 0x05ffff) AM_ROM
278	312	AM_RANGE(0x060000, 0x060fff) AM_RAM AM_BASE(&spriteram16) AM_SIZE(&spriteram_size)
r2864	r2865
399	433	AM_RANGE(0xc000, 0xffff) AM_RAM
400	434	ADDRESS_MAP_END
401	435
	436
	437	static ADDRESS_MAP_START( terrafb_extraz80_map, ADDRESS_SPACE_PROGRAM, 8 )
	438	AM_RANGE(0x0000, 0x3fff) AM_ROM
	439	ADDRESS_MAP_END
	440
	441	static ADDRESS_MAP_START( terrafb_extraz80_portmap, ADDRESS_SPACE_IO, 8 )
	442	ADDRESS_MAP_GLOBAL_MASK(0xff)
	443	ADDRESS_MAP_END
	444
	445
402	446	static READ8_HANDLER( soundlatch_clear_r )
403	447	{
404	448	soundlatch_clear_w(machine,0,0);
r2864	r2865
749	793	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
750	794	MACHINE_DRIVER_END
751	795
	796	static MACHINE_DRIVER_START( terrafb )
	797
	798	/* basic machine hardware */
	799	MDRV_CPU_ADD(M68000, 8000000) /* 8 MHz?? */
	800	MDRV_CPU_PROGRAM_MAP(terrafb_map,0)
	801	MDRV_CPU_VBLANK_INT("main", irq1_line_hold)
	802
	803	MDRV_CPU_ADD(Z80, 3072000) /* 3.072 MHz???? */
	804	MDRV_CPU_PROGRAM_MAP(sound_map,0)
	805	MDRV_CPU_IO_MAP(sound_portmap,0)
	806	MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,128)
	807
	808	MDRV_CPU_ADD(Z80, 3072000) /* 3.072 MHz???? */
	809	MDRV_CPU_PROGRAM_MAP(terrafb_extraz80_map,0)
	810	MDRV_CPU_IO_MAP(terrafb_extraz80_portmap,0)
	811	MDRV_CPU_VBLANK_INT_HACK(irq0_line_hold,128)
	812
	813
	814	/* video hardware */
	815	MDRV_VIDEO_ATTRIBUTES(VIDEO_BUFFERS_SPRITERAM)
	816
	817	MDRV_SCREEN_ADD("main", RASTER)
	818	MDRV_SCREEN_REFRESH_RATE(57)
	819	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
	820	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
	821	MDRV_SCREEN_SIZE(648, 328)
	822	MDRV_SCREEN_VISIBLE_AREA(128, (64-12)8-1, 18, 318-1 )
	823	MDRV_GFXDECODE(armedf)
	824	MDRV_PALETTE_LENGTH(2048)
	825
	826	MDRV_VIDEO_EOF(armedf)
	827	MDRV_VIDEO_START(armedf)
	828	MDRV_VIDEO_UPDATE(armedf)
	829
	830	/* sound hardware */
	831	MDRV_SPEAKER_STANDARD_MONO("mono")
	832
	833	MDRV_SOUND_ADD(YM3812, 4000000)
	834	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
	835
	836	MDRV_SOUND_ADD(DAC, 0)
	837	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	838
	839	MDRV_SOUND_ADD(DAC, 0)
	840	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	841	MACHINE_DRIVER_END
	842
752	843	static MACHINE_DRIVER_START( kodure )
753	844
754	845	/* basic machine hardware */
r2864	r2865
1053	1144	ROM_LOAD( "n82s129an.11j", 0x0000, 0x0100, CRC(81244757) SHA1(6324f63e571f0f7a0bb9eb97f9994809db79493f) ) /* N82S129AN or compatible labled "TF" */
1054	1145	ROM_END
1055	1146
	1147	/*
	1148
	1149	CPU
	1150
	1151	Main cpu 68000,Z80B*
	1152	Sound cpu Z80
	1153	Sound ic ym3812
	1154	Osc 16 and 24 Mhz
	1155
	1156	Note:
	1157
	1158	The custom mcu of original was been replaced by a small daughterboard inversely
	1159	connected to the main cpu board.It has a Z80B*,which uses 2kb of ram (6116 SRAM x1),
	1160	and some standard TTL ics.
	1161
	1162	ROMs
	1163
	1164	tfb-1 to 3 and tfb-6 to 8 main program
	1165	tfb-10 Z80B* program (mcu hack)
	1166	the rest of roms (sound program and gfx data) are the same of existing set
	1167
	1168	All roms are 24128,24256,27512
	1169	Note
	1170
	1171	This romset comes from a bootleg/hacked pcb.Game differences from original are:
	1172	Company logo and copyright string removed.
	1173
	1174	*/
	1175
	1176
	1177	ROM_START( terrafb )
	1178	ROM_REGION( 0x50000, REGION_CPU1, 0 ) /* 64K8 for 68000 code /
	1179	ROM_LOAD16_BYTE( "tfb-8.bin", 0x00000, 0x10000, CRC(b11a6fa7) SHA1(7bb2b98be02d8913796a6d4fa20eed16226ce6b9) )
	1180	ROM_LOAD16_BYTE( "tfb-3.bin", 0x00001, 0x10000, CRC(6c6aa7ed) SHA1(ee5fdeb5411034ce0fd1c883ee25bf1fe9a3ec52) )
	1181	ROM_LOAD16_BYTE( "tfb-7.bin", 0x20000, 0x10000, CRC(fde8de7e) SHA1(6b0d27ec49c8c0609c110ad97938bec8c077ad18) )
	1182	ROM_LOAD16_BYTE( "tfb-2.bin", 0x20001, 0x10000, CRC(db987414) SHA1(0a1734794c626cf9083d7854c9000c5daadfc3fd) )
	1183	ROM_LOAD16_BYTE( "tfb-6.bin", 0x40000, 0x08000, CRC(1de681a1) SHA1(bddf404988226698d65e075b4c21de736a862df1) )
	1184	ROM_LOAD16_BYTE( "tfb-1.bin", 0x40001, 0x08000, CRC(6a0b94c7) SHA1(55fb32ab859bf51a1c79bf962bb677fa557216ed) )
	1185
	1186	ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* Z80 code (sound) */
	1187	ROM_LOAD( "tf-001.17k", 0x00000, 0x10000, CRC(eb6b4138) SHA1(04c53bf46d87a156d3fad86f051985d0df79bd20) )
	1188
	1189	ROM_REGION( 0x4000, REGION_CPU3, 0 ) /* z80 program (replacement mcu/blitter) */
	1190	ROM_LOAD( "tfb-10.bin", 0x0000, 0x4000, CRC(3f9aa367) SHA1(8278fb357b2d68869e39efa01ff19005807b41f8) )
	1191
	1192	ROM_REGION( 0x08000, REGION_GFX1, ROMREGION_DISPOSE )
	1193	ROM_LOAD( "9.11e", 0x00000, 0x08000, CRC(bc6f7cbc) SHA1(20b8a34de4bfa0c2fdcd2f7743a0ab35141f4bf9) ) /* characters */
	1194
	1195	ROM_REGION( 0x20000, REGION_GFX2, ROMREGION_DISPOSE )
	1196	ROM_LOAD( "5.15h", 0x00000, 0x10000, CRC(25d23dfd) SHA1(da32895c1aca403209b7fb181fa4fa23a8e74d32) ) /* foreground tiles */
	1197	ROM_LOAD( "4.13h", 0x10000, 0x10000, CRC(b9b0fe27) SHA1(983c48239ba1524b517f89f281f2b70564bea1e9) )
	1198
	1199	ROM_REGION( 0x20000, REGION_GFX3, ROMREGION_DISPOSE )
	1200	ROM_LOAD( "15.8a", 0x00000, 0x10000, CRC(2144d8e0) SHA1(ed89da11abf3d79753b478603009970c2600ab60) ) /* background tiles */
	1201	ROM_LOAD( "14.6a", 0x10000, 0x10000, CRC(744f5c9e) SHA1(696223a087bb575c7cfaba11e682b221ada461e4) )
	1202
	1203	ROM_REGION( 0x20000, REGION_GFX4, ROMREGION_DISPOSE )
	1204	ROM_LOAD( "tf-003.7d", 0x00000, 0x10000, CRC(d74085a1) SHA1(3f6ba85dbd6e48a502c115b2d322a586fc4f56c9) ) /* sprites */
	1205	ROM_LOAD( "tf-002.9d", 0x10000, 0x10000, CRC(148aa0c5) SHA1(8d8a565540e91b384a9c154522501921b7da4d4e) )
	1206
	1207
	1208	ROM_REGION( 0x0100, REGION_PROMS, 0 ) /* Unknown use */
	1209	ROM_LOAD( "n82s129an.11j", 0x0000, 0x0100, CRC(81244757) SHA1(6324f63e571f0f7a0bb9eb97f9994809db79493f) ) /* N82S129AN or compatible labled "TF" */
	1210	ROM_END
	1211
	1212
1056	1213	ROM_START( terrafu )
1057	1214	ROM_REGION( 0x50000, REGION_CPU1, 0 ) /* 64K8 for 68000 code /
1058	1215	ROM_LOAD16_BYTE( "tf-8.6e", 0x00000, 0x10000, CRC(fea6dd64) SHA1(682eae338ce14808f134897f594fae1c69e75a1a) )
r2864	r2865
1309	1466	GAME( 1987, legion, 0, legion, legion, legion, ROT270, "Nichibutsu", "Chouji Meikyuu Legion (ver 2.03)", GAME_IMPERFECT_GRAPHICS \| GAME_UNEMULATED_PROTECTION )
1310	1467	GAME( 1987, legiono, legion, legiono, legion, legiono, ROT270, "Nichibutsu", "Chouji Meikyuu Legion (ver 1.05)", GAME_IMPERFECT_GRAPHICS \| GAME_UNEMULATED_PROTECTION )
1311	1468	GAME( 1987, terraf, 0, terraf, terraf, terraf, ROT0, "Nichibutsu", "Terra Force (set 1)", GAME_IMPERFECT_GRAPHICS \| GAME_UNEMULATED_PROTECTION )
	1469	GAME( 1987, terrafb, terraf, terrafb, terraf, terrafu, ROT0, "bootleg", "Terra Force (bootleg with additional Z80)",GAME_NOT_WORKING )
1312	1470	GAME( 1987, terrafa, terraf, terraf, terraf, terrafu, ROT0, "Nichibutsu", "Terra Force (set 2)", GAME_IMPERFECT_GRAPHICS \| GAME_UNEMULATED_PROTECTION )
1313	1471	GAME( 1987, terrafu, terraf, terraf, terraf, terrafu, ROT0, "Nichibutsu USA", "Terra Force (US)", GAME_IMPERFECT_GRAPHICS \| GAME_UNEMULATED_PROTECTION )
1314	1472	GAME( 1987, kodure, 0, kodure, kodure, kodure, ROT0, "Nichibutsu", "Kodure Ookami (Japan)", GAME_IMPERFECT_GRAPHICS \| GAME_UNEMULATED_PROTECTION )

src/mame/drivers/ddenlovr.c
r2864	r2865
1307	1307
1308	1308	static READ16_HANDLER( ddenlovr_special_r )
1309	1309	{
1310		int res = input_port_read~~_indexed~~(machine, 2) \| (ddenlovr_blitter_irq_flag << 6);
	1310	int res = input_port_read(machine, "IN2") \| (ddenlovr_blitter_irq_flag << 6);
1311	1311
1312	1312	return res;
1313	1313	}
r2864	r2865
1488	1488	/* 0 and 1 are read from offset 1, 2 from offset 0... */
1489	1489	switch( ddenlovr_select2 )
1490	1490	{
1491		case 0x00: return input_port_read_indexed(machine, 0);
1492		case 0x01: return input_port_read_indexed(machine, 1);
1493		case 0x02: return input_port_read_indexed(machine, 2);
	1491	case 0x00: return input_port_read(machine, "IN0");
	1492	case 0x01: return input_port_read(machine, "IN1");
	1493	case 0x02: return input_port_read(machine, "IN2");
1494	1494	}
1495	1495	return 0xff;
1496	1496	}
r2864	r2865
1498	1498
1499	1499	static READ8_HANDLER( quiz365_input_r )
1500	1500	{
1501		if (!(ddenlovr_select & 0x01)) return input_port_read_indexed(machine, 3);
1502		if (!(ddenlovr_select & 0x02)) return input_port_read_indexed(machine, 4);
1503		if (!(ddenlovr_select & 0x04)) return input_port_read_indexed(machine, 5);
	1501	if (!(ddenlovr_select & 0x01)) return input_port_read(machine, "DSW1");
	1502	if (!(ddenlovr_select & 0x02)) return input_port_read(machine, "DSW2");
	1503	if (!(ddenlovr_select & 0x04)) return input_port_read(machine, "DSW3");
1504	1504	if (!(ddenlovr_select & 0x08)) return 0xff;//mame_rand(machine);
1505	1505	if (!(ddenlovr_select & 0x10)) return 0xff;//mame_rand(machine);
1506	1506	return 0xff;
r2864	r2865
1512	1512	/* 0 and 1 are read from offset 1, 2 from offset 0... */
1513	1513	switch( ddenlovr_select2 )
1514	1514	{
1515		case 0x10: return input_port_read_indexed(machine, 0);
1516		case 0x11: return input_port_read_indexed(machine, 1);
1517		case 0x12: return input_port_read_indexed(machine, 2) \| (ddenlovr_blitter_irq_flag << 6);
	1515	case 0x10: return input_port_read(machine, "IN0");
	1516	case 0x11: return input_port_read(machine, "IN1");
	1517	case 0x12: return input_port_read(machine, "IN2") \| (ddenlovr_blitter_irq_flag << 6);
1518	1518	}
1519	1519	return 0xff;
1520	1520	}
r2864	r2865
1617	1617	static READ16_HANDLER( ddenlvrj_dsw_r )
1618	1618	{
1619	1619	UINT16 dsw = 0;
1620		if ((~*ddenlvrj_dsw_sel) & 0x01) dsw \|= input_port_read_indexed(machine, 3); // dsw 1
1621		if ((~*ddenlvrj_dsw_sel) & 0x02) dsw \|= input_port_read_indexed(machine, 4); // dsw 2
1622		if ((~*ddenlvrj_dsw_sel) & 0x04) dsw \|= input_port_read_indexed(machine, 5); // ?
	1620	if ((~*ddenlvrj_dsw_sel) & 0x01) dsw \|= input_port_read(machine, "DSW1"); // dsw 1
	1621	if ((~*ddenlvrj_dsw_sel) & 0x02) dsw \|= input_port_read(machine, "DSW2"); // dsw 2
	1622	if ((~*ddenlvrj_dsw_sel) & 0x04) dsw \|= input_port_read(machine, "DSW3"); // ?
1623	1623	return dsw;
1624	1624	}
1625	1625
r2864	r2865
1635	1635
1636	1636	static READ16_HANDLER( ddenlvrj_blitter_r )
1637	1637	{
1638		return input_port_read~~_indexed~~(machine, 2) \| (ddenlovr_blitter_irq_flag ? 0x60 : 0x00 ); // bit 4 = 1 -> blitter busy
	1638	return input_port_read(machine, "IN2") \| (ddenlovr_blitter_irq_flag ? 0x60 : 0x00 ); // bit 4 = 1 -> blitter busy
1639	1639	}
1640	1640
1641	1641	static ADDRESS_MAP_START( ddenlvrj_readmem, ADDRESS_SPACE_PROGRAM, 16 )
r2864	r2865
1720	1720
1721	1721	static READ16_HANDLER( nettoqc_special_r )
1722	1722	{
1723		return input_port_read~~_indexed~~(machine, 2) \| (ddenlovr_blitter_irq_flag ? 0x60 : 0x00 );
	1723	return input_port_read(machine, "IN2") \| (ddenlovr_blitter_irq_flag ? 0x60 : 0x00 );
1724	1724	}
1725	1725
1726	1726	static READ16_HANDLER( nettoqc_input_r )
1727	1727	{
1728		if (!(ddenlovr_select & 0x01)) return input_port_read_indexed(machine, 3);
1729		if (!(ddenlovr_select & 0x02)) return input_port_read_indexed(machine, 4);
1730		if (!(ddenlovr_select & 0x04)) return input_port_read_indexed(machine, 5);
	1728	if (!(ddenlovr_select & 0x01)) return input_port_read(machine, "DSW1");
	1729	if (!(ddenlovr_select & 0x02)) return input_port_read(machine, "DSW2");
	1730	if (!(ddenlovr_select & 0x04)) return input_port_read(machine, "DSW3");
1731	1731	return 0xffff;
1732	1732	}
1733	1733
r2864	r2865
1812	1812
1813	1813	static READ8_HANDLER( rongrong_input_r )
1814	1814	{
1815		if (!(ddenlovr_select & 0x01)) return input_port_read_indexed(machine, 3);
1816		if (!(ddenlovr_select & 0x02)) return input_port_read_indexed(machine, 4);
	1815	if (!(ddenlovr_select & 0x01)) return input_port_read(machine, "DSW1");
	1816	if (!(ddenlovr_select & 0x02)) return input_port_read(machine, "DSW2");
1817	1817	if (!(ddenlovr_select & 0x04)) return 0xff;//mame_rand(machine);
1818	1818	if (!(ddenlovr_select & 0x08)) return 0xff;//mame_rand(machine);
1819		if (!(ddenlovr_select & 0x10)) return input_port_read~~_indexed~~(machine, 5);
	1819	if (!(ddenlovr_select & 0x10)) return input_port_read(machine, "DSW3");
1820	1820	return 0xff;
1821	1821	}
1822	1822
r2864	r2865
2017	2017	AM_RANGE(0x38, 0x38) AM_READ(unk_r ) // ? must be 78 on startup
2018	2018	AM_RANGE(0x58, 0x58) AM_READ(unk_r ) // ? must be 78 on startup
2019	2019	AM_RANGE(0x63, 0x63) AM_READ(rongrong_gfxrom_r ) // Video Chip
2020		AM_RANGE(0x6a, 0x6a) AM_READ(input_port_0_r )
2021		AM_RANGE(0x6b, 0x6b) AM_READ(input_port_1_r )
	2020	AM_RANGE(0x6a, 0x6a) AM_READ_PORT("IN0")
	2021	AM_RANGE(0x6b, 0x6b) AM_READ_PORT("IN1")
2022	2022	AM_RANGE(0x6c, 0x6d) AM_READ(mmpanic_link_r ) // Other cabinets?
2023	2023	AM_RANGE(0x7c, 0x7c) AM_READ(OKIM6295_status_0_r ) // Sound
2024		AM_RANGE(0x94, 0x94) AM_READ(input_port_2_r ) // DSW 1
2025		AM_RANGE(0x98, 0x98) AM_READ(input_port_3_r ) // DSW 2
2026		AM_RANGE(0x9c, 0x9c) AM_READ(input_port_4_r ) // DSW 1&2 high bits
	2024	AM_RANGE(0x94, 0x94) AM_READ_PORT("DSW1") // DSW 1
	2025	AM_RANGE(0x98, 0x98) AM_READ_PORT("DSW2") // DSW 2
	2026	AM_RANGE(0x9c, 0x9c) AM_READ_PORT("DSW3") // DSW 1&2 high bits
2027	2027	ADDRESS_MAP_END
2028	2028
2029	2029	static ADDRESS_MAP_START( mmpanic_writeport, ADDRESS_SPACE_IO, 8 )
r2864	r2865
2135	2135
2136	2136	static READ8_HANDLER( funkyfig_dsw_r )
2137	2137	{
2138		if (!(ddenlovr_select & 0x01)) return input_port_read_indexed(machine, 3);
2139		if (!(ddenlovr_select & 0x02)) return input_port_read_indexed(machine, 4);
2140		if (!(ddenlovr_select & 0x04)) return input_port_read_indexed(machine, 5);
	2138	if (!(ddenlovr_select & 0x01)) return input_port_read(machine, "DSW1");
	2139	if (!(ddenlovr_select & 0x02)) return input_port_read(machine, "DSW2");
	2140	if (!(ddenlovr_select & 0x04)) return input_port_read(machine, "DSW3");
2141	2141	logerror("%06x: warning, unknown bits read, ddenlovr_select = %02x\n", activecpu_get_pc(), ddenlovr_select);
2142	2142	return 0xff;
2143	2143	}
r2864	r2865
2148	2148	{
2149	2149	switch( ddenlovr_select2 )
2150	2150	{
2151		case 0x22: return input_port_read~~_indexed~~(machine, 2);
	2151	case 0x22: return input_port_read(machine, "IN2");
2152	2152	case 0x23: return funkyfig_lockout;
2153	2153	}
2154	2154	logerror("%06x: warning, unknown bits read, ddenlovr_select2 = %02x\n", activecpu_get_pc(), ddenlovr_select2);
r2864	r2865
2159	2159	{
2160	2160	switch( ddenlovr_select2 )
2161	2161	{
2162		case 0x20: return input_port_read_indexed(machine, 0);
2163		case 0x21: return input_port_read_indexed(machine, 1);
	2162	case 0x20: return input_port_read(machine, "IN0");
	2163	case 0x21: return input_port_read(machine, "IN1");
2164	2164	}
2165	2165	logerror("%06x: warning, unknown bits read, ddenlovr_select2 = %02x\n", activecpu_get_pc(), ddenlovr_select2);
2166	2166	return 0xff;
r2864	r2865
2270	2270	{
2271	2271	UINT8 val = 0xff;
2272	2272
2273		if (!(keyb & 0x01)) val = input_port_read_indexed(machine, offset * 5 + 1);
2274		else if (!(keyb & 0x02)) val = input_port_read_indexed(machine, offset * 5 + 2);
2275		else if (!(keyb & 0x04)) val = input_port_read_indexed(machine, offset * 5 + 3);
2276		else if (!(keyb & 0x08)) val = input_port_read_indexed(machine, offset * 5 + 4);
2277		else if (!(keyb & 0x10)) val = input_port_read_indexed(machine, offset * 5 + 5);
	2273	if (!(keyb & 0x01)) val = input_port_read(machine, offset ? "KEY5" : "KEY0");
	2274	else if (!(keyb & 0x02)) val = input_port_read(machine, offset ? "KEY6" : "KEY1");
	2275	else if (!(keyb & 0x04)) val = input_port_read(machine, offset ? "KEY7" : "KEY2");
	2276	else if (!(keyb & 0x08)) val = input_port_read(machine, offset ? "KEY8" : "KEY3");
	2277	else if (!(keyb & 0x10)) val = input_port_read(machine, offset ? "KEY9" : "KEY4");
2278	2278
2279		val \|= input_port_read~~_indexed~~(machine, ~~16 +~~ offset);
	2279	val \|= input_port_read(machine, offset ? "HOPPER" : "BET");
2280	2280	return val;
2281	2281	}
2282	2282
2283	2283	static READ8_HANDLER( hanakanz_dsw_r )
2284	2284	{
2285		if (!(dsw & 0x01)) return input_port_read_indexed(machine, 11);
2286		if (!(dsw & 0x02)) return input_port_read_indexed(machine, 12);
2287		if (!(dsw & 0x04)) return input_port_read_indexed(machine, 13);
2288		if (!(dsw & 0x08)) return input_port_read_indexed(machine, 14);
2289		if (!(dsw & 0x10)) return input_port_read_indexed(machine, 15);
	2285	if (!(dsw & 0x01)) return input_port_read(machine, "DSW1");
	2286	if (!(dsw & 0x02)) return input_port_read(machine, "DSW2");
	2287	if (!(dsw & 0x04)) return input_port_read(machine, "DSW3");
	2288	if (!(dsw & 0x08)) return input_port_read(machine, "DSW4");
	2289	if (!(dsw & 0x10)) return input_port_read(machine, "DSW5");
2290	2290	return 0xff;
2291	2291	}
2292	2292
r2864	r2865
2376	2376	AM_RANGE(0x2c, 0x2c) AM_READ( hanakanz_busy_r )
2377	2377	AM_RANGE(0x32, 0x32) AM_READ( hanakanz_dsw_r )
2378	2378	AM_RANGE(0x83, 0x84) AM_READ( hanakanz_gfxrom_r )
2379		AM_RANGE(0x90, 0x90) AM_READ~~( input~~_~~port_~~0_r )
	2379	AM_RANGE(0x90, 0x90) AM_READ_PORT("IN0")
2380	2380	AM_RANGE(0x91, 0x92) AM_READ( hanakanz_keyb_r )
2381	2381	AM_RANGE(0x96, 0x96) AM_READ( hanakanz_rand_r )
2382	2382	AM_RANGE(0xc0, 0xc0) AM_READ( OKIM6295_status_0_r )
r2864	r2865
2403	2403	AM_RANGE(0x2c, 0x2c) AM_READ( hanakanz_busy_r )
2404	2404	AM_RANGE(0x32, 0x32) AM_READ( hanakanz_dsw_r )
2405	2405	AM_RANGE(0x83, 0x84) AM_READ( hanakanz_gfxrom_r )
2406		AM_RANGE(0xb0, 0xb0) AM_READ~~( input~~_~~port_~~0_r )
	2406	AM_RANGE(0xb0, 0xb0) AM_READ_PORT("IN0")
2407	2407	AM_RANGE(0xb1, 0xb2) AM_READ( hanakanz_keyb_r )
2408	2408	AM_RANGE(0xb6, 0xb6) AM_READ( hanakanz_rand_r )
2409	2409	AM_RANGE(0xc0, 0xc0) AM_READ( OKIM6295_status_0_r )
r2864	r2865
2444	2444	AM_RANGE(0x83, 0x84) AM_READ( hanakanz_gfxrom_r )
2445	2445	AM_RANGE(0x92, 0x92) AM_READ( hanakanz_rand_r )
2446	2446	AM_RANGE(0x93, 0x93) AM_READ( mjreach1_protection_r )
2447		AM_RANGE(0x94, 0x94) AM_READ~~( input~~_~~port_~~0_r )
	2447	AM_RANGE(0x94, 0x94) AM_READ_PORT("IN0")
2448	2448	AM_RANGE(0x95, 0x96) AM_READ( hanakanz_keyb_r )
2449	2449	AM_RANGE(0xc0, 0xc0) AM_READ( OKIM6295_status_0_r )
2450	2450	AM_RANGE(0xe0, 0xef) AM_DEVREAD(MSM6242, "rtc", msm6242_r) // 6242RTC
r2864	r2865
2475	2475	{
2476	2476	UINT8 val = 0xff;
2477	2477
2478		if (!(keyb & 0x01)) val = input_port_read_indexed(machine, offset * 5 + 1);
2479		else if (!(keyb & 0x02)) val = input_port_read_indexed(machine, offset * 5 + 2);
2480		else if (!(keyb & 0x04)) val = input_port_read_indexed(machine, offset * 5 + 3);
2481		else if (!(keyb & 0x08)) val = input_port_read_indexed(machine, offset * 5 + 4);
2482		else if (!(keyb & 0x10)) val = input_port_read_indexed(machine, offset * 5 + 5);
	2478	if (!(keyb & 0x01)) val = input_port_read(machine, offset ? "KEY5" : "KEY0");
	2479	else if (!(keyb & 0x02)) val = input_port_read(machine, offset ? "KEY6" : "KEY1");
	2480	else if (!(keyb & 0x04)) val = input_port_read(machine, offset ? "KEY7" : "KEY2");
	2481	else if (!(keyb & 0x08)) val = input_port_read(machine, offset ? "KEY8" : "KEY3");
	2482	else if (!(keyb & 0x10)) val = input_port_read(machine, offset ? "KEY9" : "KEY4");
2483	2483
2484		val \|= input_port_read~~_indexed~~(machine, ~~16 +~~ offset);
	2484	val \|= input_port_read(machine, offset ? "HOPPER" : "BET");
2485	2485	if (offset) val \|= 0x80; // blitter busy
2486	2486	return val;
2487	2487	}
r2864	r2865
2573	2573	static ADDRESS_MAP_START( mjchuuka_readport, ADDRESS_SPACE_IO, 8 ) // 16 bit I/O
2574	2574	AM_RANGE(0x13, 0x13) AM_MIRROR(0xff00) AM_READ( hanakanz_rand_r )
2575	2575	AM_RANGE(0x23, 0x23) AM_MIRROR(0xff00) AM_READ( mjchuuka_gfxrom_0_r )
2576		AM_RANGE(0x42, 0x42) AM_MIRROR(0xff00) AM_READ~~( input~~_~~port_~~0_r )
	2576	AM_RANGE(0x42, 0x42) AM_MIRROR(0xff00) AM_READ_PORT("IN0")
2577	2577	AM_RANGE(0x43, 0x44) AM_MIRROR(0xff00) AM_READ( mjchuuka_keyb_r )
2578	2578	AM_RANGE(0x45, 0x45) AM_MIRROR(0xff00) AM_READ( mjchuuka_gfxrom_1_r )
2579		AM_RANGE(0x60, 0x60) AM_MIRROR(0xff00) AM_READ( input_port_11_r ) // DSW 1
2580		AM_RANGE(0x61, 0x61) AM_MIRROR(0xff00) AM_READ( input_port_12_r ) // DSW 2
2581		AM_RANGE(0x62, 0x62) AM_MIRROR(0xff00) AM_READ( input_port_13_r ) // DSW 3
2582		AM_RANGE(0x63, 0x63) AM_MIRROR(0xff00) AM_READ( input_port_14_r ) // DSW 4
2583		AM_RANGE(0x64, 0x64) AM_MIRROR(0xff00) AM_READ( input_port_15_r ) // DSW 1-4 high bits
	2579	AM_RANGE(0x60, 0x60) AM_MIRROR(0xff00) AM_READ_PORT("DSW1") // DSW 1
	2580	AM_RANGE(0x61, 0x61) AM_MIRROR(0xff00) AM_READ_PORT("DSW2") // DSW 2
	2581	AM_RANGE(0x62, 0x62) AM_MIRROR(0xff00) AM_READ_PORT("DSW3") // DSW 3
	2582	AM_RANGE(0x63, 0x63) AM_MIRROR(0xff00) AM_READ_PORT("DSW4") // DSW 4
	2583	AM_RANGE(0x64, 0x64) AM_MIRROR(0xff00) AM_READ_PORT("DSW5") // DSW 1-4 high bits
2584	2584	AM_RANGE(0x80, 0x80) AM_MIRROR(0xff00) AM_READ( OKIM6295_status_0_r )
2585	2585	AM_RANGE(0xc0, 0xcf) AM_MIRROR(0xff00) AM_DEVREAD(MSM6242, "rtc", msm6242_r) // 6242RTC
2586	2586	ADDRESS_MAP_END
r2864	r2865
2637	2637	{
2638	2638	switch( ddenlovr_select2 )
2639	2639	{
2640		case 0x00: return input_port_read~~_indexed~~(machine, 0);
	2640	case 0x00: return input_port_read(machine, "IN0");
2641	2641	case 0x01: return 0xff;
2642	2642	case 0x02: return 0xff; // bit 7 = 0 -> blitter busy, + hopper switch
2643	2643	case 0x03: return 0xff;
r2864	r2865
2652	2652	{
2653	2653	UINT8 ret = 0xff;
2654	2654
2655		if (keyb & 0x01) ret = input_port_read_indexed(machine, 1);
2656		else if (keyb & 0x02) ret = input_port_read_indexed(machine, 2);
2657		else if (keyb & 0x04) ret = input_port_read_indexed(machine, 3);
2658		else if (keyb & 0x08) ret = input_port_read_indexed(machine, 4);
2659		else if (keyb & 0x10) ret = input_port_read_indexed(machine, 5);
	2655	if (keyb & 0x01) ret = input_port_read(machine, "KEY0");
	2656	else if (keyb & 0x02) ret = input_port_read(machine, "KEY1");
	2657	else if (keyb & 0x04) ret = input_port_read(machine, "KEY2");
	2658	else if (keyb & 0x08) ret = input_port_read(machine, "KEY3");
	2659	else if (keyb & 0x10) ret = input_port_read(machine, "KEY4");
2660	2660	else logerror("%06x: warning, unknown bits read, keyb = %02x\n", activecpu_get_pc(), keyb);
2661	2661
2662	2662	keyb <<= 1;
r2864	r2865
2666	2666
2667	2667	static READ8_HANDLER( mjmyster_dsw_r )
2668	2668	{
2669		if (!(ddenlovr_select & 0x01)) return input_port_read_indexed(machine, 9);
2670		if (!(ddenlovr_select & 0x02)) return input_port_read_indexed(machine, 8);
2671		if (!(ddenlovr_select & 0x04)) return input_port_read_indexed(machine, 7);
2672		if (!(ddenlovr_select & 0x08)) return input_port_read_indexed(machine, 6);
2673		if (!(ddenlovr_select & 0x10)) return input_port_read_indexed(machine, 10);
	2669	if (!(ddenlovr_select & 0x01)) return input_port_read(machine, "DSW4");
	2670	if (!(ddenlovr_select & 0x02)) return input_port_read(machine, "DSW3");
	2671	if (!(ddenlovr_select & 0x04)) return input_port_read(machine, "DSW2");
	2672	if (!(ddenlovr_select & 0x08)) return input_port_read(machine, "DSW1");
	2673	if (!(ddenlovr_select & 0x10)) return input_port_read(machine, "DSW5");
2674	2674	logerror("%06x: warning, unknown bits read, ddenlovr_select = %02x\n", activecpu_get_pc(), ddenlovr_select);
2675	2675	return 0xff;
2676	2676	}
r2864	r2865
2769	2769
2770	2770	static READ8_HANDLER( hginga_dsw_r )
2771	2771	{
2772		if (!(ddenlovr_select & 0x01)) return input_port_read_indexed(machine, 11);
2773		if (!(ddenlovr_select & 0x02)) return input_port_read_indexed(machine, 12);
2774		if (!(ddenlovr_select & 0x04)) return input_port_read_indexed(machine, 13);
2775		if (!(ddenlovr_select & 0x08)) return input_port_read_indexed(machine, 14);
2776		if (!(ddenlovr_select & 0x10)) return input_port_read_indexed(machine, 15);
	2772	if (!(ddenlovr_select & 0x01)) return input_port_read(machine, "DSW4");
	2773	if (!(ddenlovr_select & 0x02)) return input_port_read(machine, "DSW3");
	2774	if (!(ddenlovr_select & 0x04)) return input_port_read(machine, "DSW2");
	2775	if (!(ddenlovr_select & 0x08)) return input_port_read(machine, "DSW1");
	2776	if (!(ddenlovr_select & 0x10)) return input_port_read(machine, "DSW5");
2777	2777	logerror("%06x: warning, unknown bits read, ddenlovr_select = %02x\n", activecpu_get_pc(), ddenlovr_select);
2778	2778	return 0xff;
2779	2779	}
r2864	r2865
2790	2790	{
2791	2791	switch( hginga_select )
2792	2792	{
2793		case 0x20: return input_port_read_indexed(machine, 0);
2794		case 0x21: return input_port_read_indexed(machine, 16);
	2793	case 0x20: return input_port_read(machine, "IN0");
	2794	case 0x21: return input_port_read(machine, "BET");
2795	2795	case 0x22: return 0x7f; // bit 7 = blitter busy, bit 6 = hopper
2796	2796	case 0x23: return hginga_coins;
2797	2797	}
2798		logerror("%04x: coins_r with select = %02x\n",activecpu_get_pc(),hginga_select);
	2798	logerror("%04x: coins_r with select = %02x\n", activecpu_get_pc(), hginga_select);
2799	2799	return 0xff;
2800	2800	}
2801	2801
r2864	r2865
2823	2823	hginga_coins = data;
2824	2824	break;
2825	2825	default:
2826		logerror("%04x: coins_w with select = %02x, data = %02x\n",activecpu_get_pc(),hginga_select,data);
	2826	logerror("%04x: coins_w with select = %02x, data = %02x\n", activecpu_get_pc(), hginga_select, data);
2827	2827	}
2828	2828	}
2829	2829
2830	2830	static READ8_HANDLER( hginga_input_r )
2831	2831	{
	2832	static const char *keynames0[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
	2833	static const char *keynames1[] = { "KEY5", "KEY6", "KEY7", "KEY8", "KEY9" };
	2834
2832	2835	switch( hginga_select )
2833	2836	{
2834	2837	case 0x2d:
r2864	r2865
2836	2839
2837	2840	// player 1
2838	2841	case 0xa1:
2839		return input_port_read~~_indexed~~(machine, ~~1 +~~ hginga_ip++);
	2842	return input_port_read(machine, keynames0[hginga_ip++]);
2840	2843
2841	2844	// player 2
2842	2845	case 0xa2:
2843		return input_port_read~~_indexed~~(machine, 1 ~~+ 5 +~~ hginga_ip++);
	2846	return input_port_read(machine, keynames1[hginga_ip++]);
2844	2847	}
2845		logerror("%04x: input_r with select = %02x\n",activecpu_get_pc(),hginga_select);
	2848	logerror("%04x: input_r with select = %02x\n", activecpu_get_pc(), hginga_select);
2846	2849	return 0xff;
2847	2850	}
2848	2851
r2864	r2865
2918	2921	{
2919	2922	UINT8 hopper_bit = ((hgokou_hopper && !(video_screen_get_frame_number(machine->primary_screen)%10)) ? 0 : (1<<6));
2920	2923
2921		if (!(ddenlovr_select2 & 0x01)) return input_port_read_indexed(machine, player * 5 + 1) \| hopper_bit;
2922		if (!(ddenlovr_select2 & 0x02)) return input_port_read_indexed(machine, player * 5 + 2) \| hopper_bit;
2923		if (!(ddenlovr_select2 & 0x04)) return input_port_read_indexed(machine, player * 5 + 3) \| hopper_bit;
2924		if (!(ddenlovr_select2 & 0x08)) return input_port_read_indexed(machine, player * 5 + 4) \| hopper_bit;
2925		if (!(ddenlovr_select2 & 0x10)) return input_port_read_indexed(machine, player * 5 + 5) \| hopper_bit;
	2924	if (!(ddenlovr_select2 & 0x01)) return input_port_read(machine, player ? "KEY5" : "KEY0") \| hopper_bit;
	2925	if (!(ddenlovr_select2 & 0x02)) return input_port_read(machine, player ? "KEY6" : "KEY1") \| hopper_bit;
	2926	if (!(ddenlovr_select2 & 0x04)) return input_port_read(machine, player ? "KEY7" : "KEY2") \| hopper_bit;
	2927	if (!(ddenlovr_select2 & 0x08)) return input_port_read(machine, player ? "KEY8" : "KEY3") \| hopper_bit;
	2928	if (!(ddenlovr_select2 & 0x10)) return input_port_read(machine, player ? "KEY9" : "KEY4") \| hopper_bit;
2926	2929
2927	2930	return 0x7f; // bit 7 = blitter busy, bit 6 = hopper
2928	2931	}
r2864	r2865
2931	2934	{
2932	2935	switch (hginga_select)
2933	2936	{
2934		case 0x20: return input_port_read~~_indexed~~(machine, 0);
	2937	case 0x20: return input_port_read(machine, "IN0");
2935	2938	case 0x21: return hgokou_player_r(machine, 1);
2936	2939	case 0x22: return hgokou_player_r(machine, 0);
2937	2940	case 0x23: return hginga_coins;
r2864	r2865
3039	3042
3040	3043	static READ8_HANDLER( hparadis_input_r )
3041	3044	{
	3045	static const char *keynames0[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
	3046	static const char *keynames1[] = { "KEY5", "KEY6", "KEY7", "KEY8", "KEY9" };
	3047
3042	3048	switch (hginga_select)
3043	3049	{
3044		case 0x00: return input_port_read_indexed(machine, 0); // P1 (Joy)
3045		case 0x01: return input_port_read_indexed(machine, 1); // P2 (Joy)
3046		case 0x02: return input_port_read_indexed(machine, 2); // Coins
	3050	case 0x00: return input_port_read(machine, "IN0"); // P1 (Joy)
	3051	case 0x01: return input_port_read(machine, "IN1"); // P2 (Joy)
	3052	case 0x02: return input_port_read(machine, "IN2"); // Coins
3047	3053	case 0x0d: return 0x00;
3048		case 0x80: return input_port_read_indexed(machine, 3 + hginga_ip++); // P1 (Keys)
3049		case 0x81: return input_port_read_indexed(machine, 8 + hginga_ip++); // P2 (Keys)
	3054	case 0x80: return input_port_read(machine, keynames0[hginga_ip++]); // P1 (Keys)
	3055	case 0x81: return input_port_read(machine, keynames1[hginga_ip++]); // P2 (Keys)
3050	3056	}
3051	3057	logerror("%06x: warning, unknown bits read, hginga_select = %02x\n", activecpu_get_pc(), hginga_select);
3052	3058	return 0xff;
r2864	r2865
3054	3060
3055	3061	static READ8_HANDLER( hparadis_dsw_r )
3056	3062	{
3057		if (!(ddenlovr_select & 0x01)) return input_port_read_indexed(machine, 13);
3058		if (!(ddenlovr_select & 0x02)) return input_port_read_indexed(machine, 14);
	3063	if (!(ddenlovr_select & 0x01)) return input_port_read(machine, "DSW1");
	3064	if (!(ddenlovr_select & 0x02)) return input_port_read(machine, "DSW2");
3059	3065	if (!(ddenlovr_select & 0x04)) return 0xff;
3060	3066	if (!(ddenlovr_select & 0x08)) return 0xff;
3061		if (!(ddenlovr_select & 0x10)) return input_port_read~~_indexed~~(machine, 15);
	3067	if (!(ddenlovr_select & 0x10)) return input_port_read(machine, "DSW3");
3062	3068	return 0xff;
3063	3069	}
3064	3070
r2864	r2865
3122	3128	{
3123	3129	switch( ddenlovr_select2 )
3124	3130	{
3125		case 0x80: return input_port_read~~_indexed~~(machine, 0);
	3131	case 0x80: return input_port_read(machine, "IN0");
3126	3132	case 0x81: return 0x00;
3127	3133	case 0x82: return 0xff; // bit 7 = 0 -> blitter busy, + hopper switch
3128	3134	case 0x83: return 0x00;
r2864	r2865
3198	3204	static READ16_HANDLER( akamaru_dsw_r )
3199	3205	{
3200	3206	UINT16 dsw = 0;
3201		if (akamaru_dsw_sel[1] == 0xff) dsw \|= input_port_read_indexed(machine, 3);
3202		if (akamaru_dsw_sel[0] == 0xff) dsw \|= input_port_read_indexed(machine, 4);
	3207	if (akamaru_dsw_sel[1] == 0xff) dsw \|= input_port_read(machine, "DSW1");
	3208	if (akamaru_dsw_sel[0] == 0xff) dsw \|= input_port_read(machine, "DSW2");
3203	3209	return dsw;
3204	3210	}
3205	3211
r2864	r2865
3284	3290	{
3285	3291	UINT8 val = 0xff;
3286	3292
3287		if (!(keyb & 0x01)) val = input_port_read_indexed(machine, offset * 5 + 1);
3288		else if (!(keyb & 0x02)) val = input_port_read_indexed(machine, offset * 5 + 2);
3289		else if (!(keyb & 0x04)) val = input_port_read_indexed(machine, offset * 5 + 3);
3290		else if (!(keyb & 0x08)) val = input_port_read_indexed(machine, offset * 5 + 4);
3291		else if (!(keyb & 0x10)) val = input_port_read_indexed(machine, offset * 5 + 5);
	3293	if (!(keyb & 0x01)) val = input_port_read(machine, offset ? "KEY5" : "KEY0");
	3294	else if (!(keyb & 0x02)) val = input_port_read(machine, offset ? "KEY6" : "KEY1");
	3295	else if (!(keyb & 0x04)) val = input_port_read(machine, offset ? "KEY7" : "KEY2");
	3296	else if (!(keyb & 0x08)) val = input_port_read(machine, offset ? "KEY8" : "KEY3");
	3297	else if (!(keyb & 0x10)) val = input_port_read(machine, offset ? "KEY9" : "KEY4");
3292	3298
3293	3299	return val;
3294	3300	}
r2864	r2865
3300	3306	// bit 7 = 1 -> blitter busy
3301	3307	// bit 6 = 0 -> VBLANK?
3302	3308	// bit 5 = 0 -> RTC?
3303		return input_port_read~~_indexed~~(machine, 0) \| mjflove_irq_cause;
	3309	return input_port_read(machine, "IN0") \| mjflove_irq_cause;
3304	3310	}
3305	3311
3306	3312	static WRITE8_HANDLER( mjflove_blitter_w )
r2864	r2865
3322	3328
3323	3329	static ADDRESS_MAP_START( mjflove_readport, ADDRESS_SPACE_IO, 8 ) // 16 bit I/O
3324	3330	AM_RANGE(0x0010, 0x0010) AM_READ( hanakanz_rand_r ) AM_MIRROR(0xff00)
3325		AM_RANGE(0x001c, 0x001c) AM_READ~~( input~~_~~port_1~~2_r ) AM_MIRROR(0xff00)
	3331	AM_RANGE(0x001c, 0x001c) AM_READ_PORT("DSW2") AM_MIRROR(0xff00)
3326	3332	AM_RANGE(0x0038, 0x0038) AM_READ( SMH_NOP ) // ? ack or watchdog
3327	3333	AM_RANGE(0x0043, 0x0043) AM_READ( rongrong_gfxrom_r )
3328	3334	AM_RANGE(0x0080, 0x0081) AM_READ( mjflove_keyb_r )
3329	3335	AM_RANGE(0x0082, 0x0082) AM_READ( mjflove_blitter_r )
3330	3336	AM_RANGE(0x00da, 0x00da) AM_READ( mjflove_protection_r ) AM_MIRROR(0xff00)
3331		AM_RANGE(0x0100, 0x0100) AM_READ~~( input~~_~~port_~~1~~1_r~~ )
	3337	AM_RANGE(0x0100, 0x0100) AM_READ_PORT("DSW1")
3332	3338	AM_RANGE(0x0280, 0x028f) AM_DEVREAD(MSM6242, "rtc", msm6242_r) // 6242RTC
3333	3339	AM_RANGE(0x0380, 0x0380) AM_READ( OKIM6295_status_0_r )
3334	3340	ADDRESS_MAP_END
r2864	r2865
3358	3364
3359	3365
3360	3366	static INPUT_PORTS_START( ddenlvrj )
3361		PORT_START // IN0 - Player 1
	3367	PORT_START_TAG("IN0") /* IN0 - Player 1 */
3362	3368	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
3363	3369	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
3364	3370	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
r2864	r2865
3368	3374	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
3369	3375	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3370	3376
3371		PORT_START // IN1 - Player 2
	3377	PORT_START_TAG("IN1") /* IN1 - Player 2 */
3372	3378	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
3373	3379	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
3374	3380	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
r2864	r2865
3378	3384	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
3379	3385	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3380	3386
3381		PORT_START // IN2 - Coins + ?
	3387	PORT_START_TAG("IN2") /* IN2 - Coins + ? */
3382	3388	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
3383	3389	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
3384	3390	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
3388	3394	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) // RTC
3389	3395	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL )
3390	3396
3391		PORT_START // IN3 - DSW1
	3397	PORT_START_TAG("DSW1") /* IN3 - DSW1 */
3392	3398	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
3393	3399	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
3394	3400	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
3412	3418	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3413	3419	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3414	3420
3415		PORT_START // IN4 - DSW2
	3421	PORT_START_TAG("DSW2") /* IN4 - DSW2 */
3416	3422	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) )
3417	3423	PORT_DIPSETTING( 0x06, "1 (Easy)" )
3418	3424	PORT_DIPSETTING( 0x05, "2" )
r2864	r2865
3437	3443	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3438	3444	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3439	3445
3440		PORT_START // IN5 - DSW1 & 2 top bits
	3446	PORT_START_TAG("DSW3") /* IN5 - DSW1 & 2 top bits */
3441	3447	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
3442	3448	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3443	3449	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3464	3470
3465	3471
3466	3472	static INPUT_PORTS_START( ddenlovr )
3467		PORT_START // IN0 - Player 1
	3473	PORT_START_TAG("IN0") /* IN0 - Player 1 */
3468	3474	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
3469	3475	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
3470	3476	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
r2864	r2865
3474	3480	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
3475	3481	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3476	3482
3477		PORT_START // IN1 - Player 2
	3483	PORT_START_TAG("IN1") /* IN1 - Player 2 */
3478	3484	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
3479	3485	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
3480	3486	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
r2864	r2865
3484	3490	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
3485	3491	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3486	3492
3487		PORT_START // IN2 - Coins + ?
	3493	PORT_START_TAG("IN2") /* IN2 - Coins + ? */
3488	3494	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
3489	3495	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
3490	3496	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
3494	3500	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter irq flag
3495	3501	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter busy flag
3496	3502
3497		PORT_START // IN3 - DSW
	3503	PORT_START_TAG("DSW") /* IN3 - DSW */
3498	3504	PORT_SERVICE( 0x01, IP_ACTIVE_LOW )
3499	3505	PORT_DIPNAME( 0x02, 0x02, "Unknown 1-1" )
3500	3506	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
r2864	r2865
3520	3526
3521	3527
3522	3528	static INPUT_PORTS_START( nettoqc )
3523		PORT_START // IN0 - Player 1
	3529	PORT_START_TAG("IN0") /* IN0 - Player 1 */
3524	3530	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
3525	3531	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
3526	3532	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
r2864	r2865
3530	3536	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
3531	3537	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3532	3538
3533		PORT_START // IN1 - Player 2
	3539	PORT_START_TAG("IN1") /* IN1 - Player 2 */
3534	3540	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
3535	3541	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
3536	3542	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
r2864	r2865
3540	3546	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
3541	3547	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3542	3548
3543		PORT_START // IN2 - Coins + ?
	3549	PORT_START_TAG("IN2") /* IN2 - Coins + ? */
3544	3550	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
3545	3551	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
3546	3552	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
3550	3556	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter irq flag
3551	3557	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL )
3552	3558
3553		PORT_START // IN3 - DSW
	3559	PORT_START_TAG("DSW1") /* IN3 - DSW */
3554	3560	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
3555	3561	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
3556	3562	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
3574	3580	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3575	3581	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3576	3582
3577		PORT_START // IN4 - DSW
	3583	PORT_START_TAG("DSW2") /* IN4 - DSW */
3578	3584	PORT_DIPNAME( 0x03, 0x03, "Unknown 2-0&1*" )
3579	3585	PORT_DIPSETTING( 0x02, "0" )
3580	3586	PORT_DIPSETTING( 0x03, "1" )
r2864	r2865
3599	3605	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3600	3606	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3601	3607
3602		PORT_START // IN5 - DSW
	3608	PORT_START_TAG("DSW3") /* IN5 - DSW */
3603	3609	PORT_DIPNAME( 0x01, 0x01, "Unknown 1-8*" )
3604	3610	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3605	3611	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3618	3624
3619	3625
3620	3626	static INPUT_PORTS_START( quiz365 )
3621		PORT_START // IN0 - Player 1
	3627	PORT_START_TAG("IN0") /* IN0 - Player 1 */
3622	3628	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
3623	3629	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
3624	3630	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
r2864	r2865
3628	3634	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
3629	3635	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3630	3636
3631		PORT_START // IN1 - Player 2
	3637	PORT_START_TAG("IN1") /* IN1 - Player 2 */
3632	3638	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
3633	3639	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
3634	3640	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
r2864	r2865
3638	3644	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
3639	3645	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3640	3646
3641		PORT_START // IN2 - Coins + ?
	3647	PORT_START_TAG("IN2") /* IN2 - Coins + ? */
3642	3648	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
3643	3649	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
3644	3650	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
3645		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) /* Test */
	3651	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) /* Test */
3646	3652	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
3647	3653	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SPECIAL ) // ? quiz365
3648	3654	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter irq flag
3649	3655	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter busy flag
3650	3656
3651		PORT_START // IN3 - DSW
	3657	PORT_START_TAG("DSW1") /* IN3 - DSW */
3652	3658	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
3653	3659	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
3654	3660	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
3671	3677	PORT_DIPSETTING( 0xc0, "2" )
3672	3678	// PORT_DIPSETTING( 0x00, "2" )
3673	3679
3674		PORT_START // IN4 - DSW
	3680	PORT_START_TAG("DSW2") /* IN4 - DSW */
3675	3681	PORT_DIPNAME( 0x03, 0x03, "Unknown 2-0&1" )
3676	3682	PORT_DIPSETTING( 0x02, "0" )
3677	3683	PORT_DIPSETTING( 0x03, "1" )
r2864	r2865
3695	3701	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3696	3702	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3697	3703
3698		PORT_START // IN5 - DSW
	3704	PORT_START_TAG("DSW3") /* IN5 - DSW */
3699	3705	PORT_DIPNAME( 0x01, 0x01, "Unknown 3-0" )
3700	3706	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3701	3707	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3711	3717
3712	3718
3713	3719	static INPUT_PORTS_START( rongrong )
3714		PORT_START // IN0 - Player 1
	3720	PORT_START_TAG("IN0") /* IN0 - Player 1 */
3715	3721	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
3716	3722	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
3717	3723	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
r2864	r2865
3721	3727	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
3722	3728	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
3723	3729
3724		PORT_START // IN1 - Player 2
	3730	PORT_START_TAG("IN1") /* IN1 - Player 2 */
3725	3731	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
3726	3732	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
3727	3733	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
r2864	r2865
3731	3737	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
3732	3738	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
3733	3739
3734		PORT_START // IN2 - Coins + ?
	3740	PORT_START_TAG("IN2") /* IN2 - Coins + ? */
3735	3741	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
3736	3742	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
3737	3743	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
3741	3747	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SPECIAL ) // ? blitter irq flag ?
3742	3748	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) // ? blitter busy flag ?
3743	3749
3744		PORT_START // IN3 - DSW
	3750	PORT_START_TAG("DSW1") /* IN3 - DSW */
3745	3751	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
3746	3752	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
3747	3753	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
3765	3771	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3766	3772	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3767	3773
3768		PORT_START // IN4 - DSW
	3774	PORT_START_TAG("DSW2") /* IN4 - DSW */
3769	3775	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
3770	3776	PORT_DIPSETTING( 0x02, DEF_STR( Easy ) )
3771	3777	PORT_DIPSETTING( 0x03, DEF_STR( Normal ) )
r2864	r2865
3788	3794	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3789	3795	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3790	3796
3791		PORT_START // IN5 - DSW
	3797	PORT_START_TAG("DSW3") /* IN5 - DSW */
3792	3798	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
3793	3799	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3794	3800	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3803	3809	INPUT_PORTS_END
3804	3810
3805	3811	static INPUT_PORTS_START( quizchq )
3806		PORT_START // IN0 - Player 1
	3812	PORT_START_TAG("IN0") /* IN0 - Player 1 */
3807	3813	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
3808	3814	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
3809	3815	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
r2864	r2865
3813	3819	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
3814	3820	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3815	3821
3816		PORT_START // IN1 - Player 2
	3822	PORT_START_TAG("IN1") /* IN1 - Player 2 */
3817	3823	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
3818	3824	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
3819	3825	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
r2864	r2865
3823	3829	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
3824	3830	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3825	3831
3826		PORT_START // IN2 - Coins + ?
	3832	PORT_START_TAG("IN2") /* IN2 - Coins + ? */
3827	3833	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
3828	3834	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
3829	3835	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
3833	3839	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SPECIAL ) // ? blitter irq flag ?
3834	3840	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) // ? blitter busy flag ?
3835	3841
3836		PORT_START // IN3 - DSW
	3842	PORT_START_TAG("DSW1") /* IN3 - DSW */
3837	3843	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
3838	3844	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
3839	3845	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
3857	3863	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3858	3864	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3859	3865
3860		PORT_START // IN4 - DSW
	3866	PORT_START_TAG("DSW2") /* IN4 - DSW */
3861	3867	PORT_DIPNAME( 0x01, 0x01, "Unknown 2-0" )
3862	3868	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3863	3869	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3881	3887	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3882	3888	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
3883	3889
3884		PORT_START // IN5 - DSW
	3890	PORT_START_TAG("DSW3") /* IN5 - DSW */
3885	3891	PORT_DIPNAME( 0x01, 0x01, "Unknown 1-0" )
3886	3892	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3887	3893	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3898	3904	INPUT_PORTS_END
3899	3905
3900	3906	static INPUT_PORTS_START( mmpanic )
3901		PORT_START // IN0 6a (68 = 1:used? 2:normal 3:goes to 69)
	3907	PORT_START_TAG("IN0") /* IN0 6a (68 = 1:used? 2:normal 3:goes to 69) */
3902	3908	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
3903	3909	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // tested?
3904	3910	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
3908	3914	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("9") PORT_CODE(KEYCODE_9_PAD)
3909	3915	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) // busy?
3910	3916
3911		PORT_START // IN1 6b (68 = 0 & 1)
	3917	PORT_START_TAG("IN1") /* IN1 6b (68 = 0 & 1) */
3912	3918	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
3913	3919	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
3914	3920	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
r2864	r2865
3918	3924	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
3919	3925	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD)
3920	3926
3921		PORT_START // IN2 - DSW
	3927	PORT_START_TAG("DSW1") /* IN2 - DSW */
3922	3928	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
3923	3929	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
3924	3930	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
3943	3949	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3944	3950	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3945	3951
3946		PORT_START // IN3 - DSW
	3952	PORT_START_TAG("DSW2") /* IN3 - DSW */
3947	3953	PORT_DIPNAME( 0x01, 0x01, "Unknown 2-0*" )
3948	3954	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3949	3955	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3968	3974	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3969	3975	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3970	3976
3971		PORT_START // IN4 - DSW
	3977	PORT_START_TAG("DSW3") /* IN4 - DSW */
3972	3978	PORT_DIPNAME( 0x01, 0x01, "Set Date" )
3973	3979	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3974	3980	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
3995	4001
3996	4002
3997	4003	static INPUT_PORTS_START( animaljr )
3998		PORT_START // IN0 6a (68 = 1:used? 2:normal 3:goes to 69)
	4004	PORT_START_TAG("IN0") /* IN0 6a (68 = 1:used? 2:normal 3:goes to 69) */
3999	4005	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
4000	4006	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
4001	4007	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
4005	4011	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
4006	4012	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) // busy?
4007	4013
4008		PORT_START // IN1 6b (68 = 0 & 1)
	4014	PORT_START_TAG("IN1") /* IN1 6b (68 = 0 & 1) */
4009	4015	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // tested ?
4010	4016	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
4011	4017	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
r2864	r2865
4015	4021	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
4016	4022	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
4017	4023
4018		PORT_START // IN2 - DSW
	4024	PORT_START_TAG("DSW1") /* IN2 - DSW */
4019	4025	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
4020	4026	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
4021	4027	PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
r2864	r2865
4040	4046	PORT_DIPSETTING( 0x20, "6" )
4041	4047	PORT_DIPSETTING( 0x00, "7" )
4042	4048
4043		PORT_START // IN3 - DSW
	4049	PORT_START_TAG("DSW2") /* IN3 - DSW */
4044	4050	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
4045	4051	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
4046	4052	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
4065	4071	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
4066	4072	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
4067	4073
4068		PORT_START // IN4 - DSW
	4074	PORT_START_TAG("DSW3") /* IN4 - DSW */
4069	4075	PORT_DIPNAME( 0x01, 0x01, "Unknown 3-0*" )
4070	4076	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
4071	4077	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
4093	4099
4094	4100	static INPUT_PORTS_START( hanakanz )
4095	4101
4096		PORT_START // IN0 - Coins + Service Keys
	4102	PORT_START_TAG("IN0") /* IN0 - Coins + Service Keys */
4097	4103	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE3 ) // medal out
4098	4104	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
4099	4105	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // Test
r2864	r2865
4103	4109	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
4104	4110	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
4105	4111
4106		// keyb 2
4107		PORT_START
	4112	/* keyb 2 */
	4113
	4114	PORT_START_TAG("KEY0")
4108	4115	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) // A
4109	4116	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) // E
4110	4117	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
4112	4119	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Kan
4113	4120	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
4114	4121
4115		PORT_START
	4122	PORT_START_TAG("KEY1")
4116	4123	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) // B
4117	4124	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) // F
4118	4125	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
4120	4127	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Reach
4121	4128	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2) // BET
4122	4129
4123		PORT_START
	4130	PORT_START_TAG("KEY2")
4124	4131	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) // C
4125	4132	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) // G
4126	4133	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
4128	4135	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
4129	4136	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
4130	4137
4131		PORT_START
	4138	PORT_START_TAG("KEY3")
4132	4139	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) // D
4133	4140	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) // H
4134	4141	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
4136	4143	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
4137	4144	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
4138	4145
4139		PORT_START
	4146	PORT_START_TAG("KEY4")
4140	4147	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
4141	4148	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
4142	4149	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
r2864	r2865
4144	4151	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(2) // "b"
4145	4152	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // "s"
4146	4153
4147		// keyb 1
4148		PORT_START
	4154	/* keyb 1 */
	4155
	4156	PORT_START_TAG("KEY5")
4149	4157	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD) // A
4150	4158	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD) // E
4151	4159	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
4153	4161	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Kan
4154	4162	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
4155	4163
4156		PORT_START
	4164	PORT_START_TAG("KEY6")
4157	4165	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD) // B
4158	4166	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD) // F
4159	4167	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
4161	4169	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Reach
4162	4170	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) // BET
4163	4171
4164		PORT_START
	4172	PORT_START_TAG("KEY7")
4165	4173	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD) // C
4166	4174	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD) // G
4167	4175	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
4169	4177	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
4170	4178	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
4171	4179
4172		PORT_START
	4180	PORT_START_TAG("KEY8")
4173	4181	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD) // D
4174	4182	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("8") PORT_CODE(KEYCODE_8_PAD) // H
4175	4183	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
4177	4185	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
4178	4186	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
4179	4187
4180		PORT_START
	4188	PORT_START_TAG("KEY9")
4181	4189	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
4182	4190	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
4183	4191	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
r2864	r2865
4185	4193	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
4186	4194	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
4187	4195
4188		PORT_START // IN11 - DSW1
	4196	PORT_START_TAG("DSW1") /* IN11 - DSW1 */
4189	4197	PORT_DIPNAME( 0x07, 0x07, "Unknown 1-0&1&2" )
4190	4198	PORT_DIPSETTING( 0x07, "0" )
4191	4199	PORT_DIPSETTING( 0x06, "1" )
r2864	r2865
4210	4218	PORT_DIPSETTING( 0x00, "5" )
4211	4219	PORT_DIPSETTING( 0x80, "10" )
4212	4220
4213		PORT_START // IN12 - DSW2
	4221	PORT_START_TAG("DSW2") /* IN12 - DSW2 */
4214	4222	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
4215	4223	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
4216	4224	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
4232	4240	PORT_DIPSETTING( 0x40, "70" )
4233	4241	PORT_DIPSETTING( 0x00, "80" )
4234	4242
4235		PORT_START // IN13 - DSW3
	4243	PORT_START_TAG("DSW3") /* IN13 - DSW3 */
4236	4244	PORT_DIPNAME( 0x03, 0x03, "Game Type" )
4237	4245	PORT_DIPSETTING( 0x03, "8 Cards" )
4238	4246	PORT_DIPSETTING( 0x02, "6 Cards (Bets)" )
r2864	r2865
4255	4263	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
4256	4264	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
4257	4265
4258		PORT_START // IN14 - DSW4
	4266	PORT_START_TAG("DSW4") /* IN14 - DSW4 */
4259	4267	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Demo_Sounds ) )
4260	4268	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
4261	4269	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
4281	4289	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
4282	4290	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4283	4291
4284		PORT_START // IN15 - DSWs top bits
	4292	PORT_START_TAG("DSW5") /* IN15 - DSWs top bits */
4285	4293	PORT_DIPNAME( 0x01, 0x01, "Unknown 1-8" )
4286	4294	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
4287	4295	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
4304	4312	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4305	4313	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
4306	4314
4307		PORT_START // IN16 - Fake DSW
	4315	PORT_START_TAG("BET") /* IN16 - Fake DSW */
4308	4316	PORT_DIPNAME( 0x40, 0x40, "Allow Bets" )
4309	4317	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
4310	4318	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4311	4319
4312		PORT_START // IN17 - Fake DSW
	4320	PORT_START_TAG("HOPPER") /* IN17 - Fake DSW */
4313	4321	PORT_DIPNAME( 0x40, 0x40, "? Hopper M." )
4314	4322	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
4315	4323	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
4319	4327
4320	4328	static INPUT_PORTS_START( hkagerou )
4321	4329
4322		PORT_START // IN0 - Coins + Service Keys
	4330	PORT_START_TAG("IN0") /* IN0 - Coins + Service Keys */
4323	4331	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE3 ) // medal out
4324	4332	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
4325	4333	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // Test
r2864	r2865
4329	4337	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
4330	4338	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
4331	4339
4332		// keyb 2
4333		PORT_START
	4340	/* keyb 2 */
	4341
	4342	PORT_START_TAG("KEY0")
4334	4343	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) // A
4335	4344	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) // E
4336	4345	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
4338	4347	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Kan
4339	4348	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
4340	4349
4341		PORT_START
	4350	PORT_START_TAG("KEY1")
4342	4351	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) // B
4343	4352	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) // F
4344	4353	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
4346	4355	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Reach
4347	4356	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2) // BET
4348	4357
4349		PORT_START
	4358	PORT_START_TAG("KEY2")
4350	4359	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) // C
4351	4360	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) // G
4352	4361	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
4354	4363	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
4355	4364	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
4356	4365
4357		PORT_START
	4366	PORT_START_TAG("KEY3")
4358	4367	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) // D
4359	4368	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) // H
4360	4369	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
4362	4371	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
4363	4372	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
4364	4373
4365		PORT_START
	4374	PORT_START_TAG("KEY4")
4366	4375	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
4367	4376	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
4368	4377	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
r2864	r2865
4370	4379	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(2) // "b"
4371	4380	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // "s"
4372	4381
4373		// keyb 1
4374		PORT_START
	4382	/* keyb 1 */
	4383
	4384	PORT_START_TAG("KEY5")
4375	4385	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD) // A
4376	4386	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD) // E
4377	4387	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
4379	4389	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
4380	4390	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
4381	4391
4382		PORT_START
	4392	PORT_START_TAG("KEY6")
4383	4393	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD) // B
4384	4394	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD) // F
4385	4395	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
4387	4397	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
4388	4398	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) // BET
4389	4399
4390		PORT_START
	4400	PORT_START_TAG("KEY7")
4391	4401	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD) // C
4392	4402	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD) // G
4393	4403	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
4395	4405	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
4396	4406	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
4397	4407
4398		PORT_START
	4408	PORT_START_TAG("KEY8")
4399	4409	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD) // D
4400	4410	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("8") PORT_CODE(KEYCODE_8_PAD) // H
4401	4411	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
4403	4413	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
4404	4414	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
4405	4415
4406		PORT_START
	4416	PORT_START_TAG("KEY9")
4407	4417	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
4408	4418	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
4409	4419	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
r2864	r2865
4411	4421	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
4412	4422	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
4413	4423
4414		PORT_START // IN11 - DSW1
	4424	PORT_START_TAG("DSW1") /* IN11 - DSW1 */
4415	4425	PORT_DIPNAME( 0x07, 0x07, "Unknown 1-0&1&2" )
4416	4426	PORT_DIPSETTING( 0x07, "0" )
4417	4427	PORT_DIPSETTING( 0x06, "1" )
r2864	r2865
4436	4446	PORT_DIPSETTING( 0x00, "25" )
4437	4447	PORT_DIPSETTING( 0x80, "50" )
4438	4448
4439		PORT_START // IN12 - DSW2
	4449	PORT_START_TAG("DSW2") /* IN12 - DSW2 */
4440	4450	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
4441	4451	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
4442	4452	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r2864	r2865
4458	4468	PORT_DIPSETTING( 0x40, "70" )
4459	4469	PORT_DIPSETTING( 0x00, "80" )
4460	4470
4461		PORT_START // IN13 - DSW3
	4471	PORT_START_TAG("DSW3") /* IN13 - DSW3 */
4462	4472	PORT_DIPNAME( 0x01, 0x01, "Game Type?" )
4463	4473	PORT_DIPSETTING( 0x01, "0" )
4464	4474	PORT_DIPSETTING( 0x00, "1" )
r2864	r2865
4482	4492	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
4483	4493	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
4484	4494
4485		PORT_START // IN14 - DSW4
	4495	PORT_START_TAG("DSW4") /* IN14 - DSW4 */
4486	4496	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Demo_Sounds ) )
4487	4497	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
4488	4498	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
4508	4518	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
4509	4519	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4510	4520
4511		PORT_START // IN15 - DSWs top bits
	4521	PORT_START_TAG("DSW5") /* IN15 - DSWs top bits */
4512	4522	PORT_DIPNAME( 0x01, 0x01, "Unknown 1-8" )
4513	4523	PORT_DIPSETTING( 0x00, "5" )
4514	4524	PORT_DIPSETTING( 0x01, "10" )
r2864	r2865
4531	4541	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4532	4542	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
4533	4543
4534		PORT_START // IN16 - Fake DSW
	4544	PORT_START_TAG("BET") /* IN16 - Fake DSW */
4535	4545	PORT_DIPNAME( 0x40, 0x40, "Disable Bets" )
4536	4546	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
4537	4547	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4538	4548
4539		PORT_START // IN17 - Fake DSW
	4549	PORT_START_TAG("HOPPER") /* IN17 - Fake DSW */
4540	4550	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
4541	4551	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
4542	4552	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
4546	4556
4547	4557	static INPUT_PORTS_START( mjreach1 )
4548	4558
4549		PORT_START // IN0 - Coins + Service Keys
	4559	PORT_START_TAG("IN0") /* IN0 - Coins + Service Keys */
4550	4560	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE3 ) // medal out
4551	4561	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
4552	4562	PORT_SERVICE(0x04, IP_ACTIVE_LOW)
r2864	r2865
4556	4566	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
4557	4567	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
4558	4568
4559		// keyb 2
4560		PORT_START
	4569	/* keyb 2 */
	4570
	4571	PORT_START_TAG("KEY0")
4561	4572	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2) // A
4562	4573	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2) // E
4563	4574	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2) // I
r2864	r2865
4565	4576	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2) // Kan
4566	4577	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 ) // Start 2
4567	4578
4568		PORT_START
	4579	PORT_START_TAG("KEY1")
4569	4580	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2) // B
4570	4581	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2) // F
4571	4582	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2) // J
r2864	r2865
4573	4584	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2) // Reach
4574	4585	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2) // BET
4575	4586
4576		PORT_START
	4587	PORT_START_TAG("KEY2")
4577	4588	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2) // C
4578	4589	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2) // G
4579	4590	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2) // K
r2864	r2865
4581	4592	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2) // Ron
4582	4593	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4583	4594
4584		PORT_START
	4595	PORT_START_TAG("KEY3")
4585	4596	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2) // D
4586	4597	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2) // H
4587	4598	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2) // L
r2864	r2865
4589	4600	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4590	4601	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4591	4602
4592		PORT_START
	4603	PORT_START_TAG("KEY4")
4593	4604	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
4594	4605	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
4595	4606	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
r2864	r2865
4597	4608	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(2) // "b"
4598	4609	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // "s"
4599	4610
4600		// keyb 1
4601		PORT_START
	4611	/* keyb 1 */
	4612
	4613	PORT_START_TAG("KEY5")
4602	4614	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) // A
4603	4615	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) // E
4604	4616	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) // I
r2864	r2865
4606	4618	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) // Kan
4607	4619	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) // Start 1
4608	4620
4609		PORT_START
	4621	PORT_START_TAG("KEY6")
4610	4622	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) // B
4611	4623	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) // F
4612	4624	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) // J
r2864	r2865
4614	4626	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) // Reach
4615	4627	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) // BET
4616	4628
4617		PORT_START
	4629	PORT_START_TAG("KEY7")
4618	4630	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) // C
4619	4631	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) // G
4620	4632	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) // K
r2864	r2865
4622	4634	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) // Ron
4623	4635	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4624	4636
4625		PORT_START
	4637	PORT_START_TAG("KEY8")
4626	4638	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) // D
4627	4639	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) // H
4628	4640	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) // L
r2864	r2865
4630	4642	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4631	4643	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4632	4644
4633		PORT_START
	4645	PORT_START_TAG("KEY9")
4634	4646	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
4635	4647	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
4636	4648	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
r2864	r2865
4638	4650	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
4639	4651	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
4640	4652
4641		PORT_START // IN11 - DSW1
	4653	PORT_START_TAG("DSW1") /* IN11 - DSW1 */
4642	4654	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate (%)" )
4643	4655	PORT_DIPSETTING( 0x00, "50" )
4644	4656	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
4667	4679	PORT_DIPSETTING( 0x40, "10" )
4668	4680	PORT_DIPSETTING( 0x00, "20" )
4669	4681
4670		PORT_START // IN12 - DSW2
	4682	PORT_START_TAG("DSW2") /* IN12 - DSW2 */
4671	4683	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
4672	4684	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
4673	4685	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r2864	r2865
4690	4702	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
4691	4703	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4692	4704
4693		PORT_START // IN13 - DSW3
	4705	PORT_START_TAG("DSW3") /* IN13 - DSW3 */
4694	4706	PORT_DIPNAME( 0x07, 0x07, "YAKUMAN Bonus" )
4695	4707	PORT_DIPSETTING( 0x07, "Cut" )
4696	4708	PORT_DIPSETTING( 0x06, "1 T" )
r2864	r2865
4715	4727	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
4716	4728	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4717	4729
4718		PORT_START // IN14 - DSW4
	4730	PORT_START_TAG("DSW4") /* IN14 - DSW4 */
4719	4731	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
4720	4732	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
4721	4733	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
4741	4753	PORT_DIPSETTING( 0x80, "Start" )
4742	4754	PORT_DIPSETTING( 0x00, "Flip/Flop" )
4743	4755
4744		PORT_START // IN15 - DSWs top bits
	4756	PORT_START_TAG("DSW5") /* IN15 - DSWs top bits */
4745	4757	PORT_DIPNAME( 0x01, 0x01, "Credits Per Note" )
4746	4758	PORT_DIPSETTING( 0x01, "5" )
4747	4759	PORT_DIPSETTING( 0x00, "10" )
r2864	r2865
4766	4778	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
4767	4779	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4768	4780
4769		PORT_START // IN16 - Fake DSW
	4781	PORT_START_TAG("BET") /* IN16 - Fake DSW */
4770	4782	PORT_DIPNAME( 0x40, 0x40, "Bets?" )
4771	4783	PORT_DIPSETTING( 0x40, "0" )
4772	4784	PORT_DIPSETTING( 0x00, "1" )
4773	4785
4774		PORT_START // IN17 - Fake DSW
	4786	PORT_START_TAG("HOPPER") /* IN17 - Fake DSW */
4775	4787	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
4776	4788	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
4777	4789	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
4781	4793
4782	4794	static INPUT_PORTS_START( mjchuuka )
4783	4795
4784		PORT_START // IN0 - Coins + Service Keys
	4796	PORT_START_TAG("IN0") /* IN0 - Coins + Service Keys */
4785	4797	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE3 ) // medal out
4786	4798	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
4787	4799	PORT_SERVICE(0x04, IP_ACTIVE_LOW)
r2864	r2865
4791	4803	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
4792	4804	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
4793	4805
4794		// keyb 2
4795		PORT_START
	4806	/* keyb 2 */
	4807
	4808	PORT_START_TAG("KEY0")
4796	4809	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2) // A
4797	4810	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2) // E
4798	4811	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2) // I
r2864	r2865
4800	4813	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2) // Kan
4801	4814	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 ) // Start 2
4802	4815
4803		PORT_START
	4816	PORT_START_TAG("KEY1")
4804	4817	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2) // B
4805	4818	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2) // F
4806	4819	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2) // J
r2864	r2865
4808	4821	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2) // Reach
4809	4822	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2) // BET
4810	4823
4811		PORT_START
	4824	PORT_START_TAG("KEY2")
4812	4825	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2) // C
4813	4826	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2) // G
4814	4827	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2) // K
r2864	r2865
4816	4829	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2) // Ron
4817	4830	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4818	4831
4819		PORT_START
	4832	PORT_START_TAG("KEY3")
4820	4833	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2) // D
4821	4834	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2) // H
4822	4835	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2) // L
r2864	r2865
4824	4837	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4825	4838	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4826	4839
4827		PORT_START
	4840	PORT_START_TAG("KEY4")
4828	4841	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
4829	4842	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
4830	4843	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
r2864	r2865
4832	4845	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(2) // "b"
4833	4846	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // "s"
4834	4847
4835		// keyb 1
4836		PORT_START
	4848	/* keyb 1 */
	4849
	4850	PORT_START_TAG("KEY5")
4837	4851	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) // A
4838	4852	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) // E
4839	4853	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) // I
r2864	r2865
4841	4855	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) // Kan
4842	4856	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) // Start 1
4843	4857
4844		PORT_START
	4858	PORT_START_TAG("KEY6")
4845	4859	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) // B
4846	4860	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) // F
4847	4861	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) // J
r2864	r2865
4849	4863	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) // Reach
4850	4864	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) // BET
4851	4865
4852		PORT_START
	4866	PORT_START_TAG("KEY7")
4853	4867	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) // C
4854	4868	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) // G
4855	4869	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) // K
r2864	r2865
4857	4871	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) // Ron
4858	4872	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4859	4873
4860		PORT_START
	4874	PORT_START_TAG("KEY8")
4861	4875	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) // D
4862	4876	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) // H
4863	4877	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) // L
r2864	r2865
4865	4879	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4866	4880	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
4867	4881
4868		PORT_START
	4882	PORT_START_TAG("KEY9")
4869	4883	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
4870	4884	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
4871	4885	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
r2864	r2865
4873	4887	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
4874	4888	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
4875	4889
4876		PORT_START // IN11 - DSW1
	4890	PORT_START_TAG("DSW1") /* IN11 - DSW1 */
4877	4891	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate (%)" )
4878	4892	PORT_DIPSETTING( 0x00, "50" )
4879	4893	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
4902	4916	PORT_DIPSETTING( 0x40, "10" )
4903	4917	PORT_DIPSETTING( 0x00, "20" )
4904	4918
4905		PORT_START // IN12 - DSW2
	4919	PORT_START_TAG("DSW2") /* IN12 - DSW2 */
4906	4920	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
4907	4921	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
4908	4922	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r2864	r2865
4926	4940	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
4927	4941	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4928	4942
4929		PORT_START // IN13 - DSW3
	4943	PORT_START_TAG("DSW3") /* IN13 - DSW3 */
4930	4944	PORT_DIPNAME( 0x07, 0x07, "YAKUMAN Bonus" )
4931	4945	PORT_DIPSETTING( 0x07, "Cut" )
4932	4946	PORT_DIPSETTING( 0x06, "1 T" )
r2864	r2865
4951	4965	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
4952	4966	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4953	4967
4954		PORT_START // IN14 - DSW4
	4968	PORT_START_TAG("DSW4") /* IN14 - DSW4 */
4955	4969	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
4956	4970	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
4957	4971	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
4976	4990	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
4977	4991	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
4978	4992
4979		PORT_START // IN15 - DSWs top bits
	4993	PORT_START_TAG("DSW5") /* IN15 - DSWs top bits */
4980	4994	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
4981	4995	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
4982	4996	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
5001	5015	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
5002	5016	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5003	5017
5004		PORT_START // IN16 - Fake DSW
	5018	PORT_START_TAG("BET") /* IN16 - Fake DSW */
5005	5019	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
5006	5020	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
5007	5021	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5008	5022
5009		PORT_START // IN17 - Fake DSW
	5023	PORT_START_TAG("HOPPER") /* IN17 - Fake DSW */
5010	5024	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
5011	5025	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
5012	5026	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
5015	5029
5016	5030
5017	5031	static INPUT_PORTS_START( funkyfig )
5018		PORT_START // IN0 - Keys (port 83 with port 80 = 20)
	5032	PORT_START_TAG("IN0") /* IN0 - Keys (port 83 with port 80 = 20) */
5019	5033	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
5020	5034	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
5021	5035	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
r2864	r2865
5025	5039	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
5026	5040	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD)
5027	5041
5028		PORT_START // IN1 - ? (port 83 with port 80 = 21)
	5042	PORT_START_TAG("IN1") /* IN1 - ? (port 83 with port 80 = 21) */
5029	5043	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 ) // ?
5030	5044	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN )
5031	5045
5032		PORT_START // IN2 - Coins (port 82 with port 80 = 22)
	5046	PORT_START_TAG("IN2") /* IN2 - Coins (port 82 with port 80 = 22) */
5033	5047	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
5034	5048	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
5035	5049	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
5039	5053	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("9") PORT_CODE(KEYCODE_9_PAD)
5040	5054	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
5041	5055
5042		PORT_START // IN3 - DSW1 (low bits, port 1c with rombank = 1e)
	5056	PORT_START_TAG("DSW1") /* IN3 - DSW1 (low bits, port 1c with rombank = 1e) */
5043	5057	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
5044	5058	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
5045	5059	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
5064	5078	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
5065	5079	PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
5066	5080
5067		PORT_START // IN4 - DSW2 (low bits, port 1c with rombank = 1d)
	5081	PORT_START_TAG("DSW2") /* IN4 - DSW2 (low bits, port 1c with rombank = 1d) */
5068	5082	PORT_DIPNAME( 0x01, 0x01, "2 Player Game" )
5069	5083	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
5070	5084	PORT_DIPSETTING( 0x01, DEF_STR( Yes ) )
r2864	r2865
5088	5102	PORT_DIPSETTING( 0x40, "2" )
5089	5103	PORT_DIPSETTING( 0x00, "3" )
5090	5104
5091		PORT_START // IN5 - DSW1 & 2 (high bits, port 1c with rombank = 1b)
	5105	PORT_START_TAG("DSW3") /* IN5 - DSW1 & 2 (high bits, port 1c with rombank = 1b) */
5092	5106	PORT_DIPNAME( 0x01, 0x01, "Continue?" ) // related to continue
5093	5107	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
5094	5108	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
5116	5130
5117	5131
5118	5132	static INPUT_PORTS_START( mjmyster )
5119		PORT_START // IN0 - Coins + Service Keys
	5133	PORT_START_TAG("IN0") /* IN0 - Coins + Service Keys */
5120	5134	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE3 ) // medal out
5121	5135	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
5122	5136	PORT_SERVICE_NO_TOGGLE(0x04, IP_ACTIVE_LOW)
r2864	r2865
5126	5140	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
5127	5141	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
5128	5142
5129		// keyb 1
5130		PORT_START
	5143	/* keyb 1 */
	5144
	5145	PORT_START_TAG("KEY0")
5131	5146	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) // A
5132	5147	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) // E
5133	5148	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) // I
r2864	r2865
5135	5150	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) // Kan
5136	5151	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) // Start 1
5137	5152
5138		PORT_START
	5153	PORT_START_TAG("KEY1")
5139	5154	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) // B
5140	5155	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) // F
5141	5156	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) // J
r2864	r2865
5143	5158	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) // Reach
5144	5159	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) // BET
5145	5160
5146		PORT_START
	5161	PORT_START_TAG("KEY2")
5147	5162	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) // C
5148	5163	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) // G
5149	5164	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) // K
r2864	r2865
5151	5166	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) // Ron
5152	5167	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
5153	5168
5154		PORT_START
	5169	PORT_START_TAG("KEY3")
5155	5170	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) // D
5156	5171	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) // H
5157	5172	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) // L
r2864	r2865
5159	5174	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
5160	5175	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
5161	5176
5162		PORT_START
	5177	PORT_START_TAG("KEY4")
5163	5178	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
5164	5179	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
5165	5180	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
r2864	r2865
5167	5182	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
5168	5183	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
5169	5184
5170		PORT_START // IN6 - DSW1
	5185	PORT_START_TAG("DSW1") /* IN6 - DSW1 */
5171	5186	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate (%)" )
5172	5187	PORT_DIPSETTING( 0x00, "50" )
5173	5188	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
5196	5211	PORT_DIPSETTING( 0x40, "10" )
5197	5212	PORT_DIPSETTING( 0x00, "20" )
5198	5213
5199		PORT_START // IN7 - DSW2
	5214	PORT_START_TAG("DSW2") /* IN7 - DSW2 */
5200	5215	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
5201	5216	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
5202	5217	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r2864	r2865
5220	5235	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
5221	5236	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5222	5237
5223		PORT_START // IN8 - DSW3
	5238	PORT_START_TAG("DSW3") /* IN8 - DSW3 */
5224	5239	PORT_DIPNAME( 0x03, 0x03, "YAKUMAN Times" )
5225	5240	// PORT_DIPSETTING( 0x00, "1" )
5226	5241	PORT_DIPSETTING( 0x03, "1" )
r2864	r2865
5244	5259	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
5245	5260	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5246	5261
5247		PORT_START // IN9 - DSW4
	5262	PORT_START_TAG("DSW4") /* IN9 - DSW4 */
5248	5263	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
5249	5264	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
5250	5265	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
5270	5285	PORT_DIPSETTING( 0x80, DEF_STR( Japan ) )
5271	5286	PORT_DIPSETTING( 0x00, "Hong Kong" )
5272	5287
5273		PORT_START // IN10 - DSWs top bits
	5288	PORT_START_TAG("DSW5") /* IN10 - DSWs top bits */
5274	5289	PORT_DIPNAME( 0x03, 0x03, "Computer Strength?" )
5275	5290	PORT_DIPSETTING( 0x03, "Weak" )
5276	5291	PORT_DIPSETTING( 0x02, DEF_STR( Normal ))
r2864	r2865
5298	5313
5299	5314	static INPUT_PORTS_START( hginga )
5300	5315
5301		PORT_START // IN0 - Coins + Service Keys
	5316	PORT_START_TAG("IN0") /* IN0 - Coins + Service Keys */
5302	5317	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE3 ) // medal out
5303	5318	// PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
5304	5319	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // Test
r2864	r2865
5308	5323	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
5309	5324	// PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
5310	5325
5311		// keyb 2
5312		PORT_START
	5326	/* keyb 2 */
	5327
	5328	PORT_START_TAG("KEY0")
5313	5329	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2) // A
5314	5330	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2) // E
5315	5331	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
5317	5333	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Kan
5318	5334	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
5319	5335
5320		PORT_START
	5336	PORT_START_TAG("KEY1")
5321	5337	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2) // B
5322	5338	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2) // F
5323	5339	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
5325	5341	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Reach
5326	5342	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2) // BET
5327	5343
5328		PORT_START
	5344	PORT_START_TAG("KEY2")
5329	5345	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2) // C
5330	5346	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // G
5331	5347	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
5333	5349	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
5334	5350	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
5335	5351
5336		PORT_START
	5352	PORT_START_TAG("KEY3")
5337	5353	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2) // D
5338	5354	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // H
5339	5355	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
5341	5357	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
5342	5358	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
5343	5359
5344		PORT_START
	5360	PORT_START_TAG("KEY4")
5345	5361	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
5346	5362	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
5347	5363	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
r2864	r2865
5349	5365	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(2) // "b"
5350	5366	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // "s"
5351	5367
5352		// keyb 1
5353		PORT_START
	5368	/* keyb 1 */
	5369
	5370	PORT_START_TAG("KEY5")
5354	5371	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) // A
5355	5372	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) // E
5356	5373	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
5358	5375	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Kan
5359	5376	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
5360	5377
5361		PORT_START
	5378	PORT_START_TAG("KEY6")
5362	5379	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) // B
5363	5380	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) // F
5364	5381	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
5366	5383	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Reach
5367	5384	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) // BET
5368	5385
5369		PORT_START
	5386	PORT_START_TAG("KEY7")
5370	5387	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) // C
5371	5388	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // G
5372	5389	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
5374	5391	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
5375	5392	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
5376	5393
5377		PORT_START
	5394	PORT_START_TAG("KEY8")
5378	5395	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) // D
5379	5396	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // H
5380	5397	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
5382	5399	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
5383	5400	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
5384	5401
5385		PORT_START
	5402	PORT_START_TAG("KEY9")
5386	5403	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
5387	5404	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
5388	5405	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
r2864	r2865
5390	5407	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
5391	5408	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
5392	5409
5393		PORT_START // IN11 - DSW4
	5410	PORT_START_TAG("DSW4") /* IN11 - DSW4 */
5394	5411	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Demo_Sounds ) )
5395	5412	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
5396	5413	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
5417	5434	PORT_DIPSETTING( 0x80, "Numbers" )
5418	5435	PORT_DIPSETTING( 0x00, "Letters" )
5419	5436
5420		PORT_START // IN12 - DSW3
	5437	PORT_START_TAG("DSW3") /* IN12 - DSW3 */
5421	5438	PORT_DIPNAME( 0x03, 0x03, "Unknown 3-0&1" )
5422	5439	PORT_DIPSETTING( 0x03, "1" )
5423	5440	PORT_DIPSETTING( 0x02, "2" )
r2864	r2865
5440	5457	PORT_DIPSETTING( 0x40, "2" )
5441	5458	PORT_DIPSETTING( 0x00, "3" )
5442	5459
5443		PORT_START // IN13 - DSW2
	5460	PORT_START_TAG("DSW2") /* IN13 - DSW2 */
5444	5461	PORT_DIPNAME( 0x03, 0x03, "Unknown 2-0&1" )
5445	5462	PORT_DIPSETTING( 0x03, "1" )
5446	5463	PORT_DIPSETTING( 0x02, "2" )
r2864	r2865
5463	5480	PORT_DIPSETTING( 0x40, "70" )
5464	5481	PORT_DIPSETTING( 0x00, "80" )
5465	5482
5466		PORT_START // IN14 - DSW1
	5483	PORT_START_TAG("DSW1") /* IN14 - DSW1 */
5467	5484	PORT_DIPNAME( 0x07, 0x07, "Unknown 1-0&1&2" )
5468	5485	PORT_DIPSETTING( 0x07, "0" )
5469	5486	PORT_DIPSETTING( 0x06, "1" )
r2864	r2865
5488	5505	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
5489	5506	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5490	5507
5491		PORT_START // IN15 - DSWs top bits
	5508	PORT_START_TAG("DSW5") /* IN15 - DSWs top bits */
5492	5509	PORT_DIPNAME( 0x01, 0x01, "Keyboard" )
5493	5510	PORT_DIPSETTING( 0x00, "Hanafuda" ) // Requires different inputs
5494	5511	PORT_DIPSETTING( 0x01, "Mahjong" )
r2864	r2865
5512	5529	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
5513	5530	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5514	5531
5515		PORT_START // IN16 - Fake DSW
	5532	PORT_START_TAG("BET") /* IN16 - Fake DSW */
5516	5533	PORT_DIPNAME( 0x40, 0x40, "Allow Bets" )
5517	5534	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
5518	5535	PORT_DIPSETTING( 0x40, DEF_STR( On ) )
r2864	r2865
5520	5537	INPUT_PORTS_END
5521	5538
5522	5539	static INPUT_PORTS_START( hgokou )
5523		PORT_START // IN0
	5540	PORT_START_TAG("IN0") /* IN0 */
5524	5541	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE3 ) // medal out
5525	5542	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
5526	5543	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) PORT_TOGGLE
r2864	r2865
5530	5547	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
5531	5548	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
5532	5549
5533		// keyb 1
5534		PORT_START // IN1
	5550	/* keyb 1 */
	5551
	5552	PORT_START_TAG("KEY0") /* IN1 */
5535	5553	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD) // A
5536	5554	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD) // E
5537	5555	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
5539	5557	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // Kan
5540	5558	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
5541	5559
5542		PORT_START // IN2
	5560	PORT_START_TAG("KEY1") /* IN2 */
5543	5561	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD) // B
5544	5562	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD) // F
5545	5563	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
5547	5565	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // Reach
5548	5566	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // BET
5549	5567
5550		PORT_START // IN3
	5568	PORT_START_TAG("KEY2") /* IN3 */
5551	5569	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD) // C
5552	5570	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // G
5553	5571	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
5555	5573	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
5556	5574	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
5557	5575
5558		PORT_START // IN4
	5576	PORT_START_TAG("KEY3") /* IN4 */
5559	5577	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD) // D
5560	5578	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // H
5561	5579	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
5563	5581	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
5564	5582	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
5565	5583
5566		PORT_START // IN5
	5584	PORT_START_TAG("KEY4") /* IN5 */
5567	5585	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
5568	5586	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "t"
5569	5587	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "w"
r2864	r2865
5571	5589	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "b"
5572	5590	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "s"
5573	5591
5574		// keyb 2
5575		PORT_START // IN6
	5592	/* keyb 2 */
	5593
	5594	PORT_START_TAG("KEY5") /* IN6 */
5576	5595	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2) // A
5577	5596	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2) // E
5578	5597	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
5580	5599	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // Kan
5581	5600	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
5582	5601
5583		PORT_START // IN7
	5602	PORT_START_TAG("KEY6") /* IN7 */
5584	5603	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2) // B
5585	5604	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2) // F
5586	5605	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
5588	5607	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // Reach
5589	5608	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // BET
5590	5609
5591		PORT_START // IN8
	5610	PORT_START_TAG("KEY7") /* IN8 */
5592	5611	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2) // C
5593	5612	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_PLAYER(2) // G
5594	5613	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
5596	5615	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
5597	5616	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
5598	5617
5599		PORT_START // IN9
	5618	PORT_START_TAG("KEY8") /* IN9 */
5600	5619	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2) // D
5601	5620	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_PLAYER(2) // H
5602	5621	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
5604	5623	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
5605	5624	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
5606	5625
5607		PORT_START // IN10
	5626	PORT_START_TAG("KEY9") /* IN10 */
5608	5627	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
5609	5628	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "t"
5610	5629	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "w"
r2864	r2865
5612	5631	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "b"
5613	5632	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "s"
5614	5633
5615		PORT_START // IN11 - DSW4
	5634	PORT_START_TAG("DSW4") /* IN11 - DSW4 */
5616	5635	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Demo_Sounds ) )
5617	5636	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
5618	5637	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
5639	5658	PORT_DIPSETTING( 0x80, "Numbers" )
5640	5659	PORT_DIPSETTING( 0x00, "Letters" )
5641	5660
5642		PORT_START // IN12 - DSW3
	5661	PORT_START_TAG("DSW3") /* IN12 - DSW3 */
5643	5662	PORT_DIPNAME( 0x03, 0x03, "Unknown 3-0&1" )
5644	5663	PORT_DIPSETTING( 0x03, "1" )
5645	5664	PORT_DIPSETTING( 0x02, "2" )
r2864	r2865
5662	5681	PORT_DIPSETTING( 0x40, "2" )
5663	5682	PORT_DIPSETTING( 0x00, "3" )
5664	5683
5665		PORT_START // IN13 - DSW2
	5684	PORT_START_TAG("DSW2") /* IN13 - DSW2 */
5666	5685	PORT_DIPNAME( 0x03, 0x03, "Unknown 2-0&1" )
5667	5686	PORT_DIPSETTING( 0x03, "1" )
5668	5687	PORT_DIPSETTING( 0x02, "2" )
r2864	r2865
5685	5704	PORT_DIPSETTING( 0x40, "70" )
5686	5705	PORT_DIPSETTING( 0x00, "80" )
5687	5706
5688		PORT_START // IN14 - DSW1
	5707	PORT_START_TAG("DSW1") /* IN14 - DSW1 */
5689	5708	PORT_DIPNAME( 0x07, 0x07, "Unknown 1-0&1&2" )
5690	5709	PORT_DIPSETTING( 0x07, "0" )
5691	5710	PORT_DIPSETTING( 0x06, "1" )
r2864	r2865
5710	5729	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
5711	5730	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5712	5731
5713		PORT_START // IN15 - DSWs top bits
	5732	PORT_START_TAG("DSW5") /* IN15 - DSWs top bits */
5714	5733	PORT_DIPNAME( 0x01, 0x00, "Control Panel" )
5715	5734	PORT_DIPSETTING( 0x00, "Hanafuda" )
5716	5735	PORT_DIPSETTING( 0x01, "Mahjong" ) // Requires different inputs
r2864	r2865
5736	5755	INPUT_PORTS_END
5737	5756
5738	5757	static INPUT_PORTS_START( mjmyornt )
5739		PORT_START // IN0 - Coins + Service Keys
	5758	PORT_START_TAG("IN0") /* IN0 - Coins + Service Keys */
5740	5759	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE3 ) // medal out
5741	5760	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
5742	5761	PORT_SERVICE_NO_TOGGLE(0x04, IP_ACTIVE_LOW)
r2864	r2865
5746	5765	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
5747	5766	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
5748	5767
5749		// keyb 1
5750		PORT_START
	5768	/* keyb 1 */
	5769
	5770	PORT_START_TAG("KEY0")
5751	5771	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) // A
5752	5772	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) // E
5753	5773	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) // I
r2864	r2865
5755	5775	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) // Kan
5756	5776	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) // Start 1
5757	5777
5758		PORT_START
	5778	PORT_START_TAG("KEY1")
5759	5779	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) // B
5760	5780	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) // F
5761	5781	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) // J
r2864	r2865
5763	5783	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) // Reach
5764	5784	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) // BET
5765	5785
5766		PORT_START
	5786	PORT_START_TAG("KEY2")
5767	5787	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) // C
5768	5788	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) // G
5769	5789	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) // K
r2864	r2865
5771	5791	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) // Ron
5772	5792	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
5773	5793
5774		PORT_START
	5794	PORT_START_TAG("KEY3")
5775	5795	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) // D
5776	5796	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) // H
5777	5797	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) // L
r2864	r2865
5779	5799	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
5780	5800	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
5781	5801
5782		PORT_START
	5802	PORT_START_TAG("KEY4")
5783	5803	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
5784	5804	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
5785	5805	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
r2864	r2865
5787	5807	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
5788	5808	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
5789	5809
5790		PORT_START // IN6 - DSW1
	5810	PORT_START_TAG("DSW1") /* IN6 - DSW1 */
5791	5811	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate (%)" )
5792	5812	PORT_DIPSETTING( 0x00, "50" )
5793	5813	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
5816	5836	PORT_DIPSETTING( 0x40, "10" )
5817	5837	PORT_DIPSETTING( 0x00, "20" )
5818	5838
5819		PORT_START // IN7 - DSW2
	5839	PORT_START_TAG("DSW2") /* IN7 - DSW2 */
5820	5840	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
5821	5841	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
5822	5842	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r2864	r2865
5840	5860	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
5841	5861	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5842	5862
5843		PORT_START // IN8 - DSW3
	5863	PORT_START_TAG("DSW3") /* IN8 - DSW3 */
5844	5864	PORT_DIPNAME( 0x03, 0x03, "YAKUMAN Times" )
5845	5865	// PORT_DIPSETTING( 0x00, "1" )
5846	5866	PORT_DIPSETTING( 0x03, "1" )
r2864	r2865
5864	5884	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
5865	5885	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5866	5886
5867		PORT_START // IN9 - DSW4
	5887	PORT_START_TAG("DSW4") /* IN9 - DSW4 */
5868	5888	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
5869	5889	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
5870	5890	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
5890	5910	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
5891	5911	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5892	5912
5893		PORT_START // IN10 - DSWs top bits
	5913	PORT_START_TAG("DSW5") /* IN10 - DSWs top bits */
5894	5914	PORT_DIPNAME( 0x03, 0x03, "Computer Strength?" )
5895	5915	PORT_DIPSETTING( 0x03, "Weak" )
5896	5916	PORT_DIPSETTING( 0x02, DEF_STR( Normal ))
r2864	r2865
5918	5938
5919	5939	#ifdef UNUSED_DEFINITION
5920	5940	static INPUT_PORTS_START( mjmyuniv )
5921		PORT_START // IN0 - Coins + Service Keys
	5941	PORT_START_TAG("IN0") /* IN0 - Coins + Service Keys */
5922	5942	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE3 ) // medal out
5923	5943	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
5924	5944	PORT_SERVICE_NO_TOGGLE(0x04, IP_ACTIVE_LOW)
r2864	r2865
5928	5948	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
5929	5949	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
5930	5950
5931		// keyb 1
5932		PORT_START
	5951	/* keyb 1 */
	5952
	5953	PORT_START_TAG("KEY0")
5933	5954	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) // A
5934	5955	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) // E
5935	5956	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) // I
r2864	r2865
5937	5958	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) // Kan
5938	5959	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) // Start 1
5939	5960
5940		PORT_START
	5961	PORT_START_TAG("KEY1")
5941	5962	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) // B
5942	5963	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) // F
5943	5964	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) // J
r2864	r2865
5945	5966	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) // Reach
5946	5967	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) // BET
5947	5968
5948		PORT_START
	5969	PORT_START_TAG("KEY2")
5949	5970	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) // C
5950	5971	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) // G
5951	5972	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) // K
r2864	r2865
5953	5974	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) // Ron
5954	5975	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
5955	5976
5956		PORT_START
	5977	PORT_START_TAG("KEY3")
5957	5978	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) // D
5958	5979	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) // H
5959	5980	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) // L
r2864	r2865
5961	5982	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
5962	5983	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
5963	5984
5964		PORT_START
	5985	PORT_START_TAG("KEY4")
5965	5986	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
5966	5987	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
5967	5988	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
r2864	r2865
5969	5990	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
5970	5991	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
5971	5992
5972		PORT_START // IN6 - DSW1
	5993	PORT_START_TAG("DSW1") /* IN6 - DSW1 */
5973	5994	PORT_DIPNAME( 0x0f, 0x07, "Pay Out Rate (%)" )
5974	5995	PORT_DIPSETTING( 0x00, "50" )
5975	5996	PORT_DIPSETTING( 0x01, "53" )
r2864	r2865
5998	6019	PORT_DIPSETTING( 0x40, "10" )
5999	6020	PORT_DIPSETTING( 0x00, "20" )
6000	6021
6001		PORT_START // IN7 - DSW2
	6022	PORT_START_TAG("DSW2") /* IN7 - DSW2 */
6002	6023	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
6003	6024	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
6004	6025	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r2864	r2865
6022	6043	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
6023	6044	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
6024	6045
6025		PORT_START // IN8 - DSW3
	6046	PORT_START_TAG("DSW3") /* IN8 - DSW3 */
6026	6047	PORT_DIPNAME( 0x03, 0x03, "YAKUMAN Times" )
6027	6048	// PORT_DIPSETTING( 0x00, "1" )
6028	6049	PORT_DIPSETTING( 0x03, "1" )
r2864	r2865
6046	6067	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
6047	6068	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
6048	6069
6049		PORT_START // IN9 - DSW4
	6070	PORT_START_TAG("DSW4") /* IN9 - DSW4 */
6050	6071	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
6051	6072	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
6052	6073	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
6072	6093	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
6073	6094	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
6074	6095
6075		PORT_START // IN10 - DSWs top bits
	6096	PORT_START_TAG("DSW5") /* IN10 - DSWs top bits */
6076	6097	PORT_DIPNAME( 0x03, 0x03, "Computer Strength?" )
6077	6098	PORT_DIPSETTING( 0x03, "Weak" )
6078	6099	PORT_DIPSETTING( 0x02, DEF_STR( Normal ))
r2864	r2865
6100	6121	#endif
6101	6122
6102	6123	static INPUT_PORTS_START( akamaru )
6103		PORT_START // IN0 - Player 1
	6124	PORT_START_TAG("IN0") /* IN0 - Player 1 */
6104	6125	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
6105	6126	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
6106	6127	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
r2864	r2865
6110	6131	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
6111	6132	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
6112	6133
6113		PORT_START // IN1 - Player 2
	6134	PORT_START_TAG("IN1") /* IN1 - Player 2 */
6114	6135	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
6115	6136	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
6116	6137	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
r2864	r2865
6120	6141	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
6121	6142	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
6122	6143
6123		PORT_START // IN2 - Coins + ?
	6144	PORT_START_TAG("IN2") /* IN2 - Coins + ? */
6124	6145	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
6125	6146	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
6126	6147	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
6130	6151	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter irq flag
6131	6152	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter busy flag
6132	6153
6133		PORT_START // IN3 - DSW1
	6154	PORT_START_TAG("DSW1") /* IN3 - DSW1 */
6134	6155	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
6135	6156	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
6136	6157	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
6152	6173	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
6153	6174	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
6154	6175
6155		PORT_START // IN4 - DSW2
	6176	PORT_START_TAG("DSW2") /* IN4 - DSW2 */
6156	6177	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
6157	6178	PORT_DIPSETTING( 0x02, DEF_STR( Easy ) )
6158	6179	PORT_DIPSETTING( 0x03, DEF_STR( Normal ) )
r2864	r2865
6179	6200	INPUT_PORTS_END
6180	6201
6181	6202	static INPUT_PORTS_START( mjflove )
6182		PORT_START // IN0 - Coins + Service Keys
	6203	PORT_START_TAG("IN0") /* IN0 - Coins + Service Keys */
6183	6204	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
6184	6205	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
6185	6206	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
6189	6210	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter irq flag
6190	6211	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter busy flag
6191	6212
6192		// keyb 1
6193		PORT_START
	6213	/* keyb 1 */
	6214
	6215	PORT_START_TAG("KEY0")
6194	6216	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) // A
6195	6217	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) // E
6196	6218	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) // I
r2864	r2865
6198	6220	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) // Kan
6199	6221	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 ) // Start 1
6200	6222
6201		PORT_START
	6223	PORT_START_TAG("KEY1")
6202	6224	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) // B
6203	6225	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) // F
6204	6226	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) // J
r2864	r2865
6206	6228	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) // Reach
6207	6229	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) // BET
6208	6230
6209		PORT_START
	6231	PORT_START_TAG("KEY2")
6210	6232	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) // C
6211	6233	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) // G
6212	6234	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) // K
r2864	r2865
6214	6236	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) // Ron
6215	6237	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
6216	6238
6217		PORT_START
	6239	PORT_START_TAG("KEY3")
6218	6240	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) // D
6219	6241	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) // H
6220	6242	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) // L
r2864	r2865
6222	6244	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
6223	6245	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
6224	6246
6225		PORT_START
	6247	PORT_START_TAG("KEY4")
6226	6248	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
6227	6249	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
6228	6250	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
r2864	r2865
6230	6252	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
6231	6253	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
6232	6254
6233		// keyb 2
6234		PORT_START
	6255	/* keyb 2 */
	6256
	6257	PORT_START_TAG("KEY5")
6235	6258	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2) // A
6236	6259	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2) // E
6237	6260	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2) // I
r2864	r2865
6239	6262	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2) // Kan
6240	6263	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 ) // Start 2
6241	6264
6242		PORT_START
	6265	PORT_START_TAG("KEY6")
6243	6266	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2) // B
6244	6267	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2) // F
6245	6268	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2) // J
r2864	r2865
6247	6270	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2) // Reach
6248	6271	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2) // BET
6249	6272
6250		PORT_START
	6273	PORT_START_TAG("KEY7")
6251	6274	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2) // C
6252	6275	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2) // G
6253	6276	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2) // K
r2864	r2865
6255	6278	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2) // Ron
6256	6279	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
6257	6280
6258		PORT_START
	6281	PORT_START_TAG("KEY8")
6259	6282	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2) // D
6260	6283	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2) // H
6261	6284	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2) // L
r2864	r2865
6263	6286	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
6264	6287	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // nothing
6265	6288
6266		PORT_START
	6289	PORT_START_TAG("KEY9")
6267	6290	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
6268	6291	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
6269	6292	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
r2864	r2865
6271	6294	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(2) // "b"
6272	6295	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // "s"
6273	6296
6274		PORT_START // IN11 - DSW1
	6297	PORT_START_TAG("DSW1") /* IN11 - DSW1 */
6275	6298	PORT_DIPNAME( 0x01, 0x01, "Unknown 2-0" )
6276	6299	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
6277	6300	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
6297	6320	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
6298	6321	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
6299	6322
6300		PORT_START // IN12 - DSW2
	6323	PORT_START_TAG("DSW2") /* IN12 - DSW2 */
6301	6324	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
6302	6325	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
6303	6326	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
6322	6345	INPUT_PORTS_END
6323	6346
6324	6347	static INPUT_PORTS_START( hparadis )
6325		PORT_START // IN0 - Player 1
	6348	PORT_START_TAG("IN0") /* IN0 - Player 1 */
6326	6349	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
6327	6350	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
6328	6351	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
r2864	r2865
6332	6355	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
6333	6356	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
6334	6357
6335		PORT_START // IN1 - Player 2
	6358	PORT_START_TAG("IN1") /* IN1 - Player 2 */
6336	6359	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
6337	6360
6338		PORT_START // IN2
	6361	PORT_START_TAG("IN2") /* IN2 */
6339	6362	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
6340	6363	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
6341	6364	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
6345	6368	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
6346	6369	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
6347	6370
6348		// keyb 1
6349		PORT_START // IN3
	6371	/* keyb 1 */
	6372
	6373	PORT_START_TAG("KEY0") /* IN3 */
6350	6374	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD) // A
6351	6375	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD) // E
6352	6376	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
6354	6378	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Kan
6355	6379	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
6356	6380
6357		PORT_START // IN4
	6381	PORT_START_TAG("KEY1") /* IN4 */
6358	6382	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD) // B
6359	6383	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD) // F
6360	6384	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
6362	6386	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Reach
6363	6387	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // BET
6364	6388
6365		PORT_START // IN5
	6389	PORT_START_TAG("KEY2") /* IN5 */
6366	6390	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD) // C
6367	6391	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD) // G
6368	6392	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
6370	6394	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
6371	6395	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
6372	6396
6373		PORT_START // IN6
	6397	PORT_START_TAG("KEY3") /* IN6 */
6374	6398	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD) // D
6375	6399	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("8") PORT_CODE(KEYCODE_8_PAD) // H
6376	6400	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
6378	6402	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
6379	6403	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
6380	6404
6381		PORT_START // IN7
	6405	PORT_START_TAG("KEY4") /* IN7 */
6382	6406	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
6383	6407	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "t"
6384	6408	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "w"
r2864	r2865
6386	6410	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "b"
6387	6411	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "s"
6388	6412
6389		// keyb 2
6390		PORT_START // IN8
	6413	/* keyb 2 */
	6414
	6415	PORT_START_TAG("KEY5") /* IN8 */
6391	6416	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2) // A
6392	6417	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2) // E
6393	6418	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // I
r2864	r2865
6395	6420	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Kan
6396	6421	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
6397	6422
6398		PORT_START // IN9
	6423	PORT_START_TAG("KEY6") /* IN9 */
6399	6424	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2) // B
6400	6425	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2) // F
6401	6426	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // J
r2864	r2865
6403	6428	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Reach
6404	6429	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // BET
6405	6430
6406		PORT_START // IN10
	6431	PORT_START_TAG("KEY7") /* IN10 */
6407	6432	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2) // C
6408	6433	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2) // G
6409	6434	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // K
r2864	r2865
6411	6436	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // Ron
6412	6437	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
6413	6438
6414		PORT_START // IN11
	6439	PORT_START_TAG("KEY8") /* IN11 */
6415	6440	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2) // D
6416	6441	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2) // H
6417	6442	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // L
r2864	r2865
6419	6444	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
6420	6445	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
6421	6446
6422		PORT_START // IN12
	6447	PORT_START_TAG("KEY9") /* IN12 */
6423	6448	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
6424	6449	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "t"
6425	6450	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "w"
r2864	r2865
6427	6452	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "b"
6428	6453	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "s"
6429	6454
6430		PORT_START // IN13 - DSW1
	6455	PORT_START_TAG("DSW1") /* IN13 - DSW1 */
6431	6456	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
6432	6457	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
6433	6458	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r2864	r2865
6450	6475	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
6451	6476	PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
6452	6477
6453		PORT_START // IN14 - DSW2
	6478	PORT_START_TAG("DSW2") /* IN14 - DSW2 */
6454	6479	PORT_DIPNAME( 0x03, 0x03, "Unknown 2-0&1" )
6455	6480	PORT_DIPSETTING( 0x03, "0" )
6456	6481	PORT_DIPSETTING( 0x02, "1" )
r2864	r2865
6475	6500	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
6476	6501	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
6477	6502
6478		PORT_START // IN15 - DSWs top bits
	6503	PORT_START_TAG("DSW3") /* IN15 - DSWs top bits */
6479	6504	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
6480	6505	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
6481	6506	PORT_DIPSETTING( 0x00, DEF_STR( On ) )

src/mame/drivers/kaneko16.c
r2864	r2865
598	598
599	599	static READ16_HANDLER( gtmr_wheel_r )
600	600	{
601		if ( (input_port_read_indexed(machine, 4) & 0x1800) == 0x10) // DSW setting
602		return input_port_read_indexed(machine, 5)<<8; // 360' Wheel
	601	if ( (input_port_read(machine, "DSW1") & 0x1800) == 0x10) // DSW setting
	602	return input_port_read(machine, "WHEEL0")<<8; // 360' Wheel
603	603	else
604		return input_port_read~~_indexed~~(machine, 5); // 270' Wheel
	604	return input_port_read(machine, "WHEEL0"); // 270' Wheel
605	605	}
606	606
607	607	static WRITE16_HANDLER( gtmr_oki_0_bank_w )
r2864	r2865
703	703
704	704	static READ16_HANDLER( gtmr2_wheel_r )
705	705	{
706		switch (input_port_read~~_indexed~~(machine, 4) & 0x1800)
	706	switch (input_port_read(machine, "DSW1") & 0x1800)
707	707	{
708	708	case 0x0000: // 270' A. Wheel
709		return (input_port_read~~_indexed~~(machine, 5));
	709	return (input_port_read(machine, "WHEEL0"));
710	710	break;
711	711	case 0x1000: // 270' D. Wheel
712		return (input_port_read~~_indexed~~(machine, 6) << 8);
	712	return (input_port_read(machine, "WHEEL1") << 8);
713	713	break;
714	714	case 0x0800: // 360' Wheel
715		return (input_port_read~~_indexed~~(machine, 7) << 8);
	715	return (input_port_read(machine, "WHEEL2") << 8);
716	716	break;
717	717	default:
718	718	logerror("gtmr2_wheel_r : read at %06x with joystick\n", activecpu_get_pc());
r2864	r2865
723	723
724	724	static READ16_HANDLER( gtmr2_IN1_r )
725	725	{
726		return (input_port_read~~_indexed~~(machine, 1) & (input_port_read~~_indexed~~(machine, 8) \| ~0x7100));
	726	return (input_port_read(machine, "IN1") & (input_port_read(machine, "FAKE") \| ~0x7100));
727	727	}
728	728
729	729	static ADDRESS_MAP_START( gtmr2_readmem, ADDRESS_SPACE_PROGRAM, 16 )
r2864	r2865
874	874	***************************************************************************/
875	875
876	876	static INPUT_PORTS_START( bakubrkr )
877		PORT_START // IN0 - Player 1 + DSW - e00000.w
	877	PORT_START_TAG("IN0") // IN0 - Player 1 + DSW - e00000.w
878	878	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:1")
879	879	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
880	880	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
896	896	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
897	897	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
898	898
899		PORT_START // IN1 - Player 2 - e00002.b
	899	PORT_START_TAG("IN1") // IN1 - Player 2 - e00002.b
900	900	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
901	901	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
902	902	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
906	906	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
907	907	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
908	908
909		PORT_START // IN2 - Coins - e00004.b
	909	PORT_START_TAG("IN2") // IN2 - Coins - e00004.b
910	910	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
911	911	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
912	912	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
r2864	r2865
916	916	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SERVICE1 )
917	917	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
918	918
919		PORT_START // IN3 - Seems unused ! - e00006.b
	919	PORT_START_TAG("IN3") // IN3 - Seems unused ! - e00006.b
920	920	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
921	921	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
922	922	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
933	933	***************************************************************************/
934	934
935	935	static INPUT_PORTS_START( berlwall )
936		PORT_START // IN0 - Player 1 - 680000.w
	936	PORT_START_TAG("IN0") // IN0 - Player 1 - 680000.w
937	937	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
938	938	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
939	939	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
943	943	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
944	944	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
945	945
946		PORT_START // IN1 - Player 2 - 680002.w
	946	PORT_START_TAG("IN1") // IN1 - Player 2 - 680002.w
947	947	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
948	948	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
949	949	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
953	953	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
954	954	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
955	955
956		PORT_START // IN2 - Coins - 680004.w
	956	PORT_START_TAG("IN2") // IN2 - Coins - 680004.w
957	957	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
958	958	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
959	959	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
r2864	r2865
963	963	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SERVICE1 )
964	964	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
965	965
966		PORT_START // IN3 - ? - 680006.w
	966	PORT_START_TAG("IN3") // IN3 - ? - 680006.w
967	967	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
968	968	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
969	969	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1043	1043	***************************************************************************/
1044	1044
1045	1045	static INPUT_PORTS_START( blazeon )
1046		PORT_START // IN0 - Player 1 + DSW - c00000.w
	1046	PORT_START_TAG("IN0") // IN0 - Player 1 + DSW - c00000.w
1047	1047	PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
1048	1048	PORT_DIPSETTING( 0x0002, DEF_STR( Easy ) )
1049	1049	PORT_DIPSETTING( 0x0003, DEF_STR( Normal ) )
r2864	r2865
1070	1070	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_START1 )
1071	1071	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
1072	1072
1073		PORT_START // IN1 - Player 2 - c00002.w
	1073	PORT_START_TAG("IN1") // IN1 - Player 2 - c00002.w
1074	1074	PORT_DIPNAME( 0x000f, 0x000f, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:1,2,3,4")
1075	1075	PORT_DIPSETTING( 0x0007, DEF_STR( 4C_1C ) )
1076	1076	PORT_DIPSETTING( 0x0008, DEF_STR( 3C_1C ) )
r2864	r2865
1116	1116	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_START2 )
1117	1117	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
1118	1118
1119		PORT_START // IN2 - ? - c00004.w
	1119	PORT_START_TAG("IN2") // IN2 - ? - c00004.w
1120	1120	PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNKNOWN ) // unused?
1121	1121
1122		PORT_START // IN3 - Other Buttons - c00006.w
	1122	PORT_START_TAG("IN3") // IN3 - Other Buttons - c00006.w
1123	1123	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
1124	1124	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
1125	1125	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1135	1135	***************************************************************************/
1136	1136
1137	1137	static INPUT_PORTS_START( bloodwar )
1138		PORT_START // IN0 - Player 1 - b00000.w
	1138	PORT_START_TAG("IN0") // IN0 - Player 1 - b00000.w
1139	1139	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
1140	1140	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
1141	1141	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
r2864	r2865
1145	1145	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
1146	1146	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
1147	1147
1148		PORT_START // IN1 - Player 2 - b00002.w
	1148	PORT_START_TAG("IN1") // IN1 - Player 2 - b00002.w
1149	1149	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
1150	1150	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
1151	1151	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
r2864	r2865
1155	1155	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1156	1156	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1157	1157
1158		PORT_START // IN2 - Coins - b00004.w
	1158	PORT_START_TAG("IN2") // IN2 - Coins - b00004.w
1159	1159	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
1160	1160	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
1161	1161	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
r2864	r2865
1165	1165	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SERVICE1 )
1166	1166	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_SERVICE2 ) // tested
1167	1167
1168		PORT_START // IN3 - ? - b00006.w
	1168	PORT_START_TAG("IN3") // IN3 - ? - b00006.w
1169	1169	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN ) // tested
1170	1170	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
1171	1171	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2) // tested
r2864	r2865
1175	1175	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1176	1176	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1177	1177
1178		PORT_START // IN4 - DSW from the MCU - $10497e.b <- $208000.b
	1178	PORT_START_TAG("DSW1") // IN4 - DSW from the MCU - $10497e.b <- $208000.b
1179	1179	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:1")
1180	1180	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
1181	1181	PORT_DIPSETTING( 0x0100, DEF_STR( On ) )
r2864	r2865
1205	1205	***************************************************************************/
1206	1206
1207	1207	static INPUT_PORTS_START( bonkadv )
1208		PORT_START // IN0 - Player 1 - b00000.w
	1208	PORT_START_TAG("IN0") // IN0 - Player 1 - b00000.w
1209	1209	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
1210	1210	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
1211	1211	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
r2864	r2865
1215	1215	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
1216	1216	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
1217	1217
1218		PORT_START // IN1 - Player 2 - b00002.w
	1218	PORT_START_TAG("IN1") // IN1 - Player 2 - b00002.w
1219	1219	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
1220	1220	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
1221	1221	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
r2864	r2865
1225	1225	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1226	1226	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
1227	1227
1228		PORT_START // IN2 - Coins - b00004.w
	1228	PORT_START_TAG("IN2") // IN2 - Coins - b00004.w
1229	1229	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
1230	1230	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
1231	1231	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
r2864	r2865
1235	1235	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SERVICE1 )
1236	1236	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_SERVICE2 )
1237	1237
1238		PORT_START // IN3 - ? - b00006.w
	1238	PORT_START_TAG("IN3") // IN3 - ? - b00006.w
1239	1239	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
1240	1240	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
1241	1241	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1245	1245	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1246	1246	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1247	1247
1248		PORT_START // IN4 - DSW from the MCU - $10019e.b <- $200200.b
	1248	PORT_START_TAG("DSW1") // IN4 - DSW from the MCU - $10019e.b <- $200200.b
1249	1249	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Flip_Screen ) )
1250	1250	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
1251	1251	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
1276	1276	***************************************************************************/
1277	1277
1278	1278	static INPUT_PORTS_START( gtmr )
1279		PORT_START // IN0 - Player 1 - b00000.w
	1279	PORT_START_TAG("IN0") // IN0 - Player 1 - b00000.w
1280	1280	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1281	1281	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1282	1282	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1286	1286	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1287	1287	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1288	1288
1289		PORT_START // IN1 - Player 2 - b00002.w
	1289	PORT_START_TAG("IN1") // IN1 - Player 2 - b00002.w
1290	1290	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1291	1291	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1292	1292	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1296	1296	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1297	1297	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1298	1298
1299		PORT_START // IN2 - Coins - b00004.w
	1299	PORT_START_TAG("IN2") // IN2 - Coins - b00004.w
1300	1300	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
1301	1301	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
1302	1302	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
r2864	r2865
1306	1306	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SERVICE1 )
1307	1307	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1308	1308
1309		PORT_START // IN3 - Seems unused ! - b00006.w
	1309	PORT_START_TAG("IN3") // IN3 - Seems unused ! - b00006.w
1310	1310	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
1311	1311	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
1312	1312	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1316	1316	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1317	1317	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1318	1318
1319		PORT_START // IN4 - DSW from the MCU - 101265.b <- 206000.b
	1319	PORT_START_TAG("DSW1") // IN4 - DSW from the MCU - 101265.b <- 206000.b
1320	1320	PORT_SERVICE_DIPLOC( 0x0100, IP_ACTIVE_LOW, "SW1:1" )
1321	1321	PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:2")
1322	1322	PORT_DIPSETTING( 0x0200, DEF_STR( Off ) )
r2864	r2865
1339	1339	PORT_DIPSETTING( 0x4000, "Flag Only" )
1340	1340	PORT_DIPSETTING( 0x0000, DEF_STR( None ) )
1341	1341
1342		PORT_START // IN5 - Wheel - 100015.b <- ffffe.b
	1342	PORT_START_TAG("WHEEL0") // IN5 - Wheel - 100015.b <- ffffe.b
1343	1343	PORT_BIT ( 0x00ff, 0x0080, IPT_PADDLE ) PORT_SENSITIVITY(30) PORT_KEYDELTA(1)
1344	1344	INPUT_PORTS_END
1345	1345
r2864	r2865
1349	1349	***************************************************************************/
1350	1350
1351	1351	static INPUT_PORTS_START( gtmr2 )
1352		PORT_START // IN0 - Player 1 - 100004.w <- b00000.w (cpl)
	1352	PORT_START_TAG("IN0") // IN0 - Player 1 - 100004.w <- b00000.w (cpl)
1353	1353	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1354	1354	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1355	1355	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1359	1359	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1360	1360	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1361	1361
1362		PORT_START // IN1 - Player 2 - 10000c.w <- b00002.w (cpl) - for "test mode" only
	1362	PORT_START_TAG("IN1") // IN1 - Player 2 - 10000c.w <- b00002.w (cpl) - for "test mode" only
1363	1363	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1364	1364	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1365	1365	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1369	1369	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1370	1370	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1371	1371
1372		PORT_START // IN2 - Coins - 100014.w <- b00004.w (cpl)
	1372	PORT_START_TAG("IN2") // IN2 - Coins - 100014.w <- b00004.w (cpl)
1373	1373	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
1374	1374	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 ) // only in "test mode"
1375	1375	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
r2864	r2865
1379	1379	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SERVICE1 )
1380	1380	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1381	1381
1382		PORT_START // IN3 - 100017.w <- b00006.w
	1382	PORT_START_TAG("IN3") // IN3 - 100017.w <- b00006.w
1383	1383	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
1384	1384	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
1385	1385	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1389	1389	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("IN 3-6") // Code at 0x002236 - Centers 270D wheel ?
1390	1390	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1391	1391
1392		PORT_START // IN4 - DSW from the MCU - 1016f7.b <- 206000.b
	1392	PORT_START_TAG("DSW1") // IN4 - DSW from the MCU - 1016f7.b <- 206000.b
1393	1393	PORT_DIPNAME( 0x0700, 0x0700, "Linked Operation Board Number" ) PORT_DIPLOCATION("SW1:6,7,8")
1394	1394	PORT_DIPSETTING( 0x0700, "No Communication" )
1395	1395	PORT_DIPSETTING( 0x0600, "Board #1" )
r2864	r2865
1414	1414	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
1415	1415	PORT_SERVICE_DIPLOC( 0x8000, IP_ACTIVE_LOW, "SW1:1" )
1416	1416
1417		PORT_START // IN5 - Wheel (270A) - 100019.b <- fffff.b
	1417	PORT_START_TAG("WHEEL0") // IN5 - Wheel (270A) - 100019.b <- fffff.b
1418	1418	PORT_BIT ( 0x00ff, 0x0080, IPT_PADDLE ) PORT_SENSITIVITY(30) PORT_KEYDELTA(1)
1419	1419
1420		PORT_START // IN6 - Wheel (270D) - 100019.b <- ffffe.b
	1420	PORT_START_TAG("WHEEL1") // IN6 - Wheel (270D) - 100019.b <- ffffe.b
1421	1421	PORT_BIT ( 0x00ff, 0x0080, IPT_PADDLE ) PORT_SENSITIVITY(30) PORT_KEYDELTA(1)
1422	1422
1423		PORT_START // IN7 - Wheel (360) - 100019.b <- ffffe.b
	1423	PORT_START_TAG("WHEEL2") // IN7 - Wheel (360) - 100019.b <- ffffe.b
1424	1424	PORT_BIT( 0x00ff, 0x0000, IPT_DIAL ) PORT_SENSITIVITY(30) PORT_KEYDELTA(1) PORT_CODE_DEC(KEYCODE_LEFT) PORT_CODE_INC(KEYCODE_RIGHT)
1425	1425
1426		PORT_START // Fake IN1 - To be pressed during boot sequence - Code at 0x000c9e
	1426	PORT_START_TAG("FAKE") // Fake IN1 - To be pressed during boot sequence - Code at 0x000c9e
1427	1427	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("IN 1-0") PORT_CODE(KEYCODE_H) // "sound test"
1428	1428	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
1429	1429	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1440	1440	***************************************************************************/
1441	1441
1442	1442	static INPUT_PORTS_START( mgcrystl )
1443		PORT_START // IN0 - Player 1 + DSW - c00000.w
	1443	PORT_START_TAG("IN0") // IN0 - Player 1 + DSW - c00000.w
1444	1444	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:1")
1445	1445	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
1446	1446	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
1462	1462	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1463	1463	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1464	1464
1465		PORT_START // IN1 - Player 2 - c00002.b
	1465	PORT_START_TAG("IN1") // IN1 - Player 2 - c00002.b
1466	1466	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
1467	1467	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
1468	1468	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1481	1481	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1482	1482	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1483	1483
1484		PORT_START // IN2 - Other Buttons - c00004.b
	1484	PORT_START_TAG("IN2") // IN2 - Other Buttons - c00004.b
1485	1485	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1486	1486	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
1487	1487	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
r2864	r2865
1500	1500	***************************************************************************/
1501	1501
1502	1502	static INPUT_PORTS_START( shogwarr )
1503		PORT_START // IN0 - - b80000.w
	1503	PORT_START_TAG("IN0") // IN0 - - b80000.w
1504	1504	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1505	1505	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1506	1506	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1510	1510	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
1511	1511	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN ) // ? tested
1512	1512
1513		PORT_START // IN1 - - b80002.w
	1513	PORT_START_TAG("IN1") // IN1 - - b80002.w
1514	1514	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1515	1515	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1516	1516	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1520	1520	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1521	1521	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN ) // ? tested
1522	1522
1523		PORT_START // IN2 - Coins - b80004.w
	1523	PORT_START_TAG("IN2") // IN2 - Coins - b80004.w
1524	1524	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
1525	1525	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
1526	1526	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
r2864	r2865
1530	1530	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SERVICE1 )
1531	1531	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN ) // ? tested
1532	1532
1533		PORT_START // IN3 - ? - b80006.w
	1533	PORT_START_TAG("IN3") // IN3 - ? - b80006.w
1534	1534	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
1535	1535	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
1536	1536	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1540	1540	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1541	1541	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1542	1542
1543		PORT_START // IN4 - DSW from the MCU - 102e15.b <- 200059.b
	1543	PORT_START_TAG("DSW1") // IN4 - DSW from the MCU - 102e15.b <- 200059.b
1544	1544	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:1")
1545	1545	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1546	1546	PORT_DIPSETTING( 0x00, DEF_STR( On ) )

src/mame/drivers/gauntlet.c
r2864	r2865
193	193
194	194	static READ16_HANDLER( port4_r )
195	195	{
196		int temp = input_port_read~~_indexed~~(machine, 4);
	196	int temp = input_port_read(machine, "IN4");
197	197	if (atarigen_cpu_to_sound_ready) temp ^= 0x0020;
198	198	if (atarigen_sound_to_cpu_ready) temp ^= 0x0010;
199	199	return temp;
r2864	r2865
237	237	if (atarigen_cpu_to_sound_ready) temp ^= 0x80;
238	238	if (atarigen_sound_to_cpu_ready) temp ^= 0x40;
239	239	if (tms5220_ready_r()) temp ^= 0x20;
240		if (!(input_port_read~~_indexed~~(machine, 4) & 0x0008)) temp ^= 0x10;
	240	if (!(input_port_read(machine, "IN4") & 0x0008)) temp ^= 0x10;
241	241
242	242	return temp;
243	243	}
r2864	r2865
1631	1631	*
1632	1632	*************************************/
1633	1633
1634		static void gauntlet_common_init(int slapstic, int vindctr2)
	1634	static void gauntlet_common_init(running_machine *machine, int slapstic, int vindctr2)
1635	1635	{
1636	1636	UINT8 *rom = memory_region(REGION_CPU1);
1637	1637	atarigen_eeprom_default = NULL;
1638		atarigen_slapstic_init(0, 0x038000, 0, slapstic);
	1638	atarigen_slapstic_init(machine, 0, 0x038000, 0, slapstic);
1639	1639
1640	1640	/* swap the top and bottom halves of the main CPU ROM images */
1641	1641	atarigen_swap_mem(rom + 0x000000, rom + 0x008000, 0x8000);
r2864	r2865
1651	1651
1652	1652	static DRIVER_INIT( gauntlet )
1653	1653	{
1654		gauntlet_common_init(104, 0);
	1654	gauntlet_common_init(machine, 104, 0);
1655	1655	}
1656	1656
1657	1657
1658	1658	static DRIVER_INIT( gaunt2p )
1659	1659	{
1660		gauntlet_common_init(107, 0);
	1660	gauntlet_common_init(machine, 107, 0);
1661	1661	}
1662	1662
1663	1663
1664	1664	static DRIVER_INIT( gauntlet2 )
1665	1665	{
1666		gauntlet_common_init(106, 0);
	1666	gauntlet_common_init(machine, 106, 0);
1667	1667	}
1668	1668
1669	1669
r2864	r2865
1673	1673	UINT8 *data = malloc_or_die(0x8000);
1674	1674	int i;
1675	1675
1676		gauntlet_common_init(118, 1);
	1676	gauntlet_common_init(machine, 118, 1);
1677	1677
1678	1678	/* highly strange -- the address bits on the chip at 2J (and only that
1679	1679	chip) are scrambled -- this is verified on the schematics! */

src/mame/drivers/ms32.c
r2864	r2865
1288	1288	return i;
1289	1289	}
1290	1290
1291		static void irq_init(void)
	1291	static void irq_init(running_machine *machine)
1292	1292	{
1293	1293	irqreq = 0;
1294		cpunum_set_input_line(Machine, 0, 0, CLEAR_LINE);
	1294	cpunum_set_input_line(machine, 0, 0, CLEAR_LINE);
1295	1295	cpunum_set_irq_callback(0, irq_callback);
1296	1296	}
1297	1297
1298		static void irq_raise(int level)
	1298	static void irq_raise(running_machine *machine, int level)
1299	1299	{
1300	1300	irqreq \|= (1<<level);
1301		cpunum_set_input_line(Machine, 0, 0, ASSERT_LINE);
	1301	cpunum_set_input_line(machine, 0, 0, ASSERT_LINE);
1302	1302	}
1303	1303
1304	1304	static INTERRUPT_GEN(ms32_interrupt)
1305	1305	{
1306		if( cpu_getiloops() == 0 ) irq_raise(10);
1307		if( cpu_getiloops() == 1 ) irq_raise(9);
	1306	if( cpu_getiloops() == 0 ) irq_raise(machine, 10);
	1307	if( cpu_getiloops() == 1 ) irq_raise(machine, 9);
1308	1308	/* hayaosi2 needs at least 12 IRQ 0 per frame to work (see code at FFE02289)
1309	1309	kirarast needs it too, at least 8 per frame, but waits for a variable amount
1310	1310	47pi2 needs ?? per frame (otherwise it hangs when you lose)
r2864	r2865
1313	1313	desertwr
1314	1314	p47aces
1315	1315	*/
1316		if( cpu_getiloops() >= 3 && cpu_getiloops() <= 32 ) irq_raise(0);
	1316	if( cpu_getiloops() >= 3 && cpu_getiloops() <= 32 ) irq_raise(machine, 0);
1317	1317	}
1318	1318
1319	1319	/******** SOUND ********/
r2864	r2865
1354	1354	static WRITE8_HANDLER( to_main_w )
1355	1355	{
1356	1356	to_main=data;
1357		irq_raise(1);
	1357	irq_raise(machine, 1);
1358	1358	}
1359	1359
1360	1360	static ADDRESS_MAP_START( ms32_snd_readmem, ADDRESS_SPACE_PROGRAM, 8 )
r2864	r2865
1391	1391	memory_set_bankptr(1, memory_region(REGION_CPU1));
1392	1392	memory_set_bank(4, 0);
1393	1393	memory_set_bank(5, 1);
1394		irq_init();
	1394	irq_init(machine);
1395	1395	}
1396	1396
1397	1397	/******** MACHINE DRIVER ********/

src/mame/drivers/system16.c
r2864	r2865
169	169	#include "sound/2151intf.h"
170	170	#include "sound/upd7759.h"
171	171
172		void fd1094_machine_init(void);
173		void fd1094_driver_init(void (set_decrypted)(UINT8 ));
174
175	172	static void sys16_video_config(void (update)(void), int sprxoffs, const int bank)
176	173	{
177	174	static const int bank_default[16] =
r2864	r2865
2634	2631	ROM_LOAD( "pas4p.2", 0x10000, 0x10000, CRC(092e016e) SHA1(713638749efa9dce19c547b84308236110bc85fe) )
2635	2632	ROM_END
2636	2633
	2634	/* Passing Shot Bootleg is a decrypted version of Passing Shot Japanese (passshtj). It has been heavily modified */
	2635
2637	2636	ROM_START( passshtb )
2638	2637	ROM_REGION( 0x020000, REGION_CPU1, 0 ) /* 68000 code */
2639	2638	ROM_LOAD16_BYTE( "pass3_2p.bin", 0x000000, 0x10000, CRC(26bb9299) SHA1(11bacf86dfdd8bcfbfb61f0ebc59890325c48adc) )

src/mame/drivers/limenko.c
r2864	r2865
38	38
39	39	static READ32_HANDLER( port2_r )
40	40	{
41		return (eeprom_read_bit() << 23) \| (input_port_read~~_indexed~~(machine, 2) & ~(1<<23));
	41	return (eeprom_read_bit() << 23) \| (input_port_read(machine, "IN2") & ~(1<<23));
42	42	}
43	43
44	44	static WRITE32_HANDLER( eeprom_w )
r2864	r2865
313	313	*****************************************************************************************************/
314	314
315	315	static INPUT_PORTS_START( legendoh )
316		PORT_START
	316	PORT_START_TAG("IN0")
317	317	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
318	318	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
319	319	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
r2864	r2865
332	332	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(3)
333	333	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNUSED )
334	334
335		PORT_START
	335	PORT_START_TAG("IN1")
336	336	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
337	337	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
338	338	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
r2864	r2865
351	351	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(4)
352	352	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNUSED )
353	353
354		PORT_START
	354	PORT_START_TAG("IN2")
355	355	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_START1 )
356	356	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_START2 )
357	357	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
373	373	INPUT_PORTS_END
374	374
375	375	static INPUT_PORTS_START( sb2003 )
376		PORT_START
	376	PORT_START_TAG("IN0")
377	377	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
378	378	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
379	379	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
r2864	r2865
384	384	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
385	385	PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
386	386
387		PORT_START
	387	PORT_START_TAG("IN1")
388	388	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
389	389	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
390	390	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
r2864	r2865
395	395	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
396	396	PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
397	397
398		PORT_START
	398	PORT_START_TAG("IN2")
399	399	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_START1 )
400	400	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_START2 )
401	401	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
411	411	INPUT_PORTS_END
412	412
413	413	static INPUT_PORTS_START( spotty )
414		PORT_START
	414	PORT_START_TAG("IN0")
415	415	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Hold 1")
416	416	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Hold 2")
417	417	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_NAME("Hold 3")
r2864	r2865
422	422	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_UNUSED )
423	423	PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
424	424
425		PORT_START
	425	PORT_START_TAG("IN1")
426	426	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_UNUSED )
427	427	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_UNUSED )
428	428	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
433	433	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_UNUSED )
434	434	PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
435	435
436		PORT_START
	436	PORT_START_TAG("IN2")
437	437	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_START1 )
438	438	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_UNUSED )
439	439	PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_COIN1 )

src/mame/drivers/model1.c
r2864	r2865
679	679
680	680	static int last_irq;
681	681
682		static void irq_raise(int level)
	682	static void irq_raise(running_machine *machine, int level)
683	683	{
684	684	// logerror("irq: raising %d\n", level);
685	685	// irq_status \|= (1 << level);
686	686	last_irq = level;
687		cpunum_set_input_line(Machine, 0, 0, HOLD_LINE);
	687	cpunum_set_input_line(machine, 0, 0, HOLD_LINE);
688	688	}
689	689
690	690	static IRQ_CALLBACK(irq_callback)
r2864	r2865
705	705	// 3 = ff54c
706	706	// other = ff568/ff574
707	707
708		static void irq_init(void)
	708	static void irq_init(running_machine *machine)
709	709	{
710		cpunum_set_input_line(Machine, 0, 0, CLEAR_LINE);
	710	cpunum_set_input_line(machine, 0, 0, CLEAR_LINE);
711	711	cpunum_set_irq_callback(0, irq_callback);
712	712	}
713	713
r2864	r2865
715	715	{
716	716	if (cpu_getiloops())
717	717	{
718		irq_raise(1);
	718	irq_raise(machine, 1);
719	719	}
720	720	else
721	721	{
722		irq_raise(model1_sound_irq);
	722	irq_raise(machine, model1_sound_irq);
723	723
724	724	// if the FIFO has something in it, signal the 68k too
725	725	if (fifo_rptr != fifo_wptr)
r2864	r2865
732	732	static MACHINE_RESET(model1)
733	733	{
734	734	memory_set_bankptr(1, memory_region(REGION_CPU1) + 0x1000000);
735		irq_init();
	735	irq_init(machine);
736	736	model1_tgp_reset(!strcmp(machine->gamedrv->name, "swa") \|\| !strcmp(machine->gamedrv->name, "wingwar") \|\| !strcmp(machine->gamedrv->name, "wingwara"));
737	737	if (!strcmp(machine->gamedrv->name, "swa"))
738	738	{
r2864	r2865
751	751	static MACHINE_RESET(model1_vr)
752	752	{
753	753	memory_set_bankptr(1, memory_region(REGION_CPU1) + 0x1000000);
754		irq_init();
	754	irq_init(machine);
755	755	model1_vr_tgp_reset();
756	756	model1_sound_irq = 3;
757	757

src/mame/drivers/jackal.c
r2864	r2865
87	87
88	88	static READ8_HANDLER( topgunbl_rotary_r )
89	89	{
90		return (1 << (input_port_read~~_indexed~~(machine, ~~5 +~~ offset) * 8 / 256)) ^ 0xff;
	90	return (1 << (input_port_read(machine, offset ? "DIAL1" : "DIAL0") * 8 / 256)) ^ 0xff;
91	91	}
92	92
93	93	static WRITE8_HANDLER( jackal_flipscreen_w )
r2864	r2865
232	232	PORT_MODIFY("IN0")
233	233	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
234	234
235		PORT_START // player 1 8-way rotary control - converted in topgunbl_rotary_r()
	235	PORT_START_TAG("DIAL0") // player 1 8-way rotary control - converted in topgunbl_rotary_r()
236	236	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(25) PORT_KEYDELTA(10) PORT_CODE_DEC(KEYCODE_Z) PORT_CODE_INC(KEYCODE_X)
237	237
238		PORT_START // player 2 8-way rotary control - converted in topgunbl_rotary_r()
	238	PORT_START_TAG("DIAL1") // player 2 8-way rotary control - converted in topgunbl_rotary_r()
239	239	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(25) PORT_KEYDELTA(10) PORT_CODE_DEC(KEYCODE_N) PORT_CODE_INC(KEYCODE_M) PORT_PLAYER(2)
240	240	INPUT_PORTS_END
241	241

src/mame/drivers/tank8.c
r2864	r2865
5	5	***************************************************************************/
6	6
7	7	#include "driver.h"
8		#include "deprecat.h"
9	8	#include "tank8.h"
10	9	#include "sound/discrete.h"
11	10
12	11	static int collision_index;
13	12
14	13
15		void tank8_set_collision(int index)
	14	void tank8_set_collision(running_machine *machine, int index)
16	15	{
17		cpunum_set_input_line(Machine, 0, 0, ASSERT_LINE);
	16	cpunum_set_input_line(machine, 0, 0, ASSERT_LINE);
18	17
19	18	collision_index = index;
20	19	}

src/mame/drivers/cps1.c
r2864	r2865
7705	7705	ROM_LOAD( "pa3-06.11d", 0x20000, 0x20000, CRC(affa4f82) SHA1(27b9292bbc121cf585f53297a79fe8f0d0a729ae) )
7706	7706	ROM_END
7707	7707
7708		/* B-Board uncertain but should be 91634B/91635B from the program ROM names */
7709		/* there's a photo of a 91635B board but it's clearly not original */
	7708	/* B-Board 91634B */
7710	7709	ROM_START( megaman )
7711	7710	ROM_REGION( CODE_SIZE, REGION_CPU1, 0 ) /* 68000 code */
7712	7711	ROM_LOAD16_WORD_SWAP( "rcma_23b.rom", 0x000000, 0x80000, CRC(61e4a397) SHA1(a90b1cbef4206a4554398bc458a4b3e2c46d4c4f) )
r2864	r2865
7952	7951	GAME( 1992, varthr1, varth, cps1_12MHz, varth, cps1, ROT270, "Capcom", "Varth - Operation Thunderstorm (World 920612)" , 0) // "ETC"
7953	7952	GAME( 1992, varthu, varth, cps1_12MHz, varth, cps1, ROT270, "Capcom (Romstar license)", "Varth - Operation Thunderstorm (US 920612)", 0 )
7954	7953	GAME( 1992, varthj, varth, cps1_12MHz, varth, cps1, ROT270, "Capcom", "Varth - Operation Thunderstorm (Japan 920714)", 0 )
7955		GAME( 1992, cworld2j, 0, cps1_10MHz, cworld2j, cps1, ROT0, "Capcom", "Capcom World 2 (Japan 920611)", 0 )
	7954	GAME( 1992, cworld2j, 0, cps1_12MHz, cworld2j, cps1, ROT0, "Capcom", "Capcom World 2 (Japan 920611)", 0 )
7956	7955	GAME( 1992, sf2hf, sf2ce, cps1_12MHz, sf2, cps1, ROT0, "Capcom", "Street Fighter II' - Hyper Fighting (World 921209)", 0 )
7957	7956	GAME( 1992, sf2t, sf2ce, cps1_12MHz, sf2, cps1, ROT0, "Capcom", "Street Fighter II' - Hyper Fighting (US 921209)", 0 )
7958	7957	GAME( 1992, sf2tj, sf2ce, cps1_12MHz, sf2j, cps1, ROT0, "Capcom", "Street Fighter II' Turbo - Hyper Fighting (Japan 921209)", 0 )
7959	7958	GAME( 1992, qad, 0, cps1_12MHz, qad, cps1, ROT0, "Capcom", "Quiz & Dragons (US 920701)", 0 ) // 12MHz verified
7960		GAME( 1994, qadj, qad, cps1_10MHz, qadj, cps1, ROT0, "Capcom", "Quiz & Dragons (Japan 940921)", 0 )
7961		GAME( 1995, qtono2, 0, cps1_10MHz, qtono2, cps1, ROT0, "Capcom", "Quiz Tonosama no Yabou 2 Zenkoku-ban (Japan 950123)", 0 )
7962		GAME( 1995, megaman, 0, cps1_10MHz, megaman, cps1, ROT0, "Capcom", "Mega Man - The Power Battle (CPS1 Asia 951006)", 0 )
7963		GAME( 1995, rockmanj, megaman, cps1_10MHz, rockmanj, cps1, ROT0, "Capcom", "Rockman - The Power Battle (CPS1 Japan 950922)", 0 )
	7959	GAME( 1994, qadj, qad, cps1_12MHz, qadj, cps1, ROT0, "Capcom", "Quiz & Dragons (Japan 940921)", 0 )
	7960	GAME( 1995, qtono2, 0, cps1_12MHz, qtono2, cps1, ROT0, "Capcom", "Quiz Tonosama no Yabou 2 Zenkoku-ban (Japan 950123)", 0 )
	7961	GAME( 1995, megaman, 0, cps1_12MHz, megaman, cps1, ROT0, "Capcom", "Mega Man - The Power Battle (CPS1 Asia 951006)", 0 )
	7962	GAME( 1995, rockmanj, megaman, cps1_12MHz, rockmanj, cps1, ROT0, "Capcom", "Rockman - The Power Battle (CPS1 Japan 950922)", 0 )
7964	7963
7965	7964	GAME( 1992, wof, 0, qsound, wof, wof, ROT0, "Capcom", "Warriors of Fate (World 921002)" , 0) // "ETC"
7966	7965	GAME( 1992, wofa, wof, qsound, wof, wof, ROT0, "Capcom", "Sangokushi II (Asia 921005)" , 0) // World "warning"
r2864	r2865
7978	7977	GAME( 1993, mbombrd, 0, qsound, slammast, slammast, ROT0, "Capcom", "Muscle Bomber Duo - Ultimate Team Battle (World 931206)" , 0) // "ETC"
7979	7978	GAME( 1993, mbombrdj, mbombrd, qsound, slammast, slammast, ROT0, "Capcom", "Muscle Bomber Duo - Heat Up Warriors (Japan 931206)", 0 )
7980	7979
7981		GAME( 1994, pnickj, 0, cps1_10MHz, pnickj, cps1, ROT0, "Compile (Capcom license)", "Pnickies (Japan 940608)", 0 )
	7980	GAME( 1994, pnickj, 0, cps1_12MHz, pnickj, cps1, ROT0, "Compile (Capcom license)", "Pnickies (Japan 940608)", 0 )
7982	7981	/* Japanese version of Pang 3 is encrypted, Euro version is not */
7983	7982	GAME( 1995, pang3, 0, pang3, pang3, pang3, ROT0, "Mitchell", "Pang! 3 (Euro 950511)", 0 )
7984	7983	GAME( 1995, pang3j, pang3, pang3, pang3, pang3j, ROT0, "Mitchell", "Pang! 3 (Japan 950511)", 0 )

src/mame/drivers/lethalj.c
r2864	r2865
143	143	*************************************/
144	144
145	145	static INPUT_PORTS_START( lethalj )
146		PORT_START
	146	PORT_START_TAG("IN0")
147	147	PORT_BIT( 0x0003, IP_ACTIVE_LOW, IPT_UNUSED )
148	148	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
149	149	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* ??? Seems to be rigged up to the auto scroll, and acts as a fast forward*/
150	150	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
151	151	PORT_BIT( 0xffe0, IP_ACTIVE_LOW, IPT_UNUSED )
152	152
153		PORT_START
	153	PORT_START_TAG("IN1")
154	154	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE1 )
155	155	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
156	156	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
190	190	PORT_DIPSETTING( 0x0000, "-2.5" )
191	191	PORT_DIPSETTING( 0x8000, "+0" )
192	192
193		PORT_START /* fake analog X */
	193	PORT_START_TAG("LIGHT0_X") /* fake analog X */
194	194	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
195	195
196		PORT_START /* fake analog Y */
	196	PORT_START_TAG("LIGHT0_Y") /* fake analog Y */
197	197	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
198	198
199		PORT_START /* fake analog X */
	199	PORT_START_TAG("LIGHT1_X") /* fake analog X */
200	200	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(2)
201	201
202		PORT_START /* fake analog Y */
	202	PORT_START_TAG("LIGHT1_Y") /* fake analog Y */
203	203	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10) PORT_PLAYER(2)
204	204	INPUT_PORTS_END
205	205
206	206
207	207	static INPUT_PORTS_START( eggventr )
208		PORT_START
	208	PORT_START_TAG("IN0")
209	209	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE1 )
210	210	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
211	211	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
235	235	PORT_DIPSETTING( 0x1000, DEF_STR( On ) ) // but not actually called (EC).
236	236	PORT_BIT( 0xe000, IP_ACTIVE_LOW, IPT_UNUSED )
237	237
238		PORT_START
	238	PORT_START_TAG("IN1")
239	239	PORT_BIT( 0x000f, IP_ACTIVE_LOW, IPT_UNUSED )
240	240	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
241	241	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
r2864	r2865
244	244	PORT_BIT( 0x7f00, IP_ACTIVE_LOW, IPT_UNUSED )
245	245	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
246	246
247		PORT_START /* fake analog X */
	247	PORT_START_TAG("LIGHT0_X") /* fake analog X */
248	248	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
249	249
250		PORT_START /* fake analog Y */
	250	PORT_START_TAG("LIGHT0_Y") /* fake analog Y */
251	251	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
252	252
253		PORT_START /* fake analog X */
	253	PORT_START_TAG("LIGHT1_X") /* fake analog X */
254	254	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(2)
255	255
256		PORT_START /* fake analog Y */
	256	PORT_START_TAG("LIGHT1_Y") /* fake analog Y */
257	257	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10) PORT_PLAYER(2)
258	258	INPUT_PORTS_END
259	259
260	260
261	261	static INPUT_PORTS_START( eggvntdx )
262		PORT_START
	262	PORT_START_TAG("IN0")
263	263	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE1 )
264	264	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
265	265	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
286	286	PORT_DIPSETTING( 0x0000, DEF_STR( Hard ) )
287	287	PORT_BIT( 0xe000, IP_ACTIVE_LOW, IPT_UNUSED )
288	288
289		PORT_START
	289	PORT_START_TAG("IN1")
290	290	PORT_BIT( 0x000f, IP_ACTIVE_LOW, IPT_UNUSED )
291	291	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
292	292	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
r2864	r2865
295	295	PORT_BIT( 0x7f00, IP_ACTIVE_LOW, IPT_UNUSED )
296	296	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
297	297
298		PORT_START /* fake analog X */
	298	PORT_START_TAG("LIGHT0_X") /* fake analog X */
299	299	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
300	300
301		PORT_START /* fake analog Y */
	301	PORT_START_TAG("LIGHT0_Y") /* fake analog Y */
302	302	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
303	303
304		PORT_START /* fake analog X */
	304	PORT_START_TAG("LIGHT1_X") /* fake analog X */
305	305	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(2)
306	306
307		PORT_START /* fake analog Y */
	307	PORT_START_TAG("LIGHT1_Y") /* fake analog Y */
308	308	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10) PORT_PLAYER(2)
309	309	INPUT_PORTS_END
310	310
311	311
312	312	static INPUT_PORTS_START( ripribit )
313		PORT_START
	313	PORT_START_TAG("IN0")
314	314	PORT_BIT( 0x000f, IP_ACTIVE_LOW, IPT_UNUSED )
315	315	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
316	316	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_SPECIAL ) PORT_CUSTOM(ticket_status, NULL)
317	317	PORT_BIT( 0xffc0, IP_ACTIVE_LOW, IPT_UNUSED )
318	318
319		PORT_START
	319	PORT_START_TAG("IN1")
320	320	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE1 )
321	321	PORT_SERVICE_NO_TOGGLE( 0x0002, IP_ACTIVE_HIGH )
322	322	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
356	356	PORT_DIPSETTING( 0x2000, "800" )
357	357	PORT_DIPSETTING( 0x0000, "1000" )
358	358
359		PORT_START /* fake analog X */
360		PORT_START /* fake analog Y */
361		PORT_START /* fake analog X */
362		PORT_START /* fake analog Y */
	359	PORT_START_TAG("LIGHT0_X") /* fake analog X */
	360	PORT_START_TAG("LIGHT0_Y") /* fake analog Y */
	361	PORT_START_TAG("LIGHT1_X") /* fake analog X */
	362	PORT_START_TAG("LIGHT1_Y") /* fake analog Y */
363	363	INPUT_PORTS_END
364	364
365	365
366	366	static INPUT_PORTS_START( cfarm )
367		PORT_START
	367	PORT_START_TAG("IN0")
368	368	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE1 )
369	369	PORT_SERVICE_NO_TOGGLE( 0x0002, IP_ACTIVE_HIGH )
370	370	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
404	404	PORT_DIPSETTING( 0x2000, "8" )
405	405	PORT_DIPSETTING( 0x0000, "10" )
406	406
407		PORT_START
	407	PORT_START_TAG("IN1")
408	408	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SPECIAL ) PORT_CUSTOM(ticket_status, NULL)
409	409	PORT_BIT( 0x0006, IP_ACTIVE_LOW, IPT_UNUSED )
410	410	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
r2864	r2865
412	412	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
413	413	PORT_BIT( 0xffc0, IP_ACTIVE_LOW, IPT_UNUSED )
414	414
415		PORT_START /* fake analog X */
416		PORT_START /* fake analog Y */
417		PORT_START /* fake analog X */
418		PORT_START /* fake analog Y */
	415	PORT_START_TAG("LIGHT0_X") /* fake analog X */
	416	PORT_START_TAG("LIGHT0_Y") /* fake analog Y */
	417	PORT_START_TAG("LIGHT1_X") /* fake analog X */
	418	PORT_START_TAG("LIGHT1_Y") /* fake analog Y */
419	419	INPUT_PORTS_END
420	420
421	421
422	422	static INPUT_PORTS_START( cclownz )
423		PORT_START
	423	PORT_START_TAG("IN0")
424	424	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE1 )
425	425	PORT_SERVICE_NO_TOGGLE( 0x0002, IP_ACTIVE_HIGH )
426	426	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
460	460	PORT_DIPSETTING( 0x2000, "2400" )
461	461	PORT_DIPSETTING( 0x0000, "3000" )
462	462
463		PORT_START
	463	PORT_START_TAG("IN1")
464	464	PORT_BIT( 0x0f0f, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(cclownz_paddle, NULL)
465	465	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_SPECIAL ) PORT_CUSTOM(ticket_status, NULL)
466	466	PORT_BIT( 0x0060, IP_ACTIVE_LOW, IPT_UNUSED )
467	467	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START1 )
468	468	PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNUSED )
469	469
470		PORT_START /* fake analog X */
471		PORT_START /* fake analog Y */
472		PORT_START /* fake analog X */
473		PORT_START /* fake analog Y */
	470	PORT_START_TAG("LIGHT0_X") /* fake analog X */
	471	PORT_START_TAG("LIGHT0_Y") /* fake analog Y */
	472	PORT_START_TAG("LIGHT1_X") /* fake analog X */
	473	PORT_START_TAG("LIGHT1_Y") /* fake analog Y */
474	474
475	475	PORT_START_TAG("PADDLE")
476	476	PORT_BIT( 0x00ff, 0x0000, IPT_PADDLE ) PORT_PLAYER(1) PORT_SENSITIVITY(50) PORT_KEYDELTA(8) PORT_CENTERDELTA(0) PORT_REVERSE

src/mame/drivers/itech8.c
r2864	r2865
712	712	/* used by most games */
713	713	static READ8_HANDLER( special_port0_r )
714	714	{
715		UINT8 result = input_port_read~~_indexed~~(machine, 0);
	715	UINT8 result = input_port_read(machine, "40");
716	716	result = (result & 0xfe) \| (pia_portb_data & 0x01);
717	717	return result;
718	718	}
r2864	r2865
721	721	/* used by Rim Rockin' Basketball */
722	722	static READ8_HANDLER( special_port1_r )
723	723	{
724		UINT8 result = input_port_read~~_indexed~~(machine, 1);
	724	UINT8 result = input_port_read(machine, "60");
725	725	result = (result & 0x7f) \| ((pia_portb_data & 0x01) << 7);
726	726	return result;
727	727	}
r2864	r2865
1013	1013	*
1014	1014	*************************************/
1015	1015
1016		#define UNUSED_ANALOG \
1017		PORT_START \
	1016	#define UNUSED_ANALOG(TAG) \
	1017	PORT_START_TAG(TAG) \
1018	1018	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1019	1019
1020	1020
1021	1021	static INPUT_PORTS_START( wfortune )
1022		PORT_START /* 40 */
	1022	PORT_START_TAG("40") /* 40 */
1023	1023	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1024	1024	PORT_BIT( 0x06, IP_ACTIVE_LOW, IPT_UNUSED )
1025	1025	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Cabinet ))
r2864	r2865
1028	1028	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
1029	1029	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1030	1030
1031		PORT_START /* 60 */
	1031	PORT_START_TAG("60") /* 60 */
1032	1032	PORT_BIT( 0x07, IP_ACTIVE_LOW, IPT_UNKNOWN )
1033	1033	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Blue Player") PORT_PLAYER(3)
1034	1034	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Yellow Player") PORT_PLAYER(2)
r2864	r2865
1036	1036	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
1037	1037	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
1038	1038
1039		PORT_START /* 80 */
	1039	PORT_START_TAG("80") /* 80 */
1040	1040	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1041	1041
1042		UNUSED_ANALOG /* analog C */
	1042	UNUSED_ANALOG("AN_C") /* analog C */
1043	1043
1044		PORT_START /* analog D */
	1044	PORT_START_TAG("AN_D") /* analog D */
1045	1045	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(75) PORT_KEYDELTA(10) PORT_PLAYER(1)
1046	1046
1047		UNUSED_ANALOG /* analog E */
	1047	UNUSED_ANALOG("AN_E") /* analog E */
1048	1048
1049		PORT_START /* analog F */
	1049	PORT_START_TAG("AN_F") /* analog F */
1050	1050	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(75) PORT_KEYDELTA(10) PORT_COCKTAIL PORT_PLAYER(2)
1051	1051	INPUT_PORTS_END
1052	1052
1053	1053
1054	1054	static INPUT_PORTS_START( stratab )
1055		PORT_START /* 40 */
	1055	PORT_START_TAG("40") /* 40 */
1056	1056	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1057	1057	PORT_BIT( 0x06, IP_ACTIVE_LOW, IPT_UNUSED )
1058	1058	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Cabinet ))
r2864	r2865
1061	1061	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
1062	1062	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1063	1063
1064		PORT_START /* 60 */
	1064	PORT_START_TAG("60") /* 60 */
1065	1065	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P2 Right Hook") PORT_COCKTAIL PORT_PLAYER(2)
1066	1066	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P2 Left Hook") PORT_COCKTAIL PORT_PLAYER(2)
1067	1067	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P1 Right Hook") PORT_PLAYER(1)
r2864	r2865
1071	1071	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
1072	1072	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1073	1073
1074		PORT_START /* 80 */
	1074	PORT_START_TAG("80") /* 80 */
1075	1075	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1076	1076
1077		PORT_START /* analog C */
	1077	PORT_START_TAG("AN_C") /* analog C */
1078	1078	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_PLAYER(1)
1079	1079
1080		PORT_START /* analog D */
	1080	PORT_START_TAG("AN_D") /* analog D */
1081	1081	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_REVERSE PORT_PLAYER(1)
1082	1082
1083		PORT_START /* analog E */
	1083	PORT_START_TAG("AN_E") /* analog E */
1084	1084	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_COCKTAIL PORT_PLAYER(2)
1085	1085
1086		PORT_START /* analog F */
	1086	PORT_START_TAG("AN_F") /* analog F */
1087	1087	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_REVERSE PORT_COCKTAIL PORT_PLAYER(2)
1088	1088	INPUT_PORTS_END
1089	1089
r2864	r2865
1096	1096	}
1097	1097
1098	1098	static INPUT_PORTS_START( gtg )
1099		PORT_START /* 40 */
	1099	PORT_START_TAG("40") /* 40 */
1100	1100	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1101	1101	PORT_BIT( 0x06, IP_ACTIVE_LOW, IPT_UNUSED )
1102	1102	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Cabinet ))
r2864	r2865
1105	1105	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
1106	1106	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1107	1107
1108		PORT_START /* 60 */
	1108	PORT_START_TAG("60") /* 60 */
1109	1109	/* it is still unknown how the second player inputs are muxed in */
1110	1110	/* currently we map both sets of controls to the same inputs */
1111	1111	PORT_BIT( 0x1f, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(gtg_mux, "P1\0P2")
r2864	r2865
1113	1113	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
1114	1114	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1115	1115
1116		PORT_START /* 80 */
	1116	PORT_START_TAG("80") /* 80 */
1117	1117	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1118	1118
1119		UNUSED_ANALOG /* analog C */
1120		UNUSED_ANALOG /* analog D */
1121		UNUSED_ANALOG /* analog E */
1122		UNUSED_ANALOG /* analog F */
	1119	UNUSED_ANALOG("AN_C") /* analog C */
	1120	UNUSED_ANALOG("AN_D") /* analog D */
	1121	UNUSED_ANALOG("AN_E") /* analog E */
	1122	UNUSED_ANALOG("AN_F") /* analog F */
1123	1123
1124	1124	PORT_START_TAG("P1")
1125	1125	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
r2864	r2865
1138	1138
1139	1139
1140	1140	static INPUT_PORTS_START( gtgt )
1141		PORT_START /* 40 */
	1141	PORT_START_TAG("40") /* 40 */
1142	1142	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1143	1143	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNKNOWN )
1144	1144	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1145	1145
1146		PORT_START /* 60 */
	1146	PORT_START_TAG("60") /* 60 */
1147	1147	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
1148	1148	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
1149	1149	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Face Right") PORT_PLAYER(1)
r2864	r2865
1153	1153	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
1154	1154	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1155	1155
1156		PORT_START /* 80 */
	1156	PORT_START_TAG("80") /* 80 */
1157	1157	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1158	1158
1159		PORT_START /* analog C */
	1159	PORT_START_TAG("AN_C") /* analog C */
1160	1160	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_PLAYER(1)
1161	1161
1162		PORT_START /* analog D */
	1162	PORT_START_TAG("AN_D") /* analog D */
1163	1163	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_REVERSE PORT_PLAYER(1)
1164	1164
1165		UNUSED_ANALOG /* analog E */
1166		UNUSED_ANALOG /* analog F */
	1165	UNUSED_ANALOG("AN_E") /* analog E */
	1166	UNUSED_ANALOG("AN_F") /* analog F */
1167	1167	INPUT_PORTS_END
1168	1168
1169	1169
1170	1170	static INPUT_PORTS_START( gtg2t )
1171		PORT_START /* 40 */
	1171	PORT_START_TAG("40") /* 40 */
1172	1172	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1173	1173	PORT_BIT( 0x06, IP_ACTIVE_LOW, IPT_UNUSED )
1174	1174	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Cabinet ))
r2864	r2865
1177	1177	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
1178	1178	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1179	1179
1180		PORT_START /* 60 */
	1180	PORT_START_TAG("60") /* 60 */
1181	1181	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P2 Face Right") PORT_COCKTAIL PORT_PLAYER(2)
1182	1182	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P2 Face Left") PORT_COCKTAIL PORT_PLAYER(2)
1183	1183	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P1 Face Right") PORT_PLAYER(1)
r2864	r2865
1187	1187	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
1188	1188	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1189	1189
1190		PORT_START /* 80 */
	1190	PORT_START_TAG("80") /* 80 */
1191	1191	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1192	1192
1193		PORT_START /* analog C */
	1193	PORT_START_TAG("AN_C") /* analog C */
1194	1194	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_PLAYER(1)
1195	1195
1196		PORT_START /* analog D */
	1196	PORT_START_TAG("AN_D") /* analog D */
1197	1197	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_REVERSE PORT_PLAYER(1)
1198	1198
1199		PORT_START /* analog E */
	1199	PORT_START_TAG("AN_E") /* analog E */
1200	1200	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_COCKTAIL PORT_PLAYER(2)
1201	1201
1202		PORT_START /* analog F */
	1202	PORT_START_TAG("AN_F") /* analog F */
1203	1203	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_REVERSE PORT_COCKTAIL PORT_PLAYER(2)
1204	1204	INPUT_PORTS_END
1205	1205
1206	1206
1207	1207	static INPUT_PORTS_START( slikshot )
1208		PORT_START /* 40 */
	1208	PORT_START_TAG("40") /* 40 */
1209	1209	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1210	1210	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNKNOWN )
1211	1211	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1212	1212
1213		PORT_START /* 60 */
	1213	PORT_START_TAG("60") /* 60 */
1214	1214	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN4 )
1215	1215	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1216	1216	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SPECIAL )
r2864	r2865
1220	1220	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Green")
1221	1221	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1222	1222
1223		PORT_START /* 80 */
	1223	PORT_START_TAG("80") /* 80 */
1224	1224	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1225	1225
1226		UNUSED_ANALOG /* analog C */
1227		UNUSED_ANALOG /* analog D */
1228		UNUSED_ANALOG /* analog E */
1229		UNUSED_ANALOG /* analog F */
	1226	UNUSED_ANALOG("AN_C") /* analog C */
	1227	UNUSED_ANALOG("AN_D") /* analog D */
	1228	UNUSED_ANALOG("AN_E") /* analog E */
	1229	UNUSED_ANALOG("AN_F") /* analog F */
1230	1230
1231	1231	PORT_START_TAG("FAKEX") /* fake */
1232	1232	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_RESET PORT_PLAYER(1)
r2864	r2865
1237	1237
1238	1238
1239	1239	static INPUT_PORTS_START( dynobop )
1240		PORT_START /* 40 */
	1240	PORT_START_TAG("40") /* 40 */
1241	1241	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1242	1242	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNKNOWN )
1243	1243	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1244	1244
1245		PORT_START /* 60 */
	1245	PORT_START_TAG("60") /* 60 */
1246	1246	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* ball gate */
1247	1247	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1248	1248	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* ball detect */
r2864	r2865
1252	1252	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
1253	1253	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1254	1254
1255		PORT_START /* 80 */
	1255	PORT_START_TAG("80") /* 80 */
1256	1256	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1257	1257
1258		UNUSED_ANALOG /* analog C */
1259		UNUSED_ANALOG /* analog D */
1260		UNUSED_ANALOG /* analog E */
1261		UNUSED_ANALOG /* analog F */
	1258	UNUSED_ANALOG("AN_C") /* analog C */
	1259	UNUSED_ANALOG("AN_D") /* analog D */
	1260	UNUSED_ANALOG("AN_E") /* analog E */
	1261	UNUSED_ANALOG("AN_F") /* analog F */
1262	1262
1263	1263	PORT_START_TAG("FAKEX") /* fake */
1264	1264	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_RESET PORT_PLAYER(1)
r2864	r2865
1269	1269
1270	1270
1271	1271	static INPUT_PORTS_START( sstrike )
1272		PORT_START /* 40 */
	1272	PORT_START_TAG("40") /* 40 */
1273	1273	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1274	1274	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNKNOWN )
1275	1275	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1276	1276
1277		PORT_START /* 60 */
	1277	PORT_START_TAG("60") /* 60 */
1278	1278	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN4 )
1279	1279	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1280	1280	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SPECIAL )
r2864	r2865
1284	1284	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
1285	1285	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1286	1286
1287		PORT_START /* 80 */
	1287	PORT_START_TAG("80") /* 80 */
1288	1288	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1289	1289
1290		UNUSED_ANALOG /* analog C */
1291		UNUSED_ANALOG /* analog D */
1292		UNUSED_ANALOG /* analog E */
1293		UNUSED_ANALOG /* analog F */
	1290	UNUSED_ANALOG("AN_C") /* analog C */
	1291	UNUSED_ANALOG("AN_D") /* analog D */
	1292	UNUSED_ANALOG("AN_E") /* analog E */
	1293	UNUSED_ANALOG("AN_F") /* analog F */
1294	1294
1295	1295	PORT_START_TAG("FAKEX") /* fake */
1296	1296	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_RESET PORT_PLAYER(1)
r2864	r2865
1301	1301
1302	1302
1303	1303	static INPUT_PORTS_START( pokrdice )
1304		PORT_START /* 40 */
	1304	PORT_START_TAG("40") /* 40 */
1305	1305	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1306	1306	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Lower Right") PORT_CODE(KEYCODE_3_PAD)
1307	1307	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
1314	1314	PORT_BIT( 0x60, IP_ACTIVE_LOW, IPT_UNUSED )
1315	1315	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1316	1316
1317		PORT_START /* 60 */
	1317	PORT_START_TAG("60") /* 60 */
1318	1318	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Upper Right") PORT_CODE(KEYCODE_9_PAD)
1319	1319	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1320	1320	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("Middle") PORT_CODE(KEYCODE_5_PAD)
r2864	r2865
1324	1324	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Play")
1325	1325	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1326	1326
1327		PORT_START /* 80 */
	1327	PORT_START_TAG("80") /* 80 */
1328	1328	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1329	1329
1330		UNUSED_ANALOG /* analog C */
1331		UNUSED_ANALOG /* analog D */
1332		UNUSED_ANALOG /* analog E */
1333		UNUSED_ANALOG /* analog F */
	1330	UNUSED_ANALOG("AN_C") /* analog C */
	1331	UNUSED_ANALOG("AN_D") /* analog D */
	1332	UNUSED_ANALOG("AN_E") /* analog E */
	1333	UNUSED_ANALOG("AN_F") /* analog F */
1334	1334	INPUT_PORTS_END
1335	1335
1336	1336
1337	1337	static INPUT_PORTS_START( hstennis )
1338		PORT_START /* 40 */
	1338	PORT_START_TAG("40") /* 40 */
1339	1339	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1340	1340	PORT_BIT( 0x06, IP_ACTIVE_LOW, IPT_UNUSED )
1341	1341	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Cabinet ))
r2864	r2865
1347	1347	PORT_BIT( 0x60, IP_ACTIVE_LOW, IPT_UNUSED )
1348	1348	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1349	1349
1350		PORT_START /* 60 */
	1350	PORT_START_TAG("60") /* 60 */
1351	1351	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
1352	1352	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P1 Soft") PORT_PLAYER(1)
1353	1353	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
r2864	r2865
1357	1357	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P1 Hard") PORT_PLAYER(1)
1358	1358	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1359	1359
1360		PORT_START /* 80 */
	1360	PORT_START_TAG("80") /* 80 */
1361	1361	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN4 )
1362	1362	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P2 Soft") PORT_PLAYER(2)
1363	1363	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
r2864	r2865
1367	1367	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P2 Hard") PORT_PLAYER(2)
1368	1368	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
1369	1369
1370		UNUSED_ANALOG /* analog C */
1371		UNUSED_ANALOG /* analog D */
1372		UNUSED_ANALOG /* analog E */
1373		UNUSED_ANALOG /* analog F */
	1370	UNUSED_ANALOG("AN_C") /* analog C */
	1371	UNUSED_ANALOG("AN_D") /* analog D */
	1372	UNUSED_ANALOG("AN_E") /* analog E */
	1373	UNUSED_ANALOG("AN_F") /* analog F */
1374	1374	INPUT_PORTS_END
1375	1375
1376	1376
1377	1377	static INPUT_PORTS_START( arlingtn )
1378		PORT_START /* 40 */
	1378	PORT_START_TAG("40") /* 40 */
1379	1379	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1380	1380	PORT_BIT( 0x06, IP_ACTIVE_LOW, IPT_UNUSED )
1381	1381	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown )) /* see code at e23c */
r2864	r2865
1384	1384	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
1385	1385	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1386	1386
1387		PORT_START /* 60 */
	1387	PORT_START_TAG("60") /* 60 */
1388	1388	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
1389	1389	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1390	1390	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Place")
r2864	r2865
1394	1394	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1395	1395	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1396	1396
1397		PORT_START /* 80 */
	1397	PORT_START_TAG("80") /* 80 */
1398	1398	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN4 )
1399	1399	PORT_BIT( 0x06, IP_ACTIVE_LOW, IPT_UNKNOWN )
1400	1400	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Show")
r2864	r2865
1403	1403	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1404	1404	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
1405	1405
1406		UNUSED_ANALOG /* analog C */
1407		UNUSED_ANALOG /* analog D */
1408		UNUSED_ANALOG /* analog E */
1409		UNUSED_ANALOG /* analog F */
	1406	UNUSED_ANALOG("AN_C") /* analog C */
	1407	UNUSED_ANALOG("AN_D") /* analog D */
	1408	UNUSED_ANALOG("AN_E") /* analog E */
	1409	UNUSED_ANALOG("AN_F") /* analog F */
1410	1410	INPUT_PORTS_END
1411	1411
1412	1412
1413	1413	static INPUT_PORTS_START( peggle )
1414		PORT_START /* 40 */
	1414	PORT_START_TAG("40") /* 40 */
1415	1415	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1416	1416	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNUSED )
1417	1417	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1418	1418
1419		PORT_START /* 60 */
	1419	PORT_START_TAG("60") /* 60 */
1420	1420	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
1421	1421	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1422	1422	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
r2864	r2865
1425	1425	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
1426	1426	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1427	1427
1428		PORT_START /* 80 */
	1428	PORT_START_TAG("80") /* 80 */
1429	1429	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN4 )
1430	1430	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNKNOWN )
1431	1431	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
1432	1432
1433		UNUSED_ANALOG /* analog C */
1434		UNUSED_ANALOG /* analog D */
1435		UNUSED_ANALOG /* analog E */
1436		UNUSED_ANALOG /* analog F */
	1433	UNUSED_ANALOG("AN_C") /* analog C */
	1434	UNUSED_ANALOG("AN_D") /* analog D */
	1435	UNUSED_ANALOG("AN_E") /* analog E */
	1436	UNUSED_ANALOG("AN_F") /* analog F */
1437	1437	INPUT_PORTS_END
1438	1438
1439	1439
1440	1440	static INPUT_PORTS_START( pegglet )
1441		PORT_START /* 40 */
	1441	PORT_START_TAG("40") /* 40 */
1442	1442	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1443	1443	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNUSED )
1444	1444	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1445	1445
1446		PORT_START /* 60 */
	1446	PORT_START_TAG("60") /* 60 */
1447	1447	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
1448	1448	PORT_BIT( 0x3e, IP_ACTIVE_LOW, IPT_UNKNOWN )
1449	1449	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
1450	1450	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1451	1451
1452		PORT_START /* 80 */
	1452	PORT_START_TAG("80") /* 80 */
1453	1453	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN4 )
1454	1454	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNKNOWN )
1455	1455	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
1456	1456
1457		UNUSED_ANALOG /* analog C */
	1457	UNUSED_ANALOG("AN_C") /* analog C */
1458	1458
1459		PORT_START /* analog D */
	1459	PORT_START_TAG("AN_D") /* analog D */
1460	1460	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_RESET PORT_PLAYER(1)
1461	1461
1462		UNUSED_ANALOG /* analog E */
1463		UNUSED_ANALOG /* analog F */
	1462	UNUSED_ANALOG("AN_E") /* analog E */
	1463	UNUSED_ANALOG("AN_F") /* analog F */
1464	1464	INPUT_PORTS_END
1465	1465
1466	1466
1467	1467	static INPUT_PORTS_START( neckneck )
1468		PORT_START /* 40 */
	1468	PORT_START_TAG("40") /* 40 */
1469	1469	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1470	1470	PORT_BIT( 0x06, IP_ACTIVE_LOW, IPT_UNUSED )
1471	1471	PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown )) /* see code at e23c */
r2864	r2865
1474	1474	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
1475	1475	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
1476	1476
1477		PORT_START /* 60 */
	1477	PORT_START_TAG("60") /* 60 */
1478	1478	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
1479	1479	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1480	1480	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Horse 3")
r2864	r2865
1484	1484	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1485	1485	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
1486	1486
1487		PORT_START /* 80 */
	1487	PORT_START_TAG("80") /* 80 */
1488	1488	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN4 )
1489	1489	PORT_BIT( 0x06, IP_ACTIVE_LOW, IPT_UNKNOWN )
1490	1490	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Horse 4")
r2864	r2865
1493	1493	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1494	1494	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
1495	1495
1496		UNUSED_ANALOG /* analog C */
1497		UNUSED_ANALOG /* analog D */
1498		UNUSED_ANALOG /* analog E */
1499		UNUSED_ANALOG /* analog F */
	1496	UNUSED_ANALOG("AN_C") /* analog C */
	1497	UNUSED_ANALOG("AN_D") /* analog D */
	1498	UNUSED_ANALOG("AN_E") /* analog E */
	1499	UNUSED_ANALOG("AN_F") /* analog F */
1500	1500	INPUT_PORTS_END
1501	1501
1502	1502
1503	1503	static INPUT_PORTS_START( rimrockn )
1504		PORT_START /* 40 */
	1504	PORT_START_TAG("40") /* 40 */
1505	1505	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1506	1506
1507		PORT_START /* 60 */
	1507	PORT_START_TAG("60") /* 60 */
1508	1508	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1509	1509	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
1510	1510	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
1514	1514	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1515	1515	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* input from sound board */
1516	1516
1517		PORT_START /* 80 */
	1517	PORT_START_TAG("80") /* 80 */
1518	1518	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1519	1519
1520		PORT_START /* special 161 */
	1520	PORT_START_TAG("161") /* special 161 */
1521	1521	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1522	1522	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P1 Pass") PORT_PLAYER(1)
1523	1523	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P1 Shoot") PORT_PLAYER(1)
r2864	r2865
1527	1527	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
1528	1528	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
1529	1529
1530		PORT_START /* special 162 */
	1530	PORT_START_TAG("162") /* special 162 */
1531	1531	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1532	1532	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P2 Pass") PORT_PLAYER(2)
1533	1533	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P2 Shoot") PORT_PLAYER(2)
r2864	r2865
1537	1537	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
1538	1538	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
1539	1539
1540		PORT_START /* special 163 */
	1540	PORT_START_TAG("163") /* special 163 */
1541	1541	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P3 Shoot") PORT_PLAYER(3)
1542	1542	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P3 Pass") PORT_PLAYER(3)
1543	1543	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1547	1547	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(3)
1548	1548	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START3 )
1549	1549
1550		PORT_START /* special 164 */
	1550	PORT_START_TAG("164") /* special 164 */
1551	1551	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P4 Shoot") PORT_PLAYER(4)
1552	1552	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P4 Pass") PORT_PLAYER(4)
1553	1553	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1557	1557	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(4)
1558	1558	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
1559	1559
1560		PORT_START /* special 165 */
	1560	PORT_START_TAG("165") /* special 165 */
1561	1561	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE2 )
1562	1562	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE3 )
1563	1563	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE4 )
r2864	r2865
1577	1577
1578	1578
1579	1579	static INPUT_PORTS_START( ninclown )
1580		PORT_START /* 40 */
	1580	PORT_START_TAG("40") /* 40 */
1581	1581	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE1 )
1582	1582	PORT_SERVICE_NO_TOGGLE( 0x0200, IP_ACTIVE_LOW )
1583	1583	PORT_BIT( 0x0c00, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1585	1585	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_COIN1 )
1586	1586	PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNKNOWN )
1587	1587
1588		PORT_START /* 60 */
	1588	PORT_START_TAG("60") /* 60 */
1589	1589	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("P1 Throw") PORT_PLAYER(1)
1590	1590	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START1 )
1591	1591	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
r2864	r2865
1595	1595	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P1 Kick") PORT_PLAYER(1)
1596	1596	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P1 Punch") PORT_PLAYER(1)
1597	1597
1598		PORT_START /* 80 */
	1598	PORT_START_TAG("80") /* 80 */
1599	1599	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("P2 Throw") PORT_PLAYER(2)
1600	1600	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
1601	1601	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
r2864	r2865
1605	1605	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P2 Kick") PORT_PLAYER(2)
1606	1606	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P2 Punch") PORT_PLAYER(2)
1607	1607
1608		UNUSED_ANALOG /* analog C */
1609		UNUSED_ANALOG /* analog D */
1610		UNUSED_ANALOG /* analog E */
1611		UNUSED_ANALOG /* analog F */
	1608	UNUSED_ANALOG("AN_C") /* analog C */
	1609	UNUSED_ANALOG("AN_D") /* analog D */
	1610	UNUSED_ANALOG("AN_E") /* analog E */
	1611	UNUSED_ANALOG("AN_F") /* analog F */
1612	1612	INPUT_PORTS_END
1613	1613
1614	1614
1615	1615	static INPUT_PORTS_START( gtg2 )
1616		PORT_START /* 40 */
	1616	PORT_START_TAG("40") /* 40 */
1617	1617	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1618	1618	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
1619	1619	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
1624	1624	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ))
1625	1625	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
1626	1626
1627		PORT_START /* 60 */
	1627	PORT_START_TAG("60") /* 60 */
1628	1628	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
1629	1629	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P1 Face Right") PORT_PLAYER(1)
1630	1630	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P1 Face Left") PORT_PLAYER(1)
1631	1631	PORT_BIT( 0x78, IP_ACTIVE_LOW, IPT_UNUSED )
1632	1632	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
1633	1633
1634		PORT_START /* 80 */
	1634	PORT_START_TAG("80") /* 80 */
1635	1635	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
1636	1636	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P2 Face Right") PORT_COCKTAIL PORT_PLAYER(2)
1637	1637	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P2 Face Left") PORT_COCKTAIL PORT_PLAYER(2)
1638	1638	PORT_BIT( 0x78, IP_ACTIVE_LOW, IPT_UNUSED )
1639	1639	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
1640	1640
1641		PORT_START /* analog C */
	1641	PORT_START_TAG("AN_C") /* analog C */
1642	1642	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_PLAYER(1)
1643	1643
1644		PORT_START /* analog D */
	1644	PORT_START_TAG("AN_D") /* analog D */
1645	1645	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_REVERSE PORT_PLAYER(1)
1646	1646
1647		PORT_START /* analog E */
	1647	PORT_START_TAG("AN_E") /* analog E */
1648	1648	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_COCKTAIL PORT_PLAYER(2)
1649	1649
1650		PORT_START /* analog F */
	1650	PORT_START_TAG("AN_F") /* analog F */
1651	1651	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_RESET PORT_REVERSE PORT_COCKTAIL PORT_PLAYER(2)
1652	1652	INPUT_PORTS_END
1653	1653
1654	1654
1655	1655	static INPUT_PORTS_START( gpgolf )
1656		PORT_START /* 40 */
	1656	PORT_START_TAG("40") /* 40 */
1657	1657	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1658	1658	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
1659	1659	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
1664	1664	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ))
1665	1665	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
1666	1666
1667		PORT_START /* 60 */
1668
	1667	PORT_START_TAG("60") /* 60 */
1669	1668	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
1670	1669	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
1671	1670	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P1 Swing") PORT_PLAYER(1)
r2864	r2865
1675	1674	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
1676	1675	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
1677	1676
1678		PORT_START /* 80 */
	1677	PORT_START_TAG("80") /* 80 */
1679	1678	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1680	1679
1681		UNUSED_ANALOG /* analog C */
1682		UNUSED_ANALOG /* analog D */
1683		UNUSED_ANALOG /* analog E */
1684		UNUSED_ANALOG /* analog F */
	1680	UNUSED_ANALOG("AN_C") /* analog C */
	1681	UNUSED_ANALOG("AN_D") /* analog D */
	1682	UNUSED_ANALOG("AN_E") /* analog E */
	1683	UNUSED_ANALOG("AN_F") /* analog F */
1685	1684	INPUT_PORTS_END
1686	1685
1687	1686

src/mame/drivers/gstriker.c
r2864	r2865
345	345	AM_RANGE(0x08, 0x08) AM_WRITE(gs_sh_pending_command_clear_w)
346	346	ADDRESS_MAP_END
347	347
	348
	349
	350	static ADDRESS_MAP_START( vgoal_map, ADDRESS_SPACE_PROGRAM, 16 )
	351	AM_RANGE(0x000000, 0x0fffff) AM_ROM
	352	AM_RANGE(0x100000, 0x103fff) AM_RAM AM_WRITE(MB60553_0_vram_w) AM_BASE(&MB60553_0_vram)
	353	AM_RANGE(0x140000, 0x141fff) AM_RAM AM_BASE(&CG10103_0_vram)
	354	AM_RANGE(0x180000, 0x180fff) AM_RAM AM_WRITE(VS920A_0_vram_w) AM_BASE(&VS920A_0_vram)
	355	AM_RANGE(0x181000, 0x181fff) AM_RAM AM_BASE(&gstriker_lineram)
	356	AM_RANGE(0x1c0000, 0x1c4fff) AM_RAM AM_WRITE(paletteram16_xRRRRRGGGGGBBBBB_word_w) AM_BASE(&paletteram16)
	357	AM_RANGE(0x200000, 0x20000f) AM_WRITE(MB60553_0_regs_w)
	358	AM_RANGE(0x200040, 0x20005f) AM_RAM AM_BASE(&gs_mixer_regs)
	359
	360	AM_RANGE(0x200080, 0x200081) AM_READ(input_port_1_word_r)
	361	AM_RANGE(0x200082, 0x200083) AM_READ(input_port_2_word_r)
	362	AM_RANGE(0x200084, 0x200085) AM_READ(input_port_0_word_r)
	363	AM_RANGE(0x200086, 0x200087) AM_READ(input_port_3_word_r)
	364	AM_RANGE(0x200088, 0x200089) AM_READ(input_port_4_word_r)
	365	AM_RANGE(0x20008e, 0x20008f) AM_READ(dmmy_8f)
	366
	367	AM_RANGE(0x2000a0, 0x2000a1) AM_WRITE(sound_command_w)
	368	AM_RANGE(0xffc000, 0xffffff) AM_RAM AM_BASE(&work_ram)
	369	ADDRESS_MAP_END
	370
348	371	/* INPUT PORTS ***********************************************************/
349	372
350		static INPUT_PORTS_START( gstriker )
	373	static INPUT_PORTS_START( gstriker_generic )
351	374	PORT_START
352	375	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
353	376	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
r2864	r2865
370	393	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1) // "Spare"
371	394	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
372	395
373		PORT_START
	396	PORT_START /* IN2 */
374	397	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
375	398	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
376	399	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
380	403	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
381	404	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2) // "Spare"
382	405	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
	406	INPUT_PORTS_END
383	407
384		PORT_START
	408	static INPUT_PORTS_START( gstriker )
	409	PORT_INCLUDE( gstriker_generic )
	410
	411	PORT_START /* IN3 */
385	412	PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Coin_A ) )
386	413	PORT_DIPSETTING( 0x0001, DEF_STR( 3C_1C ) )
387	414	PORT_DIPSETTING( 0x0002, DEF_STR( 2C_1C ) )
r2864	r2865
406	433	PORT_DIPSETTING( 0x0080, "2" )
407	434	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
408	435
409		PORT_START
	436	PORT_START /* IN4 */
410	437	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Difficulty ) )
411	438	PORT_DIPSETTING( 0x0001, DEF_STR( Normal ) )
412	439	PORT_DIPSETTING( 0x0000, DEF_STR( Hard ) )
r2864	r2865
430	457	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
431	458	INPUT_PORTS_END
432	459
	460	static INPUT_PORTS_START( twrldc94 )
	461	PORT_INCLUDE( gstriker_generic )
	462
	463	PORT_START /* IN3 */
	464	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )
	465	PORT_DIPSETTING( 0x0000, DEF_STR( 4C_1C ) )
	466	PORT_DIPSETTING( 0x0001, DEF_STR( 3C_1C ) )
	467	PORT_DIPSETTING( 0x0002, DEF_STR( 2C_1C ) )
	468	PORT_DIPSETTING( 0x0007, DEF_STR( 1C_1C ) )
	469	PORT_DIPSETTING( 0x0006, DEF_STR( 1C_2C ) )
	470	PORT_DIPSETTING( 0x0005, DEF_STR( 1C_3C ) )
	471	PORT_DIPSETTING( 0x0004, DEF_STR( 1C_4C ) )
	472	PORT_DIPSETTING( 0x0003, DEF_STR( 1C_6C ) )
	473
	474	PORT_DIPNAME( 0x0038, 0x0038, DEF_STR( Coin_B ) )
	475	PORT_DIPSETTING( 0x0000, DEF_STR( 4C_1C ) )
	476	PORT_DIPSETTING( 0x0008, DEF_STR( 3C_1C ) )
	477	PORT_DIPSETTING( 0x0010, DEF_STR( 2C_1C ) )
	478	PORT_DIPSETTING( 0x0038, DEF_STR( 1C_1C ) )
	479	PORT_DIPSETTING( 0x0030, DEF_STR( 1C_2C ) )
	480	PORT_DIPSETTING( 0x0028, DEF_STR( 1C_3C ) )
	481	PORT_DIPSETTING( 0x0020, DEF_STR( 1C_4C ) )
	482	PORT_DIPSETTING( 0x0018, DEF_STR( 1C_6C ) )
	483
	484	PORT_DIPNAME( 0x00c0, 0x00c0, "Play Time" )
	485	PORT_DIPSETTING( 0x0000, "P v CPU 1:00, P v P 1:30" )
	486	PORT_DIPSETTING( 0x00c0, "P v CPU 1:30, P v P 2:00" )
	487	PORT_DIPSETTING( 0x0040, "P v CPU 2:00, P v P 2:30" )
	488	PORT_DIPSETTING( 0x0080, "P v CPU 2:30, P v P 3:00" )
	489	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
	490
	491	PORT_START /* IN4 */
	492	PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Difficulty ) )
	493	PORT_DIPSETTING( 0x0000, DEF_STR( Very_Hard ) )
	494	PORT_DIPSETTING( 0x0001, DEF_STR( Hard ) )
	495	PORT_DIPSETTING( 0x0002, DEF_STR( Easy ) )
	496	PORT_DIPSETTING( 0x0003, DEF_STR( Normal ) )
	497
	498	PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Demo_Sounds ) )
	499	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
	500	PORT_DIPSETTING( 0x0004, DEF_STR( On ) )
	501	PORT_DIPNAME( 0x0008, 0x0008, "Show Configuration" )
	502	PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
	503	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	504	PORT_DIPNAME( 0x0010, 0x0010, "Countdown" )
	505	PORT_DIPSETTING( 0x0010, "54 sec" )
	506	PORT_DIPSETTING( 0x0000, "60 sec" )
	507	PORT_DIPNAME( 0x0020, 0x0020, "Start credit" )
	508	PORT_DIPSETTING( 0x0020, "1" )
	509	PORT_DIPSETTING( 0x0000, "2" )
	510	PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unused ) )
	511	PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
	512	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	513	PORT_SERVICE( 0x0080, IP_ACTIVE_LOW )
	514	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
	515	INPUT_PORTS_END
	516
	517	static INPUT_PORTS_START( vgoalsoc )
	518	PORT_INCLUDE( gstriker_generic )
	519
	520	PORT_START /* IN3 */
	521	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )
	522	PORT_DIPSETTING( 0x0000, DEF_STR( 4C_1C ) )
	523	PORT_DIPSETTING( 0x0001, DEF_STR( 3C_1C ) )
	524	PORT_DIPSETTING( 0x0002, DEF_STR( 2C_1C ) )
	525	PORT_DIPSETTING( 0x0007, DEF_STR( 1C_1C ) )
	526	PORT_DIPSETTING( 0x0006, DEF_STR( 1C_2C ) )
	527	PORT_DIPSETTING( 0x0005, DEF_STR( 1C_3C ) )
	528	PORT_DIPSETTING( 0x0004, DEF_STR( 1C_4C ) )
	529	PORT_DIPSETTING( 0x0003, DEF_STR( 1C_6C ) )
	530
	531	PORT_DIPNAME( 0x0038, 0x0038, DEF_STR( Coin_B ) )
	532	PORT_DIPSETTING( 0x0000, DEF_STR( 4C_1C ) )
	533	PORT_DIPSETTING( 0x0008, DEF_STR( 3C_1C ) )
	534	PORT_DIPSETTING( 0x0010, DEF_STR( 2C_1C ) )
	535	PORT_DIPSETTING( 0x0038, DEF_STR( 1C_1C ) )
	536	PORT_DIPSETTING( 0x0030, DEF_STR( 1C_2C ) )
	537	PORT_DIPSETTING( 0x0028, DEF_STR( 1C_3C ) )
	538	PORT_DIPSETTING( 0x0020, DEF_STR( 1C_4C ) )
	539	PORT_DIPSETTING( 0x0018, DEF_STR( 1C_6C ) )
	540
	541	PORT_DIPNAME( 0x00c0, 0x00c0, DEF_STR (Unknown) ) // Probably difficulty
	542	PORT_DIPSETTING( 0x0080, "A" )
	543	PORT_DIPSETTING( 0x00c0, "B" )
	544	PORT_DIPSETTING( 0x0040, "C" )
	545	PORT_DIPSETTING( 0x0000, "D" )
	546	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
	547
	548	PORT_START /* IN4 */
	549	PORT_DIPNAME( 0x0003, 0x0003, "Player VS CPU Time" ) // no coperative
	550	PORT_DIPSETTING( 0x0002, "1:00" )
	551	PORT_DIPSETTING( 0x0003, "1:30" )
	552	PORT_DIPSETTING( 0x0001, "2:00" )
	553	PORT_DIPSETTING( 0x0000, "2:30" )
	554	PORT_DIPNAME( 0x000c, 0x000c, "Player VS Player Time" )
	555	PORT_DIPSETTING( 0x0008, "1:30" )
	556	PORT_DIPSETTING( 0x000c, "2:00" )
	557	PORT_DIPSETTING( 0x0004, "2:30" )
	558	PORT_DIPSETTING( 0x0000, "3:00" )
	559	PORT_DIPNAME( 0x0010, 0x0010, "Countdown" )
	560	PORT_DIPSETTING( 0x0010, "54 sec" )
	561	PORT_DIPSETTING( 0x0000, "60 sec" )
	562	PORT_DIPNAME( 0x0020, 0x0000, DEF_STR( Demo_Sounds ) )
	563	PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
	564	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	565	PORT_DIPNAME( 0x0040, 0x0040, "DWS2:6" ) // hangs at POST
	566	PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
	567	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	568	PORT_DIPNAME( 0x0080, 0x0080, "Start credit" )
	569	PORT_DIPSETTING( 0x0080, "1" )
	570	PORT_DIPSETTING( 0x0000, "2" )
	571	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
	572	INPUT_PORTS_END
	573
433	574	/* MACHINE DRIVER ********************************************************/
434	575
435	576	static MACHINE_DRIVER_START( gstriker )
r2864	r2865
472	613	MDRV_VIDEO_START( twrldc94 )
473	614	MACHINE_DRIVER_END
474	615
	616
	617	static MACHINE_DRIVER_START( vgoal )
	618	MDRV_CPU_ADD(M68000, 16000000)
	619	MDRV_CPU_PROGRAM_MAP(vgoal_map,0)
	620	MDRV_CPU_VBLANK_INT("main", irq1_line_hold)
	621
	622	MDRV_CPU_ADD(Z80,8000000/2)
	623	/* audio CPU / / 4 MHz ??? */
	624	MDRV_CPU_PROGRAM_MAP(sound_readmem,sound_writemem)
	625	MDRV_CPU_IO_MAP(sound_readport,sound_writeport)
	626
	627	MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK)
	628
	629	MDRV_SCREEN_ADD("main", RASTER)
	630	MDRV_SCREEN_REFRESH_RATE(60)
	631	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(5000) /* hand-tuned, it needs a bit */)
	632	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
	633	MDRV_SCREEN_SIZE(648, 648)
	634	MDRV_SCREEN_VISIBLE_AREA(08, 408-1, 08, 288-1)
	635
	636	MDRV_GFXDECODE(gstriker)
	637	MDRV_PALETTE_LENGTH(0x2000)
	638
	639	MDRV_VIDEO_START(vgoalsoc)
	640	MDRV_VIDEO_UPDATE(gstriker)
	641
	642	MDRV_SPEAKER_STANDARD_STEREO("left", "right")
	643
	644	MDRV_SOUND_ADD(YM2610, 8000000)
	645	MDRV_SOUND_CONFIG(ym2610_interface)
	646	MDRV_SOUND_ROUTE(0, "left", 0.25)
	647	MDRV_SOUND_ROUTE(0, "right", 0.25)
	648	MDRV_SOUND_ROUTE(1, "left", 1.0)
	649	MDRV_SOUND_ROUTE(2, "right", 1.0)
	650	MACHINE_DRIVER_END
	651
	652
	653
	654
475	655	/* ROM LOADING ***********************************************************/
476	656
477	657	ROM_START( gstriker )
r2864	r2865
632	812	work_ram[0x000/2] = (_num_ & 0xffff0000) >> 16;\
633	813	work_ram[0x002/2] = (_num_ & 0x0000ffff) >> 0;
634	814
	815	static int gametype = 0;
	816	static UINT16 mcu_data = 0;
	817
635	818	static WRITE16_HANDLER( twrldc94_mcu_w )
636	819	{
637		switch(data)
	820	mcu_data = data;
	821	}
	822
	823	static READ16_HANDLER( twrldc94_mcu_r )
	824	{
	825	return mcu_data;
	826	}
	827
	828	static UINT16 prot_reg[2] = {0,0}; // current,last
	829	static WRITE16_HANDLER( twrldc94_prot_reg_w )
	830	{
	831	prot_reg[1] = prot_reg[0];
	832	prot_reg[0] = data;
	833
	834	if( ((prot_reg[1] & 2) == 2) && ((prot_reg[0] & 2) == 0) )
638	835	{
639		/P.O.S.T. / Test Mode/
640		case 0x53: PC(0x00000a4c); break;
641		/Time Up/
642		case 0x68: break;
643		/Title Screen/
644		case 0x69: break;
645		/Gameplay / Attract mode/
646		case 0x6b: PC(0x00000746); break;
647		/(after the P.O.S.T.)/
648		case 0x6e: PC(0x00000746); break;/WRONG?/
649		default: popmessage("Unknown MCU CMD %04x",data);
	836	switch( gametype )
	837	{
	838	case 1:
	839	switch(mcu_data)
	840	{
	841	#define NULL_SUB 0x0000828E
	842	case 0x53: PC(0x0000a4c); break; // boot -> main loop
	843
	844	/*
	845	68 and 62 could be sprite or sound changes, or ?
	846	68(),61()
	847	if( !carry )
	848	{
	849	68(),65()
	850	}
	851	else
	852	{
	853	62(),72()
	854	}
	855	*/
	856	case 0x68: PC(NULL_SUB); break; // time up doesn't block long enough for pk shootout
	857	case 0x61: PC(0x0003AF4); break; // after time up, pk shootout???
	858	case 0x65: PC(0x0003F26); break;
	859
	860	// 62->72
	861	case 0x62: PC(NULL_SUB); break; // after lose shootout, continue ???
	862	case 0x72: PC(0x000409E); break; // game over
	863
	864	/*
	865	Attract mode is pre programmed loop called from main
	866	that runs through top11->demoplay
	867	(NOTE: sprites for demo play are being drawn at 0x141000,
	868	this address is used in a few places, and there's some activity
	869	further up around 0x1410b0.)
	870
	871	The loop begins with three prot calls:
	872	one always present (may be diversion to 0x0010DC8 unreachable code
	873	and prot cases 6a,79,6f) and two alternating calls.
	874	The loop is 6e -> [6b\|69] -> top11 -> (4 segment)playdemo
	875
	876	These are the likely suspects for attract mode:
	877	0x0010E28 red tecmo on black
	878	0x0010EEC bouncing ball and player with game title
	879	0x00117A2 single segment demo play with player sprites at 0x140000
	880	0x001120A sliding display of player photos
	881	0x0010DC8 unreachable code at end of attract loop with cases 6a,79,6f
	882
	883	*/
	884	case 0x6e: PC(0x0010E28); break; // loop
	885	case 0x6b: PC(0x0010EEC); break; // attract even
	886	case 0x69: PC(0x001120A); break; // attract odd
	887
	888	// In "continue" screen
	889	// if( w@FFE078 & 80) 75
	890	// *** after 75 beq
	891	case 0x75: PC(NULL_SUB); break;
	892
	893	// unreachable code at end of attract loop 6a->79->6f
	894	case 0x6a: PC(NULL_SUB); break;
	895	case 0x79: PC(NULL_SUB); break;
	896	case 0x6f: PC(NULL_SUB); break;
	897
	898	default:
	899	popmessage("Unknown MCU CMD %04x",mcu_data);
	900	PC(NULL_SUB);
	901	break;
	902	}
	903	break;
	904
	905	case 2:
	906	switch(mcu_data)
	907	{
	908	case 0x53: PC(0x00000a5c); break; // POST
	909
	910	default:
	911	popmessage("Unknown MCU CMD %04x",mcu_data);
	912	PC(NULL_SUB);
	913	break;
	914	}
	915	break;
	916
	917
	918	case 3:
	919	switch(mcu_data)
	920	{
	921	case 0x33: PC(0x00063416); break; // *after game over, is this right?
	922	case 0x3d: PC(0x0006275C); break; // after sprite ram init, team select
	923	case 0x42: PC(0x0006274E); break; // after press start, init sprite ram
	924	case 0x43: PC(0x0006a000); break; // POST
	925	case 0x50: PC(0x00001900); break; // enter main loop
	926	case 0x65: PC(0x0006532C); break; // results
	927	case 0x70: PC(0x00063416); break; // *attract loop ends, what should happen after "standings" display?
	928	case 0x74: PC(0x000650D8); break; // after time up, show scores and continue
	929	case 0x79: PC(0x0006072E); break; // after select, start match
	930
	931	default:
	932	popmessage("Unknown MCU CMD %04x",mcu_data);
	933	PC(0x00000586); // rts
	934	break;
	935	}
	936	break;
	937	}
650	938	}
651	939	}
652	940
653		static DRIVER_INIT( twrldc94 )
	941	static READ16_HANDLER( twrldc94_prot_reg_r )
654	942	{
	943	// bit 0 is for debugging vgoalsoc?
	944	// Setting it results in a hang with a digit displayed on screen
	945	// For twrldc94, it just disables sound.
	946
	947	return prot_reg[0];
	948	}
	949
	950	/*
	951	vgoalsoc uses a set of programmable timers.
	952	There is a code implementation for at 00065F00 that appears to have
	953	been RTSed out.
	954	I'm guessing it was replaced with an external implementation.
	955
	956	This does indicate though that the protection could be performing
	957	other more complicated functions.
	958
	959	The tick count is usually set to 0x3c => it's driven off vblank?
	960	*/
	961	//work_ram[ (0xffe900 - 0xffc00) ]
	962	#define COUNTER1_ENABLE work_ram[0x2900/2] >> 8
	963	#define COUNTER2_ENABLE (work_ram[0x2900/2] & 0xff)
	964	#define TICK_1 work_ram[0x2908/2]
	965	#define TICKCOUNT_1 work_ram[0x290a/2]
	966	#define TICK_2 work_ram[0x290c/2]
	967	#define TICKCOUNT_3 work_ram[0x290e/2]
	968	#define COUNTER_1 work_ram[0x2928/2]
	969	#define COUNTER_2 work_ram[0x292a/2]
	970	static READ16_HANDLER( vbl_toggle_r )
	971	{
	972	return 0xff;
	973	}
	974
	975	static WRITE16_HANDLER( vbl_toggle_w )
	976	{
	977	if( COUNTER1_ENABLE == 1 )
	978	{
	979	TICK_1 = (TICK_1 - 1) & 0xff; // 8bit
	980	if( TICK_1 <= 0 )
	981	{
	982	TICK_1 = TICKCOUNT_1;
	983	COUNTER_1 = (COUNTER_1 - 1);// & 0xff; has to be 16bit for continue timer.
	984	}
	985	}
	986
	987	if( COUNTER2_ENABLE == 2 )
	988	{
	989	TICK_2 = (TICK_2 - 1) & 0xff;
	990	if( TICK_2 <= 0 )
	991	{
	992	TICK_2 = TICKCOUNT_3;
	993	COUNTER_2 = (COUNTER_2 - 1);// & 0xff;
	994	}
	995	}
	996	}
	997
	998	static void mcu_init( running_machine *machine )
	999	{
655	1000	memory_install_write16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x20008a, 0x20008b, 0, 0, twrldc94_mcu_w);
	1001	memory_install_read16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x20008a, 0x20008b, 0, 0, twrldc94_mcu_r);
	1002
	1003	memory_install_write16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x20008e, 0x20008f, 0, 0, twrldc94_prot_reg_w);
	1004	memory_install_read16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x20008e, 0x20008f, 0, 0, twrldc94_prot_reg_r);
656	1005	}
657	1006
	1007	static DRIVER_INIT( twrldc94 )
	1008	{
	1009	gametype = 1;
	1010	mcu_init( machine );
	1011	}
	1012
	1013	static DRIVER_INIT( twrldc94a )
	1014	{
	1015	gametype = 2;
	1016	mcu_init( machine );
	1017	}
	1018
	1019	static DRIVER_INIT( vgoalsoc )
	1020	{
	1021	gametype = 3;
	1022	mcu_init( machine );
	1023
	1024	memory_install_write16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x200090, 0x200091, 0, 0, vbl_toggle_w); // vblank toggle
	1025	memory_install_read16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x200090, 0x200091, 0, 0, vbl_toggle_r);
	1026	}
	1027
658	1028	/* GAME DRIVERS **********************************************************/
659	1029
660	1030	GAME( 1993, gstriker, 0, gstriker, gstriker, 0, ROT0, "Human", "Grand Striker", GAME_IMPERFECT_GRAPHICS )
661	1031
662	1032	/* Similar, but not identical hardware, appear to be protected by an MCU :-( */
663		GAME( 199?, vgoalsoc, 0, gstriker, gstriker, 0, ROT0, "Tecmo", "V Goal Soccer (set 1)", GAME_NOT_WORKING )
664		GAME( 199?, vgoalsca, vgoalsoc, gstriker, gstriker, 0, ROT0, "Tecmo", "V Goal Soccer (set 2)", GAME_NOT_WORKING )
665		GAME( 1994, twrldc94, 0, twrldc94, gstriker, twrldc94, ROT0, "Tecmo", "Tecmo World Cup '94 (set 1)", GAME_NOT_WORKING \| GAME_UNEMULATED_PROTECTION \| GAME_IMPERFECT_GRAPHICS )
666		GAME( 1994, twrdc94a, twrldc94, twrldc94, gstriker, twrldc94, ROT0, "Tecmo", "Tecmo World Cup '94 (set 2)", GAME_NOT_WORKING \| GAME_UNEMULATED_PROTECTION \| GAME_IMPERFECT_GRAPHICS )
	1033	GAME( 199?, vgoalsoc, 0, vgoal, vgoalsoc, vgoalsoc, ROT0, "Tecmo", "V Goal Soccer (set 1)", GAME_NOT_WORKING )
	1034	GAME( 199?, vgoalsca, vgoalsoc, vgoal, vgoalsoc, vgoalsoc, ROT0, "Tecmo", "V Goal Soccer (set 2)", GAME_NOT_WORKING )
	1035	GAME( 1994, twrldc94, 0, twrldc94, twrldc94, twrldc94, ROT0, "Tecmo", "Tecmo World Cup '94 (set 1)", GAME_NOT_WORKING \| GAME_UNEMULATED_PROTECTION \| GAME_IMPERFECT_GRAPHICS )
	1036	GAME( 1994, twrdc94a, twrldc94, twrldc94, twrldc94, twrldc94a, ROT0, "Tecmo", "Tecmo World Cup '94 (set 2)", GAME_NOT_WORKING \| GAME_UNEMULATED_PROTECTION \| GAME_IMPERFECT_GRAPHICS )

src/mame/drivers/flstory.c
r2864	r2865
85	85	AM_RANGE(0xd400, 0xd400) AM_READWRITE(from_snd_r, sound_command_w)
86	86	AM_RANGE(0xd401, 0xd401) AM_READ(snd_flag_r)
87	87	AM_RANGE(0xd403, 0xd403) AM_NOP /* unknown */
88		AM_RANGE(0xd800, 0xd800) AM_READ(input_port_0_r)
89		AM_RANGE(0xd801, 0xd801) AM_READ(input_port_1_r)
90		AM_RANGE(0xd802, 0xd802) AM_READ(input_port_2_r)
91		AM_RANGE(0xd803, 0xd803) AM_READ(input_port_3_r)
92		AM_RANGE(0xd804, 0xd804) AM_READ(input_port_4_r)
	88	AM_RANGE(0xd800, 0xd800) AM_READ_PORT("DSW0")
	89	AM_RANGE(0xd801, 0xd801) AM_READ_PORT("DSW1")
	90	AM_RANGE(0xd802, 0xd802) AM_READ_PORT("IN0")
	91	AM_RANGE(0xd803, 0xd803) AM_READ_PORT("IN1")
	92	AM_RANGE(0xd804, 0xd804) AM_READ_PORT("IN2")
93	93	AM_RANGE(0xd805, 0xd805) AM_READ(flstory_mcu_status_r)
94		AM_RANGE(0xd806, 0xd806) AM_READ~~(input~~_~~port_5_r~~)
	94	AM_RANGE(0xd806, 0xd806) AM_READ_PORT("IN3")
95	95	// AM_RANGE(0xda00, 0xda00) AM_WRITE(SMH_RAM)
96	96	AM_RANGE(0xdc00, 0xdc9f) AM_RAM AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
97	97	AM_RANGE(0xdca0, 0xdcbf) AM_RAM_WRITE(flstory_scrlram_w) AM_BASE(&flstory_scrlram)
r2864	r2865
111	111	AM_RANGE(0xd400, 0xd400) AM_READWRITE(from_snd_r, sound_command_w)
112	112	AM_RANGE(0xd401, 0xd401) AM_READ(snd_flag_r)
113	113	AM_RANGE(0xd403, 0xd403) AM_NOP /* unknown */
114		AM_RANGE(0xd800, 0xd800) AM_READ(input_port_0_r)
115		AM_RANGE(0xd801, 0xd801) AM_READ(input_port_1_r)
116		AM_RANGE(0xd802, 0xd802) AM_READ(input_port_2_r)
117		AM_RANGE(0xd803, 0xd803) AM_READ(input_port_3_r)
118		AM_RANGE(0xd804, 0xd804) AM_READ(input_port_4_r)
	114	AM_RANGE(0xd800, 0xd800) AM_READ_PORT("DSW0")
	115	AM_RANGE(0xd801, 0xd801) AM_READ_PORT("DSW1")
	116	AM_RANGE(0xd802, 0xd802) AM_READ_PORT("DSW2")
	117	AM_RANGE(0xd803, 0xd803) AM_READ_PORT("IN0")
	118	AM_RANGE(0xd804, 0xd804) AM_READ_PORT("IN1")
119	119	AM_RANGE(0xd805, 0xd805) AM_READ(onna34ro_mcu_status_r)
120		AM_RANGE(0xd806, 0xd806) AM_READ~~(input~~_~~port_5_r~~)
	120	AM_RANGE(0xd806, 0xd806) AM_READ_PORT("IN2")
121	121	// AM_RANGE(0xda00, 0xda00) AM_WRITE(SMH_RAM)
122	122	AM_RANGE(0xdc00, 0xdc9f) AM_RAM AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
123	123	AM_RANGE(0xdca0, 0xdcbf) AM_RAM_WRITE(flstory_scrlram_w) AM_BASE(&flstory_scrlram)
r2864	r2865
129	129
130	130	static READ8_HANDLER( victnine_port_5_r )
131	131	{
132		return (victnine_mcu_status_r(machine,0) & 3) \| (input_port_read~~_indexed~~(machine, 5) & ~3);
	132	return (victnine_mcu_status_r(machine,0) & 3) \| (input_port_read(machine, "IN2") & ~3);
133	133	}
134	134
135	135	static ADDRESS_MAP_START( victnine_map, ADDRESS_SPACE_PROGRAM, 8 )
r2864	r2865
142	142	AM_RANGE(0xd400, 0xd400) AM_READWRITE(from_snd_r, sound_command_w)
143	143	AM_RANGE(0xd401, 0xd401) AM_READ(snd_flag_r)
144	144	AM_RANGE(0xd403, 0xd403) AM_READNOP /* unknown */
145		AM_RANGE(0xd800, 0xd800) AM_READ(input_port_0_r)
146		AM_RANGE(0xd801, 0xd801) AM_READ(input_port_1_r)
147		AM_RANGE(0xd802, 0xd802) AM_READ(input_port_2_r)
148		AM_RANGE(0xd803, 0xd803) AM_READ(input_port_3_r)
149		AM_RANGE(0xd804, 0xd804) AM_READ(input_port_4_r)
	145	AM_RANGE(0xd800, 0xd800) AM_READ_PORT("DSW0")
	146	AM_RANGE(0xd801, 0xd801) AM_READ_PORT("DSW1")
	147	AM_RANGE(0xd802, 0xd802) AM_READ_PORT("DSW2")
	148	AM_RANGE(0xd803, 0xd803) AM_READ_PORT("IN0")
	149	AM_RANGE(0xd804, 0xd804) AM_READ_PORT("IN1")
150	150	AM_RANGE(0xd805, 0xd805) AM_READ(victnine_port_5_r)
151		AM_RANGE(0xd806, 0xd806) AM_READ(input_port_6_r)
152		AM_RANGE(0xd807, 0xd807) AM_READ(input_port_7_r)
	151	AM_RANGE(0xd806, 0xd806) AM_READ_PORT("IN3")
	152	AM_RANGE(0xd807, 0xd807) AM_READ_PORT("IN4")
153	153	// AM_RANGE(0xda00, 0xda00) AM_WRITE(SMH_RAM)
154	154	AM_RANGE(0xdc00, 0xdc9f) AM_RAM AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
155	155	AM_RANGE(0xdca0, 0xdcbf) AM_RAM_WRITE(flstory_scrlram_w) AM_BASE(&flstory_scrlram)

src/mame/drivers/f-32.c
r2864	r2865
98	98	if ((activecpu_get_pc() == 0x000379de) \|\|
99	99	(activecpu_get_pc() == 0x000379cc) ) activecpu_adjust_icount(-100);
100	100	//else printf("PC %08x\n", activecpu_get_pc() );
101		return input_port_read~~_indexed~~(machine, 1);
	101	return input_port_read(machine, "IN1");
102	102	}
103	103
104	104
r2864	r2865
118	118
119	119
120	120	static INPUT_PORTS_START( mosaicf2 )
121		PORT_START
	121	PORT_START_TAG("IN0")
122	122	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNUSED )
123	123	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
124	124	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
r2864	r2865
130	130	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_START1 )
131	131	PORT_BIT( 0xff000000, IP_ACTIVE_LOW, IPT_UNUSED )
132	132
133		PORT_START
	133	PORT_START_TAG("IN1")
134	134	PORT_BIT( 0x000000ff, IP_ACTIVE_LOW, IPT_UNUSED )
135	135	PORT_BIT( 0x00000100, IP_ACTIVE_LOW, IPT_COIN1 )
136	136	PORT_BIT( 0x00000200, IP_ACTIVE_LOW, IPT_COIN2 )

src/mame/drivers/atetris.c
r2864	r2865
493	493
494	494	static DRIVER_INIT( atetris )
495	495	{
496		slapstic_init(101);
	496	slapstic_init(machine, 101);
497	497	slapstic_source = &memory_region(REGION_CPU1)[0x10000];
498	498	slapstic_base = &memory_region(REGION_CPU1)[0x04000];
499	499	}

src/mame/drivers/model2.c
r2864	r2865
307	307	model2_timerrun[offset] = 1;
308	308	}
309	309
310		static void model2_timer_exp(int tnum, int bit)
	310	static void model2_timer_exp(running_machine *machine, int tnum, int bit)
311	311	{
312	312	timer_adjust_oneshot(model2_timers[tnum], attotime_never, 0);
313	313
314	314	model2_intreq \|= (1<<bit);
315	315	if (model2_intena & (1<<bit))
316	316	{
317		cpunum_set_input_line(Machine, 0, I960_IRQ2, ASSERT_LINE);
	317	cpunum_set_input_line(machine, 0, I960_IRQ2, ASSERT_LINE);
318	318	}
319	319
320	320	model2_timervals[tnum] = 0;
321	321	model2_timerrun[tnum] = 0;
322	322	}
323	323
324		static TIMER_CALLBACK( model2_timer_0_cb ) { model2_timer_exp(0, 2); }
325		static TIMER_CALLBACK( model2_timer_1_cb ) { model2_timer_exp(1, 3); }
326		static TIMER_CALLBACK( model2_timer_2_cb ) { model2_timer_exp(2, 4); }
327		static TIMER_CALLBACK( model2_timer_3_cb ) { model2_timer_exp(3, 5); }
	324	static TIMER_CALLBACK( model2_timer_0_cb ) { model2_timer_exp(machine, 0, 2); }
	325	static TIMER_CALLBACK( model2_timer_1_cb ) { model2_timer_exp(machine, 1, 3); }
	326	static TIMER_CALLBACK( model2_timer_2_cb ) { model2_timer_exp(machine, 2, 4); }
	327	static TIMER_CALLBACK( model2_timer_3_cb ) { model2_timer_exp(machine, 3, 5); }
328	328
329	329	static MACHINE_RESET(model2_common)
330	330	{
r2864	r2865
407	407	dsp_type = DSP_TYPE_TGPX4;
408	408	}
409	409
410		static void chcolor(pen_t color, UINT16 data)
	410	static void chcolor(running_machine *machine, pen_t color, UINT16 data)
411	411	{
412		palette_set_color_rgb(Machine,color,pal5bit(data >> 0),pal5bit(data >> 5),pal5bit(data >> 10));
	412	palette_set_color_rgb(machine,color,pal5bit(data >> 0),pal5bit(data >> 5),pal5bit(data >> 10));
413	413	}
414	414
415	415	static WRITE32_HANDLER(pal32_w)
416	416	{
417	417	COMBINE_DATA(paletteram32+offset);
418	418	if(ACCESSING_BITS_0_15)
419		chcolor(offset*2, paletteram32[offset]);
	419	chcolor(machine, offset*2, paletteram32[offset]);
420	420	if(ACCESSING_BITS_16_31)
421		chcolor(offset*2+1, paletteram32[offset]>>16);
	421	chcolor(machine, offset*2+1, paletteram32[offset]>>16);
422	422	}
423	423
424	424	static WRITE32_HANDLER(ctrl0_w)
r2864	r2865
907	907	return 0xff;
908	908	}
909	909
910		static void snd_latch_to_68k_w(int data)
	910	static void snd_latch_to_68k_w(running_machine *machine, int data)
911	911	{
912	912	while (!snd_68k_ready_r())
913	913	{
r2864	r2865
916	916
917	917	to_68k = data;
918	918
919		cpunum_set_input_line(Machine, 1, 2, HOLD_LINE);
	919	cpunum_set_input_line(machine, 1, 2, HOLD_LINE);
920	920
921	921	// give the 68k time to notice
922	922	cpu_spinuntil_time(ATTOTIME_IN_USEC(40));
r2864	r2865
936	936	{
937	937	if (mem_mask == 0x0000ffff)
938	938	{
939		snd_latch_to_68k_w(data&0xff);
	939	snd_latch_to_68k_w(machine, data&0xff);
940	940	}
941	941	}
942	942

src/mame/drivers/ataxx.c
r2864	r2865
104	104
105	105
106	106	static INPUT_PORTS_START( ataxx )
107		PORT_START /* 0xF6 */
	107	PORT_START_TAG("IN0") /* 0xF6 */
108	108	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
109	109	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
110	110	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* huh? affects trackball movement */
111		PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
	111	PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
112	112	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
113	113	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
114	114	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
115	115	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
116	116
117		PORT_START /* 0xF7 */
	117	PORT_START_TAG("IN1") /* 0xF7 */
118	118	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SLAVEHALT )
119	119	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
120	120	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
121	121
122		PORT_START /* 0x20 */
	122	PORT_START_TAG("IN2") /* 0x20 */
123	123	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
124	124	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNUSED )
125	125
126		PORT_START /* 0x00 - analog X */
	126	PORT_START_TAG("AN0") /* 0x00 - analog X */
127	127	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
128		PORT_START /* 0x01 - analog Y */
	128	PORT_START_TAG("AN1") /* 0x01 - analog Y */
129	129	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
130		PORT_START /* 0x02 - analog X */
	130	PORT_START_TAG("AN2") /* 0x02 - analog X */
131	131	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
132		PORT_START /* 0x03 - analog Y */
	132	PORT_START_TAG("AN3") /* 0x03 - analog Y */
133	133	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
134	134	INPUT_PORTS_END
135	135
136	136
137	137	static INPUT_PORTS_START( wsf )
138		PORT_START /* 0xF6 */
	138	PORT_START_TAG("IN0") /* 0xF6 */
139	139	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
140		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
141		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
142		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN4 )
143		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
144		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
145		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
146		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
	140	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
	141	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
	142	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN4 )
	143	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
	144	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
	145	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
	146	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
147	147
148		PORT_START /* 0xF7 */
149		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SLAVEHALT )
150		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
151		PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
	148	PORT_START_TAG("IN1") /* 0xF7 */
	149	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SLAVEHALT )
	150	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
	151	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
152	152
153		PORT_START /* 0x20 */
	153	PORT_START_TAG("IN2") /* 0x20 */
154	154	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
155	155	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
156		PORT_SERVICE_NO_TOGGLE( 0x04, IP_ACTIVE_LOW )
	156	PORT_SERVICE_NO_TOGGLE( 0x04, IP_ACTIVE_LOW )
157	157	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNUSED )
158	158
159		PORT_START /* 0x0D */
160		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
161		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
162		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
163		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
164		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
165		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
166		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
167		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
	159	PORT_START_TAG("IN3") /* 0x0D */
	160	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
	161	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
	162	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
	163	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
	164	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
	165	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
	166	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
	167	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
168	168
169		PORT_START /* 0x0E */
170		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
171		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
172		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
173		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
174		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
175		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
176		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
177		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
	169	PORT_START_TAG("IN4") /* 0x0E */
	170	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
	171	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
	172	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
	173	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
	174	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
	175	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
	176	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
	177	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
178	178
179		PORT_START /* 0x0F */
180		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
181		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
182		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
183		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
184		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
185		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START3 )
186		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
187		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
	179	PORT_START_TAG("IN5") /* 0x0F */
	180	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
	181	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
	182	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
	183	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
	184	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
	185	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START3 )
	186	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
	187	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
188	188	INPUT_PORTS_END
189	189
190	190
191	191	static INPUT_PORTS_START( indyheat )
192		PORT_START /* 0xF6 */
193		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
	192	PORT_START_TAG("IN0") /* 0xF6 */
	193	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
194	194	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
195		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_IMPULSE(1)
196		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN3 ) PORT_IMPULSE(1)
	195	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_IMPULSE(1)
	196	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN3 ) PORT_IMPULSE(1)
197	197	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
198		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
	198	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
199	199
200		PORT_START /* 0xF7 */
	200	PORT_START_TAG("IN1") /* 0xF7 */
201	201	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SLAVEHALT )
202	202	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
203		PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
	203	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
204	204
205		PORT_START /* 0x20 */
	205	PORT_START_TAG("IN2") /* 0x20 */
206	206	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
207	207	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNUSED )
208	208
209		PORT_START /* Analog wheel 1 */
	209	PORT_START_TAG("AN0") /* Analog wheel 1 */
210	210	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
211		PORT_START /* Analog wheel 2 */
	211	PORT_START_TAG("AN1") /* Analog wheel 2 */
212	212	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
213		PORT_START /* Analog wheel 3 */
	213	PORT_START_TAG("AN2") /* Analog wheel 3 */
214	214	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(3)
215		PORT_START /* Analog pedal 1 */
	215	PORT_START_TAG("AN3") /* Analog pedal 1 */
216	216	PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
217		PORT_START /* Analog pedal 2 */
	217	PORT_START_TAG("AN4") /* Analog pedal 2 */
218	218	PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
219		PORT_START /* Analog pedal 3 */
	219	PORT_START_TAG("AN5") /* Analog pedal 3 */
220	220	PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(3)
221	221
222		PORT_START /* 0x0D */
223		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
	222	PORT_START_TAG("IN3") /* 0x0D */
	223	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
224	224	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNUSED )
225	225
226		PORT_START /* 0x0E */
227		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
	226	PORT_START_TAG("IN4") /* 0x0E */
	227	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
228	228	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNUSED )
229	229
230		PORT_START /* 0x0F */
231		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
	230	PORT_START_TAG("IN5") /* 0x0F */
	231	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
232	232	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNUSED )
233		PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
	233	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
234	234	INPUT_PORTS_END
235	235
236	236
237	237	static INPUT_PORTS_START( brutforc )
238		PORT_START /* 0xF6 */
239		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
	238	PORT_START_TAG("IN0") /* 0xF6 */
	239	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
240	240	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_IMPULSE(1)
241		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
242		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN3 ) PORT_IMPULSE(1)
243		PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
244		PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
	241	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
	242	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN3 ) PORT_IMPULSE(1)
	243	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
	244	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
245	245
246		PORT_START /* 0xF7 */
247		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SLAVEHALT )
248		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
249		PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
	246	PORT_START_TAG("IN1") /* 0xF7 */
	247	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SLAVEHALT )
	248	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
	249	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
250	250
251		PORT_START /* 0x20 */
	251	PORT_START_TAG("IN2") /* 0x20 */
252	252	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
253	253	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNUSED )
254	254
255		PORT_START /* 0x0D */
256		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
257		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
258		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
259		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
260		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
261		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
262		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
263		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	255	PORT_START_TAG("IN3") /* 0x0D */
	256	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
	257	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
	258	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
	259	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
	260	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
	261	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
	262	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
	263	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
264	264
265		PORT_START /* 0x0E */
266		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
267		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
268		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
269		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
270		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
271		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
272		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
273		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	265	PORT_START_TAG("IN4") /* 0x0E */
	266	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
	267	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
	268	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
	269	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
	270	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
	271	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
	272	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
	273	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
274	274
275		PORT_START /* 0x0F */
276		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
277		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
278		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
279		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
280		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
281		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
282		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START3 )
283		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	275	PORT_START_TAG("IN5") /* 0x0F */
	276	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
	277	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
	278	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
	279	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
	280	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
	281	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
	282	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START3 )
	283	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
284	284	INPUT_PORTS_END
285	285
286	286

src/mame/drivers/leland.c
r2864	r2865
126	126
127	127
128	128	static INPUT_PORTS_START( cerberus ) /* complete, verified from code */
129		PORT_START /* 0x80 */
	129	PORT_START_TAG("IN0") /* 0x80 */
130	130	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_SPECIAL ) PORT_PLAYER(1)
131	131	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
132	132	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
133	133
134		PORT_START /* 0x81 */
	134	PORT_START_TAG("IN1") /* 0x81 */
135	135	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
136	136	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
137	137	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
138	138	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
139	139	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
140	140
141		PORT_START /* 0x90 */
	141	PORT_START_TAG("IN2") /* 0x90 */
142	142	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_SPECIAL ) PORT_PLAYER(2)
143	143	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
144	144	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
145	145
146		PORT_START /* 0x91 */
	146	PORT_START_TAG("IN3") /* 0x91 */
147	147	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
148	148	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
149	149	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 ) PORT_PLAYER(1)
150	150	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_PLAYER(1)
151	151	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
152	152
153		PORT_START /* Analog joystick 1 */
	153	PORT_START_TAG("AN0") /* Analog joystick 1 */
154	154	PORT_BIT( 0xff, 0, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(1)
155		PORT_START
	155	PORT_START_TAG("AN1")
156	156	PORT_BIT( 0xff, 0, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(2)
157		PORT_START /* Analog joystick 2 */
158		PORT_START
159		PORT_START /* Analog joystick 3 */
160		PORT_START
	157	PORT_START_TAG("AN2") /* Analog joystick 2 */
	158	PORT_START_TAG("AN3")
	159	PORT_START_TAG("AN4") /* Analog joystick 3 */
	160	PORT_START_TAG("AN5")
161	161	INPUT_PORTS_END
162	162
163	163
164	164	static INPUT_PORTS_START( mayhem ) /* complete, verified from code */
165		PORT_START /* 0xC0 */
	165	PORT_START_TAG("IN0") /* 0xC0 */
166	166	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
167	167	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
168	168	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
r2864	r2865
172	172	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
173	173	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
174	174
175		PORT_START /* 0xC1 */
	175	PORT_START_TAG("IN1") /* 0xC1 */
176	176	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
177	177	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
178	178	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
179	179	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
180	180	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
181	181
182		PORT_START /* 0xD0 */
	182	PORT_START_TAG("IN2") /* 0xD0 */
183	183	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
184	184	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
185	185	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
189	189	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
190	190	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
191	191
192		PORT_START /* 0xD1 */
	192	PORT_START_TAG("IN3") /* 0xD1 */
193	193	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
194	194	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
195	195	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
196	196	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
197	197	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
198	198
199		PORT_START /* Analog joystick 1 */
200		PORT_START
201		PORT_START /* Analog joystick 2 */
202		PORT_START
203		PORT_START /* Analog joystick 3 */
204		PORT_START
	199	PORT_START_TAG("AN0") /* Analog joystick 1 */
	200	PORT_START_TAG("AN1")
	201	PORT_START_TAG("AN2") /* Analog joystick 2 */
	202	PORT_START_TAG("AN3")
	203	PORT_START_TAG("AN4") /* Analog joystick 3 */
	204	PORT_START_TAG("AN5")
205	205	INPUT_PORTS_END
206	206
207	207
208	208	static INPUT_PORTS_START( wseries ) /* complete, verified from code */
209		PORT_START /* 0x80 */
	209	PORT_START_TAG("IN0") /* 0x80 */
210	210	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNUSED )
211	211	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Extra Base") PORT_PLAYER(1)
212	212	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Go Back") PORT_PLAYER(1)
213	213
214		PORT_START /* 0x81 */
	214	PORT_START_TAG("IN1") /* 0x81 */
215	215	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
216	216	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
217	217	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
218	218	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
219	219	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
220	220
221		PORT_START /* 0x90 */
	221	PORT_START_TAG("IN2") /* 0x90 */
222	222	PORT_BIT( 0x7f, IP_ACTIVE_LOW, IPT_UNUSED )
223	223	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Aim") PORT_PLAYER(1)
224	224
225		PORT_START /* 0x91 */
	225	PORT_START_TAG("IN3") /* 0x91 */
226	226	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
227	227	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
228	228	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 ) PORT_PLAYER(1)
229	229	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_PLAYER(1)
230	230	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
231	231
232		PORT_START /* Analog joystick 1 */
	232	PORT_START_TAG("AN0") /* Analog joystick 1 */
233	233	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
234		PORT_START
	234	PORT_START_TAG("AN1")
235	235	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
236		PORT_START /* Analog joystick 2 */
237		PORT_START
238		PORT_START /* Analog joystick 3 */
	236	PORT_START_TAG("AN2") /* Analog joystick 2 */
	237	PORT_START_TAG("AN3")
	238	PORT_START_TAG("AN4") /* Analog joystick 3 */
239	239	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
240		PORT_START
	240	PORT_START_TAG("AN5")
241	241	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
242	242	INPUT_PORTS_END
243	243
244	244
245	245	static INPUT_PORTS_START( alleymas ) /* complete, verified from code */
246		PORT_START /* 0xC0 */
	246	PORT_START_TAG("IN0") /* 0xC0 */
247	247	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNUSED )
248	248	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 )
249	249	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 )
250	250
251		PORT_START /* 0xC1 */
	251	PORT_START_TAG("IN1") /* 0xC1 */
252	252	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
253	253	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
254	254	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
255	255	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
256	256	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
257	257
258		PORT_START /* 0xD0 */
	258	PORT_START_TAG("IN2") /* 0xD0 */
259	259	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNUSED )
260	260	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) /* redundant inputs */
261	261	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) /* redundant inputs */
262	262
263		PORT_START /* 0xD1 */
	263	PORT_START_TAG("IN3") /* 0xD1 */
264	264	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
265	265	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
266	266	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 ) PORT_PLAYER(1)
267	267	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_PLAYER(1)
268	268	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
269	269
270		PORT_START /* Analog joystick 1 */
	270	PORT_START_TAG("AN0") /* Analog joystick 1 */
271	271	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
272		PORT_START
	272	PORT_START_TAG("AN1")
273	273	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(0,224) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
274		PORT_START /* Analog joystick 2 */
275		PORT_START
276		PORT_START /* Analog joystick 3 */
277		PORT_START
	274	PORT_START_TAG("AN2") /* Analog joystick 2 */
	275	PORT_START_TAG("AN3")
	276	PORT_START_TAG("AN4") /* Analog joystick 3 */
	277	PORT_START_TAG("AN5")
278	278	INPUT_PORTS_END
279	279
280	280
281	281	static INPUT_PORTS_START( upyoural ) /* complete, verified from code */
282		PORT_START /* 0xC0 */
	282	PORT_START_TAG("IN0") /* 0xC0 */
283	283	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNUSED )
284	284	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON4 )
285	285	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 )
286	286
287		PORT_START /* 0xC1 */
	287	PORT_START_TAG("IN1") /* 0xC1 */
288	288	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
289	289	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
290	290	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
291	291	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
292	292	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
293	293
294		PORT_START /* 0xD0 */
	294	PORT_START_TAG("IN2") /* 0xD0 */
295	295	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNUSED )
296	296	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
297	297	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 )
298	298
299		PORT_START /* 0xD1 */
	299	PORT_START_TAG("IN3") /* 0xD1 */
300	300	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
301	301	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
302	302	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 ) PORT_PLAYER(1)
303	303	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_PLAYER(1)
304	304	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
305	305
306		PORT_START /* Analog joystick 1 */
	306	PORT_START_TAG("AN0") /* Analog joystick 1 */
307	307	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
308		PORT_START
	308	PORT_START_TAG("AN1")
309	309	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(0,224) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
310		PORT_START /* Analog joystick 2 */
311		PORT_START
312		PORT_START /* Analog joystick 3 */
313		PORT_START
	310	PORT_START_TAG("AN2") /* Analog joystick 2 */
	311	PORT_START_TAG("AN3")
	312	PORT_START_TAG("AN4") /* Analog joystick 3 */
	313	PORT_START_TAG("AN5")
314	314	INPUT_PORTS_END
315	315
316	316
317	317	static INPUT_PORTS_START( dangerz ) /* complete, verified from code */
318		PORT_START /* 0x80 */
	318	PORT_START_TAG("IN0") /* 0x80 */
319	319	PORT_BIT( 0x1f, IP_ACTIVE_LOW, IPT_UNUSED )
320	320	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 )
321	321	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 )
322	322	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
323	323
324		PORT_START /* 0x81 */
	324	PORT_START_TAG("IN1") /* 0x81 */
325	325	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
326	326	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
327	327	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
328	328	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
329	329	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
330	330
331		PORT_START /* 0x90 */
	331	PORT_START_TAG("IN2") /* 0x90 */
332	332	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
333	333
334		PORT_START /* 0x91 */
	334	PORT_START_TAG("IN3") /* 0x91 */
335	335	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
336	336	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
337	337	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
338	338	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
339	339	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
340	340
341		PORT_START /* Analog 1 */
	341	PORT_START_TAG("AN0") /* Analog 1 */
342	342	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
343		PORT_START /* Analog 2 */
	343	PORT_START_TAG("AN1") /* Analog 2 */
344	344	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
345	345	INPUT_PORTS_END
346	346
347	347
348	348	static INPUT_PORTS_START( basebal2 ) /* complete, verified from code */
349		PORT_START /* 0x40/C0 */
	349	PORT_START_TAG("IN0") /* 0x40/C0 */
350	350	PORT_BIT( 0x0f, IP_ACTIVE_LOW, IPT_UNUSED )
351	351	PORT_BIT( 0x30, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* read by strkzone, but never referenced */
352	352	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Extra Base") PORT_PLAYER(1)
353	353	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Go Back") PORT_PLAYER(1)
354	354
355		PORT_START /* 0x41/C1 */
	355	PORT_START_TAG("IN1") /* 0x41/C1 */
356	356	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
357	357	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
358	358	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
359	359	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
360	360	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
361	361
362		PORT_START /* 0x50/D0 */
	362	PORT_START_TAG("IN2") /* 0x50/D0 */
363	363	PORT_BIT( 0x0f, IP_ACTIVE_LOW, IPT_UNUSED )
364	364	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("R Run/Steal") PORT_PLAYER(1)
365	365	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("L Run/Steal") PORT_PLAYER(1)
366	366	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_NAME("Run/Aim") PORT_PLAYER(1)
367	367	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("Run/Cutoff") PORT_PLAYER(1)
368	368
369		PORT_START /* 0x51/D1 */
	369	PORT_START_TAG("IN3") /* 0x51/D1 */
370	370	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
371	371	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
372	372	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 ) PORT_PLAYER(1)
373	373	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_PLAYER(1)
374	374	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
375	375
376		PORT_START /* Analog joystick 1 */
	376	PORT_START_TAG("AN0") /* Analog joystick 1 */
377	377	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
378		PORT_START
	378	PORT_START_TAG("AN1")
379	379	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
380		PORT_START /* Analog joystick 2 */
381		PORT_START
382		PORT_START /* Analog joystick 3 */
	380	PORT_START_TAG("AN2") /* Analog joystick 2 */
	381	PORT_START_TAG("AN3")
	382	PORT_START_TAG("AN4") /* Analog joystick 3 */
383	383	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
384		PORT_START
	384	PORT_START_TAG("AN5")
385	385	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
386	386	INPUT_PORTS_END
387	387
388	388
389	389	static INPUT_PORTS_START( redline ) /* complete, verified in code */
390		PORT_START /* 0xC0 */
	390	PORT_START_TAG("IN0") /* 0xC0 */
391	391	PORT_BIT( 0x1f, IP_ACTIVE_LOW, IPT_UNUSED )
392	392	PORT_BIT( 0xe0, 0x00, IPT_PEDAL ) PORT_MINMAX(0x00,0xe0) PORT_SENSITIVITY(100) PORT_KEYDELTA(64) PORT_PLAYER(1)
393	393
394		PORT_START /* 0xC1 */
	394	PORT_START_TAG("IN1") /* 0xC1 */
395	395	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
396	396	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
397	397	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
r2864	r2865
399	399	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNUSED )
400	400	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* used, but for what purpose? */
401	401
402		PORT_START /* 0xD0 */
	402	PORT_START_TAG("IN2") /* 0xD0 */
403	403	PORT_BIT( 0x1f, IP_ACTIVE_LOW, IPT_UNUSED )
404	404	PORT_BIT( 0xe0, 0x00, IPT_PEDAL ) PORT_MINMAX(0x00,0xe0) PORT_SENSITIVITY(100) PORT_KEYDELTA(64) PORT_PLAYER(2)
405	405
406		PORT_START /* 0xD1 */
	406	PORT_START_TAG("IN3") /* 0xD1 */
407	407	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
408	408	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
409	409	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
410	410	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
411	411	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
412	412
413		PORT_START /* Analog wheel 1 */
	413	PORT_START_TAG("AN0") /* Analog wheel 1 */
414	414	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
415		PORT_START /* Analog wheel 2 */
	415	PORT_START_TAG("AN1") /* Analog wheel 2 */
416	416	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
417	417	INPUT_PORTS_END
418	418
419	419
420	420	static INPUT_PORTS_START( quarterb ) /* complete, verified in code */
421		PORT_START /* 0x80 */
	421	PORT_START_TAG("IN0") /* 0x80 */
422	422	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
423	423	PORT_BIT( 0x0e, IP_ACTIVE_LOW, IPT_UNUSED )
424	424	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
425	425	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
426	426
427		PORT_START /* 0x81 */
	427	PORT_START_TAG("IN1") /* 0x81 */
428	428	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
429	429	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
430	430	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
431	431	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
432	432	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
433	433
434		PORT_START /* 0x90 */
	434	PORT_START_TAG("IN2") /* 0x90 */
435	435	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
436	436	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
437	437	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
r2864	r2865
441	441	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
442	442	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
443	443
444		PORT_START /* 0x91 */
	444	PORT_START_TAG("IN3") /* 0x91 */
445	445	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
446	446	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
447	447	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
448	448	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
449	449	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
450	450
451		PORT_START /* Analog spring stick 1 */
	451	PORT_START_TAG("AN0") /* Analog spring stick 1 */
452	452	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
453		PORT_START /* Analog spring stick 2 */
	453	PORT_START_TAG("AN1") /* Analog spring stick 2 */
454	454	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
455		PORT_START /* Analog spring stick 3 */
456		PORT_START /* Analog spring stick 4 */
457		PORT_START /* Analog spring stick 5 */
458		PORT_START /* Analog spring stick 6 */
	455	PORT_START_TAG("AN2") /* Analog spring stick 3 */
	456	PORT_START_TAG("AN3") /* Analog spring stick 4 */
	457	PORT_START_TAG("AN4") /* Analog spring stick 5 */
	458	PORT_START_TAG("AN5") /* Analog spring stick 6 */
459	459	INPUT_PORTS_END
460	460
461	461
462	462	static INPUT_PORTS_START( teamqb ) /* complete, verified in code */
463		PORT_START /* 0x80 */
	463	PORT_START_TAG("IN0") /* 0x80 */
464	464	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
465	465	PORT_BIT( 0x0e, IP_ACTIVE_LOW, IPT_UNUSED )
466	466	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
467	467	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
468	468
469		PORT_START /* 0x81 */
	469	PORT_START_TAG("IN1") /* 0x81 */
470	470	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
471	471	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
472	472	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
473	473	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
474	474	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
475	475
476		PORT_START /* 0x90 */
	476	PORT_START_TAG("IN2") /* 0x90 */
477	477	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
478	478	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
479	479	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
r2864	r2865
483	483	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
484	484	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
485	485
486		PORT_START /* 0x91 */
	486	PORT_START_TAG("IN3") /* 0x91 */
487	487	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
488	488	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
489	489	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
490	490	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
491	491	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
492	492
493		PORT_START /* Analog spring stick 1 */
	493	PORT_START_TAG("AN0") /* Analog spring stick 1 */
494	494	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
495		PORT_START /* Analog spring stick 2 */
	495	PORT_START_TAG("AN1") /* Analog spring stick 2 */
496	496	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
497		PORT_START /* Analog spring stick 3 */
498		PORT_START /* Analog spring stick 4 */
499		PORT_START /* Analog spring stick 5 */
	497	PORT_START_TAG("AN2") /* Analog spring stick 3 */
	498	PORT_START_TAG("AN3") /* Analog spring stick 4 */
	499	PORT_START_TAG("AN4") /* Analog spring stick 5 */
500	500	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(3)
501		PORT_START /* Analog spring stick 6 */
	501	PORT_START_TAG("AN5") /* Analog spring stick 6 */
502	502	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(3)
503	503
504		PORT_START /* 0x7C */
	504	PORT_START_TAG("IN4") /* 0x7C */
505	505	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
506	506	PORT_BIT( 0x0e, IP_ACTIVE_LOW, IPT_UNUSED )
507	507	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
r2864	r2865
509	509	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START3 )
510	510	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
511	511
512		PORT_START /* 0x7F */
	512	PORT_START_TAG("IN5") /* 0x7F */
513	513	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(4)
514	514	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(4)
515	515	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(4)
r2864	r2865
522	522
523	523
524	524	static INPUT_PORTS_START( aafb2p ) /* complete, verified in code */
525		PORT_START /* 0x80 */
	525	PORT_START_TAG("IN0") /* 0x80 */
526	526	PORT_BIT( 0x0f, IP_ACTIVE_LOW, IPT_UNUSED )
527	527	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
528	528	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
529	529
530		PORT_START /* 0x81 */
	530	PORT_START_TAG("IN1") /* 0x81 */
531	531	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
532	532	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
533	533	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
534	534	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
535	535	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
536	536
537		PORT_START /* 0x90 */
	537	PORT_START_TAG("IN2") /* 0x90 */
538	538	PORT_BIT( 0x0f, IP_ACTIVE_LOW, IPT_UNUSED )
539	539	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
540	540	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
541	541	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
542	542	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
543	543
544		PORT_START /* 0x91 */
	544	PORT_START_TAG("IN3") /* 0x91 */
545	545	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
546	546	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
547	547	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
548	548	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
549	549	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
550	550
551		PORT_START /* Analog spring stick 1 */
	551	PORT_START_TAG("AN0") /* Analog spring stick 1 */
552	552	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
553		PORT_START /* Analog spring stick 2 */
	553	PORT_START_TAG("AN1") /* Analog spring stick 2 */
554	554	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
555		PORT_START /* Analog spring stick 3 */
556		PORT_START /* Analog spring stick 4 */
557		PORT_START /* Analog spring stick 5 */
	555	PORT_START_TAG("AN2") /* Analog spring stick 3 */
	556	PORT_START_TAG("AN3") /* Analog spring stick 4 */
	557	PORT_START_TAG("AN4") /* Analog spring stick 5 */
558	558	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
559		PORT_START /* Analog spring stick 6 */
	559	PORT_START_TAG("AN5") /* Analog spring stick 6 */
560	560	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
561	561
562		PORT_START /* 0x7C */
	562	PORT_START_TAG("IN4") /* 0x7C */
563	563	PORT_BIT( 0x0f, IP_ACTIVE_LOW, IPT_UNUSED )
564	564	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
565	565	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
566	566	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
567	567	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
568	568
569		PORT_START /* 0x7F */
	569	PORT_START_TAG("IN5") /* 0x7F */
570	570	PORT_BIT( 0x0f, IP_ACTIVE_LOW, IPT_UNUSED )
571	571	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
572	572	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
r2864	r2865
576	576
577	577
578	578	static INPUT_PORTS_START( offroad ) /* complete, verified from code */
579		PORT_START /* 0xC0 */
	579	PORT_START_TAG("IN0") /* 0xC0 */
580	580	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* read */
581	581	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* read */
582	582	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* read */
r2864	r2865
586	586	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
587	587	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
588	588
589		PORT_START /* 0xC1 */
	589	PORT_START_TAG("IN1") /* 0xC1 */
590	590	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
591	591	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN3 )
592	592	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
593	593	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
594	594	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
595	595
596		PORT_START /* 0xD0 */
	596	PORT_START_TAG("IN2") /* 0xD0 */
597	597	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
598	598
599		PORT_START /* 0xD1 */
	599	PORT_START_TAG("IN3") /* 0xD1 */
600	600	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
601	601	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
602	602	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
603	603	PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
604	604	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
605	605
606		PORT_START /* Analog pedal 1 */
	606	PORT_START_TAG("AN0") /* Analog pedal 1 */
607	607	PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
608		PORT_START /* Analog pedal 2 */
	608	PORT_START_TAG("AN1") /* Analog pedal 2 */
609	609	PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
610		PORT_START /* Analog pedal 3 */
	610	PORT_START_TAG("AN2") /* Analog pedal 3 */
611	611	PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(3)
612		PORT_START /* Analog wheel 1 */
	612	PORT_START_TAG("AN3") /* Analog wheel 1 */
613	613	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
614		PORT_START /* Analog wheel 2 */
	614	PORT_START_TAG("AN4") /* Analog wheel 2 */
615	615	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
616		PORT_START /* Analog wheel 3 */
	616	PORT_START_TAG("AN5") /* Analog wheel 3 */
617	617	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(3)
618	618	INPUT_PORTS_END
619	619
620	620
621	621	static INPUT_PORTS_START( pigout ) /* complete, verified from code */
622		PORT_START /* 0x40 */
	622	PORT_START_TAG("IN0") /* 0x40 */
623	623	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
624	624	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
625	625	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
r2864	r2865
629	629	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
630	630	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
631	631
632		PORT_START /* 0x41 */
	632	PORT_START_TAG("IN1") /* 0x41 */
633	633	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLAVEHALT )
634	634	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN1 )
635	635	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* read, but never referenced */
636	636	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN2 )
637	637	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
638	638
639		PORT_START /* 0x50 */
	639	PORT_START_TAG("IN2") /* 0x50 */
640	640	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START3 )
641	641	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
642	642	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
r2864	r2865
646	646	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
647	647	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
648	648
649		PORT_START /* 0x51 */
	649	PORT_START_TAG("IN3") /* 0x51 */
650	650	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_eeprom_DATA )
651	651	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_VBLANK )
652	652	PORT_SERVICE_NO_TOGGLE( 0x04, IP_ACTIVE_LOW )
653	653	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNUSED )
654	654
655		PORT_START /* 0x7F */
	655	PORT_START_TAG("IN4") /* 0x7F */
656	656	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
657	657	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
658	658	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)

src/mame/drivers/lazercmd.c
r2864	r2865
286	286	static READ8_HANDLER( lazercmd_data_port_r )
287	287	{
288	288	int data;
289		data = input_port_read~~_indexed~~(machine, 2) & 0x0f;
	289	data = input_port_read(machine, "DSW") & 0x0f;
290	290	return data;
291	291	}
292	292
r2864	r2865
381	381	switch (offset)
382	382	{
383	383	case 0: /* player 1 joysticks */
384		data = input_port_read~~_indexed~~(machine, 0);
	384	data = input_port_read(machine, "IN0");
385	385	break;
386	386	case 1: /* player 2 joysticks */
387		data = input_port_read~~_indexed~~(machine, 1);
	387	data = input_port_read(machine, "IN1");
388	388	break;
389	389	case 2: /* player 1 + 2 buttons */
390		data = input_port_read~~_indexed~~(machine, 4);
	390	data = input_port_read(machine, "IN3");
391	391	break;
392	392	case 3: /* coin slot + start buttons */
393		data = input_port_read~~_indexed~~(machine, 3);
	393	data = input_port_read(machine, "IN2");
394	394	break;
395	395	case 4: /* vertical scan counter */
396	396	data = ((timer_count&0x10)>>1)\|((timer_count&0x20)>>3)\|((timer_count&0x40)>>5)\|((timer_count&0x80)>>7);
r2864	r2865
451	451
452	452
453	453	static INPUT_PORTS_START( lazercmd )
454		PORT_START /* IN0 player 1 controls */
	454	PORT_START_TAG("IN0") /* IN0 player 1 controls */
455	455	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
456	456	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
457	457	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
458	458	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
459	459	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
460	460
461		PORT_START /* IN1 player 2 controls */
	461	PORT_START_TAG("IN1") /* IN1 player 2 controls */
462	462	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
463	463	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
464	464	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
465	465	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
466	466	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
467	467
468		PORT_START /* IN2 dip switch */
	468	PORT_START_TAG("DSW") /* IN2 dip switch */
469	469	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Game_Time ) )
470	470	PORT_DIPSETTING( 0x00, "60 seconds" )
471	471	PORT_DIPSETTING( 0x01, "90 seconds" )
r2864	r2865
482	482	// PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
483	483	// PORT_DIPSETTING( 0x80, DEF_STR( On ) )
484	484
485		PORT_START /* IN3 coinage & start */
	485	PORT_START_TAG("IN2") /* IN3 coinage & start */
486	486	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Coinage ) )
487	487	PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
488	488	PORT_DIPSETTING( 0x01, DEF_STR( 1C_1C ) )
r2864	r2865
491	491	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN1 )
492	492	PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNUSED )
493	493
494		PORT_START /* IN4 player 1 + 2 buttons */
	494	PORT_START_TAG("IN3") /* IN4 player 1 + 2 buttons */
495	495	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
496	496	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
497	497	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
r2864	r2865
500	500	INPUT_PORTS_END
501	501
502	502	static INPUT_PORTS_START( medlanes )
503		PORT_START /* IN0 player 1 controls */
	503	PORT_START_TAG("IN0") /* IN0 player 1 controls */
504	504	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
505	505	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
506	506	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 )
507	507	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 )
508	508	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
509	509
510		PORT_START /* IN1 player 1 controls */
	510	PORT_START_TAG("IN1") /* IN1 player 1 controls */
511	511	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Hook Left") PORT_CODE(KEYCODE_Z)
512	512	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Hook Right") PORT_CODE(KEYCODE_X)
513	513	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED)
514	514
515		PORT_START /* IN2 dip switch */
	515	PORT_START_TAG("DSW") /* IN2 dip switch */
516	516	PORT_DIPNAME( 0x01, 0x01, "Game Timer" )
517	517	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
518	518	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
530	530	// PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
531	531	// PORT_DIPSETTING( 0x80, DEF_STR( On ) )
532	532
533		PORT_START /* IN3 coinage & start */
	533	PORT_START_TAG("IN2") /* IN3 coinage & start */
534	534	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Coinage ) )
535	535	PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
536	536	PORT_DIPSETTING( 0x01, DEF_STR( 1C_1C ) )
r2864	r2865
538	538	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN1 )
539	539	PORT_BIT( 0xf4, IP_ACTIVE_HIGH, IPT_UNUSED )
540	540
541		PORT_START /* IN4 not used */
	541	PORT_START_TAG("IN3") /* IN4 not used */
542	542	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
543	543	INPUT_PORTS_END
544	544
545	545	static INPUT_PORTS_START( bbonk )
546		PORT_START /* IN0 player 1 controls */
	546	PORT_START_TAG("IN0") /* IN0 player 1 controls */
547	547	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
548	548	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
549	549	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
550	550	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
551	551	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
552	552
553		PORT_START /* IN1 player 2 controls */
	553	PORT_START_TAG("IN1") /* IN1 player 2 controls */
554	554	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
555	555	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
556	556	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
557	557	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
558	558	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
559	559
560		PORT_START /* IN2 dip switch */
	560	PORT_START_TAG("DSW") /* IN2 dip switch */
561	561	PORT_DIPNAME( 0x03, 0x02, "Games to win" )
562	562	PORT_DIPSETTING( 0x02, "2" )
563	563	PORT_DIPSETTING( 0x03, "3" )
r2864	r2865
572	572	// PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
573	573	// PORT_DIPSETTING( 0x80, DEF_STR( On ) )
574	574
575		PORT_START /* IN3 coinage & start */
	575	PORT_START_TAG("IN2") /* IN3 coinage & start */
576	576	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Coinage ) )
577	577	PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
578	578	PORT_DIPSETTING( 0x01, DEF_STR( 1C_1C ) )
r2864	r2865
580	580	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN1 )
581	581	PORT_BIT( 0xf4, IP_ACTIVE_HIGH, IPT_UNUSED )
582	582
583		PORT_START /* IN4 not used */
	583	PORT_START_TAG("IN3") /* IN4 not used */
584	584	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
585	585	INPUT_PORTS_END
586	586

src/mame/drivers/lordgun.c
r2864	r2865
110	110
111	111	static READ8_HANDLER( lordgun_eeprom_r )
112	112	{
113		return input_port_read~~_indexed~~(machine, 0) \| ((eeprom_read_bit() & 1) << 7);
	113	return input_port_read(machine, "IN0") \| ((eeprom_read_bit() & 1) << 7);
114	114	}
115	115
116	116	static WRITE8_HANDLER( lordgun_eeprom_w )
r2864	r2865
328	328	***************************************************************************/
329	329
330	330	static INPUT_PORTS_START( lordgun )
331		PORT_START // IN0
	331	PORT_START_TAG("IN0")
332	332	PORT_DIPNAME( 0x01, 0x01, "Game Mode" )
333	333	PORT_DIPSETTING( 0x01, "Arcade" )
334	334	PORT_DIPSETTING( 0x00, "Street" )
r2864	r2865
346	346	PORT_SERVICE_NO_TOGGLE( 0x40, IP_ACTIVE_LOW )
347	347	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) // eeprom
348	348
349		PORT_START // IN1
	349	PORT_START_TAG("IN1")
350	350	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
351	351	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
352	352	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
355	355	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
356	356	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE2 ) // cheat: skip ahead
357	357
358		PORT_START // IN2
	358	PORT_START_TAG("IN2")
359	359	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
360	360	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
361	361	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
365	365	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
366	366	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
367	367
368		PORT_START // IN3
	368	PORT_START_TAG("IN3")
369	369	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
370	370	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
371	371	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
375	375	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
376	376	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
377	377
378		PORT_START //IN 4
	378	PORT_START_TAG("IN4")
379	379	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(5)
380	380	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(5)
381	381	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
385	385	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
386	386	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
387	387
388		PORT_START // IN5
	388	PORT_START_TAG("LIGHT0_X")
389	389	PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_MINMAX(0,0x1ff) PORT_SENSITIVITY(35) PORT_KEYDELTA(10) PORT_PLAYER(1)
390	390
391		PORT_START // IN6
	391	PORT_START_TAG("LIGHT1_X")
392	392	PORT_BIT( 0x1ff, 0x100, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_MINMAX(0,0x1ff) PORT_SENSITIVITY(35) PORT_KEYDELTA(10) PORT_PLAYER(2)
393	393
394		PORT_START // IN7
	394	PORT_START_TAG("LIGHT0_Y")
395	395	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(10) PORT_PLAYER(1)
396	396
397		PORT_START // IN8
	397	PORT_START_TAG("LIGHT1_Y")
398	398	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(10) PORT_PLAYER(2)
399	399	INPUT_PORTS_END
400	400

src/mame/drivers/lemmings.c
r2864	r2865
32	32	static READ16_HANDLER( lemmings_trackball_r )
33	33	{
34	34	switch (offset) {
35		case 0: return input_port_read_indexed(machine, 4); break;
36		case 1: return input_port_read_indexed(machine, 5); break;
37		case 4: return input_port_read_indexed(machine, 6); break;
38		case 5: return input_port_read_indexed(machine, 7); break;
	35	case 0: return input_port_read(machine, "AN0"); break;
	36	case 1: return input_port_read(machine, "AN1"); break;
	37	case 4: return input_port_read(machine, "AN2"); break;
	38	case 5: return input_port_read(machine, "AN3"); break;
39	39	}
40	40	return 0;
41	41	}
r2864	r2865
45	45	{
46	46	switch (offset<<1) {
47	47	case 0x41a: /* Player input */
48		return input_port_read~~_indexed~~(machine, 0);
	48	return input_port_read(machine, "IN0");
49	49
50	50	case 0x320: /* Coins */
51		return input_port_read~~_indexed~~(machine, 1);
	51	return input_port_read(machine, "IN1");
52	52
53	53	case 0x4e6: /* Dips */
54		return (input_port_read~~_indexed~~(machine, 2) + (input_port_read~~_indexed~~(machine, 3) << 8));
	54	return (input_port_read(machine, "DSW1") + (input_port_read(machine, "DSW2") << 8));
55	55	}
56	56
57	57	return 0;

src/mame/drivers/pushman.c
r2864	r2865
15	15	The hardware is actually very similar to F1-Dream and Tiger Road but
16	16	with a 68705 for protection.
17	17
	18	There is a Top Tronic licensed version currently not dumped
	19
18	20	**************************************************************************
19	21
20	22	Bouncing Balls (c) 1991 Comad

src/mame/drivers/hnayayoi.c
r2864	r2865
54	54	{
55	55	int res = 0x3f;
56	56	int i;
	57	static const char *keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
57	58
58	59	for (i = 0;i < 5;i++)
59		if (~keyb & (1 << i)) res &= input_port_read~~_indexed~~(machine, 4+i);
	60	if (~keyb & (1 << i)) res &= input_port_read(machine, keynames[i]);
60	61
61	62	return res;
62	63	}
r2864	r2865
118	119	ADDRESS_MAP_GLOBAL_MASK(0xff)
119	120	AM_RANGE(0x02, 0x02) AM_READ(YM2203_status_port_0_r)
120	121	AM_RANGE(0x03, 0x03) AM_READ(YM2203_read_port_0_r)
121		AM_RANGE(0x04, 0x04) AM_READ~~(input~~_~~port_2_r~~)
	122	AM_RANGE(0x04, 0x04) AM_READ_PORT("DSW3")
122	123	AM_RANGE(0x41, 0x41) AM_READ(keyboard_0_r)
123	124	AM_RANGE(0x42, 0x42) AM_READ(keyboard_1_r)
124		AM_RANGE(0x43, 0x43) AM_READ~~(input~~_~~port_3_r~~)
	125	AM_RANGE(0x43, 0x43) AM_READ_PORT("COIN")
125	126	ADDRESS_MAP_END
126	127
127	128	static ADDRESS_MAP_START( hnayayoi_writeport, ADDRESS_SPACE_IO, 8 )
r2864	r2865
147	148	AM_RANGE(0x8000, 0xfeff) AM_READ(SMH_ROM)
148	149	AM_RANGE(0xff02, 0xff02) AM_READ(YM2203_status_port_0_r)
149	150	AM_RANGE(0xff03, 0xff03) AM_READ(YM2203_read_port_0_r)
150		AM_RANGE(0xff04, 0xff04) AM_READ~~(input~~_~~port_2_r~~)
	151	AM_RANGE(0xff04, 0xff04) AM_READ_PORT("DSW3")
151	152	AM_RANGE(0xff41, 0xff41) AM_READ(keyboard_0_r)
152	153	AM_RANGE(0xff42, 0xff42) AM_READ(keyboard_1_r)
153		AM_RANGE(0xff43, 0xff43) AM_READ~~(input~~_~~port_3_r~~)
	154	AM_RANGE(0xff43, 0xff43) AM_READ_PORT("COIN")
154	155	ADDRESS_MAP_END
155	156
156	157	static ADDRESS_MAP_START( hnfubuki_writemem, ADDRESS_SPACE_PROGRAM, 8 )
r2864	r2865
200	201	AM_RANGE(0x51, 0x51) AM_READ(YM2203_read_port_0_r)
201	202	AM_RANGE(0x16, 0x16) AM_READ(keyboard_0_r) // bit 7 = blitter busy flag
202	203	AM_RANGE(0x15, 0x15) AM_READ(keyboard_1_r)
203		AM_RANGE(0x14, 0x14) AM_READ~~(input~~_~~port_3_r~~)
	204	AM_RANGE(0x14, 0x14) AM_READ_PORT("COIN")
204	205	ADDRESS_MAP_END
205	206
206	207	static ADDRESS_MAP_START( untoucha_writeport, ADDRESS_SPACE_IO, 8 )
r2864	r2865
220	221	ADDRESS_MAP_END
221	222
222	223
	224	static INPUT_PORTS_START( mj_keyboard )
	225	PORT_START_TAG("KEY0")
	226	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
	227	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
	228	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
	229	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M )
	230	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
	231	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
	232	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
223	233
	234	PORT_START_TAG("KEY1")
	235	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
	236	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
	237	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
	238	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N )
	239	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
	240	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
	241	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
	242
	243	PORT_START_TAG("KEY2")
	244	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
	245	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
	246	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
	247	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
	248	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
	249	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
	250
	251	PORT_START_TAG("KEY3")
	252	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
	253	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
	254	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
	255	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
	256	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
	257
	258	PORT_START_TAG("KEY4")
	259	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE )
	260	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE )
	261	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP )
	262	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
	263	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG )
	264	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL )
	265	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
	266	INPUT_PORTS_END
	267
	268
224	269	static INPUT_PORTS_START( hnayayoi )
225		PORT_START /* DSW1 */
	270	PORT_START_TAG("DSW1") /* DSW1 */
226	271	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
227	272	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
228	273	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
248	293	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
249	294	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
250	295
251		PORT_START /* DSW2 */
	296	PORT_START_TAG("DSW2") /* DSW2 */
252	297	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
253	298	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
254	299	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
274	319	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
275	320	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
276	321
277		PORT_START /* DSW3 */
	322	PORT_START_TAG("DSW3") /* DSW3 */
278	323	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter busy flag
279	324	PORT_SERVICE( 0x02, IP_ACTIVE_LOW )
280	325	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
r2864	r2865
296	341	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
297	342	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
298	343
299		PORT_START /* COIN */
	344	PORT_START_TAG("COIN") /* COIN */
300	345	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
301	346	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
302		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) /* Test */
	347	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) /* Test */
303	348	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) /* Analizer (Statistics) */
304	349	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
305	350	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) /* "Note" ("Paper Money") = 10 Credits */
306	351	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
307	352	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
308	353
309		PORT_START /* P1 keyboard */
310		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
311		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
312		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
313		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M )
314		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
315		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
316		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
317
318		PORT_START
319		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
320		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
321		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
322		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N )
323		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
324		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
325		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
326
327		PORT_START
328		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
329		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
330		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
331		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
332		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
333		PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
334
335		PORT_START
336		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
337		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
338		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
339		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
340		PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
341
342		PORT_START
343		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE )
344		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE )
345		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP )
346		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
347		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG )
348		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL )
349		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
	354	PORT_INCLUDE( mj_keyboard )
350	355	INPUT_PORTS_END
351	356
352
353	357	static INPUT_PORTS_START( hnfubuki )
354		PORT_START /* DSW1 */
	358	PORT_START_TAG("DSW1") /* DSW1 */
355	359	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
356	360	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
357	361	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
377	381	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
378	382	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
379	383
380		PORT_START /* DSW2 */
	384	PORT_START_TAG("DSW2") /* DSW2 */
381	385	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
382	386	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
383	387	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
403	407	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
404	408	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
405	409
406		PORT_START /* DSW3 */
	410	PORT_START_TAG("DSW3") /* DSW3 */
407	411	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) // blitter busy flag
408	412	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
409	413	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
r2864	r2865
427	431	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
428	432	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
429	433
430		PORT_START /* COIN */
	434	PORT_START_TAG("COIN") /* COIN */
431	435	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
432	436	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
433		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) /* Test */
	437	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) /* Test */
434	438	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) /* Analizer (Statistics) */
435	439	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
436	440	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) /* "Note" ("Paper Money") = 10 Credits */
437	441	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
438	442	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
439	443
440		PORT_START /* P1 keyboard */
441		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
442		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
443		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
444		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M )
445		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
446		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
447		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
448
449		PORT_START
450		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
451		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
452		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
453		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N )
454		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
455		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
456		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
457
458		PORT_START
459		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
460		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
461		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
462		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
463		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
464		PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
465
466		PORT_START
467		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
468		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
469		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
470		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
471		PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
472
473		PORT_START
474		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE )
475		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE )
476		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP )
477		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
478		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG )
479		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL )
480		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
	444	PORT_INCLUDE( mj_keyboard )
481	445	INPUT_PORTS_END
482	446
483	447
484	448	static INPUT_PORTS_START( untoucha )
485		PORT_START /* DSW1 */
	449	PORT_START_TAG("DSW1") /* DSW1 */
486	450	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
487	451	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
488	452	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
508	472	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
509	473	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
510	474
511		PORT_START /* DSW2 */
	475	PORT_START_TAG("DSW2") /* DSW2 */
512	476	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
513	477	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
514	478	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
534	498	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
535	499	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
536	500
537		PORT_START /* not used */
538		PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
539
540		PORT_START /* COIN */
	501	PORT_START_TAG("COIN") /* COIN */
541	502	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
542	503	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
543		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) /* Test */
	504	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) /* Test */
544	505	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) /* Analizer (Statistics) */
545	506	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
546	507	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) /* "Note" ("Paper Money") = 10 Credits */
547	508	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
548	509	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
549	510
550		PORT_START /* P1 keyboard */
551		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 1") PORT_CODE(KEYCODE_Z)
552		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 3") PORT_CODE(KEYCODE_C)
553		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 5") PORT_CODE(KEYCODE_B)
	511	PORT_START_TAG("KEY0") /* P1 keyboard */
	512	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 1") PORT_CODE(KEYCODE_Z)
	513	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 3") PORT_CODE(KEYCODE_C)
	514	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 5") PORT_CODE(KEYCODE_B)
554	515	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
555	516	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
556	517	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
557	518	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
558	519
559		PORT_START
	520	PORT_START_TAG("KEY1")
560	521	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
561	522	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
562	523	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
563		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet") PORT_CODE(KEYCODE_3)
	524	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet") PORT_CODE(KEYCODE_3)
564	525	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
565		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Take Score") PORT_CODE(KEYCODE_RCONTROL)
	526	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Take Score") PORT_CODE(KEYCODE_RCONTROL)
566	527	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
567	528
568		PORT_START
569		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 2") PORT_CODE(KEYCODE_X)
570		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 4") PORT_CODE(KEYCODE_V)
	529	PORT_START_TAG("KEY2")
	530	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 2") PORT_CODE(KEYCODE_X)
	531	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Hold 4") PORT_CODE(KEYCODE_V)
571	532	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
572	533	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
573		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Cancel") PORT_CODE(KEYCODE_N)
	534	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Cancel") PORT_CODE(KEYCODE_N)
574	535	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
575	536	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
576	537
577		PORT_START
	538	PORT_START_TAG("KEY3")
578	539	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
579	540	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
580		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Deal") PORT_CODE(KEYCODE_1)
	541	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Deal") PORT_CODE(KEYCODE_1)
581	542	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
582	543	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
583	544	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
584	545	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNKNOWN )
585	546
586		PORT_START
	547	PORT_START_TAG("KEY4")
587	548	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
588		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Double Up") PORT_CODE(KEYCODE_RSHIFT)
	549	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Double Up") PORT_CODE(KEYCODE_RSHIFT)
589	550	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
590		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Flip Flop") PORT_CODE(KEYCODE_F)
	551	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Flip Flop") PORT_CODE(KEYCODE_F)
591	552	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
592	553	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
593	554	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )

src/mame/drivers/system18.c
r2864	r2865
70	70	#include "sound/2612intf.h"
71	71	#include "sound/rf5c68.h"
72	72
73		void fd1094_machine_init(void);
74		void fd1094_driver_init(void (set_decrypted)(UINT8 ));
75
76	73	/* video/segac2.c */
77	74	extern void update_system18_vdp( bitmap_t bitmap, const rectangle cliprect );
78	75	extern READ16_HANDLER( segac2_vdp_r );

src/mame/drivers/missb2.c
r2864	r2865
14	14	*/
15	15
16	16	#include "driver.h"
17		#include "deprecat.h"
18	17	#include "sound/okim6295.h"
19	18	#include "sound/3812intf.h"
20	19	#include "includes/bublbobl.h"
r2864	r2865
117	116	return 0;
118	117	}
119	118
120		INLINE void bg_changecolor_RRRRGGGGBBBBxxxx(pen_t color,int data)
	119	INLINE void bg_changecolor_RRRRGGGGBBBBxxxx(running_machine *machine,pen_t color,int data)
121	120	{
122		palette_set_color_rgb(Machine,color+256,pal4bit(data >> 12),pal4bit(data >> 8),pal4bit(data >> 4));
	121	palette_set_color_rgb(machine,color+256,pal4bit(data >> 12),pal4bit(data >> 8),pal4bit(data >> 4));
123	122	}
124	123
125	124	static WRITE8_HANDLER( bg_paletteram_RRRRGGGGBBBBxxxx_be_w )
126	125	{
127	126	bg_paletteram[offset] = data;
128		bg_changecolor_RRRRGGGGBBBBxxxx(offset / 2,bg_paletteram[offset \| 1] \| (bg_paletteram[offset & ~1] << 8));
	127	bg_changecolor_RRRRGGGGBBBBxxxx(machine, offset / 2,bg_paletteram[offset \| 1] \| (bg_paletteram[offset & ~1] << 8));
129	128	}
130	129
131	130	static WRITE8_HANDLER( missb2_bg_bank_w )

src/mame/drivers/liberatr.c
r2864	r2865
177	177	/* input becomes the starting point for the trackball counters */
178	178	if (((data ^ ctrld) & 0x10) && (data & 0x10))
179	179	{
180		UINT8 trackball = input_port_read_indexed(machine, 4);
181		UINT8 switches = input_port_read_indexed(machine, 0);
	180	UINT8 trackball = input_port_read(machine, "FAKE");
	181	UINT8 switches = input_port_read(machine, "IN0");
182	182	trackball_offset = ((trackball & 0xf0) - (switches & 0xf0)) \| ((trackball - switches) & 0x0f);
183	183	}
184	184	ctrld = data & 0x10;
r2864	r2865
190	190	/* if ctrld is high, the /ld signal on the LS191 is NOT set, meaning that the trackball is counting */
191	191	if (ctrld)
192	192	{
193		UINT8 trackball = input_port_read~~_indexed~~(machine, 4);
	193	UINT8 trackball = input_port_read(machine, "FAKE");
194	194	return ((trackball & 0xf0) - (trackball_offset & 0xf0)) \| ((trackball - trackball_offset) & 0x0f);
195	195	}
196	196
197	197	/* otherwise, the LS191 is simply passing through the raw switch inputs */
198	198	else
199		return input_port_read~~_indexed~~(machine, 0);
	199	return input_port_read(machine, "IN0");
200	200	}
201	201
202	202
r2864	r2865
246	246	AM_RANGE(0x0002, 0x0002) AM_READWRITE(liberatr_bitmap_xy_r, liberatr_bitmap_xy_w)
247	247	AM_RANGE(0x0000, 0x3fff) AM_RAM_WRITE(liberatr_bitmap_w) AM_BASE(&liberatr_bitmapram) /* overlapping for my convenience */
248	248	AM_RANGE(0x4000, 0x4000) AM_READ(liberatr_input_port_0_r)
249		AM_RANGE(0x4001, 0x4001) AM_READ~~(input~~_~~port_~~1_r)
	249	AM_RANGE(0x4001, 0x4001) AM_READ_PORT("IN1")
250	250	AM_RANGE(0x4000, 0x400f) AM_WRITE(SMH_RAM) AM_BASE(&liberatr_base_ram)
251	251	AM_RANGE(0x4200, 0x421f) AM_WRITE(SMH_RAM) AM_BASE(&liberatr_colorram)
252	252	AM_RANGE(0x4400, 0x4400) AM_WRITENOP
r2864	r2865
275	275	*************************************/
276	276
277	277	static INPUT_PORTS_START( liberatr )
278		PORT_START /* IN0 - $5000 */
	278	PORT_START_TAG("IN0") /* IN0 - $5000 */
279	279	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
280	280	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN1 )
281	281	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
r2864	r2865
287	287	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
288	288	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
289	289
290		PORT_START /* IN1 - $5001 */
	290	PORT_START_TAG("IN1") /* IN1 - $5001 */
291	291	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
292	292	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
293	293	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 )
r2864	r2865
297	297	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
298	298	PORT_BIT( 0x80, IP_ACTIVE_HIGH,IPT_VBLANK )
299	299
300		PORT_START /* IN2 - Game Option switches DSW @ D4 on PCB */
	300	PORT_START_TAG("DSW1") /* IN2 - Game Option switches DSW @ D4 on PCB */
301	301	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Lives ) )
302	302	PORT_DIPSETTING( 0x00, "4" )
303	303	PORT_DIPSETTING( 0x01, "5" )
r2864	r2865
320	320	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
321	321	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
322	322
323		PORT_START /* IN3 - Pricing Option switches DSW @ A4 on PCB */
	323	PORT_START_TAG("DSW2") /* IN3 - Pricing Option switches DSW @ A4 on PCB */
324	324	PORT_DIPNAME( 0x03, 0x02, DEF_STR( Coinage ) )
325	325	PORT_DIPSETTING( 0x03, DEF_STR( 2C_1C ) )
326	326	PORT_DIPSETTING( 0x02, DEF_STR( 1C_1C ) )
r2864	r2865
345	345	PORT_DIPSETTING ( 0xc0, "Freeze Mode" )
346	346	PORT_DIPSETTING ( 0xe0, "Freeze Mode" )
347	347
348		PORT_START /* IN4 - FAKE - overlaps IN0 in the HW */
	348	PORT_START_TAG("FAKE") /* IN4 - FAKE - overlaps IN0 in the HW */
349	349	PORT_BIT( 0x0f, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(30) PORT_KEYDELTA(10)
350	350	PORT_BIT( 0xf0, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(30) PORT_KEYDELTA(10)
351	351	INPUT_PORTS_END

src/mame/drivers/namcos21.c
r2864	r2865
509	509	static UINT16 *master_dsp_code;
510	510
511	511	void
512		namcos21_kickstart( int internal )
	512	namcos21_kickstart( running_machine *machine, int internal )
513	513	{
514	514	/* patch dsp watchdog */
515	515	switch( namcos2_gametype )
r2864	r2865
535	535	mpDspState->slaveOutputSize = 0;
536	536	mpDspState->masterFinished = 0;
537	537	mpDspState->slaveActive = 0;
538		cpunum_set_input_line(Machine, 4, 0, HOLD_LINE); /* DSP: master */
539		cpunum_set_input_line(Machine, 5, INPUT_LINE_RESET, PULSE_LINE); /* DSP: slave */
	538	cpunum_set_input_line(machine, 4, 0, HOLD_LINE); /* DSP: master */
	539	cpunum_set_input_line(machine, 5, INPUT_LINE_RESET, PULSE_LINE); /* DSP: slave */
540	540	}
541	541
542	542	static UINT16
r2864	r2865
558	558	} /* ReadWordFromSlaveInput */
559	559
560	560	static size_t
561		GetInputBytesAdvertisedForSlave( void )
	561	GetInputBytesAdvertisedForSlave( running_machine *machine )
562	562	{
563	563	if( mpDspState->slaveBytesAdvertised < mpDspState->slaveBytesAvailable )
564	564	{
r2864	r2865
566	566	}
567	567	else if( mpDspState->slaveActive && mpDspState->masterFinished && mpDspState->masterSourceAddr )
568	568	{
569		namcos21_kickstart(0);
	569	namcos21_kickstart(machine, 0);
570	570	}
571	571	return mpDspState->slaveBytesAdvertised;
572	572	} /* GetInputBytesAdvertisedForSlave */
r2864	r2865
880	880
881	881	static READ16_HANDLER(slave_port2_r)
882	882	{
883		return GetInputBytesAdvertisedForSlave();
	883	return GetInputBytesAdvertisedForSlave(machine);
884	884	} /* slave_port2_r */
885	885
886	886	static READ16_HANDLER(slave_port3_r)

src/mame/drivers/gameplan.c
r2864	r2865
95	95
96	96	static READ8_HANDLER( io_port_r )
97	97	{
	98	static const char *portnames[] = { "IN0", "IN1", "IN2", "IN3", "DSW0", "DSW1" };
98	99	gameplan_state *state = machine->driver_data;
99	100
100		return input_port_read~~_indexed~~(machine, state->current_port);
	101	return input_port_read(machine, portnames[state->current_port]);
101	102	}
102	103
103	104
r2864	r2865
279	280	*************************************/
280	281
281	282	static INPUT_PORTS_START( killcom )
282		PORT_START /* COL. A - from "TEST NO.7 - status locator - coin-door" */
	283	PORT_START_TAG("IN0") /* COL. A - from "TEST NO.7 - status locator - coin-door" */
283	284	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
284	285	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
285	286	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_TILT )
r2864	r2865
289	290	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN2 )
290	291	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 )
291	292
292		PORT_START /* COL. B - from "TEST NO.7 - status locator - start sws." */
	293	PORT_START_TAG("IN1") /* COL. B - from "TEST NO.7 - status locator - start sws." */
293	294	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
294	295	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
295	296	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
299	300	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
300	301	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
301	302
302		PORT_START /* COL. C - from "TEST NO.8 - status locator - player no.1" */
	303	PORT_START_TAG("IN2") /* COL. C - from "TEST NO.8 - status locator - player no.1" */
303	304	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 )
304	305	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
305	306	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 )
r2864	r2865
309	310	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
310	311	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
311	312
312		PORT_START /* COL. D - from "TEST NO.8 - status locator - player no.2" */
	313	PORT_START_TAG("IN3") /* COL. D - from "TEST NO.8 - status locator - player no.2" */
313	314	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_COCKTAIL
314	315	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
315	316	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_COCKTAIL
r2864	r2865
319	320	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_COCKTAIL
320	321	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_COCKTAIL
321	322
322		PORT_START /* DSW A - from "TEST NO.6 - dip switch A" */
	323	PORT_START_TAG("DSW0") /* DSW A - from "TEST NO.6 - dip switch A" */
323	324	PORT_DIPNAME( 0x03, 0x03, "Coinage P1/P2" )
324	325	PORT_DIPSETTING( 0x03, "1 Credit/2 Credits" )
325	326	PORT_DIPSETTING( 0x02, "2 Credits/3 Credits" )
r2864	r2865
343	344	PORT_DIPSETTING( 0x40, "Fast" )
344	345	PORT_DIPSETTING( 0x00, "Fastest" )
345	346
346		PORT_START /* DSW B - from "TEST NO.6 - dip switch B" */
	347	PORT_START_TAG("DSW1") /* DSW B - from "TEST NO.6 - dip switch B" */
347	348	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
348	349	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
349	350	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
369	370	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
370	371	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
371	372
372		PORT_START /* audio board DSW A */
	373	PORT_START_TAG("DSW2") /* audio board DSW A */
373	374	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
374	375	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
375	376	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
395	396	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
396	397	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
397	398
398		PORT_START /* audio board DSW B */
	399	PORT_START_TAG("DSW3") /* audio board DSW B */
399	400	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
400	401	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
401	402	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
424	425
425	426
426	427	static INPUT_PORTS_START( megatack )
427		PORT_START /* COL. A - from "TEST NO.7 - status locator - coin-door" */
	428	PORT_START_TAG("IN0") /* COL. A - from "TEST NO.7 - status locator - coin-door" */
428	429	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
429	430	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
430	431	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_TILT )
r2864	r2865
434	435	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN2 )
435	436	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 )
436	437
437		PORT_START /* COL. B - from "TEST NO.7 - status locator - start sws." */
	438	PORT_START_TAG("IN1") /* COL. B - from "TEST NO.7 - status locator - start sws." */
438	439	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
439	440	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
440	441	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
444	445	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
445	446	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
446	447
447		PORT_START /* COL. C - from "TEST NO.8 - status locator - player no.1" */
	448	PORT_START_TAG("IN2") /* COL. C - from "TEST NO.8 - status locator - player no.1" */
448	449	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
449	450	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 )
450	451	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
454	455	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
455	456	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
456	457
457		PORT_START /* COL. D - from "TEST NO.8 - status locator - player no.2" */
	458	PORT_START_TAG("IN3") /* COL. D - from "TEST NO.8 - status locator - player no.2" */
458	459	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
459	460	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
460	461	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
464	465	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_COCKTAIL
465	466	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
466	467
467		PORT_START /* DSW A - from "TEST NO.6 - dip switch A" */
	468	PORT_START_TAG("DSW0") /* DSW A - from "TEST NO.6 - dip switch A" */
468	469	PORT_DIPNAME( 0x03, 0x03, "Coinage P1/P2" )
469	470	PORT_DIPSETTING( 0x03, "1 Credit/2 Credits" )
470	471	PORT_DIPSETTING( 0x02, "2 Credits/3 Credits" )
r2864	r2865
489	490	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
490	491	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
491	492
492		PORT_START /* DSW B - from "TEST NO.6 - dip switch B" */
	493	PORT_START_TAG("DSW1") /* DSW B - from "TEST NO.6 - dip switch B" */
493	494	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Bonus_Life ) )
494	495	PORT_DIPSETTING( 0x07, "20000" )
495	496	PORT_DIPSETTING( 0x06, "30000" )
r2864	r2865
515	516	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
516	517	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
517	518
518		PORT_START /* audio board DSW A */
	519	PORT_START_TAG("DSW2") /* audio board DSW A */
519	520	PORT_DIPNAME( 0x01, 0x00, "Sound Test A 0" )
520	521	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
521	522	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
541	542	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
542	543	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
543	544
544		PORT_START /* audio board DSW B */
	545	PORT_START_TAG("DSW3") /* audio board DSW B */
545	546	PORT_DIPNAME( 0x01, 0x00, "Sound Test B 0" )
546	547	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
547	548	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
570	571
571	572
572	573	static INPUT_PORTS_START( challeng )
573		PORT_START /* COL. A - from "TEST NO.7 - status locator - coin-door" */
	574	PORT_START_TAG("IN0") /* COL. A - from "TEST NO.7 - status locator - coin-door" */
574	575	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
575	576	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
576	577	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_TILT )
r2864	r2865
580	581	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
581	582	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
582	583
583		PORT_START /* COL. B - from "TEST NO.7 - status locator - start sws." */
	584	PORT_START_TAG("IN1") /* COL. B - from "TEST NO.7 - status locator - start sws." */
584	585	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
585	586	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
586	587	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
590	591	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
591	592	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
592	593
593		PORT_START /* COL. C - from "TEST NO.8 - status locator - player no.1" */
	594	PORT_START_TAG("IN2") /* COL. C - from "TEST NO.8 - status locator - player no.1" */
594	595	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 )
595	596	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 )
596	597	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
600	601	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
601	602	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
602	603
603		PORT_START /* COL. D - from "TEST NO.8 - status locator - player no.2" */
	604	PORT_START_TAG("IN3") /* COL. D - from "TEST NO.8 - status locator - player no.2" */
604	605	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_COCKTAIL
605	606	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
606	607	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
610	611	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_COCKTAIL
611	612	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
612	613
613		PORT_START /* DSW A - from "TEST NO.6 - dip switch A" */
	614	PORT_START_TAG("DSW0") /* DSW A - from "TEST NO.6 - dip switch A" */
614	615	PORT_DIPNAME( 0x03, 0x03, "Coinage P1/P2" )
615	616	PORT_DIPSETTING( 0x03, "1 Credit/2 Credits" )
616	617	PORT_DIPSETTING( 0x02, "2 Credits/3 Credits" )
r2864	r2865
634	635	PORT_DIPSETTING( 0x40, "5" )
635	636	PORT_DIPSETTING( 0x00, "6" )
636	637
637		PORT_START /* DSW B - from "TEST NO.6 - dip switch B" */
	638	PORT_START_TAG("DSW1") /* DSW B - from "TEST NO.6 - dip switch B" */
638	639	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Bonus_Life ) )
639	640	PORT_DIPSETTING( 0x01, "20000" )
640	641	PORT_DIPSETTING( 0x00, "30000" )
r2864	r2865
660	661	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
661	662	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
662	663
663		PORT_START /* audio board DSW A */
	664	PORT_START_TAG("DSW2") /* audio board DSW A */
664	665	PORT_DIPNAME( 0x01, 0x00, "Sound Test A 0" )
665	666	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
666	667	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
686	687	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
687	688	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
688	689
689		PORT_START /* audio board DSW B */
	690	PORT_START_TAG("DSW3") /* audio board DSW B */
690	691	PORT_DIPNAME( 0x01, 0x00, "Sound Test B 0" )
691	692	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
692	693	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
715	716
716	717
717	718	static INPUT_PORTS_START( kaos )
718		PORT_START /* COL. A - from "TEST NO.7 - status locator - coin-door" */
	719	PORT_START_TAG("IN0") /* COL. A - from "TEST NO.7 - status locator - coin-door" */
719	720	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
720	721	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
721	722	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_TILT )
r2864	r2865
725	726	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN2 )
726	727	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 )
727	728
728		PORT_START /* COL. B - from "TEST NO.7 - status locator - start sws." */
	729	PORT_START_TAG("IN1") /* COL. B - from "TEST NO.7 - status locator - start sws." */
729	730	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
730	731	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
731	732	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
735	736	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
736	737	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
737	738
738		PORT_START /* COL. C - from "TEST NO.8 - status locator - player no.1" */
	739	PORT_START_TAG("IN2") /* COL. C - from "TEST NO.8 - status locator - player no.1" */
739	740	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
740	741	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 )
741	742	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
r2864	r2865
745	746	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
746	747	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
747	748
748		PORT_START /* COL. D - from "TEST NO.8 - status locator - player no.2" */
	749	PORT_START_TAG("IN3") /* COL. D - from "TEST NO.8 - status locator - player no.2" */
749	750	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
750	751	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
751	752	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_COCKTAIL
r2864	r2865
755	756	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_COCKTAIL
756	757	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
757	758
758		PORT_START
	759	PORT_START_TAG("DSW0")
759	760	PORT_DIPNAME( 0x0f, 0x0e, DEF_STR( Coinage ) )
760	761	PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
761	762	PORT_DIPSETTING( 0x0e, DEF_STR( 1C_1C ) )
r2864	r2865
785	786	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
786	787	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
787	788
788		PORT_START
	789	PORT_START_TAG("DSW1")
789	790	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Lives ) )
790	791	PORT_DIPSETTING( 0x01, "3" )
791	792	PORT_DIPSETTING( 0x00, "4" )
r2864	r2865
810	811	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
811	812	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
812	813
813		PORT_START /* audio board DSW A */
	814	PORT_START_TAG("DSW2") /* audio board DSW A */
814	815	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
815	816	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
816	817	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
836	837	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
837	838	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
838	839
839		PORT_START /* audio board DSW B */
	840	PORT_START_TAG("DSW3") /* audio board DSW B */
840	841	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
841	842	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
842	843	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
865	866
866	867
867	868	static INPUT_PORTS_START( leprechn )
868		PORT_START /* COL. A - from "TEST NO.7 - status locator - coin-door" */
	869	PORT_START_TAG("IN0") /* COL. A - from "TEST NO.7 - status locator - coin-door" */
869	870	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
870	871	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
871	872	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_TILT )
r2864	r2865
875	876	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN2 )
876	877	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 )
877	878
878		PORT_START /* COL. B - from "TEST NO.7 - status locator - start sws." */
	879	PORT_START_TAG("IN1") /* COL. B - from "TEST NO.7 - status locator - start sws." */
879	880	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
880	881	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
881	882	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
885	886	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
886	887	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
887	888
888		PORT_START /* COL. C - from "TEST NO.8 - status locator - player no.1" */
	889	PORT_START_TAG("IN2") /* COL. C - from "TEST NO.8 - status locator - player no.1" */
889	890	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
890	891	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
891	892	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
895	896	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
896	897	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
897	898
898		PORT_START /* COL. D - from "TEST NO.8 - status locator - player no.2" */
	899	PORT_START_TAG("IN3") /* COL. D - from "TEST NO.8 - status locator - player no.2" */
899	900	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
900	901	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
901	902	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
905	906	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_COCKTAIL
906	907	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_COCKTAIL
907	908
908		PORT_START /* DSW A - from "TEST NO.6 - dip switch A" */
	909	PORT_START_TAG("DSW0") /* DSW A - from "TEST NO.6 - dip switch A" */
909	910	PORT_DIPNAME( 0x09, 0x09, DEF_STR( Coin_B ) )
910	911	PORT_DIPSETTING( 0x09, DEF_STR( 1C_1C ) )
911	912	PORT_DIPSETTING( 0x01, DEF_STR( 1C_5C ) )
r2864	r2865
928	929	PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) )
929	930	PORT_DIPSETTING( 0x00, DEF_STR( 1C_4C ) )
930	931
931		PORT_START /* DSW B - from "TEST NO.6 - dip switch B" */
	932	PORT_START_TAG("DSW1") /* DSW B - from "TEST NO.6 - dip switch B" */
932	933	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
933	934	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
934	935	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
953	954	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
954	955	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
955	956
956		PORT_START /* audio board DSW A */
	957	PORT_START_TAG("DSW2") /* audio board DSW A */
957	958	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
958	959	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
959	960	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
979	980	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
980	981	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
981	982
982		PORT_START /* audio board DSW B */
	983	PORT_START_TAG("DSW3") /* audio board DSW B */
983	984	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
984	985	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
985	986	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
1008	1009
1009	1010
1010	1011	static INPUT_PORTS_START( piratetr )
1011		PORT_START /* COL. A - from "TEST NO.7 - status locator - coin-door" */
	1012	PORT_START_TAG("IN0") /* COL. A - from "TEST NO.7 - status locator - coin-door" */
1012	1013	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
1013	1014	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
1014	1015	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_TILT )
r2864	r2865
1018	1019	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN2 )
1019	1020	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 )
1020	1021
1021		PORT_START /* COL. B - from "TEST NO.7 - status locator - start sws." */
	1022	PORT_START_TAG("IN1") /* COL. B - from "TEST NO.7 - status locator - start sws." */
1022	1023	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
1023	1024	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
1024	1025	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
1028	1029	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
1029	1030	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
1030	1031
1031		PORT_START /* COL. C - from "TEST NO.8 - status locator - player no.1" */
	1032	PORT_START_TAG("IN2") /* COL. C - from "TEST NO.8 - status locator - player no.1" */
1032	1033	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
1033	1034	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
1034	1035	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
1038	1039	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
1039	1040	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
1040	1041
1041		PORT_START /* COL. D - from "TEST NO.8 - status locator - player no.2" */
	1042	PORT_START_TAG("IN3") /* COL. D - from "TEST NO.8 - status locator - player no.2" */
1042	1043	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
1043	1044	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
1044	1045	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
1048	1049	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_COCKTAIL
1049	1050	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_COCKTAIL
1050	1051
1051		PORT_START /* DSW A - from "TEST NO.6 - dip switch A" */
	1052	PORT_START_TAG("DSW0") /* DSW A - from "TEST NO.6 - dip switch A" */
1052	1053	PORT_DIPNAME( 0x09, 0x09, DEF_STR( Coin_B ) )
1053	1054	PORT_DIPSETTING( 0x09, DEF_STR( 1C_1C ) )
1054	1055	PORT_DIPSETTING( 0x01, DEF_STR( 1C_5C ) )
r2864	r2865
1071	1072	PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) )
1072	1073	PORT_DIPSETTING( 0x00, DEF_STR( 1C_4C ) )
1073	1074
1074		PORT_START /* DSW B - from "TEST NO.6 - dip switch B" */
	1075	PORT_START_TAG("DSW1") /* DSW B - from "TEST NO.6 - dip switch B" */
1075	1076	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
1076	1077	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1077	1078	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
1096	1097	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1097	1098	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1098	1099
1099		PORT_START /* audio board DSW A */
	1100	PORT_START_TAG("DSW2") /* audio board DSW A */
1100	1101	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
1101	1102	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1102	1103	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
1122	1123	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1123	1124	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1124	1125
1125		PORT_START /* audio board DSW B */
	1126	PORT_START_TAG("DSW3") /* audio board DSW B */
1126	1127	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
1127	1128	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1128	1129	PORT_DIPSETTING( 0x00, DEF_STR( On ) )

src/mame/drivers/darius.c
r2864	r2865
127	127	***************************************************************************/
128	128
129	129	#include "driver.h"
130		#include "deprecat.h"
131	130	#include "video/taitoic.h"
132	131	#include "cpu/z80/z80.h"
133	132	#include "audio/taitosnd.h"
r2864	r2865
151	150	WRITE16_HANDLER( darius_fg_layer_w );
152	151
153	152
154		static void parse_control( void ) /* assumes Z80 sandwiched between 68Ks */
	153	static void parse_control( running_machine machine ) / assumes Z80 sandwiched between 68Ks */
155	154	{
156	155	/* bit 0 enables cpu B */
157	156	/* however this fails when recovering from a save state
158	157	if cpu B is disabled !! */
159		cpunum_set_input_line(Machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
	158	cpunum_set_input_line(machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
160	159
161	160	}
162	161
r2864	r2865
166	165	data = data >> 8; /* for Wgp */
167	166	cpua_ctrl = data;
168	167
169		parse_control();
	168	parse_control(machine);
170	169
171	170	logerror("CPU #0 PC %06x: write %04x to cpu control\n",activecpu_get_pc(),data);
172	171	}
r2864	r2865
189	188	return (taitosound_comm_r(machine,0) & 0xff); /* sound interface read */
190	189
191	190	case 0x04:
192		return input_port_read~~_indexed~~(machine,0); ~~/* IN0 */~~
	191	return input_port_read(machine, "P1");
193	192
194	193	case 0x05:
195		return input_port_read~~_indexed~~(machine,1); ~~/* IN1 */~~
	194	return input_port_read(machine, "P2");
196	195
197	196	case 0x06:
198		return input_port_read~~_indexed~~(machine,2); ~~/* IN2 */~~
	197	return input_port_read(machine, "SYSTEM");
199	198
200	199	case 0x07:
201	200	return coin_word; /* bits 3&4 coin lockouts, must return zero */
202	201
203	202	case 0x08:
204		return input_port_read~~_indexed~~(machine,3); /* DSW */
	203	return input_port_read(machine, "DSW");
205	204	}
206	205
207	206	logerror("CPU #0 PC %06x: warning - read unmapped ioc offset %06x\n",activecpu_get_pc(),offset);
r2864	r2865
612	611	PORT_DIPSETTING( 0x0100, DEF_STR( Hard ) ) \
613	612	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
614	613
615		#define DARIUS_PLAYERS_INPUT( player ) \
616		PORT_START \
617		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(player) PORT_8WAY \
618		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(player) PORT_8WAY \
619		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(player) PORT_8WAY \
620		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(player) PORT_8WAY \
621		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(player) \
622		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(player) \
623		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
	614
	615	static INPUT_PORTS_START( darius_common )
	616	PORT_START_TAG("P1")
	617	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1) PORT_8WAY
	618	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1) PORT_8WAY
	619	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1) PORT_8WAY
	620	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1) PORT_8WAY
	621	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
	622	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
	623	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
624	624	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
625	625
626		#define DARIUS_SYSTEM_INPUT \
627		PORT_START \
628		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 ) \
629		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 ) \
630		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 ) \
631		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 ) \
632		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 ) \
633		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_TILT ) \
634		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
	626	PORT_START_TAG("P2")
	627	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) PORT_8WAY
	628	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_8WAY
	629	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2) PORT_8WAY
	630	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2) PORT_8WAY
	631	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
	632	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
	633	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	634	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	635
	636	PORT_START_TAG("SYSTEM")
	637	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
	638	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )
	639	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
	640	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
	641	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 )
	642	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_TILT )
	643	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
635	644	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	645	INPUT_PORTS_END
636	646
637
638	647	static INPUT_PORTS_START( darius )
639		~~DARIUS_~~P~~LAYE~~RS_INPUT( 1 )
	648	PORT_INCLUDE( darius_common )
640	649
641		DARIUS_PLAYERS_INPUT( 2 )
642
643		DARIUS_SYSTEM_INPUT
644
645		PORT_START /* DSW */
	650	PORT_START_TAG("DSW") /* DSW */
646	651	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
647	652	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
648	653	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
674	679	INPUT_PORTS_END
675	680
676	681	static INPUT_PORTS_START( dariuse )
677		~~DARIUS_~~P~~LAYE~~RS_INPUT( 1 )
	682	PORT_INCLUDE( darius_common )
678	683
679		DARIUS_PLAYERS_INPUT( 2 )
680
681		DARIUS_SYSTEM_INPUT
682
683		PORT_START /* DSW */
	684	PORT_START_TAG("DSW") /* DSW */
684	685	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
685	686	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
686	687	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
712	713	INPUT_PORTS_END
713	714
714	715	static INPUT_PORTS_START( dariusj )
715		~~DARIUS_~~P~~LAYE~~RS_INPUT( 1 )
	716	PORT_INCLUDE( darius_common )
716	717
717		DARIUS_PLAYERS_INPUT( 2 )
718
719		DARIUS_SYSTEM_INPUT
720
721		PORT_START /* DSW */
	718	PORT_START_TAG("DSW") /* DSW */
722	719	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
723	720	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
724	721	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
1202	1199
1203	1200	static STATE_POSTLOAD( darius_postload )
1204	1201	{
1205		parse_control();
	1202	parse_control(machine);
1206	1203	reset_sound_region();
1207	1204	}
1208	1205

src/mame/drivers/kinst.c
r2864	r2865
330	330	static READ32_HANDLER( kinst_control_r )
331	331	{
332	332	UINT32 result;
	333	static const char *portnames[] = { "P1", "P2", "IN0", "IN1", "DSW" };
333	334
334	335	/* apply shuffling */
335	336	offset = control_map[offset / 2];
r2864	r2865
338	339	switch (offset)
339	340	{
340	341	case 2: /* $90 -- sound return */
341		result = 0xffff0000 \| input_port_read~~_indexed~~(machine, offset);
	342	result = 0xffff0000 \| input_port_read(machine, portnames[offset]);
342	343	result &= ~0x0002;
343	344	if (dcs_control_r() & 0x800)
344	345	result \|= 0x0002;
r2864	r2865
347	348	case 0: /* $80 */
348	349	case 1: /* $88 */
349	350	case 3: /* $98 */
350		result = 0xffff0000 \| input_port_read~~_indexed~~(machine, offset);
	351	result = 0xffff0000 \| input_port_read(machine, portnames[offset]);
351	352	break;
352	353
353	354	case 4: /* $a0 */
354		result = 0xffff0000 \| input_port_read~~_indexed~~(machine, offset);
	355	result = 0xffff0000 \| input_port_read(machine, portnames[offset]);
355	356	if (activecpu_get_pc() == 0x802d428)
356	357	cpu_spinuntil_int();
357	358	break;
r2864	r2865
452	453	*************************************/
453	454
454	455	static INPUT_PORTS_START( kinst )
455		PORT_START
	456	PORT_START_TAG("P1")
456	457	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
457	458	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
458	459	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
r2864	r2865
470	471	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_COIN4 )
471	472	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_SPECIAL ) /* door */
472	473
473		PORT_START
	474	PORT_START_TAG("P2")
474	475	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
475	476	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
476	477	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
r2864	r2865
488	489	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BILL1 ) /* bill */
489	490	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_SPECIAL ) /* coin door */
490	491
491		PORT_START
	492	PORT_START_TAG("IN0")
492	493	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
493	494	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* sound status */
494	495	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_VOLUME_UP )
495	496	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_VOLUME_DOWN )
496	497	PORT_BIT( 0xfff0, IP_ACTIVE_LOW, IPT_UNKNOWN )
497	498
498		PORT_START
	499	PORT_START_TAG("IN1")
499	500	PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED ) /* verify */
500	501
501		PORT_START
	502	PORT_START_TAG("DSW")
502	503	PORT_DIPNAME( 0x0003, 0x0003, "Blood Level" )
503	504	PORT_DIPSETTING( 0x0003, DEF_STR( High ))
504	505	PORT_DIPSETTING( 0x0002, DEF_STR( Medium ))
r2864	r2865
556	557
557	558
558	559	static INPUT_PORTS_START( kinst2 )
559		PORT_START
	560	PORT_START_TAG("P1")
560	561	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
561	562	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
562	563	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
r2864	r2865
574	575	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_COIN4 )
575	576	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_SPECIAL ) /* door */
576	577
577		PORT_START
	578	PORT_START_TAG("P2")
578	579	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
579	580	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
580	581	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
r2864	r2865
592	593	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BILL1 ) /* bill */
593	594	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_SPECIAL ) /* coin door */
594	595
595		PORT_START
	596	PORT_START_TAG("IN0")
596	597	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
597	598	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* sound status */
598	599	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_VOLUME_UP )
599	600	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_VOLUME_DOWN )
600	601	PORT_BIT( 0xfff0, IP_ACTIVE_LOW, IPT_UNKNOWN )
601	602
602		PORT_START
	603	PORT_START_TAG("IN1")
603	604	PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED ) /* verify */
604	605
605		PORT_START
	606	PORT_START_TAG("DSW")
606	607	PORT_DIPNAME( 0x0003, 0x0003, "Blood Level" )
607	608	PORT_DIPSETTING( 0x0003, DEF_STR( High ))
608	609	PORT_DIPSETTING( 0x0002, DEF_STR( Medium ))

src/mame/drivers/beathead.c
r2864	r2865
511	511	{
512	512	/* initialize the common systems */
513	513	atarigen_eeprom_default = NULL;
514		atarijsa_init(machine, 2, 0x0040);
	514	atarijsa_init(machine, "IN2", 0x0040);
515	515	atarijsa3_init_adpcm(REGION_SOUND1);
516	516
517	517	/* prepare the speedups */

src/mame/drivers/funkyjet.c
r2864	r2865
155	155	/******************************************************************************/
156	156
157	157	static INPUT_PORTS_START( funkyjet )
158		PORT_START /* Player 1 controls */
	158	PORT_START_TAG("P1") /* Player 1 controls */
159	159	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
160	160	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
161	161	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
165	165	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) /* Button 3 only in "test mode" */
166	166	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
167	167
168		PORT_START /* Player 2 controls */
	168	PORT_START_TAG("P2") /* Player 2 controls */
169	169	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
170	170	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
171	171	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
175	175	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) /* Button 3 only in "test mode" */
176	176	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
177	177
178		PORT_START /* System Inputs */
	178	PORT_START_TAG("IN0") /* System Inputs */
179	179	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
180	180	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
181	181	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
243	243	INPUT_PORTS_END
244	244
245	245	static INPUT_PORTS_START( sotsugyo )
246		PORT_START /* Player 1 controls */
	246	PORT_START_TAG("P1") /* Player 1 controls */
247	247	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
248	248	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
249	249	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
253	253	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) /* only in "test mode" */
254	254	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
255	255
256		PORT_START /* Player 2 controls */
	256	PORT_START_TAG("P2") /* Player 2 controls */
257	257	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
258	258	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
259	259	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
263	263	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) /* only in "test mode" */
264	264	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
265	265
266		PORT_START /* System Inputs */
	266	PORT_START_TAG("IN0") /* System Inputs */
267	267	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
268	268	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) // Not working - see notes
269	269	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 ) // See notes
r2864	r2865
271	271
272	272	/* Dips seem inverted with respect to other Deco games */
273	273
274		PORT_START /* Dip switch bank 1 */
	274	PORT_START_TAG("DSWA") /* Dip switch bank 1 */
275	275	PORT_DIPNAME( 0xe0, 0xe0, DEF_STR( Coin_A ) )
276	276	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
277	277	PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
r2864	r2865
295	295	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
296	296	PORT_SERVICE( 0x01, IP_ACTIVE_LOW )
297	297
298		PORT_START /* Dip switch bank 2 */
	298	PORT_START_TAG("DSWB") /* Dip switch bank 2 */
299	299	PORT_DIPNAME( 0x80, 0x80, "Freeze" )
300	300	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
301	301	PORT_DIPSETTING( 0x00, DEF_STR( On ) )

src/mame/drivers/xexex.c
r2864	r2865
145	145	#endif
146	146
147	147
148		static void xexex_objdma(int limiter)
	148	static void xexex_objdma(running_machine *machine, int limiter)
149	149	{
150	150	static int frame = -1;
151	151
r2864	r2865
153	153	UINT16 src, dst;
154	154
155	155	counter = frame;
156		frame = video_screen_get_frame_number(Machine->primary_screen);
	156	frame = video_screen_get_frame_number(machine->primary_screen);
157	157	if (limiter && counter == frame) return; // make sure we only do DMA transfer once per frame
158	158
159	159	K053247_export_config(&dst, 0, 0, 0, &counter);
r2864	r2865
328	328	if (K053246_is_IRQ_enabled())
329	329	{
330	330	// OBJDMA starts at the beginning of V-blank
331		xexex_objdma(0);
	331	xexex_objdma(machine, 0);
332	332
333	333	// schedule DMA end interrupt
334	334	timer_adjust_oneshot(dmadelay_timer, XE_DMADELAY, 0);

src/mame/drivers/skullxbo.c
r2864	r2865
96	96
97	97	static READ16_HANDLER( special_port1_r )
98	98	{
99		int temp = input_port_read~~_indexed~~(machine, 1);
	99	int temp = input_port_read(machine, "FF5802");
100	100	if (atarigen_cpu_to_sound_ready) temp ^= 0x0040;
101	101	if (atarigen_get_hblank(machine->primary_screen)) temp ^= 0x0010;
102	102	return temp;
r2864	r2865
164	164	*************************************/
165	165
166	166	static INPUT_PORTS_START( skullxbo )
167		PORT_START /* ff5800 */
	167	PORT_START_TAG("FF5800") /* ff5800 */
168	168	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
169	169	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
170	170	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
r2864	r2865
175	175	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
176	176	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
177	177
178		PORT_START /* ff5802 */
	178	PORT_START_TAG("FF5802") /* ff5802 */
179	179	PORT_BIT( 0x000f, IP_ACTIVE_LOW, IPT_UNUSED )
180	180	PORT_BIT( 0x0010, IP_ACTIVE_HIGH, IPT_UNUSED ) /* HBLANK */
181	181	PORT_BIT( 0x0020, IP_ACTIVE_HIGH, IPT_VBLANK )
r2864	r2865
618	618	static DRIVER_INIT( skullxbo )
619	619	{
620	620	atarigen_eeprom_default = NULL;
621		atarijsa_init(machine, 1, 0x0080);
	621	atarijsa_init(machine, "FF5802", 0x0080);
622	622	memset(memory_region(REGION_GFX1) + 0x170000, 0, 0x20000);
623	623	}
624	624

src/mame/drivers/jchan.c
r2864	r2865
302	302
303	303	case 0x03: // DSW
304	304	{
305		mcu_ram[mcu_offset] = input_port_read~~_indexed~~(machine, 3);
	305	mcu_ram[mcu_offset] = input_port_read(machine, "DSW");
306	306	logerror("PC=%06X : MCU executed command: %04X %04X (read DSW)\n",activecpu_get_pc(),mcu_command,mcu_offset*2);
307	307	}
308	308	break;
r2864	r2865
455	455	{
456	456	switch(offset)
457	457	{
458		case 0/2: return input_port_read_indexed(machine, 0); // Player 1 controls
459		case 2/2: return input_port_read_indexed(machine, 1); // Player 2 controls
	458	case 0/2: return input_port_read(machine, "IN0"); // Player 1 controls
	459	case 2/2: return input_port_read(machine, "IN1"); // Player 2 controls
460	460	default: logerror("jchan_ctrl_r unknown!"); break;
461	461	}
462	462	return jchan_ctrl[offset];
r2864	r2865
704	704	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SERVICE1 )
705	705	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
706	706
707		PORT_START_TAG("~~IN3~~") // DSW provided by the MCU - $200098.b <- $300200
	707	PORT_START_TAG("DSW") // DSW provided by the MCU - $200098.b <- $300200
708	708	PORT_DIPNAME( 0x0100, 0x0100, "Test Mode" )
709	709	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
710	710	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )

src/mame/drivers/seattle.c
r2864	r2865
183	183	**************************************************************************/
184	184
185	185	#include "driver.h"
186		#include "deprecat.h"
187	186	#include "cpu/adsp2100/adsp2100.h"
188	187	#include "cpu/mips/mips3.h"
189	188	#include "audio/dcs.h"
r2864	r2865
471	470	static TIMER_CALLBACK( galileo_timer_callback );
472	471	static void galileo_perform_dma(running_machine *machine, int which);
473	472	static void voodoo_stall(running_machine *machine, int stall);
474		static void widget_reset(void);
	473	static void widget_reset(running_machine *machine);
475	474	static void update_widget_irq(running_machine *machine);
476	475
477	476
r2864	r2865
569	568	devtag_reset(machine, IDE_CONTROLLER, "ide");
570	569	voodoo_reset(0);
571	570	if (board_config == SEATTLE_WIDGET_CONFIG)
572		widget_reset();
	571	widget_reset(machine);
573	572	if (board_config == FLAGSTAFF_CONFIG)
574	573	smc91c94_reset(machine);
575	574	}
r2864	r2865
927	926	*
928	927	*************************************/
929	928
930		static int galileo_dma_fetch_next(int which)
	929	static int galileo_dma_fetch_next(running_machine *machine, int which)
931	930	{
932	931	offs_t address = 0;
933	932	UINT32 data;
r2864	r2865
942	941	if (galileo.reg[GREG_DMA0_CONTROL + which] & 0x400)
943	942	{
944	943	galileo.reg[GREG_INT_STATE] \|= 1 << (GINT_DMA0COMP_SHIFT + which);
945		update_galileo_irqs(Machine);
	944	update_galileo_irqs(machine);
946	945	}
947	946	galileo.reg[GREG_DMA0_CONTROL + which] &= ~0x5000;
948	947	return 0;
r2864	r2865
1053	1052	galileo.reg[GREG_INT_STATE] \|= 1 << (GINT_DMA0COMP_SHIFT + which);
1054	1053	update_galileo_irqs(machine);
1055	1054	}
1056		} while (galileo_dma_fetch_next(which));
	1055	} while (galileo_dma_fetch_next(machine, which));
1057	1056
1058	1057	galileo.reg[GREG_DMA0_CONTROL + which] &= ~0x5000;
1059	1058	}
r2864	r2865
1177	1176
1178	1177	/* fetch next record */
1179	1178	if (data & 0x2000)
1180		galileo_dma_fetch_next(which);
	1179	galileo_dma_fetch_next(machine, which);
1181	1180	galileo.reg[offset] &= ~0x2000;
1182	1181
1183	1182	/* if enabling, start the DMA */
r2864	r2865
1489	1488	*
1490	1489	*************************************/
1491	1490
1492		static void widget_reset(void)
	1491	static void widget_reset(running_machine *machine)
1493	1492	{
1494	1493	UINT8 saved_irq = widget.irq_num;
1495	1494	memset(&widget, 0, sizeof(widget));
1496	1495	widget.irq_num = saved_irq;
1497		smc91c94_reset(Machine);
	1496	smc91c94_reset(machine);
1498	1497	}
1499	1498
1500	1499
r2864	r2865
1617	1616	{
1618	1617	COMBINE_DATA(asic_reset);
1619	1618	if (!(*asic_reset & 0x0002))
1620		midway_ioasic_reset();
	1619	midway_ioasic_reset(machine);
1621	1620	}
1622	1621
1623	1622
1624	1623	static WRITE32_HANDLER( asic_fifo_w )
1625	1624	{
1626		midway_ioasic_fifo_w(data);
	1625	midway_ioasic_fifo_w(machine, data);
1627	1626	}
1628	1627
1629	1628
r2864	r2865
2725	2724	static void init_common(running_machine *machine, int ioasic, int serialnum, int yearoffs, int config)
2726	2725	{
2727	2726	/* initialize the subsystems */
2728		midway_ioasic_init(ioasic, serialnum, yearoffs, ioasic_irq);
	2727	midway_ioasic_init(machine, ioasic, serialnum, yearoffs, ioasic_irq);
2729	2728
2730	2729	/* switch off the configuration */
2731	2730	board_config = config;

src/mame/drivers/funkybee.c
r2864	r2865
88	88
89	89	static READ8_HANDLER( funkybee_input_port_0_r )
90	90	{
91		watchdog_reset_r(machine,0);
92		return input_port_read_indexed(machine,0);
	91	watchdog_reset_r(machine, 0);
	92	return input_port_read(machine, "IN0");
93	93	}
94	94
95	95	static WRITE8_HANDLER( funkybee_coin_counter_w )
r2864	r2865
103	103	AM_RANGE(0xa000, 0xdfff) AM_READ(SMH_RAM)
104	104	AM_RANGE(0xf000, 0xf000) AM_READ(SMH_NOP) /* IRQ Ack */
105	105	AM_RANGE(0xf800, 0xf800) AM_READ(funkybee_input_port_0_r)
106		AM_RANGE(0xf801, 0xf801) AM_READ(input_port_1_r)
107		AM_RANGE(0xf802, 0xf802) AM_READ(input_port_2_r)
	106	AM_RANGE(0xf801, 0xf801) AM_READ_PORT("IN1")
	107	AM_RANGE(0xf802, 0xf802) AM_READ_PORT("IN2")
108	108	ADDRESS_MAP_END
109	109
110	110	static ADDRESS_MAP_START( writemem, ADDRESS_SPACE_PROGRAM, 8 )

src/mame/drivers/freekick.c
r2864	r2865
93	93
94	94	static READ8_HANDLER( spinner_r )
95	95	{
96		return input_port_read~~_indexed~~(machine, ~~5 +~~ spinner);
	96	return input_port_read(machine, spinner ? "IN3" : "IN2");
97	97	}
98	98
99		static READ8_HANDLER( gigas_spinner_r )
100		{
101		return input_port_read_indexed(machine, spinner );
102		}
103
104	99	static MACHINE_RESET( pbillrd )
105	100	{
106	101	memory_configure_bank(1, 0, 2, memory_region(REGION_CPU1) + 0x10000, 0x4000);
r2864	r2865
194	189	AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM)
195	190	AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1)
196	191	AM_RANGE(0xc000, 0xdfff) AM_READ(SMH_RAM)
197		AM_RANGE(0xe000, 0xe000) AM_READ(input_port_0_r)
198		AM_RANGE(0xe800, 0xe800) AM_READ(input_port_1_r)
199		AM_RANGE(0xf000, 0xf000) AM_READ(input_port_2_r)
200		AM_RANGE(0xf800, 0xf800) AM_READ(input_port_3_r)
	192	AM_RANGE(0xe000, 0xe000) AM_READ_PORT("IN0")
	193	AM_RANGE(0xe800, 0xe800) AM_READ_PORT("IN1")
	194	AM_RANGE(0xf000, 0xf000) AM_READ_PORT("DSW1")
	195	AM_RANGE(0xf800, 0xf800) AM_READ_PORT("DSW2")
201	196	ADDRESS_MAP_END
202	197
203	198	static ADDRESS_MAP_START( pbillrd_writemem, ADDRESS_SPACE_PROGRAM, 8 )
r2864	r2865
223	218	AM_RANGE(0xe800, 0xe8ff) AM_READ(SMH_RAM) // sprites
224	219	AM_RANGE(0xec00, 0xec03) AM_DEVREAD(PPI8255, "ppi8255_0", ppi8255_r)
225	220	AM_RANGE(0xf000, 0xf003) AM_DEVREAD(PPI8255, "ppi8255_1", ppi8255_r)
226		AM_RANGE(0xf800, 0xf800) AM_READ(input_port_3_r)
227		AM_RANGE(0xf801, 0xf801) AM_READ(input_port_4_r)
	221	AM_RANGE(0xf800, 0xf800) AM_READ_PORT("IN0")
	222	AM_RANGE(0xf801, 0xf801) AM_READ_PORT("IN1")
228	223	AM_RANGE(0xf802, 0xf802) AM_READ(SMH_NOP) //MUST return bit 0 = 0, otherwise game resets
229	224	AM_RANGE(0xf803, 0xf803) AM_READ(spinner_r)
230	225	ADDRESS_MAP_END
r2864	r2865
250	245	AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM)
251	246	AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_ROM)
252	247	AM_RANGE(0xc000, 0xdfff) AM_READ(SMH_RAM)
253		AM_RANGE(0xe000, 0xe000) AM_READ(input_port_2_r)
254		AM_RANGE(0xe800, 0xe800) AM_READ(input_port_3_r)
255		AM_RANGE(0xf000, 0xf000) AM_READ(input_port_4_r)
256		AM_RANGE(0xf800, 0xf800) AM_READ(input_port_5_r)
	248	AM_RANGE(0xe000, 0xe000) AM_READ_PORT("IN0")
	249	AM_RANGE(0xe800, 0xe800) AM_READ_PORT("IN1")
	250	AM_RANGE(0xf000, 0xf000) AM_READ_PORT("DSW1")
	251	AM_RANGE(0xf800, 0xf800) AM_READ_PORT("DSW2")
257	252	ADDRESS_MAP_END
258	253
259	254	static ADDRESS_MAP_START( gigas_writemem, ADDRESS_SPACE_PROGRAM, 8 )
r2864	r2865
275	270
276	271	static ADDRESS_MAP_START( gigas_readport, ADDRESS_SPACE_IO, 8 )
277	272	ADDRESS_MAP_GLOBAL_MASK(0xff)
278		AM_RANGE(0x00, 0x00) AM_READ(~~gigas_~~spinner_r)
	273	AM_RANGE(0x00, 0x00) AM_READ(spinner_r)
279	274	AM_RANGE(0x01, 0x01) AM_READ(SMH_NOP) //unused dip 3
280	275	ADDRESS_MAP_END
281	276
r2864	r2865
286	281
287	282	static ADDRESS_MAP_START( oigas_readport, ADDRESS_SPACE_IO, 8 )
288	283	ADDRESS_MAP_GLOBAL_MASK(0xff)
289		AM_RANGE(0x00, 0x00) AM_READ(~~gigas_~~spinner_r)
	284	AM_RANGE(0x00, 0x00) AM_READ(spinner_r)
290	285	AM_RANGE(0x01, 0x01) AM_READ(SMH_NOP) //unused dip 3
291	286	AM_RANGE(0x02, 0x02) AM_READ(oigas_2_r)
292	287	AM_RANGE(0x03, 0x03) AM_READ(oigas_3_r)

src/mame/drivers/namcos22.c
r2864	r2865
1225	1225	/*********************************************************************************************/
1226	1226
1227	1227	static void
1228		InitDSP( int bSuperSystem22 )
	1228	InitDSP( running_machine *machine, int bSuperSystem22 )
1229	1229	{
1230	1230	mbSuperSystem22 = bSuperSystem22;
1231		cpunum_set_input_line(Machine, 1,INPUT_LINE_RESET,ASSERT_LINE); /* master DSP */
1232		cpunum_set_input_line(Machine, 2,INPUT_LINE_RESET,ASSERT_LINE); /* slave DSP */
1233		cpunum_set_input_line(Machine, 3,INPUT_LINE_RESET,ASSERT_LINE); /* MCU */
	1231	cpunum_set_input_line(machine, 1,INPUT_LINE_RESET,ASSERT_LINE); /* master DSP */
	1232	cpunum_set_input_line(machine, 2,INPUT_LINE_RESET,ASSERT_LINE); /* slave DSP */
	1233	cpunum_set_input_line(machine, 3,INPUT_LINE_RESET,ASSERT_LINE); /* MCU */
1234	1234	} /* InitDSP */
1235	1235
1236	1236	static READ16_HANDLER( pdp_status_r )
r2864	r2865
1408	1408	COMBINE_DATA( &mpSlaveExternalRAM[offset] );
1409	1409	}
1410	1410
1411		static void HaltSlaveDSP( void )
	1411	static void HaltSlaveDSP( running_machine *machine )
1412	1412	{
1413		cpunum_set_input_line(Machine, 2, INPUT_LINE_RESET, ASSERT_LINE);
	1413	cpunum_set_input_line(machine, 2, INPUT_LINE_RESET, ASSERT_LINE);
1414	1414	}
1415	1415
1416	1416	static void EnableSlaveDSP( void )
r2864	r2865
1495	1495	logerror( "UPLOAD_READY; cmd = 0x%x\n", data );
1496	1496	if( data==0 )
1497	1497	{
1498		HaltSlaveDSP();
	1498	HaltSlaveDSP(machine);
1499	1499	}
1500	1500	else if( data==1 )
1501	1501	{
r2864	r2865
2333	2333
2334	2334	static MACHINE_RESET(namcoss22)
2335	2335	{
2336		InitDSP(1/super/);
	2336	InitDSP(machine, 1/super/);
2337	2337	}
2338	2338
2339	2339	/*
r2864	r2865
3071	3071
3072	3072	static MACHINE_RESET(namcos22)
3073	3073	{
3074		InitDSP(0);
	3074	InitDSP(machine, 0);
3075	3075	}
3076	3076
3077	3077	static MACHINE_DRIVER_START( namcos22 )

src/mame/drivers/flyball.c
r2864	r2865
41	41
42	42	memset(potsense, 0, sizeof potsense);
43	43
44		potsense[input_port_read_indexed(machine, 1)] \|= 1;
45		potsense[input_port_read_indexed(machine, 2)] \|= 2;
46		potsense[input_port_read_indexed(machine, 3)] \|= 4;
47		potsense[input_port_read_indexed(machine, 4)] \|= 8;
	44	potsense[input_port_read(machine, "STICK1_Y")] \|= 1;
	45	potsense[input_port_read(machine, "STICK1_X")] \|= 2;
	46	potsense[input_port_read(machine, "STICK0_Y")] \|= 4;
	47	potsense[input_port_read(machine, "STICK0_X")] \|= 8;
48	48
49	49	for (i = 0; i < 64; i++)
50	50	if (potsense[i] != 0)
r2864	r2865
79	79
80	80	static READ8_HANDLER( flyball_input_r )
81	81	{
82		return input_port_read~~_indexed~~(machine, 0) & input_port_read~~_indexed~~(machine, 5);
	82	return input_port_read(machine, "IN0") & input_port_read(machine, "IN1");
83	83	}
84	84
85	85	static READ8_HANDLER( flyball_scanline_r )
r2864	r2865
170	170
171	171
172	172	static INPUT_PORTS_START( flyball )
173		PORT_START /* IN0 */
	173	PORT_START_TAG("IN0") /* IN0 */
174	174	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
175	175	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
176	176	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
186	186	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
187	187	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
188	188
189		PORT_START /* IN1 */
	189	PORT_START_TAG("STICK1_Y") /* IN1 */
190	190	PORT_BIT( 0x3f, 0x20, IPT_AD_STICK_Y ) PORT_MINMAX(1,63) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(2)
191	191
192		PORT_START /* IN2 */
	192	PORT_START_TAG("STICK1_X") /* IN2 */
193	193	PORT_BIT( 0x3f, 0x20, IPT_AD_STICK_X ) PORT_MINMAX(1,63) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(2)
194	194
195		PORT_START /* IN3 */
	195	PORT_START_TAG("STICK0_Y") /* IN3 */
196	196	PORT_BIT( 0x3f, 0x20, IPT_AD_STICK_Y ) PORT_MINMAX(1,63) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(1)
197	197
198		PORT_START /* IN4 */
	198	PORT_START_TAG("STICK0_X") /* IN4 */
199	199	PORT_BIT( 0x3f, 0x20, IPT_AD_STICK_X ) PORT_MINMAX(1,63) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(1)
200	200
201		PORT_START /* IN5 */
	201	PORT_START_TAG("IN1") /* IN5 */
202	202	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
203	203	PORT_BIT( 0xFE, IP_ACTIVE_LOW, IPT_UNUSED )
204	204	INPUT_PORTS_END

src/mame/drivers/xybots.c
r2864	r2865
66	66	{
67	67	static int h256 = 0x0400;
68	68
69		int result = input_port_read~~_indexed~~(machine, 1);
	69	int result = input_port_read(machine, "FFE200");
70	70
71	71	if (atarigen_cpu_to_sound_ready) result ^= 0x0200;
72	72	result ^= h256 ^= 0x0400;
r2864	r2865
112	112	*************************************/
113	113
114	114	static INPUT_PORTS_START( xybots )
115		PORT_START /* ffe100 */
	115	PORT_START_TAG("FFE100") /* ffe100 */
116	116	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_START2 )
117	117	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
118	118	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("P2 Twist Right") PORT_CODE(KEYCODE_W) PORT_PLAYER(2)
r2864	r2865
130	130	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
131	131	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
132	132
133		PORT_START /* ffe200 */
	133	PORT_START_TAG("FFE200") /* ffe200 */
134	134	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
135	135	PORT_SERVICE( 0x0100, IP_ACTIVE_LOW )
136	136	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNUSED ) /* /AUDBUSY */
r2864	r2865
388	388	static DRIVER_INIT( xybots )
389	389	{
390	390	atarigen_eeprom_default = NULL;
391		atarigen_slapstic_init(0, 0x008000, 0, 107);
392		atarijsa_init(machine, 1, 0x0100);
	391	atarigen_slapstic_init(machine, 0, 0x008000, 0, 107);
	392	atarijsa_init(machine, "FFE200", 0x0100);
393	393	}
394	394
395	395

src/mame/drivers/galaxold.c
r2864	r2865
546	546
547	547
548	548	static READ8_HANDLER( scramb2_protection_r ) { return 0x25; }
549		static READ8_HANDLER( scramb2_port0_r ) { return (input_port_read_indexed(machine, 0)>>offset)&0x1; }
550		static READ8_HANDLER( scramb2_port1_r ) { return (input_port_read_indexed(machine, 1)>>offset)&0x1; }
551		static READ8_HANDLER( scramb2_port2_r ) { return (input_port_read_indexed(machine, 2)>>offset)&0x1; }
	549	static READ8_HANDLER( scramb2_port0_r ) { return (input_port_read(machine, "IN0") >> offset) & 0x1; }
	550	static READ8_HANDLER( scramb2_port1_r ) { return (input_port_read(machine, "IN1") >> offset) & 0x1; }
	551	static READ8_HANDLER( scramb2_port2_r ) { return (input_port_read(machine, "IN2") >> offset) & 0x1; }
552	552
553	553	static ADDRESS_MAP_START( scramb2_readmem, ADDRESS_SPACE_PROGRAM, 8 )
554	554	AM_RANGE(0x0000, 0x3fff) AM_READ(SMH_ROM)
r2864	r2865
977	977	AM_RANGE(S2650_SENSE_PORT, S2650_SENSE_PORT) AM_READ(input_port_3_r)
978	978	ADDRESS_MAP_END
979	979
980		#define GAL_IN0\
981		PORT_START_TAG("IN0")\
982		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )\
983		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )\
984		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_2WAY\
985		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_2WAY\
986		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )\
987		PORT_DIPNAME( 0x20, 0x00, DEF_STR( Cabinet ) )\
988		PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )\
989		PORT_DIPSETTING( 0x20, DEF_STR( Cocktail ) )\
990		PORT_SERVICE( 0x40, IP_ACTIVE_HIGH )\
991		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SERVICE1 )
992	980
993		#define GAL_IN1\
994		PORT_START_TAG("IN1")\
995		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )\
996		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )\
997		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_2WAY PORT_COCKTAIL\
998		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_2WAY PORT_COCKTAIL\
999		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL\
1000		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED )\
1001		PORT_DIPNAME( 0xc0, 0x00, DEF_STR( Coinage ) )\
1002		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) )\
1003		PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )\
1004		PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )\
1005		PORT_DIPSETTING( 0xc0, DEF_STR( Free_Play ) )
1006
1007	981	static INPUT_PORTS_START( scramblb )
1008	982	PORT_START_TAG("IN0")
1009	983	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
r2864	r2865
1089	1063	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1090	1064	INPUT_PORTS_END
1091	1065
1092
1093		#define MOON_IN0\
1094		PORT_START_TAG("IN0")\
1095		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )\
1096		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )\
1097		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_2WAY\
1098		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_2WAY\
1099		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )\
1100		PORT_DIPNAME( 0x20, 0x00, DEF_STR( Cabinet ) )\
1101		PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )\
1102		PORT_DIPSETTING( 0x20, DEF_STR( Cocktail ) )\
1103		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN ) /* "reset" on schematics */\
1104		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
1105
1106	1066	static INPUT_PORTS_START( 4in1 )
1107	1067	PORT_START_TAG("IN0")
1108	1068	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )

src/mame/drivers/atarisy1.c
r2864	r2865
2101	2101	via_config(0, &via_interface);
2102	2102
2103	2103	atarigen_eeprom_default = NULL;
2104		atarigen_slapstic_init(0, 0x080000, 0, 103);
	2104	atarigen_slapstic_init(machine, 0, 0x080000, 0, 103);
2105	2105
2106	2106	joystick_type = 0; /* none */
2107	2107	trackball_type = 1; /* rotated */
r2864	r2865
2113	2113	via_config(0, &via_interface);
2114	2114
2115	2115	atarigen_eeprom_default = NULL;
2116		atarigen_slapstic_init(0, 0x080000, 0, 107);
	2116	atarigen_slapstic_init(machine, 0, 0x080000, 0, 107);
2117	2117
2118	2118	joystick_type = 1; /* digital */
2119	2119	trackball_type = 0; /* none */
r2864	r2865
2125	2125	via_config(0, &via_interface);
2126	2126
2127	2127	atarigen_eeprom_default = NULL;
2128		atarigen_slapstic_init(0, 0x080000, 0, 105);
	2128	atarigen_slapstic_init(machine, 0, 0x080000, 0, 105);
2129	2129
2130	2130	joystick_type = 1; /* digital */
2131	2131	trackball_type = 0; /* none */
r2864	r2865
2137	2137	via_config(0, &via_interface);
2138	2138
2139	2139	atarigen_eeprom_default = NULL;
2140		atarigen_slapstic_init(0, 0x080000, 0, 108);
	2140	atarigen_slapstic_init(machine, 0, 0x080000, 0, 108);
2141	2141
2142	2142	joystick_type = 2; /* analog */
2143	2143	trackball_type = 0; /* none */
r2864	r2865
2149	2149	via_config(0, &via_interface);
2150	2150
2151	2151	atarigen_eeprom_default = NULL;
2152		atarigen_slapstic_init(0, 0x080000, 0, 109);
	2152	atarigen_slapstic_init(machine, 0, 0x080000, 0, 109);
2153	2153
2154	2154	joystick_type = 3; /* pedal */
2155	2155	trackball_type = 2; /* steering wheel */
r2864	r2865
2161	2161	via_config(0, &via_interface);
2162	2162
2163	2163	atarigen_eeprom_default = NULL;
2164		atarigen_slapstic_init(0, 0x080000, 0, 110);
	2164	atarigen_slapstic_init(machine, 0, 0x080000, 0, 110);
2165	2165
2166	2166	joystick_type = 3; /* pedal */
2167	2167	trackball_type = 2; /* steering wheel */

src/mame/drivers/wgp.c
r2864	r2865
394	394	***************************************************************************/
395	395
396	396	#include "driver.h"
397		#include "deprecat.h"
398	397	#include "taitoipt.h"
399	398	#include "cpu/m68000/m68000.h"
400	399	#include "video/taitoic.h"
r2864	r2865
433	432	COMBINE_DATA(&sharedram[offset]);
434	433	}
435	434
436		static void parse_control(void)
	435	static void parse_control(running_machine *machine)
437	436	{
438	437	/* bit 0 enables cpu B */
439	438	/* however this fails when recovering from a save state
440	439	if cpu B is disabled !! */
441		cpunum_set_input_line(Machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
	440	cpunum_set_input_line(machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
442	441
443	442	/* bit 1 is "vibration" acc. to test mode */
444	443	}
r2864	r2865
449	448	data = data >> 8; /* for Wgp */
450	449	cpua_ctrl = data;
451	450
452		parse_control();
	451	parse_control(machine);
453	452
454	453	logerror("CPU #0 PC %06x: write %04x to cpu control\n",activecpu_get_pc(),data);
455	454	}
r2864	r2865
937	936
938	937	static STATE_POSTLOAD( wgp_postload )
939	938	{
940		parse_control();
	939	parse_control(machine);
941	940	reset_sound_region();
942	941	}
943	942

src/mame/drivers/sprint8.c
r2864	r2865
5	5	***************************************************************************/
6	6
7	7	#include "driver.h"
8		#include "deprecat.h"
9	8	#include "includes/sprint8.h"
10	9
11	10	static int steer_dir[8];
r2864	r2865
15	14	static int collision_index;
16	15
17	16
18		void sprint8_set_collision(int n)
	17	void sprint8_set_collision(running_machine *machine, int n)
19	18	{
20	19	if (collision_reset == 0)
21	20	{
22		cpunum_set_input_line(Machine, 0, 0, ASSERT_LINE);
	21	cpunum_set_input_line(machine, 0, 0, ASSERT_LINE);
23	22
24	23	collision_index = n;
25	24	}

src/mame/drivers/getrivia.c
r2864	r2865
121	121
122	122	static READ8_HANDLER( port1_r )
123	123	{
124		return input_port_read~~_indexed~~(machine, 1) \| (ticket_dispenser_0_r(machine, 0) >> 5);
	124	return input_port_read(machine, "IN0") \| (ticket_dispenser_0_r(machine, 0) >> 5);
125	125	}
126	126
127	127	static WRITE8_HANDLER( lamps_w )
r2864	r2865
301	301
302	302
303	303	static INPUT_PORTS_START( gselect )
304		PORT_START /* DSW A */
	304	PORT_START_TAG("DSWA")
305	305	PORT_DIPNAME( 0x01, 0x01, "Poker: Discard Cards" )
306	306	PORT_DIPSETTING( 0x01, "5" )
307	307	PORT_DIPSETTING( 0x00, "3" )
r2864	r2865
336	336	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
337	337	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON9 ) PORT_IMPULSE(2) PORT_NAME ("Play / Raise")
338	338
339		PORT_START /* IN1 */
	339	PORT_START_TAG("IN1")
340	340	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_IMPULSE(2)
341	341	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_IMPULSE(2)
342	342	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_IMPULSE(2)
r2864	r2865
347	347	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON7 ) PORT_IMPULSE(2) PORT_NAME ("Stand")
348	348	/* Button 8, 6, 7 order verified in test mode switch test */
349	349
350		PORT_START
	350	PORT_START_TAG("IN2")
351	351	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
352	352	INPUT_PORTS_END
353	353
r2864	r2865
397	397	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
398	398	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
399	399
400		PORT_START /* IN1 */
	400	PORT_START_TAG("IN1")
401	401	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
402	402	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
403	403	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 )

src/mame/drivers/dec0.c
r2864	r2865
72	72	break;
73	73
74	74	case 6: /* Intel 8751 microcontroller - Bad Dudes, Heavy Barrel, Birdy Try only */
75		dec0_i8751_write(data);
	75	dec0_i8751_write(machine, data);
76	76	break;
77	77
78	78	case 8: /* Interrupt ack (VBL - IRQ 6) */
r2864	r2865
696	696	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
697	697	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
698	698
699		PORT_START_TAG("DSW1")
	699	PORT_START_TAG("DSW0")
700	700	DEC0_COIN_SETTING
701	701	PORT_SERVICE( 0x10, IP_ACTIVE_LOW )
702	702	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) )
r2864	r2865
709	709	PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
710	710	PORT_DIPSETTING( 0x80, DEF_STR( Cocktail ) )
711	711
712		PORT_START_TAG("DSW2")
	712	PORT_START_TAG("DSW1")
713	713	PORT_DIPNAME( 0x03, 0x03, "Energy" )
714	714	PORT_DIPSETTING( 0x02, DEF_STR( Low ) )
715	715	PORT_DIPSETTING( 0x03, DEF_STR( Medium ) )

src/mame/drivers/atarig42.c
r2864	r2865
111	111	if (ACCESSING_BITS_8_15)
112	112	{
113	113	/* bit 14 controls the ASIC65 reset line */
114		asic65_reset((~data >> 14) & 1);
	114	asic65_reset(machine, (~data >> 14) & 1);
115	115
116	116	/* bits 13-11 are the MO control bits */
117	117	atarirle_control_w(machine, 0, (data >> 11) & 7);
r2864	r2865
689	689	0x0118,0x0100,0x01C8,0x01D0,0x0000
690	690	};
691	691	atarigen_eeprom_default = default_eeprom;
692		atarijsa_init(machine, 2, 0x0040);
	692	atarijsa_init(machine, "IN2", 0x0040);
693	693	atarijsa3_init_adpcm(REGION_SOUND1);
694	694
695	695	atarig42_playfield_base = 0x400;
r2864	r2865
699	699	sloop_base = memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x000000, 0x07ffff, 0, 0, roadriot_sloop_data_r, roadriot_sloop_data_w);
700	700	memory_set_opbase_handler(0, sloop_opbase_handler);
701	701
702		asic65_config(ASIC65_ROMBASED);
	702	asic65_config(machine, ASIC65_ROMBASED);
703	703	/*
704	704	Road Riot color MUX
705	705
r2864	r2865
739	739	0x0109,0x0100,0x0108,0x0134,0x0105,0x0148,0x1400,0x0000
740	740	};
741	741	atarigen_eeprom_default = default_eeprom;
742		atarijsa_init(machine, 2, 0x0040);
	742	atarijsa_init(machine, "IN2", 0x0040);
743	743	atarijsa3_init_adpcm(REGION_SOUND1);
744	744
745	745	atarig42_playfield_base = 0x000;
r2864	r2865
753	753	sloop_base = memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x000000, 0x07ffff, 0, 0, guardians_sloop_data_r, guardians_sloop_data_w);
754	754	memory_set_opbase_handler(0, sloop_opbase_handler);
755	755
756		asic65_config(ASIC65_GUARDIANS);
	756	asic65_config(machine, ASIC65_GUARDIANS);
757	757	/*
758	758	Guardians color MUX
759	759

src/mame/drivers/vindictr.c
r2864	r2865
111	111	*************************************/
112	112
113	113	static INPUT_PORTS_START( vindictr )
114		PORT_START_TAG("26000")
	114	PORT_START_TAG("260000")
115	115	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
116	116	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
117	117	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
r2864	r2865
122	122	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) PORT_2WAY PORT_PLAYER(1)
123	123	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_DOWN ) PORT_2WAY PORT_PLAYER(1)
124	124
125		PORT_START_TAG("26010")
	125	PORT_START_TAG("260010")
126	126	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_VBLANK )
127	127	PORT_SERVICE( 0x0002, IP_ACTIVE_LOW )
128	128	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
138	138	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) PORT_2WAY PORT_PLAYER(2)
139	139	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_DOWN ) PORT_2WAY PORT_PLAYER(2)
140	140
141		PORT_START_TAG("26020")
	141	PORT_START_TAG("260020")
142	142	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
143	143	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
144	144	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_START2 )
r2864	r2865
541	541	static DRIVER_INIT( vindictr )
542	542	{
543	543	atarigen_eeprom_default = NULL;
544		atarijsa_init(machine, 1, 0x0002);
	544	atarijsa_init(machine, "260010", 0x0002);
545	545	}
546	546
547	547

src/mame/drivers/hanaawas.c
r2864	r2865
47	47	switch( mux )
48	48	{
49	49	case 1: /* start buttons */
50		buttons = input_port_read~~_indexed~~(machine, 4);
	50	buttons = input_port_read(machine, "START");
51	51	break;
52	52	case 2: /* player 1 buttons */
53		buttons = input_port_read~~_indexed~~(machine, 2);
	53	buttons = input_port_read(machine, "P1");
54	54	break;
55	55	case 4: /* player 2 buttons */
56		buttons = input_port_read~~_indexed~~(machine, 3);
	56	buttons = input_port_read(machine, "P2");
57	57	break;
58	58	}
59	59
r2864	r2865
69	69	}
70	70	}
71	71
72		return (input_port_read~~_indexed~~(machine, 0) & 0xf0) \| ordinal;
	72	return (input_port_read(machine, "IN0") & 0xf0) \| ordinal;
73	73	}
74	74
75	75	static WRITE8_HANDLER( hanaawas_inputs_mux_w )
r2864	r2865
109	109
110	110
111	111	static INPUT_PORTS_START( hanaawas )
112		PORT_START /* IN0 */
	112	PORT_START_TAG("IN0") /* IN0 */
113	113	PORT_BIT( 0x0f, IP_ACTIVE_HIGH, IPT_SPECIAL )
114	114	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN )
115	115	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
116	116	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
117	117	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
118	118
119		PORT_START /* DSW0 */
	119	PORT_START_TAG("DSW") /* DSW0 */
120	120	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ) )
121	121	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
122	122	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
141	141	PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
142	142
143	143	/* fake port. The button depressed gets converted to an integer in the 1-10 range */
144		PORT_START /* IN2 */
	144	PORT_START_TAG("P1") /* IN2 */
145	145	PORT_BIT( 0x001, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(1)
146	146	PORT_BIT( 0x002, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(1)
147	147	PORT_BIT( 0x004, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(1)
r2864	r2865
154	154	PORT_BIT( 0x200, IP_ACTIVE_HIGH, IPT_BUTTON10 ) PORT_PLAYER(1)
155	155
156	156	/* fake port. The button depressed gets converted to an integer in the 1-10 range */
157		PORT_START /* IN3 */
	157	PORT_START_TAG("P2") /* IN3 */
158	158	PORT_BIT( 0x001, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2)
159	159	PORT_BIT( 0x002, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(2)
160	160	PORT_BIT( 0x004, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(2)
r2864	r2865
166	166	PORT_BIT( 0x100, IP_ACTIVE_HIGH, IPT_BUTTON9 ) PORT_PLAYER(2)
167	167	PORT_BIT( 0x200, IP_ACTIVE_HIGH, IPT_BUTTON10 ) PORT_PLAYER(2)
168	168
169		PORT_START /* IN4 */
	169	PORT_START_TAG("START") /* IN4 */
170	170	PORT_BIT( 0x001, IP_ACTIVE_HIGH, IPT_START1 )
171	171	PORT_BIT( 0x002, IP_ACTIVE_HIGH, IPT_START2 )
172	172	INPUT_PORTS_END

src/mame/drivers/hshavoc.c
r2864	r2865
41	41
42	42
43	43	static INPUT_PORTS_START( hshavoc )
44		PORT_START /* 16bit */
	44	PORT_START_TAG("IN0") /* 16bit */
45	45	PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Unknown ) )
46	46	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
47	47	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )

src/mame/drivers/midvunit.c
r2864	r2865
397	397
398	398	static WRITE32_HANDLER( offroadc_serial_data_w )
399	399	{
400		midway_serial_pic2_w(data >> 16);
	400	midway_serial_pic2_w(machine, data >> 16);
401	401	}
402	402
403	403
r2864	r2865
1429	1429	memory_install_write32_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x994000, 0x994000, 0, 0, crusnwld_control_w);
1430	1430
1431	1431	/* valid values are 450 or 460 */
1432		midway_serial_pic_init(450);
	1432	midway_serial_pic_init(machine, 450);
1433	1433	memory_install_read32_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x991030, 0x991030, 0, 0, offroadc_serial_status_r);
1434	1434	memory_install_read32_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x996000, 0x996000, 0, 0, offroadc_serial_data_r);
1435	1435	memory_install_write32_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x996000, 0x996000, 0, 0, offroadc_serial_data_w);
r2864	r2865
1457	1457	memory_install_write32_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x994000, 0x994000, 0, 0, crusnwld_control_w);
1458	1458
1459	1459	/* valid values are 230 or 234 */
1460		midway_serial_pic2_init(230, 94);
	1460	midway_serial_pic2_init(machine, 230, 94);
1461	1461	memory_install_read32_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x991030, 0x991030, 0, 0, offroadc_serial_status_r);
1462	1462	memory_install_readwrite32_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x996000, 0x996000, 0, 0, offroadc_serial_data_r, offroadc_serial_data_w);
1463	1463
r2864	r2865
1472	1472
1473	1473	/* initialize the subsystems */
1474	1474	dcs2_init(machine, 2, 0x3839);
1475		midway_ioasic_init(0, 452/* no alternates */, 94, NULL);
	1475	midway_ioasic_init(machine, 0, 452/* no alternates */, 94, NULL);
1476	1476	adc_shift = 16;
1477	1477
1478	1478	/* we need proper VRAM */

src/mame/drivers/littlerb.c
r2864	r2865
59	59	*/
60	60
61	61	#include "driver.h"
62		#include "deprecat.h"
63	62
64	63	static UINT16 littlerb_vdp_address_low;
65	64	static UINT16 littlerb_vdp_address_high;
r2864	r2865
78	77	static UINT16* littlerb_region4;
79	78
80	79
81		static void littlerb_data_write(UINT16 data)
	80	static void littlerb_data_write(running_machine *machine, UINT16 data)
82	81	{
83	82	UINT32 addr = littlerb_write_address>>4; // is this right? should we shift?
84	83
r2864	r2865
105	104	r = littlerb_region2[x+1];
106	105	g = littlerb_region2[x+2];
107	106
108		palette_set_color(Machine,x/3,MAKE_RGB(r,g,b));
	107	palette_set_color(machine,x/3,MAKE_RGB(r,g,b));
109	108	}
110	109
111	110
r2864	r2865
175	174
176	175
177	176	case 2:
178		littlerb_data_write(data);
	177	littlerb_data_write(machine, data);
179	178	break;
180	179
181	180	case 3:

src/mame/drivers/firebeat.c
r2864	r2865
109	109	*/
110	110
111	111	#include "driver.h"
112		#include "deprecat.h"
113	112	#include "cpu/powerpc/ppc.h"
114	113	#include "machine/intelfsh.h"
115	114	#include "machine/scsicd.h"
r2864	r2865
679	678
680	679	if (ACCESSING_BITS_24_31)
681	680	{
682		r \|= (input_port_read~~_indexed~~(machine, 0) & 0xff) << 24;
	681	r \|= (input_port_read(machine, "IN0") & 0xff) << 24;
683	682	}
684	683	if (ACCESSING_BITS_8_15)
685	684	{
686		r \|= (input_port_read~~_indexed~~(machine, 1) & 0xff) << 8;
	685	r \|= (input_port_read(machine, "IN1") & 0xff) << 8;
687	686	}
688	687	if (ACCESSING_BITS_0_7)
689	688	{
690		r \|= (input_port_read~~_indexed~~(machine, 2) & 0xff);
	689	r \|= (input_port_read(machine, "IN2") & 0xff);
691	690	}
692	691
693	692	return r;
r2864	r2865
697	696	{
698	697	if (offset == 0)
699	698	{
700		return input_port_read~~_indexed~~(machine, 3) \| 0x01000100;
	699	return input_port_read(machine, "SENSOR1") \| 0x01000100;
701	700	}
702	701	else
703	702	{
704		return input_port_read~~_indexed~~(machine, 4) \| 0x01000100;
	703	return input_port_read(machine, "SENSOR2") \| 0x01000100;
705	704	}
706	705	}
707	706
r2864	r2865
855	854	static int atapi_data_ptr, atapi_xferlen, atapi_xfermod, atapi_cdata_wait;
856	855	static int atapi_drivesel;
857	856
858		static void atapi_cause_irq(void)
	857	static void atapi_cause_irq(running_machine *machine)
859	858	{
860		cpunum_set_input_line(Machine, 0, INPUT_LINE_IRQ4, ASSERT_LINE);
	859	cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ4, ASSERT_LINE);
861	860	}
862	861
863		static void atapi_clear_irq(void)
	862	static void atapi_clear_irq(running_machine *machine)
864	863	{
865		cpunum_set_input_line(Machine, 0, INPUT_LINE_IRQ4, CLEAR_LINE);
	864	cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ4, CLEAR_LINE);
866	865	}
867	866
868	867	static void atapi_exit(running_machine* machine)
r2864	r2865
905	904
906	905
907	906
908		static UINT16 atapi_command_reg_r(int reg)
	907	static UINT16 atapi_command_reg_r(running_machine *machine, int reg)
909	908	{
910	909	int i, data;
911	910	static UINT8 temp_data[64*1024];
r2864	r2865
918	917	if (atapi_data_ptr == 0)
919	918	{
920	919	//printf("ATAPI: dropping DRQ\n");
921		atapi_cause_irq();
	920	atapi_cause_irq(machine);
922	921	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
923	922
924	923	// get the data from the device
r2864	r2865
938	937	if (atapi_xfermod && atapi_data_ptr == (atapi_xferlen/2))
939	938	{
940	939	//printf("ATAPI: DRQ interrupt\n");
941		atapi_cause_irq();
	940	atapi_cause_irq(machine);
942	941	atapi_regs[ATAPI_REG_CMDSTATUS] \|= ATAPI_STAT_DRQ;
943	942	atapi_data_ptr = 0;
944	943
r2864	r2865
963	962	else
964	963	{
965	964	if (reg == ATAPI_REG_CMDSTATUS)
966		atapi_clear_irq();
	965	atapi_clear_irq(machine);
967	966	return atapi_regs[reg];
968	967	}
969	968	}
970	969
971		static void atapi_command_reg_w(int reg, UINT16 data)
	970	static void atapi_command_reg_w(running_machine *machine, int reg, UINT16 data)
972	971	{
973	972	int i;
974	973
r2864	r2865
994	993	SCSIWriteData( atapi_device_data[atapi_drivesel], atapi_scsi_packet, atapi_cdata_wait );
995	994
996	995	// assert IRQ
997		atapi_cause_irq();
	996	atapi_cause_irq(machine);
998	997
999	998	// not sure here, but clear DRQ at least?
1000	999	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
r2864	r2865
1011	1010	atapi_regs[ATAPI_REG_CMDSTATUS] \|= ATAPI_STAT_BSY;
1012	1011
1013	1012	// assert IRQ
1014		atapi_cause_irq();
	1013	atapi_cause_irq(machine);
1015	1014
1016	1015	// decompose SCSI packet into proper byte order
1017	1016	for (i = 0; i < 16; i += 2)
r2864	r2865
1173	1172	// printf("atapi_command_r: %08X, %08X\n", offset, mem_mask);
1174	1173	if (ACCESSING_BITS_16_31)
1175	1174	{
1176		r = atapi_command_reg_r(offset*2);
	1175	r = atapi_command_reg_r(machine, offset*2);
1177	1176	return ATAPI_ENDIAN(r) << 16;
1178	1177	}
1179	1178	else
1180	1179	{
1181		r = atapi_command_reg_r((offset*2) + 1);
	1180	r = atapi_command_reg_r(machine, (offset*2) + 1);
1182	1181	return ATAPI_ENDIAN(r) << 0;
1183	1182	}
1184	1183	}
r2864	r2865
1189	1188
1190	1189	if (ACCESSING_BITS_16_31)
1191	1190	{
1192		atapi_command_reg_w(offset*2, ATAPI_ENDIAN((data >> 16) & 0xffff));
	1191	atapi_command_reg_w(machine, offset*2, ATAPI_ENDIAN((data >> 16) & 0xffff));
1193	1192	}
1194	1193	else
1195	1194	{
1196		atapi_command_reg_w((offset*2) + 1, ATAPI_ENDIAN((data >> 0) & 0xffff));
	1195	atapi_command_reg_w(machine, (offset*2) + 1, ATAPI_ENDIAN((data >> 0) & 0xffff));
1197	1196	}
1198	1197	}
1199	1198
r2864	r2865
1395	1394	{
1396	1395	if (offset == 0) // Keyboard Wheel (P1)
1397	1396	{
1398		return input_port_read~~_indexed~~(machine, 3) << 24;
	1397	return input_port_read(machine, "WHEEL_P1") << 24;
1399	1398	}
1400	1399	else if (offset == 2) // Keyboard Wheel (P2)
1401	1400	{
1402		return input_port_read~~_indexed~~(machine, 4) << 24;
	1401	return input_port_read(machine, "WHEEL_P2") << 24;
1403	1402	}
1404	1403
1405	1404	return 0;
r2864	r2865
1482	1481	static TIMER_CALLBACK( keyboard_timer_callback )
1483	1482	{
1484	1483	static const int kb_uart_channel[2] = { 1, 0 };
	1484	static const char *keynames[] = { "KEYBOARD_P1", "KEYBOARD_P2" };
1485	1485	int keyboard;
1486	1486	int i;
1487	1487
1488	1488	for (keyboard=0; keyboard < 2; keyboard++)
1489	1489	{
1490		UINT32 kbstate = input_port_read~~_indexed~~(machine, ~~5 +~~ keyboard);
	1490	UINT32 kbstate = input_port_read(machine, keynames[keyboard]);
1491	1491	int uart_channel = kb_uart_channel[keyboard];
1492	1492
1493	1493	if (kbstate != keyboard_state[keyboard])

src/mame/drivers/eolith.c
r2864	r2865
104	104	*/
105	105	eolith_speedup_read();
106	106
107		return (input_port_read~~_indexed~~(machine, 0) & ~0x308) \| (eeprom_read_bit() << 3) \| (mame_rand(machine) & 0x300);
	107	return (input_port_read(machine, "IN0") & ~0x308) \| (eeprom_read_bit() << 3) \| (mame_rand(machine) & 0x300);
108	108	}
109	109
110	110	static WRITE32_HANDLER( systemcontrol_w )

src/mame/drivers/bagman.c
r2864	r2865
223	223	AM_RANGE(0xa800, 0xa800) AM_READ(input_port_2_r)
224	224
225	225
	226	AM_RANGE(0xa005, 0xa005) AM_WRITE(SMH_NOP) /* ???? */
	227	AM_RANGE(0xa006, 0xa006) AM_WRITE(SMH_NOP) /* ???? */
	228	AM_RANGE(0xa007, 0xa007) AM_WRITE(SMH_NOP) /* ???? */
226	229
227		#if 0
228		AM_RANGE(0xa007, 0xa007) AM_WRITE(SMH_NOP) /* ???? */
229		AM_RANGE(0xb000, 0xb000) AM_WRITE(SMH_NOP) /* ???? */
230		AM_RANGE(0xb800, 0xb800) AM_READ(SMH_NOP) /* ???? */
231		AM_RANGE(0xb800, 0xb800) AM_WRITE(SMH_NOP) /* ???? */
232		#endif
	230	/* guess */
	231	AM_RANGE(0xb000, 0xb000) AM_WRITE(AY8910_control_port_1_w)
	232	AM_RANGE(0xb800, 0xb800) AM_READWRITE(AY8910_read_port_1_r, AY8910_write_port_1_w)
233	233	ADDRESS_MAP_END
234	234
235	235	static ADDRESS_MAP_START( main_portmap, ADDRESS_SPACE_IO, 8 )
r2864	r2865
342	342	INPUT_PORTS_END
343	343
344	344
	345	static INPUT_PORTS_START( squaitsa )
	346	PORT_START_TAG("IN0")
	347	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
	348	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
	349	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
	350	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
	351	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
	352	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY // these must be tied to a spinner somehow?
	353	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY // ^
	354	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 )
345	355
	356	PORT_START_TAG("IN1")
	357	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
	358	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN4 )
	359	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
	360	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
	361	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
	362	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL // these must be tied to a spinner somehow?
	363	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL // ^
	364	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
	365
	366	PORT_START_TAG("DSW")
	367	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
	368	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	369	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	370	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	371	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	372	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	373	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	374	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	375	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	376	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	377	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	378	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	379	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	380	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	381	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	382	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	383	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	384	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	385	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	386	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	387	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	388	PORT_DIPNAME( 0x80, 0x00, "Protection?" )
	389	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	390	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	391	INPUT_PORTS_END
	392
346	393	static const gfx_layout charlayout =
347	394	{
348	395	8,8, /* 88 characters /
r2864	r2865
392	439	NULL
393	440	};
394	441
	442	static const struct AY8910interface ay8910_interface_2 =
	443	{
	444	AY8910_LEGACY_OUTPUT,
	445	AY8910_DEFAULT_LOADS,
	446	NULL,
	447	NULL,
	448	NULL,
	449	NULL
	450	};
	451
395	452	static const struct TMS5110interface tms5110_interface =
396	453	{
397	454	-1, /* ROM_REGION */
r2864	r2865
464	521	MDRV_SOUND_ADD(AY8910, 1500000)
465	522	MDRV_SOUND_CONFIG(ay8910_interface)
466	523	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.10)
	524
	525	/* maybe */
	526	MDRV_SOUND_ADD(AY8910, 1500000)
	527	MDRV_SOUND_CONFIG(ay8910_interface_2)
	528	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.10)
467	529	MACHINE_DRIVER_END
468	530
469	531	/*
r2864	r2865
514	576	MDRV_SOUND_ADD(AY8910, 1500000)
515	577	MDRV_SOUND_CONFIG(ay8910_interface)
516	578	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.10)
	579
	580	MDRV_SOUND_ADD(AY8910, 1500000)
	581	MDRV_SOUND_CONFIG(ay8910_interface_2)
	582	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.10)
517	583	MACHINE_DRIVER_END
518	584
519	585	/***************************************************************************
r2864	r2865
847	913	GAME( 1984, sbagmans, sbagman, bagman, sbagman, 0, ROT270, "Valadon Automation (Stern license)", "Super Bagman (Stern)", 0 )
848	914	GAME( 1983, pickin, 0, pickin, pickin, 0, ROT270, "Valadon Automation", "Pickin'", 0 )
849	915	GAME( 1984, botanic, 0, botanic, botanic, 0, ROT270, "Valadon Automation (Itisa license)", "Botanic", 0 )
850		GAME( 1984, squaitsa, 0, botanic, ~~bot~~anic, 0, ROT0, "Itisa", "Squash (Itisa)", GAME_NOT_WORKING )
	916	GAME( 1984, squaitsa, 0, botanic, squaitsa, 0, ROT0, "Itisa", "Squash (Itisa)", GAME_NOT_WORKING )
851	917

src/mame/drivers/namcos23.c
r2864	r2865
500	500
501	501
502	502	#include "driver.h"
503		#include "deprecat.h"
504	503	#include "cpu/mips/mips3.h"
505	504	#include "cpu/h83002/h83002.h"
506	505	#include "sound/c352.h"
r2864	r2865
732	731	return (pSource[0]<<((offs&3)*8))>>24;
733	732	}
734	733
735		INLINE void UpdatePalette( int entry )
	734	INLINE void UpdatePalette( running_machine *machine, int entry )
736	735	{
737	736	int j;
738	737
r2864	r2865
742	741	int r = nthbyte(paletteram32,which+0x00001);
743	742	int g = nthbyte(paletteram32,which+0x08001);
744	743	int b = nthbyte(paletteram32,which+0x18001);
745		palette_set_color( Machine,which,MAKE_RGB(r,g,b) );
	744	palette_set_color( machine,which,MAKE_RGB(r,g,b) );
746	745	}
747	746	}
748	747
r2864	r2865
757	756	{
758	757	COMBINE_DATA( &paletteram32[offset] );
759	758
760		UpdatePalette((offset % (0x8000/4))*2);
	759	UpdatePalette(machine, (offset % (0x8000/4))*2);
761	760	}
762	761
763	762	// must return this magic number

src/mame/drivers/inufuku.c
r2864	r2865
158	158
159	159	soundflag = pending_command ? 0x0000 : 0x0080; // bit7
160	160	eeprom = (eeprom_read_bit() & 1) << 6; // bit6
161		inputport = input_port_read~~_indexed~~(machine, 4) & 0xff3f; // bit5-0
	161	inputport = input_port_read(machine, "IN1") & 0xff3f; // bit5-0
162	162
163	163	return (soundflag \| eeprom \| inputport);
164	164	}
r2864	r2865
269	269	******************************************************************************/
270	270
271	271	static INPUT_PORTS_START( inufuku )
272		PORT_START // 0
	272	PORT_START_TAG("P1") // 0
273	273	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
274	274	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
275	275	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
r2864	r2865
279	279	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
280	280	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
281	281
282		PORT_START // 1
	282	PORT_START_TAG("P2") // 1
283	283	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
284	284	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
285	285	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
r2864	r2865
289	289	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
290	290	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
291	291
292		PORT_START // 2
	292	PORT_START_TAG("IN0") // 2
293	293	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
294	294	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
295	295	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r2864	r2865
299	299	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
300	300	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
301	301
302		PORT_START // 3
	302	PORT_START_TAG("P4") // 3
303	303	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(4)
304	304	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(4)
305	305	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(4)
r2864	r2865
309	309	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
310	310	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(4)
311	311
312		PORT_START // 4
	312	PORT_START_TAG("IN1") // 4
313	313	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
314	314	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN4 )
315	315	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 )
r2864	r2865
321	321	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
322	322	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) // pending sound command
323	323
324		PORT_START // 5
	324	PORT_START_TAG("P3") // 5
325	325	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(3)
326	326	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(3)
327	327	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(3)

src/mame/drivers/atarisy2.c
r2864	r2865
3033	3033	UINT8 *cpu1 = memory_region(REGION_CPU1);
3034	3034
3035	3035	atarigen_eeprom_default = compressed_default_eeprom;
3036		slapstic_init(105);
	3036	slapstic_init(machine, 105);
3037	3037
3038	3038	/* expand the 16k program ROMs into full 64k chunks */
3039	3039	for (i = 0x10000; i < 0x90000; i += 0x20000)
r2864	r2865
3080	3080	0x0000
3081	3081	};
3082	3082	atarigen_eeprom_default = compressed_default_eeprom;
3083		slapstic_init(107);
	3083	slapstic_init(machine, 107);
3084	3084
3085	3085	pedal_count = -1;
3086	3086	has_tms5220 = 1;
r2864	r2865
3093	3093	UINT8 *cpu1 = memory_region(REGION_CPU1);
3094	3094
3095	3095	atarigen_eeprom_default = default_eeprom;
3096		slapstic_init(108);
	3096	slapstic_init(machine, 108);
3097	3097
3098	3098	/* expand the 32k program ROMs into full 64k chunks */
3099	3099	for (i = 0x10000; i < 0x90000; i += 0x20000)
r2864	r2865
3217	3217	UINT8 *cpu1 = memory_region(REGION_CPU1);
3218	3218
3219	3219	atarigen_eeprom_default = compressed_default_eeprom;
3220		slapstic_init(109);
	3220	slapstic_init(machine, 109);
3221	3221
3222	3222	/* expand the 32k program ROMs into full 64k chunks */
3223	3223	for (i = 0x10000; i < 0x90000; i += 0x20000)
r2864	r2865
3231	3231	static DRIVER_INIT( apb )
3232	3232	{
3233	3233	atarigen_eeprom_default = NULL;
3234		slapstic_init(110);
	3234	slapstic_init(machine, 110);
3235	3235
3236	3236	pedal_count = 2;
3237	3237	has_tms5220 = 1;

src/mame/drivers/onetwo.c
r2864	r2865
40	40	*/
41	41
42	42	#include "driver.h"
43		#include "deprecat.h"
44	43	#include "sound/okim6295.h"
45	44	#include "sound/3812intf.h"
46	45
r2864	r2865
83	82	cpunum_set_input_line(machine, 1, INPUT_LINE_NMI, PULSE_LINE);
84	83	}
85	84
86		static void setColor(int offset)
	85	static void setColor(running_machine *machine, int offset)
87	86	{
88	87	int r,g,b;
89	88	r=paletteram[offset]&0x1f;
90	89	g=paletteram_2[offset]&0x1f;
91	90	b=((paletteram[offset]&0x60)>>2)\|((paletteram_2[offset]&0xe0)>>5);
92		palette_set_color_rgb(Machine,offset,pal5bit(r),pal5bit(g),pal5bit(b));
	91	palette_set_color_rgb(machine,offset,pal5bit(r),pal5bit(g),pal5bit(b));
93	92	}
94	93
95	94	static WRITE8_HANDLER(palette1_w)
96	95	{
97	96	paletteram[offset]=data;
98		setColor(offset);
	97	setColor(machine, offset);
99	98	}
100	99
101	100	static WRITE8_HANDLER(palette2_w)
102	101	{
103	102	paletteram_2[offset]=data;
104		setColor(offset);
	103	setColor(machine, offset);
105	104	}
106	105
107	106	/* Main CPU */

src/mame/drivers/liberate.c
r2864	r2865
126	126	ADDRESS_MAP_END
127	127
128	128	static ADDRESS_MAP_START( deco16_readport, ADDRESS_SPACE_IO, 8 )
129		AM_RANGE(0x00, 0x00) AM_READ~~(input~~_~~port_~~0_r)
	129	AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0")
130	130	ADDRESS_MAP_END
131	131
132	132	static ADDRESS_MAP_START( deco16_writeport, ADDRESS_SPACE_IO, 8 )
r2864	r2865
134	134	ADDRESS_MAP_END
135	135
136	136	static ADDRESS_MAP_START( liberatb_readmem, ADDRESS_SPACE_PROGRAM, 8 )
137		AM_RANGE(0x00fe, 0x00fe) AM_READ~~(input~~_~~port_~~0_r)
	137	AM_RANGE(0x00fe, 0x00fe) AM_READ_PORT("IN0")
138	138	AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_RAM)
139	139	AM_RANGE(0x1000, 0x3fff) AM_READ(SMH_ROM) /* Mirror of main rom */
140	140	AM_RANGE(0x4000, 0x7fff) AM_READ(deco16_bank_r)
141		AM_RANGE(0xf000, 0xf000) AM_READ(input_port_1_r)
142		AM_RANGE(0xf001, 0xf001) AM_READ(input_port_2_r)
143		AM_RANGE(0xf002, 0xf002) AM_READ(input_port_3_r)
144		AM_RANGE(0xf003, 0xf003) AM_READ(input_port_4_r)
145		AM_RANGE(0xf004, 0xf004) AM_READ(input_port_5_r)
	141	AM_RANGE(0xf000, 0xf000) AM_READ_PORT("IN1")
	142	AM_RANGE(0xf001, 0xf001) AM_READ_PORT("IN2")
	143	AM_RANGE(0xf002, 0xf002) AM_READ_PORT("IN3")
	144	AM_RANGE(0xf003, 0xf003) AM_READ_PORT("DSW1")
	145	AM_RANGE(0xf004, 0xf004) AM_READ_PORT("DSW2")
146	146	AM_RANGE(0x8000, 0xffff) AM_READ(SMH_ROM)
147	147	ADDRESS_MAP_END
148	148
r2864	r2865
497	497
498	498	static INTERRUPT_GEN( deco16_interrupt )
499	499	{
500		static int latch=0;
501		int p=~input_port_read_indexed(machine, 3);
502		if (p&0x43 && !latch) {
503		cpunum_set_input_line(machine, 0,DECO16_IRQ_LINE,ASSERT_LINE);
504		latch=1;
505		} else {
506		if (!(p&0x43))
	500	static int latch = 0;
	501	int p = ~input_port_read(machine, "IN3");
	502	if ((p & 0x43) && !latch)
	503	{
	504	cpunum_set_input_line(machine, 0, DECO16_IRQ_LINE, ASSERT_LINE);
	505	latch = 1;
	506	}
	507	else
	508	{
	509	if (!(p & 0x43))
507	510	latch=0;
508	511	}
509	512	}

src/mame/drivers/laserbat.c
r2864	r2865
89	89
90	90	static READ8_HANDLER( laserbat_input_r )
91	91	{
92		// Add coktail inputs
93		return input_port_read_indexed(machine, 0 + laserbat_input_mux);
	92	static const char *portnames[] = { "IN0", "IN1", "IN2", "IN3" };
	93
	94	return input_port_read(machine, portnames[laserbat_input_mux]);
94	95	}
95	96
96	97	static WRITE8_HANDLER( laserbat_cnteff_w )
r2864	r2865
221	222
222	223
223	224	static INPUT_PORTS_START( laserbat )
224		PORT_START
	225	PORT_START_TAG("IN0")
225	226	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
226	227	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
227	228	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
r2864	r2865
231	232	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
232	233	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 )
233	234
234		PORT_START
	235	PORT_START_TAG("IN1")
235	236	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
236	237	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
237	238	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
253	254	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
254	255	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Reset")
255	256
256		PORT_START
	257	PORT_START_TAG("IN2")
257	258	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coin_A ) )
258	259	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
259	260	PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) )
r2864	r2865
277	278	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
278	279	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
279	280
280		PORT_START
	281	PORT_START_TAG("IN3")
281	282	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
282	283	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
283	284	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
295	296	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
296	297	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
297	298
298		PORT_START /* SENSE */
	299	PORT_START_TAG("SENSE") /* SENSE */
299	300	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_VBLANK )
300	301	INPUT_PORTS_END
301	302
302	303	static INPUT_PORTS_START( lazarian )
303		PORT_START
	304	PORT_START_TAG("IN0")
304	305	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
305	306	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
306	307	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
r2864	r2865
310	311	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
311	312	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 )
312	313
313		PORT_START
	314	PORT_START_TAG("IN1")
314	315	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
315	316	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
316	317	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
332	333	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
333	334	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Reset")
334	335
335		PORT_START
	336	PORT_START_TAG("IN2")
336	337	PORT_DIPNAME( 0x03, 0x01, DEF_STR( Coin_A ) )
337	338	PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
338	339	PORT_DIPSETTING( 0x01, DEF_STR( 1C_1C ) )
r2864	r2865
355	356	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
356	357	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
357	358
358		PORT_START
	359	PORT_START_TAG("IN3")
359	360	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
360	361	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
361	362	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
373	374	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
374	375	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
375	376
376		PORT_START /* SENSE */
	377	PORT_START_TAG("SENSE") /* SENSE */
377	378	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_VBLANK )
378	379	INPUT_PORTS_END
379	380
380	381	static INPUT_PORTS_START( catnmous )
381		PORT_START
	382	PORT_START_TAG("IN0")
382	383	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
383	384	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
384	385	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
r2864	r2865
388	389	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 )
389	390	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
390	391
391		PORT_START
	392	PORT_START_TAG("IN1")
392	393	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
393	394	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
394	395	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
406	407	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
407	408	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Reset")
408	409
409		PORT_START
	410	PORT_START_TAG("IN2")
410	411	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coin_A ) )
411	412	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
412	413	PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) )
r2864	r2865
430	431	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
431	432	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
432	433
433		PORT_START
	434	PORT_START_TAG("IN3")
434	435	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
435	436	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
436	437	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
456	457	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
457	458	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
458	459
459		PORT_START /* SENSE */
	460	PORT_START_TAG("SENSE") /* SENSE */
460	461	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_VBLANK )
461	462	INPUT_PORTS_END
462	463

src/mame/drivers/rohga.c
r2864	r2865
124	124	VIDEO_UPDATE( nitrobal );
125	125	WRITE16_HANDLER( rohga_buffer_spriteram16_w );
126	126
127		static READ16_HANDLER( rohga_dip3_r ) { return input_port_read_indexed(machine, 3); }
128		static READ16_HANDLER( nitrobal_control_r ) { return input_port_read_indexed(machine, 3); }
129		static READ16_HANDLER( schmeisr_control_r ) { return input_port_read_indexed(machine, 1); }
	127	static READ16_HANDLER( rohga_dip3_r ) { return input_port_read(machine, "DSW3"); }
	128	static READ16_HANDLER( nitrobal_control_r ) { return input_port_read(machine, "DSW3"); }
	129	static READ16_HANDLER( schmeisr_control_r ) { return input_port_read(machine, "IN1"); }
130	130
131	131	/**********************************************************************************/
132	132
r2864	r2865
349	349	/**********************************************************************************/
350	350
351	351	static INPUT_PORTS_START( rohga )
352		PORT_START
	352	PORT_START_TAG("IN0")
353	353	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
354	354	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
355	355	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
r2864	r2865
367	367	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
368	368	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
369	369
370		PORT_START
	370	PORT_START_TAG("IN1")
371	371	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
372	372	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
373	373	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
374	374	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_VBLANK )
375	375
376		PORT_START /* Dip switch bank 1/2 */
	376	PORT_START_TAG("DSW1_2") /* Dip switch bank 1/2 */
377	377	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )
378	378	PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
379	379	PORT_DIPSETTING( 0x0001, DEF_STR( 2C_1C ) )
r2864	r2865
422	422	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
423	423	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
424	424
425		PORT_START /* Dip switch bank 3 */
	425	PORT_START_TAG("DSW3") /* Dip switch bank 3 */
426	426	PORT_DIPNAME( 0x0001, 0x0001, "Stage Clear Bonus" ) /* Life Recovery At stage clear */
427	427	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
428	428	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
447	447	INPUT_PORTS_END
448	448
449	449	static INPUT_PORTS_START( wizdfire )
450		PORT_START
	450	PORT_START_TAG("IN0")
451	451	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
452	452	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
453	453	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
r2864	r2865
465	465	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
466	466	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
467	467
468		PORT_START
	468	PORT_START_TAG("IN1")
469	469	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
470	470	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
471	471	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
472	472	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_VBLANK )
473	473
474		PORT_START /* Dip switch bank 1/2 */
	474	PORT_START_TAG("DSW1_2") /* Dip switch bank 1/2 */
475	475	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )
476	476	PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
477	477	PORT_DIPSETTING( 0x0001, DEF_STR( 2C_1C ) )
r2864	r2865
520	520	INPUT_PORTS_END
521	521
522	522	static INPUT_PORTS_START( nitrobal )
523		PORT_START
	523	PORT_START_TAG("IN0")
524	524	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
525	525	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
526	526	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
r2864	r2865
538	538	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
539	539	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
540	540
541		PORT_START
	541	PORT_START_TAG("IN1")
542	542	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
543	543	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
544	544	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
545	545	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_VBLANK )
546	546
547		PORT_START /* Dip switch bank 1/2 */
	547	PORT_START_TAG("DSW1_2") /* Dip switch bank 1/2 */
548	548	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )
549	549	PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
550	550	PORT_DIPSETTING( 0x0001, DEF_STR( 2C_1C ) )
r2864	r2865
592	592	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
593	593	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
594	594
595		PORT_START
	595	PORT_START_TAG("DSW3") /* Not really a DSW, but this way it's easier to read by tag */
596	596	PORT_BIT( 0x1, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
597	597	PORT_BIT( 0x2, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
598	598	PORT_BIT( 0x4, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
r2864	r2865
604	604	INPUT_PORTS_END
605	605
606	606	static INPUT_PORTS_START( schmeisr )
607		PORT_START
	607	PORT_START_TAG("IN0")
608	608	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
609	609	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
610	610	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
r2864	r2865
622	622	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
623	623	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
624	624
625		PORT_START
	625	PORT_START_TAG("IN1")
626	626	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
627	627	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
628	628	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
629	629	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_VBLANK )
630	630
631		PORT_START /* Dip switch bank 1/2 */
	631	PORT_START_TAG("DSW1_2") /* Dip switch bank 1/2 */
632	632	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )
633	633	PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
634	634	PORT_DIPSETTING( 0x0001, DEF_STR( 2C_1C ) )
r2864	r2865
676	676	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
677	677	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
678	678
679		PORT_START /* Dip switch bank 3 - This bank of switches are _NOT_ shown in the test mode screen */
	679	PORT_START_TAG("DSW3") /* Dip switch bank 3 - This bank of switches are _NOT_ shown in the test mode screen */
680	680	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
681	681	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
682	682	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )

src/mame/drivers/batman.c
r2864	r2865
353	353	0x01D0,0x02C8,0x0000
354	354	};
355	355	atarigen_eeprom_default = default_eeprom;
356		atarijsa_init(machine, 2, 0x0040);
	356	atarijsa_init(machine, "260010", 0x0040);
357	357	atarijsa3_init_adpcm(REGION_SOUND1);
358	358	}
359	359

src/mame/drivers/stv.c
r2864	r2865
235	235	scu_size_1, /* lv 1*/
236	236	scu_size_2; /* lv 2*/
237	237
238		static void dma_direct_lv0(void); /DMA level 0 direct transfer function/
239		static void dma_direct_lv1(void); /DMA level 1 direct transfer function/
240		static void dma_direct_lv2(void); /DMA level 2 direct transfer function/
241		static void dma_indirect_lv0(void); /DMA level 0 indirect transfer function/
242		static void dma_indirect_lv1(void); /DMA level 1 indirect transfer function/
243		static void dma_indirect_lv2(void); /DMA level 2 indirect transfer function/
	238	static void dma_direct_lv0(running_machine machine); /DMA level 0 direct transfer function*/
	239	static void dma_direct_lv1(running_machine machine); /DMA level 1 direct transfer function*/
	240	static void dma_direct_lv2(running_machine machine); /DMA level 2 direct transfer function*/
	241	static void dma_indirect_lv0(running_machine machine); /DMA level 0 indirect transfer function*/
	242	static void dma_indirect_lv1(running_machine machine); /DMA level 1 indirect transfer function*/
	243	static void dma_indirect_lv2(running_machine machine); /DMA level 2 indirect transfer function*/
244	244
245	245
246	246	int minit_boost,sinit_boost;
r2864	r2865
1234	1234	*/
1235	1235	if(stv_scu[4] & 1 && ((stv_scu[5] & 7) == 7) && stv_scu[4] & 0x100)
1236	1236	{
1237		if(DIRECT_MODE(0)) { dma_direct_lv0(); }
1238		else { dma_indirect_lv0(); }
	1237	if(DIRECT_MODE(0)) { dma_direct_lv0(machine); }
	1238	else { dma_indirect_lv0(machine); }
1239	1239
1240	1240	stv_scu[4]^=1;//disable starting bit.
1241	1241
r2864	r2865
1295	1295	case 12:
1296	1296	if(stv_scu[12] & 1 && ((stv_scu[13] & 7) == 7) && stv_scu[12] & 0x100)
1297	1297	{
1298		if(DIRECT_MODE(1)) { dma_direct_lv1(); }
1299		else { dma_indirect_lv1(); }
	1298	if(DIRECT_MODE(1)) { dma_direct_lv1(machine); }
	1299	else { dma_indirect_lv1(machine); }
1300	1300
1301	1301	stv_scu[12]^=1;
1302	1302
r2864	r2865
1345	1345	case 20:
1346	1346	if(stv_scu[20] & 1 && ((stv_scu[21] & 7) == 7) && stv_scu[20] & 0x100)
1347	1347	{
1348		if(DIRECT_MODE(2)) { dma_direct_lv2(); }
1349		else { dma_indirect_lv2(); }
	1348	if(DIRECT_MODE(2)) { dma_direct_lv2(machine); }
	1349	else { dma_indirect_lv2(machine); }
1350	1350
1351	1351	stv_scu[20]^=1;
1352	1352
r2864	r2865
1375	1375	/DSP section/
1376	1376	/Use functions so it is easier to work out/
1377	1377	case 32:
1378		dsp_prg_ctrl(data);
	1378	dsp_prg_ctrl(machine, data);
1379	1379	if(LOG_SCU) logerror("SCU DSP: Program Control Port Access %08x\n",data);
1380	1380	break;
1381	1381	case 33:
r2864	r2865
1434	1434	}
1435	1435	}
1436	1436
1437		static void dma_direct_lv0()
	1437	static void dma_direct_lv0(running_machine *machine)
1438	1438	{
1439	1439	static UINT32 tmp_src,tmp_dst,tmp_size;
1440	1440	if(LOG_SCU) logerror("DMA lv 0 transfer START\n"
r2864	r2865
1532	1532
1533	1533	if(LOG_SCU) logerror("DMA transfer END\n");
1534	1534	if(!(stv_scu[40] & 0x800))/Lv 0 DMA end irq/
1535		cpunum_set_input_line_and_vector(Machine, 0, 5, HOLD_LINE , 0x4b);
	1535	cpunum_set_input_line_and_vector(machine, 0, 5, HOLD_LINE , 0x4b);
1536	1536
1537	1537	if(scu_add_tmp & 0x80000000)
1538	1538	{
r2864	r2865
1544	1544	D0MV_0;
1545	1545	}
1546	1546
1547		static void dma_direct_lv1()
	1547	static void dma_direct_lv1(running_machine *machine)
1548	1548	{
1549	1549	static UINT32 tmp_src,tmp_dst,tmp_size;
1550	1550	if(LOG_SCU) logerror("DMA lv 1 transfer START\n"
r2864	r2865
1635	1635
1636	1636	if(LOG_SCU) logerror("DMA transfer END\n");
1637	1637	if(!(stv_scu[40] & 0x400))/Lv 1 DMA end irq/
1638		cpunum_set_input_line_and_vector(Machine, 0, 6, HOLD_LINE , 0x4a);
	1638	cpunum_set_input_line_and_vector(machine, 0, 6, HOLD_LINE , 0x4a);
1639	1639
1640	1640	if(scu_add_tmp & 0x80000000)
1641	1641	{
r2864	r2865
1647	1647	D1MV_0;
1648	1648	}
1649	1649
1650		static void dma_direct_lv2()
	1650	static void dma_direct_lv2(running_machine *machine)
1651	1651	{
1652	1652	static UINT32 tmp_src,tmp_dst,tmp_size;
1653	1653	if(LOG_SCU) logerror("DMA lv 2 transfer START\n"
r2864	r2865
1738	1738
1739	1739	if(LOG_SCU) logerror("DMA transfer END\n");
1740	1740	if(!(stv_scu[40] & 0x200))/Lv 2 DMA end irq/
1741		cpunum_set_input_line_and_vector(Machine, 0, 6, HOLD_LINE , 0x49);
	1741	cpunum_set_input_line_and_vector(machine, 0, 6, HOLD_LINE , 0x49);
1742	1742
1743	1743	if(scu_add_tmp & 0x80000000)
1744	1744	{
r2864	r2865
1750	1750	D2MV_0;
1751	1751	}
1752	1752
1753		static void dma_indirect_lv0()
	1753	static void dma_indirect_lv0(running_machine *machine)
1754	1754	{
1755	1755	/Helper to get out of the cycle/
1756	1756	UINT8 job_done = 0;
r2864	r2865
1816	1816	}while(job_done == 0);
1817	1817
1818	1818	if(!(stv_scu[40] & 0x800))/Lv 0 DMA end irq/
1819		cpunum_set_input_line_and_vector(Machine, 0, 5, HOLD_LINE , 0x4b);
	1819	cpunum_set_input_line_and_vector(machine, 0, 5, HOLD_LINE , 0x4b);
1820	1820
1821	1821	D0MV_0;
1822	1822	}
1823	1823
1824		static void dma_indirect_lv1()
	1824	static void dma_indirect_lv1(running_machine *machine)
1825	1825	{
1826	1826	/Helper to get out of the cycle/
1827	1827	UINT8 job_done = 0;
r2864	r2865
1888	1888	}while(job_done == 0);
1889	1889
1890	1890	if(!(stv_scu[40] & 0x400))/Lv 1 DMA end irq/
1891		cpunum_set_input_line_and_vector(Machine, 0, 6, HOLD_LINE , 0x4a);
	1891	cpunum_set_input_line_and_vector(machine, 0, 6, HOLD_LINE , 0x4a);
1892	1892
1893	1893	D1MV_0;
1894	1894	}
1895	1895
1896		static void dma_indirect_lv2()
	1896	static void dma_indirect_lv2(running_machine *machine)
1897	1897	{
1898	1898	/Helper to get out of the cycle/
1899	1899	UINT8 job_done = 0;
r2864	r2865
1959	1959	}while(job_done == 0);
1960	1960
1961	1961	if(!(stv_scu[40] & 0x200))/Lv 2 DMA end irq/
1962		cpunum_set_input_line_and_vector(Machine, 0, 6, HOLD_LINE , 0x49);
	1962	cpunum_set_input_line_and_vector(machine, 0, 6, HOLD_LINE , 0x49);
1963	1963
1964	1964	D2MV_0;
1965	1965	}

src/mame/drivers/megatech.c
r2864	r2865
477	477	}
478	478
479	479
480		static READ8_HANDLER( megaplay_r0) { return input_port_read(machine, "BIOS_IN0") ; }
481		static READ8_HANDLER( megaplay_r1) { return input_port_read(machine, "BIOS_IN1") ; }
482		static READ8_HANDLER( megaplay_r2) { return input_port_read(machine, "BIOS_DSW0") ; }
483		static READ8_HANDLER( megaplay_r3) { return input_port_read(machine, "BIOS_DSW1") ; }
484
485	480	static int mt_bank_bank_pos = 0;
486	481	static int mt_bank_partial = 0;
487	482	static int mt_bank_addr = 0;
r2864	r2865
524	519	AM_RANGE(0x3000, 0x3fff) AM_READWRITE(megatech_banked_ram_r, megatech_banked_ram_w) // copies instruction data here at startup, must be banked
525	520	AM_RANGE(0x4000, 0x5fff) AM_RAM // plain ram?
526	521	AM_RANGE(0x6000, 0x6000) AM_WRITE( mt_z80_bank_w )
527		AM_RANGE(0x6400, 0x6400) AM_READ(megaplay_r2)
528		AM_RANGE(0x6401, 0x6401) AM_READ(megaplay_r3)
	522	AM_RANGE(0x6400, 0x6400) AM_READ_PORT("BIOS_DSW0")
	523	AM_RANGE(0x6401, 0x6401) AM_READ_PORT("BIOS_DSW1")
529	524	AM_RANGE(0x6404, 0x6404) AM_READWRITE(megatech_cart_select_r, megatech_cart_select_w) // cart select & ram bank
530		AM_RANGE(0x6800, 0x6800) AM_READ(megaplay_r0)
531		AM_RANGE(0x6801, 0x6801) AM_READ(megaplay_r1)
	525	AM_RANGE(0x6800, 0x6800) AM_READ_PORT("BIOS_IN0")
	526	AM_RANGE(0x6801, 0x6801) AM_READ_PORT("BIOS_IN1")
532	527	AM_RANGE(0x6802, 0x6807) AM_READWRITE(bios_ctrl_r, bios_ctrl_w)
533	528	// AM_RANGE(0x6805, 0x6805) AM_READ(input_port_8_r)
534	529	AM_RANGE(0x7000, 0x77ff) AM_ROM // from bios rom (0x7000-0x77ff populated in ROM)
r2864	r2865
578	573
579	574	static VIDEO_START(mtnew)
580	575	{
581		init_for_megadrive(); // create an sms vdp too, for comptibility mode
	576	init_for_megadrive(machine); // create an sms vdp too, for comptibility mode
582	577	VIDEO_START_CALL(megadriv);
583	578	}
584	579	//attotime_never

src/mame/drivers/timelimt.c
r2864	r2865
33	33
34	34	static MACHINE_START( timelimt )
35	35	{
36		soundlatch_setclearedvalue( 0 );
	36	soundlatch_setclearedvalue( machine, 0 );
37	37	}
38	38
39	39	static MACHINE_RESET( timelimt )

src/mame/drivers/igs_blit.c
r2864	r2865
323	323	{ \
324	324	COMBINE_DATA(&igs_input_sel); \
325	325	\
326		if ( (igs_input_sel & 0xff00) \|\| ((~igs_input_sel) & ((1 << NUM)-1)) ) \
	326	if ( (igs_input_sel & 0xff00) \|\| ((~igs_input_sel) & ((1 << NUM)-1)) ) \
327	327	logerror("%06x: warning, unknown bits written in igs_input_sel = %02x\n", activecpu_get_pc(), igs_input_sel); \
328	328	} \
329	329	\
r2864	r2865
331	331	{ \
332	332	int i; \
333	333	UINT16 ret=0; \
	334	static const char *dipnames[] = { "DSW1", "DSW2", "DSW3", "DSW4", "DSW5" }; \
334	335	\
335	336	for (i = 0; i < NUM; i++) \
336	337	if ((~igs_input_sel) & (1 << i) ) \
337		ret = input_port_read~~_indexed~~(machine, i); \
	338	ret = input_port_read(machine, dipnames[i]); \
338	339	\
339	340	/* 0x0100 is blitter busy */ \
340	341	return (ret & 0xff) \| 0x0000; \
r2864	r2865
663	664	switch(igs_magic[0])
664	665	{
665	666	case 0x01:
666		if (~igs_input_sel2 & 0x01) return input_port_read_indexed(machine, 4);
667		if (~igs_input_sel2 & 0x02) return input_port_read_indexed(machine, 5);
668		if (~igs_input_sel2 & 0x04) return input_port_read_indexed(machine, 6);
669		if (~igs_input_sel2 & 0x08) return input_port_read_indexed(machine, 7);
670		if (~igs_input_sel2 & 0x10) return input_port_read_indexed(machine, 8);
	667	if (~igs_input_sel2 & 0x01) return input_port_read(machine, "KEY0");
	668	if (~igs_input_sel2 & 0x02) return input_port_read(machine, "KEY1");
	669	if (~igs_input_sel2 & 0x04) return input_port_read(machine, "KEY2");
	670	if (~igs_input_sel2 & 0x08) return input_port_read(machine, "KEY3");
	671	if (~igs_input_sel2 & 0x10) return input_port_read(machine, "KEY4");
671	672	/* fall through */
672	673	default:
673	674	logerror("%06x: warning, reading with igs_magic = %02x\n", activecpu_get_pc(), igs_magic[0]);
r2864	r2865
736	737	{
737	738	switch(igs_magic[0])
738	739	{
739		case 0x00: return input_port_read_indexed(machine, 4);
740		case 0x01: return input_port_read_indexed(machine, 5);
741		case 0x02: return input_port_read_indexed(machine, 6);
	740	case 0x00: return input_port_read(machine, "IN0");
	741	case 0x01: return input_port_read(machine, "IN1");
	742	case 0x02: return input_port_read(machine, "IN2");
742	743
743	744	case 0x20: return 0x49;
744	745	case 0x21: return 0x47;
r2864	r2865
803	804	{
804	805	switch(igs_magic[0])
805	806	{
806		case 0x00: return input_port_read~~_indexed~~(machine, 5);
	807	case 0x00: return input_port_read(machine, "IN0");
807	808
808	809	case 0x20: return 0x49;
809	810	case 0x21: return 0x47;
r2864	r2865
873	874	case 0: return igs_input_sel2;
874	875
875	876	case 1:
876		if (~igs_input_sel2 & 0x01) return input_port_read_indexed(machine, 6);
877		if (~igs_input_sel2 & 0x02) return input_port_read_indexed(machine, 7);
878		if (~igs_input_sel2 & 0x04) return input_port_read_indexed(machine, 8);
879		if (~igs_input_sel2 & 0x08) return input_port_read_indexed(machine, 9);
880		if (~igs_input_sel2 & 0x10) return input_port_read_indexed(machine, 10);
	877	if (~igs_input_sel2 & 0x01) return input_port_read(machine, "KEY0");
	878	if (~igs_input_sel2 & 0x02) return input_port_read(machine, "KEY1");
	879	if (~igs_input_sel2 & 0x04) return input_port_read(machine, "KEY2");
	880	if (~igs_input_sel2 & 0x08) return input_port_read(machine, "KEY3");
	881	if (~igs_input_sel2 & 0x10) return input_port_read(machine, "KEY4");
881	882
882	883	logerror("%06x: warning, reading with igs_input_sel2 = %02x\n", activecpu_get_pc(), igs_input_sel2);
883	884	break;
r2864	r2865
918	919	{
919	920	switch(igs_magic[0])
920	921	{
921		case 0x00: return input_port_read_indexed(machine, 5);
922		case 0x01: return input_port_read_indexed(machine, 6);
	922	case 0x00: return input_port_read(machine, "IN0");
	923	case 0x01: return input_port_read(machine, "IN1");
923	924
924	925	case 0x20: return 0x49;
925	926	case 0x21: return 0x47;
r2864	r2865
985	986	{
986	987	switch(igs_magic[0])
987	988	{
988		case 0x00: return input_port_read~~_indexed~~(machine, 3);
	989	case 0x00: return input_port_read(machine, "COIN");
989	990
990	991	case 0x02:
991		if (~igs_input_sel2 & 0x01) return input_port_read_indexed(machine, 4);
992		if (~igs_input_sel2 & 0x02) return input_port_read_indexed(machine, 5);
993		if (~igs_input_sel2 & 0x04) return input_port_read_indexed(machine, 6);
994		if (~igs_input_sel2 & 0x08) return input_port_read_indexed(machine, 7);
995		if (~igs_input_sel2 & 0x10) return input_port_read_indexed(machine, 8);
	992	if (~igs_input_sel2 & 0x01) return input_port_read(machine, "KEY0");
	993	if (~igs_input_sel2 & 0x02) return input_port_read(machine, "KEY1");
	994	if (~igs_input_sel2 & 0x04) return input_port_read(machine, "KEY2");
	995	if (~igs_input_sel2 & 0x08) return input_port_read(machine, "KEY3");
	996	if (~igs_input_sel2 & 0x10) return input_port_read(machine, "KEY4");
996	997	/* fall through */
997	998	default:
998	999	logerror("%06x: warning, reading with igs_magic = %02x\n", activecpu_get_pc(), igs_magic[0]);
r2864	r2865
1194	1195	static VIDEO_EOF( vbowl )
1195	1196	{
1196	1197	vbowl_trackball[0] = vbowl_trackball[1];
1197		vbowl_trackball[1] = (input_port_read~~_indexed~~(machine, 8) << 8) \| input_port_read~~_indexed~~(machine, 7);
	1198	vbowl_trackball[1] = (input_port_read(machine, "AN1") << 8) \| input_port_read(machine, "AN0");
1198	1199	}
1199	1200
1200	1201	static WRITE16_HANDLER( vbowl_pen_hi_w )
r2864	r2865
1300	1301	***************************************************************************/
1301	1302
1302	1303	static INPUT_PORTS_START( chindrag )
1303		PORT_START // IN0 - DSW1
	1304	PORT_START_TAG("DSW1") // IN0 - DSW1
1304	1305	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
1305	1306	PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
1306	1307	PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
r2864	r2865
1325	1326	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1326	1327	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1327	1328
1328		PORT_START // IN1 - DSW2
	1329	PORT_START_TAG("DSW2") // IN1 - DSW2
1329	1330	PORT_DIPNAME( 0x01, 0x01, "Background" )
1330	1331	PORT_DIPSETTING( 0x01, "Girl" )
1331	1332	PORT_DIPSETTING( 0x00, "Landscape" )
r2864	r2865
1351	1352	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1352	1353	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1353	1354
1354		PORT_START // IN2 - DSW3
	1355	PORT_START_TAG("DSW3") // IN2 - DSW3
1355	1356	PORT_DIPNAME( 0xff, 0xff, DEF_STR( Unused ) )
1356	1357	PORT_DIPSETTING( 0xff, DEF_STR( Off ) )
1357	1358	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1358	1359
1359		PORT_START // IN3
	1360	PORT_START_TAG("COIN") // IN3
1360	1361	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1361	1362	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1362	1363	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // keep pressed while booting
r2864	r2865
1366	1367	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1367	1368	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1368	1369
1369		PORT_START // IN4
	1370	PORT_START_TAG("IN0") // IN4
1370	1371	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
1371	1372	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1372	1373	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
r2864	r2865
1376	1377	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) // press in girl test to pause, button 3 advances
1377	1378	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1378	1379
1379		PORT_START // IN5
	1380	PORT_START_TAG("IN1") // IN5
1380	1381	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1381	1382	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
1382	1383	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1386	1387	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1387	1388	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1388	1389
1389		PORT_START // IN6
	1390	PORT_START_TAG("IN2") // IN6
1390	1391	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
1391	1392	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
1392	1393	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 )
r2864	r2865
1398	1399	INPUT_PORTS_END
1399	1400
1400	1401
1401
1402	1402	static INPUT_PORTS_START( chmplst2 )
1403		PORT_START // IN0 - DSW1
	1403	PORT_START_TAG("DSW1") // IN0 - DSW1
1404	1404	PORT_DIPNAME( 0x07, 0x02, "Pay Out (%)" )
1405	1405	PORT_DIPSETTING( 0x07, "50" )
1406	1406	PORT_DIPSETTING( 0x06, "54" )
r2864	r2865
1425	1425	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1426	1426	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1427	1427
1428		PORT_START // IN1 - DSW2
	1428	PORT_START_TAG("DSW2") // IN1 - DSW2
1429	1429	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) ) // Only when bit 4 = 1
1430	1430	PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
1431	1431	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
r2864	r2865
1450	1450	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1451	1451	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
1452	1452
1453		PORT_START // IN2 - DSW3
	1453	PORT_START_TAG("DSW3") // IN2 - DSW3
1454	1454	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Unknown ) )
1455	1455	PORT_DIPSETTING( 0x03, "500" )
1456	1456	PORT_DIPSETTING( 0x02, "1000" )
r2864	r2865
1474	1474	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1475	1475	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1476	1476
1477		PORT_START // IN3
	1477	PORT_START_TAG("COIN") // IN3
1478	1478	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1479	1479	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 ) // data clear
1480	1480	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // keep pressed while booting
r2864	r2865
1484	1484	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1485	1485	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1486	1486
1487		PORT_START // IN4
	1487	PORT_START_TAG("KEY0") // IN4
1488	1488	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
1489	1489	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
1490	1490	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
r2864	r2865
1494	1494	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) // ? set to 0 both
1495	1495	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) // ? and you can't start a game
1496	1496
1497		PORT_START // IN5
	1497	PORT_START_TAG("KEY1") // IN5
1498	1498	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
1499	1499	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
1500	1500	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
r2864	r2865
1504	1504	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1505	1505	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1506	1506
1507		PORT_START // IN6
	1507	PORT_START_TAG("KEY2") // IN6
1508	1508	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
1509	1509	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
1510	1510	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
r2864	r2865
1514	1514	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1515	1515	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1516	1516
1517		PORT_START // IN7
	1517	PORT_START_TAG("KEY3") // IN7
1518	1518	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
1519	1519	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
1520	1520	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
r2864	r2865
1524	1524	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1525	1525	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1526	1526
1527		PORT_START // IN8
	1527	PORT_START_TAG("KEY4") // IN8
1528	1528	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1529	1529	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1530	1530	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1536	1536	INPUT_PORTS_END
1537	1537
1538	1538
1539
1540	1539	static INPUT_PORTS_START( drgnwrld )
1541		PORT_START // IN0 - DSW1
	1540	PORT_START_TAG("DSW1") // IN0 - DSW1
1542	1541	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
1543	1542	PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
1544	1543	PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
r2864	r2865
1563	1562	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1564	1563	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1565	1564
1566		PORT_START // IN1 - DSW2
	1565	PORT_START_TAG("DSW2") // IN1 - DSW2
1567	1566	PORT_DIPNAME( 0x01, 0x01, "Open Girl?" )
1568	1567	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1569	1568	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
1589	1588	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1590	1589	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1591	1590
1592		PORT_START // IN2 - DSW3
	1591	PORT_START_TAG("DSW3") // IN2 - DSW3
1593	1592	PORT_DIPNAME( 0xff, 0xff, DEF_STR( Unused ) )
1594	1593	PORT_DIPSETTING( 0xff, DEF_STR( Off ) )
1595	1594	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1596	1595
1597		PORT_START // IN3
	1596	PORT_START_TAG("COIN") // IN3
1598	1597	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1599	1598	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1600	1599	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // keep pressed while booting
r2864	r2865
1604	1603	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1605	1604	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1606	1605
1607		PORT_START // IN4
	1606	PORT_START_TAG("IN0") // IN4
1608	1607	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
1609	1608	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1610	1609	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
r2864	r2865
1614	1613	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) // press in girl test to pause, button 3 advances
1615	1614	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1616	1615
1617		PORT_START // IN5
	1616	PORT_START_TAG("IN1") // IN5
1618	1617	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1619	1618	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
1620	1619	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1624	1623	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1625	1624	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1626	1625
1627		PORT_START // IN6
	1626	PORT_START_TAG("IN2") // IN6
1628	1627	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
1629	1628	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
1630	1629	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 )
r2864	r2865
1636	1635	INPUT_PORTS_END
1637	1636
1638	1637
1639
1640	1638	static INPUT_PORTS_START( grtwall )
1641		PORT_START // IN0 - DSW3
	1639	PORT_START_TAG("DSW1") // IN0 - DSW3
1642	1640	PORT_DIPNAME( 0xff, 0xff, "3" )
1643	1641	PORT_DIPSETTING( 0xff, DEF_STR( Off ) )
1644	1642	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1645	1643
1646		PORT_START // IN1 - DSW2
	1644	PORT_START_TAG("DSW2") // IN1 - DSW2
1647	1645	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Unknown ) )
1648	1646	PORT_DIPSETTING( 0x03, "1000" )
1649	1647	PORT_DIPSETTING( 0x02, "1500" )
r2864	r2865
1667	1665	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1668	1666	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1669	1667
1670		PORT_START // IN2 - DSW1
	1668	PORT_START_TAG("DSW3") // IN2 - DSW1
1671	1669	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
1672	1670	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
1673	1671	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r2864	r2865
1691	1689	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1692	1690	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
1693	1691
1694		PORT_START // IN3 - DSW4
	1692	PORT_START_TAG("DSW4") // IN3 - DSW4
1695	1693	PORT_DIPNAME( 0xff, 0xff, "4" )
1696	1694	PORT_DIPSETTING( 0xff, DEF_STR( Off ) )
1697	1695	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1698	1696
1699		PORT_START // IN4
	1697	PORT_START_TAG("COIN") // IN4
1700	1698	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1701	1699	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1702	1700	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // keep pressed while booting
r2864	r2865
1706	1704	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1707	1705	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1708	1706
1709		PORT_START // IN5
	1707	PORT_START_TAG("IN0") // IN5
1710	1708	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
1711	1709	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
1712	1710	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
r2864	r2865
1719	1717
1720	1718
1721	1719	static INPUT_PORTS_START( lhb )
1722		PORT_START // IN0 - DSW1
	1720	PORT_START_TAG("DSW1") // IN0 - DSW1
1723	1721	PORT_DIPNAME( 0x0f, 0x07, "Pay Out (%)" )
1724	1722	PORT_DIPSETTING( 0x0f, "96" )
1725	1723	PORT_DIPSETTING( 0x0e, "93" )
r2864	r2865
1748	1746	PORT_DIPSETTING( 0x40, "10" )
1749	1747	PORT_DIPSETTING( 0x00, "20" )
1750	1748
1751		PORT_START // IN1 - DSW2
	1749	PORT_START_TAG("DSW2") // IN1 - DSW2
1752	1750	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
1753	1751	PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
1754	1752	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
r2864	r2865
1772	1770	PORT_DIPSETTING( 0x80, "2" )
1773	1771	// PORT_DIPSETTING( 0x00, "2" )
1774	1772
1775		PORT_START // IN2 - DSW3
	1773	PORT_START_TAG("DSW3") // IN2 - DSW3
1776	1774	PORT_DIPNAME( 0x03, 0x03, "Max Credit" )
1777	1775	PORT_DIPSETTING( 0x03, "1000" )
1778	1776	PORT_DIPSETTING( 0x02, "2000" )
r2864	r2865
1795	1793	PORT_DIPSETTING( 0x40, "5" )
1796	1794	PORT_DIPSETTING( 0x00, "8" )
1797	1795
1798		PORT_START // IN3 - DSW4
	1796	PORT_START_TAG("DSW4") // IN3 - DSW4
1799	1797	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
1800	1798	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1801	1799	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
1820	1818	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
1821	1819	PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
1822	1820
1823		PORT_START // IN4 - DSW5
	1821	PORT_START_TAG("DSW5") // IN4 - DSW5
1824	1822	PORT_DIPNAME( 0xff, 0xff, "5" )
1825	1823	PORT_DIPSETTING( 0xff, DEF_STR( Off ) )
1826	1824	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1827	1825
1828		PORT_START // IN5
	1826	PORT_START_TAG("COIN") // IN5
1829	1827	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1830	1828	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1831	1829	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // keep pressed while booting
r2864	r2865
1835	1833	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1836	1834	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1837	1835
1838		PORT_START // IN6
	1836	PORT_START_TAG("KEY0") // IN6
1839	1837	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
1840	1838	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
1841	1839	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
r2864	r2865
1845	1843	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1846	1844	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1847	1845
1848		PORT_START // IN7
	1846	PORT_START_TAG("KEY1") // IN7
1849	1847	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
1850	1848	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
1851	1849	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
r2864	r2865
1855	1853	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1856	1854	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1857	1855
1858		PORT_START // IN8
	1856	PORT_START_TAG("KEY2") // IN8
1859	1857	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
1860	1858	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
1861	1859	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
r2864	r2865
1865	1863	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1866	1864	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1867	1865
1868		PORT_START // IN9
	1866	PORT_START_TAG("KEY3") // IN9
1869	1867	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
1870	1868	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
1871	1869	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
r2864	r2865
1875	1873	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1876	1874	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1877	1875
1878		PORT_START // IN10
	1876	PORT_START_TAG("KEY4") // IN10
1879	1877	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1880	1878	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1881	1879	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1888	1886
1889	1887
1890	1888	static INPUT_PORTS_START( vbowl )
1891		PORT_START // IN0 - DSW1
	1889	PORT_START_TAG("DSW1") // IN0 - DSW1
1892	1890	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
1893	1891	PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) )
1894	1892	PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) )
r2864	r2865
1914	1912	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1915	1913	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1916	1914
1917		PORT_START // IN1 - DSW2
	1915	PORT_START_TAG("DSW2") // IN1 - DSW2
1918	1916	PORT_DIPNAME( 0x03, 0x02, DEF_STR( Difficulty ) )
1919	1917	PORT_DIPSETTING( 0x03, DEF_STR( Easy ) ) // 5
1920	1918	PORT_DIPSETTING( 0x02, DEF_STR( Normal ) ) // 7
r2864	r2865
1938	1936	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1939	1937	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1940	1938
1941		PORT_START // IN2 - DSW3
	1939	PORT_START_TAG("DSW3") // IN2 - DSW3
1942	1940	PORT_DIPNAME( 0x03, 0x03, "Cabinet ID" )
1943	1941	PORT_DIPSETTING( 0x03, "1" )
1944	1942	PORT_DIPSETTING( 0x02, "2" )
r2864	r2865
1961	1959	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1962	1960	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1963	1961
1964		PORT_START // IN3 - DSW4
	1962	PORT_START_TAG("DSW4") // IN3 - DSW4
1965	1963	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1966	1964	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1967	1965	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
1987	1985	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1988	1986	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1989	1987
1990		PORT_START // IN4
	1988	PORT_START_TAG("COIN") // IN4
1991	1989	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1992	1990	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1993	1991	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1997	1995	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1998	1996	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1999	1997
2000		PORT_START // IN5
	1998	PORT_START_TAG("IN0") // IN5
2001	1999	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
2002	2000	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
2003	2001	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
r2864	r2865
2007	2005	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 )
2008	2006	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 )
2009	2007
2010		PORT_START // IN6
	2008	PORT_START_TAG("IN1") // IN6
2011	2009	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
2012	2010	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
2013	2011	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
r2864	r2865
2017	2015	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
2018	2016	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
2019	2017
2020		PORT_START // IN7
	2018	PORT_START_TAG("AN0") // IN7
2021	2019	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(30) PORT_KEYDELTA(30) PORT_PLAYER(1)
2022	2020
2023		PORT_START // IN8
	2021	PORT_START_TAG("AN1") // IN8
2024	2022	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(30) PORT_KEYDELTA(30) PORT_PLAYER(1)
2025	2023	INPUT_PORTS_END
2026	2024
2027	2025
2028	2026	static INPUT_PORTS_START( vbowlj )
2029		PORT_START // IN0 - DSW1
	2027	PORT_START_TAG("DSW1") // IN0 - DSW1
2030	2028	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
2031	2029	PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) )
2032	2030	PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) )
r2864	r2865
2052	2050	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2053	2051	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2054	2052
2055		PORT_START // IN1 - DSW2
	2053	PORT_START_TAG("DSW2") // IN1 - DSW2
2056	2054	PORT_DIPNAME( 0x03, 0x02, DEF_STR( Difficulty ) )
2057	2055	PORT_DIPSETTING( 0x03, DEF_STR( Easy ) ) // 5
2058	2056	PORT_DIPSETTING( 0x02, DEF_STR( Normal ) ) // 7
r2864	r2865
2076	2074	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2077	2075	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2078	2076
2079		PORT_START // IN2 - DSW3
	2077	PORT_START_TAG("DSW3") // IN2 - DSW3
2080	2078	PORT_DIPNAME( 0x03, 0x03, "Cabinet ID" )
2081	2079	PORT_DIPSETTING( 0x03, "1" )
2082	2080	PORT_DIPSETTING( 0x02, "2" )
r2864	r2865
2099	2097	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2100	2098	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
2101	2099
2102		PORT_START // IN3 - DSW4
	2100	PORT_START_TAG("DSW4") // IN3 - DSW4
2103	2101	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
2104	2102	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
2105	2103	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
2125	2123	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2126	2124	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2127	2125
2128		PORT_START // IN4
	2126	PORT_START_TAG("COIN") // IN4
2129	2127	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
2130	2128	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
2131	2129	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
2135	2133	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2136	2134	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2137	2135
2138		PORT_START // IN5
	2136	PORT_START_TAG("IN0") // IN5
2139	2137	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
2140	2138	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
2141	2139	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
r2864	r2865
2145	2143	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 )
2146	2144	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 )
2147	2145
2148		PORT_START // IN6
	2146	PORT_START_TAG("IN1") // IN6
2149	2147	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START2 )
2150	2148	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
2151	2149	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
r2864	r2865
2155	2153	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
2156	2154	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
2157	2155
2158		PORT_START // IN7
	2156	PORT_START_TAG("AN0") // IN7
2159	2157	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(30) PORT_KEYDELTA(30) PORT_PLAYER(1)
2160	2158
2161		PORT_START // IN8
	2159	PORT_START_TAG("AN1") // IN8
2162	2160	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(30) PORT_KEYDELTA(30) PORT_PLAYER(1)
2163	2161	INPUT_PORTS_END
2164	2162
2165	2163
2166	2164	static INPUT_PORTS_START( xymg )
2167		PORT_START // IN0 - DSW1
	2165	PORT_START_TAG("DSW1") // IN0 - DSW1
2168	2166	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
2169	2167	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
2170	2168	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r2864	r2865
2188	2186	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
2189	2187	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
2190	2188
2191		PORT_START // IN1 - DSW2
	2189	PORT_START_TAG("DSW2") // IN1 - DSW2
2192	2190	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Unknown ) )
2193	2191	PORT_DIPSETTING( 0x03, "1000" )
2194	2192	PORT_DIPSETTING( 0x02, "1500" )
r2864	r2865
2212	2210	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
2213	2211	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2214	2212
2215		PORT_START // IN2 - DSW3
	2213	PORT_START_TAG("DSW3") // IN2 - DSW3
2216	2214	PORT_DIPNAME( 0xff, 0xff, DEF_STR( Unused ) )
2217	2215	PORT_DIPSETTING( 0xff, DEF_STR( Off ) )
2218	2216	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2219	2217
2220		PORT_START // IN3
	2218	PORT_START_TAG("COIN") // IN3
2221	2219	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2222	2220	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2223	2221	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // keep pressed while booting
r2864	r2865
2227	2225	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2228	2226	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2229	2227
2230		PORT_START // IN4
	2228	PORT_START_TAG("KEY0") // IN4
2231	2229	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
2232	2230	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
2233	2231	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
r2864	r2865
2237	2235	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2238	2236	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2239	2237
2240		PORT_START // IN5
	2238	PORT_START_TAG("KEY1") // IN5
2241	2239	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
2242	2240	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
2243	2241	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
r2864	r2865
2247	2245	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2248	2246	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2249	2247
2250		PORT_START // IN6
	2248	PORT_START_TAG("KEY2") // IN6
2251	2249	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
2252	2250	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
2253	2251	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
r2864	r2865
2257	2255	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2258	2256	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2259	2257
2260		PORT_START // IN7
	2258	PORT_START_TAG("KEY3") // IN7
2261	2259	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
2262	2260	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
2263	2261	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
r2864	r2865
2267	2265	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2268	2266	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2269	2267
2270		PORT_START // IN8
	2268	PORT_START_TAG("KEY4") // IN8
2271	2269	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE )
2272	2270	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE )
2273	2271	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP )

src/mame/drivers/goal92.c
r2864	r2865
40	40	switch(offset)
41	41	{
42	42	case 0:
43		return input_port_read~~_indexed~~(machine, 0);
	43	return input_port_read(machine, "DSW1");
44	44	case 1:
45		return input_port_read~~_indexed~~(machine, 1);
	45	return input_port_read(machine, "IN1");
46	46	case 2:
47		return input_port_read~~_indexed~~(machine, 2);
	47	return input_port_read(machine, "IN2");
48	48	case 3:
49		return input_port_read~~_indexed~~(machine, 3);
	49	return input_port_read(machine, "IN3");
50	50	case 7:
51		return input_port_read~~_indexed~~(machine, 4);
	51	return input_port_read(machine, "DSW2");
52	52
53	53	default:
54	54	logerror("reading unhandled goal92 inputs %04X %04X @ PC = %04X\n",offset, mem_mask,activecpu_get_pc());

src/mame/drivers/raiden.c
r2864	r2865
49	49	VIDEO_START( raiden );
50	50	VIDEO_START( raidena );
51	51	WRITE16_HANDLER( raiden_control_w );
	52	WRITE16_HANDLER( raidena_control_w );
52	53	VIDEO_UPDATE( raiden );
53	54
54	55	static UINT16 *raiden_shared_ram;
r2864	r2865
86	87	AM_RANGE(0x07000, 0x07fff) AM_RAM AM_BASE(&spriteram16) AM_SIZE(&spriteram_size)
87	88	AM_RANGE(0x08000, 0x08fff) AM_RAM AM_SHARE(1) AM_BASE(&raiden_shared_ram)
88	89	AM_RANGE(0x0a000, 0x0a00d) AM_READWRITE(seibu_main_word_r, seibu_main_word_w)
89		AM_RANGE(0x0b000, 0x0b007) AM_WRITE(raiden_control_w)
90	90	AM_RANGE(0x0c000, 0x0c7ff) AM_WRITE(raiden_text_w) AM_BASE(&videoram16)
91	91	AM_RANGE(0x0e000, 0x0e001) AM_READ(input_port_1_word_r)
	92	AM_RANGE(0x0e000, 0x0e007) AM_WRITE(raidena_control_w)
92	93	AM_RANGE(0x0e002, 0x0e003) AM_READ(input_port_2_word_r)
93	94	AM_RANGE(0x0f000, 0x0f035) AM_WRITE(SMH_RAM) AM_BASE(&raiden_scroll_ram)
94	95	AM_RANGE(0xa0000, 0xfffff) AM_ROM

src/mame/drivers/fromanc2.c
r2864	r2865
155	155	UINT16 ret;
156	156
157	157	switch (fromanc2_portselect) {
158		case 0x01: ret = input_port_read(machine, "IN1"); break;
	158	case 0x01: ret = input_port_read(machine, "IN1"); break;
159	159	case 0x02: ret = input_port_read(machine, "IN2"); break;
160	160	case 0x04: ret = input_port_read(machine, "IN3"); break;
161	161	case 0x08: ret = input_port_read(machine, "IN4"); break;
r2864	r2865
175	175	((fromanc2_subcpu_nmi_flag & 1) << 6) \|
176	176	((fromanc2_sndcpu_nmi_flag & 1) << 5));
177	177	eeprom = (eeprom_read_bit() & 1) << 7; // EEPROM DATA
178		coinsw = input_port_read~~_indexed~~(machine, 0) & 0x030f; // COIN, TEST
	178	coinsw = input_port_read(machine, "IN0") & 0x030f; // COIN, TEST
179	179
180	180	return (cflag \| eeprom \| coinsw);
181	181	}
r2864	r2865
186	186
187	187	cflag = (fromanc2_sndcpu_nmi_flag & 1) << 5;
188	188	eeprom = (eeprom_read_bit() & 1) << 7; // EEPROM DATA
189		coinsw = input_port_read~~_indexed~~(machine, 0) & 0x001f; // COIN, TEST
	189	coinsw = input_port_read(machine, "IN0") & 0x001f; // COIN, TEST
190	190
191	191	return (cflag \| eeprom \| coinsw);
192	192	}

src/mame/drivers/gridlee.c
r2864	r2865
172	172	{
173	173	int delta, sign, magnitude;
174	174	UINT8 newval;
	175	static const char *portnames[] = { "TRACK0_Y", "TRACK0_X", "TRACK1_Y", "TRACK1_X" };
175	176
176	177	/* first read the new trackball value and compute the signed delta */
177		newval = input_port_read~~_indexed~~(machine, offset + 2 * gridlee_cocktail_flip);
	178	newval = input_port_read(machine, portnames[offset + 2 * gridlee_cocktail_flip]);
178	179	delta = (int)newval - (int)last_analog_input[offset];
179	180
180	181	/* handle the case where we wrap around from 0x00 to 0xff, or vice versa */
r2864	r2865
300	301	static ADDRESS_MAP_START( readmem_cpu1, ADDRESS_SPACE_PROGRAM, 8 )
301	302	AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_RAM)
302	303	AM_RANGE(0x9500, 0x9501) AM_READ(analog_port_r)
303		AM_RANGE(0x9502, 0x9502) AM_READ(input_port_4_r)
304		AM_RANGE(0x9503, 0x9503) AM_READ(input_port_5_r)
305		AM_RANGE(0x9600, 0x9600) AM_READ(input_port_6_r)
306		AM_RANGE(0x9700, 0x9700) AM_READ(input_port_7_r)
	304	AM_RANGE(0x9502, 0x9502) AM_READ_PORT("IN0")
	305	AM_RANGE(0x9503, 0x9503) AM_READ_PORT("IN1")
	306	AM_RANGE(0x9600, 0x9600) AM_READ_PORT("DSW")
	307	AM_RANGE(0x9700, 0x9700) AM_READ_PORT("IN2")
307	308	AM_RANGE(0x9820, 0x9820) AM_READ(random_num_r)
308	309	AM_RANGE(0x9c00, 0x9cff) AM_READ(SMH_RAM)
309	310	AM_RANGE(0xa000, 0xffff) AM_READ(SMH_ROM)
r2864	r2865
335	336	*************************************/
336	337
337	338	static INPUT_PORTS_START( gridlee )
338		PORT_START /* 9500 (fake) */
	339	PORT_START_TAG("TRACK0_Y") /* 9500 (fake) */
339	340	PORT_BIT( 0xff, 0, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(8)
340	341
341		PORT_START /* 9501 (fake) */
	342	PORT_START_TAG("TRACK0_X") /* 9501 (fake) */
342	343	PORT_BIT( 0xff, 0, IPT_TRACKBALL_X ) PORT_SENSITIVITY(20) PORT_KEYDELTA(8) PORT_REVERSE
343	344
344		PORT_START /* 9500 (fake) */
	345	PORT_START_TAG("TRACK1_Y") /* 9500 (fake) */
345	346	PORT_BIT( 0xff, 0, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(8) PORT_COCKTAIL
346	347
347		PORT_START /* 9501 (fake) */
	348	PORT_START_TAG("TRACK1_X") /* 9501 (fake) */
348	349	PORT_BIT( 0xff, 0, IPT_TRACKBALL_X ) PORT_SENSITIVITY(20) PORT_KEYDELTA(8) PORT_REVERSE PORT_COCKTAIL
349	350
350		PORT_START /* 9502 */
	351	PORT_START_TAG("IN0") /* 9502 */
351	352	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
352	353	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
353	354	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNKNOWN )
354	355
355		PORT_START /* 9503 */
	356	PORT_START_TAG("IN1") /* 9503 */
356	357	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
357	358	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
358	359	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r2864	r2865
363	364	PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ))
364	365	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNKNOWN )
365	366
366		PORT_START /* 9600 */
	367	PORT_START_TAG("DSW") /* 9600 */
367	368	PORT_DIPNAME( 0x03, 0x01, DEF_STR( Bonus_Life ))
368	369	PORT_DIPSETTING( 0x00, "8000 points" )
369	370	PORT_DIPSETTING( 0x01, "10000 points" )
r2864	r2865
387	388	PORT_DIPSETTING( 0x00, DEF_STR( No ))
388	389	PORT_DIPSETTING( 0x80, DEF_STR( Yes ))
389	390
390		PORT_START /* 9700 */
	391	PORT_START_TAG("IN2") /* 9700 */
391	392	PORT_BIT( 0x1f, IP_ACTIVE_LOW, IPT_UNKNOWN )
392	393	PORT_SERVICE( 0x20, IP_ACTIVE_LOW )
393	394	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )

src/mame/drivers/bnstars.c
r2864	r2865
298	298	}
299	299
300	300
301		static void update_color(int color, int screen)
	301	static void update_color(running_machine *machine, int color, int screen)
302	302	{
303	303	int r,g,b;
304	304
r2864	r2865
306	306	g = ((ms32_pal_ram[screen][color*2] & 0x00ff) >>0 );
307	307	b = ((ms32_pal_ram[screen][color*2+1] & 0x00ff) >>0 );
308	308
309		palette_set_color(Machine,color+screen*0x8000,MAKE_RGB(r,g,b));
	309	palette_set_color(machine,color+screen*0x8000,MAKE_RGB(r,g,b));
310	310	}
311	311
312	312	static WRITE32_HANDLER( ms32_pal0_ram_w )
313	313	{
314	314	COMBINE_DATA(&ms32_pal_ram[0][offset]);
315		update_color(offset/2, 0);
	315	update_color(machine, offset/2, 0);
316	316	}
317	317
318	318	static WRITE32_HANDLER( ms32_pal1_ram_w )
319	319	{
320	320	COMBINE_DATA(&ms32_pal_ram[1][offset]);
321		update_color(offset/2, 1);
	321	update_color(machine, offset/2, 1);
322	322	}
323	323
324	324	static int ms32_reverse_sprite_order = 0;

src/mame/drivers/gcpinbal.c
r2864	r2865
81	81	switch (offset)
82	82	{
83	83	case 0x80/2:
84		return input_port_read~~_indexed~~(machine,0); /* DSW */
	84	return input_port_read(machine, "DSW");
85	85
86	86	case 0x84/2:
87		return input_port_read~~_indexed~~(machine,1); /* IN0 */
	87	return input_port_read(machine, "IN0");
88	88
89	89	case 0x86/2:
90		return input_port_read~~_indexed~~(machine,2); /* IN1 */
	90	return input_port_read(machine, "IN1");
91	91
92	92	case 0x50:
93	93	case 0x51:
r2864	r2865
231	231	***********************************************************/
232	232
233	233	static INPUT_PORTS_START( gcpinbal )
234		PORT_START /* DSW */
	234	PORT_START_TAG("DSW") /* DSW */
235	235	PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Difficulty ) )
236	236	PORT_DIPSETTING( 0x0002, DEF_STR( Easy ) )
237	237	PORT_DIPSETTING( 0x0003, DEF_STR( Normal ) )
r2864	r2865
278	278	PORT_DIPSETTING( 0x8000, "4" )
279	279	PORT_DIPSETTING( 0x4000, "5" )
280	280
281		PORT_START /* IN0 */
	281	PORT_START_TAG("IN0") /* IN0 */
282	282	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
283	283	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
284	284	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
296	296	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON7 ) PORT_PLAYER(1) // Tilt left
297	297	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START1 )
298	298
299		PORT_START /* IN1 */
	299	PORT_START_TAG("IN1") /* IN1 */
300	300	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
301	301	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
302	302	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )

src/mame/drivers/gundealr.c
r2864	r2865
73	73	{
74	74	if (input_ports_hack)
75	75	{
76		rambase[0x004] = input_port_read_indexed(machine, 4); /* COIN */
77		rambase[0x005] = input_port_read_indexed(machine, 3); /* IN1 */
78		rambase[0x006] = input_port_read_indexed(machine, 2); /* IN0 */
	76	rambase[0x004] = input_port_read(machine, "IN2");
	77	rambase[0x005] = input_port_read(machine, "IN1");
	78	rambase[0x006] = input_port_read(machine, "IN0");
79	79	}
80	80	cpunum_set_input_line_and_vector(machine, 0, 0, HOLD_LINE, 0xd7); /* RST 10h vblank */
81	81	}
r2864	r2865
158	158	static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 )
159	159	AM_RANGE(0x0000, 0x7fff) AM_ROM
160	160	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK(1)
161		AM_RANGE(0xc000, 0xc000) AM_READ(input_port_0_r) /* DSW0 */
162		AM_RANGE(0xc001, 0xc001) AM_READ(input_port_1_r) /* DSW1 */
163		AM_RANGE(0xc004, 0xc004) AM_READ(input_port_2_r) /* COIN (Gun Dealer only) */
164		AM_RANGE(0xc005, 0xc005) AM_READ(input_port_3_r) /* IN1 (Gun Dealer only) */
165		AM_RANGE(0xc006, 0xc006) AM_READ(input_port_4_r) /* IN0 (Gun Dealer only) */
	161	AM_RANGE(0xc000, 0xc000) AM_READ_PORT("DSW0") /* DSW0 */
	162	AM_RANGE(0xc001, 0xc001) AM_READ_PORT("DSW1") /* DSW1 */
	163	AM_RANGE(0xc004, 0xc004) AM_READ_PORT("IN0") /* COIN (Gun Dealer only) */
	164	AM_RANGE(0xc005, 0xc005) AM_READ_PORT("IN1") /* IN1 (Gun Dealer only) */
	165	AM_RANGE(0xc006, 0xc006) AM_READ_PORT("IN2") /* IN0 (Gun Dealer only) */
166	166	AM_RANGE(0xc010, 0xc013) AM_WRITE(yamyam_fg_scroll_w) /* Yam Yam only */
167	167	AM_RANGE(0xc014, 0xc014) AM_WRITE(gundealr_flipscreen_w)
168	168	AM_RANGE(0xc016, 0xc016) AM_WRITE(yamyam_bankswitch_w)
r2864	r2865
182	182
183	183
184	184	static INPUT_PORTS_START( gundealr )
185		PORT_START /* DSW0 */
	185	PORT_START_TAG("DSW0") /* DSW0 */
186	186	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
187	187	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
188	188	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
207	207	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
208	208	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
209	209
210		PORT_START /* DSW1 */
	210	PORT_START_TAG("DSW1") /* DSW1 */
211	211	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coin_A ) )
212	212	PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
213	213	PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
r2864	r2865
232	232	PORT_DIPSETTING( 0x80, "2" )
233	233	PORT_DIPSETTING( 0xc0, "3" )
234	234
235		PORT_START /* COIN */
	235	PORT_START_TAG("IN0") /* COIN */
236	236	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
237	237	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
238	238	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
242	242	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
243	243	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
244	244
245		PORT_START /* ~~IN1~~ */
	245	PORT_START_TAG("IN1") /* Player 2 controls */
246	246	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(2)
247	247	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(2)
248	248	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(2)
r2864	r2865
252	252	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
253	253	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
254	254
255		PORT_START /* ~~IN0~~ */
	255	PORT_START_TAG("IN2") /* Player 1 controls */
256	256	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(1)
257	257	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(1)
258	258	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(1)
r2864	r2865
264	264	INPUT_PORTS_END
265	265
266	266	static INPUT_PORTS_START( gundealt )
267		PORT_START /* DSW0 */
	267	PORT_START_TAG("DSW0") /* DSW0 */
268	268	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
269	269	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
270	270	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
289	289	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
290	290	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
291	291
292		PORT_START /* DSW1 */
	292	PORT_START_TAG("DSW1") /* DSW1 */
293	293	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coin_A ) )
294	294	PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
295	295	PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
r2864	r2865
314	314	PORT_DIPSETTING( 0x80, "2" )
315	315	PORT_DIPSETTING( 0xc0, "3" )
316	316
317		PORT_START /* ~~IN0~~ */
	317	PORT_START_TAG("IN0") /* Player 1 controls */
318	318	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(1)
319	319	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(1)
320	320	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(1)
r2864	r2865
324	324	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
325	325	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
326	326
327		PORT_START /* ~~IN1~~ */
	327	PORT_START_TAG("IN1") /* Player 2 controls */
328	328	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(2)
329	329	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(2)
330	330	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(2)
r2864	r2865
334	334	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
335	335	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
336	336
337		PORT_START /* COIN */
	337	PORT_START_TAG("IN2") /* COIN */
338	338	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
339	339	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
340	340	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
346	346	INPUT_PORTS_END
347	347
348	348	static INPUT_PORTS_START( yamyam )
349		PORT_START /* DSW0 */
	349	PORT_START_TAG("DSW0") /* DSW0 */
350	350	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Lives ) )
351	351	PORT_DIPSETTING( 0x00, "3" )
352	352	PORT_DIPSETTING( 0x01, "4" )
r2864	r2865
370	370	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
371	371	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
372	372
373		PORT_START /* DSW1 */
	373	PORT_START_TAG("DSW1") /* DSW1 */
374	374	PORT_DIPNAME( 0x07, 0x00, DEF_STR( Coin_A ) )
375	375	PORT_DIPSETTING( 0x07, DEF_STR( 5C_1C ) )
376	376	PORT_DIPSETTING( 0x06, DEF_STR( 4C_1C ) )
r2864	r2865
394	394	PORT_DIPSETTING( 0x40, DEF_STR( On ) )
395	395	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
396	396
397		PORT_START /* COIN */
	397	PORT_START_TAG("IN0") /* COIN */
398	398	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
399	399	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
400	400	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
404	404	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
405	405	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
406	406
407		PORT_START /* ~~IN1~~ */
	407	PORT_START_TAG("IN1") /* Player 2 controls */
408	408	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(2)
409	409	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(2)
410	410	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(2)
r2864	r2865
414	414	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
415	415	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
416	416
417		PORT_START /* ~~IN0~~ */
	417	PORT_START_TAG("IN2") /* Player 1 controls */
418	418	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(1)
419	419	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(1)
420	420	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(1)

src/mame/drivers/namcos1.c
r2864	r2865
2435	2435	GAME( 1990, soukobdx, boxyboy, ns1, boxyboy, soukobdx, ROT0, "Namco", "Souko Ban Deluxe (Japan)", 0 )
2436	2436	GAME( 1990, puzlclub, 0, ns1, puzlclub, puzlclub, ROT90, "Namco", "Puzzle Club (Japan prototype)", 0 )
2437	2437	GAME( 1991, tankfrce, 0, ns1, ns1, tankfrce, ROT0, "Namco", "Tank Force (US, 2 Player)", 0 )
2438		GAME( 1991, tankfrc4, tankfrce, ns1, tankfrc4, tankfrce, ROT0, "Namco", "Tank Force (US, 4 Player)", GAME_NOT_WORKING ) /* No controls */
	2438	GAME( 1991, tankfrc4, tankfrce, ns1, tankfrc4, tankfrc4, ROT0, "Namco", "Tank Force (US, 4 Player)", GAME_NOT_WORKING ) /* No controls */
2439	2439	GAME( 1991, tankfrcj, tankfrce, ns1, ns1, tankfrce, ROT0, "Namco", "Tank Force (Japan)", 0 )
2440	2440

src/mame/drivers/deco156.c
r2864	r2865
150	150
151	151	static READ32_HANDLER(hvysmsh_eeprom_r)
152	152	{
153		return (eeprom_read_bit()<<24) \| input_port_read~~_indexed~~(machine, 0) \| (input_port_read~~_indexed~~(machine, 1)<<16);
	153	return (eeprom_read_bit()<<24) \| input_port_read(machine, "IN0") \| (input_port_read(machine, "IN1")<<16);
154	154	}
155	155
156	156	static WRITE32_HANDLER(hvysmsh_eeprom_w)
r2864	r2865
193	193
194	194	static READ32_HANDLER(wcvol95_eeprom_r)
195	195	{
196		return (eeprom_read_bit()<<24) \| input_port_read~~_indexed~~(machine, 0) \| ((input_port_read~~_indexed~~(machine, 1)&0xff)<<16);
	196	return (eeprom_read_bit()<<24) \| input_port_read(machine, "IN0") \| ((input_port_read(machine, "IN1") & 0xff)<<16);
197	197	}
198	198
199	199	static WRITE32_HANDLER(wcvol95_eeprom_w)
r2864	r2865
278	278	/***************************************************************************/
279	279
280	280	static INPUT_PORTS_START( hvysmsh )
281		PORT_START
	281	PORT_START_TAG("IN0")
282	282	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
283	283	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
284	284	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
296	296	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
297	297	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
298	298
299		PORT_START
	299	PORT_START_TAG("IN1")
300	300	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
301	301	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
302	302	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
316	316	INPUT_PORTS_END
317	317
318	318	static INPUT_PORTS_START( wcvol95 )
319		PORT_START
	319	PORT_START_TAG("IN0")
320	320	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
321	321	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
322	322	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
334	334	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
335	335	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
336	336
337		PORT_START
	337	PORT_START_TAG("IN1")
338	338	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
339	339	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
340	340	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )

src/mame/drivers/ertictac.c
r2864	r2865
41	41
42	42	static READ32_HANDLER(IOCR_r)
43	43	{
44		return (input_port_read~~_indexed~~(machine, 5)&0x80)\|0x34;
	44	return (input_port_read(machine, "dummy") & 0x80) \| 0x34;
45	45	}
46	46
47	47	static WRITE32_HANDLER(IOCR_w)
r2864	r2865
179	179	ADDRESS_MAP_END
180	180
181	181	static INPUT_PORTS_START( ertictac )
182		PORT_START_TAG("IN 0")
	182	PORT_START_TAG("IN0")
183	183	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START2 )
184	184	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START1 )
185	185	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_IMPULSE(1)
186	186	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
187	187
188		PORT_START_TAG("IN 1")
	188	PORT_START_TAG("IN1")
189	189	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
190	190	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
191	191	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
192	192	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
193	193	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
194	194
195		PORT_START_TAG("IN 2")
	195	PORT_START_TAG("IN2")
196	196	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
197	197	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
198	198	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
199	199	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
200	200	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
201	201
202		PORT_START_TAG("DSW 1")
	202	PORT_START_TAG("DSW1")
203	203	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Language ) )
204	204	PORT_DIPSETTING( 0x01, DEF_STR( French ) )
205	205	PORT_DIPSETTING( 0x00, DEF_STR( English ) )
r2864	r2865
223	223	PORT_DIPSETTING( 0x40, "Difficult" )
224	224	PORT_DIPSETTING( 0x00, "Very Difficult" )
225	225
226		PORT_START_TAG("DSW 2")
	226	PORT_START_TAG("DSW2")
227	227	PORT_DIPNAME( 0x05, 0x00, DEF_STR( Coin_A ) )
228	228	PORT_DIPSETTING( 0x05, DEF_STR( 4C_1C ) )
229	229	PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) )
r2864	r2865
249	249	INPUT_PORTS_END
250	250
251	251	static INPUT_PORTS_START( poizone )
252		PORT_START_TAG("IN 0")
	252	PORT_START_TAG("IN0")
253	253	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START2 )
254	254	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START1 )
255	255	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_IMPULSE(1)
256	256	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
257	257
258		PORT_START_TAG("IN 1")
	258	PORT_START_TAG("IN1")
259	259	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
260	260	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
261	261	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
262	262	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
263	263	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
264	264
265		PORT_START_TAG("IN 2")
	265	PORT_START_TAG("IN2")
266	266	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
267	267	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
268	268	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
269	269	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
270	270	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
271	271
272		PORT_START_TAG("DSW 1")
	272	PORT_START_TAG("DSW1")
273	273	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Language ) ) // 01
274	274	PORT_DIPSETTING( 0x01, DEF_STR( English ) )
275	275	PORT_DIPSETTING( 0x00, DEF_STR( French ) )
r2864	r2865
293	293	PORT_DIPSETTING( 0x40, DEF_STR( 1C_3C ) )
294	294	PORT_DIPSETTING( 0xC0, DEF_STR( 1C_4C ) )
295	295
296		// PORT_START_TAG("DSW 2") /* DSW 2 doesn't work, may not be hooked up properly */
	296	PORT_START_TAG("DSW2") /* DSW 2 doesn't work, may not be hooked up properly */
297	297	// PORT_DIPNAME( 0x01, 0x01, "2-1" )
298	298	// PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
299	299	// PORT_DIPSETTING( 0x00, DEF_STR( On ) )

src/mame/drivers/jcross.c
r2864	r2865
70	70
71	71	static READ8_HANDLER( jcross_port_0_r )
72	72	{
73		return(input_port_read~~_indexed~~(machine, 0) \| sound_cpu_busy);
	73	return(input_port_read(machine, "IN0") \| sound_cpu_busy);
74	74	}
75	75
76	76	static WRITE8_HANDLER(jcross_vregs0_w){jcross_vregs[0]=data;}
r2864	r2865
100	100	static ADDRESS_MAP_START( cpuA_map, ADDRESS_SPACE_PROGRAM, 8 )
101	101	AM_RANGE(0x0000, 0x9fff) AM_ROM
102	102	AM_RANGE(0xa000, 0xa000) AM_READ(jcross_port_0_r)
103		AM_RANGE(0xa100, 0xa100) AM_READ(input_port_1_r)
104		AM_RANGE(0xa200, 0xa200) AM_READ(input_port_2_r)
	103	AM_RANGE(0xa100, 0xa100) AM_READ_PORT("IN1")
	104	AM_RANGE(0xa200, 0xa200) AM_READ_PORT("IN2")
105	105	AM_RANGE(0xa300, 0xa300) AM_WRITE(sound_command_w)
106		AM_RANGE(0xa400, 0xa400) AM_READ(input_port_3_r)
107		AM_RANGE(0xa500, 0xa500) AM_READ(input_port_4_r)
	106	AM_RANGE(0xa400, 0xa400) AM_READ_PORT("DSW1")
	107	AM_RANGE(0xa500, 0xa500) AM_READ_PORT("DSW2")
108	108	AM_RANGE(0xa600, 0xa600) AM_WRITE(jcross_palettebank_w)
109	109	AM_RANGE(0xa700, 0xa700) AM_READWRITE(snk_cpuB_nmi_trigger_r, snk_cpuA_nmi_ack_w)
110	110	AM_RANGE(0xd300, 0xd300) AM_WRITE(jcross_vregs0_w)
r2864	r2865
339	339	ROM_END
340	340
341	341	GAME( 1984, jcross, 0, jcross, jcross, 0, ROT270, "SNK", "Jumping Cross",GAME_NO_COCKTAIL\|GAME_IMPERFECT_GRAPHICS)
342
343

src/mame/drivers/nss.c
r2864	r2865
325	325	ADDRESS_MAP_END
326	326
327	327	static INPUT_PORTS_START( snes )
328		PORT_START /* IN 0 : Joypad 1 - L */
	328	PORT_START_TAG("PAD1L") /* IN 0 : Joypad 1 - L */
329	329	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("P1 Button A") PORT_PLAYER(1)
330	330	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("P1 Button X") PORT_PLAYER(1)
331	331	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("P1 Button L") PORT_PLAYER(1)
332	332	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("P1 Button R") PORT_PLAYER(1)
333		PORT_START /* IN 1 : Joypad 1 - H */
	333	PORT_START_TAG("PAD1H") /* IN 1 : Joypad 1 - H */
334	334	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P1 Button B") PORT_PLAYER(1)
335	335	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P1 Button Y") PORT_PLAYER(1)
336	336	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE1 ) PORT_NAME("P1 Select")
r2864	r2865
340	340	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
341	341	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
342	342
343		PORT_START /* IN 2 : Joypad 2 - L */
	343	PORT_START_TAG("PAD2L") /* IN 2 : Joypad 2 - L */
344	344	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("P2 Button A") PORT_PLAYER(2)
345	345	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("P2 Button X") PORT_PLAYER(2)
346	346	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("P2 Button L") PORT_PLAYER(2)
347	347	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("P2 Button R") PORT_PLAYER(2)
348		PORT_START /* IN 3 : Joypad 2 - H */
	348	PORT_START_TAG("PAD2H") /* IN 3 : Joypad 2 - H */
349	349	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P2 Button B") PORT_PLAYER(2)
350	350	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P2 Button Y") PORT_PLAYER(2)
351	351	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE2 ) PORT_NAME("P2 Select")
r2864	r2865
355	355	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
356	356	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
357	357
358		PORT_START /* IN 4 : Joypad 3 - L */
	358	PORT_START_TAG("PAD3L") /* IN 4 : Joypad 3 - L */
359	359	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("P3 Button A") PORT_PLAYER(3)
360	360	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("P3 Button X") PORT_PLAYER(3)
361	361	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("P3 Button L") PORT_PLAYER(3)
362	362	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("P3 Button R") PORT_PLAYER(3)
363		PORT_START /* IN 5 : Joypad 3 - H */
	363	PORT_START_TAG("PAD3H") /* IN 5 : Joypad 3 - H */
364	364	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P3 Button B") PORT_PLAYER(3)
365	365	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P3 Button Y") PORT_PLAYER(3)
366	366	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE3 ) PORT_NAME("P3 Select")
r2864	r2865
370	370	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(3)
371	371	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(3)
372	372
373		PORT_START /* IN 6 : Joypad 4 - L */
	373	PORT_START_TAG("PAD4L") /* IN 6 : Joypad 4 - L */
374	374	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("P4 Button A") PORT_PLAYER(4)
375	375	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("P4 Button X") PORT_PLAYER(4)
376	376	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("P4 Button L") PORT_PLAYER(4)
377	377	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("P4 Button R") PORT_PLAYER(4)
378		PORT_START /* IN 7 : Joypad 4 - H */
	378	PORT_START_TAG("PAD4H") /* IN 7 : Joypad 4 - H */
379	379	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P4 Button B") PORT_PLAYER(4)
380	380	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P4 Button Y") PORT_PLAYER(4)
381	381	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE4 ) PORT_NAME("P4 Select")
r2864	r2865
385	385	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(4)
386	386	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(4)
387	387
388		PORT_START /* IN 8 : dip-switches */
	388	PORT_START_TAG("DSW") /* IN 8 : dip-switches */
389	389	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Difficulty ) )
390	390	PORT_DIPSETTING( 0x00, DEF_STR( Normal ) )
391	391	PORT_DIPSETTING( 0x03, DEF_STR( Hard ) )

src/mame/drivers/jack.c
r2864	r2865
89	89
90	90	static READ8_HANDLER( joinem_input1_r )
91	91	{
92		UINT8 ret = input_port_read~~_indexed~~(machine, 1) & ~0x20;
	92	UINT8 ret = input_port_read(machine, "DSW2") & ~0x20;
93	93
94		if((input_port_read~~_indexed~~(machine, 4) & 0x80) && !joinem_snd_bit)
	94	if((input_port_read(machine, "IN2") & 0x80) && !joinem_snd_bit)
95	95	ret \|= 0x20;
96	96
97	97	return ret;
r2864	r2865
142	142	AM_RANGE(0x0000, 0x3fff) AM_READ(SMH_ROM)
143	143	AM_RANGE(0x4000, 0x5fff) AM_READ(SMH_RAM)
144	144	AM_RANGE(0xb000, 0xb07f) AM_READ(SMH_RAM)
145		AM_RANGE(0xb500, 0xb500) AM_READ(input_port_0_r)
146		AM_RANGE(0xb501, 0xb501) AM_READ(input_port_1_r)
147		AM_RANGE(0xb502, 0xb502) AM_READ(input_port_2_r)
148		AM_RANGE(0xb503, 0xb503) AM_READ(input_port_3_r)
149		AM_RANGE(0xb504, 0xb504) AM_READ(input_port_4_r)
150		AM_RANGE(0xb505, 0xb505) AM_READ(input_port_5_r)
	145	AM_RANGE(0xb500, 0xb500) AM_READ_PORT("DSW1")
	146	AM_RANGE(0xb501, 0xb501) AM_READ_PORT("DSW2")
	147	AM_RANGE(0xb502, 0xb502) AM_READ_PORT("IN0")
	148	AM_RANGE(0xb503, 0xb503) AM_READ_PORT("IN1")
	149	AM_RANGE(0xb504, 0xb504) AM_READ_PORT("IN2")
	150	AM_RANGE(0xb505, 0xb505) AM_READ_PORT("IN3")
151	151	AM_RANGE(0xb506, 0xb507) AM_READ(jack_flipscreen_r)
152	152	AM_RANGE(0xb800, 0xbfff) AM_READ(SMH_RAM)
153	153	AM_RANGE(0xc000, 0xffff) AM_READ(SMH_ROM)
r2864	r2865
170	170	AM_RANGE(0x8000, 0x8fff) AM_RAM
171	171	AM_RANGE(0xb000, 0xb0ff) AM_RAM AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
172	172	AM_RANGE(0xb400, 0xb400) AM_WRITE(jack_sh_command_w)
173		AM_RANGE(0xb500, 0xb500) AM_READ~~(input~~_~~port_0_r~~)
	173	AM_RANGE(0xb500, 0xb500) AM_READ_PORT("DSW1")
174	174	AM_RANGE(0xb501, 0xb501) AM_READ(joinem_input1_r)
175		AM_RANGE(0xb502, 0xb502) AM_READ(input_port_2_r)
176		AM_RANGE(0xb503, 0xb503) AM_READ(input_port_3_r)
177		AM_RANGE(0xb504, 0xb504) AM_READ(input_port_4_r)
	175	AM_RANGE(0xb502, 0xb502) AM_READ_PORT("IN0")
	176	AM_RANGE(0xb503, 0xb503) AM_READ_PORT("IN1")
	177	AM_RANGE(0xb504, 0xb504) AM_READ_PORT("IN2")
178	178	AM_RANGE(0xb506, 0xb507) AM_READWRITE(jack_flipscreen_r, jack_flipscreen_w)
179	179	AM_RANGE(0xb700, 0xb700) AM_WRITE(joinem_misc_w)
180	180	AM_RANGE(0xb800, 0xbbff) AM_RAM_WRITE(jack_videoram_w) AM_BASE(&videoram)
r2864	r2865
232	232	PORT_DIPNAME( 0x80, 0x00, "255 Lives (Cheat)")\
233	233	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )\
234	234	PORT_DIPSETTING( 0x80, DEF_STR( On ) )\
235		PORT_START_TAG("IN2")\
	235	PORT_START_TAG("IN0")\
236	236	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )\
237	237	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )\
238	238	PORT_BIT( 0x1c, IP_ACTIVE_HIGH, IPT_UNUSED )\
239	239	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN2 )\
240	240	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN1 )\
241	241	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )\
242		PORT_START_TAG("IN3")\
	242	PORT_START_TAG("IN1")\
243	243	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY\
244	244	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY\
245	245	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY\
r2864	r2865
248	248	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL\
249	249	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL\
250	250	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL\
251		PORT_START_TAG("IN4")\
	251	PORT_START_TAG("IN2")\
252	252	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 )\
253	253	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON2 )\
254	254	PORT_BIT( 0xfc, IP_ACTIVE_HIGH, IPT_UNUSED )\
255		PORT_START_TAG("IN5")\
	255	PORT_START_TAG("IN3")\
256	256	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL\
257	257	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_COCKTAIL\
258	258	PORT_BIT( 0xfc, IP_ACTIVE_HIGH, IPT_UNUSED )
r2864	r2865
292	292
293	293	/* Same as 'jack', but another different coinage */
294	294	static INPUT_PORTS_START( jack3 )
295		PORT_START /* DSW1 */
	295	PORT_START_TAG("DSW1")
296	296	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coin_B ) )
297	297	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
298	298	PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) )
r2864	r2865
383	383	PORT_DIPSETTING( 0x40, DEF_STR( None ) ) // 3 under 0 pts
384	384	// PORT_DIPSETTING( 0xc0, DEF_STR( None ) ) // 5 under 0 pts
385	385
386		PORT_START_TAG("IN2")
	386	PORT_START_TAG("IN0")
387	387	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
388	388	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
389	389	PORT_BIT( 0x1c, IP_ACTIVE_HIGH, IPT_UNUSED )
390	390	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN1 )
391	391	PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
392	392
393		PORT_START_TAG("IN3")
	393	PORT_START_TAG("IN1")
394	394	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_2WAY
395	395	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_2WAY
396	396	PORT_BIT( 0x0c, IP_ACTIVE_HIGH, IPT_UNUSED )
r2864	r2865
398	398	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_2WAY PORT_COCKTAIL
399	399	PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
400	400
401		PORT_START_TAG("IN4")
	401	PORT_START_TAG("IN2")
402	402	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 )
403	403	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNUSED )
404	404
405		PORT_START_TAG("IN5")
	405	PORT_START_TAG("IN3")
406	406	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL
407	407	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNUSED )
408	408	INPUT_PORTS_END
r2864	r2865
434	434	/* probably unused */
435	435	PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNKNOWN )
436	436
437		PORT_START_TAG("IN2")
	437	PORT_START_TAG("IN0")
438	438	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
439	439	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
440	440	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
444	444	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
445	445	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
446	446
447		PORT_START_TAG("IN3")
	447	PORT_START_TAG("IN1")
448	448	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_2WAY
449	449	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_2WAY
450	450	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
454	454	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
455	455	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
456	456
457		PORT_START_TAG("IN4")
	457	PORT_START_TAG("IN2")
458	458	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON2 )
459	459	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
460	460	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
464	464	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
465	465	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
466	466
467		PORT_START_TAG("IN5")
	467	PORT_START_TAG("IN3")
468	468	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
469	469	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN )
470	470	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
502	502	PORT_START_TAG("DSW2")
503	503	PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED )
504	504
505		PORT_START_TAG("IN2")
	505	PORT_START_TAG("IN0")
506	506	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
507	507	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
508	508	PORT_BIT( 0x3c, IP_ACTIVE_HIGH, IPT_UNUSED )
509	509	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN1 )
510	510	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
511	511
512		PORT_START_TAG("IN3")
	512	PORT_START_TAG("IN1")
513	513	PORT_BIT( 0x03, IP_ACTIVE_HIGH, IPT_UNUSED )
514	514	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_2WAY
515	515	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_2WAY
r2864	r2865
517	517	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_2WAY PORT_COCKTAIL
518	518	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_2WAY PORT_COCKTAIL
519	519
520		PORT_START_TAG("IN4")
	520	PORT_START_TAG("IN2")
521	521	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 )
522	522	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNUSED )
523	523
524		PORT_START_TAG("IN5")
	524	PORT_START_TAG("IN3")
525	525	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL
526	526	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNUSED )
527	527	INPUT_PORTS_END
r2864	r2865
579	579	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
580	580	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
581	581
582		PORT_START_TAG("IN2")
	582	PORT_START_TAG("IN0")
583	583	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
584	584	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
585	585	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME ("Select Game 1")
r2864	r2865
589	589	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN1 )
590	590	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
591	591
592		PORT_START_TAG("IN3")
	592	PORT_START_TAG("IN1")
593	593	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY
594	594	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY
595	595	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY
r2864	r2865
599	599	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
600	600	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
601	601
602		PORT_START_TAG("IN4")
	602	PORT_START_TAG("IN2")
603	603	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 )
604	604	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON2 ) // not needed?
605	605	PORT_BIT( 0xfc, IP_ACTIVE_HIGH, IPT_UNUSED )
606	606
607		PORT_START_TAG("IN5")
	607	PORT_START_TAG("IN3")
608	608	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL
609	609	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_COCKTAIL // not needed?
610	610	PORT_BIT( 0xfc, IP_ACTIVE_HIGH, IPT_UNUSED )
611	611	INPUT_PORTS_END
612	612
613	613	static INPUT_PORTS_START( joinem )
614		PORT_START
	614	PORT_START_TAG("DSW1")
615	615	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coin_A ) )
616	616	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
617	617	PORT_DIPSETTING( 0x03, DEF_STR( 4C_3C ) )
r2864	r2865
635	635	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
636	636	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
637	637
638		PORT_START
	638	PORT_START_TAG("DSW2")
639	639	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Cabinet ) )
640	640	PORT_DIPSETTING( 0x01, DEF_STR( Upright ) )
641	641	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
r2864	r2865
659	659	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
660	660	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
661	661
662		PORT_START
	662	PORT_START_TAG("IN0")
663	663	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY
664	664	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY
665	665	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY
666	666	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY
667	667	PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNKNOWN )
668	668
669		PORT_START
	669	PORT_START_TAG("IN1")
670	670	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
671	671	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
672	672	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
673	673	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
674	674	PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNKNOWN )
675	675
676		PORT_START
	676	PORT_START_TAG("IN2")
677	677	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
678	678	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )
679	679	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START1 )
r2864	r2865
685	685	INPUT_PORTS_END
686	686
687	687	static INPUT_PORTS_START( loverboy )
688		PORT_START
	688	PORT_START_TAG("DSW1")
689	689	PORT_DIPNAME( 0x0f, 0x00, DEF_STR( Coin_A ) )
690	690	PORT_DIPSETTING( 0x0c, DEF_STR( 4C_1C ) )
691	691	PORT_DIPSETTING( 0x08, DEF_STR( 3C_1C ) )
r2864	r2865
716	716	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
717	717	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
718	718
719		PORT_START
	719	PORT_START_TAG("DSW2")
720	720	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ) )
721	721	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
722	722	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
742	742	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
743	743	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
744	744
745		PORT_START
	745	PORT_START_TAG("IN0")
746	746	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY
747	747	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY
748	748	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY
r2864	r2865
752	752	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
753	753	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
754	754
755		PORT_START
	755	PORT_START_TAG("IN1")
756	756	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
757	757	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
758	758	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
r2864	r2865
762	762	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
763	763	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
764	764
765		PORT_START
	765	PORT_START_TAG("IN2")
766	766	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
767	767	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )
768	768	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START1 )
r2864	r2865
804	804	PORT_START_TAG("DSW2")
805	805	PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED ) //?
806	806
807		PORT_START_TAG("IN2")
	807	PORT_START_TAG("IN0")
808	808	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
809	809	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
810	810	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON2 )
r2864	r2865
814	814	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNUSED )
815	815	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
816	816
817		PORT_START_TAG("IN3")
	817	PORT_START_TAG("IN1")
818	818	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
819	819	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2)
820	820	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(2)
r2864	r2865
824	824	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNUSED )
825	825	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
826	826
827		PORT_START_TAG("IN4")
	827	PORT_START_TAG("IN2")
828	828	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(2)
829	829	PORT_BIT( 0xfd, IP_ACTIVE_HIGH, IPT_UNUSED )
830	830
831		PORT_START_TAG("IN5")
	831	PORT_START_TAG("IN3")
832	832	PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED ) //?
833	833	INPUT_PORTS_END
834	834
r2864	r2865
920	920	cpunum_set_input_line(machine, 0, 0, HOLD_LINE);
921	921	else
922	922	{
923		if(!(input_port_read~~_indexed~~(machine, 4) & 0x80))
	923	if(!(input_port_read(machine, "IN2") & 0x80))
924	924	cpunum_set_input_line(machine, 0, INPUT_LINE_NMI, PULSE_LINE);
925	925	}
926	926	}

src/mame/drivers/dietgo.c
r2864	r2865
67	67
68	68
69	69	static INPUT_PORTS_START( dietgo )
70		PORT_START /* Verified as 4 bit input port only */
	70	PORT_START_TAG("IN0") /* Verified as 4 bit input port only */
71	71	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
72	72	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
73	73	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )
74	74	PORT_BIT( 0x0008, IP_ACTIVE_HIGH, IPT_VBLANK )
75	75
76		PORT_START /* 16bit */
	76	PORT_START_TAG("IN1") /* 16bit */
77	77	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
78	78	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
79	79	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
91	91	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
92	92	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 )
93	93
94		PORT_START /* Dip switch bank 1 */
	94	PORT_START_TAG("DSW") /* Dip switch bank 1 */
95	95	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )
96	96	PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
97	97	PORT_DIPSETTING( 0x0001, DEF_STR( 2C_1C ) )

src/mame/drivers/ettrivia.c
r2864	r2865
132	132	ADDRESS_MAP_END
133	133
134	134	INPUT_PORTS_START( ettrivia )
135		PORT_START
	135	PORT_START_TAG("IN0")
136	136	PORT_SERVICE( 0x01, IP_ACTIVE_LOW )
137	137	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
138	138	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
142	142	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 )
143	143	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 )
144	144
145		PORT_START
	145	PORT_START_TAG("IN1")
146	146	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
147	147	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
148	148	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
152	152	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
153	153	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
154	154
155		PORT_START
	155	PORT_START_TAG("COIN")
156	156	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
157	157	INPUT_PORTS_END
158	158
r2864	r2865
230	230
231	231	static INTERRUPT_GEN( ettrivia_interrupt )
232	232	{
233		if( input_port_read~~_indexed~~(machine, 2) & 0x01 )
	233	if( input_port_read(machine, "COIN") & 0x01 )
234	234	cpunum_set_input_line(machine, 0, INPUT_LINE_NMI, PULSE_LINE);
235	235	else
236	236	cpunum_set_input_line(machine, 0, 0, HOLD_LINE);

src/mame/drivers/jalmah.c
r2864	r2865
194	194	tilemap_set_transparent_pen(sc3_tilemap,15);
195	195	}
196	196
197		#define MCU_READ(_number_,_bit_,_offset_,_retval_)\
198		if((0xffff - input_port_read_indexed(machine, _number_)) & _bit_) { jm_regs[_offset_] = _retval_; }
	197	#define MCU_READ(tag, _bit_, _offset_, _retval_) \
	198	if((0xffff - input_port_read(machine, tag)) & _bit_) { jm_regs[_offset_] = _retval_; }
199	199
200	200	/RAM-based protection handlings/
201	201	static void daireika_mcu_run(running_machine *machine)
202	202	{
203	203	static UINT16 prg_prot;
204	204
205		if((0xffff - input_port_read~~_indexed~~(machine,0)) & 0x0008)//service_mode
	205	if((0xffff - input_port_read(machine, "SYSTEM")) & 0x0008) //service_mode
206	206	{
207		jm_regs[0x000/2] = input_port_read_indexed(machine,2);
208		jm_regs[0x002/2] = input_port_read_indexed(machine,3);
209		jm_regs[0x004/2] = input_port_read_indexed(machine,4);
210		jm_regs[0x006/2] = input_port_read_indexed(machine,5);
211		jm_regs[0x008/2] = input_port_read_indexed(machine,6);
212		jm_regs[0x00a/2] = input_port_read_indexed(machine,7);
	207	jm_regs[0x000/2] = input_port_read(machine, "KEY0");
	208	jm_regs[0x002/2] = input_port_read(machine, "KEY1");
	209	jm_regs[0x004/2] = input_port_read(machine, "KEY2");
	210	jm_regs[0x006/2] = input_port_read(machine, "KEY3");
	211	jm_regs[0x008/2] = input_port_read(machine, "KEY4");
	212	jm_regs[0x00a/2] = input_port_read(machine, "KEY5");
213	213	}
214	214	else
215	215	{
216	216	jm_regs[0x000/2] = 0x0000;
217		MCU_READ(3,0x0001,0x000/2,0x00);/FF/
218		MCU_READ(4,0x0400,0x000/2,0x01);/A/
219		MCU_READ(4,0x1000,0x000/2,0x02);/B/
220		MCU_READ(4,0x0200,0x000/2,0x03);/C/
221		MCU_READ(4,0x0800,0x000/2,0x04);/D/
222		MCU_READ(4,0x0004,0x000/2,0x05);/E/
223		MCU_READ(4,0x0010,0x000/2,0x06);/F/
224		MCU_READ(4,0x0002,0x000/2,0x07);/G/
225		MCU_READ(4,0x0008,0x000/2,0x08);/H/
226		MCU_READ(3,0x0400,0x000/2,0x09);/I/
227		MCU_READ(3,0x1000,0x000/2,0x0a);/J/
228		MCU_READ(3,0x0200,0x000/2,0x0b);/K/
229		MCU_READ(3,0x0800,0x000/2,0x0c);/L/
230		MCU_READ(3,0x0004,0x000/2,0x0d);/M/
231		MCU_READ(3,0x0010,0x000/2,0x0e);/N/
232		MCU_READ(2,0x0200,0x000/2,0x0f);/RON (trusted)/
233		MCU_READ(2,0x1000,0x000/2,0x10);/REACH (trusted)/
234		MCU_READ(2,0x0400,0x000/2,0x11);/KAN /
235		MCU_READ(3,0x0008,0x000/2,0x12);/PON /
236		MCU_READ(3,0x0002,0x000/2,0x13);/CHI (trusted)/
237		MCU_READ(2,0x0004,0x000/2,0x14);/START1/
	217	MCU_READ("KEY1", 0x0001, 0x000/2, 0x00); /FF/
	218	MCU_READ("KEY2", 0x0400, 0x000/2, 0x01); /A/
	219	MCU_READ("KEY2", 0x1000, 0x000/2, 0x02); /B/
	220	MCU_READ("KEY2", 0x0200, 0x000/2, 0x03); /C/
	221	MCU_READ("KEY2", 0x0800, 0x000/2, 0x04); /D/
	222	MCU_READ("KEY2", 0x0004, 0x000/2, 0x05); /E/
	223	MCU_READ("KEY2", 0x0010, 0x000/2, 0x06); /F/
	224	MCU_READ("KEY2", 0x0002, 0x000/2, 0x07); /G/
	225	MCU_READ("KEY2", 0x0008, 0x000/2, 0x08); /H/
	226	MCU_READ("KEY1", 0x0400, 0x000/2, 0x09); /I/
	227	MCU_READ("KEY1", 0x1000, 0x000/2, 0x0a); /J/
	228	MCU_READ("KEY1", 0x0200, 0x000/2, 0x0b); /K/
	229	MCU_READ("KEY1", 0x0800, 0x000/2, 0x0c); /L/
	230	MCU_READ("KEY1", 0x0004, 0x000/2, 0x0d); /M/
	231	MCU_READ("KEY1", 0x0010, 0x000/2, 0x0e); /N/
	232	MCU_READ("KEY0", 0x0200, 0x000/2, 0x0f); /RON (trusted)/
	233	MCU_READ("KEY0", 0x1000, 0x000/2, 0x10); /REACH (trusted)/
	234	MCU_READ("KEY0", 0x0400, 0x000/2, 0x11); /KAN /
	235	MCU_READ("KEY1", 0x0008, 0x000/2, 0x12); /PON /
	236	MCU_READ("KEY1", 0x0002, 0x000/2, 0x13); /CHI (trusted)/
	237	MCU_READ("KEY0", 0x0004, 0x000/2, 0x14); /START1/
238	238	}
239	239	jm_regs[0x00c/2] = mame_rand(machine) & 0xffff;
240	240	prg_prot++;
r2864	r2865
247	247	{
248	248	static UINT16 prg_prot;
249	249
250		if((0xffff - input_port_read~~_indexed~~(machine,0)) & 0x0008)//service_mode
	250	if((0xffff - input_port_read(machine, "SYSTEM")) & 0x0008) //service_mode
251	251	{
252		jm_regs[0x300/2] = input_port_read_indexed(machine,2);
253		jm_regs[0x302/2] = input_port_read_indexed(machine,3);
254		jm_regs[0x304/2] = input_port_read_indexed(machine,4);
255		jm_regs[0x306/2] = input_port_read_indexed(machine,5);
256		jm_regs[0x308/2] = input_port_read_indexed(machine,6);
257		jm_regs[0x30a/2] = input_port_read_indexed(machine,7);
	252	jm_regs[0x300/2] = input_port_read(machine, "KEY0");
	253	jm_regs[0x302/2] = input_port_read(machine, "KEY1");
	254	jm_regs[0x304/2] = input_port_read(machine, "KEY2");
	255	jm_regs[0x306/2] = input_port_read(machine, "KEY3");
	256	jm_regs[0x308/2] = input_port_read(machine, "KEY4");
	257	jm_regs[0x30a/2] = input_port_read(machine, "KEY5");
258	258	}
259	259	else
260	260	{
261	261	jm_regs[0x300/2] = 0x0000;
262		MCU_READ(3,0x0001,0x300/2,0x00);/FF/
263		MCU_READ(4,0x0400,0x300/2,0x01);/A/
264		MCU_READ(4,0x1000,0x300/2,0x02);/B/
265		MCU_READ(4,0x0200,0x300/2,0x03);/C/
266		MCU_READ(4,0x0800,0x300/2,0x04);/D/
267		MCU_READ(4,0x0004,0x300/2,0x05);/E/
268		MCU_READ(4,0x0010,0x300/2,0x06);/F/
269		MCU_READ(4,0x0002,0x300/2,0x07);/G/
270		MCU_READ(4,0x0008,0x300/2,0x08);/H/
271		MCU_READ(3,0x0400,0x300/2,0x09);/I/
272		MCU_READ(3,0x1000,0x300/2,0x0a);/J/
273		MCU_READ(3,0x0200,0x300/2,0x0b);/K/
274		MCU_READ(3,0x0800,0x300/2,0x0c);/L/
275		MCU_READ(3,0x0004,0x300/2,0x0d);/M/
276		MCU_READ(3,0x0010,0x300/2,0x0e);/N/
277		MCU_READ(2,0x0200,0x300/2,0x0f);/RON (trusted)/
278		MCU_READ(2,0x1000,0x300/2,0x10);/REACH (trusted)/
279		MCU_READ(2,0x0400,0x300/2,0x11);/KAN /
280		MCU_READ(3,0x0008,0x300/2,0x12);/PON /
281		MCU_READ(3,0x0002,0x300/2,0x13);/CHI (trusted)/
282		MCU_READ(2,0x0004,0x300/2,0x14);/START1/
	262	MCU_READ("KEY1", 0x0001, 0x300/2, 0x00); /FF/
	263	MCU_READ("KEY2", 0x0400, 0x300/2, 0x01); /A/
	264	MCU_READ("KEY2", 0x1000, 0x300/2, 0x02); /B/
	265	MCU_READ("KEY2", 0x0200, 0x300/2, 0x03); /C/
	266	MCU_READ("KEY2", 0x0800, 0x300/2, 0x04); /D/
	267	MCU_READ("KEY2", 0x0004, 0x300/2, 0x05); /E/
	268	MCU_READ("KEY2", 0x0010, 0x300/2, 0x06); /F/
	269	MCU_READ("KEY2", 0x0002, 0x300/2, 0x07); /G/
	270	MCU_READ("KEY2", 0x0008, 0x300/2, 0x08); /H/
	271	MCU_READ("KEY1", 0x0400, 0x300/2, 0x09); /I/
	272	MCU_READ("KEY1", 0x1000, 0x300/2, 0x0a); /J/
	273	MCU_READ("KEY1", 0x0200, 0x300/2, 0x0b); /K/
	274	MCU_READ("KEY1", 0x0800, 0x300/2, 0x0c); /L/
	275	MCU_READ("KEY1", 0x0004, 0x300/2, 0x0d); /M/
	276	MCU_READ("KEY1", 0x0010, 0x300/2, 0x0e); /N/
	277	MCU_READ("KEY0", 0x0200, 0x300/2, 0x0f); /RON (trusted)/
	278	MCU_READ("KEY0", 0x1000, 0x300/2, 0x10); /REACH (trusted)/
	279	MCU_READ("KEY0", 0x0400, 0x300/2, 0x11); /KAN /
	280	MCU_READ("KEY1", 0x0008, 0x300/2, 0x12); /PON /
	281	MCU_READ("KEY1", 0x0002, 0x300/2, 0x13); /CHI (trusted)/
	282	MCU_READ("KEY0", 0x0004, 0x300/2, 0x14); /START1/
283	283	}
284	284	jm_regs[0x30c/2] = mame_rand(machine) & 0xffff;
285	285	prg_prot++;
r2864	r2865
289	289
290	290	static void second_mcu_run(running_machine *machine)
291	291	{
292		if((0xffff - input_port_read~~_indexed~~(machine,1)) & 0x0004)//service_mode
	292	if((0xffff - input_port_read(machine, "DSW")) & 0x0004) //service_mode
293	293	{
294		jm_regs[0x200/2] = input_port_read_indexed(machine,2);
295		jm_regs[0x202/2] = input_port_read_indexed(machine,3);
296		jm_regs[0x204/2] = input_port_read_indexed(machine,4);
	294	jm_regs[0x200/2] = input_port_read(machine, "KEY0");
	295	jm_regs[0x202/2] = input_port_read(machine, "KEY1");
	296	jm_regs[0x204/2] = input_port_read(machine, "KEY2");
297	297	}
298	298	else
299	299	{
300	300	jm_regs[0x200/2] = 0x0000;
301		MCU_READ(3,0x0001,0x200/2,0x00);/FF/
302		MCU_READ(4,0x0400,0x200/2,0x01);/A/
303		MCU_READ(4,0x1000,0x200/2,0x02);/B/
304		MCU_READ(4,0x0200,0x200/2,0x03);/C/
305		MCU_READ(4,0x0800,0x200/2,0x04);/D/
306		MCU_READ(4,0x0004,0x200/2,0x05);/E/
307		MCU_READ(4,0x0010,0x200/2,0x06);/F/
308		MCU_READ(4,0x0002,0x200/2,0x07);/G/
309		MCU_READ(4,0x0008,0x200/2,0x08);/H/
310		MCU_READ(3,0x0400,0x200/2,0x09);/I/
311		MCU_READ(3,0x1000,0x200/2,0x0a);/J/
312		MCU_READ(3,0x0200,0x200/2,0x0b);/K/
313		MCU_READ(3,0x0800,0x200/2,0x0c);/L/
314		MCU_READ(3,0x0004,0x200/2,0x0d);/M/
315		MCU_READ(3,0x0010,0x200/2,0x0e);/N/
316		MCU_READ(2,0x0200,0x200/2,0x0f);/RON/
317		MCU_READ(2,0x1000,0x200/2,0x10);/REACH/
318		MCU_READ(2,0x0400,0x200/2,0x11);/KAN/
319		MCU_READ(3,0x0008,0x200/2,0x12);/PON/
320		MCU_READ(3,0x0002,0x200/2,0x13);/CHI/
321		MCU_READ(2,0x0004,0x200/2,0x14);/START1/
	301	MCU_READ("KEY1", 0x0001, 0x200/2, 0x00); /FF/
	302	MCU_READ("KEY2", 0x0400, 0x200/2, 0x01); /A/
	303	MCU_READ("KEY2", 0x1000, 0x200/2, 0x02); /B/
	304	MCU_READ("KEY2", 0x0200, 0x200/2, 0x03); /C/
	305	MCU_READ("KEY2", 0x0800, 0x200/2, 0x04); /D/
	306	MCU_READ("KEY2", 0x0004, 0x200/2, 0x05); /E/
	307	MCU_READ("KEY2", 0x0010, 0x200/2, 0x06); /F/
	308	MCU_READ("KEY2", 0x0002, 0x200/2, 0x07); /G/
	309	MCU_READ("KEY2", 0x0008, 0x200/2, 0x08); /H/
	310	MCU_READ("KEY1", 0x0400, 0x200/2, 0x09); /I/
	311	MCU_READ("KEY1", 0x1000, 0x200/2, 0x0a); /J/
	312	MCU_READ("KEY1", 0x0200, 0x200/2, 0x0b); /K/
	313	MCU_READ("KEY1", 0x0800, 0x200/2, 0x0c); /L/
	314	MCU_READ("KEY1", 0x0004, 0x200/2, 0x0d); /M/
	315	MCU_READ("KEY1", 0x0010, 0x200/2, 0x0e); /N/
	316	MCU_READ("KEY0", 0x0200, 0x200/2, 0x0f); /RON/
	317	MCU_READ("KEY0", 0x1000, 0x200/2, 0x10); /REACH/
	318	MCU_READ("KEY0", 0x0400, 0x200/2, 0x11); /KAN/
	319	MCU_READ("KEY1", 0x0008, 0x200/2, 0x12); /PON/
	320	MCU_READ("KEY1", 0x0002, 0x200/2, 0x13); /CHI/
	321	MCU_READ("KEY0", 0x0004, 0x200/2, 0x14); /START1/
322	322
323		// MCU_READ(2,0x0004,0x7b8/2,0x03);/START1(correct?) /
	323	// MCU_READ("KEY0", 0x0004, 0x7b8/2, 0x03); /START1(correct?) /
324	324	}
325	325	jm_regs[0x20c/2] = mame_rand(machine) & 0xffff; //kakumei2
326	326
r2864	r2865
548	548	ADDRESS_MAP_END
549	549
550	550
551
552
553		static INPUT_PORTS_START( jalmah )
	551	static INPUT_PORTS_START( common )
554	552	/System port/
555		PORT_START
	553	PORT_START_TAG("SYSTEM")
556	554	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
557	555	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
558	556	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
562	560	PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
563	561	PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
564	562	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
565		PORT_SERVICE( 0x0008, IP_ACTIVE_LOW )
	563	PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
	564	PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
	565	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
566	566	PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
567	567	PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
568	568	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
595	595	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
596	596
597	597	/Dip-SW port/
598		PORT_START
	598	PORT_START_TAG("DSW")
599	599	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) ) // Coin2 is always 1C/1C.
600	600	PORT_DIPSETTING( 0x0001, DEF_STR( 4C_1C ) )
601	601	PORT_DIPSETTING( 0x0002, DEF_STR( 3C_1C ) )
r2864	r2865
646	646	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
647	647
648	648	/Mahjong Panel ports/
649		PORT_START
	649	PORT_START_TAG("KEY0")
650	650	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_START1 )
651	651	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
652	652	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
653	653	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
654	654	PORT_BIT( 0xe9fb, IP_ACTIVE_LOW, IPT_UNUSED )
655	655
656		PORT_START
	656	PORT_START_TAG("KEY1")
657	657	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
658	658	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
659	659	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_M )
r2864	r2865
665	665	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_J )
666	666	PORT_BIT( 0xe1e0, IP_ACTIVE_LOW, IPT_UNUSED )
667	667
668		PORT_START
	668	PORT_START_TAG("KEY2")
669	669	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_G )
670	670	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_E )
671	671	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_H )
r2864	r2865
675	675	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_MAHJONG_D )
676	676	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_B )
677	677	PORT_BIT( 0xe1e1, IP_ACTIVE_LOW, IPT_UNUSED )
	678	INPUT_PORTS_END
678	679
679		PORT_START
	680	static INPUT_PORTS_START( jalmah )
	681	PORT_INCLUDE( common )
	682
	683	PORT_MODIFY("SYSTEM")
	684	PORT_SERVICE( 0x0008, IP_ACTIVE_LOW )
	685
	686	PORT_START_TAG("KEY3")
680	687	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_START2 )
681	688	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
682	689	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
683	690	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )PORT_PLAYER(2)
684	691	PORT_BIT( 0xe9fb, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_PLAYER(2)
685	692
686		PORT_START
	693	PORT_START_TAG("KEY4")
687	694	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(2)
688	695	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(2)
689	696	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(2)
r2864	r2865
695	702	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
696	703	PORT_BIT( 0xe1e0, IP_ACTIVE_LOW, IPT_UNUSED )
697	704
698		PORT_START
	705	PORT_START_TAG("KEY5")
699	706	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_G )PORT_PLAYER(2)
700	707	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_E )PORT_PLAYER(2)
701	708	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_H )PORT_PLAYER(2)
r2864	r2865
709	716
710	717
711	718	static INPUT_PORTS_START( jalmah2 )
712		/System port/
713		PORT_START
714		PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
715		PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
716		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
717		PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
718		PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
719		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
720		PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
721		PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
722		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
723		PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
724		PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
725		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
726		PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
727		PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
728		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
729		PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_SERVICE1 )
730		PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN1 )
731		PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN2 )
732		PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) )
733		PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
734		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
735		PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
736		PORT_DIPSETTING( 0x0200, DEF_STR( Off ) )
737		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
738		PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
739		PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
740		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
741		PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
742		PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
743		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
744		PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
745		PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
746		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
747		PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
748		PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
749		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
750		PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
751		PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
752		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
753		PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
754		PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
755		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	719	PORT_INCLUDE( common )
756	720
757		/Dip-SW port/
758		PORT_START
	721	PORT_MODIFY("DSW")
759	722	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) )
760	723	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
761	724	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
763	726	PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
764	727	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
765	728	PORT_SERVICE( 0x0004, IP_ACTIVE_LOW )
766		PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
767		PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
768		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
769		PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
770		PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
771		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
772		PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
773		PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
774		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
775		PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
776		PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
777		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
778	729	PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
779	730	PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
780	731	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
787	738	PORT_DIPSETTING( 0x0500, DEF_STR( 1C_3C ) )
788	739	PORT_DIPSETTING( 0x0400, DEF_STR( 1C_4C ) )
789	740	PORT_DIPSETTING( 0x0000, "1 Coin / 99 Credits" )
790		PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
791		PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
792		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
793		PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
794		PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
795		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
796		PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
797		PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
798		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
799		PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
800		PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
801		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
802		PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
803		PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
804		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
805	741
806		/Mahjong Panel ports/
807		PORT_START
808		PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_START1 )
809		PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
810		PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
811		PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
812		PORT_BIT( 0xe9fb, IP_ACTIVE_LOW, IPT_UNUSED )
813
814		PORT_START
	742	PORT_MODIFY("KEY1")
815	743	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_NAME("P1 Mahjong Flip Flop?") PORT_CODE(KEYCODE_2) //? seems a button,affects continue countdown
816		PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
817		PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_M )
818		PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
819		PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_N )
820		PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_MAHJONG_K )
821		PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_MAHJONG_I )
822		PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_MAHJONG_L )
823		PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_J )
824		PORT_BIT( 0xe1e0, IP_ACTIVE_LOW, IPT_UNUSED )
825
826		PORT_START
827		PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_G )
828		PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_E )
829		PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_H )
830		PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_F )
831		PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_MAHJONG_C )
832		PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_MAHJONG_A )
833		PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_MAHJONG_D )
834		PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_B )
835		PORT_BIT( 0xe1e1, IP_ACTIVE_LOW, IPT_UNUSED )
836	744	INPUT_PORTS_END
837	745
838	746
839	747	static INPUT_PORTS_START( jalmah2a )
840		/System port/
841		PORT_START
842		PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
843		PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
844		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
845		PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
846		PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
847		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
848		PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
849		PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
850		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
851		PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
852		PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
853		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
854		PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
855		PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
856		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
857		PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_SERVICE1 )
858		PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_COIN1 )
859		PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_COIN2 )
860		PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) )
861		PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
862		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
863		PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
864		PORT_DIPSETTING( 0x0200, DEF_STR( Off ) )
865		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
866		PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
867		PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
868		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
869		PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
870		PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
871		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
872		PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
873		PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
874		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
875		PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
876		PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
877		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
878		PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
879		PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
880		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
881		PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
882		PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
883		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	748	PORT_INCLUDE( common )
884	749
885		/Dip-SW port/
886		PORT_START
	750	PORT_MODIFY("DSW")
887	751	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
888	752	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
889	753	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
891	755	PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
892	756	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
893	757	PORT_SERVICE( 0x0004, IP_ACTIVE_LOW )
894		PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
895		PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
896		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
897	758	PORT_DIPNAME( 0x0010, 0x0000, DEF_STR( Demo_Sounds ) )
898	759	PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
899	760	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
900		PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
901		PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
902		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
903		PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
904		PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
905		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
906	761	PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
907	762	PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
908	763	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
915	770	PORT_DIPSETTING( 0x0500, DEF_STR( 1C_3C ) )
916	771	PORT_DIPSETTING( 0x0400, DEF_STR( 1C_4C ) )
917	772	PORT_DIPSETTING( 0x0000, "1 Coin / 99 Credits" )
918		PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
919		PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
920		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
921		PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
922		PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
923		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
924		PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
925		PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
926		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
927		PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
928		PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
929		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
930	773	PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Flip_Screen ) )
931	774	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
932	775	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
933	776
934		/Mahjong Panel ports/
935		PORT_START
936		PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_START1 )
937		PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
938		PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
939		PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
940		PORT_BIT( 0xe9fb, IP_ACTIVE_LOW, IPT_UNUSED )
941
942		PORT_START
	777	PORT_MODIFY("KEY1")
943	778	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_NAME("P1 Mahjong Flip Flop?") PORT_CODE(KEYCODE_2) //? seems a button,affects continue countdown
944		PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
945		PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_M )
946		PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
947		PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_N )
948		PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_MAHJONG_K )
949		PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_MAHJONG_I )
950		PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_MAHJONG_L )
951		PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_J )
952		PORT_BIT( 0xe1e0, IP_ACTIVE_LOW, IPT_UNUSED )
953
954		PORT_START
955		PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_G )
956		PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_E )
957		PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_H )
958		PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_F )
959		PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_MAHJONG_C )
960		PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_MAHJONG_A )
961		PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_MAHJONG_D )
962		PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_MAHJONG_B )
963		PORT_BIT( 0xe1e1, IP_ACTIVE_LOW, IPT_UNUSED )
964	779	INPUT_PORTS_END
965	780
966	781	static const gfx_layout charlayout =

src/mame/drivers/lvcards.c
r2864	r2865
136	136
137	137	static READ8_HANDLER( payout_r )
138	138	{
139		result = input_port_read~~_indexed~~(machine, 2);
	139	result = input_port_read(machine, "IN2");
140	140
141	141	if (payout)
142	142	{
r2864	r2865
158	158	AM_RANGE(0x6000, 0x67ff) AM_RAM AM_BASE(&generic_nvram) AM_SIZE(&generic_nvram_size)
159	159	AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE(lvcards_videoram_w) AM_BASE(&videoram)
160	160	AM_RANGE(0x8400, 0x87ff) AM_RAM_WRITE(lvcards_colorram_w) AM_BASE(&colorram)
161		AM_RANGE(0xa000, 0xa000) AM_READ(input_port_0_r)
162		AM_RANGE(0xa001, 0xa001) AM_READ(input_port_1_r) AM_WRITENOP // lamps
	161	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("IN0")
	162	AM_RANGE(0xa001, 0xa001) AM_READ_PORT("IN1") AM_WRITENOP // lamps
163	163	AM_RANGE(0xa002, 0xa002) AM_READ(payout_r) AM_WRITE(control_port_2a_w)//AM_WRITENOP // ???
164	164	ADDRESS_MAP_END
165	165
r2864	r2865
168	168	AM_RANGE(0x6000, 0x67ff) AM_RAM AM_BASE(&generic_nvram) AM_SIZE(&generic_nvram_size)
169	169	AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(lvcards_videoram_w) AM_BASE(&videoram)
170	170	AM_RANGE(0x9400, 0x97ff) AM_RAM_WRITE(lvcards_colorram_w) AM_BASE(&colorram)
171		AM_RANGE(0xa000, 0xa000) AM_READ(input_port_0_r)
172		AM_RANGE(0xa001, 0xa001) AM_READ(input_port_1_r) AM_WRITENOP
173		AM_RANGE(0xa002, 0xa002) AM_READ(input_port_2_r) AM_WRITENOP
	171	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("IN0")
	172	AM_RANGE(0xa001, 0xa001) AM_READ_PORT("IN1") AM_WRITENOP
	173	AM_RANGE(0xa002, 0xa002) AM_READ_PORT("IN2") AM_WRITENOP
174	174	AM_RANGE(0xc000, 0xdfff) AM_ROM
175	175	ADDRESS_MAP_END
176	176
r2864	r2865
185	185	AM_RANGE(0x6000, 0x67ff) AM_RAM AM_BASE(&generic_nvram) AM_SIZE(&generic_nvram_size)
186	186	AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(lvcards_videoram_w) AM_BASE(&videoram)
187	187	AM_RANGE(0x9400, 0x97ff) AM_RAM_WRITE(lvcards_colorram_w) AM_BASE(&colorram)
188		AM_RANGE(0xa000, 0xa000) AM_READ(input_port_0_r)
189		AM_RANGE(0xa001, 0xa001) AM_READ(input_port_1_r) AM_WRITENOP // lamps
	188	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("IN0")
	189	AM_RANGE(0xa001, 0xa001) AM_READ_PORT("IN1") AM_WRITENOP // lamps
190	190	AM_RANGE(0xa002, 0xa002) AM_READ(payout_r) AM_WRITE(control_port_2_w)
191	191	AM_RANGE(0xc000, 0xdfff) AM_ROM
192	192	ADDRESS_MAP_END

src/mame/drivers/tecmosys.c
r2864	r2865
188	188	#include "sound/okim6295.h"
189	189	#include "sound/262intf.h"
190	190	#include "sound/ymz280b.h"
191		#include "deprecat.h"
192	191
193	192	static UINT16* tecmosys_spriteram;
194	193	static UINT16* tilemap_paletteram16;
r2864	r2865
399	398	}
400	399
401	400
402		INLINE void set_color_555(pen_t color, int rshift, int gshift, int bshift, UINT16 data)
	401	INLINE void set_color_555(running_machine *machine, pen_t color, int rshift, int gshift, int bshift, UINT16 data)
403	402	{
404		palette_set_color_rgb(Machine, color, pal5bit(data >> rshift), pal5bit(data >> gshift), pal5bit(data >> bshift));
	403	palette_set_color_rgb(machine, color, pal5bit(data >> rshift), pal5bit(data >> gshift), pal5bit(data >> bshift));
405	404	}
406	405
407	406
408	407	static WRITE16_HANDLER( tilemap_paletteram16_xGGGGGRRRRRBBBBB_word_w )
409	408	{
410	409	COMBINE_DATA(&tilemap_paletteram16[offset]);
411		set_color_555(offset+0x4000, 5, 10, 0, tilemap_paletteram16[offset]);
	410	set_color_555(machine, offset+0x4000, 5, 10, 0, tilemap_paletteram16[offset]);
412	411	}
413	412
414	413	static WRITE16_HANDLER( bg0_tilemap_lineram_w )
r2864	r2865
731	730	}
732	731	}
733	732
734		static void tecmosys_do_final_mix(bitmap_t* bitmap)
	733	static void tecmosys_do_final_mix(running_machine machine, bitmap_t bitmap)
735	734	{
736		const pen_t *paldata = Machine->pens;
	735	const pen_t *paldata = machine->pens;
737	736	int y,x;
738	737	UINT16 *srcptr;
739	738	UINT16 *srcptr2;
r2864	r2865
806	805	static VIDEO_UPDATE(deroon)
807	806	{
808	807
809		fillbitmap(bitmap,Machine->pens[0x4000],cliprect);
	808	fillbitmap(bitmap,screen->machine->pens[0x4000],cliprect);
810	809
811	810
812	811	tilemap_set_scrolly( bg0tilemap, 0, tecmosys_c80000regs[1]+16);
r2864	r2865
837	836	tecmosys_tilemap_copy_to_compose(0xc000);
838	837
839	838
840		tecmosys_do_final_mix(bitmap);
	839	tecmosys_do_final_mix(screen->machine, bitmap);
841	840
842	841	/*
843	842	popmessage("%04x %04x %04x %04x \| %04x %04x %04x %04x \| %04x %04x %04x %04x \| %04x %04x %04x %04x \| %04x %04x %04x %04x \| %04x %04x %04x %04x",
r2864	r2865
936	935	MDRV_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK)
937	936
938	937	MDRV_SCREEN_ADD("main", RASTER)
939		MDRV_SCREEN_REFRESH_RATE(60)
	938	MDRV_SCREEN_REFRESH_RATE(57.4458)
940	939	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(3000))
941	940	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
942	941	MDRV_SCREEN_SIZE(648, 648)

src/mame/drivers/exidy440.c
r2864	r2865
344	344	{
345	345	/* I/O1 accesses clear the CIRQ flip/flop */
346	346	cpunum_set_input_line(machine, 0, 0, CLEAR_LINE);
347		return input_port_read~~_indexed~~(machine, 3);
	347	return input_port_read(machine, "IN3");
348	348	}
349	349
350	350
r2864	r2865
435	435
436	436	static READ8_HANDLER( topsecex_input_port_5_r )
437	437	{
438		return (input_port_read~~_indexed~~(machine, 5) & 1) ? 0x01 : 0x02;
	438	return (input_port_read(machine, "AN1") & 1) ? 0x01 : 0x02;
439	439	}
440	440
441	441
r2864	r2865
517	517
518	518
519	519	static INPUT_PORTS_START( crossbow )
520		PORT_START /* player inputs and logic board dips */
	520	PORT_START_TAG("IN0") /* player inputs and logic board dips */
521	521	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
522	522	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 )
523	523	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Lives ) )
r2864	r2865
533	533	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
534	534	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
535	535
536		PORT_START /* audio board dips */
	536	PORT_START_TAG("IN1") /* audio board dips */
537	537	COINAGE
538	538	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNKNOWN )
539	539	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Free_Play ) )
540	540	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
541	541	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
542	542
543		PORT_START /* start button */
	543	PORT_START_TAG("IN2") /* start button */
544	544	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
545	545	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN )
546	546
547		PORT_START /* coin counters */
	547	PORT_START_TAG("IN3") /* coin counters */
548	548	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
549	549	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
550	550	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNKNOWN )
551	551
552		PORT_START /* fake analog X */
	552	PORT_START_TAG("AN0") /* fake analog X */
553	553	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
554	554
555		PORT_START /* fake analog Y */
	555	PORT_START_TAG("AN1") /* fake analog Y */
556	556	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
557	557	INPUT_PORTS_END
558	558
559	559
560	560	static INPUT_PORTS_START( cheyenne )
561		PORT_START /* player inputs and logic board dips */
	561	PORT_START_TAG("IN0") /* player inputs and logic board dips */
562	562	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
563	563	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
564	564	PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Lives ) )
r2864	r2865
574	574	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
575	575	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
576	576
577		PORT_START /* audio board dips */
	577	PORT_START_TAG("IN1") /* audio board dips */
578	578	COINAGE
579	579	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNKNOWN )
580	580	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Free_Play ) )
581	581	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
582	582	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
583	583
584		PORT_START /* start button */
	584	PORT_START_TAG("IN2") /* start button */
585	585	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
586	586	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN )
587	587
588		PORT_START /* coin counters */
	588	PORT_START_TAG("IN3") /* coin counters */
589	589	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
590	590	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
591	591	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNKNOWN )
592	592
593		PORT_START /* fake analog X */
	593	PORT_START_TAG("AN0") /* fake analog X */
594	594	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
595	595
596		PORT_START /* fake analog Y */
	596	PORT_START_TAG("AN1") /* fake analog Y */
597	597	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
598	598	INPUT_PORTS_END
599	599
600	600
601	601	static INPUT_PORTS_START( combat )
602		PORT_START /* player inputs and logic board dips */
	602	PORT_START_TAG("IN0") /* player inputs and logic board dips */
603	603	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
604	604	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
605	605	PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Lives ) )
r2864	r2865
615	615	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
616	616	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
617	617
618		PORT_START /* audio board dips */
	618	PORT_START_TAG("IN1") /* audio board dips */
619	619	COINAGE
620	620	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNKNOWN )
621	621	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Free_Play ) )
622	622	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
623	623	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
624	624
625		PORT_START /* start button */
	625	PORT_START_TAG("IN2") /* start button */
626	626	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
627	627	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNKNOWN )
628	628
629		PORT_START /* coin counters */
	629	PORT_START_TAG("IN3") /* coin counters */
630	630	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
631	631	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
632	632	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNKNOWN )
633	633
634		PORT_START /* fake analog X */
	634	PORT_START_TAG("AN0") /* fake analog X */
635	635	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
636	636
637		PORT_START /* fake analog Y */
	637	PORT_START_TAG("AN1") /* fake analog Y */
638	638	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
639	639	INPUT_PORTS_END
640	640
641	641
642	642	static INPUT_PORTS_START( catch22 )
643		PORT_START /* player inputs and logic board dips */
	643	PORT_START_TAG("IN0") /* player inputs and logic board dips */
644	644	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
645	645	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
646	646	PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Lives ) )
r2864	r2865
656	656	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
657	657	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
658	658
659		PORT_START /* audio board dips */
	659	PORT_START_TAG("IN1") /* audio board dips */
660	660	COINAGE
661	661	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNKNOWN )
662	662	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Free_Play ) )
663	663	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
664	664	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
665	665
666		PORT_START /* start button */
	666	PORT_START_TAG("IN2") /* start button */
667	667	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
668	668	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNKNOWN )
669	669
670		PORT_START /* coin counters */
	670	PORT_START_TAG("IN3") /* coin counters */
671	671	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
672	672	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
673	673	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
674	674	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
675	675
676		PORT_START /* fake analog X */
	676	PORT_START_TAG("AN0") /* fake analog X */
677	677	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
678	678
679		PORT_START /* fake analog Y */
	679	PORT_START_TAG("AN1") /* fake analog Y */
680	680	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
681	681	INPUT_PORTS_END
682	682
683	683
684	684	static INPUT_PORTS_START( cracksht )
685		PORT_START /* player inputs and logic board dips */
	685	PORT_START_TAG("IN0") /* player inputs and logic board dips */
686	686	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
687	687	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
688	688	PORT_DIPNAME( 0x0c, 0x00, "Seconds" )
r2864	r2865
698	698	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
699	699	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
700	700
701		PORT_START /* audio board dips */
	701	PORT_START_TAG("IN1") /* audio board dips */
702	702	COINAGE
703	703	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNKNOWN )
704	704	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
705	705	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
706	706	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
707	707
708		PORT_START /* start button */
	708	PORT_START_TAG("IN2") /* start button */
709	709	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
710	710	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNKNOWN )
711	711
712		PORT_START /* coin counters */
	712	PORT_START_TAG("IN3") /* coin counters */
713	713	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
714	714	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
715	715	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
716	716	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
717	717
718		PORT_START /* fake analog X */
	718	PORT_START_TAG("AN0") /* fake analog X */
719	719	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
720	720
721		PORT_START /* fake analog Y */
	721	PORT_START_TAG("AN1") /* fake analog Y */
722	722	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
723	723	INPUT_PORTS_END
724	724
725	725
726	726	static INPUT_PORTS_START( claypign )
727		PORT_START /* player inputs and logic board dips */
	727	PORT_START_TAG("IN0") /* player inputs and logic board dips */
728	728	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
729	729	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
730	730	PORT_BIT( 0x0c, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
736	736	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
737	737	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
738	738
739		PORT_START /* audio board dips */
	739	PORT_START_TAG("IN1") /* audio board dips */
740	740	COINAGE
741	741	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNKNOWN )
742	742	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
743	743	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
744	744	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
745	745
746		PORT_START /* start button */
	746	PORT_START_TAG("IN2") /* start button */
747	747	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
748	748	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNKNOWN )
749	749
750		PORT_START /* coin counters */
	750	PORT_START_TAG("IN3") /* coin counters */
751	751	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
752	752	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
753	753	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
754	754	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
755	755
756		PORT_START /* fake analog X */
	756	PORT_START_TAG("AN0") /* fake analog X */
757	757	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
758	758
759		PORT_START /* fake analog Y */
	759	PORT_START_TAG("AN1") /* fake analog Y */
760	760	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
761	761	INPUT_PORTS_END
762	762
763	763
764	764	static INPUT_PORTS_START( chiller )
765		PORT_START /* player inputs and logic board dips */
	765	PORT_START_TAG("IN0") /* player inputs and logic board dips */
766	766	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
767	767	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
768	768	PORT_DIPNAME( 0x0c, 0x00, "Seconds" )
r2864	r2865
778	778	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
779	779	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
780	780
781		PORT_START /* audio board dips */
	781	PORT_START_TAG("IN1") /* audio board dips */
782	782	COINAGE
783	783	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )
784	784
785		PORT_START /* start button */
	785	PORT_START_TAG("IN2") /* start button */
786	786	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
787	787	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNKNOWN )
788	788
789		PORT_START /* coin counters */
	789	PORT_START_TAG("IN3") /* coin counters */
790	790	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
791	791	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
792	792	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
793	793	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
794	794
795		PORT_START /* fake analog X */
	795	PORT_START_TAG("AN0") /* fake analog X */
796	796	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
797	797
798		PORT_START /* fake analog Y */
	798	PORT_START_TAG("AN1") /* fake analog Y */
799	799	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
800	800	INPUT_PORTS_END
801	801
802	802
803	803	static INPUT_PORTS_START( topsecex )
804		PORT_START /* player inputs and logic board dips */
	804	PORT_START_TAG("IN0") /* player inputs and logic board dips */
805	805	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
806	806	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN )
807	807	PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Lives ) )
r2864	r2865
817	817	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
818	818	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
819	819
820		PORT_START /* audio board dips */
	820	PORT_START_TAG("IN1") /* audio board dips */
821	821	COINAGE
822	822	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )
823	823
824		PORT_START /* start button */
	824	PORT_START_TAG("IN2") /* start button */
825	825	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON2 )
826	826	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNKNOWN )
827	827
828		PORT_START /* coin counters */
	828	PORT_START_TAG("IN3") /* coin counters */
829	829	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
830	830	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
831	831	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
832	832	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
833	833
834		PORT_START /* fake analog X */
	834	PORT_START_TAG("AN0") /* fake analog X */
835	835	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE
836	836
837		PORT_START /* fake analog Y */
	837	PORT_START_TAG("AN1") /* fake analog Y */
838	838	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_BUTTON1 )
839	839
840		PORT_START /* start button */
	840	PORT_START_TAG("IN4") /* start button */
841	841	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Fireball")
842	842	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Laser")
843	843	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("Missile")
r2864	r2865
850	850
851	851
852	852	static INPUT_PORTS_START( hitnmiss )
853		PORT_START /* player inputs and logic board dips */
	853	PORT_START_TAG("IN0") /* player inputs and logic board dips */
854	854	PORT_BIT( 0x03, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(hitnmiss_button1_r, 0)
855	855	PORT_DIPNAME( 0x0c, 0x00, "Seconds" )
856	856	PORT_DIPSETTING( 0x04, "20" )
r2864	r2865
865	865	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
866	866	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
867	867
868		PORT_START /* audio board dips */
	868	PORT_START_TAG("IN1") /* audio board dips */
869	869	COINAGE
870	870	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNKNOWN )
871	871	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Free_Play ) )
872	872	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
873	873	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
874	874
875		PORT_START /* start button */
	875	PORT_START_TAG("IN2") /* start button */
876	876	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
877	877	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNKNOWN )
878	878
879		PORT_START /* coin counters */
	879	PORT_START_TAG("IN3") /* coin counters */
880	880	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
881	881	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
882	882	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
883	883	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
884	884
885		PORT_START /* fake analog X */
	885	PORT_START_TAG("AN0") /* fake analog X */
886	886	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
887	887
888		PORT_START /* fake analog Y */
	888	PORT_START_TAG("AN1") /* fake analog Y */
889	889	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
890	890
891	891	PORT_START_TAG("HITNMISS_BUTTON1")
r2864	r2865
894	894
895	895
896	896	static INPUT_PORTS_START( whodunit )
897		PORT_START /* player inputs and logic board dips */
	897	PORT_START_TAG("IN0") /* player inputs and logic board dips */
898	898	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
899	899	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
900	900	PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Lives ) )
r2864	r2865
910	910	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
911	911	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
912	912
913		PORT_START /* audio board dips */
	913	PORT_START_TAG("IN1") /* audio board dips */
914	914	COINAGE
915	915	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )
916	916
917		PORT_START /* start button */
	917	PORT_START_TAG("IN2") /* start button */
918	918	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
919	919	PORT_BIT( 0xfe, IP_ACTIVE_HIGH, IPT_UNKNOWN )
920	920
921		PORT_START /* coin counters */
	921	PORT_START_TAG("IN3") /* coin counters */
922	922	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
923	923	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
924	924	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
925	925	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
926	926
927		PORT_START /* fake analog X */
	927	PORT_START_TAG("AN0") /* fake analog X */
928	928	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
929	929
930		PORT_START /* fake analog Y */
	930	PORT_START_TAG("AN1") /* fake analog Y */
931	931	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
932	932	INPUT_PORTS_END
933	933
934	934
935	935	static INPUT_PORTS_START( showdown )
936		PORT_START /* player inputs and logic board dips */
	936	PORT_START_TAG("IN0") /* player inputs and logic board dips */
937	937	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
938	938	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 )
939	939	PORT_DIPNAME( 0x0c, 0x00, "Hands" )
r2864	r2865
949	949	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_beam_r, 0)
950	950	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(firq_vblank_r, 0)
951	951
952		PORT_START /* audio board dips */
	952	PORT_START_TAG("IN1") /* audio board dips */
953	953	COINAGE
954	954	PORT_DIPNAME( 0x70, 0x70, DEF_STR( Unknown ) )
955	955	PORT_DIPSETTING( 0x70, "1" )
r2864	r2865
964	964	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
965	965	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
966	966
967		PORT_START /* start button */
	967	PORT_START_TAG("IN2") /* start button */
968	968	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 ) PORT_NAME("Action")
969	969	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("Bet-All")
970	970	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("Gold")
r2864	r2865
974	974	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
975	975	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
976	976
977		PORT_START /* coin counters */
	977	PORT_START_TAG("IN3") /* coin counters */
978	978	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CHANGED(coin_inserted, 0)
979	979	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_CHANGED(coin_inserted, 0)
980	980	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
981	981	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNKNOWN )
982	982
983		PORT_START /* fake analog X */
	983	PORT_START_TAG("AN0") /* fake analog X */
984	984	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
985	985
986		PORT_START /* fake analog Y */
	986	PORT_START_TAG("AN1") /* fake analog Y */
987	987	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(70) PORT_KEYDELTA(10)
988	988	INPUT_PORTS_END
989	989

src/mame/drivers/topshoot.c
r2864	r2865
138	138
139	139
140	140	static INPUT_PORTS_START( topshoot ) /* Top Shooter Input Ports */
141		PORT_START /* 16bit */
	141	PORT_START_TAG("IN0") /* 16bit */
142	142	PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Unknown ) )
143	143	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
144	144	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )

src/mame/drivers/blstroid.c
r2864	r2865
430	430	static DRIVER_INIT( blstroid )
431	431	{
432	432	atarigen_eeprom_default = NULL;
433		atarijsa_init(machine, 2, 0x80);
	433	atarijsa_init(machine, "IN0", 0x80);
434	434	}
435	435
436	436

src/mame/drivers/megaplay.c
r2864	r2865
117	117
118	118	static UINT32 readpos = 1; // serial bank selection position (9-bit)
119	119
120		#define MEGAPLAY_TEST \
121		PORT_START \
122		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Select") PORT_CODE(KEYCODE_0) \
123		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 1") PORT_CODE(KEYCODE_W) \
124		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 2") PORT_CODE(KEYCODE_E) \
125		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 3") PORT_CODE(KEYCODE_R) \
126		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 4") PORT_CODE(KEYCODE_T) \
127		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 5") PORT_CODE(KEYCODE_Y) \
128		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 6") PORT_CODE(KEYCODE_U) \
	120	static INPUT_PORTS_START ( megaplay )
	121	PORT_START_TAG("P1_1") /* Player 1 Controls - part 1 */
	122	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
	123	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
	124	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
	125	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
	126	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 )
	127	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 )
	128	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	129	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	130
	131	PORT_START_TAG("P1_2") /* Player 1 Controls - part 2 */
	132	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
	133	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
	134	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
	135	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
	136	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
	137	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
	138	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	139	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	140
	141	PORT_START_TAG("P2_1") /* Player 2 Controls - part 1 */
	142	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
	143	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
	144	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
	145	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
	146	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
	147	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
	148	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	149	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	150
	151	PORT_START_TAG("P2_2") /* Player 2 Controls - part 2 */
	152	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
	153	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
	154	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
	155	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
	156	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
	157	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
	158	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	159	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	160
	161	PORT_START_TAG("TEST")
	162	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Select") PORT_CODE(KEYCODE_0)
	163	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 1") PORT_CODE(KEYCODE_W)
	164	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 2") PORT_CODE(KEYCODE_E)
	165	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 3") PORT_CODE(KEYCODE_R)
	166	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 4") PORT_CODE(KEYCODE_T)
	167	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 5") PORT_CODE(KEYCODE_Y)
	168	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_NAME("0x6400 bit 6") PORT_CODE(KEYCODE_U)
129	169	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
130	170
131		#define MEGAPLAY_COIN \
132		PORT_START \
133		PORT_BIT ( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) \
134		PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) \
135		PORT_BIT ( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN ) \
136		PORT_BIT ( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN ) \
137		PORT_BIT ( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 ) \
138		PORT_BIT ( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
139		PORT_BIT ( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
	171	PORT_START_TAG("COIN")
	172	PORT_BIT ( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
	173	PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
	174	PORT_BIT ( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	175	PORT_BIT ( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	176	PORT_BIT ( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 )
	177	PORT_BIT ( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	178	PORT_BIT ( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
140	179	PORT_BIT ( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
141	180
142	181	/* Caused 01081:
143		* PORT_BIT ( 0x40, IP_ACTIVE_LOW, IPT_START1 ) \
	182	* PORT_BIT ( 0x40, IP_ACTIVE_LOW, IPT_START1 )
144	183	* PORT_BIT ( 0x80, IP_ACTIVE_LOW, IPT_START2 )
145	184	*/
146	185
147		#define MEGAPLAY_DSWA \
148		PORT_START \
149		PORT_DIPNAME( 0x0f, 0x0f, "Coin slot 1" ) PORT_DIPLOCATION("SW1:1,2,3,4") \
150		PORT_DIPSETTING( 0x07, DEF_STR( 4C_1C ) ) \
151		PORT_DIPSETTING( 0x08, DEF_STR( 3C_1C ) ) \
152		PORT_DIPSETTING( 0x09, DEF_STR( 2C_1C ) ) \
153		PORT_DIPSETTING( 0x05, "2 coins/1 credit - 5 coins/3 credits - 6 coins/4 credits" ) \
154		PORT_DIPSETTING( 0x04, "2 coins/1 credit - 4 coins/3 credits" ) \
155		PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) ) \
156		PORT_DIPSETTING( 0x06, DEF_STR( 2C_3C ) ) \
157		PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) ) \
158		PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) ) \
159		PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) ) \
160		PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) ) \
161		PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) ) \
162		PORT_DIPSETTING( 0x03, "1 coin/1 credit - 5 coins/6 credits" ) \
163		PORT_DIPSETTING( 0x02, "1 coin/1 credit - 4 coins/5 credits" ) \
164		PORT_DIPSETTING( 0x01, "1 coin/1 credit - 2 coins/3 credits" ) \
	186	PORT_START_TAG("DSW0")
	187	PORT_DIPNAME( 0x0f, 0x0f, "Coin slot 1" ) PORT_DIPLOCATION("SW1:1,2,3,4")
	188	PORT_DIPSETTING( 0x07, DEF_STR( 4C_1C ) )
	189	PORT_DIPSETTING( 0x08, DEF_STR( 3C_1C ) )
	190	PORT_DIPSETTING( 0x09, DEF_STR( 2C_1C ) )
	191	PORT_DIPSETTING( 0x05, "2 coins/1 credit - 5 coins/3 credits - 6 coins/4 credits" )
	192	PORT_DIPSETTING( 0x04, "2 coins/1 credit - 4 coins/3 credits" )
	193	PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
	194	PORT_DIPSETTING( 0x06, DEF_STR( 2C_3C ) )
	195	PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
	196	PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
	197	PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
	198	PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
	199	PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) )
	200	PORT_DIPSETTING( 0x03, "1 coin/1 credit - 5 coins/6 credits" )
	201	PORT_DIPSETTING( 0x02, "1 coin/1 credit - 4 coins/5 credits" )
	202	PORT_DIPSETTING( 0x01, "1 coin/1 credit - 2 coins/3 credits" )
165	203	PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
166	204
167		#define MEGAPLAY_DSWB \
168	205	PORT_DIPNAME( 0xf0, 0xf0, "Coin slot 2" ) PORT_DIPLOCATION("SW2:1,2,3,4")\
169		PORT_DIPSETTING( 0x70, DEF_STR( 4C_1C ) ) \
170		PORT_DIPSETTING( 0x80, DEF_STR( 3C_1C ) ) \
171		PORT_DIPSETTING( 0x90, DEF_STR( 2C_1C ) ) \
172		PORT_DIPSETTING( 0x50, "2 coins/1 credit - 5 coins/3 credits - 6 coins/4 credits" ) \
173		PORT_DIPSETTING( 0x40, "2 coins/1 credit - 4 coins/3 credits" ) \
174		PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) ) \
175		PORT_DIPSETTING( 0x60, DEF_STR( 2C_3C ) ) \
176		PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) ) \
177		PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) ) \
178		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) ) \
179		PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) ) \
180		PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) ) \
181		PORT_DIPSETTING( 0x30, "1 coin/1 credit - 5 coins/6 credits" ) \
182		PORT_DIPSETTING( 0x20, "1 coin/1 credit - 4 coins/5 credits" ) \
183		PORT_DIPSETTING( 0x10, "1 coin/1 credit - 2 coins/3 credits" ) \
	206	PORT_DIPSETTING( 0x70, DEF_STR( 4C_1C ) )
	207	PORT_DIPSETTING( 0x80, DEF_STR( 3C_1C ) )
	208	PORT_DIPSETTING( 0x90, DEF_STR( 2C_1C ) )
	209	PORT_DIPSETTING( 0x50, "2 coins/1 credit - 5 coins/3 credits - 6 coins/4 credits" )
	210	PORT_DIPSETTING( 0x40, "2 coins/1 credit - 4 coins/3 credits" )
	211	PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
	212	PORT_DIPSETTING( 0x60, DEF_STR( 2C_3C ) )
	213	PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
	214	PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
	215	PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
	216	PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
	217	PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
	218	PORT_DIPSETTING( 0x30, "1 coin/1 credit - 5 coins/6 credits" )
	219	PORT_DIPSETTING( 0x20, "1 coin/1 credit - 4 coins/5 credits" )
	220	PORT_DIPSETTING( 0x10, "1 coin/1 credit - 2 coins/3 credits" )
184	221	PORT_DIPSETTING( 0x00, " 1 coin/1 credit" )
185
186		static INPUT_PORTS_START ( megaplay )
187		GENESIS_PORTS
188		MEGAPLAY_TEST
189		MEGAPLAY_COIN
190		MEGAPLAY_DSWA
191		MEGAPLAY_DSWB
192	222	INPUT_PORTS_END
193	223
194	224	static INPUT_PORTS_START ( mp_sonic )
195		GENESIS_PORTS
196		MEGAPLAY_TEST
197		MEGAPLAY_COIN
198		MEGAPLAY_DSWA
199		MEGAPLAY_DSWB
	225	PORT_INCLUDE( megaplay )
200	226
201		PORT_START
202		// DSW C (per game settings)
	227	PORT_START_TAG("DSW1") /* DSW C (per game settings) */
203	228	PORT_DIPNAME( 0x03, 0x01, "Initial Players" ) PORT_DIPLOCATION("SW3:1,2")
204	229	PORT_DIPSETTING( 0x00, "4" )
205	230	PORT_DIPSETTING( 0x01, "3" )
r2864	r2865
218	243	INPUT_PORTS_END
219	244
220	245	static INPUT_PORTS_START ( mp_gaxe2 )
221		GENESIS_PORTS
222		MEGAPLAY_TEST
223		MEGAPLAY_COIN
224		MEGAPLAY_DSWA
225		MEGAPLAY_DSWB
	246	PORT_INCLUDE( megaplay )
226	247
227		PORT_START
228		// DSW C (per game settings)
	248	PORT_START_TAG("DSW1") /* DSW C (per game settings) */
229	249	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW3:1")
230	250	PORT_DIPSETTING( 0x01, DEF_STR( Normal ) )
231	251	PORT_DIPSETTING( 0x00, DEF_STR( Hard ) )
r2864	r2865
247	267
248	268	#ifdef UNUSED_DEFINITION
249	269	static INPUT_PORTS_START ( mp_col3 )
250		GENESIS_PORTS
251		MEGAPLAY_TEST
252		MEGAPLAY_COIN
253		MEGAPLAY_DSWA
254		MEGAPLAY_DSWB
	270	PORT_INCLUDE( megaplay )
255	271
256		PORT_START
257		// DSW C (per game settings)
	272	PORT_START_TAG("DSW1") /* DSW C (per game settings) */
258	273	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Language ) ) PORT_DIPLOCATION("SW3:1")
259	274	PORT_DIPSETTING( 0x01, DEF_STR( English ) )
260	275	PORT_DIPSETTING( 0x00, DEF_STR( Japanese ) )
r2864	r2865
275	290	#endif
276	291
277	292	static INPUT_PORTS_START ( mp_twc )
278		GENESIS_PORTS
279		MEGAPLAY_TEST
280		MEGAPLAY_COIN
281		MEGAPLAY_DSWA
282		MEGAPLAY_DSWB
	293	PORT_INCLUDE( megaplay )
283	294
284		PORT_START
285		// DSW C (per game settings)
	295	PORT_START_TAG("DSW1") /* DSW C (per game settings) */
286	296	PORT_DIPNAME( 0x01, 0x01, "Time" ) PORT_DIPLOCATION("SW3:1")
287	297	PORT_DIPSETTING( 0x01, DEF_STR( Normal ) )
288	298	PORT_DIPSETTING( 0x00, "Short" )
r2864	r2865
298	308	INPUT_PORTS_END
299	309
300	310	static INPUT_PORTS_START ( mp_sor2 )
301		GENESIS_PORTS
302		MEGAPLAY_TEST
303		MEGAPLAY_COIN
304		MEGAPLAY_DSWA
305		MEGAPLAY_DSWB
	311	PORT_INCLUDE( megaplay )
306	312
307		PORT_START
308		// DSW C (per game settings)
	313	PORT_START_TAG("DSW1") /* DSW C (per game settings) */
309	314	PORT_DIPNAME( 0x03, 0x01, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW3:1,2")
310	315	PORT_DIPSETTING( 0x00, "4" )
311	316	PORT_DIPSETTING( 0x01, "3" )
r2864	r2865
319	324	INPUT_PORTS_END
320	325
321	326	static INPUT_PORTS_START ( mp_bio )
322		GENESIS_PORTS
323		MEGAPLAY_TEST
324		MEGAPLAY_COIN
325		MEGAPLAY_DSWA
326		MEGAPLAY_DSWB
	327	PORT_INCLUDE( megaplay )
327	328
328		PORT_START
329		// DSW C (per game settings)
	329	PORT_START_TAG("DSW1") /* DSW C (per game settings) */
330	330	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW3:1,2")
331	331	PORT_DIPSETTING( 0x00, "5" )
332	332	PORT_DIPSETTING( 0x01, "4" )
r2864	r2865
340	340	INPUT_PORTS_END
341	341
342	342	static INPUT_PORTS_START ( mp_gslam )
343		GENESIS_PORTS
344		MEGAPLAY_TEST
345		MEGAPLAY_COIN
346		MEGAPLAY_DSWA
347		MEGAPLAY_DSWB
	343	PORT_INCLUDE( megaplay )
348	344
349		PORT_START
350		// DSW C (per game settings)
	345	PORT_START_TAG("DSW1") /* DSW C (per game settings) */
351	346	PORT_DIPNAME( 0x07, 0x04, DEF_STR ( Game_Time ) ) PORT_DIPLOCATION("SW3:1,2,3")
352	347	PORT_DIPSETTING( 0x00, "5:00" )
353	348	PORT_DIPSETTING( 0x01, "4:30" )
r2864	r2865
363	358	INPUT_PORTS_END
364	359
365	360	static INPUT_PORTS_START ( mp_mazin )
366		GENESIS_PORTS
367		MEGAPLAY_TEST
368		MEGAPLAY_COIN
369		MEGAPLAY_DSWA
370		MEGAPLAY_DSWB
	361	PORT_INCLUDE( megaplay )
371	362
372		PORT_START
373		// DSW C (per game settings)
	363	PORT_START_TAG("DSW1") /* DSW C (per game settings) */
374	364	PORT_DIPNAME( 0x01, 0x01, "Initial Player" ) PORT_DIPLOCATION("SW3:1")
375	365	PORT_DIPSETTING( 0x01, "2" )
376	366	PORT_DIPSETTING( 0x00, "1" )
r2864	r2865
386	376	INPUT_PORTS_END
387	377
388	378	static INPUT_PORTS_START ( mp_soni2 )
389		GENESIS_PORTS
390		MEGAPLAY_TEST
391		MEGAPLAY_COIN
392		MEGAPLAY_DSWA
393		MEGAPLAY_DSWB
	379	PORT_INCLUDE( megaplay )
394	380
395		PORT_START
396		// DSW C (per game settings)
	381	PORT_START_TAG("DSW1") /* DSW C (per game settings) */
397	382	PORT_DIPNAME( 0x03, 0x01, "Initial Players (Normal mode)" ) PORT_DIPLOCATION("SW3:1,2")
398	383	PORT_DIPSETTING( 0x00, "4" )
399	384	PORT_DIPSETTING( 0x01, "3" )
r2864	r2865
439	424	}
440	425
441	426
	427	/* Old code, todo, update the new code instead */
	428
	429	static READ16_HANDLER ( OLD_megaplay_genesis_io_r )
	430	{
	431	/* 8-bit only, data is mirrored in both halves */
	432
	433	UINT8 return_value = 0;
	434
	435	switch (offset)
	436	{
	437	case 0:
	438	/* Charles MacDonald ( http://cgfm2.emuviews.com/ )
	439	D7 : Console is 1= Export (USA, Europe, etc.) 0= Domestic (Japan)
	440	D6 : Video type is 1= PAL, 0= NTSC
	441	D5 : Sega CD unit is 1= not present, 0= connected.
	442	D4 : Unused (always returns zero)
	443	D3 : Bit 3 of version number
	444	D2 : Bit 2 of version number
	445	D1 : Bit 1 of version number
	446	D0 : Bit 0 of version number
	447	*/
	448	return_value = 0x80; /* ? megatech is usa? */
	449	break;
	450
	451	case 1: /* port A data (joypad 1) */
	452
	453	if (genesis_io_ram[offset] & 0x40)
	454	return_value = input_port_read(machine, "P1_1") & (genesis_io_ram[4]^0xff);
	455	else
	456	{
	457	return_value = input_port_read(machine, "P1_2") & (genesis_io_ram[4]^0xff);
	458	return_value \|= input_port_read(machine, "P1_1") & 0x03;
	459	}
	460	return_value = (genesis_io_ram[offset] & 0x80) \| return_value;
	461	// logerror ("reading joypad 1 , type %02x %02x\n",genesis_io_ram[offset] & 0xb0, return_value &0x7f);
	462	break;
	463
	464	case 2: /* port B data (joypad 2) */
	465
	466	if (genesis_io_ram[offset] & 0x40)
	467	return_value = input_port_read(machine, "P2_1") & (genesis_io_ram[5]^0xff);
	468	else
	469	{
	470	return_value = input_port_read(machine, "P2_2") & (genesis_io_ram[5]^0xff);
	471	return_value \|= input_port_read(machine, "P2_1") & 0x03;
	472	}
	473	return_value = (genesis_io_ram[offset] & 0x80) \| return_value;
	474	// logerror ("reading joypad 2 , type %02x %02x\n",genesis_io_ram[offset] & 0xb0, return_value &0x7f);
	475	break;
	476
	477	// case 3: /* port C data */
	478	// return_value = bios_6402 << 3;
	479	// break;
	480
	481	default:
	482	return_value = genesis_io_ram[offset];
	483
	484	}
	485	return return_value \| return_value << 8;
	486	}
	487
	488	static WRITE16_HANDLER ( OLD_megaplay_genesis_io_w )
	489	{
	490	// logerror ("write io offset :%02x data %04x PC: 0x%06x\n",offset,data,activecpu_get_previouspc());
	491
	492	switch (offset)
	493	{
	494	case 0x00:
	495	/??/
	496	break;
	497
	498	case 0x01:/* port A data */
	499	genesis_io_ram[offset] = (data & (genesis_io_ram[0x04])) \| (genesis_io_ram[offset] & ~(genesis_io_ram[0x04]));
	500	break;
	501
	502	case 0x02: /* port B data */
	503	genesis_io_ram[offset] = (data & (genesis_io_ram[0x05])) \| (genesis_io_ram[offset] & ~(genesis_io_ram[0x05]));
	504	break;
	505
	506	case 0x03: /* port C data */
	507	genesis_io_ram[offset] = (data & (genesis_io_ram[0x06])) \| (genesis_io_ram[offset] & ~(genesis_io_ram[0x06]));
	508	bios_6204 = data & 0x07;
	509	break;
	510
	511	case 0x04: /* port A control */
	512	genesis_io_ram[offset] = data;
	513	break;
	514
	515	case 0x05: /* port B control */
	516	genesis_io_ram[offset] = data;
	517	break;
	518
	519	case 0x06: /* port C control */
	520	genesis_io_ram[offset] = data;
	521	break;
	522
	523	case 0x07: /* port A TxData */
	524	genesis_io_ram[offset] = data;
	525	break;
	526
	527	default:
	528	genesis_io_ram[offset] = data;
	529	}
	530	}
	531
442	532	static READ8_HANDLER( bank_r )
443	533	{
444	534	UINT8* bank = memory_region(REGION_CPU3);
445	535	UINT8* game = memory_region(REGION_CPU1);
446	536
447	537	if(game_banksel == 0x142) // Genesis I/O
448		return megaplay_genesis_io_r(machine, (offset & 0x1f) / 2, 0xffff);
	538	return OLD_megaplay_genesis_io_r(machine, (offset & 0x1f) / 2, 0xffff);
449	539
450	540	if(bios_mode & MP_ROM)
451	541	{
r2864	r2865
478	568	static WRITE8_HANDLER ( bank_w )
479	569	{
480	570	if(game_banksel == 0x142) // Genesis I/O
481		genesis_io_w(machine, (offset & 0x1f) / 2, data, 0xffff);
	571	OLD_megaplay_genesis_io_w(machine, (offset & 0x1f) / 2, data, 0xffff);
482	572
483	573	if(offset <= 0x1fff && (bios_width & 0x08))
484	574	ic37_ram[(0x2000 * (bios_bank & 0x03)) + offset] = data;
r2864	r2865
569	659	AM_RANGE(0x0000, 0x3fff) AM_READ(SMH_ROM)
570	660	AM_RANGE(0x4000, 0x4fff) AM_READ(SMH_RAM)
571	661	AM_RANGE(0x5000, 0x5fff) AM_READ(SMH_RAM)
572		AM_RANGE(0x6200, 0x6200) AM_READ(input_port_7_r)
573		AM_RANGE(0x6201, 0x6201) AM_READ(input_port_8_r)
574		AM_RANGE(0x6400, 0x6400) AM_READ(input_port_5_r)
575		AM_RANGE(0x6401, 0x6401) AM_READ(input_port_6_r)
	662	AM_RANGE(0x6200, 0x6200) AM_READ_PORT("DSW0")
	663	AM_RANGE(0x6201, 0x6201) AM_READ_PORT("DSW1")
	664	AM_RANGE(0x6400, 0x6400) AM_READ_PORT("TEST")
	665	AM_RANGE(0x6401, 0x6401) AM_READ_PORT("COIN")
576	666	AM_RANGE(0x6204, 0x6204) AM_READ(megaplay_bios_6204_r)
577	667	AM_RANGE(0x6203, 0x6203) AM_READ(megaplay_bios_banksel_r)
578	668	AM_RANGE(0x6402, 0x6402) AM_READ(megaplay_bios_6402_r)
r2864	r2865
853	943	}
854	944	}
855	945
856		/* Old code, todo, update the new code instead */
857		static READ16_HANDLER ( OLD_megaplay_genesis_io_r )
858		{
859		/* 8-bit only, data is mirrored in both halves */
860
861		UINT8 return_value = 0;
862
863		switch (offset)
864		{
865		case 0:
866		/* Charles MacDonald ( http://cgfm2.emuviews.com/ )
867		D7 : Console is 1= Export (USA, Europe, etc.) 0= Domestic (Japan)
868		D6 : Video type is 1= PAL, 0= NTSC
869		D5 : Sega CD unit is 1= not present, 0= connected.
870		D4 : Unused (always returns zero)
871		D3 : Bit 3 of version number
872		D2 : Bit 2 of version number
873		D1 : Bit 1 of version number
874		D0 : Bit 0 of version number
875		*/
876		return_value = 0x80; /* ? megatech is usa? */
877		break;
878
879		case 1: /* port A data (joypad 1) */
880
881		if (genesis_io_ram[offset] & 0x40)
882		return_value = input_port_read_indexed(machine, 1) & (genesis_io_ram[4]^0xff);
883		else
884		{
885		return_value = input_port_read_indexed(machine, 2) & (genesis_io_ram[4]^0xff);
886		return_value \|= input_port_read_indexed(machine, 1) & 0x03;
887		}
888		return_value = (genesis_io_ram[offset] & 0x80) \| return_value;
889		// logerror ("reading joypad 1 , type %02x %02x\n",genesis_io_ram[offset] & 0xb0, return_value &0x7f);
890		break;
891
892		case 2: /* port B data (joypad 2) */
893
894		if (genesis_io_ram[offset] & 0x40)
895		return_value = input_port_read_indexed(machine, 3) & (genesis_io_ram[5]^0xff);
896		else
897		{
898		return_value = input_port_read_indexed(machine, 4) & (genesis_io_ram[5]^0xff);
899		return_value \|= input_port_read_indexed(machine, 3) & 0x03;
900		}
901		return_value = (genesis_io_ram[offset] & 0x80) \| return_value;
902		// logerror ("reading joypad 2 , type %02x %02x\n",genesis_io_ram[offset] & 0xb0, return_value &0x7f);
903		break;
904
905		// case 3: /* port C data */
906		// return_value = bios_6402 << 3;
907		// break;
908
909		default:
910		return_value = genesis_io_ram[offset];
911
912		}
913		return return_value \| return_value << 8;
914		}
915
916		static WRITE16_HANDLER ( OLD_megaplay_genesis_io_w )
917		{
918		// logerror ("write io offset :%02x data %04x PC: 0x%06x\n",offset,data,activecpu_get_previouspc());
919
920		switch (offset)
921		{
922		case 0x00:
923		/??/
924		break;
925
926		case 0x01:/* port A data */
927		genesis_io_ram[offset] = (data & (genesis_io_ram[0x04])) \| (genesis_io_ram[offset] & ~(genesis_io_ram[0x04]));
928		break;
929
930		case 0x02: /* port B data */
931		genesis_io_ram[offset] = (data & (genesis_io_ram[0x05])) \| (genesis_io_ram[offset] & ~(genesis_io_ram[0x05]));
932		break;
933
934		case 0x03: /* port C data */
935		genesis_io_ram[offset] = (data & (genesis_io_ram[0x06])) \| (genesis_io_ram[offset] & ~(genesis_io_ram[0x06]));
936		bios_6204 = data & 0x07;
937		break;
938
939		case 0x04: /* port A control */
940		genesis_io_ram[offset] = data;
941		break;
942
943		case 0x05: /* port B control */
944		genesis_io_ram[offset] = data;
945		break;
946
947		case 0x06: /* port C control */
948		genesis_io_ram[offset] = data;
949		break;
950
951		case 0x07: /* port A TxData */
952		genesis_io_ram[offset] = data;
953		break;
954
955		default:
956		genesis_io_ram[offset] = data;
957		}
958		}
959
960
961	946	static READ16_HANDLER( megadriv_68k_read_z80_extra_ram )
962	947	{
963	948	return ic36_ram[(offset<<1)^1] \| (ic36_ram[(offset<<1)]<<8);

src/mame/drivers/harddriv.c
r2864	r2865
179	179	#include "sound/dac.h"
180	180
181	181	/* from slapstic.c */
182		void slapstic_init(int chip);
	182	void slapstic_init(running_machine *machine, int chip);
183	183
184	184
185	185
r2864	r2865
534	534	*************************************/
535	535
536	536	static INPUT_PORTS_START( harddriv )
537		PORT_START_TAG("600000")
	537	PORT_START_TAG("IN0") /* 600000 */
538	538	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED ) /* diagnostic switch */
539	539	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
540	540	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_VBLANK )
r2864	r2865
590	590
591	591
592	592	static INPUT_PORTS_START( racedriv )
593		PORT_START_TAG("600000")
	593	PORT_START_TAG("IN0") /* 600000 */
594	594	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED ) /* diagnostic switch */
595	595	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
596	596	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_VBLANK )
r2864	r2865
646	646
647	647
648	648	static INPUT_PORTS_START( racedrvc )
649		PORT_START_TAG("60c000")
	649	PORT_START_TAG("IN0") /* 60c000 */
650	650	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED ) /* diagnostic switch */
651	651	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
652	652	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_VBLANK )
r2864	r2865
708	708
709	709
710	710	static INPUT_PORTS_START( stunrun )
711		PORT_START_TAG("60c000")
	711	PORT_START_TAG("IN0") /* 60c000 */
712	712	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
713	713	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
714	714	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_VBLANK )
r2864	r2865
766	766
767	767
768	768	static INPUT_PORTS_START( steeltal )
769		PORT_START_TAG("60c000")
	769	PORT_START_TAG("IN0") /* 60c000 */
770	770	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
771	771	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
772	772	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_VBLANK )
r2864	r2865
825	825
826	826
827	827	static INPUT_PORTS_START( strtdriv )
828		PORT_START_TAG("60c000")
	828	PORT_START_TAG("IN0") /* 60c000 */
829	829	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
830	830	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
831	831	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_VBLANK )
r2864	r2865
874	874	PORT_START_TAG("8BADC7") /* b00000 - 8 bit ADC 7 - seat adjust */
875	875	PORT_BIT( 0xff, 0X80, IPT_UNUSED )
876	876
877		PORT_START_TAG("~~40000~~0") /* 400000 - steering wheel */
	877	PORT_START_TAG("12BADC0") /* 400000 - steering wheel */
878	878	PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(25) PORT_KEYDELTA(5)
879	879
880	880	/* dummy ADC ports to end up with the same number as the full version */
881		PORT_START_TAG("12BADCX")
	881	PORT_START_TAG("12BADC1") /* FAKE */
882	882	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
883		PORT_START_TAG("12BADCY")
	883	PORT_START_TAG("12BADC2") /* FAKE */
884	884	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
885		PORT_START_TAG("12BADCZ")
	885	PORT_START_TAG("12BADC3") /* FAKE */
886	886	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
887	887	INPUT_PORTS_END
888	888
889	889
890	890	static INPUT_PORTS_START( hdrivair )
891		PORT_START_TAG("60c000")
	891	PORT_START_TAG("IN0") /* 60c000 */
892	892	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
893	893	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* HBLANK */
894	894	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_VBLANK )
r2864	r2865
3522	3522	hddsk_rom = (UINT16 *)(memory_region(REGION_USER3) + 0x00000);
3523	3523
3524	3524	/* set up the ASIC65 */
3525		asic65_config(ASIC65_STANDARD);
	3525	asic65_config(machine, ASIC65_STANDARD);
3526	3526	}
3527	3527
3528	3528
r2864	r2865
3549	3549	hddsk_rom = (UINT16 *)(memory_region(REGION_USER3) + 0x000000);
3550	3550
3551	3551	/* set up the ASIC65 */
3552		asic65_config(ASIC65_STANDARD);
	3552	asic65_config(machine, ASIC65_STANDARD);
3553	3553	}
3554	3554
3555	3555
r2864	r2865
3562	3562	memory_install_read16_handler(machine, hdcpu_main, ADDRESS_SPACE_PROGRAM, 0x901000, 0x910001, 0, 0, asic65_io_r);
3563	3563
3564	3564	/* set up the ASIC65 */
3565		asic65_config(ASIC65_STEELTAL);
	3565	asic65_config(machine, ASIC65_STEELTAL);
3566	3566
3567	3567	/* install DSPCOM control */
3568	3568	memory_install_write16_handler(machine, hdcpu_main, ADDRESS_SPACE_PROGRAM, 0x904000, 0x90401f, 0, 0, hddspcom_control_w);
r2864	r2865
3640	3640	/* initialize the boards */
3641	3641	init_multisync(machine, 0);
3642	3642	init_adsp(machine);
3643		atarijsa_init(machine, 0, 0x0020);
	3643	atarijsa_init(machine, "IN0", 0x0020);
3644	3644
3645	3645	/* set up gsp speedup handler */
3646	3646	hdgsp_speedup_addr[0] = memory_install_write16_handler(machine, hdcpu_gsp, ADDRESS_SPACE_PROGRAM, 0xfff9fc00, 0xfff9fc0f, 0, 0, hdgsp_speedup1_w);
r2864	r2865
3685	3685	init_driver_sound(machine);
3686	3686
3687	3687	/* set up the slapstic */
3688		slapstic_init(117);
	3688	slapstic_init(machine, 117);
3689	3689	hd68k_slapstic_base = memory_install_readwrite16_handler(machine, hdcpu_main, ADDRESS_SPACE_PROGRAM, 0xe0000, 0xfffff, 0, 0, rd68k_slapstic_r, rd68k_slapstic_w);
3690	3690
3691	3691	/* synchronization */
r2864	r2865
3710	3710	init_driver_sound(machine);
3711	3711
3712	3712	/* set up the slapstic */
3713		slapstic_init(117);
	3713	slapstic_init(machine, 117);
3714	3714	hd68k_slapstic_base = memory_install_readwrite16_handler(machine, hdcpu_main, ADDRESS_SPACE_PROGRAM, 0xe0000, 0xfffff, 0, 0, rd68k_slapstic_r, rd68k_slapstic_w);
3715	3715
3716	3716	/* synchronization */
r2864	r2865
3751	3751	init_ds3(machine);
3752	3752	init_dspcom(machine);
3753	3753	atarijsa3_init_adpcm(REGION_SOUND1);
3754		atarijsa_init(machine, 0, 0x0020);
	3754	atarijsa_init(machine, "IN0", 0x0020);
3755	3755
3756	3756	memory_install_read16_handler(machine, hdcpu_main, ADDRESS_SPACE_PROGRAM, 0x908000, 0x908001, 0, 0, steeltal_dummy_r);
3757	3757
r2864	r2865
3800	3800	init_dsk(machine);
3801	3801
3802	3802	/* set up the slapstic */
3803		slapstic_init(117);
	3803	slapstic_init(machine, 117);
3804	3804	hd68k_slapstic_base = memory_install_readwrite16_handler(machine, hdcpu_main, ADDRESS_SPACE_PROGRAM, 0xe0000, 0xfffff, 0, 0, rd68k_slapstic_r, rd68k_slapstic_w);
3805	3805
3806	3806	memory_install_read16_handler(machine, hdcpu_main, ADDRESS_SPACE_PROGRAM, 0xa80000, 0xafffff, 0, 0, hda68k_port1_r);

src/mame/drivers/pokechmp.c
r2864	r2865
45	45	*/
46	46
47	47	#include "driver.h"
48		#include "deprecat.h"
49	48	#include "cpu/m6502/m6502.h"
50	49	#include "sound/2203intf.h"
51	50	#include "sound/3812intf.h"
r2864	r2865
99	98	}
100	99
101	100
102		INLINE void pokechmp_set_color(pen_t color, int rshift, int gshift, int bshift, UINT16 data)
	101	INLINE void pokechmp_set_color(running_machine *machine, pen_t color, int rshift, int gshift, int bshift, UINT16 data)
103	102	{
104		palette_set_color_rgb(Machine, color, pal5bit(data >> rshift), pal5bit(data >> gshift), pal5bit(data >> bshift));
	103	palette_set_color_rgb(machine, color, pal5bit(data >> rshift), pal5bit(data >> gshift), pal5bit(data >> bshift));
105	104	}
106	105
107	106
108	107	static WRITE8_HANDLER( pokechmp_paletteram_w )
109	108	{
110	109	paletteram[offset] = data;
111		pokechmp_set_color(offset &0x3ff, 0, 5, 10, (paletteram[offset&0x3ff]<<8) \| ( paletteram[ (offset&0x3ff)+0x400 ] ) );
	110	pokechmp_set_color(machine, offset &0x3ff, 0, 5, 10, (paletteram[offset&0x3ff]<<8) \| ( paletteram[ (offset&0x3ff)+0x400 ] ) );
112	111	}
113	112
114	113

src/mame/drivers/konamigv.c
r2864	r2865
517	517	int axis;
518	518	UINT16 diff;
519	519	UINT16 value;
	520	static const char *axisnames[] = { "TRACK0_X", "TRACK0_Y" };
520	521
521	522	for( axis = 0; axis < 2; axis++ )
522	523	{
523		value = input_port_read~~_indexed~~(machine, axis ~~+ 3~~ );
	524	value = input_port_read(machine, axisnames[axis]);
524	525	diff = value - trackball_prev[ axis ];
525	526	trackball_prev[ axis ] = value;
526	527	trackball_data[ axis ] = ( ( diff & 0xf00 ) << 16 ) \| ( ( diff & 0xff ) << 8 );
r2864	r2865
556	557	static INPUT_PORTS_START( simpbowl )
557	558	PORT_INCLUDE( konamigv )
558	559
559		PORT_START_TAG("~~IN3~~")
	560	PORT_START_TAG("TRACK0_X")
560	561	PORT_BIT( 0xfff, 0x0000, IPT_TRACKBALL_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(63) PORT_REVERSE PORT_PLAYER(1)
561	562
562		PORT_START_TAG("~~IN4~~")
	563	PORT_START_TAG("TRACK0_Y")
563	564	PORT_BIT( 0xfff, 0x0000, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(63) PORT_PLAYER(1)
564	565
565	566	INPUT_PORTS_END
r2864	r2865
601	602	int axis;
602	603	UINT16 diff;
603	604	UINT16 value;
	605	static const char *axisnames[] = { "TRACK0_X", "TRACK0_Y", "TRACK1_X", "TRACK1_Y" };
604	606
605	607	for( axis = 0; axis < 4; axis++ )
606	608	{
607		value = input_port_read~~_indexed~~(machine, axis ~~+ 3~~ );
	609	value = input_port_read(machine, axisnames[axis]);
608	610	diff = value - btc_trackball_prev[ axis ];
609	611	btc_trackball_prev[ axis ] = value;
610	612	btc_trackball_data[ axis ] = ( ( diff & 0xf00 ) << 16 ) \| ( ( diff & 0xff ) << 8 );
r2864	r2865
643	645	static INPUT_PORTS_START( btchamp )
644	646	PORT_INCLUDE( konamigv )
645	647
646		PORT_START_TAG("~~IN3~~")
	648	PORT_START_TAG("TRACK0_X")
647	649	PORT_BIT( 0x7ff, 0x0000, IPT_TRACKBALL_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(63) PORT_REVERSE PORT_PLAYER(1)
648	650
649		PORT_START_TAG("~~IN4~~")
	651	PORT_START_TAG("TRACK0_Y")
650	652	PORT_BIT( 0x7ff, 0x0000, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(63) PORT_PLAYER(1)
651	653
652		PORT_START_TAG("~~IN5~~")
	654	PORT_START_TAG("TRACK1_X")
653	655	PORT_BIT( 0x7ff, 0x0000, IPT_TRACKBALL_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(63) PORT_REVERSE PORT_PLAYER(2)
654	656
655		PORT_START_TAG("~~IN6~~")
	657	PORT_START_TAG("TRACK1_Y")
656	658	PORT_BIT( 0x7ff, 0x0000, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(63) PORT_PLAYER(2)
657	659	INPUT_PORTS_END
658	660

src/mame/drivers/firetrap.c
r2864	r2865
101	101	/* Check for coin insertion */
102	102	/* the following only works in the bootleg version, which doesn't have an */
103	103	/* 8751 - the real thing is much more complicated than that. */
104		if ((input_port_read~~_indexed~~(machine, 2) & 0x70) != 0x70) return 0xff;
	104	if ((input_port_read(machine, "IN2") & 0x70) != 0x70) return 0xff;
105	105	return 0;
106	106	}
107	107
r2864	r2865
247	247	AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM)
248	248	AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1)
249	249	AM_RANGE(0xc000, 0xe97f) AM_READ(SMH_RAM)
250		AM_RANGE(0xf010, 0xf010) AM_READ(input_port_0_r)
251		AM_RANGE(0xf011, 0xf011) AM_READ(input_port_1_r)
252		AM_RANGE(0xf012, 0xf012) AM_READ(input_port_2_r)
253		AM_RANGE(0xf013, 0xf013) AM_READ(input_port_3_r)
254		AM_RANGE(0xf014, 0xf014) AM_READ(input_port_4_r)
	250	AM_RANGE(0xf010, 0xf010) AM_READ_PORT("IN0")
	251	AM_RANGE(0xf011, 0xf011) AM_READ_PORT("IN1")
	252	AM_RANGE(0xf012, 0xf012) AM_READ_PORT("IN2")
	253	AM_RANGE(0xf013, 0xf013) AM_READ_PORT("DSW0")
	254	AM_RANGE(0xf014, 0xf014) AM_READ_PORT("DSW1")
255	255	AM_RANGE(0xf016, 0xf016) AM_READ(firetrap_8751_r)
256	256	ADDRESS_MAP_END
257	257
r2864	r2865
278	278	AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM)
279	279	AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1)
280	280	AM_RANGE(0xc000, 0xe97f) AM_READ(SMH_RAM)
281		AM_RANGE(0xf010, 0xf010) AM_READ(input_port_0_r)
282		AM_RANGE(0xf011, 0xf011) AM_READ(input_port_1_r)
283		AM_RANGE(0xf012, 0xf012) AM_READ(input_port_2_r)
284		AM_RANGE(0xf013, 0xf013) AM_READ(input_port_3_r)
285		AM_RANGE(0xf014, 0xf014) AM_READ(input_port_4_r)
	281	AM_RANGE(0xf010, 0xf010) AM_READ_PORT("IN0")
	282	AM_RANGE(0xf011, 0xf011) AM_READ_PORT("IN1")
	283	AM_RANGE(0xf012, 0xf012) AM_READ_PORT("IN2")
	284	AM_RANGE(0xf013, 0xf013) AM_READ_PORT("DSW0")
	285	AM_RANGE(0xf014, 0xf014) AM_READ_PORT("DSW1")
286	286	AM_RANGE(0xf016, 0xf016) AM_READ(firetrap_8751_bootleg_r)
287	287	AM_RANGE(0xf800, 0xf8ff) AM_READ(SMH_ROM) /* extra ROM in the bootleg with unprotection code */
288	288	ADDRESS_MAP_END
r2864	r2865
327	327
328	328
329	329	static INPUT_PORTS_START( firetrap )
330		PORT_START /* IN0 */
	330	PORT_START_TAG("IN0") /* IN0 */
331	331	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_UP ) PORT_4WAY
332	332	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) PORT_4WAY
333	333	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_LEFT ) PORT_4WAY
r2864	r2865
337	337	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_LEFT ) PORT_4WAY
338	338	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_RIGHT ) PORT_4WAY
339	339
340		PORT_START /* IN1 */
	340	PORT_START_TAG("IN1") /* IN1 */
341	341	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_UP ) PORT_4WAY PORT_COCKTAIL
342	342	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) PORT_4WAY PORT_COCKTAIL
343	343	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_LEFT ) PORT_4WAY PORT_COCKTAIL
r2864	r2865
347	347	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_LEFT ) PORT_4WAY PORT_COCKTAIL
348	348	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_RIGHT ) PORT_4WAY PORT_COCKTAIL
349	349
350		PORT_START /* IN2 */
	350	PORT_START_TAG("IN2") /* IN2 */
351	351	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
352	352	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START1 )
353	353	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
r2864	r2865
357	357	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
358	358	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_VBLANK )
359	359
360		PORT_START /* DSW0 */
	360	PORT_START_TAG("DSW0") /* DSW0 */
361	361	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coin_A ) )
362	362	// PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
363	363	// PORT_DIPSETTING( 0x01, DEF_STR( 1C_1C ) )
r2864	r2865
382	382	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
383	383	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
384	384
385		PORT_START /* DSW1 */
	385	PORT_START_TAG("DSW1") /* DSW1 */
386	386	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
387	387	PORT_DIPSETTING( 0x02, DEF_STR( Easy ) )
388	388	PORT_DIPSETTING( 0x03, DEF_STR( Normal ) )
r2864	r2865
403	403	PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
404	404	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
405	405
406		PORT_START /* Connected to i8751 directly */
	406	PORT_START_TAG("COIN") /* Connected to i8751 directly */
407	407	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
408	408	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
409	409	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
410	410	INPUT_PORTS_END
411	411
412	412	static INPUT_PORTS_START( firetpbl )
413		PORT_START /* IN0 */
	413	PORT_START_TAG("IN0") /* IN0 */
414	414	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_UP ) PORT_4WAY
415	415	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) PORT_4WAY
416	416	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_LEFT ) PORT_4WAY
r2864	r2865
420	420	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_LEFT ) PORT_4WAY
421	421	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_RIGHT ) PORT_4WAY
422	422
423		PORT_START /* IN1 */
	423	PORT_START_TAG("IN1") /* IN1 */
424	424	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_UP ) PORT_4WAY PORT_COCKTAIL
425	425	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) PORT_4WAY PORT_COCKTAIL
426	426	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_LEFT ) PORT_4WAY PORT_COCKTAIL
r2864	r2865
430	430	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_LEFT ) PORT_4WAY PORT_COCKTAIL
431	431	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_RIGHT ) PORT_4WAY PORT_COCKTAIL
432	432
433		PORT_START /* IN2 */
	433	PORT_START_TAG("IN2") /* IN2 */
434	434	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
435	435	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START1 )
436	436	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
r2864	r2865
440	440	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 ) /* bootleg only */
441	441	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_VBLANK )
442	442
443		PORT_START /* DSW0 */
	443	PORT_START_TAG("DSW0") /* DSW0 */
444	444	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coin_A ) )
445	445	// PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
446	446	// PORT_DIPSETTING( 0x01, DEF_STR( 1C_1C ) )
r2864	r2865
465	465	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
466	466	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
467	467
468		PORT_START /* DSW1 */
	468	PORT_START_TAG("DSW1") /* DSW1 */
469	469	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
470	470	PORT_DIPSETTING( 0x02, DEF_STR( Easy ) )
471	471	PORT_DIPSETTING( 0x03, DEF_STR( Normal ) )
r2864	r2865
544	544	static int coin_command_pending=0;
545	545
546	546	/* Check for coin IRQ */
547		if (cpu_getiloops()) {
548		if ((input_port_read_indexed(machine, 5) & 0x7) != 0x7 && !latch) {
549		coin_command_pending=~input_port_read_indexed(machine, 5);
	547	if (cpu_getiloops())
	548	{
	549	if ((input_port_read(machine, "COIN") & 0x7) != 0x7 && !latch)
	550	{
	551	coin_command_pending = ~input_port_read(machine, "COIN");
550	552	latch=1;
551	553	}
552		if ((input_port_read~~_indexed~~(machine, 5) & 0x7) == 0x7)
	554	if ((input_port_read(machine, "COIN") & 0x7) == 0x7)
553	555	latch=0;
554	556
555	557	/* Make sure coin IRQ's aren't generated when another command is pending, the main cpu

src/mame/drivers/topspeed.c
r2864	r2865
230	230	***************************************************************************/
231	231
232	232	#include "driver.h"
233		#include "deprecat.h"
234	233	#include "taitoipt.h"
235	234	#include "cpu/m68000/m68000.h"
236	235	#include "video/taitoic.h"
r2864	r2865
265	264	COMBINE_DATA(&sharedram[offset]);
266	265	}
267	266
268		static void parse_control(void) /* assumes Z80 sandwiched between 68Ks */
	267	static void parse_control(running_machine machine) / assumes Z80 sandwiched between 68Ks */
269	268	{
270	269	/* bit 0 enables cpu B */
271	270	/* however this fails when recovering from a save state
272	271	if cpu B is disabled !! */
273		cpunum_set_input_line(Machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
	272	cpunum_set_input_line(machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
274	273
275	274	}
276	275
r2864	r2865
280	279	data = data >> 8; /* for Wgp */
281	280	cpua_ctrl = data;
282	281
283		parse_control();
	282	parse_control(machine);
284	283
285	284	logerror("CPU #0 PC %06x: write %04x to cpu control\n",activecpu_get_pc(),data);
286	285	}
r2864	r2865
681	680
682	681	static STATE_POSTLOAD( topspeed_postload )
683	682	{
684		parse_control();
	683	parse_control(machine);
685	684	reset_sound_region();
686	685	}
687	686

src/mame/drivers/segae.c
r2864	r2865
765	765	return retdata;
766	766	}
767	767
768		static void vdp_data_w(UINT8 data, struct sms_vdp* chip)
	768	static void vdp_data_w(running_machine machine, UINT8 data, struct sms_vdp chip)
769	769	{
770	770	/* data writes clear the pending flag */
771	771	chip->cmd_pend = 0;
r2864	r2865
801	801	r = (palword & 0x000f)>>0;
802	802	g = (palword & 0x00f0)>>4;
803	803	b = (palword & 0x0f00)>>8;
804		palette_set_color_rgb(Machine,(chip->addr_reg&0x3e)/2, pal4bit(r), pal4bit(g), pal4bit(b));
	804	palette_set_color_rgb(machine,(chip->addr_reg&0x3e)/2, pal4bit(r), pal4bit(g), pal4bit(b));
805	805	chip->cram_mamecolours[(chip->addr_reg&0x3e)/2]=(b<<1)\|(g<<6)\|(r<<11);
806	806	}
807	807	}
r2864	r2865
816	816	r = (data & 0x03)>>0;
817	817	g = (data & 0x0c)>>2;
818	818	b = (data & 0x30)>>4;
819		palette_set_color_rgb(Machine,chip->addr_reg&0x1f, pal2bit(r), pal2bit(g), pal2bit(b));
	819	palette_set_color_rgb(machine,chip->addr_reg&0x1f, pal2bit(r), pal2bit(g), pal2bit(b));
820	820	chip->cram_mamecolours[chip->addr_reg&0x1f]=(b<<3)\|(g<<8)\|(r<<13);
821	821	}
822	822
r2864	r2865
945	945
946	946	WRITE8_HANDLER( md_sms_vdp_data_w )
947	947	{
948		vdp_data_w(data, md_sms_vdp);
	948	vdp_data_w(machine, data, md_sms_vdp);
949	949	}
950	950
951	951	READ8_HANDLER( md_sms_vdp_ctrl_r )
r2864	r2865
973	973
974	974	WRITE8_HANDLER( sms_vdp_data_w )
975	975	{
976		vdp_data_w(data, vdp1);
	976	vdp_data_w(machine, data, vdp1);
977	977	}
978	978
979	979	READ8_HANDLER( sms_vdp_ctrl_r )
r2864	r2865
1422	1422	Even though some games set bit 7, it does nothing.
1423	1423	*/
1424	1424
1425		static void end_of_frame(struct sms_vdp *chip)
	1425	static void end_of_frame(running_machine machine, struct sms_vdp chip)
1426	1426	{
1427	1427	UINT8 m1 = (chip->regs[0x1]&0x10)>>4;
1428	1428	UINT8 m2 = (chip->regs[0x0]&0x02)>>1;
r2864	r2865
1440	1440	visarea.min_y = 0;
1441	1441	visarea.max_y = sms_mode_table[chip->screen_mode].sms2_height-1;
1442	1442
1443		if (chip->chip_id==3) video_screen_configure(Machine->primary_screen, 256, 256, &visarea, HZ_TO_ATTOSECONDS(chip->sms_framerate));
	1443	if (chip->chip_id==3) video_screen_configure(machine->primary_screen, 256, 256, &visarea, HZ_TO_ATTOSECONDS(chip->sms_framerate));
1444	1444
1445	1445	}
1446	1446	else /* 160x144 */
r2864	r2865
1464	1464	#ifdef UNUSED_FUNCTION
1465	1465	VIDEO_EOF(sms)
1466	1466	{
1467		end_of_frame(vdp1);
	1467	end_of_frame(machine, vdp1);
1468	1468	//if (SMS_PAUSE_BUTTON) cpunum_set_input_line(machine, 0,INPUT_LINE_NMI,PULSE_LINE); // not on systeme!!!
1469	1469	}
1470	1470	#endif
r2864	r2865
1954	1954
1955	1955	static VIDEO_EOF(systeme)
1956	1956	{
1957		end_of_frame(vdp1);
1958		end_of_frame(vdp2);
	1957	end_of_frame(machine, vdp1);
	1958	end_of_frame(machine, vdp2);
1959	1959	}
1960	1960
1961	1961
1962	1962	VIDEO_EOF(megatech_md_sms)
1963	1963	{
1964		end_of_frame(md_sms_vdp);
	1964	end_of_frame(machine, md_sms_vdp);
1965	1965	}
1966	1966
1967	1967	VIDEO_EOF(megatech_bios)
1968	1968	{
1969		end_of_frame(vdp1);
	1969	end_of_frame(machine, vdp1);
1970	1970	}
1971	1971
1972	1972	VIDEO_UPDATE(megatech_md_sms)
r2864	r2865
2081	2081
2082	2082	static WRITE8_HANDLER( sms_vdp_2_data_w )
2083	2083	{
2084		vdp_data_w(data, vdp2);
	2084	vdp_data_w(machine, data, vdp2);
2085	2085	}
2086	2086
2087	2087	static READ8_HANDLER( sms_vdp_2_ctrl_r )
r2864	r2865
2210	2210	init_ports_systeme(machine);
2211	2211	}
2212	2212
2213		void init_for_megadrive(void)
	2213	void init_for_megadrive(running_machine *machine)
2214	2214	{
2215		md_sms_vdp = start_vdp(Machine, GEN_VDP);
	2215	md_sms_vdp = start_vdp(machine, GEN_VDP);
2216	2216	md_sms_vdp->set_irq = sms_vdp_cpu1_irq_callback;
2217	2217	md_sms_vdp->is_pal = 0;
2218	2218	md_sms_vdp->sms_total_scanlines = 262;

src/mame/drivers/fantland.c
r2864	r2865
178	178	static int old_x[2], old_y[2], old_f[2];
179	179	static UINT8 ret[2];
180	180
181		switch (input_port_read~~_indexed~~(machine, 7) & 0x03)
	181	switch (input_port_read(machine, "Controls") & 0x03)
182	182	{
183	183	case 3:
184		case 1: return input_port_read_indexed(machine, 0 + offset); // Lightgun buttons
185		case 2: return input_port_read_indexed(machine, 4 + offset); // Joystick
	184	case 1: return input_port_read(machine, offset ? "IN1" : "IN0"); // Lightgun buttons
	185	case 2: return input_port_read(machine, offset ? "IN5" : "IN4"); // Joystick
186	186	}
187	187
188	188	// Trackball
189	189
190		x = input_port_read_indexed(machine, 13 + offset * 2);
191		y = input_port_read_indexed(machine, 12 + offset * 2);
	190	x = input_port_read(machine, offset ? "P2 Trackball X" : "P1 Trackball X");
	191	y = input_port_read(machine, offset ? "P2 Trackball Y" : "P1 Trackball Y");
192	192	f = video_screen_get_frame_number(machine->primary_screen);
193	193
194		ret[offset] = (ret[offset] & 0x14) \| (input_port_read~~_indexed~~(machine, ~~2 +~~ offset) & 0xc3);
	194	ret[offset] = (ret[offset] & 0x14) \| (input_port_read(machine, offset ? "IN3" : "IN2") & 0xc3);
195	195
196	196	x = (x & 0x7f) - (x & 0x80);
197	197	y = (y & 0x7f) - (y & 0x80);
r2864	r2865
221	221	AM_RANGE( 0x52000, 0x521ff ) AM_READWRITE( SMH_RAM, paletteram_xRRRRRGGGGGBBBBB_le_w ) AM_BASE( &paletteram )
222	222	AM_RANGE( 0x53000, 0x53001 ) AM_READWRITE( borntofi_inputs_r, borntofi_nmi_enable_w )
223	223	AM_RANGE( 0x53002, 0x53002 ) AM_READWRITE( input_port_6_r, fantland_soundlatch_w )
224		AM_RANGE( 0x53003, 0x53003 ) AM_READ( input~~_po~~r~~t_7_r~~ )
	224	AM_RANGE( 0x53003, 0x53003 ) AM_READ_PORT( "Controls" )
225	225
226	226	AM_RANGE( 0x54000, 0x567ff ) AM_RAM AM_BASE( &spriteram )
227	227
228		AM_RANGE( 0x57000, 0x57000 ) AM_READ( input_port_8_r )
229		AM_RANGE( 0x57001, 0x57001 ) AM_READ( input_port_9_r )
230		AM_RANGE( 0x57002, 0x57002 ) AM_READ( input_port_10_r )
231		AM_RANGE( 0x57003, 0x57003 ) AM_READ( input_port_11_r )
	228	AM_RANGE( 0x57000, 0x57000 ) AM_READ_PORT( "P1 Lightgun Y" )
	229	AM_RANGE( 0x57001, 0x57001 ) AM_READ_PORT( "P1 Lightgun X" )
	230	AM_RANGE( 0x57002, 0x57002 ) AM_READ_PORT( "P2 Lightgun Y" )
	231	AM_RANGE( 0x57003, 0x57003 ) AM_READ_PORT( "P2 Lightgun X" )
232	232
233	233	AM_RANGE( 0x60000, 0x6ffff ) AM_RAM AM_BASE( &spriteram_2 )
234	234
r2864	r2865
405	405	***************************************************************************/
406	406
407	407	static INPUT_PORTS_START( fantland )
408		PORT_START /* IN0 - a3000 */
	408	PORT_START_TAG("a3000") /* IN0 - a3000 */
409	409	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
410	410	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START1 )
411	411	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
r2864	r2865
425	425	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
426	426	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
427	427
428		PORT_START /* IN2 - a3002 */
	428	PORT_START_TAG("a3002") /* IN2 - a3002 */
429	429	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) )
430	430	PORT_DIPSETTING( 0x0001, DEF_STR( 4C_1C ) )
431	431	PORT_DIPSETTING( 0x0002, DEF_STR( 3C_1C ) )
r2864	r2865
554	554	***************************************************************************/
555	555
556	556	static INPUT_PORTS_START( borntofi )
557		PORT_START /* IN0 - 53000 (Lightgun) */
	557	PORT_START_TAG("IN0") /* IN0 - 53000 (Lightgun) */
558	558	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
559	559	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START1 )
560	560	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 )
r2864	r2865
564	564	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
565	565	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
566	566
567		PORT_START /* IN1 - 53001 (Lightgun) */
	567	PORT_START_TAG("IN1") /* IN1 - 53001 (Lightgun) */
568	568	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN2 )
569	569	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
570	570	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
r2864	r2865
574	574	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
575	575	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
576	576
577		PORT_START /* IN2 - 53000 (Trackball) */
	577	PORT_START_TAG("IN2") /* IN2 - 53000 (Trackball) */
578	578	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
579	579	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START1 )
580	580	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SPECIAL ) // trackball x
r2864	r2865
584	584	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 )
585	585	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 )
586	586
587		PORT_START /* IN3 - 53001 (Trackball) */
	587	PORT_START_TAG("IN3") /* IN3 - 53001 (Trackball) */
588	588	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN2 )
589	589	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
590	590	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SPECIAL ) // trackball x
r2864	r2865
594	594	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
595	595	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
596	596
597		PORT_START /* IN4 - 53000 (Joystick) */
	597	PORT_START_TAG("IN4") /* IN4 - 53000 (Joystick) */
598	598	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
599	599	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START1 )
600	600	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
r2864	r2865
604	604	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 )
605	605	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 )
606	606
607		PORT_START /* IN5 - 53001 (Joystick) */
	607	PORT_START_TAG("IN5") /* IN5 - 53001 (Joystick) */
608	608	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN2 )
609	609	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
610	610	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
r2864	r2865
614	614	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
615	615	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
616	616
617		PORT_START /* IN6 - 53002 */
	617	PORT_START_TAG("IN6") /* IN6 - 53002 */
618	618	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
619	619	PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
620	620	PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
r2864	r2865
662	662	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
663	663	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
664	664
665		PORT_START_TAG("P1 Lightgun Y") /* IN8 - 57000 */
	665	PORT_START_TAG("P1 Lightgun Y") /* IN8 - 57000 */
666	666	PORT_BIT( 0xff, 0xb0, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, (352.0 - 12) / 352, 12.0 / 352, 0) PORT_MINMAX(0x80,0xfc) PORT_SENSITIVITY(100) PORT_KEYDELTA(5) PORT_PLAYER(1)
667	667
668		PORT_START_TAG("P1 Lightgun X") /* IN9 - 57001 */
	668	PORT_START_TAG("P1 Lightgun X") /* IN9 - 57001 */
669	669	PORT_BIT( 0xff, 0x60, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_MINMAX(0x07,0xb7) PORT_SENSITIVITY(100) PORT_KEYDELTA(5) PORT_PLAYER(1)
670	670
671		PORT_START_TAG("P2 Lightgun Y") /* IN10 - 57002 */
	671	PORT_START_TAG("P2 Lightgun Y") /* IN10 - 57002 */
672	672	PORT_BIT( 0xff, 0xb0, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, (352.0 - 12) / 352, 12.0 / 352, 0) PORT_MINMAX(0x80,0xfc) PORT_SENSITIVITY(100) PORT_KEYDELTA(5) PORT_PLAYER(2)
673	673
674		PORT_START_TAG("P2 Lightgun X") /* IN11 - 57003 */
	674	PORT_START_TAG("P2 Lightgun X") /* IN11 - 57003 */
675	675	PORT_BIT( 0xff, 0x70, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_MINMAX(0x07,0xb7) PORT_SENSITIVITY(100) PORT_KEYDELTA(5) PORT_PLAYER(2)
676	676
677		PORT_START /* IN12 - 53000 */
	677	PORT_START_TAG("P1 Trackball Y") /* IN12 - 53000 */
678	678	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(10) PORT_KEYDELTA(5) PORT_PLAYER(1) PORT_RESET
679	679
680		PORT_START /* IN13 - 53000 */
	680	PORT_START_TAG("P1 Trackball X") /* IN13 - 53000 */
681	681	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(10) PORT_KEYDELTA(5) PORT_PLAYER(1) PORT_RESET
682	682
683		PORT_START /* IN14 - 53001 */
	683	PORT_START_TAG("P2 Trackball Y") /* IN14 - 53001 */
684	684	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(10) PORT_KEYDELTA(5) PORT_PLAYER(2)
685	685
686		PORT_START /* IN15 - 53001 */
	686	PORT_START_TAG("P2 Trackball X") /* IN15 - 53001 */
687	687	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(10) PORT_KEYDELTA(5) PORT_PLAYER(2)
688	688	INPUT_PORTS_END
689	689
r2864	r2865
695	695	static CUSTOM_INPUT( wheelrun_wheel_r )
696	696	{
697	697	int player = (FPTR)param;
698		int delta = input_port_read~~_indexed~~(field->port->machine, ~~4 +~~ player);
	698	int delta = input_port_read(field->port->machine, player ? "WHEEL1" : "WHEEL0");
699	699	delta = (delta & 0x7f) - (delta & 0x80) + 4;
700	700
701	701	if (delta > 7) delta = 7;
r2864	r2865
706	706	}
707	707
708	708	static INPUT_PORTS_START( wheelrun )
709		PORT_START /* IN0 - 53000 */
	709	PORT_START_TAG("53000") /* IN0 - 53000 */
710	710	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
711	711	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
712	712	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
714	714	PORT_BIT( 0x70, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(wheelrun_wheel_r, (void *)0)
715	715	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
716	716
717		PORT_START /* IN1 - 53001 */
	717	PORT_START_TAG("53001") /* IN1 - 53001 */
718	718	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN2 )
719	719	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
720	720	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
722	722	PORT_BIT( 0x70, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(wheelrun_wheel_r, (void *)1)
723	723	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
724	724
725		PORT_START /* IN2 - 53002 */
	725	PORT_START_TAG("53002") /* IN2 - 53002 */
726	726	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
727	727	PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
728	728	PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
r2864	r2865
745	745	PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
746	746	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
747	747
748		PORT_START /* IN3 - 53003 */
	748	PORT_START_TAG("53003") /* IN3 - 53003 */
749	749	PORT_DIPNAME( 0xff, 0xdf, "Wheel Sensitivity" )
750	750	PORT_DIPSETTING( 0x7f, "0" )
751	751	PORT_DIPSETTING( 0xbf, "1" )
r2864	r2865
756	756	PORT_DIPSETTING( 0xfd, "6" )
757	757	PORT_DIPSETTING( 0xfe, "7" )
758	758
759		PORT_START /* IN4 */
	759	PORT_START_TAG("WHEEL0") /* IN4 */
760	760	PORT_BIT( 0xff, 0, IPT_DIAL ) PORT_SENSITIVITY(25) PORT_KEYDELTA(10) PORT_RESET PORT_REVERSE PORT_PLAYER(1)
761		PORT_START /* IN5 */
	761	PORT_START_TAG("WHEEL1") /* IN5 */
762	762	PORT_BIT( 0xff, 0, IPT_DIAL ) PORT_SENSITIVITY(25) PORT_KEYDELTA(10) PORT_RESET PORT_REVERSE PORT_PLAYER(2)
763	763	INPUT_PORTS_END
764	764

src/mame/drivers/ksys573.c
r2864	r2865
301	301	switch (offset)
302	302	{
303	303	case 0:
304		data = input_port_read~~_indexed~~(machine, 0);
	304	data = input_port_read(machine, "IN0");
305	305	break;
306	306	case 1:
307	307	{
308		data = input_port_read~~_indexed~~(machine, 1);
	308	data = input_port_read(machine, "IN1");
309	309	data \|= 0x000000c0;
310	310
311	311	if( has_ds2401[ security_cart_number ] )
r2864	r2865
341	341	break;
342	342	}
343	343	case 2:
344		data = input_port_read~~_indexed~~(machine, 2);
	344	data = input_port_read(machine, "IN2");
345	345	break;
346	346	case 3:
347		data = input_port_read~~_indexed~~(machine, 3);
	347	data = input_port_read(machine, "IN3");
348	348	break;
349	349	}
350	350

src/mame/drivers/atarig1.c
r2864	r2865
964	964	state_save_register_postload(machine, pitfighb_state_postload, NULL);
965	965	}
966	966	else if (slapstic != 0)
967		atarigen_slapstic_init(0, slapstic_base, 0, slapstic);
	967	atarigen_slapstic_init(machine, 0, slapstic_base, 0, slapstic);
968	968	atarijsa_init(machine, 0, 0x4000);
969	969
970	970	atarig1_pitfight = is_pitfight;

src/mame/drivers/sbrkout.c
r2864	r2865
31	31	***************************************************************************/
32	32
33	33	#include "driver.h"
34		#include "deprecat.h"
35	34	#include "sound/dac.h"
36	35
37	36	#include "sbrkout.lh"
r2864	r2865
180	179	}
181	180
182	181
183		static void update_nmi_state(void)
	182	static void update_nmi_state(running_machine *machine)
184	183	{
185	184	if ((pot_trigger[0] & ~pot_mask[0]) \| (pot_trigger[1] & ~pot_mask[1]))
186		cpunum_set_input_line(Machine, 0, INPUT_LINE_NMI, ASSERT_LINE);
	185	cpunum_set_input_line(machine, 0, INPUT_LINE_NMI, ASSERT_LINE);
187	186	else
188		cpunum_set_input_line(Machine, 0, INPUT_LINE_NMI, CLEAR_LINE);
	187	cpunum_set_input_line(machine, 0, INPUT_LINE_NMI, CLEAR_LINE);
189	188	}
190	189
191	190
192	191	static TIMER_CALLBACK( pot_trigger_callback )
193	192	{
194	193	pot_trigger[param] = 1;
195		update_nmi_state();
	194	update_nmi_state(machine);
196	195	}
197	196
198	197
r2864	r2865
200	199	{
201	200	pot_mask[0] = ~offset & 1;
202	201	pot_trigger[0] = 0;
203		update_nmi_state();
	202	update_nmi_state(machine);
204	203	}
205	204
206	205
r2864	r2865
208	207	{
209	208	pot_mask[1] = ~offset & 1;
210	209	pot_trigger[1] = 0;
211		update_nmi_state();
	210	update_nmi_state(machine);
212	211	}
213	212
214	213

src/mame/drivers/segae.h
r2864	r2865
14	14	extern READ8_HANDLER( sms_vdp_ctrl_r );
15	15	extern WRITE8_HANDLER( sms_vdp_ctrl_w );
16	16
17		extern void init_for_megadrive(void);
	17	extern void init_for_megadrive(running_machine *machine);
18	18	extern void segae_md_sms_stop_scanline_timer(void);
19	19
20	20

src/mame/drivers/toobin.c
r2864	r2865
95	95
96	96	static READ16_HANDLER( special_port1_r )
97	97	{
98		int result = input_port_read~~_indexed~~(machine, 1);
	98	int result = input_port_read(machine, "FF9000");
99	99	if (atarigen_get_hblank(machine->primary_screen)) result ^= 0x8000;
100	100	if (atarigen_cpu_to_sound_ready) result ^= 0x2000;
101	101	return result;
r2864	r2865
151	151	*************************************/
152	152
153	153	static INPUT_PORTS_START( toobin )
154		PORT_START /* ff8800 */
	154	PORT_START_TAG("FF8800") /* ff8800 */
155	155	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P2 R Paddle Forward") PORT_CODE(KEYCODE_L) PORT_PLAYER(2)
156	156	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("P2 L Paddle Forward") PORT_CODE(KEYCODE_J) PORT_PLAYER(2)
157	157	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("P2 L Paddle Backward") PORT_CODE(KEYCODE_U) PORT_PLAYER(2)
r2864	r2865
164	164	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P2 Throw") PORT_CODE(KEYCODE_RCONTROL) PORT_PLAYER(2)
165	165	PORT_BIT( 0xfc00, IP_ACTIVE_LOW, IPT_UNUSED )
166	166
167		PORT_START /* ff9000 */
	167	PORT_START_TAG("FF9000") /* ff9000 */
168	168	PORT_BIT( 0x03ff, IP_ACTIVE_LOW, IPT_UNUSED )
169	169	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNUSED )
170	170	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
617	617	static DRIVER_INIT( toobin )
618	618	{
619	619	atarigen_eeprom_default = NULL;
620		atarijsa_init(machine, 1, 0x1000);
	620	atarijsa_init(machine, "FF9000", 0x1000);
621	621	}
622	622
623	623

src/mame/drivers/overdriv.c
r2864	r2865
339	339	AM_RANGE(0x1000, 0xffff) AM_WRITE(SMH_ROM)
340	340	ADDRESS_MAP_END
341	341
	342	/* Both IPT_START1 assignments are needed. The game will reset during */
	343	/* the "continue" sequence if the assignment on the first port */
	344	/* is missing. */
342	345
343
344	346	static INPUT_PORTS_START( overdriv )
345	347	PORT_START
346	348	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_TOGGLE

src/mame/drivers/gsword.c
r2864	r2865
177	177	static int gsword_coins_in(void)
178	178	{
179	179	/* emulate 8741 coin slot */
180		if (input_port_read~~_indexed~~(machine, 4)&0xc0)
	180	if (input_port_read(machine, "IN4") & 0xc0)
181	181	{
182	182	logerror("Coin In\n");
183	183	return 0x80;
r2864	r2865
215	215	switch (offset)
216	216	{
217	217	case 0x01: /* start button , coins */
218		return input_port_read~~_indexed~~(machine, 0);
	218	return input_port_read(machine, "IN0");
219	219	case 0x02: /* Player 1 Controller */
220		return input_port_read~~_indexed~~(machine, 1);
	220	return input_port_read(machine, "IN1");
221	221	case 0x04: /* Player 2 Controller */
222		return input_port_read~~_indexed~~(machine, 3);
	222	return input_port_read(machine, "IN3");
223	223	// default:
224	224	// logerror("8741-2 unknown read %d PC=%04x\n",offset,activecpu_get_pc());
225	225	}
r2864	r2865
232	232	switch (offset)
233	233	{
234	234	case 0x01: /* start button */
235		return input_port_read~~_indexed~~(machine, 2);
	235	return input_port_read(machine, "IN2");
236	236	case 0x02: /* Player 1 Controller? */
237		return input_port_read~~_indexed~~(machine, 1);
	237	return input_port_read(machine, "IN1");
238	238	case 0x04: /* Player 2 Controller? */
239		return input_port_read~~_indexed~~(machine, 3);
	239	return input_port_read(machine, "IN3");
240	240	}
241	241	/* unknown */
242	242	// logerror("8741-3 unknown read %d PC=%04x\n",offset,activecpu_get_pc());
r2864	r2865
422	422	AM_RANGE(0x4000, 0x43ff) AM_RAM AM_BASE(&gsword_cpu2_ram)
423	423
424	424	/* 8000 to 8003 looks MCU */
425		AM_RANGE(0x8000, 0x8000) AM_READ(input_port_1_r) // 1PL
426		AM_RANGE(0x8001, 0x8001) AM_READ(input_port_2_r) // 2PL / ACK
427		AM_RANGE(0x8002, 0x8002) AM_READ(input_port_0_r) // START
	425	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("IN1") // 1PL
	426	AM_RANGE(0x8001, 0x8001) AM_READ_PORT("IN2") // 2PL / ACK
	427	AM_RANGE(0x8002, 0x8002) AM_READ_PORT("IN0") // START
428	428
429	429	// AM_RANGE(0x6000, 0x6000) AM_WRITE(adpcm_soundcommand_w)
430	430	AM_RANGE(0xA000, 0xA001) AM_WRITE(josvolly_8741_1_w) AM_READ(josvolly_8741_1_r)
r2864	r2865
443	443	ADDRESS_MAP_END
444	444
445	445	static INPUT_PORTS_START( gsword )
446		PORT_START /* IN0 (8741-2 port1?) */
	446	PORT_START_TAG("IN0") /* IN0 (8741-2 port1?) */
447	447	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
448	448	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
449	449	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
452	452	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
453	453	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
454	454	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
455		PORT_START /* IN1 (8741-2 port2?) */
	455
	456	PORT_START_TAG("IN1") /* IN1 (8741-2 port2?) */
456	457	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_2WAY
457	458	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_2WAY
458	459	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
461	462	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 )
462	463	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
463	464	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
464		PORT_START /* IN2 (8741-3 port1?) */
	465
	466	PORT_START_TAG("IN2") /* IN2 (8741-3 port1?) */
465	467	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
466	468	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
467	469	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
469	471	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
470	472	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
471	473	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
472		PORT_START /* IN3 (8741-3 port2?) */
	474
	475	PORT_START_TAG("IN3") /* IN3 (8741-3 port2?) */
473	476	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_2WAY PORT_COCKTAIL
474	477	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_2WAY PORT_COCKTAIL
475	478	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
478	481	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_COCKTAIL
479	482	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
480	483	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
481		PORT_START /* IN4 (coins) */
	484
	485	PORT_START_TAG("IN4") /* IN4 (coins) */
482	486	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
483	487	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN )
484	488	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
r2864	r2865
488	492	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
489	493	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(1)
490	494
491		PORT_START /* DSW0 */
	495	PORT_START_TAG("DSW0") /* DSW0 */
492	496	/* NOTE: Switches 0 & 1, 6,7,8 not used */
493	497	/* Coins configurations were handled */
494	498	/* via external hardware & not via program */
r2864	r2865
501	505	PORT_DIPSETTING( 0x08, DEF_STR( 1C_4C ) )
502	506	PORT_DIPSETTING( 0x0c, DEF_STR( 1C_5C ) )
503	507
504		PORT_START /* DSW1 */
	508	PORT_START_TAG("DSW1") /* DSW1 */
505	509	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unused ) )
506	510	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
507	511	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
526	530	PORT_DIPSETTING( 0x00, "1" )
527	531	PORT_DIPSETTING( 0x80, "255 (Cheat)" )
528	532
529		PORT_START /* DSW2 */
	533	PORT_START_TAG("DSW2") /* DSW2 */
530	534	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unused ) )
531	535	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
532	536	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
553	557	INPUT_PORTS_END
554	558
555	559	static INPUT_PORTS_START( josvolly )
556		PORT_START /* IN0 */
	560	PORT_START_TAG("IN0") /* IN0 */
557	561	PORT_BIT( 0x01, IP_ACTIVE_LOW , IPT_START2 )
558	562	PORT_BIT( 0x02, IP_ACTIVE_LOW , IPT_START1 )
559	563	PORT_BIT( 0x04, IP_ACTIVE_LOW , IPT_COIN2 ) PORT_IMPULSE(1)
r2864	r2865
563	567	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
564	568	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
565	569
566		PORT_START /* IN1 */
	570	PORT_START_TAG("IN1") /* IN1 */
567	571	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
568	572	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
569	573	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
r2864	r2865
573	577	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
574	578	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
575	579
576		PORT_START /* IN2 */
	580	PORT_START_TAG("IN2") /* IN2 */
577	581	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
578	582	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
579	583	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
r2864	r2865
583	587	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
584	588	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
585	589
586		PORT_START /* DSW1 */
	590	PORT_START_TAG("DSW1") /* DSW1 */
587	591	PORT_DIPNAME( 0x0c, 0x00, "DIP1-0c(982E)" )
588	592	PORT_DIPSETTING( 0x0c, "0" )
589	593	PORT_DIPSETTING( 0x08, "1" )
r2864	r2865
601	605	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
602	606	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
603	607
604		PORT_START /* DSW2 */
	608	PORT_START_TAG("DSW2") /* DSW2 */
605	609	// PORT_DIPNAME( 0x01, 0x00, "DSW2-0" )
606	610	// PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
607	611	// PORT_DIPSETTING( 0x01, DEF_STR( On ) )

src/mame/drivers/lethal.c
r2864	r2865
176	176	#define SOUND_CLOCK XTAL_18_432MHz
177	177
178	178
179		#define GUNX( a ) (( ( input_port_read_indexed(machine, a ) * 287 ) / 0xff ) + 16)
180		#define GUNY( a ) (( ( input_port_read_indexed(machine, a ) * 223 ) / 0xff ) + 10)
	179	static const char *gunnames[] = { "LIGHT0_X", "LIGHT0_Y", "LIGHT1_X", "LIGHT1_Y" };
181	180
	181	/* a = 1, 2 = player # */
	182	#define GUNX( a ) (( ( input_port_read(machine, gunnames[2 * (a - 1)]) * 287 ) / 0xff ) + 16)
	183	#define GUNY( a ) (( ( input_port_read(machine, gunnames[2 * (a - 1) + 1]) * 223 ) / 0xff ) + 10)
	184
182	185	VIDEO_START(lethalen);
183	186	VIDEO_UPDATE(lethalen);
184	187	WRITE8_HANDLER(lethalen_palette_control);
r2864	r2865
229	232
230	233	static READ8_HANDLER( control2_r )
231	234	{
232		return 0x02 \| eeprom_read_bit() \| (input_port_read~~_indexed~~(machine, 1) & 0xf0);
	235	return 0x02 \| eeprom_read_bit() \| (input_port_read(machine, "IN1") & 0xf0);
233	236	}
234	237
235	238	static WRITE8_HANDLER( control2_w )
r2864	r2865
455	458	switch (offset)
456	459	{
457	460	case 0:
458		return GUNX(2)>>1;
	461	return GUNX(1)>>1;
459	462	break;
460	463	case 1:
461		if ((240-GUNY(3)) == 7)
	464	if ((240-GUNY(1)) == 7)
462	465	return 0;
463	466	else
464		return (240-GUNY(3));
	467	return (240-GUNY(1));
465	468	break;
466	469	case 2:
467		return GUNX(4)>>1;
	470	return GUNX(2)>>1;
468	471	break;
469	472	case 3:
470		if ((240-GUNY(5)) == 7)
	473	if ((240-GUNY(2)) == 7)
471	474	return 0;
472	475	else
473		return (240-GUNY(5));
	476	return (240-GUNY(2));
474	477	break;
475	478	}
476	479
r2864	r2865
481	484	{
482	485	int res = 0;
483	486
484		if (GUNX(2) & 1) res \|= 0x80;
485		if (GUNX(4) & 1) res \|= 0x40;
	487	if (GUNX(1) & 1) res \|= 0x80;
	488	if (GUNX(2) & 1) res \|= 0x40;
486	489
487	490	return res;
488	491	}
r2864	r2865
499	502	AM_RANGE(0x40c8, 0x40d0) AM_WRITE(lethalen_palette_control) // PCU1-PCU3 on the schematics
500	503	AM_RANGE(0x40d4, 0x40d7) AM_READ(guns_r)
501	504	AM_RANGE(0x40d8, 0x40d8) AM_READ(control2_r)
502		AM_RANGE(0x40d9, 0x40d9) AM_READ~~(input~~_~~port_~~0_r)
	505	AM_RANGE(0x40d9, 0x40d9) AM_READ_PORT("IN0")
503	506	AM_RANGE(0x40db, 0x40db) AM_READ(gunsaux_r) // top X bit of guns
504	507	AM_RANGE(0x40dc, 0x40dc) AM_WRITE(le_bankswitch_w)
505	508	AM_RANGE(0x47fe, 0x47ff) AM_WRITE(le_bgcolor_w) // BG color
r2864	r2865
520	523
521	524	static INPUT_PORTS_START( lethalen )
522	525	/* IN 0 */
523		PORT_START
	526	PORT_START_TAG("IN0")
524	527	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
525	528	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
526	529	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
531	534	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
532	535
533	536	/* IN 1 */
534		PORT_START
	537	PORT_START_TAG("IN1")
535	538	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
536	539	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
537	540	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
538	541	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
539		PORT_DIPNAME( 0x10, 0x10, DEF_STR(Language) )
540		PORT_DIPSETTING( 0x10, DEF_STR(English) )
541		PORT_DIPSETTING( 0x00, DEF_STR(Spanish) )
	542	PORT_DIPNAME( 0x10, 0x10, DEF_STR(Language) )
	543	PORT_DIPSETTING( 0x10, DEF_STR(English) )
	544	PORT_DIPSETTING( 0x00, DEF_STR(Spanish) )
542	545	PORT_DIPNAME( 0x20, 0x00, "Game Type" )
543	546	PORT_DIPSETTING( 0x20, "Street" )
544	547	PORT_DIPSETTING( 0x00, "Arcade" )
r2864	r2865
550	553	PORT_DIPSETTING( 0x0080, DEF_STR( Stereo ) )
551	554
552	555	/* IN 2 */
553		PORT_START
	556	PORT_START_TAG("LIGHT0_X")
554	557	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(25) PORT_KEYDELTA(15) PORT_PLAYER(1)
555	558
556	559	/* IN 3 */
557		PORT_START
	560	PORT_START_TAG("LIGHT0_Y")
558	561	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, -1.0, 0.0, 0) PORT_SENSITIVITY(25) PORT_KEYDELTA(15) PORT_PLAYER(1)
559	562
560	563	/* IN 4 */
561		PORT_START
	564	PORT_START_TAG("LIGHT1_X")
562	565	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(25) PORT_KEYDELTA(15) PORT_PLAYER(2)
563	566
564	567	/* IN 5 */
565		PORT_START
	568	PORT_START_TAG("LIGHT1_Y")
566	569	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, -1.0, 0.0, 0) PORT_SENSITIVITY(25) PORT_KEYDELTA(15) PORT_PLAYER(2)
567	570	INPUT_PORTS_END
568	571
569	572	static INPUT_PORTS_START( lethalej )
570	573	/* IN 0 */
571		PORT_START
	574	PORT_START_TAG("IN0")
572	575	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
573	576	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
574	577	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
579	582	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
580	583
581	584	/* IN 1 */
582		PORT_START
	585	PORT_START_TAG("IN1")
583	586	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
584	587	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
585	588	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
598	601	PORT_DIPSETTING( 0x0080, DEF_STR( Stereo ) )
599	602
600	603	/* IN 2 */
601		PORT_START
	604	PORT_START_TAG("LIGHT0_X")
602	605	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, -1.0, 0.0, 0) PORT_SENSITIVITY(25) PORT_KEYDELTA(15) PORT_PLAYER(1) PORT_REVERSE
603	606
604	607	/* IN 3 */
605		PORT_START
	608	PORT_START_TAG("LIGHT0_Y")
606	609	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, -1.0, 0.0, 0) PORT_SENSITIVITY(25) PORT_KEYDELTA(15) PORT_PLAYER(1) PORT_REVERSE
607	610
608	611	/* IN 4 */
609		PORT_START
	612	PORT_START_TAG("LIGHT1_X")
610	613	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, -1.0, 0.0, 0) PORT_SENSITIVITY(25) PORT_KEYDELTA(15) PORT_PLAYER(2) PORT_REVERSE
611	614
612	615	/* IN 5 */
613		PORT_START
	616	PORT_START_TAG("LIGHT1_Y")
614	617	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, -1.0, 0.0, 0) PORT_SENSITIVITY(25) PORT_KEYDELTA(15) PORT_PLAYER(2) PORT_REVERSE
615	618	INPUT_PORTS_END
616	619

src/mame/drivers/exprraid.c
r2864	r2865
104	104
105	105	static READ8_HANDLER( vblank_r )
106	106	{
107		return input_port_read~~_indexed~~(machine, 0 );
	107	return input_port_read(machine, "IN0");
108	108	}
109	109
110	110	static ADDRESS_MAP_START( master_map, ADDRESS_SPACE_PROGRAM, 8 )
r2864	r2865
115	115	AM_RANGE(0x0c00, 0x0fff) AM_RAM_WRITE(exprraid_colorram_w) AM_BASE(&colorram)
116	116	AM_RANGE(0x1317, 0x1317) AM_READNOP // ???
117	117	AM_RANGE(0x1700, 0x1700) AM_READNOP // ???
118		AM_RANGE(0x1800, 0x1800) AM_READ(input_port_1_r) /* DSW 0 */
119		AM_RANGE(0x1801, 0x1801) AM_READ(input_port_2_r) /* Controls */
120		AM_RANGE(0x1802, 0x1802) AM_READ(input_port_3_r) /* Coins */
121		AM_RANGE(0x1803, 0x1803) AM_READ(input_port_4_r) /* DSW 1 */
	118	AM_RANGE(0x1800, 0x1800) AM_READ_PORT("DSW0") /* DSW 0 */
	119	AM_RANGE(0x1801, 0x1801) AM_READ_PORT("IN1") /* Controls */
	120	AM_RANGE(0x1802, 0x1802) AM_READ_PORT("IN2") /* Coins */
	121	AM_RANGE(0x1803, 0x1803) AM_READ_PORT("DSW1") /* DSW 1 */
122	122	AM_RANGE(0x2000, 0x2000) AM_WRITENOP // ???
123	123	AM_RANGE(0x2001, 0x2001) AM_WRITE(sound_cpu_command_w)
124	124	AM_RANGE(0x2002, 0x2002) AM_WRITE(exprraid_flipscreen_w)
r2864	r2865
143	143
144	144
145	145	static INPUT_PORTS_START( exprraid )
146		PORT_START /* IN 0 - 0x3800 */
	146	PORT_START_TAG("IN0") /* IN 0 - 0x3800 */
147	147	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_VBLANK )
148	148
149		PORT_START /* DSW 0 - 0x1800 */
	149	PORT_START_TAG("DSW0") /* DSW 0 - 0x1800 */
150	150	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
151	151	PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
152	152	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
r2864	r2865
166	166	PORT_DIPSETTING( 0x40, DEF_STR( Cocktail ) )
167	167	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
168	168
169		PORT_START /* IN 1 - 0x1801 */
	169	PORT_START_TAG("IN1") /* IN 1 - 0x1801 */
170	170	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
171	171	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
172	172	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
r2864	r2865
176	176	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
177	177	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
178	178
179		PORT_START /* IN 2 - 0x1802 */
	179	PORT_START_TAG("IN2") /* IN 2 - 0x1802 */
180	180	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
181	181	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
182	182	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
r2864	r2865
186	186	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
187	187	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
188	188
189		PORT_START /* IN 3 - 0x1803 */
	189	PORT_START_TAG("DSW1") /* IN 3 - 0x1803 */
190	190	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )
191	191	PORT_DIPSETTING( 0x01, "1" )
192	192	PORT_DIPSETTING( 0x03, "3" )
r2864	r2865
287	287	{
288	288	static int coin = 0;
289	289
290		if ( ( ~input_port_read_indexed(machine, 3 ) ) & 0xc0 ) {
291		if ( coin == 0 ) {
	290	if ((~input_port_read(machine, "IN2")) & 0xc0 )
	291	{
	292	if ( coin == 0 )
	293	{
292	294	coin = 1;
293	295	cpunum_set_input_line(machine, 0, INPUT_LINE_NMI, PULSE_LINE);
294	296	}
295		} else
	297	}
	298	else
296	299	coin = 0;
297	300	}
298	301

src/mame/drivers/taitowlf.c
r2864	r2865
692	692	{
693	693	bios_ram = auto_malloc(0x10000);
694	694
695		init_pc_common(PCCOMMON_KEYBOARD_AT, taitowlf_set_keyb_int);
	695	init_pc_common(machine, PCCOMMON_KEYBOARD_AT, taitowlf_set_keyb_int);
696	696	mc146818_init(MC146818_STANDARD);
697	697
698	698	intel82439tx_init();

src/mame/drivers/gunbustr.c
r2864	r2865
91	91	{
92	92	case 0x00:
93	93	{
94		return (input_port_read_indexed(machine,0) << 16) \| input_port_read_indexed(machine,1) \|
95		(eeprom_read_bit() << 7);
	94	return (input_port_read(machine, "IN0") << 16) \| input_port_read(machine, "IN1") \| (eeprom_read_bit() << 7);
96	95	}
97	96
98	97	case 0x01:
99	98	{
100		return input_port_read~~_indexed~~(machine,2) \| (coin_word << 16);
	99	return input_port_read(machine, "IN2") \| (coin_word << 16);
101	100	}
102	101	}
103	102	logerror("CPU #0 PC %06x: read input %06x\n",activecpu_get_pc(),offset);
r2864	r2865
174	173
175	174	static READ32_HANDLER( gunbustr_gun_r )
176	175	{
177		return ( input_port_read_indexed(machine,3) << 24) \| (input_port_read_indexed(machine,4) << 16) \|
178		( input_port_read_indexed(machine,5) << 8) \| input_port_read_indexed(machine,6);
	176	return ( input_port_read(machine, "LIGHT0_X") << 24) \| (input_port_read(machine, "LIGHT0_Y") << 16) \|
	177	( input_port_read(machine, "LIGHT1_X") << 8) \| input_port_read(machine, "LIGHT1_Y");
179	178	}
180	179
181	180	static WRITE32_HANDLER( gunbustr_gun_w )
r2864	r2865
221	220	***********************************************************/
222	221
223	222	static INPUT_PORTS_START( gunbustr )
224		PORT_START /* IN0 */
	223	PORT_START_TAG("IN0") /* IN0 */
225	224	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
226	225	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
227	226	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
239	238	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
240	239	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
241	240
242		PORT_START /* IN1 */
	241	PORT_START_TAG("IN1") /* IN1 */
243	242	PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(1) /* Freeze input */
244	243	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
245	244	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
257	256	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
258	257	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
259	258
260		PORT_START /* IN2 */
	259	PORT_START_TAG("IN2") /* IN2 */
261	260	PORT_SERVICE_NO_TOGGLE( 0x0001, IP_ACTIVE_LOW )
262	261	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SERVICE1 )
263	262	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
277	276
278	277	/* Light gun inputs */
279	278
280		PORT_START /* IN 3, P1X */
	279	PORT_START_TAG("LIGHT0_X") /* IN 3, P1X */
281	280	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_PLAYER(1)
282	281
283		PORT_START /* IN 4, P1Y */
	282	PORT_START_TAG("LIGHT0_Y") /* IN 4, P1Y */
284	283	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_REVERSE PORT_PLAYER(1)
285	284
286		PORT_START /* IN 5, P2X */
	285	PORT_START_TAG("LIGHT1_X") /* IN 5, P2X */
287	286	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_PLAYER(2)
288	287
289		PORT_START /* IN 6, P2Y */
	288	PORT_START_TAG("LIGHT1_Y") /* IN 6, P2Y */
290	289	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_REVERSE PORT_PLAYER(2)
291	290	INPUT_PORTS_END
292	291

src/mame/drivers/taito_z.c
r2864	r2865
771	771	***************************************************************************/
772	772
773	773	#include "driver.h"
774		#include "deprecat.h"
775	774	#include "cpu/m68000/m68000.h"
776	775	#include "machine/eeprom.h"
777	776	#include "video/taitoic.h"
r2864	r2865
820	819	COMBINE_DATA(&taitoz_sharedram[offset]);
821	820	}
822	821
823		static void parse_control(void)
	822	static void parse_control(running_machine *machine)
824	823	{
825	824	/* bit 0 enables cpu B */
826	825	/* however this fails when recovering from a save state
827	826	if cpu B is disabled !! */
828		cpunum_set_input_line(Machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
	827	cpunum_set_input_line(machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
829	828
830	829	}
831	830
832		static void parse_control_noz80(void)
	831	static void parse_control_noz80(running_machine *machine)
833	832	{
834	833	/* bit 0 enables cpu B */
835	834	/* however this fails when recovering from a save state
836	835	if cpu B is disabled !! */
837		cpunum_set_input_line(Machine, 1, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
	836	cpunum_set_input_line(machine, 1, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
838	837
839	838	}
840	839
r2864	r2865
844	843	data = data >> 8; /* for Wgp */
845	844	cpua_ctrl = data;
846	845
847		parse_control();
	846	parse_control(machine);
848	847
849	848	// Chase HQ: handle the lights
850	849	if ((!strcmp(machine->gamedrv->name, "chasehq")) \|\| (!strcmp(machine->gamedrv->name, "chasehqj")))
r2864	r2865
862	861	data = data >> 8; /* for Wgp */
863	862	cpua_ctrl = data;
864	863
865		parse_control_noz80();
	864	parse_control_noz80(machine);
866	865
867	866	logerror("CPU #0 PC %06x: write %04x to cpu control\n",activecpu_get_pc(),data);
868	867	}
r2864	r2865
1426	1425
1427	1426	static STATE_POSTLOAD( taitoz_postload )
1428	1427	{
1429		parse_control();
	1428	parse_control(machine);
1430	1429	reset_sound_region();
1431	1430	}
1432	1431
r2864	r2865
4340	4339
4341	4340	static STATE_POSTLOAD( bshark_postload )
4342	4341	{
4343		parse_control_noz80();
	4342	parse_control_noz80(machine);
4344	4343	}
4345	4344
4346	4345	static DRIVER_INIT( bshark )

src/mame/drivers/lastfght.c
r2864	r2865
109	109	{
110	110	for ( x = 0; x < 512; x++ )
111	111	{
112		data = ( ((count&0xf)==0)&&((count&0x1e00)==0) )? get_white_pen(Machine) : gfxdata[count]; // white grid or data
	112	data = ( ((count&0xf)==0)&&((count&0x1e00)==0) )? get_white_pen(screen->machine) : gfxdata[count]; // white grid or data
113	113	*BITMAP_ADDR16(bitmap, y, x) = data;
114	114	count++;
115	115	}
r2864	r2865
306	306	{
307	307	// high byte:
308	308	// mask 0x1c: from sound?
309		return (mame_rand(machine) & 0x1c00) \| input_port_read~~_indexed~~(machine, 0);
	309	return (mame_rand(machine) & 0x1c00) \| input_port_read(machine, "IN0");
310	310	}
311	311
312	312	static READ16_HANDLER( lastfght_c00004_r )
313	313	{
314		return input_port_read~~_indexed~~(machine, 1);
	314	return input_port_read(machine, "IN1");
315	315	}
316	316
317	317	static READ16_HANDLER( lastfght_c00006_r )
r2864	r2865
319	319	// low byte:
320	320	// bit 7 = protection?
321	321	// bit 5 = blitter?
322		return input_port_read~~_indexed~~(machine, 2);
	322	return input_port_read(machine, "IN2");
323	323	}
324	324
325	325	static WRITE16_HANDLER( lastfght_c00006_w )
r2864	r2865
384	384	***************************************************************************/
385	385
386	386	static INPUT_PORTS_START( lastfght )
387		PORT_START // IN0 - c00002&3
	387	PORT_START_TAG("IN0") /* IN0 - c00002&3 */
388	388	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE1 )
389	389	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
390	390	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Reset") PORT_CODE(KEYCODE_F1)
r2864	r2865
403	403	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
404	404	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
405	405
406		PORT_START // IN1 - c00004&5
	406	PORT_START_TAG("IN1") /* IN1 - c00004&5 */
407	407	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 )
408	408	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 )
409	409	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
422	422	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_COIN1 )
423	423	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_COIN2 )
424	424
425		PORT_START // IN2 - c00006&7
	425	PORT_START_TAG("IN2") /* IN2 - c00006&7 */
426	426	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
427	427	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
428	428	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )

src/mame/drivers/embargo.c
r2864	r2865
58	58
59	59	static READ8_HANDLER( input_port_bit_r )
60	60	{
61		return (input_port_read~~_indexed~~(machine, 1) << (7 - input_select)) & 0x80;
	61	return (input_port_read(machine, "IN1") << (7 - input_select)) & 0x80;
62	62	}
63	63
64	64
r2864	r2865
82	82
83	83	if (dial_enable_1 && !dial_enable_2)
84	84	{
85		lo = input_port_read_indexed(machine, 3);
86		hi = input_port_read_indexed(machine, 4);
	85	lo = input_port_read(machine, "DIAL0");
	86	hi = input_port_read(machine, "DIAL1");
87	87	}
88	88
89	89	if (dial_enable_2 && !dial_enable_1)
90	90	{
91		lo = input_port_read_indexed(machine, 5);
92		hi = input_port_read_indexed(machine, 6);
	91	lo = input_port_read(machine, "DIAL2");
	92	hi = input_port_read(machine, "DIAL3");
93	93	}
94	94
95	95	lo = 12 * lo / 256;
r2864	r2865
185	185
186	186	static INPUT_PORTS_START( embargo )
187	187
188		PORT_START /* port 0x01 */
	188	PORT_START_TAG("IN0") /* port 0x01 */
189	189	PORT_DIPNAME( 0x03, 0x00, "Rounds" )
190	190	PORT_DIPSETTING( 0x00, "3" )
191	191	PORT_DIPSETTING( 0x01, "4" )
192	192	PORT_DIPSETTING( 0x02, "5" )
193	193	PORT_DIPSETTING( 0x03, "6" )
194	194
195		PORT_START /* S2650_CONTROL_PORT */
	195	PORT_START_TAG("IN1") /* S2650_CONTROL_PORT */
196	196	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
197	197	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
198	198	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 )
r2864	r2865
202	202	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
203	203	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
204	204
205		PORT_START /* S2650_DATA_PORT */
	205	PORT_START_TAG("IN2") /* S2650_DATA_PORT */
206	206	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN1 )
207	207
208		PORT_START
	208	PORT_START_TAG("DIAL0")
209	209	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(8) PORT_PLAYER(1)
210	210
211		PORT_START
	211	PORT_START_TAG("DIAL1")
212	212	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(8) PORT_PLAYER(2)
213	213
214		PORT_START
	214	PORT_START_TAG("DIAL2")
215	215	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(8) PORT_PLAYER(3)
216	216
217		PORT_START
	217	PORT_START_TAG("DIAL3")
218	218	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(8) PORT_PLAYER(4)
219	219
220	220	INPUT_PORTS_END

src/mame/drivers/cyberbal.c
r2864	r2865
995	995	static DRIVER_INIT( cyberbal )
996	996	{
997	997	atarigen_eeprom_default = default_eeprom;
998		atarigen_slapstic_init(0, 0x018000, 0, 0);
	998	atarigen_slapstic_init(machine, 0, 0x018000, 0, 0);
999	999	}
1000	1000
1001	1001
1002	1002	static DRIVER_INIT( cyberbt )
1003	1003	{
1004	1004	atarigen_eeprom_default = default_eeprom;
1005		atarigen_slapstic_init(0, 0x018000, 0, 116);
	1005	atarigen_slapstic_init(machine, 0, 0x018000, 0, 116);
1006	1006	}
1007	1007
1008	1008
1009	1009	static DRIVER_INIT( cyberb2p )
1010	1010	{
1011	1011	atarigen_eeprom_default = default_eeprom;
1012		atarijsa_init(machine, 2, 0x8000);
	1012	atarijsa_init(machine, "IN2", 0x8000);
1013	1013	}
1014	1014
1015	1015

src/mame/drivers/gijoe.c
r2864	r2865
96	96	/* bit 8 is EEPROM data */
97	97	/* bit 9 is EEPROM ready */
98	98	/* bit 11 is service button */
99		res = (eeprom_read_bit()<<8) \| input_port_read~~_indexed~~(machine,0);
	99	res = (eeprom_read_bit()<<8) \| input_port_read(machine, "IN0");
100	100
101	101	if (init_eeprom_count)
102	102	{
r2864	r2865
269	269	ADDRESS_MAP_END
270	270
271	271	static INPUT_PORTS_START( gijoe )
272		PORT_START
	272	PORT_START_TAG("IN0")
273	273	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_START1 )
274	274	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START2 )
275	275	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_START3 )
r2864	r2865
278	278	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_SPECIAL ) // EEPROM ready (always 1)
279	279	PORT_SERVICE_NO_TOGGLE( 0x0800, IP_ACTIVE_LOW )
280	280
281		PORT_START
	281	PORT_START_TAG("IN1")
282	282	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
283	283	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
284	284	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN3 )
r2864	r2865
288	288	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_SERVICE3 )
289	289	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_SERVICE4 )
290	290
291		PORT_START
	291	PORT_START_TAG("IN2")
292	292	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
293	293	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
294	294	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
310	310	PORT_DIPSETTING( 0x8000, "Common" )
311	311	PORT_DIPSETTING( 0x0000, "Independant" )
312	312
313		PORT_START
	313	PORT_START_TAG("IN3")
314	314	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
315	315	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
316	316	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)

src/mame/drivers/wilytowr.c
r2864	r2865
11	11	rely on vblank for timing. It all seems to be controlled by the CPU clock.
12	12	The NMI handler just handles the "Stop Mode" dip switch.
13	13
	14	Tomasz Slanina 2008.06.14:
	15	- Addedd sound emulation - atomboy and fghtbskt req different interrupt (T1)
	16	timing than wilytowr, otherwise music/fx tempo is too fast. Maybe both
	17	tmings are wrong - must be verified on real pcb.
	18	- Extra space in atomboy 2764 eproms is filled with garbage z80 code
	19	(taken from one of code roms, but from different offset)
	20	- Fghtbskt has one AY, but every frame writes 0 to 2nd AY regs - probably
	21	leftover from Wily Tower sound driver/code
	22	- I'm not sure about sound_status write - maybe it's something else or
	23	different data (p1?) is used as status
	24
14	25	TODO:
15		- Sound: it's difficult to guess how the I8039 is connected... there's also a
16		OKI MSM80C39RS chip.
17		- One unknown ROM. Samples?
18	26	- Sprite positioning is wacky. The electric 'bands' that go along the pipes
19	27	are drawn 2 pixels off in x/y directions. If you fix that, then the player
20	28	sprite doesn't slide in the middle of the pipes when climbing...
	29	- Clocks
21	30
22	31	Dip locations verified for:
23	32	- atomboy (manual)
24	33
	34
25	35	***************************************************************************/
26	36
27	37	#include "driver.h"
r2864	r2865
33	43	extern WRITE8_HANDLER( fghtbskt_samples_w );
34	44
35	45	static UINT8 wilytowr_videoram2, wilytowr_scrollram;
36
37	46	static int pal_bank, fg_flag, sy_offset;
38
39	47	static tilemap bg_tilemap, fg_tilemap;
	48	static UINT8 sound_irq;
	49	static int sound_status;
	50	static int p1,p2;
40	51
41	52
42	53	static PALETTE_INIT( wilytowr )
43	54	{
44	55	int i;
45	56
46
47	57	for (i = 0;i < 256;i++)
48	58	{
49	59	int bit0,bit1,bit2,bit3,r,g,b;
r2864	r2865
217	227	coin_counter_w(offset, data & 0x01);
218	228	}
219	229
220
221	230	static WRITE8_HANDLER( snd_irq_w )
222	231	{
223		cpunum_set_input_line(machine, 1, 0, PULSE_LINE);
	232	cpunum_set_input_line(machine, 1, 0, ASSERT_LINE);
	233	timer_call_after_resynch(NULL, 0, NULL);
224	234	}
225	235
226
227
228		static int p1,p2;
229
230	236	static WRITE8_HANDLER( snddata_w )
231	237	{
232	238	int num_ays = (sndti_exists(SOUND_AY8910, 1)) ? 2 : 1;
	239
233	240	if ((p2 & 0xf0) == 0xe0)
234	241	AY8910_control_port_0_w(machine,0,offset);
235	242	else if ((p2 & 0xf0) == 0xa0)
r2864	r2865
237	244	else if (num_ays == 2 && (p1 & 0xe0) == 0x60)
238	245	AY8910_control_port_1_w(machine,0,offset);
239	246	else if (num_ays == 2 && (p1 & 0xe0) == 0x40)
240		AY8910_write_port_1_w(machine,0,offset);
241		else // if ((p2 & 0xf0) != 0x70)
242		/* the port address is the data, while the data seems to be control bits */
243		logerror("%04x: snddata_w ctrl = %02x, p1 = %02x, p2 = %02x, data = %02x\n",activecpu_get_pc(),data,p1,p2,offset);
	247	AY8910_write_port_1_w(machine,0,offset);
	248	else if ((p2 & 0xf0) == 0x70 )
	249	sound_status=offset;
244	250	}
245	251
246	252	static WRITE8_HANDLER( p1_w )
r2864	r2865
251	257	static WRITE8_HANDLER( p2_w )
252	258	{
253	259	p2 = data;
	260	if((p2&0xf0)==0x50)
	261	{
	262	cpunum_set_input_line(machine, 1, 0, CLEAR_LINE);
	263	}
254	264	}
255	265
	266	static READ8_HANDLER( snd_status_r )
	267	{
	268	return sound_status;
	269	}
256	270
	271	static READ8_HANDLER( irq_r )
	272	{
	273	if (sound_irq)
	274	{
	275	sound_irq = 0;
	276	return 1;
	277	}
	278	return 0;
	279	}
	280
	281	static READ8_HANDLER( snddata_r )
	282	{
	283	switch(p2&0xf0)
	284	{
	285	case 0x60: return soundlatch_r(machine,0); ;
	286	case 0x70: return memory_region(REGION_USER1)[((p1&0x1f)<<8)\|offset];
	287	}
	288	return 0xff;
	289	}
	290
257	291	static ADDRESS_MAP_START( wilytowr_map, ADDRESS_SPACE_PROGRAM, 8 )
258	292	AM_RANGE(0x0000, 0xbfff) AM_ROM
259	293	AM_RANGE(0xd000, 0xdfff) AM_RAM
r2864	r2865
284	318	AM_RANGE(0xd400, 0xd7ff) AM_RAM_WRITE(wilytowr_videoram2_w) AM_BASE(&wilytowr_videoram2)
285	319	AM_RANGE(0xd800, 0xdbff) AM_RAM_WRITE(wilytowr_videoram_w) AM_BASE(&videoram)
286	320	AM_RANGE(0xdc00, 0xdfff) AM_RAM_WRITE(wilytowr_colorram_w) AM_BASE(&colorram)
287		AM_RANGE(0xf000, 0xf000) AM_READ~~NOP //~~sound status
	321	AM_RANGE(0xf000, 0xf000) AM_READ(snd_status_r)
288	322	AM_RANGE(0xf001, 0xf001) AM_READ(input_port_0_r)
289	323	AM_RANGE(0xf002, 0xf002) AM_READ(input_port_1_r)
290	324	AM_RANGE(0xf003, 0xf003) AM_READ(input_port_2_r)
r2864	r2865
307	341
308	342
309	343	static ADDRESS_MAP_START( i8039_port_map, ADDRESS_SPACE_IO, 8 )
310		// AM_RANGE(I8039_t1, I8039_t1)
311		AM_RANGE(0x00, 0xff) AM_WRITE(snddata_w)
	344	AM_RANGE(0x00, 0xff) AM_READWRITE(snddata_r, snddata_w)
312	345	AM_RANGE(I8039_p1, I8039_p1) AM_WRITE(p1_w)
313	346	AM_RANGE(I8039_p2, I8039_p2) AM_WRITE(p2_w)
	347	AM_RANGE(I8039_t1, I8039_t1) AM_READ(irq_r)
314	348	ADDRESS_MAP_END
315	349
316	350
r2864	r2865
502	536	fghtbskt_sh_start
503	537	};
504	538
	539	static void snd_irq(running_machine *machine, int num)
	540	{
	541	sound_irq = 1;
	542	}
505	543
506	544	static MACHINE_DRIVER_START( wilytowr )
507	545
508	546	/* basic machine hardware */
509		MDRV_CPU_ADD(Z80,12000000/4) /* 3 MHz */
	547	MDRV_CPU_ADD_TAG("maincpu",Z80,12000000/4) /* 3 MHz */
510	548	MDRV_CPU_PROGRAM_MAP(wilytowr_map,0)
511	549	MDRV_CPU_VBLANK_INT("main", nmi_line_pulse)
512	550
513	551	/* audio CPU */
514		MDRV_CPU_ADD(I8039,12000000/4) /* ????? */
	552	MDRV_CPU_ADD_TAG("soundcpu",I8039,12000000/4) /* ????? */
515	553	MDRV_CPU_PROGRAM_MAP(i8039_map,0)
516	554	MDRV_CPU_IO_MAP(i8039_port_map,0)
	555	MDRV_CPU_PERIODIC_INT(snd_irq, 60)
517	556
	557
518	558	/* video hardware */
519	559	MDRV_SCREEN_ADD("main", RASTER)
520	560	MDRV_SCREEN_REFRESH_RATE(60)
r2864	r2865
540	580	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.20)
541	581	MACHINE_DRIVER_END
542	582
	583	static MACHINE_DRIVER_START( atomboy )
	584	MDRV_IMPORT_FROM(wilytowr)
	585	MDRV_CPU_MODIFY("soundcpu")
	586	MDRV_CPU_PERIODIC_INT(snd_irq, 60/2)
	587	MACHINE_DRIVER_END
	588
543	589	static MACHINE_DRIVER_START( fghtbskt )
544	590
545	591	/* basic machine hardware */
r2864	r2865
551	597	MDRV_CPU_ADD(I8039,12000000/4) /* ????? */
552	598	MDRV_CPU_PROGRAM_MAP(i8039_map,0)
553	599	MDRV_CPU_IO_MAP(i8039_port_map,0)
	600	MDRV_CPU_PERIODIC_INT(snd_irq, 60/2)
554	601
555	602	/* video hardware */
556	603	MDRV_SCREEN_ADD("main", RASTER)
r2864	r2865
616	663	ROM_LOAD( "wt_a-3p.bin", 0x4000, 0x1000, CRC(7299f362) SHA1(5ba309d789df8432c08d67e4f9e8bf6c447fc425) )
617	664	ROM_LOAD( "wt_a-3s.bin", 0x5000, 0x1000, CRC(9b37d50d) SHA1(a08d4a7654b815cb652be66dbaa097011327f5d5) )
618	665
619		ROM_REGION( 0x1000, REGION_USER1, 0 ) ~~/* unknown; sound? */~~
	666	ROM_REGION( 0x2000, REGION_USER1, 0 )
620	667	ROM_LOAD( "wt_a-6d.bin", 0x0000, 0x1000, CRC(a5dde29b) SHA1(8f7545d2022da7c98d47112179dce717f6c3c5e2) )
621	668
	669
622	670	ROM_REGION( 0x0320, REGION_PROMS, 0 )
623	671	ROM_LOAD( "wt_a-5s-.bpr", 0x0000, 0x0100, CRC(041950e7) SHA1(8276068bec3f4c5013c773033fca3cd3ed9e82ef) ) /* red */
624	672	ROM_LOAD( "wt_a-5r-.bpr", 0x0100, 0x0100, CRC(bc04bf25) SHA1(37d0e89296760f51df5a0d434dca390fb60bb052) ) /* green */
r2864	r2865
656	704	ROM_LOAD( "wt_a-3p-b.bin", 0x8000, 0x2000, CRC(3018b840) SHA1(77df9d4f1c8d76d30c435d03d51ef9e7509fab9c) )
657	705	ROM_LOAD( "wt_a-3s-b.bin", 0xa000, 0x2000, CRC(05a251d4) SHA1(1cd9102871507ab988d5fe799024d63b93807448) )
658	706
659		ROM_REGION( 0x1000, REGION_USER1, 0 ) ~~/* unknown; sound? */~~
	707	ROM_REGION( 0x2000, REGION_USER1, 0 )
660	708	ROM_LOAD( "wt_a-6d.bin", 0x0000, 0x1000, CRC(a5dde29b) SHA1(8f7545d2022da7c98d47112179dce717f6c3c5e2) )
661	709
662	710	ROM_REGION( 0x0320, REGION_PROMS, 0 )
r2864	r2865
697	745	ROM_LOAD( "wt_a-3p.bin", 0x4000, 0x1000, CRC(7299f362) SHA1(5ba309d789df8432c08d67e4f9e8bf6c447fc425) )
698	746	ROM_LOAD( "wt_a-3s.bin", 0x5000, 0x1000, CRC(9b37d50d) SHA1(a08d4a7654b815cb652be66dbaa097011327f5d5) )
699	747
700		ROM_REGION( 0x1000, REGION_USER1, 0 ) ~~/* unknown; sound? */~~
	748	ROM_REGION( 0x1000, REGION_USER1, 0 )
701	749	ROM_LOAD( "wt_a-6d.bin", 0x0000, 0x1000, CRC(a5dde29b) SHA1(8f7545d2022da7c98d47112179dce717f6c3c5e2) )
702	750
703	751	ROM_REGION( 0x0320, REGION_PROMS, 0 )
r2864	r2865
715	763	ROM_LOAD( "fb10.6f", 0x8000, 0x2000, CRC(6b47efba) SHA1(cb55c7a9d5afe748c1c88f87dd1909e106932798) )
716	764	ROM_LOAD( "fb09.7f", 0xa000, 0x2000, CRC(be69e087) SHA1(be95ecafa494cb0787ee18eb3ecea4ad545a6ae3) )
717	765
718		ROM_REGION( 0x3000, REGION_CPU2, 0 ) /* 8039 */
	766	ROM_REGION( 0x1000, REGION_CPU2, 0 ) /* 8039 */
719	767	ROM_LOAD( "fb07.0b", 0x0000, 0x1000, CRC(50432dbd) SHA1(35a2218ed243bde47dbe06b5a11a65502ba734ea) )
720		/* on the real pcb if you remove it the ay8910 doesn't sound anymore, probably the cpu reads it somehow */
721		ROM_LOAD( "fb06.12a", 0x1000, 0x2000, CRC(bea3df99) SHA1(18b795f8626b22f6a1620e04c23f4967c3122c89) )
722	768
723	769	ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
724	770	ROM_LOAD( "fb08.12f", 0x0000, 0x1000, CRC(271cd7b8) SHA1(00cfeb6ba429cf6cc59d6542dea8de2ca79155ed) )
r2864	r2865
744	790	ROM_LOAD( "fb04.39a", 0x6000, 0x2000, CRC(02ddc42d) SHA1(9d40967071f674592c174b5a5470db56a5f99adf) )
745	791	ROM_LOAD( "fb05.38a", 0x8000, 0x2000, CRC(72ea6b49) SHA1(e081a1cad5abf373a2489169b5c86ee63dcf5823) )
746	792
	793	ROM_REGION( 0x2000, REGION_USER1, 0 )
	794	ROM_LOAD( "fb06.12a", 0x0000, 0x2000, CRC(bea3df99) SHA1(18b795f8626b22f6a1620e04c23f4967c3122c89) )
	795
747	796	ROM_REGION( 0x0300, REGION_PROMS, 0 )
748	797	ROM_LOAD( "fb_r.9e", 0x0000, 0x0100, CRC(c5cdc8ba) SHA1(3fcef3ebe0dda72dfa35e042ff611758c345d749) )
749	798	ROM_LOAD( "fb_g.10e", 0x0100, 0x0100, CRC(1460c936) SHA1(f99a544c83931de098a6cfac391f63ae43f5cdd0) )
750	799	ROM_LOAD( "fb_b.11e", 0x0200, 0x0100, CRC(fca5bf0e) SHA1(5846f43aa2906cac58e300fdab197b99f896e3ef) )
	800
	801
751	802	ROM_END
752	803
753	804	static DRIVER_INIT( wilytowr )
r2864	r2865
760	811	sy_offset = 240;
761	812	}
762	813
763		GAME( 1984, wilytowr, 0, wilytowr, wilytowr, wilytowr, ROT180, "Irem", "Wily Tower", GAME_NO_SOUND )
764		GAME( 1985, atomboy, wilytowr, wilytowr, wilytowr, wilytowr, ROT180, "Irem (Memetron license)", "Atomic Boy (revision B)", GAME_NO_SOUND )
765		GAME( 1985, atomboya, wilytowr, wilytowr, wilytowr, wilytowr, ROT180, "Irem (Memetron license)", "Atomic Boy (revision A)", GAME_NO_SOUND )
766		GAME( 1984, fghtbskt, 0, fghtbskt, fghtbskt, fghtbskt, ROT0, "Paradise Co. Ltd.", "Fighting Basketball", GAME_IMPERFECT_SOUND )
	814	GAME( 1984, wilytowr, 0, wilytowr, wilytowr, wilytowr, ROT180, "Irem", "Wily Tower", 0 )
	815	GAME( 1985, atomboy, wilytowr, atomboy, wilytowr, wilytowr, ROT180, "Irem (Memetron license)", "Atomic Boy (revision B)", 0 )
	816	GAME( 1985, atomboya, wilytowr, atomboy, wilytowr, wilytowr, ROT180, "Irem (Memetron license)", "Atomic Boy (revision A)", 0 )
	817	GAME( 1984, fghtbskt, 0, fghtbskt, fghtbskt, fghtbskt, ROT0, "Paradise Co. Ltd.", "Fighting Basketball", 0 )

src/mame/drivers/looping.c
r2864	r2865
1	1	/*
2	2	To Do:
	3	- redump COP420 internal ROM
3	4	- get sound working
4	5	- map and test any remaining input ports
5	6
r2864	r2865
10	11	TMS9995
11	12
12	13	COP420 Microcontroller
13		~~manag~~e~~s CPU~~ c~~ommunnica~~tion?
	14	protection
14	15
15	16	Sound CPU
16	17	TMS9980
r2864	r2865
716	717	ROM_LOAD( "i-o.11a", 0x2800, 0x1000, CRC(61c74c79) SHA1(9f34d18a919446dd76857b851cea23fc1526f3c2) ) /* speech */
717	718
718	719	ROM_REGION( 0x1000, REGION_CPU3, 0 ) /* COP420 microcontroller code */
719		ROM_LOAD( "cop.bin", 0x0000, 0x1000, CRC(bbfd26d5) SHA1(5f78b32b6e7c003841ef5b635084db2cdfebf0e1) )
	720	ROM_LOAD( "cop.bin", 0x0000, 0x1000, BAD_DUMP CRC(bbfd26d5) SHA1(5f78b32b6e7c003841ef5b635084db2cdfebf0e1) ) // overdumped 4 times, and starting PC is not 0
720	721
721	722	ROM_REGION( 0x1000, REGION_GFX1, ROMREGION_DISPOSE )
722	723	ROM_LOAD( "log2.8a", 0x0000, 0x800, CRC(ef3284ac) SHA1(8719c9df8c972a56c306b3c707aaa53092ffa2d6) )
r2864	r2865
740	741	ROM_LOAD( "i-o.11a", 0x2800, 0x1000, CRC(61c74c79) SHA1(9f34d18a919446dd76857b851cea23fc1526f3c2) )
741	742
742	743	ROM_REGION( 0x1000, REGION_CPU3, 0 ) /* COP420 microcontroller code */
743		ROM_LOAD( "cop.bin", 0x0000, 0x1000, CRC(bbfd26d5) SHA1(5f78b32b6e7c003841ef5b635084db2cdfebf0e1) )
	744	ROM_LOAD( "cop.bin", 0x0000, 0x1000, BAD_DUMP CRC(bbfd26d5) SHA1(5f78b32b6e7c003841ef5b635084db2cdfebf0e1) ) // overdumped 4 times, and starting PC is not 0
744	745
745	746	ROM_REGION( 0x1000, REGION_GFX1, ROMREGION_DISPOSE )
746	747	ROM_LOAD( "log2.8a", 0x0000, 0x800, CRC(ef3284ac) SHA1(8719c9df8c972a56c306b3c707aaa53092ffa2d6) )
r2864	r2865
763	764	ROM_LOAD( "snd.11a", 0x2800, 0x1000, CRC(61c74c79) SHA1(9f34d18a919446dd76857b851cea23fc1526f3c2) )
764	765
765	766	ROM_REGION( 0x1000, REGION_CPU3, 0 ) /* COP420 microcontroller code */
766		ROM_LOAD( "cop.bin", 0x0000, 0x1000, CRC(bbfd26d5) SHA1(5f78b32b6e7c003841ef5b635084db2cdfebf0e1) )
	767	ROM_LOAD( "cop.bin", 0x0000, 0x1000, BAD_DUMP CRC(bbfd26d5) SHA1(5f78b32b6e7c003841ef5b635084db2cdfebf0e1) ) // overdumped 4 times, and starting PC is not 0
767	768
768	769	ROM_REGION( 0x1000, REGION_GFX1, ROMREGION_DISPOSE )
769	770	ROM_LOAD( "vid.8a", 0x0000, 0x800, CRC(459ccc55) SHA1(747f6789605b48be9e22f779f9e3f6c98ad4e594) )

src/mame/drivers/darkhors.c
r2864	r2865
295	295	// from bit mask to bit number
296	296	int bit_p1 = mask_to_bit((input_sel & 0x00ff0000) >> 16);
297	297	int bit_p2 = mask_to_bit((input_sel & 0xff000000) >> 24);
	298	static const char *portnames[] = { "IN0", "IN1", "IN2", "IN3", "IN4", "IN5", "IN6", "IN7" };
298	299
299		return (input_port_read_indexed(machine, 5 + bit_p1) & 0x00ffffff) \|
300		(input_port_read_indexed(machine, 5 + bit_p2) & 0xff000000) ;
	300	return (input_port_read(machine, portnames[bit_p1]) & 0x00ffffff) \|
	301	(input_port_read(machine, portnames[bit_p2]) & 0xff000000) ;
301	302	}
302	303
303	304	static WRITE32_HANDLER( darkhors_unk1_w )
r2864	r2865
348	349	***************************************************************************/
349	350
350	351	static INPUT_PORTS_START( darkhors )
351		PORT_START // IN0 - 580000
	352	PORT_START_TAG("580000") /* IN0 - 580000 */
352	353	PORT_BIT( 0xff7fffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
353	354	PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("?") PORT_CODE(KEYCODE_RCONTROL)
354	355
355		PORT_START // IN1 - 580004
	356	PORT_START_TAG("580004") /* IN1 - 580004 */
356	357	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
357	358	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_BILL1 ) // bill in
358	359	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_COIN1 ) // coin in s1
r2864	r2865
365	366	PORT_BIT( 0x08000000, IP_ACTIVE_LOW, IPT_COIN2 ) // coin drop p2
366	367	PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_SPECIAL) // hopper full p2
367	368
368		PORT_START // IN2 - 580400
	369	PORT_START_TAG("580400") /* IN2 - 580400 */
369	370	PORT_BIT( 0xfffcffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
370	371	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0") PORT_CODE(KEYCODE_0_PAD)
371	372	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("9") PORT_CODE(KEYCODE_9_PAD)
372	373
373		PORT_START // IN3 - 580420
	374	PORT_START_TAG("580420") /* IN3 - 580420 */
374	375	PORT_BIT( 0xfffcffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
375	376	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("0*") PORT_CODE(KEYCODE_0_PAD)
376	377	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("9*") PORT_CODE(KEYCODE_9_PAD)
377	378
378		PORT_START // IN4 - 4e0080
	379	PORT_START_TAG("4e0080") /* IN4 - 4e0080 */
379	380	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
380	381	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_SERVICE1 ) // config
381	382	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_SERVICE2 ) // reset
r2864	r2865
394	395	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
395	396	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
396	397
397		PORT_START // IN5 - 580008(0)
	398	PORT_START_TAG("IN0") /* IN5 - 580008(0) */
398	399	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
399	400	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 1") PORT_CODE(KEYCODE_1_PAD)
400	401	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 2") PORT_CODE(KEYCODE_2_PAD)
r2864	r2865
413	414	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 7") //PORT_CODE(KEYCODE_)
414	415	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 8") //PORT_CODE(KEYCODE_)
415	416
416		PORT_START // IN6 - 580008(1)
	417	PORT_START_TAG("IN1") /* IN6 - 580008(1) */
417	418	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
418	419	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 1-2") PORT_CODE(KEYCODE_Z)
419	420	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 1-3") PORT_CODE(KEYCODE_A)
r2864	r2865
432	433	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P2 Bet 1-8") //PORT_CODE(KEYCODE_)
433	434	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
434	435
435		PORT_START // IN7 - 580008(2)
	436	PORT_START_TAG("IN2") /* IN7 - 580008(2) */
436	437	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
437	438	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 2-3") PORT_CODE(KEYCODE_X)
438	439	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 2-4") PORT_CODE(KEYCODE_S)
r2864	r2865
451	452	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
452	453	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
453	454
454		PORT_START // IN - 580008(3)
	455	PORT_START_TAG("IN3") /* IN - 580008(3) */
455	456	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
456	457	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 3-4") PORT_CODE(KEYCODE_C)
457	458	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 3-5") PORT_CODE(KEYCODE_D)
r2864	r2865
470	471	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
471	472	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
472	473
473		PORT_START // IN8 - 580008(4)
	474	PORT_START_TAG("IN4") /* IN8 - 580008(4) */
474	475	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
475	476	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 4-5") PORT_CODE(KEYCODE_V)
476	477	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 4-6") PORT_CODE(KEYCODE_F)
r2864	r2865
489	490	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
490	491	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
491	492
492		PORT_START // IN9 - 580008(5)
	493	PORT_START_TAG("IN5") /* IN9 - 580008(5) */
493	494	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
494	495	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 5-6") PORT_CODE(KEYCODE_B)
495	496	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 5-7") PORT_CODE(KEYCODE_G)
r2864	r2865
508	509	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
509	510	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
510	511
511		PORT_START // IN10 - 580008(6)
	512	PORT_START_TAG("IN6") /* IN10 - 580008(6) */
512	513	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
513	514	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 6-7") PORT_CODE(KEYCODE_N)
514	515	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 6-8") PORT_CODE(KEYCODE_H)
r2864	r2865
527	528	PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
528	529	PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
529	530
530		PORT_START // IN11 - 580008(7)
	531	PORT_START_TAG("IN7") /* IN11 - 580008(7) */
531	532	PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNKNOWN )
532	533	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("P1 Bet 7-8") PORT_CODE(KEYCODE_M)
533	534	PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_UNKNOWN )

src/mame/drivers/offtwall.c
r2864	r2865
90	90
91	91	static READ16_HANDLER( special_port3_r )
92	92	{
93		int result = input_port_read~~_indexed~~(machine, 3);
	93	int result = input_port_read(machine, "260010");
94	94	if (atarigen_cpu_to_sound_ready) result ^= 0x0020;
95	95	return result;
96	96	}
r2864	r2865
310	310	*************************************/
311	311
312	312	static INPUT_PORTS_START( offtwall )
313		PORT_START /* 260000 */
	313	PORT_START_TAG("260000") /* 260000 */
314	314	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
315	315	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
316	316	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
r2864	r2865
328	328	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
329	329	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
330	330
331		PORT_START /* 260002 */
	331	PORT_START_TAG("260002") /* 260002 */
332	332	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
333	333	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(3)
334	334	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
r2864	r2865
341	341
342	342	JSA_III_PORT /* audio board port */
343	343
344		PORT_START /* 260010 */
	344	PORT_START_TAG("260010") /* 260010 */
345	345	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED )
346	346	PORT_DIPNAME( 0x0002, 0x0000, DEF_STR( Controls ) )
347	347	PORT_DIPSETTING( 0x0000, "Whirly-gigs" ) /* this is official Atari terminology! */
r2864	r2865
354	354	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_VBLANK )
355	355	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
356	356
357		PORT_START /* 260012 */
	357	PORT_START_TAG("260012") /* 260012 */
358	358	PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED )
359	359
360		PORT_START /* 260020 */
	360	PORT_START_TAG("260020") /* 260020 */
361	361	PORT_BIT( 0xff, 0, IPT_DIAL_V ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(1)
362	362	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
363	363
364		PORT_START /* 260022 */
	364	PORT_START_TAG("260022") /* 260022 */
365	365	PORT_BIT( 0xff, 0, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_PLAYER(2)
366	366	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
367	367
368		PORT_START /* 260024 */
	368	PORT_START_TAG("260024") /* 260024 */
369	369	PORT_BIT( 0xff, 0, IPT_DIAL_V ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(3)
370	370	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
371	371	INPUT_PORTS_END
r2864	r2865
500	500	static DRIVER_INIT( offtwall )
501	501	{
502	502	atarigen_eeprom_default = default_eeprom;
503		atarijsa_init(machine, 3, 0x0040);
	503	atarijsa_init(machine, "260010", 0x0040);
504	504
505	505	/* install son-of-slapstic workarounds */
506	506	spritecache_count = memory_install_read16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x3fde42, 0x3fde43, 0, 0, spritecache_count_r);
r2864	r2865
512	512	static DRIVER_INIT( offtwalc )
513	513	{
514	514	atarigen_eeprom_default = default_eeprom;
515		atarijsa_init(machine, 3, 0x0040);
	515	atarijsa_init(machine, "260010", 0x0040);
516	516
517	517	/* install son-of-slapstic workarounds */
518	518	spritecache_count = memory_install_read16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x3fde42, 0x3fde43, 0, 0, spritecache_count_r);

src/mame/drivers/equites.c
r2864	r2865
647	647	#if HVOLTAGE_DEBUG
648	648	static READ16_HANDLER(hvoltage_debug_r)
649	649	{
650		return(input_port_read~~_indexed~~(machine, 2));
	650	return(input_port_read(machine, "FAKE"));
651	651	}
652	652	#endif
653	653
r2864	r2865
801	801	// Equites Port Map
802	802
803	803	static INPUT_PORTS_START( equites )
804		PORT_START
	804	PORT_START_TAG("IN0")
805	805	EQUITES_PLAYER_INPUT_LSB( IPT_BUTTON1, IPT_BUTTON2, IPT_BUTTON3, IPT_START1 )
806	806	EQUITES_PLAYER_INPUT_MSB( IPT_BUTTON1, IPT_BUTTON2, IPT_BUTTON3, IPT_START2 )
807	807
808		PORT_START
	808	PORT_START_TAG("IN1")
809	809	PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_COIN1 )
810	810	PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_COIN2 )
811	811	#if EASY_TEST_MODE
r2864	r2865
838	838	// Gekisou Port Map
839	839
840	840	static INPUT_PORTS_START( gekisou )
841		PORT_START
	841	PORT_START_TAG("IN0")
842	842	EQUITES_PLAYER_INPUT_LSB( IPT_BUTTON1, IPT_BUTTON2, IPT_BUTTON3, IPT_START1 )
843	843	EQUITES_PLAYER_INPUT_MSB( IPT_BUTTON1, IPT_BUTTON2, IPT_BUTTON3, IPT_START2 )
844	844
845		PORT_START
	845	PORT_START_TAG("IN1")
846	846	PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_COIN1 )
847	847	PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_COIN2 )
848	848	#if EASY_TEST_MODE
r2864	r2865
864	864	// Bull Fighter Port Map
865	865
866	866	static INPUT_PORTS_START( bullfgtr )
867		PORT_START
	867	PORT_START_TAG("IN0")
868	868	EQUITES_PLAYER_INPUT_LSB( IPT_BUTTON1, IPT_BUTTON2, IPT_BUTTON3, IPT_START1 )
869	869	EQUITES_PLAYER_INPUT_MSB( IPT_BUTTON1, IPT_BUTTON2, IPT_BUTTON3, IPT_START2 )
870	870
871		PORT_START
	871	PORT_START_TAG("IN1")
872	872	PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_COIN1 )
873	873	PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_COIN2 )
874	874	#if EASY_TEST_MODE
r2864	r2865
900	900	// Koukouyakyuh Port Map
901	901
902	902	static INPUT_PORTS_START( kouyakyu )
903		PORT_START
	903	PORT_START_TAG("IN0")
904	904	EQUITES_PLAYER_INPUT_LSB( IPT_BUTTON1, IPT_BUTTON2, IPT_BUTTON3, IPT_START1 )
905	905	EQUITES_PLAYER_INPUT_MSB( IPT_BUTTON1, IPT_BUTTON2, IPT_BUTTON3, IPT_START2 )
906	906
907		PORT_START
	907	PORT_START_TAG("IN1")
908	908	// PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_COIN1 )
909	909	// PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_UNUSED )
910	910	PORT_BIT( 0x0300, IP_ACTIVE_HIGH, IPT_COIN1 )
r2864	r2865
937	937	// Splendor Blast Port Map
938	938
939	939	static INPUT_PORTS_START( splndrbt )
940		PORT_START
	940	PORT_START_TAG("IN0")
941	941	EQUITES_PLAYER_INPUT_LSB( IPT_BUTTON1, IPT_BUTTON2, IPT_UNKNOWN, IPT_START1 )
942	942	EQUITES_PLAYER_INPUT_MSB( IPT_BUTTON1, IPT_BUTTON2, IPT_UNKNOWN, IPT_START2 )
943	943
944		PORT_START
	944	PORT_START_TAG("IN1")
945	945	PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_COIN1 )
946	946	PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_COIN2 )
947	947	#if EASY_TEST_MODE
r2864	r2865
973	973	// High Voltage Port Map
974	974
975	975	static INPUT_PORTS_START( hvoltage )
976		PORT_START
	976	PORT_START_TAG("IN0")
977	977	PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY
978	978	PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY
979	979	PORT_BIT( 0x0004, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY
r2864	r2865
993	993	PORT_BIT( 0x4000, IP_ACTIVE_HIGH, IPT_UNKNOWN ) PORT_COCKTAIL
994	994	PORT_BIT( 0x8000, IP_ACTIVE_HIGH, IPT_START2 )
995	995
996		PORT_START
	996	PORT_START_TAG("IN1")
997	997	PORT_BIT( 0x0100, IP_ACTIVE_HIGH, IPT_COIN1 )
998	998	PORT_BIT( 0x0200, IP_ACTIVE_HIGH, IPT_COIN2 )
999	999	#if EASY_TEST_MODE
r2864	r2865
1027	1027
1028	1028	#if HVOLTAGE_DEBUG
1029	1029	/* Fake port to handle debug mode */
1030		PORT_START
	1030	PORT_START_TAG("FAKE")
1031	1031	PORT_DIPNAME( 0xffff, 0xffff, "Debug Mode" )
1032	1032	PORT_DIPSETTING( 0xffff, DEF_STR( Off ) )
1033	1033	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )

src/mame/drivers/decocass.c
r2864	r2865
149	149	ADDRESS_MAP_END
150	150
151	151	static INPUT_PORTS_START( decocass )
152		PORT_START /* IN0 */
	152	PORT_START_TAG("IN0") /* IN0 */
153	153	PORT_BIT( 0x01, IP_ACTIVE_HIGH,IPT_JOYSTICK_RIGHT )
154	154	PORT_BIT( 0x02, IP_ACTIVE_HIGH,IPT_JOYSTICK_LEFT )
155	155	PORT_BIT( 0x04, IP_ACTIVE_HIGH,IPT_JOYSTICK_UP )
r2864	r2865
159	159	PORT_BIT( 0x40, IP_ACTIVE_HIGH,IPT_UNUSED )
160	160	PORT_BIT( 0x80, IP_ACTIVE_HIGH,IPT_UNUSED )
161	161
162		PORT_START /* IN1 */
	162	PORT_START_TAG("IN1") /* IN1 */
163	163	PORT_BIT( 0x01, IP_ACTIVE_HIGH,IPT_JOYSTICK_RIGHT ) PORT_COCKTAIL
164	164	PORT_BIT( 0x02, IP_ACTIVE_HIGH,IPT_JOYSTICK_LEFT ) PORT_COCKTAIL
165	165	PORT_BIT( 0x04, IP_ACTIVE_HIGH,IPT_JOYSTICK_UP ) PORT_COCKTAIL
r2864	r2865
169	169	PORT_BIT( 0x40, IP_ACTIVE_HIGH,IPT_UNUSED )
170	170	PORT_BIT( 0x80, IP_ACTIVE_HIGH,IPT_UNUSED )
171	171
172		PORT_START /* IN2 */
	172	PORT_START_TAG("IN2") /* IN2 */
173	173	PORT_BIT( 0x01, IP_ACTIVE_HIGH,IPT_UNKNOWN )
174	174	PORT_BIT( 0x02, IP_ACTIVE_HIGH,IPT_UNKNOWN )
175	175	PORT_BIT( 0x04, IP_ACTIVE_HIGH,IPT_UNKNOWN )
r2864	r2865
179	179	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(1)
180	180	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(1)
181	181
182		PORT_START /* IN3 */
	182	PORT_START_TAG("AN0") /* IN3 */
183	183	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
184	184
185		PORT_START /* IN4 */
	185	PORT_START_TAG("AN1") /* IN4 */
186	186	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
187	187
188		PORT_START /* IN5 */
	188	PORT_START_TAG("AN2") /* IN5 */
189	189	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
190	190
191		PORT_START /* IN6 */
	191	PORT_START_TAG("AN3") /* IN6 */
192	192	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_MINMAX(0x10,0xf0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
193	193
194	194	PORT_START_TAG("DSW1")

src/mame/drivers/fromance.c
r2864	r2865
202	202	int ret = 0xff;
203	203
204	204	if (fromance_portselect & 0x01)
205		ret &= input_port_read~~_indexed~~(machine, 4);
	205	ret &= input_port_read(machine, "KEY1");
206	206	if (fromance_portselect & 0x02)
207		ret &= input_port_read~~_indexed~~(machine, 5);
	207	ret &= input_port_read(machine, "KEY2");
208	208	if (fromance_portselect & 0x04)
209		ret &= input_port_read~~_indexed~~(machine, 6);
	209	ret &= input_port_read(machine, "KEY3");
210	210	if (fromance_portselect & 0x08)
211		ret &= input_port_read~~_indexed~~(machine, 7);
	211	ret &= input_port_read(machine, "KEY4");
212	212	if (fromance_portselect & 0x10)
213		ret &= input_port_read~~_indexed~~(machine, 8);
	213	ret &= input_port_read(machine, "KEY5");
214	214
215	215	return ret;
216	216	}
r2864	r2865
239	239	static ADDRESS_MAP_START( nekkyoku_readmem_main, ADDRESS_SPACE_PROGRAM, 8 )
240	240	AM_RANGE(0x0000, 0xbfff) AM_READ(SMH_ROM)
241	241	AM_RANGE(0xc000, 0xdfff) AM_READ(SMH_RAM)
242		AM_RANGE(0xf000, 0xf000) AM_READ~~(input~~_~~port_~~0_r)
	242	AM_RANGE(0xf000, 0xf000) AM_READ_PORT("IN0")
243	243	AM_RANGE(0xf001, 0xf001) AM_READ(fromance_keymatrix_r)
244		AM_RANGE(0xf002, 0xf002) AM_READ~~(input~~_~~port_~~1_r)
	244	AM_RANGE(0xf002, 0xf002) AM_READ_PORT("IN1")
245	245	AM_RANGE(0xf003, 0xf003) AM_READ(fromance_busycheck_main_r)
246		AM_RANGE(0xf004, 0xf004) AM_READ(input_port_3_r)
247		AM_RANGE(0xf005, 0xf005) AM_READ(input_port_2_r)
	246	AM_RANGE(0xf004, 0xf004) AM_READ_PORT("DSW2")
	247	AM_RANGE(0xf005, 0xf005) AM_READ_PORT("DSW1")
248	248	ADDRESS_MAP_END
249	249
250	250	static ADDRESS_MAP_START( nekkyoku_writemem_main, ADDRESS_SPACE_PROGRAM, 8 )
r2864	r2865
261	261	AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM)
262	262	AM_RANGE(0xc000, 0xdfff) AM_READ(SMH_RAM)
263	263	AM_RANGE(0x9e89, 0x9e89) AM_READ(SMH_NOP) // unknown (idolmj)
264		AM_RANGE(0xe000, 0xe000) AM_READ~~(input~~_~~port_~~0_r)
	264	AM_RANGE(0xe000, 0xe000) AM_READ_PORT("IN0")
265	265	AM_RANGE(0xe001, 0xe001) AM_READ(fromance_keymatrix_r)
266		AM_RANGE(0xe002, 0xe002) AM_READ~~(input~~_~~port_~~1_r)
	266	AM_RANGE(0xe002, 0xe002) AM_READ_PORT("IN1")
267	267	AM_RANGE(0xe003, 0xe003) AM_READ(fromance_busycheck_main_r)
268		AM_RANGE(0xe004, 0xe004) AM_READ(input_port_3_r)
269		AM_RANGE(0xe005, 0xe005) AM_READ(input_port_2_r)
	268	AM_RANGE(0xe004, 0xe004) AM_READ_PORT("DSW2")
	269	AM_RANGE(0xe005, 0xe005) AM_READ_PORT("DSW1")
270	270	ADDRESS_MAP_END
271	271
272	272	static ADDRESS_MAP_START( fromance_writemem_main, ADDRESS_SPACE_PROGRAM, 8 )
r2864	r2865
391	391	*************************************/
392	392
393	393	#define FROMANCE_KEYMATRIX1 \
394		PORT_START_TAG("~~IN4~~") \
	394	PORT_START_TAG("KEY1") \
395	395	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) \
396	396	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) \
397	397	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) \
r2864	r2865
402	402	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
403	403
404	404	#define FROMANCE_KEYMATRIX2 \
405		PORT_START_TAG("~~IN5~~") \
	405	PORT_START_TAG("KEY2") \
406	406	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) \
407	407	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) \
408	408	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) \
r2864	r2865
413	413	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
414	414
415	415	#define FROMANCE_KEYMATRIX3 \
416		PORT_START_TAG("~~IN6~~") \
	416	PORT_START_TAG("KEY3") \
417	417	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) \
418	418	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) \
419	419	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) \
r2864	r2865
424	424	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
425	425
426	426	#define FROMANCE_KEYMATRIX4 \
427		PORT_START_TAG("~~IN7~~") \
	427	PORT_START_TAG("KEY4") \
428	428	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) \
429	429	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) \
430	430	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) \
r2864	r2865
435	435	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
436	436
437	437	#define FROMANCE_KEYMATRIX5 \
438		PORT_START_TAG("~~IN8~~") \
	438	PORT_START_TAG("KEY5") \
439	439	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) \
440	440	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) \
441	441	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) \
r2864	r2865
975	975	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
976	976	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
977	977
978		PORT_START /* (3) DIPSW-2 */
	978	PORT_START_TAG("DSW2") /* (3) DIPSW-2 */
979	979	PORT_DIPNAME( 0x01, 0x00, "DIPSW 2-1" )
980	980	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
981	981	PORT_DIPSETTING( 0x01, DEF_STR( On ) )

src/mame/drivers/irobot.c
r2864	r2865
122	122	static ADDRESS_MAP_START( readmem, ADDRESS_SPACE_PROGRAM, 8 )
123	123	AM_RANGE(0x0000, 0x07ff) AM_READ(SMH_RAM)
124	124	AM_RANGE(0x0800, 0x0fff) AM_READ(SMH_BANK2)
125		AM_RANGE(0x1000, 0x103f) AM_READ(input_port_0_r)
126		AM_RANGE(0x1040, 0x1040) AM_READ(input_port_1_r)
	125	AM_RANGE(0x1000, 0x103f) AM_READ_PORT("IN0")
	126	AM_RANGE(0x1040, 0x1040) AM_READ_PORT("IN1")
127	127	AM_RANGE(0x1080, 0x1080) AM_READ(irobot_status_r)
128		AM_RANGE(0x10c0, 0x10c0) AM_READ~~(input~~_~~port_3_r~~)
	128	AM_RANGE(0x10c0, 0x10c0) AM_READ_PORT("DSW1")
129	129	AM_RANGE(0x1200, 0x12ff) AM_READ(SMH_RAM)
130	130	AM_RANGE(0x1300, 0x13ff) AM_READ(irobot_control_r)
131	131	AM_RANGE(0x1400, 0x143f) AM_READ(quad_pokey_r)
r2864	r2865
163	163	*************************************/
164	164
165	165	static INPUT_PORTS_START( irobot )
166		PORT_START /* IN0 */
	166	PORT_START_TAG("IN0") /* IN0 */
167	167	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
168	168	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
169	169	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
173	173	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
174	174	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
175	175
176		PORT_START /* IN1 */
	176	PORT_START_TAG("IN1") /* IN1 */
177	177	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
178	178	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
179	179	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
183	183	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
184	184	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
185	185
186		PORT_START /* IN2 */
	186	PORT_START_TAG("IN2") /* IN2 */
187	187	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
188	188	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
189	189	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
193	193	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN ) /* EXT DONE */
194	194	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_VBLANK )
195	195
196		PORT_START /* DSW1 */
	196	PORT_START_TAG("DSW1") /* DSW1 */
197	197	PORT_DIPNAME( 0x03, 0x00, "Coins Per Credit" )
198	198	PORT_DIPSETTING( 0x00, "1 Coin 1 Credit" )
199	199	PORT_DIPSETTING( 0x01, "2 Coins 1 Credit" )
r2864	r2865
216	216	PORT_DIPSETTING( 0x60, "2 Credits for 4 Coin Units" )
217	217	PORT_DIPSETTING( 0xe0, DEF_STR( Free_Play ) )
218	218
219		PORT_START /* DSW2 */
220		PORT_DIPNAME( 0x01, 0x01, DEF_STR( Language ) )
221		PORT_DIPSETTING( 0x01, DEF_STR( English ) )
222		PORT_DIPSETTING( 0x00, DEF_STR( German ) )
223		PORT_DIPNAME( 0x02, 0x02, "Min Game Time" )
224		PORT_DIPSETTING( 0x00, "90 Sec" )
225		PORT_DIPSETTING( 0x02, "3 Lives" )
226		PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )
227		PORT_DIPSETTING( 0x08, DEF_STR( None ) )
228		PORT_DIPSETTING( 0x0c, "20000" )
229		PORT_DIPSETTING( 0x00, "30000" )
230		PORT_DIPSETTING( 0x04, "50000" )
231		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )
232		PORT_DIPSETTING( 0x20, "2" )
233		PORT_DIPSETTING( 0x30, "3" )
234		PORT_DIPSETTING( 0x00, "4" )
235		PORT_DIPSETTING( 0x10, "5" )
236		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Difficulty ) )
237		PORT_DIPSETTING( 0x00, DEF_STR( Easy ) )
238		PORT_DIPSETTING( 0x40, DEF_STR( Medium ) )
239		PORT_DIPNAME( 0x80, 0x80, "Demo Mode" )
240		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
241		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	219	PORT_START_TAG("DSW2") /* DSW2 */
	220	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Language ) )
	221	PORT_DIPSETTING( 0x01, DEF_STR( English ) )
	222	PORT_DIPSETTING( 0x00, DEF_STR( German ) )
	223	PORT_DIPNAME( 0x02, 0x02, "Min Game Time" )
	224	PORT_DIPSETTING( 0x00, "90 Sec" )
	225	PORT_DIPSETTING( 0x02, "3 Lives" )
	226	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )
	227	PORT_DIPSETTING( 0x08, DEF_STR( None ) )
	228	PORT_DIPSETTING( 0x0c, "20000" )
	229	PORT_DIPSETTING( 0x00, "30000" )
	230	PORT_DIPSETTING( 0x04, "50000" )
	231	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )
	232	PORT_DIPSETTING( 0x20, "2" )
	233	PORT_DIPSETTING( 0x30, "3" )
	234	PORT_DIPSETTING( 0x00, "4" )
	235	PORT_DIPSETTING( 0x10, "5" )
	236	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Difficulty ) )
	237	PORT_DIPSETTING( 0x00, DEF_STR( Easy ) )
	238	PORT_DIPSETTING( 0x40, DEF_STR( Medium ) )
	239	PORT_DIPNAME( 0x80, 0x80, "Demo Mode" )
	240	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	241	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
242	242
243		PORT_START /* IN4 */
	243	PORT_START_TAG("AN0") /* IN4 */
244	244	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_MINMAX(96,163) PORT_SENSITIVITY(70) PORT_KEYDELTA(50)
245	245
246		PORT_START /* IN5 */
	246	PORT_START_TAG("AN1") /* IN5 */
247	247	PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(96,159) PORT_SENSITIVITY(50) PORT_KEYDELTA(50) PORT_REVERSE
248
249	248	INPUT_PORTS_END
250	249
251	250

src/mame/drivers/klax.c
r2864	r2865
47	47	static void scanline_update(const device_config *screen, int scanline)
48	48	{
49	49	/* generate 32V signals */
50		if ((scanline & 32) == 0 && !(input_port_read~~_indexed~~(screen->machine, 0) & 0x800))
	50	if ((scanline & 32) == 0 && !(input_port_read(screen->machine, "IN0") & 0x800))
51	51	atarigen_scanline_int_gen(screen->machine, 0);
52	52	}
53	53
r2864	r2865
137	137	*************************************/
138	138
139	139	static INPUT_PORTS_START( klax )
140		PORT_START
	140	PORT_START_TAG("IN0")
141	141	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
142	142	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
143	143	PORT_BIT( 0x00fc, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
149	149	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
150	150	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
151	151
152		PORT_START
	152	PORT_START_TAG("IN1")
153	153	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
154	154	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
155	155	PORT_BIT( 0x0600, IP_ACTIVE_LOW, IPT_UNUSED )

src/mame/drivers/halleys.c
r2864	r2865
1605	1605
1606	1606	static READ8_HANDLER( io_mirror_r )
1607	1607	{
1608		return(input_port_read_indexed(machine, offset + 3));
	1608	static const char *portnames[] = { "IN0", "IN1", "IN2", "IN3" };
	1609
	1610	return input_port_read(machine, portnames[offset]);
1609	1611	}
1610	1612
1611	1613
r2864	r2865
1620	1622	AM_RANGE(0xff66, 0xff66) AM_READ(collision_id_r) // HACK: collision detection bypass(Halley's Comet only)
1621	1623	AM_RANGE(0xff71, 0xff71) AM_READ(blitter_status_r)
1622	1624	AM_RANGE(0xff80, 0xff83) AM_READ(io_mirror_r)
1623		AM_RANGE(0xff90, 0xff90) AM_READ(input_port_3_r) // coin/start
1624		AM_RANGE(0xff91, 0xff91) AM_READ(input_port_4_r) // player 1
1625		AM_RANGE(0xff92, 0xff92) AM_READ(input_port_5_r) // player 2
1626		AM_RANGE(0xff93, 0xff93) AM_READ(input_port_6_r) // unused?
	1625	AM_RANGE(0xff90, 0xff90) AM_READ_PORT("IN0") // coin/start
	1626	AM_RANGE(0xff91, 0xff91) AM_READ_PORT("IN1") // player 1
	1627	AM_RANGE(0xff92, 0xff92) AM_READ_PORT("IN2") // player 2
	1628	AM_RANGE(0xff93, 0xff93) AM_READ_PORT("IN3") // unused?
1627	1629	AM_RANGE(0xff94, 0xff94) AM_READ(coin_lockout_r)
1628		AM_RANGE(0xff95, 0xff95) AM_READ(input_port_0_r) // dipswitch 4
1629		AM_RANGE(0xff96, 0xff96) AM_READ(input_port_1_r) // dipswitch 3
1630		AM_RANGE(0xff97, 0xff97) AM_READ(input_port_2_r) // dipswitch 2
1631		AM_RANGE(0xff00, 0xffbf) AM_READ(SMH_RAM) // I/O read fall-through
	1630	AM_RANGE(0xff95, 0xff95) AM_READ_PORT("DSW1") // dipswitch 4
	1631	AM_RANGE(0xff96, 0xff96) AM_READ_PORT("DSW2") // dipswitch 3
	1632	AM_RANGE(0xff97, 0xff97) AM_READ_PORT("DSW3") // dipswitch 2
	1633	AM_RANGE(0xff00, 0xffbf) AM_READ(SMH_RAM) // I/O read fall-through
1632	1634
1633	1635	AM_RANGE(0xffc0, 0xffdf) AM_READ(SMH_RAM) // palette read
1634	1636	AM_RANGE(0xffe0, 0xffff) AM_READ(vector_r)
r2864	r2865
1687	1689	*/
1688	1690
1689	1691	static INPUT_PORTS_START( halleys )
1690		PORT_START_TAG("DSW1") // 0xff95
	1692	PORT_START_TAG("DSW1") /* 0xff95 */
1691	1693	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) )
1692	1694	PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
1693	1695	PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
r2864	r2865
1711	1713	PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
1712	1714	PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
1713	1715
1714		PORT_START_TAG("DSW2") // 0xff96
	1716	PORT_START_TAG("DSW2") /* 0xff96 */
1715	1717	PORT_DIPNAME( 0x03, 0x01, DEF_STR( Difficulty ) )
1716	1718	PORT_DIPSETTING( 0x02, DEF_STR( Easiest ) )
1717	1719	PORT_DIPSETTING( 0x03, DEF_STR( Easy ) )
r2864	r2865
1734	1736	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1735	1737	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1736	1738
1737		PORT_START_TAG("DSW3") // 0xff97
	1739	PORT_START_TAG("DSW3") /* 0xff97 */
1738	1740	PORT_DIPNAME( 0x01, 0x01, "Unknown(3-1)" )
1739	1741	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1740	1742	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
1760	1762	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1761	1763	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1762	1764
1763		PORT_START_TAG("IN0") // 0xff90
	1765	PORT_START_TAG("IN0") /* 0xff90 */
1764	1766	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
1765	1767	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN )
1766	1768	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r2864	r2865
1770	1772	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN2 )
1771	1773	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 )
1772	1774
1773		PORT_START_TAG("IN1") // 0xff91
	1775	PORT_START_TAG("IN1") /* 0xff91 */
1774	1776	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
1775	1777	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
1776	1778	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
r2864	r2865
1780	1782	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P1 Hyperspace")
1781	1783	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P1 Fire")
1782	1784
1783		PORT_START_TAG("IN2") // 0xff92
	1785	PORT_START_TAG("IN2") /* 0xff92 */
1784	1786	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
1785	1787	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
1786	1788	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1790	1792	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) PORT_NAME("P2 Hyperspace")
1791	1793	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_NAME("P2 Fire")
1792	1794
1793		PORT_START_TAG("IN3") // 0xff93
	1795	PORT_START_TAG("IN3") /* 0xff93 */
1794	1796
1795		PORT_START_TAG("FAKE") // just to be safe
	1797	PORT_START_TAG("FAKE") /* just to be safe */
1796	1798	PORT_DIPNAME( 0x01, 0x00, "Show Unused Layer" )
1797	1799	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
1798	1800	PORT_DIPSETTING( 0x01, DEF_STR( Yes ) )
r2864	r2865
1800	1802
1801	1803
1802	1804	static INPUT_PORTS_START( benberob )
1803		PORT_START_TAG("DSW1") // 0xff95
	1805	PORT_START_TAG("DSW1") /* 0xff95 */
1804	1806	PORT_DIPNAME( 0x03, 0x01, DEF_STR( Bonus_Life ) )
1805	1807	PORT_DIPSETTING( 0x02, "Every 100K" )
1806	1808	PORT_DIPSETTING( 0x00, "100K & Every 200K" )
r2864	r2865
1824	1826	PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
1825	1827	PORT_DIPSETTING( 0x80, DEF_STR( Cocktail ) )
1826	1828
1827		// 0xff96
1828		PORT_START_TAG("DSW2")
	1829	PORT_START_TAG("DSW2") /* 0xff96 */
1829	1830	PORT_DIPNAME( 0x0f, 0x00, DEF_STR( Coin_A ) )
1830	1831	PORT_DIPSETTING( 0x0f, DEF_STR( 9C_1C ) )
1831	1832	PORT_DIPSETTING( 0x0e, DEF_STR( 8C_1C ) )
r2864	r2865
1861	1862	PORT_DIPSETTING( 0x60, DEF_STR( 1C_7C ) )
1862	1863	PORT_DIPSETTING( 0x70, DEF_STR( 1C_8C ) )
1863	1864
1864		PORT_START_TAG("DSW3") // 0xff97
	1865	PORT_START_TAG("DSW3") /* 0xff97 */
1865	1866	PORT_DIPNAME( 0x01, 0x01, "Starting Round" )
1866	1867	PORT_DIPSETTING( 0x01, "1st Round" )
1867	1868	PORT_DIPSETTING( 0x00, "2nd Round" )
r2864	r2865
1886	1887	PORT_DIPSETTING( 0x80, "9" )
1887	1888	PORT_DIPSETTING( 0x00, "16" )
1888	1889
1889		PORT_START_TAG("IN0") // 0xff90
	1890	PORT_START_TAG("IN0") /* 0xff90 */
1890	1891	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNKNOWN )
1891	1892	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNKNOWN )
1892	1893	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r2864	r2865
1896	1897	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN2 )
1897	1898	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN1 )
1898	1899
1899		PORT_START_TAG("IN1") // 0xff91
	1900	PORT_START_TAG("IN1") /* 0xff91 */
1900	1901	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
1901	1902	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
1902	1903	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
r2864	r2865
1906	1907	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P1 Jump")
1907	1908	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P1 Extinguisher")
1908	1909
1909		PORT_START_TAG("IN2") // 0xff92
	1910	PORT_START_TAG("IN2") /* 0xff92 */
1910	1911	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
1911	1912	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
1912	1913	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1916	1917	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) PORT_NAME("P2 Jump")
1917	1918	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_NAME("P2 Extinguisher")
1918	1919
1919		PORT_START_TAG("IN3") // 0xff93
	1920	PORT_START_TAG("IN3") /* 0xff93 */
1920	1921	INPUT_PORTS_END
1921	1922
1922	1923

src/mame/drivers/gomoku.c
r2864	r2865
49	49	static READ8_HANDLER( input_port_r )
50	50	{
51	51	int i, res;
	52	static const char *portnames[] = { "IN0", "IN1", "DSW", "UNUSED0", "UNUSED1", "UNUSED2", "UNUSED3", "UNUSED4" };
52	53
53	54	res = 0;
54	55	for (i = 0; i < 8; i++)
55		res \|= ((input_port_read~~_indexed~~(machine, i) >> offset) & 1) << i;
	56	res \|= ((input_port_read(machine, portnames[i]) >> offset) & 1) << i;
56	57
57	58	return res;
58	59	}
r2864	r2865
84	85
85	86
86	87	static INPUT_PORTS_START( gomoku )
87		PORT_START /* 0 */
	88	PORT_START_TAG("IN0")
88	89	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
89	90	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
90	91	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT )
r2864	r2865
94	95	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_COCKTAIL
95	96	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_COCKTAIL
96	97
97		PORT_START /* 1 */
	98	PORT_START_TAG("IN1")
98	99	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 )
99	100	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL
100	101	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START1 )
r2864	r2865
106	107	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN1 )
107	108	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_COIN2 )
108	109
109		PORT_START ~~/* 2 */~~
	110	PORT_START_TAG("DSW")
110	111	PORT_SERVICE( 0x01, IP_ACTIVE_HIGH )
111	112	PORT_DIPNAME( 0x06, 0x00, DEF_STR( Lives ))
112	113	PORT_DIPSETTING( 0x00, "2" )
r2864	r2865
127	128	PORT_DIPSETTING( 0x40, DEF_STR( 1C_3C ) )
128	129	PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
129	130
130		PORT_START ~~/* 3 */~~
	131	PORT_START_TAG("UNUSED0")
131	132	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
132	133
133		PORT_START ~~/* 4 */~~
	134	PORT_START_TAG("UNUSED1")
134	135	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
135	136
136		PORT_START ~~/* 5 */~~
	137	PORT_START_TAG("UNUSED2")
137	138	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
138	139
139		PORT_START ~~/* 6 */~~
	140	PORT_START_TAG("UNUSED3")
140	141	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
141	142
142		PORT_START ~~/* 7 */~~
	143	PORT_START_TAG("UNUSED4")
143	144	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
144	145	INPUT_PORTS_END
145	146

src/mame/drivers/segas24.c
r2864	r2865
344	344	UINT16* s24_mainram1;
345	345
346	346	extern void s24_fd1094_machine_init(void);
347		extern void s24_fd1094_driver_init(void);
	347	extern void s24_fd1094_driver_init(running_machine *machine);
348	348
349	349	VIDEO_START(system24);
350	350	VIDEO_UPDATE(system24);
r2864	r2865
688	688
689	689	static UINT8 resetcontrol, prev_resetcontrol;
690	690
691		static void reset_reset(void)
	691	static void reset_reset(running_machine *machine)
692	692	{
693	693	int changed = resetcontrol ^ prev_resetcontrol;
694	694	if(changed & 2) {
695	695	if(resetcontrol & 2) {
696		cpunum_set_input_line(Machine, 1, INPUT_LINE_HALT, CLEAR_LINE);
697		cpunum_set_input_line(Machine, 1, INPUT_LINE_RESET, PULSE_LINE);
	696	cpunum_set_input_line(machine, 1, INPUT_LINE_HALT, CLEAR_LINE);
	697	cpunum_set_input_line(machine, 1, INPUT_LINE_RESET, PULSE_LINE);
698	698	// mame_printf_debug("enable 2nd cpu!\n");
699	699	// DEBUGGER_BREAK;
700	700	s24_fd1094_machine_init();
701	701
702	702	} else
703		cpunum_set_input_line(Machine, 1, INPUT_LINE_HALT, ASSERT_LINE);
	703	cpunum_set_input_line(machine, 1, INPUT_LINE_HALT, ASSERT_LINE);
704	704	}
705	705	if(changed & 4)
706	706	sndti_reset(SOUND_YM2151, 0);
r2864	r2865
711	711	{
712	712	resetcontrol = data;
713	713	logerror("Reset control %02x (%x:%x)\n", resetcontrol, cpu_getactivecpu(), activecpu_get_pc());
714		reset_reset();
	714	reset_reset(Machine);
715	715	}
716	716
717	717
r2864	r2865
1173	1173	system24temp_sys16_io_set_callbacks(hotrod_io_r, hotrod_io_w, resetcontrol_w, iod_r, iod_w);
1174	1174	mlatch_table = 0;
1175	1175	track_size = 0x2d00;
1176		s24_fd1094_driver_init();
	1176	s24_fd1094_driver_init(machine);
1177	1177
1178	1178	}
1179	1179
r2864	r2865
1182	1182	system24temp_sys16_io_set_callbacks(hotrod_io_r, hotrod_io_w, resetcontrol_w, iod_r, iod_w);
1183	1183	mlatch_table = 0;
1184	1184	track_size = 0x2f00;
1185		s24_fd1094_driver_init();
	1185	s24_fd1094_driver_init(machine);
1186	1186
1187	1187	}
1188	1188
r2864	r2865
1191	1191	system24temp_sys16_io_set_callbacks(dcclub_io_r, hotrod_io_w, resetcontrol_w, iod_r, iod_w);
1192	1192	mlatch_table = dcclub_mlt;
1193	1193	track_size = 0x2d00;
1194		s24_fd1094_driver_init();
	1194	s24_fd1094_driver_init(machine);
1195	1195
1196	1196	}
1197	1197
r2864	r2865
1203	1203	system24temp_sys16_io_set_callbacks(hotrod_io_r, hotrod_io_w, resetcontrol_w, iod_r, iod_w);
1204	1204	mlatch_table = 0;
1205	1205	track_size = 0x2d00;
1206		s24_fd1094_driver_init();
	1206	s24_fd1094_driver_init(machine);
1207	1207
1208	1208	}
1209	1209
r2864	r2865
1212	1212	system24temp_sys16_io_set_callbacks(hotrod_io_r, hotrod_io_w, resetcontrol_w, iod_r, iod_w);
1213	1213	mlatch_table = 0;
1214	1214	track_size = 0x2d00;
1215		s24_fd1094_driver_init();
	1215	s24_fd1094_driver_init(machine);
1216	1216	}
1217	1217
1218	1218	static DRIVER_INIT(gground)
r2864	r2865
1220	1220	system24temp_sys16_io_set_callbacks(gground_io_r, hotrod_io_w, resetcontrol_w, iod_r, iod_w);
1221	1221	mlatch_table = 0;
1222	1222	track_size = 0x2d00;
1223		s24_fd1094_driver_init();
	1223	s24_fd1094_driver_init(machine);
1224	1224	}
1225	1225
1226	1226	static DRIVER_INIT(crkdown)
r2864	r2865
1228	1228	system24temp_sys16_io_set_callbacks(hotrod_io_r, hotrod_io_w, resetcontrol_w, iod_r, iod_w);
1229	1229	mlatch_table = 0;
1230	1230	track_size = 0x2d00;
1231		s24_fd1094_driver_init();
	1231	s24_fd1094_driver_init(machine);
1232	1232	}
1233	1233
1234	1234	static DRIVER_INIT(roughrac)
r2864	r2865
1236	1236	system24temp_sys16_io_set_callbacks(hotrod_io_r, hotrod_io_w, resetcontrol_w, iod_r, iod_w);
1237	1237	mlatch_table = 0;
1238	1238	track_size = 0x2d00;
1239		s24_fd1094_driver_init();
	1239	s24_fd1094_driver_init(machine);
1240	1240	}
1241	1241
1242	1242	/*************************************

src/mame/drivers/segas16a.c
r2864	r2865
180	180	*************************************/
181	181
182	182	extern void fd1094_machine_init(void);
183		extern void fd1094_driver_init(void (set_decrypted)(UINT8 ));
	183	extern void fd1094_driver_init(running_machine machine, void (set_decrypted)(UINT8 *));
184	184
185	185	static READ16_HANDLER( misc_io_r );
186	186	static WRITE16_HANDLER( misc_io_w );
r2864	r2865
220	220	MACHINE_RESET_CALL(sys16_onetime);
221	221
222	222	/* init the FD1094 */
223		fd1094_driver_init(NULL);
	223	fd1094_driver_init(machine, NULL);
224	224
225	225	/* reset the custom handlers and other pointers */
226	226	custom_io_r = NULL;
r2864	r2865
1973	1973
1974	1974	/**************************************************************************************************************************
1975	1975	Alex Kidd, Sega System 16A
1976		CPU: FD1094? 317-~~????~~
	1976	CPU: FD1089A 317-0021
1977	1977	*/
1978	1978	ROM_START( alexkid1 )
1979	1979	ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 68000 code */
r2864	r2865
3011	3011	*/
3012	3012	ROM_START( wb31 )
3013	3013	ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 68000 code */
	3014	ROM_LOAD16_BYTE( "epr12084.bin", 0x000000, 0x10000, CRC(b6deb654) SHA1(37066cc63902233bb8b56d3171c42bf8a8f82e58) )
3014	3015	ROM_LOAD16_BYTE( "epr12082.bin", 0x000001, 0x10000, CRC(38dc5b15) SHA1(b25bf60d269a87f9d8dbc1a3787c8ff9a6e7482c) )
3015		ROM_LOAD16_BYTE( "epr12084.bin", 0x000000, 0x10000, CRC(b6deb~~654~~) SHA1(37066cc639~~022~~33bb8b56d~~3171c~~42~~bf8a8f82~~e58) )
	3016	ROM_LOAD16_BYTE( "epr12085.bin", 0x020000, 0x10000, CRC(0962098b) SHA1(150fc439dd5e773bef706f058abdb4d2ec44e355) )
3016	3017	ROM_LOAD16_BYTE( "epr12083.bin", 0x020001, 0x10000, CRC(3d631a8e) SHA1(4940ff6cf380fb914876ade39ea37f42b79bf11d) )
3017		ROM_LOAD16_BYTE( "epr12085.bin", 0x020000, 0x10000, CRC(0962098b) SHA1(150fc439dd5e773bef706f058abdb4d2ec44e355) )
3018	3018
3019	3019	ROM_REGION( 0x2000, REGION_USER1, 0 ) /* decryption key */
3020	3020	ROM_LOAD( "317-0084.key", 0x0000, 0x2000, CRC(2c58dafa) SHA1(24d06970eda896fdd5e3486132bd19834f7d3659) )
r2864	r2865
3046	3046	ROM_LOAD( "epr12089.bin", 0x0000, 0x8000, CRC(8321eb0b) SHA1(61cf95833c0aa38e35fc18db39d4ec74e4aaf01e) )
3047	3047	ROM_END
3048	3048
	3049	/**************************************************************************************************************************
	3050	**************************************************************************************************************************
	3051	**************************************************************************************************************************
	3052	Wonder Boy III, Sega System 16A
	3053	CPU: FD1089A (317-unknown)
	3054	*/
	3055	ROM_START( wb35 )
	3056	ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 68000 code */
	3057	ROM_LOAD16_BYTE( "epr12120.43", 0x000000, 0x10000, CRC(cf41adf1) SHA1(aab2146d990d6698d73edf8d8699e98a1f01d534) )
	3058	ROM_LOAD16_BYTE( "epr12118.26", 0x000001, 0x10000, CRC(050ad6d0) SHA1(4d5e5b9a6b9b33ec767a18c30a8252063341eefb) )
	3059	ROM_LOAD16_BYTE( "epr12121.42", 0x020000, 0x10000, CRC(5e44c0a9) SHA1(4d4c9575a6cd571a7cf635164e92afd92d4b63fe) )
	3060	ROM_LOAD16_BYTE( "epr12119.25", 0x020001, 0x10000, CRC(b67b97a3) SHA1(0a5ab21c7b4ca6d6a31852dd8dfb94bb55c0f15d) )
3049	3061
	3062	ROM_REGION( 0x30000, REGION_GFX1, ROMREGION_DISPOSE ) /* tiles */
	3063	ROM_LOAD( "epr12086.95", 0x00000, 0x10000, CRC(45b949df) SHA1(84390d16da00b775988e5f6c20950cb2304b1a74) )
	3064	ROM_LOAD( "epr12087.94", 0x10000, 0x10000, CRC(5fb761aa) SHA1(dcf88e68732a8ec122d0603d87f6ea1f1614adef) )
	3065	ROM_LOAD( "epr12088.83", 0x20000, 0x10000, CRC(00579c39) SHA1(12acdea75e3d040d60a9f32d05fd9e0191d38f21) )
3050	3066
	3067	ROM_REGION16_BE( 0x80000, REGION_GFX2, 0 ) /* sprites */
	3068	ROM_LOAD16_BYTE( "epr12090.10", 0x00001, 0x008000, CRC(c85904c1) SHA1(e5af26ce870813bd5a88b430fc3881c7fcb63aef) )
	3069	ROM_CONTINUE( 0x40001, 0x008000 )
	3070	ROM_LOAD16_BYTE( "epr12094.11", 0x00000, 0x008000, CRC(615e4927) SHA1(d23f164973afa770714e284a77ddf10f18cc596b) )
	3071	ROM_CONTINUE( 0x40000, 0x008000 )
	3072	ROM_LOAD16_BYTE( "epr12091.17", 0x10001, 0x008000, CRC(8409a243) SHA1(bcbb9510a6499d8147543d6befa5a49f4ac055d9) )
	3073	ROM_CONTINUE( 0x50001, 0x008000 )
	3074	ROM_LOAD16_BYTE( "epr12095.18", 0x10000, 0x008000, CRC(e774ec2c) SHA1(a4aa15ec7be5539a740ad02ff720458018dbc536) )
	3075	ROM_CONTINUE( 0x50000, 0x008000 )
	3076	ROM_LOAD16_BYTE( "epr12092.23", 0x20001, 0x008000, CRC(5c2f0d90) SHA1(e0fbc0f841e4607ad232931368b16e81440a75c4) )
	3077	ROM_CONTINUE( 0x60001, 0x008000 )
	3078	ROM_LOAD16_BYTE( "epr12096.24", 0x20000, 0x008000, CRC(d55ca9c9) SHA1(cff95bd799cf9625f95261620d2df7f0891e34da) )
	3079	ROM_CONTINUE( 0x60000, 0x008000 )
	3080	ROM_LOAD16_BYTE( "epr12093.29", 0x30001, 0x008000, CRC(9e6d9086) SHA1(1cfe7175f538db9a47ef576b33be49057db0927d) )
	3081	ROM_CONTINUE( 0x70001, 0x008000 )
	3082	ROM_LOAD16_BYTE( "epr12097.30", 0x30000, 0x008000, CRC(e645902c) SHA1(497cfcf6c25cc2e042e16dbcb1963d2223def15a) )
	3083	ROM_CONTINUE( 0x70000, 0x008000 )
	3084
	3085	ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* sound CPU */
	3086	ROM_LOAD( "epr12089.12", 0x0000, 0x8000, CRC(8321eb0b) SHA1(61cf95833c0aa38e35fc18db39d4ec74e4aaf01e) )
	3087	ROM_END
	3088
3051	3089	/*************************************
3052	3090	*
3053	3091	* Generic driver initialization
r2864	r2865
3077	3115	static DRIVER_INIT( alexkid1 )
3078	3116	{
3079	3117	system16a_generic_init(machine);
3080		fd1089_decrypt_~~alexkidd~~();
	3118	fd1089_decrypt_0021();
3081	3119	}
3082	3120
3083	3121
r2864	r2865
3142	3180	fd1089_decrypt_0024();
3143	3181	}
3144	3182
	3183	static DRIVER_INIT( wb35 )
	3184	{
	3185	system16a_generic_init(machine);
	3186	fd1089_decrypt_wb35();
	3187	}
3145	3188
3146
3147	3189	/*************************************
3148	3190	*
3149	3191	* Game driver(s)
r2864	r2865
3166	3208	GAME( 1988, aceattaa, aceattac, system16a , aceattaa, aceattaa, ROT270, "Sega", "Ace Attacker (Japan, System 16A, FD1094 317-0060)", 0 )
3167	3209	GAME( 1986, afighter, 0, system16a_no7751, afighter, afighter, ROT270, "Sega", "Action Fighter, FD1089A 317-0018", 0 )
3168	3210	GAME( 1986, alexkidd, 0, system16a, alexkidd, generic_16a, ROT0, "Sega", "Alex Kidd: The Lost Stars (set 2, unprotected)", 0 )
3169		GAME( 1986, alexkid1, alexkidd, system16a, alexkidd, alexkid1, ROT0, "Sega", "Alex Kidd: The Lost Stars (set 1, FD1089A 317-~~unknown~~)", 0 )
	3211	GAME( 1986, alexkid1, alexkidd, system16a, alexkidd, alexkid1, ROT0, "Sega", "Alex Kidd: The Lost Stars (set 1, FD1089A 317-0021)", 0 )
3170	3212	GAME( 1986, fantzone, 0, system16a_no7751, fantzone, generic_16a, ROT0, "Sega", "Fantasy Zone (set 2, unprotected)", 0 )
3171	3213	GAME( 1986, fantzon1, fantzone, system16a_no7751, fantzone, generic_16a, ROT0, "Sega", "Fantasy Zone (set 1, unprotected)", 0 )
3172	3214	GAME( 1988, pshot16a, passsht, system16a, pshot16a, pshot16a, ROT270, "Sega", "Passing Shot (Japan, 4 Players, System 16A, FD1094 317-0071)", 0 )
r2864	r2865
3179	3221	GAME( 1988, tetris3, tetris, system16a_no7751, tetris, generic_16a, ROT0, "Sega", "Tetris (set 3, Japan, System 16A, FD1094 317-0093a)", 0 )
3180	3222	GAME( 1987, timesca1, timescan, system16a, timescan, timesca1, ROT270, "Sega", "Time Scanner (set 1, System 16A, FD1089B 317-0024)", 0 )
3181	3223	GAME( 1988, wb31, wb3, system16a_no7751, wb3, generic_16a, ROT0, "Sega / Westone", "Wonder Boy III - Monster Lair (set 1, System 16A, FD1094 317-0084)", 0 )
	3224	GAME( 1988, wb35, wb3, system16a_no7751, wb3, wb35, ROT0, "Sega / Westone", "Wonder Boy III - Monster Lair (set 5, System 16A, FD1089A 317-xxxx)", GAME_NOT_WORKING )

src/mame/drivers/neogeo.c
r2864	r2865
80	80	****************************************************************************/
81	81
82	82	#include "driver.h"
83		#include "deprecat.h"
84	83	#include "neogeo.h"
85	84	#include "machine/pd4990a.h"
86	85	#include "cpu/z80/z80.h"
r2864	r2865
158	157	#define IRQ2CTRL_AUTOLOAD_REPEAT (0x80)
159	158
160	159
161		static void adjust_display_position_interrupt_timer(void)
	160	static void adjust_display_position_interrupt_timer(running_machine *machine)
162	161	{
163	162	if ((display_counter + 1) != 0)
164	163	{
165	164	attotime period = attotime_mul(ATTOTIME_IN_HZ(NEOGEO_PIXEL_CLOCK), display_counter + 1);
166		if (LOG_VIDEO_SYSTEM) logerror("adjust_display_position_interrupt_timer current y: %02x current x: %02x target y: %x target x: %x\n", video_screen_get_vpos(Machine->primary_screen), video_screen_get_hpos(Machine->primary_screen), (display_counter + 1) / NEOGEO_HTOTAL, (display_counter + 1) % NEOGEO_HTOTAL);
	165	if (LOG_VIDEO_SYSTEM) logerror("adjust_display_position_interrupt_timer current y: %02x current x: %02x target y: %x target x: %x\n", video_screen_get_vpos(machine->primary_screen), video_screen_get_hpos(machine->primary_screen), (display_counter + 1) / NEOGEO_HTOTAL, (display_counter + 1) % NEOGEO_HTOTAL);
167	166
168	167	timer_adjust_oneshot(display_position_interrupt_timer, period, 0);
169	168	}
r2864	r2865
184	183	}
185	184
186	185
187		void neogeo_set_display_counter_lsb(UINT16 data)
	186	void neogeo_set_display_counter_lsb(running_machine *machine, UINT16 data)
188	187	{
189	188	display_counter = (display_counter & 0xffff0000) \| data;
190	189
r2864	r2865
193	192	if (display_position_interrupt_control & IRQ2CTRL_LOAD_RELATIVE)
194	193	{
195	194	if (LOG_VIDEO_SYSTEM) logerror("AUTOLOAD_RELATIVE ");
196		adjust_display_position_interrupt_timer();
	195	adjust_display_position_interrupt_timer(machine);
197	196	}
198	197	}
199	198
r2864	r2865
215	214	}
216	215
217	216
218		void neogeo_acknowledge_interrupt(UINT16 data)
	217	void neogeo_acknowledge_interrupt(running_machine *machine, UINT16 data)
219	218	{
220	219	if (data & 0x01) irq3_pending = 0;
221	220	if (data & 0x02) display_position_interrupt_pending = 0;
222	221	if (data & 0x04) vblank_interrupt_pending = 0;
223	222
224		update_interrupts(Machine);
	223	update_interrupts(machine);
225	224	}
226	225
227	226
r2864	r2865
239	238	if (display_position_interrupt_control & IRQ2CTRL_AUTOLOAD_REPEAT)
240	239	{
241	240	if (LOG_VIDEO_SYSTEM) logerror("AUTOLOAD_REPEAT ");
242		adjust_display_position_interrupt_timer();
	241	adjust_display_position_interrupt_timer(machine);
243	242	}
244	243	}
245	244
r2864	r2865
249	248	if (display_position_interrupt_control & IRQ2CTRL_AUTOLOAD_VBLANK)
250	249	{
251	250	if (LOG_VIDEO_SYSTEM) logerror("AUTOLOAD_VBLANK ");
252		adjust_display_position_interrupt_timer();
	251	adjust_display_position_interrupt_timer(machine);
253	252	}
254	253
255	254	/* set timer for next screen */
r2864	r2865
737	736	}
738	737
739	738
740		static void _set_audio_cpu_rom_source(void)
	739	static void _set_audio_cpu_rom_source(running_machine *machine)
741	740	{
742	741	/* if (!memory_region(NEOGEO_REGION_AUDIO_CPU_BIOS)) */
743	742	audio_cpu_rom_source = 1;
r2864	r2865
749	748	{
750	749	audio_cpu_rom_source_last = audio_cpu_rom_source;
751	750
752		cpunum_set_input_line(Machine, 1, INPUT_LINE_RESET, PULSE_LINE);
	751	cpunum_set_input_line(machine, 1, INPUT_LINE_RESET, PULSE_LINE);
753	752
754	753	if (LOG_AUDIO_CPU_BANKING) logerror("Audio CPU PC %03x: selectign %s ROM\n", safe_activecpu_get_pc(), audio_cpu_rom_source ? "CARTRIDGE" : "BIOS");
755	754	}
756	755	}
757	756
758	757
759		static void set_audio_cpu_rom_source(UINT8 data)
	758	static void set_audio_cpu_rom_source(running_machine *machine, UINT8 data)
760	759	{
761	760	audio_cpu_rom_source = data;
762	761
763		_set_audio_cpu_rom_source();
	762	_set_audio_cpu_rom_source(machine);
764	763	}
765	764
766	765
767		static void audio_cpu_banking_init(void)
	766	static void audio_cpu_banking_init(running_machine *machine)
768	767	{
769	768	int region;
770	769	int bank;
r2864	r2865
797	796	set_audio_cpu_banking();
798	797
799	798	audio_cpu_rom_source_last = 0;
800		set_audio_cpu_rom_source(0);
	799	set_audio_cpu_rom_source(machine, 0);
801	800	}
802	801
803	802
r2864	r2865
819	818	default:
820	819	case 0x00: neogeo_set_screen_dark(machine, bit); break;
821	820	case 0x01: set_main_cpu_vector_table_source(bit);
822		set_audio_cpu_rom_source(bit); /* this is a guess */
	821	set_audio_cpu_rom_source(machine, bit); /* this is a guess */
823	822	break;
824	823	case 0x05: neogeo_set_fixed_layer_source(bit); break;
825	824	case 0x06: set_save_ram_unlock(bit); break;
r2864	r2865
949	948	_set_main_cpu_bank_address();
950	949	_set_main_cpu_vector_table_source();
951	950	set_audio_cpu_banking();
952		_set_audio_cpu_rom_source();
	951	_set_audio_cpu_rom_source(machine);
953	952	set_outputs();
954	953	}
955	954
r2864	r2865
962	961	main_cpu_banking_init();
963	962
964	963	/* set the initial audio CPU ROM banks */
965		audio_cpu_banking_init();
	964	audio_cpu_banking_init(machine);
966	965
967	966	create_interrupt_timers();
968	967

src/mame/drivers/konamigx.c
r2864	r2865
489	489	// excpuint stat, objdma stat, eeprom do
490	490
491	491	// note: racin' force expects bit 1 of the eeprom port to toggle
492		return(input_port_read~~_indexed~~(machine, 6)<<24 \| input_port_read_~~ind~~e~~xed~~(machine, 7)<<16 \| input_port_read~~_indexed~~(machine, 0)<<8 \| eeprom_read_bit() \| gx_rdport1_3);
	492	return(input_port_read(machine, "DSW0")<<24 \| input_port_read_safe(machine, "DSW1", 0)<<16 \| input_port_read(machine, "IN0")<<8 \| eeprom_read_bit() \| gx_rdport1_3);
493	493	}
494	494
495	495	static WRITE32_HANDLER( eeprom_w )
r2864	r2865
817	817	return(rv);
818	818	}
819	819
820		INLINE void write_snd_020(int reg, int val)
	820	INLINE void write_snd_020(running_machine *machine, int reg, int val)
821	821	{
822	822	sndto000[reg] = val;
823	823
824	824	if (reg == 7)
825	825	{
826		cpunum_set_input_line(Machine, 1, 1, HOLD_LINE);
	826	cpunum_set_input_line(machine, 1, 1, HOLD_LINE);
827	827	}
828	828	}
829	829
r2864	r2865
835	835	{
836	836	reg = offset<<1;
837	837	val = data>>24;
838		write_snd_020(reg, val);
	838	write_snd_020(machine, reg, val);
839	839	}
840	840
841	841	if (ACCESSING_BITS_8_15)
842	842	{
843	843	reg = (offset<<1)+1;
844	844	val = (data>>8)&0xff;
845		write_snd_020(reg, val);
	845	write_snd_020(machine, reg, val);
846	846	}
847	847	}
848	848
r2864	r2865
869	869	switch( input )
870	870	{
871	871	case ADC083X_CH0:
872		return ( (double)5 * input_port_read~~_indexed~~(Machine, 9 ) ) / 255; // steer
	872	return ( (double)5 * input_port_read(Machine, "AN0" ) ) / 255; // steer
873	873	case ADC083X_CH1:
874		return ( (double)5 * input_port_read~~_indexed~~(Machine, 10 ) ) / 255; // gas
	874	return ( (double)5 * input_port_read(Machine, "AN1" ) ) / 255; // gas
875	875	case ADC083X_VREF:
876	876	return 5;
877	877	}
r2864	r2865
880	880
881	881	static READ32_HANDLER( le2_gun_H_r )
882	882	{
883		int p1x = input_port_read_indexed(machine, 9)*287/0xff+22;
884		int p2x = input_port_read_indexed(machine, 11)*287/0xff+22;
	883	int p1x = input_port_read(machine, "LIGHT0_X")*287/0xff+22;
	884	int p2x = input_port_read(machine, "LIGHT1_X")*287/0xff+22;
885	885
886	886	return (p1x<<16)\|p2x;
887	887	}
888	888
889	889	static READ32_HANDLER( le2_gun_V_r )
890	890	{
891		int p1y = input_port_read_indexed(machine, 10)*223/0xff+1;
892		int p2y = input_port_read_indexed(machine, 12)*223/0xff+1;
	891	int p1y = input_port_read(machine, "LIGHT0_Y")*223/0xff+1;
	892	int p2y = input_port_read(machine, "LIGHT1_Y")*223/0xff+1;
893	893
894	894	return (p1y<<16)\|p2y;
895	895	}
896	896
897	897	static READ32_HANDLER( service_r )
898	898	{
899		int res = (input_port_read~~_indexed~~(machine, 1)<<24) \| (input_port_read_~~ind~~e~~xed~~(machine, 8)<<8);
	899	int res = (input_port_read(machine, "IN1")<<24) \| (input_port_read_safe(machine, "IN6", 0)<<8);
900	900
901	901	if (init_eeprom_count)
902	902	{
r2864	r2865
909	909
910	910	static READ32_HANDLER( players_r )
911	911	{
912		return (input_port_read~~_indexed~~(machine, 2)<<24) \| (input_port_read~~_indexed~~(machine, 3)<<16) \| (input_port_read~~_indexed~~(machine, 4)<<8) \| (input_port_read~~_indexed~~(machine, 5));
	912	return (input_port_read(machine, "IN2")<<24) \| (input_port_read(machine, "IN3")<<16) \| (input_port_read(machine, "IN4")<<8) \| (input_port_read(machine, "IN5"));
913	913	}
914	914
915	915
r2864	r2865
1314	1314	MDRV_CPU_PROGRAM_MAP(gx_base_memmap, gx_type2_map)
1315	1315	MDRV_CPU_VBLANK_INT("main", konamigx_vbinterrupt)
1316	1316
1317		/* note: part is a -8, crystals are 18.4 and 32.0 MHz, and
1318		twinbee yahhoo will not pass POST if the 68000 isn't
1319		running at least this fast. so the higher speed is probably a HACK... */
1320		MDRV_CPU_ADD_TAG("sound", M68000, 9200000)
	1317	MDRV_CPU_ADD_TAG("sound", M68000, 8000000)
1321	1318	/* audio CPU */
1322	1319	MDRV_CPU_PROGRAM_MAP(gxsndmap, 0)
1323	1320	MDRV_CPU_PERIODIC_INT(irq2_line_hold, 480)
r2864	r2865
1332	1329	MDRV_VIDEO_ATTRIBUTES(VIDEO_HAS_SHADOWS \| VIDEO_HAS_HIGHLIGHTS \| VIDEO_UPDATE_AFTER_VBLANK)
1333	1330
1334	1331	MDRV_SCREEN_ADD("main", RASTER)
1335		MDRV_SCREEN_REFRESH_RATE(60)
1336		MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(600))
	1332	// MDRV_SCREEN_RAW_PARAMS(6000000, 288+17+32+49, 0, 287, 224+17+8+16, 0, 223)
	1333	/* These parameters should be correct according to developer manual,
	1334	but sound and graphics of tbyahhoo's attract mode doesn't sync correctly.
	1335	(better than previous 60Hz, though) Setting refresh rate to 58Hz fixes this.
	1336	We have to check actual value written to the CCU. */
	1337	MDRV_SCREEN_REFRESH_RATE(58)
	1338
	1339	// MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(600))
1337	1340	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
1338	1341	MDRV_SCREEN_SIZE(648, 328)
1339	1342	MDRV_SCREEN_VISIBLE_AREA(24, 24+288-1, 16, 16+224-1)
r2864	r2865
1443	1446	/**********************************************************************************/
1444	1447	/* port maps */
1445	1448
1446		static INPUT_PORTS_START( konamigx )
1447		PORT_START
	1449	/* here we collect players' inputs: they are shared among all the ports */
	1450	static INPUT_PORTS_START( common )
	1451	PORT_START_TAG("IN0")
1448	1452	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1449	1453	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1450	1454	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
1454	1458	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1455	1459	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1456	1460
1457		PORT_START
	1461	PORT_START_TAG("IN1")
1458	1462	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1459	1463	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1460		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) ~~PORT_PLAYER(1) /* for gun games */~~
	1464	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1461	1465	PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
1462	1466	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1463	1467	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1464	1468	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1465	1469	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1466	1470
1467		PORT_START
	1471	PORT_START_TAG("IN2")
1468	1472	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
1469	1473	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
1470	1474	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1474	1478	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
1475	1479	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
1476	1480
1477		PORT_START
	1481	PORT_START_TAG("IN3")
1478	1482	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
1479	1483	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
1480	1484	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1484	1488	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1485	1489	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
1486	1490
1487		PORT_START
	1491	PORT_START_TAG("IN4")
1488	1492	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
1489	1493	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
1490	1494	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
r2864	r2865
1494	1498	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
1495	1499	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START3 )
1496	1500
1497		PORT_START
	1501	PORT_START_TAG("IN5")
1498	1502	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
1499	1503	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
1500	1504	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
r2864	r2865
1503	1507	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
1504	1508	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
1505	1509	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
	1510	INPUT_PORTS_END
1506	1511
1507		PORT_START
	1512
	1513	static INPUT_PORTS_START( konamigx )
	1514	PORT_INCLUDE( common )
	1515
	1516	PORT_START_TAG("DSW0")
1508	1517	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Stereo ))
1509	1518	PORT_DIPSETTING( 0x00, DEF_STR( Stereo ))
1510	1519	PORT_DIPSETTING( 0x01, DEF_STR( Mono ))
r2864	r2865
1530	1539	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1531	1540	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1532	1541
1533		PORT_START
	1542	PORT_START_TAG("DSW1")
1534	1543	PORT_DIPNAME( 0x01, 0x01, "Foo")
1535	1544	PORT_DIPSETTING( 0x00, "Foo")
1536	1545	PORT_DIPSETTING( 0x01, "Bar")
r2864	r2865
1559	1568
1560	1569
1561	1570	static INPUT_PORTS_START( racinfrc )
1562		PORT_START
1563		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1564		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1565		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1566		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1567		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 )
1568		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE2 )
1569		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1570		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1571	/* racin force needs Player 2 Button 1 ("IN3" & 0x10) set to get past the calibration screen */
	1572	PORT_INCLUDE( konamigx )
1571	1573
1572		PORT_START
1573		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1574		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1575		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) /* for gun games */
1576		PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
1577		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1578		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1579		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1580		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1574	PORT_START_TAG("IN6") /* no gun */
1581	1575
1582		PORT_START
1583		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
1584		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
1585		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1586		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1587		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
1588		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
1589		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
1590		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
1591
1592		PORT_START
1593		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
1594		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
1595		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1596		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1597		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) // racin force needs this set to get past the calibration screen
1598		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
1599		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1600		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
1601
1602		PORT_START
1603		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
1604		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
1605		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
1606		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
1607		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
1608		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
1609		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
1610		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START3 )
1611
1612		PORT_START
1613		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
1614		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
1615		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
1616		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
1617		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
1618		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
1619		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
1620		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
1621
1622		PORT_START
1623		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Stereo ))
1624		PORT_DIPSETTING( 0x00, DEF_STR( Stereo ))
1625		PORT_DIPSETTING( 0x01, DEF_STR( Mono ))
1626		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) )
1627		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1628		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1629		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1630		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1631		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1632		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1633		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1634		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1635		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1636		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1637		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1638		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1639		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1640		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1641		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1642		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1643		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1644		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1645		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1646		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1647
1648		PORT_START
1649		PORT_DIPNAME( 0x01, 0x01, "Foo")
1650		PORT_DIPSETTING( 0x00, "Foo")
1651		PORT_DIPSETTING( 0x01, "Bar")
1652		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) )
1653		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1654		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1655		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1656		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1657		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1658		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1659		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1660		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1661		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1662		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1663		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1664		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1665		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1666		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1667		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1668		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1669		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1670		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1671		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1672		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1673
1674		PORT_START /* no gun */
1675
1676		PORT_START /* mask default type sens delta min max */
	1576	PORT_START_TAG("AN0") /* mask default type sens delta min max */
1677	1577	PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(0x38,0xc8) PORT_SENSITIVITY(35) PORT_KEYDELTA(5)
1678	1578
1679		PORT_START
	1579	PORT_START_TAG("AN1")
1680	1580	PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_MINMAX(0,0x68) PORT_SENSITIVITY(35) PORT_KEYDELTA(5) PORT_CODE_INC(KEYCODE_LCONTROL)
1681	1581	INPUT_PORTS_END
1682	1582
1683	1583	static INPUT_PORTS_START( le2 )
1684		PORT_START
1685		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1686		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1687		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1688		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1689		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 )
1690		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE2 )
1691		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1692		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1584	PORT_INCLUDE( common )
1693	1585
1694		PORT_START
1695		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1696		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1586	PORT_MODIFY("IN1")
1697	1587	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) /* for gun games */
1698		PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
1699		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1700		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1701		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1702		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1703	1588
1704		PORT_START
1705		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
1706		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
1707		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1708		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1709		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
1710		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
1711		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
1712		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
1713
1714		PORT_START
1715		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
1716		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
1717		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1718		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1719		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
1720		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
1721		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1722		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
1723
1724		PORT_START
1725		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
1726		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
1727		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
1728		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
1729		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
1730		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
1731		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
1732		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START3 )
1733
1734		PORT_START
1735		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
1736		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
1737		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
1738		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
1739		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
1740		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
1741		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
1742		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
1743
1744		PORT_START
	1589	PORT_START_TAG("DSW0")
1745	1590	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Stereo ))
1746	1591	PORT_DIPSETTING( 0x01, DEF_STR( Stereo ))
1747	1592	PORT_DIPSETTING( 0x00, DEF_STR( Mono ))
r2864	r2865
1767	1612	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1768	1613	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1769	1614
1770		PORT_START
	1615	PORT_START_TAG("DSW1")
1771	1616	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1772	1617
1773		PORT_START
	1618	PORT_START_TAG("IN6")
1774	1619	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1775	1620	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1776	1621	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) /* for gun games */
r2864	r2865
1780	1625	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1781	1626	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1782	1627
1783		PORT_START /* mask default type sens delta min max */
	1628	PORT_START_TAG("LIGHT0_X") /* mask default type sens delta min max */
1784	1629	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(15) PORT_PLAYER(1)
1785	1630
1786		PORT_START
	1631	PORT_START_TAG("LIGHT0_Y")
1787	1632	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(15) PORT_PLAYER(1)
1788	1633
1789		PORT_START
	1634	PORT_START_TAG("LIGHT1_X")
1790	1635	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(15) PORT_PLAYER(2)
1791	1636
1792		PORT_START
	1637	PORT_START_TAG("LIGHT1_Y")
1793	1638	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(15) PORT_PLAYER(2)
1794	1639	INPUT_PORTS_END
1795	1640
1796	1641	static INPUT_PORTS_START( gokuparo )
1797		PORT_START
1798		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1799		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1800		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1801		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1802		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 )
1803		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE2 )
1804		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1642	PORT_INCLUDE( common )
	1643
	1644	PORT_MODIFY("IN0")
1805	1645	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
1806	1646
1807		PORT_START
1808		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1809		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1810		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1811		PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
1812		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1813		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1814		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1815		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1816
1817		PORT_START
1818		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
1819		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
1820		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1821		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1822		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
1823		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
1824		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
1825		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
1826
1827		PORT_START
1828		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
1829		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
1830		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1831		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1832		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
1833		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
1834		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1835		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
1836
1837		PORT_START
1838		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
1839		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
1840		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
1841		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
1842		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
1843		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
1844		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
1845		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START3 )
1846
1847		PORT_START
1848		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
1849		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
1850		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
1851		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
1852		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
1853		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
1854		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
1855		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
1856
1857		PORT_START
	1647	PORT_START_TAG("DSW0")
1858	1648	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Stereo ))
1859	1649	PORT_DIPSETTING( 0x00, DEF_STR( Stereo ))
1860	1650	PORT_DIPSETTING( 0x01, DEF_STR( Mono ))
r2864	r2865
1882	1672	INPUT_PORTS_END
1883	1673
1884	1674	static INPUT_PORTS_START( puzldama )
1885		PORT_START
1886		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1887		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1888		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1889		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1890		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 )
1891		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE2 )
1892		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1675	PORT_INCLUDE( common )
	1676
	1677	PORT_MODIFY("IN0")
1893	1678	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
1894	1679
1895		PORT_START
1896		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1897		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1898		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1899		PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
1900		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1901		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1902		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1903		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1904
1905		PORT_START
1906		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
1907		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
1908		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1909		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1910		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
1911		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
1912		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
1913		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
1914
1915		PORT_START
1916		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
1917		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
1918		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1919		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1920		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
1921		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
1922		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
1923		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
1924
1925		PORT_START
1926		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
1927		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
1928		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
1929		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
1930		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
1931		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
1932		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
1933		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START3 )
1934
1935		PORT_START
1936		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
1937		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
1938		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
1939		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
1940		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
1941		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
1942		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
1943		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
1944
1945		PORT_START
	1680	PORT_START_TAG("DSW0")
1946	1681	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Stereo ))
1947	1682	PORT_DIPSETTING( 0x00, DEF_STR( Stereo ))
1948	1683	PORT_DIPSETTING( 0x01, DEF_STR( Mono ))
r2864	r2865
1971	1706	INPUT_PORTS_END
1972	1707
1973	1708	static INPUT_PORTS_START( dragoonj )
1974		PORT_START
1975		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1976		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1977		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1978		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1979		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 )
1980		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE2 )
1981		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1709	PORT_INCLUDE( common )
	1710
	1711	PORT_MODIFY("IN0")
1982	1712	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
1983	1713
1984		PORT_START
1985		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1986		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1987		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1988		PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
1989		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1990		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1991		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1992		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1993
1994		PORT_START
1995		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
1996		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
1997		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1998		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1999		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
2000		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
2001		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
2002		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
2003
2004		PORT_START
2005		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
2006		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
2007		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
2008		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
2009		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
2010		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
2011		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
2012		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
2013
2014		PORT_START
	1714	PORT_MODIFY("IN4")
2015	1715	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
2016	1716	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(1)
2017	1717	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(1)
r2864	r2865
2021	1721	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(2)
2022	1722	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
2023	1723
2024		PORT_~~START~~
	1724	PORT_MODIFY("IN5")
2025	1725	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
2026	1726	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
2027	1727	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
2031	1731	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
2032	1732	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
2033	1733
2034		PORT_START
	1734	PORT_START_TAG("DSW0")
2035	1735	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Stereo ))
2036	1736	PORT_DIPSETTING( 0x00, DEF_STR( Stereo ))
2037	1737	PORT_DIPSETTING( 0x01, DEF_STR( Mono ))
r2864	r2865
2060	1760	INPUT_PORTS_END
2061	1761
2062	1762	static INPUT_PORTS_START( type3 )
2063		PORT_START
2064		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
2065		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
2066		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
2067		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
2068		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE1 )
2069		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE2 )
2070		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1763	PORT_INCLUDE( common )
	1764
	1765	PORT_MODIFY("IN0")
2071	1766	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
2072	1767
2073		PORT_START
2074		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2075		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2076		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
2077		PORT_SERVICE_NO_TOGGLE( 0x08, IP_ACTIVE_LOW )
2078		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2079		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
2080		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2081		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2082
2083		PORT_START
2084		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
2085		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
2086		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
2087		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
2088		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
2089		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
2090		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
2091		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
2092
2093		PORT_START
2094		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
2095		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
2096		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
2097		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
2098		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
2099		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
2100		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
2101		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
2102
2103		PORT_START
2104		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
2105		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
2106		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
2107		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
2108		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
2109		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
2110		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
2111		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START3 )
2112
2113		PORT_START
2114		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
2115		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
2116		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
2117		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
2118		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
2119		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
2120		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
2121		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
2122
2123		PORT_START
	1768	PORT_START_TAG("DSW0")
2124	1769	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Stereo ))
2125	1770	PORT_DIPSETTING( 0x00, DEF_STR( Stereo ))
2126	1771	PORT_DIPSETTING( 0x01, DEF_STR( Mono ))

src/mame/drivers/thunderj.c
r2864	r2865
78	78
79	79	static READ16_HANDLER( special_port2_r )
80	80	{
81		int result = input_port_read~~_indexed~~(machine, 2);
	81	int result = input_port_read(machine, "260012");
82	82
83	83	if (atarigen_sound_to_cpu_ready) result ^= 0x0004;
84	84	if (atarigen_cpu_to_sound_ready) result ^= 0x0008;
r2864	r2865
252	252	*************************************/
253	253
254	254	static INPUT_PORTS_START( thunderj )
255		PORT_START /* 260000 */
	255	PORT_START_TAG("260000") /* 260000 */
256	256	PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED )
257	257
258		PORT_START /* 260010 */
	258	PORT_START_TAG("260010") /* 260010 */
259	259	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
260	260	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
261	261	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
r2864	r2865
265	265	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
266	266	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
267	267
268		PORT_START /* 260012 */
	268	PORT_START_TAG("260012") /* 260012 */
269	269	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_VBLANK )
270	270	PORT_SERVICE( 0x0002, IP_ACTIVE_LOW )
271	271	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNUSED ) /* Input buffer full (@260030) */
r2864	r2865
456	456	static DRIVER_INIT( thunderj )
457	457	{
458	458	atarigen_eeprom_default = NULL;
459		atarijsa_init(machine, 2, 0x0002);
	459	atarijsa_init(machine, "260012", 0x0002);
460	460	}
461	461
462	462

src/mame/drivers/segac2.c
r2864	r2865
9	9	Sega's C2 was used between 1989 and 1994, the hardware being very similar to that
10	10	used by the Sega MegaDrive/Genesis Home Console Sega produced around the same time.
11	11
	12	The Columns manual call this system 'System 14' instead of system C/C2.
	13
	14
12	15	todo: fill in protection chip data
13	16
14		Year Game Developer Protection Chip Board
15		==== ==================== ================ =============== =====
	17	Year Game Developer Protection Chip Board Number
	18	==== ==================== ================ =============== ===== ======
16	19	1989 Bloxeed Sega / Elorg n/a C
17		1990 Columns Sega 317-0149 C
	20	1990 Columns Sega 317-0149 C 171-5880B
18	21	1990 Columns II Sega 317-0160 C
19	22	1990 ThunderForce AC Sega / Technosoft 317-0172 C2
20	23	1990 Borench Sega 317-0173 C2
r2864	r2865
352	355
353	356	static READ16_HANDLER( io_chip_r )
354	357	{
	358	static const char *portnames[] = { "P1", "P2", "PORTC", "PORTD", "SERVICE", "COINAGE", "DSW", "PORTH" };
355	359	offset &= 0x1f/2;
356	360
357	361	switch (offset)
r2864	r2865
371	375
372	376	/* otherwise, return an input port */
373	377	if (offset == 0x04/2 && sound_banks)
374		return (input_port_read_indexed(machine, offset) & 0xbf) \| (upd7759_0_busy_r(machine,0) << 6);
375		return input_port_read_indexed(machine, offset);
	378	return (input_port_read(machine, portnames[offset]) & 0xbf) \| (upd7759_0_busy_r(machine,0) << 6);
	379	return input_port_read(machine, portnames[offset]);
376	380
377	381	/* 'SEGA' protection */
378	382	case 0x10/2:

src/mame/drivers/gottlieb.c
r2864	r2865
197	197
198	198	static READ8_HANDLER( gottlieb_track_0_r )
199	199	{
200		return input_port_read~~_indexed~~(machine, 2) - track[0];
	200	return input_port_read(machine, "IN2") - track[0];
201	201	}
202	202
203	203	static READ8_HANDLER( gottlieb_track_1_r )
204	204	{
205		return input_port_read~~_indexed~~(machine, 3) - track[1];
	205	return input_port_read(machine, "IN3") - track[1];
206	206	}
207	207
208	208	static WRITE8_HANDLER( gottlieb_track_reset_w )
209	209	{
210	210	/* reset the trackball counters */
211		track[0] = input_port_read_indexed(machine, 2);
212		track[1] = input_port_read_indexed(machine, 3);
	211	track[0] = input_port_read(machine, "IN2");
	212	track[1] = input_port_read(machine, "IN3");
213	213	}
214	214
215	215	static int joympx;
r2864	r2865
601	601	PORT_DIPSETTING( 0x80, "Normal Hard" )
602	602	PORT_DIPSETTING( 0xc0, DEF_STR( Hard ) )
603	603
604		PORT_START_TAG("~~DSW~~1") /* ? */
	604	PORT_START_TAG("IN1") /* ? */
605	605	PORT_SERVICE( 0x01, IP_ACTIVE_LOW )
606	606	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_SERVICE ) PORT_NAME("Select in Service Mode") PORT_CODE(KEYCODE_F1) // cycle through test options, hold to do test
607	607	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN2 )

src/mame/drivers/gpworld.c
r2864	r2865
40	40
41	41
42	42	#include "driver.h"
43		#include "deprecat.h"
44	43	#include "machine/laserdsc.h"
45	44
46	45	/* Assumed to be the same as segald hardware */
r2864	r2865
93	92	*BITMAP_ADDR32(bitmap, y, x) = color;
94	93	}
95	94
96		static void gpworld_draw_sprites(bitmap_t bitmap, const rectangle cliprect)
	95	static void gpworld_draw_sprites(running_machine machine, bitmap_t bitmap, const rectangle *cliprect)
97	96	{
98	97	const int SPR_Y_TOP = 0;
99	98	const int SPR_Y_BOTTOM = 1;
r2864	r2865
179	178	}
180	179
181	180	/* Daphne says "don't draw the pixel if it's black". */
182		draw_pixel(bitmap,cliprect,x+0,y,palette_get_color(Machine, pixel1 + (sprite_color*0x10 + 0x200)));
183		draw_pixel(bitmap,cliprect,x+1,y,palette_get_color(Machine, pixel2 + (sprite_color*0x10 + 0x200)));
184		draw_pixel(bitmap,cliprect,x+2,y,palette_get_color(Machine, pixel3 + (sprite_color*0x10 + 0x200)));
185		draw_pixel(bitmap,cliprect,x+3,y,palette_get_color(Machine, pixel4 + (sprite_color*0x10 + 0x200)));
	181	draw_pixel(bitmap,cliprect,x+0,y,palette_get_color(machine, pixel1 + (sprite_color*0x10 + 0x200)));
	182	draw_pixel(bitmap,cliprect,x+1,y,palette_get_color(machine, pixel2 + (sprite_color*0x10 + 0x200)));
	183	draw_pixel(bitmap,cliprect,x+2,y,palette_get_color(machine, pixel3 + (sprite_color*0x10 + 0x200)));
	184	draw_pixel(bitmap,cliprect,x+3,y,palette_get_color(machine, pixel4 + (sprite_color*0x10 + 0x200)));
186	185
187	186	x += 4;
188	187
r2864	r2865
207	206	fillbitmap(bitmap, 0, cliprect);
208	207
209	208	gpworld_draw_tiles(screen->machine, bitmap, cliprect);
210		gpworld_draw_sprites(bitmap, cliprect);
	209	gpworld_draw_sprites(screen->machine, bitmap, cliprect);
211	210
212	211	/* display disc information */
213	212	if (discinfo != NULL)

src/mame/drivers/homedata.c
r2864	r2865
255	255	static READ8_HANDLER( mrokumei_keyboard_r )
256	256	{
257	257	int res = 0x3f,i;
	258	static const char *keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
258	259
259	260	/* offset 0 is player 1, offset 1 player 2 (not supported) */
260	261	if (offset == 0)
r2864	r2865
263	264	{
264	265	if (keyb & (1 << i))
265	266	{
266		res = input_port_read~~_indexed~~(machine, 3+i) & 0x3f;
	267	res = input_port_read(machine, keynames[i]) & 0x3f;
267	268	break;
268	269	}
269	270	}
r2864	r2865
397	398
398	399	static READ8_HANDLER( reikaids_io_r )
399	400	{
400		int res = input_port_read~~_indexed~~(machine, 2); // bit 4 = coin, bit 5 = service
	401	int res = input_port_read(machine, "IN2"); // bit 4 = coin, bit 5 = service
401	402
402	403	res \|= BIT(upd7807_portc,2) * 0x01; // bit 0 = upd7807 status
403	404	res \|= BIT(upd7807_portc,6) * 0x02; // bit 1 = upd7807 data
r2864	r2865
467	468
468	469	static READ8_HANDLER( pteacher_keyboard_r )
469	470	{
470		int dips = input_port_read_indexed(machine, 0);
	471	static const char *keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4", "KEY5" };
	472	int dips = input_port_read(machine, "DSW");
471	473
472	474	// logerror("%04x: keyboard_r with port A = %02x\n",activecpu_get_pc(),upd7807_porta);
473	475
r2864	r2865
475	477	{
476	478	/* player 1 + dip switches */
477	479	int row = (upd7807_porta & 0x07);
478		return input_port_read~~_indexed~~(machine, ~~2 +~~ row) \| (((dips >> row) & 1) << 5); // 0-5
	480	return input_port_read(machine, keynames[row]) \| (((dips >> row) & 1) << 5); // 0-5
479	481	}
480	482	if (upd7807_porta & 0x08)
481	483	{
r2864	r2865
571	573	AM_RANGE(0x7000, 0x77ff) AM_READ(SMH_RAM) /* hourouki expects this to act as RAM */
572	574	AM_RANGE(0x7800, 0x7800) AM_READ(SMH_RAM) /* only used to store the result of the ROM check */
573	575	AM_RANGE(0x7801, 0x7802) AM_READ(mrokumei_keyboard_r) // also vblank and active page
574		AM_RANGE(0x7803, 0x7803) AM_READ(input_port_2_r) // coin, service
575		AM_RANGE(0x7804, 0x7804) AM_READ(input_port_0_r) // DSW1
576		AM_RANGE(0x7805, 0x7805) AM_READ(input_port_1_r) // DSW2
	576	AM_RANGE(0x7803, 0x7803) AM_READ_PORT("IN0") // coin, service
	577	AM_RANGE(0x7804, 0x7804) AM_READ_PORT("DSW1") // DSW1
	578	AM_RANGE(0x7805, 0x7805) AM_READ_PORT("DSW2") // DSW2
577	579	AM_RANGE(0x7ffe, 0x7ffe) AM_READ(SMH_NOP) // ??? read every vblank, value discarded
578	580	AM_RANGE(0x8000, 0xffff) AM_READ(SMH_ROM)
579	581	ADDRESS_MAP_END
r2864	r2865
619	621	AM_RANGE(0x4000, 0x5fff) AM_READ(SMH_RAM)
620	622	AM_RANGE(0x6000, 0x6fff) AM_READ(SMH_RAM) /* work ram */
621	623	AM_RANGE(0x7800, 0x7800) AM_READ(SMH_RAM)
622		AM_RANGE(0x7801, 0x7801) AM_READ(input_port_0_r)
623		AM_RANGE(0x7802, 0x7802) AM_READ(input_port_1_r)
	624	AM_RANGE(0x7801, 0x7801) AM_READ_PORT("IN0")
	625	AM_RANGE(0x7802, 0x7802) AM_READ_PORT("IN1")
624	626	AM_RANGE(0x7803, 0x7803) AM_READ(reikaids_io_r) // coin, blitter, upd7807
625	627	AM_RANGE(0x8000, 0xbfff) AM_READ(SMH_BANK1)
626	628	AM_RANGE(0xc000, 0xffff) AM_READ(SMH_ROM)
r2864	r2865
707	709	static ADDRESS_MAP_START( pteacher_upd7807_readport, ADDRESS_SPACE_IO, 8 )
708	710	AM_RANGE(UPD7807_PORTA, UPD7807_PORTA) AM_READ(pteacher_upd7807_porta_r)
709	711	AM_RANGE(UPD7807_PORTT, UPD7807_PORTT) AM_READ(pteacher_keyboard_r)
710		AM_RANGE(UPD7807_PORTC, UPD7807_PORTC) AM_READ~~(input~~_~~port_1_r~~)
	712	AM_RANGE(UPD7807_PORTC, UPD7807_PORTC) AM_READ_PORT("COIN")
711	713	ADDRESS_MAP_END
712	714
713	715	static ADDRESS_MAP_START( pteacher_upd7807_writeport, ADDRESS_SPACE_IO, 8 )
r2864	r2865
721	723
722	724
723	725	static INPUT_PORTS_START( mjhokite )
724		PORT_START
	726	PORT_START_TAG("DSW1")
725	727	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
726	728	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
727	729	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
746	748	PORT_DIPSETTING( 0x20, "7" )
747	749	PORT_DIPSETTING( 0x00, "8 (hardest)" )
748	750
749		PORT_START
	751	PORT_START_TAG("DSW2")
750	752	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
751	753	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
752	754	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r2864	r2865
772	774	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
773	775	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
774	776
775		PORT_START
	777	PORT_START_TAG("IN0")
776	778	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
777	779	PORT_DIPNAME( 0x02, 0x02, "Freeze?" )
778	780	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
r2864	r2865
784	786	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
785	787	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
786	788
787		PORT_START
788		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
789		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
790		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
791		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M )
792		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
	789	PORT_START_TAG("KEY0")
	790	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
	791	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
	792	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
	793	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M )
	794	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
793	795	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
794	796
795		PORT_START
796		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
797		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
798		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
799		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N )
800		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
801		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
	797	PORT_START_TAG("KEY1")
	798	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
	799	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
	800	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
	801	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N )
	802	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
	803	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
802	804
803		PORT_START
804		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
805		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
806		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
807		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
808		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
	805	PORT_START_TAG("KEY2")
	806	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
	807	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
	808	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
	809	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
	810	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
809	811	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
810	812
811		PORT_START
812		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
813		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
814		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
815		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
	813	PORT_START_TAG("KEY3")
	814	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
	815	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
	816	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
	817	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
816	818	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
817	819	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
818	820
819		PORT_START
	821	PORT_START_TAG("KEY4")
820	822	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
821	823	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
822	824	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
823		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
	825	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
824	826	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
825	827	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
826	828	INPUT_PORTS_END
827	829
828	830	static INPUT_PORTS_START( reikaids )
829		PORT_START // IN0 - 0x7801
	831	PORT_START_TAG("IN0") // IN0 - 0x7801
830	832	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(1)
831	833	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(1)
832	834	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(1)
r2864	r2865
836	838	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) /* jump */
837	839	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
838	840
839		PORT_START // IN1 - 0x7802
	841	PORT_START_TAG("IN1") // IN1 - 0x7802
840	842	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(2)
841	843	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(2)
842	844	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(2)
r2864	r2865
846	848	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) /* jump */
847	849	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
848	850
849		PORT_START // IN2 - 0x7803
	851	PORT_START_TAG("IN2") // IN2 - 0x7803
850	852	PORT_BIT( 0x01, IP_ACTIVE_HIGH,IPT_SPECIAL ) /* coprocessor status */
851	853	PORT_BIT( 0x02, IP_ACTIVE_HIGH,IPT_SPECIAL ) /* coprocessor data */
852	854	PORT_BIT( 0x04, IP_ACTIVE_HIGH,IPT_SPECIAL ) /* vblank */
r2864	r2865
856	858	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
857	859	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
858	860
859		PORT_START // DSW1
	861	PORT_START_TAG("DSW1") // DSW1
860	862	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Allow_Continue ) )
861	863	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
862	864	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
r2864	r2865
880	882	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
881	883	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
882	884
883		PORT_START // DSW2
	885	PORT_START_TAG("DSW2") // DSW2
884	886	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
885	887	PORT_DIPSETTING( 0x03, DEF_STR( Easy ) )
886	888	PORT_DIPSETTING( 0x02, DEF_STR( Normal ) )
r2864	r2865
907	909	INPUT_PORTS_END
908	910
909	911	static INPUT_PORTS_START( battlcry )
910		PORT_START // IN0 - 0x7801
911		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(1)
912		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(1)
913		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(1)
914		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(1)
915		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) /* punch */
916		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) /* kick */
917		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) /* jump */
918		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
	912	PORT_INCLUDE( reikaids )
919	913
920		PORT_START // IN1 - 0x7802
921		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(2)
922		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(2)
923		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(2)
924		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(2)
925		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) /* punch */
926		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) /* kick */
927		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) /* jump */
928		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
929
930		PORT_START // IN2 - 0x7803
931		PORT_BIT( 0x01, IP_ACTIVE_HIGH,IPT_SPECIAL ) /* coprocessor status */
932		PORT_BIT( 0x02, IP_ACTIVE_HIGH,IPT_SPECIAL ) /* coprocessor data */
933		PORT_BIT( 0x04, IP_ACTIVE_HIGH,IPT_SPECIAL ) /* vblank */
934		PORT_BIT( 0x08, IP_ACTIVE_HIGH,IPT_SPECIAL ) /* visible page */
935		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
936		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 )
937		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
938		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
939
940		PORT_START // DSW1
	914	PORT_MODIFY("DSW1")
941	915	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Allow_Continue ) )
942	916	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
943	917	PORT_DIPSETTING( 0x02, "Up To Stage 1" )
r2864	r2865
958	932	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
959	933	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
960	934
961		PORT_START // DSW2
962		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
963		PORT_DIPSETTING( 0x03, DEF_STR( Easy ) )
964		PORT_DIPSETTING( 0x02, DEF_STR( Normal ) )
965		PORT_DIPSETTING( 0x01, DEF_STR( Hard ) )
966		PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
	935	PORT_MODIFY("DSW2")
967	936	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Demo_Sounds ) )
968	937	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
969	938	PORT_DIPSETTING( 0x04, DEF_STR( On ) )
r2864	r2865
982	951	PORT_DIPSETTING( 0xa0, DEF_STR( 1C_3C ) )
983	952	PORT_DIPSETTING( 0x20, DEF_STR( 1C_4C ) )
984	953	PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
985
986	954	INPUT_PORTS_END
987	955
988	956
	957	static INPUT_PORTS_START( mj_keyboard )
	958	PORT_START_TAG("KEY0")
	959	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
	960	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_B )
	961	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_C )
	962	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_D )
	963	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	964	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately) */
	965	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
989	966
	967	PORT_START_TAG("KEY1")
	968	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_E )
	969	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
	970	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_G )
	971	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_H )
	972	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	973	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately) */
	974	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
990	975
991		#define MJ_KEYBOARD \
992		PORT_START \
993		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) \
994		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_B ) \
995		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_C ) \
996		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_D ) \
997		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
998		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately */ \
999		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED ) \
1000		\
1001		PORT_START \
1002		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_E ) \
1003		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) \
1004		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_G ) \
1005		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_H ) \
1006		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1007		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately */ \
1008		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED ) \
1009		\
1010		PORT_START \
1011		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_I ) \
1012		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_J ) \
1013		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) \
1014		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_L ) \
1015		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1016		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately */ \
1017		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED ) \
1018		\
1019		PORT_START \
1020		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_M ) \
1021		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_N ) \
1022		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) \
1023		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) \
1024		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) \
1025		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately */ \
1026		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED ) \
1027		\
1028		PORT_START \
1029		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) \
1030		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) \
1031		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) \
1032		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1033		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1034		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately */ \
1035		PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED ) \
1036		\
1037		PORT_START \
1038		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) \
1039		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) \
1040		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1041		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1042		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1043		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately */ \
	976	PORT_START_TAG("KEY2")
	977	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_I )
	978	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_J )
	979	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
	980	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_L )
	981	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	982	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately) */
1044	983	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
1045	984
	985	PORT_START_TAG("KEY3")
	986	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_M )
	987	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_N )
	988	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
	989	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
	990	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
	991	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately) */
	992	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
1046	993
	994	PORT_START_TAG("KEY4")
	995	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
	996	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
	997	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
	998	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	999	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1000	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately) */
	1001	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
	1002
	1003	PORT_START_TAG("KEY5")
	1004	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
	1005	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
	1006	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1007	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1008	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1009	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* dip switch (handled separately) */
	1010	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
	1011	INPUT_PORTS_END
	1012
1047	1013	static INPUT_PORTS_START( pteacher )
1048		PORT_START /* dip switches (handled by pteacher_keyboard_r) */
	1014	PORT_START_TAG("DSW") /* dip switches (handled by pteacher_keyboard_r) */
1049	1015	PORT_DIPNAME( 0x0001, 0x0000, DEF_STR( Demo_Sounds ) )
1050	1016	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
1051	1017	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
1082	1048	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
1083	1049	PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNUSED )
1084	1050
1085		PORT_START
	1051	PORT_START_TAG("COIN")
1086	1052	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1087	1053	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
1088	1054	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
1089	1055
1090		~~MJ_KEYB~~OARD
	1056	PORT_INCLUDE( mj_keyboard )
1091	1057	INPUT_PORTS_END
1092	1058
1093	1059	static INPUT_PORTS_START( jogakuen )
1094		PORT_START /* dip switches (handled by pteacher_keyboard_r) */
	1060	PORT_START_TAG("DSW") /* dip switches (handled by pteacher_keyboard_r) */
1095	1061	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
1096	1062	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
1097	1063	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
1128	1094	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
1129	1095	PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNUSED )
1130	1096
1131		PORT_START
	1097	PORT_START_TAG("COIN")
1132	1098	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1133	1099	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
1134	1100	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
1135	1101
1136		~~MJ_KEYB~~OARD
	1102	PORT_INCLUDE( mj_keyboard )
1137	1103	INPUT_PORTS_END
1138	1104
1139	1105	static INPUT_PORTS_START( mjikaga )
1140		PORT_START /* dip switches (handled by pteacher_keyboard_r) */
	1106	PORT_START_TAG("DSW") /* dip switches (handled by pteacher_keyboard_r) */
1141	1107	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unknown ) )
1142	1108	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
1143	1109	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
r2864	r2865
1174	1140	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
1175	1141	PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNUSED )
1176	1142
1177		PORT_START
	1143	PORT_START_TAG("COIN")
1178	1144	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1179	1145	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
1180	1146	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
1181	1147
1182		~~MJ_KEYB~~OARD
	1148	PORT_INCLUDE( mj_keyboard )
1183	1149	INPUT_PORTS_END
1184	1150
1185	1151

src/mame/drivers/imolagp.c
r2864	r2865
130	130	static int imola_draw_mode;
131	131
132	132	static void
133		InitializeColors( void )
	133	InitializeColors( running_machine *machine )
134	134	{ /* optional runtime remapping of colors */
135	135	static const UINT8 color[0x10][3] =
136	136	{ /* wrong! need color-accurate screenshots to fix */
r2864	r2865
154	154	int i;
155	155	for( i=0; i<0x10; i++ )
156	156	{
157		palette_set_color_rgb( Machine,i*2+0,0,0,0 );
158		palette_set_color_rgb( Machine,i*2+1,color[i][0],color[i][1],color[i][2] );
	157	palette_set_color_rgb( machine,i*2+0,0,0,0 );
	158	palette_set_color_rgb( machine,i*2+1,color[i][0],color[i][1],color[i][2] );
159	159	}
160	160	}
161	161
r2864	r2865
167	167	imola_videoram[i] = auto_malloc(0x4000);
168	168	memset( imola_videoram[i], 0x00, 0x4000 );
169	169	}
170		InitializeColors();
	170	InitializeColors(machine);
171	171	}
172	172
173	173
r2864	r2865
323	323	static ADDRESS_MAP_START( imolagp_master, ADDRESS_SPACE_PROGRAM, 8 )
324	324	AM_RANGE(0x0000, 0x1fff) AM_READ(SMH_ROM)
325	325	AM_RANGE(0x2000, 0x23ff) AM_READ(SMH_RAM) AM_WRITE(SMH_RAM)
326		AM_RANGE(0x2800, 0x2800) AM_READ~~(input~~_~~port_~~2_r) /* gas */
	326	AM_RANGE(0x2800, 0x2800) AM_READ_PORT("2800") /* gas */
327	327	AM_RANGE(0x2802, 0x2802) AM_READ(steerlatch_r) AM_WRITE(SMH_NOP)
328	328	/* AM_RANGE(0x2803, 0x2803) ? */
329	329	AM_RANGE(0x3000, 0x3000) AM_WRITE(vreg_control_w)
r2864	r2865
331	331	/* AM_RANGE(0x37f7, 0x37f7) ? */
332	332	AM_RANGE(0x3800, 0x3800) AM_WRITE(vreg_data_w)
333	333	AM_RANGE(0x3810, 0x3810) AM_WRITE(AY8910_write_port_0_w)
334		AM_RANGE(0x4000, 0x4000) AM_READ~~( input~~_~~port_0_r~~ ) /* DSWA */
	334	AM_RANGE(0x4000, 0x4000) AM_READ_PORT("DSWA") /* DSWA */
335	335	AM_RANGE(0x5000, 0x50ff) AM_WRITE(imola_ledram_w)
336	336	AM_RANGE(0x47ff, 0x4800) AM_WRITE(transmit_data_w)
337		AM_RANGE(0x6000, 0x6000) AM_READ~~( input~~_~~port_1_r~~ ) /* DSWB */
	337	AM_RANGE(0x6000, 0x6000) AM_READ_PORT("DSWB") /* DSWB */
338	338	ADDRESS_MAP_END
339	339
340	340	static ADDRESS_MAP_START( readport_slave, ADDRESS_SPACE_IO, 8 )
r2864	r2865
371	371	else
372	372	{
373	373	static int oldsteer;
374		int newsteer = input_port_read~~_indexed~~(machine, 3)&0xf;
	374	int newsteer = input_port_read(machine, "2802") & 0xf;
375	375	if( newsteer!=oldsteer )
376	376	{
377	377	if( imola_steerlatch==0 )
r2864	r2865
486	486	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
487	487	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
488	488
489		PORT_START /* 2800 / / speed: 08 00 0F 1C 0F 00 1E 3D */
	489	PORT_START_TAG("2800") /* 2800 / / speed: 08 00 0F 1C 0F 00 1E 3D */
490	490	// PORT_DIPNAME( 0x03, 0x03, "Pedal" )
491	491	// PORT_DIPSETTING( 0x01, "STOPPED" )
492	492	// PORT_DIPSETTING( 0x00, "SLOW" )
r2864	r2865
502	502	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 )
503	503	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
504	504
505		PORT_START /* 2802 */
	505	PORT_START_TAG("2802") /* 2802 */
506	506	PORT_BIT( 0x0f, 0x00, IPT_DIAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(1) PORT_PLAYER(1)
507	507	INPUT_PORTS_END
508	508

src/mame/drivers/puckpkmn.c
r2864	r2865
18	18	static UINT16* main_ram;
19	19
20	20	static INPUT_PORTS_START( puckpkmn ) /* Puckman Pockimon Input Ports */
21		PORT_START /* Player 2 Controls ($700011.b) */
	21	PORT_START_TAG("P2") /* Player 2 Controls ($700011.b) */
22	22	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
23	23	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
24	24	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
r2864	r2865
28	28	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
29	29	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
30	30
31		PORT_START /* Player 1 Controls ($700013.b) */
	31	PORT_START_TAG("P1") /* Player 1 Controls ($700013.b) */
32	32	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
33	33	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(10)
34	34	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r2864	r2865
38	38	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
39	39	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
40	40
41		PORT_START /* ? ($700015.b) */
	41	PORT_START_TAG("IN0") /* ? ($700015.b) */
42	42
43		PORT_START /* DSW 1 ($700017.b) */
	43	PORT_START_TAG("DSW1") /* DSW 1 ($700017.b) */
44	44	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
45	45	PORT_DIPSETTING( 0x03, DEF_STR( 5C_1C ) )
46	46	PORT_DIPSETTING( 0x04, DEF_STR( 4C_1C ) )
r2864	r2865
65	65	PORT_DIPSETTING( 0x40, DEF_STR( Hard ) )
66	66	PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
67	67
68		PORT_START /* DSW 1 ($700019.b) */
	68	PORT_START_TAG("DSW2") /* DSW 1 ($700019.b) */
69	69	PORT_SERVICE( 0x01, IP_ACTIVE_LOW )
70	70	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Demo_Sounds ) )
71	71	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )

src/mame/drivers/kinstb.c
r2864	r2865
43	43	//check coins
44	44	static INT32 oldinput=0;
45	45	INT32 coincnt;
46		#ifdef MAME_DEBUG
47		INT32 input=input_port_read_indexed(machine, 13);
48		#else
49		INT32 input=input_port_read_indexed(machine, 10);
50		#endif
	46	INT32 input = input_port_read(machine, "COIN");
51	47
52	48	if(input&3)
53	49	{
r2864	r2865
99	95	ADDRESS_MAP_END
100	96
101	97	static INPUT_PORTS_START( kinstb )
102		PORT_START /* IN 0 : Joypad 1 - L */
	98	PORT_START_TAG("PAD1L") /* IN 0 : Joypad 1 - L */
103	99	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("P1 Button A") PORT_PLAYER(1)
104	100	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("P1 Button X") PORT_PLAYER(1)
105	101	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("P1 Button L") PORT_PLAYER(1)
106	102	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("P1 Button R") PORT_PLAYER(1)
107		PORT_START /* IN 1 : Joypad 1 - H */
	103	PORT_START_TAG("PAD1H") /* IN 1 : Joypad 1 - H */
108	104	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P1 Button B") PORT_PLAYER(1)
109	105	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P1 Button Y") PORT_PLAYER(1)
110	106	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE1 ) PORT_NAME("P1 Select")
r2864	r2865
114	110	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
115	111	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
116	112
117		PORT_START /* IN 2 : Joypad 2 - L */
	113	PORT_START_TAG("PAD2L") /* IN 2 : Joypad 2 - L */
118	114	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("P2 Button A") PORT_PLAYER(2)
119	115	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("P2 Button X") PORT_PLAYER(2)
120	116	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("P2 Button L") PORT_PLAYER(2)
121	117	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("P2 Button R") PORT_PLAYER(2)
122		PORT_START /* IN 3 : Joypad 2 - H */
	118	PORT_START_TAG("PAD2H") /* IN 3 : Joypad 2 - H */
123	119	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P2 Button B") PORT_PLAYER(2)
124	120	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P2 Button Y") PORT_PLAYER(2)
125	121	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE2 ) PORT_NAME("P2 Select")
r2864	r2865
129	125	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
130	126	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
131	127
132		PORT_START /* IN 4 : Joypad 3 - L */
	128	PORT_START_TAG("PAD3L") /* IN 4 : Joypad 3 - L */
133	129	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("P3 Button A") PORT_PLAYER(3)
134	130	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("P3 Button X") PORT_PLAYER(3)
135	131	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("P3 Button L") PORT_PLAYER(3)
136	132	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("P3 Button R") PORT_PLAYER(3)
137		PORT_START /* IN 5 : Joypad 3 - H */
	133	PORT_START_TAG("PAD3H") /* IN 5 : Joypad 3 - H */
138	134	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P3 Button B") PORT_PLAYER(3)
139	135	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P3 Button Y") PORT_PLAYER(3)
140	136	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE3 ) PORT_NAME("P3 Select")
r2864	r2865
144	140	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(3)
145	141	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(3)
146	142
147		PORT_START /* IN 6 : Joypad 4 - L */
	143	PORT_START_TAG("PAD4L") /* IN 6 : Joypad 4 - L */
148	144	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("P4 Button A") PORT_PLAYER(4)
149	145	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("P4 Button X") PORT_PLAYER(4)
150	146	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("P4 Button L") PORT_PLAYER(4)
151	147	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("P4 Button R") PORT_PLAYER(4)
152		PORT_START /* IN 7 : Joypad 4 - H */
	148	PORT_START_TAG("PAD4H") /* IN 7 : Joypad 4 - H */
153	149	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P4 Button B") PORT_PLAYER(4)
154	150	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P4 Button Y") PORT_PLAYER(4)
155	151	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE4 ) PORT_NAME("P4 Select")
r2864	r2865
159	155	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(4)
160	156	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(4)
161	157
162		PORT_START /* IN 8 : Internal switches */
	158	PORT_START_TAG("INTERNAL") /* IN 8 : Internal switches */
163	159	PORT_DIPNAME( 0x1, 0x1, "Enforce 32 sprites/line" )
164	160	PORT_DIPSETTING( 0x0, DEF_STR( No ) )
165	161	PORT_DIPSETTING( 0x1, DEF_STR( Yes ) )
166	162
167	163	#ifdef MAME_DEBUG
168		PORT_START /* IN 9 : debug switches */
	164	PORT_START_TAG("DEBUG1") /* IN 9 : debug switches */
169	165	PORT_DIPNAME( 0x3, 0x0, "Browse tiles" )
170	166	PORT_DIPSETTING( 0x0, DEF_STR( Off ) )
171	167	PORT_DIPSETTING( 0x1, "2bpl" )
r2864	r2865
177	173	PORT_DIPSETTING( 0x8, "4bpl" )
178	174	PORT_DIPSETTING( 0xc, "8bpl" )
179	175
180		PORT_START /* IN 10 : debug switches */
	176	PORT_START_TAG("DEBUG2") /* IN 10 : debug switches */
181	177	PORT_BIT( 0x1, IP_ACTIVE_HIGH, IPT_BUTTON7 ) PORT_NAME("Toggle BG 1") PORT_PLAYER(2)
182	178	PORT_BIT( 0x2, IP_ACTIVE_HIGH, IPT_BUTTON8 ) PORT_NAME("Toggle BG 2") PORT_PLAYER(2)
183	179	PORT_BIT( 0x4, IP_ACTIVE_HIGH, IPT_BUTTON9 ) PORT_NAME("Toggle BG 3") PORT_PLAYER(2)
r2864	r2865
187	183	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON9 ) PORT_NAME("Toggle Back col") PORT_PLAYER(3)
188	184	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON10 ) PORT_NAME("Toggle Windows") PORT_PLAYER(3)
189	185
190		PORT_START /* IN 11 : debug input */
	186	PORT_START_TAG("DEBUG3") /* IN 11 : debug input */
191	187	PORT_BIT( 0x1, IP_ACTIVE_HIGH, IPT_BUTTON9 ) PORT_NAME("Pal prev")
192	188	PORT_BIT( 0x2, IP_ACTIVE_HIGH, IPT_BUTTON10 ) PORT_NAME("Pal next")
193	189	PORT_BIT( 0x4, IP_ACTIVE_HIGH, IPT_BUTTON7 ) PORT_NAME("Toggle Transparency") PORT_PLAYER(4)
194	190	#endif
195	191
196		PORT_START /* IN 12 : dip-switches */
	192	PORT_START_TAG("DSW") /* IN 12 : dip-switches */
197	193
198		PORT_START /* IN 13 : coins */
	194	PORT_START_TAG("COIN") /* IN 13 : coins */
199	195	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
200	196	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )
201	197

src/mame/drivers/eolith16.c
r2864	r2865
45	45	static READ16_HANDLER( eolith16_custom_r )
46	46	{
47	47	eolith_speedup_read();
48		return (input_port_read~~_indexed~~(machine, 0) & ~0x10) \| (eeprom_read_bit() << 4);
	48	return (input_port_read(machine, "IN0") & ~0x10) \| (eeprom_read_bit() << 4);
49	49	}
50	50
51	51
r2864	r2865
75	75	ADDRESS_MAP_END
76	76
77	77	static INPUT_PORTS_START( eolith16 )
78		PORT_START
	78	PORT_START_TAG("IN0")
79	79	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_SPECIAL ) // eeprom bit
80	80	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_SPECIAL ) PORT_CUSTOM(eolith_speedup_getvblank, 0)
81	81	PORT_BIT( 0xff6f, IP_ACTIVE_LOW, IPT_UNUSED )
82	82
83		PORT_START
	83	PORT_START_TAG("IN1")
84	84	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
85	85	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNUSED )
86	86	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_START1 )
r2864	r2865
90	90	PORT_SERVICE_NO_TOGGLE( 0x0040, IP_ACTIVE_LOW )
91	91	PORT_BIT( 0xff80, IP_ACTIVE_LOW, IPT_UNUSED )
92	92
93		PORT_START
	93	PORT_START_TAG("IN2")
94	94	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
95	95	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
96	96	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)

src/mame/drivers/groundfx.c
r2864	r2865
163	163	{
164	164	case 0x00:
165	165	{
166		return (input_port_read~~_indexed~~(machine,0) << 16) \| input_port_read~~_indexed~~(machine,1) \|
	166	return (input_port_read(machine, "IN0") << 16) \| input_port_read(machine, "IN1") \|
167	167	(eeprom_read_bit() << 7) \| frame_counter;
168	168	}
169	169
170	170	case 0x01:
171	171	{
172		return input_port_read~~_indexed~~(machine,2) \| (coin_word << 16);
	172	return input_port_read(machine, "IN2") \| (coin_word << 16);
173	173	}
174	174	}
175	175
r2864	r2865
214	214
215	215	static READ32_HANDLER( groundfx_adc_r )
216	216	{
217		return (input_port_read~~_indexed~~(machine,3) << 8) \| input_port_read~~_indexed~~(machine,4);
	217	return (input_port_read(machine, "AN0") << 8) \| input_port_read(machine, "AN1");
218	218	}
219	219
220	220	static WRITE32_HANDLER( groundfx_adc_w )
r2864	r2865
280	280	AM_RANGE(0x200000, 0x21ffff) AM_WRITE(SMH_RAM) AM_BASE(&groundfx_ram)
281	281	AM_RANGE(0x300000, 0x303fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram32) AM_SIZE(&spriteram_size)
282	282	AM_RANGE(0x400000, 0x400003) AM_WRITE(motor_control_w) /* gun vibration */
283		AM_RANGE(0x500000, 0x500007) AM_WRITE(groundfx_input_w) /* eerom etc. */
	283	AM_RANGE(0x500000, 0x500007) AM_WRITE(groundfx_input_w) /* eeprom etc. */
284	284	AM_RANGE(0x600000, 0x600003) AM_WRITE(groundfx_adc_w)
285	285	AM_RANGE(0x700000, 0x7007ff) AM_WRITE(SMH_RAM) AM_BASE(&f3_shared_ram)
286	286	AM_RANGE(0x800000, 0x80ffff) AM_WRITE(TC0480SCP_long_w) /* tilemaps */
r2864	r2865
298	298	***********************************************************/
299	299
300	300	static INPUT_PORTS_START( groundfx )
301		PORT_START /* IN0 */
	301	PORT_START_TAG("IN0") /* IN0 */
302	302	PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED )
303	303
304		PORT_START /* IN1 */
	304	PORT_START_TAG("IN1") /* IN1 */
305	305	PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* Frame counter */
306	306	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNUSED )
307	307	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
319	319	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
320	320	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNUSED )
321	321
322		PORT_START /* IN2 */
	322	PORT_START_TAG("IN2") /* IN2 */
323	323	PORT_SERVICE_NO_TOGGLE( 0x01, IP_ACTIVE_LOW )
324	324	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
325	325	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 )
r2864	r2865
329	329	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
330	330	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
331	331
332		PORT_START /* IN 2, steering wheel */
	332	PORT_START_TAG("AN0") /* IN 2, steering wheel */
333	333	PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(15) PORT_REVERSE PORT_PLAYER(1)
334	334
335		PORT_START /* IN 3, accel */
	335	PORT_START_TAG("AN1") /* IN 3, accel */
336	336	PORT_BIT( 0xff, 0xff, IPT_AD_STICK_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_PLAYER(1)
337	337
338		PORT_START /* IN 4, sound volume */
	338	PORT_START_TAG("AN2") /* IN 4, sound volume */
339	339	PORT_BIT( 0xff, 0x00, IPT_AD_STICK_X ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(2)
340	340
341		PORT_START /* IN 5, unknown */
	341	PORT_START_TAG("AN3") /* IN 5, unknown */
342	342	PORT_BIT( 0xff, 0x00, IPT_AD_STICK_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_PLAYER(2)
343	343	INPUT_PORTS_END
344	344

src/mame/drivers/gamecstl.c
r2864	r2865
726	726	{
727	727	bios_ram = auto_malloc(0x10000);
728	728
729		init_pc_common(PCCOMMON_KEYBOARD_AT, gamecstl_set_keyb_int);
	729	init_pc_common(machine, PCCOMMON_KEYBOARD_AT, gamecstl_set_keyb_int);
730	730	mc146818_init(MC146818_STANDARD);
731	731
732	732	intel82439tx_init();

src/mame/drivers/m92.c
r2864	r2865
189	189	*****************************************************************************/
190	190
191	191	#include "driver.h"
192		#include "deprecat.h"
193	192	#include "includes/m92.h"
194	193	#include "drivers/m92.h"
195	194	#include "machine/irem_cpu.h"
r2864	r2865
952	951
953	952	/***************************************************************************/
954	953
955		void m92_sprite_interrupt(void)
	954	void m92_sprite_interrupt(running_machine *machine)
956	955	{
957		cpunum_set_input_line_and_vector(Machine, 0, 0, HOLD_LINE, M92_IRQ_1);
	956	cpunum_set_input_line_and_vector(machine, 0, 0, HOLD_LINE, M92_IRQ_1);
958	957	}
959	958
960	959	static MACHINE_DRIVER_START( m92 )

src/mame/drivers/hal21.c
r2864	r2865
450	450	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
451	451	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
452	452
453		PORT_START_TAG("DSW0")
	453	PORT_START_TAG("DSW1")
454	454	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Allow_Continue ) )
455	455	PORT_DIPSETTING( 0x01, DEF_STR( No ) )
456	456	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
r2864	r2865
475	475	PORT_DIPSETTING( 0x40, "100k 200k" )
476	476	PORT_DIPSETTING( 0x00, DEF_STR( None ) )
477	477
478		PORT_START_TAG("DSW1")
	478	PORT_START_TAG("DSW2")
479	479	PORT_DIPNAME( 0x01, 0x01, "Bonus Occurrence" )
480	480	PORT_DIPSETTING( 0x01, "1st & every 2nd" )
481	481	PORT_DIPSETTING( 0x00, "1st & 2nd only" )
r2864	r2865
550	550
551	551	static READ8_HANDLER( CPUC_ready_r ) { snk_sound_busy_bit = 0; return 0; }
552	552
553		static READ8_HANDLER( hal21_input_port_0_r ) { return input_port_read~~_indexed~~(machine, 0) \| snk_sound_busy_bit; }
	553	static READ8_HANDLER( hal21_input_port_0_r ) { return input_port_read(machine, "IN0") \| snk_sound_busy_bit; }
554	554
555	555	static WRITE8_HANDLER( hal21_soundcommand_w ) { hal21_sound_scheduler(machine, 1, data); }
556	556	static WRITE8_HANDLER( hal21_soundack_w ) { hal21_sound_scheduler(machine,2, data); }
r2864	r2865
611	611
612	612	static ADDRESS_MAP_START( aso_cpuA_map, ADDRESS_SPACE_PROGRAM, 8 )
613	613	AM_RANGE(0x0000, 0xbfff) AM_ROM
614		AM_RANGE(0xc000, 0xc000) AM_READ(hal21_input_port_0_r) /* coin, start */
615		AM_RANGE(0xc100, 0xc100) AM_READ(input_port_1_r) /* P1 */
616		AM_RANGE(0xc200, 0xc200) AM_READ(input_port_2_r) /* P2 */
	614	AM_RANGE(0xc000, 0xc000) AM_READ(hal21_input_port_0_r) /* coin, start */
	615	AM_RANGE(0xc100, 0xc100) AM_READ_PORT("IN1") /* P1 */
	616	AM_RANGE(0xc200, 0xc200) AM_READ_PORT("IN2") /* P2 */
617	617	AM_RANGE(0xc400, 0xc400) AM_WRITE(aso_soundcommand_w)
618		AM_RANGE(0xc500, 0xc500) AM_READ(input_port_3_r) /* DSW1 */
619		AM_RANGE(0xc600, 0xc600) AM_READ(input_port_4_r) /* DSW2 */
	618	AM_RANGE(0xc500, 0xc500) AM_READ_PORT("DSW1") /* DSW1 */
	619	AM_RANGE(0xc600, 0xc600) AM_READ_PORT("DSW2") /* DSW2 */
620	620	AM_RANGE(0xc700, 0xc700) AM_READWRITE(snk_cpuB_nmi_trigger_r, snk_cpuA_nmi_ack_w)
621	621	AM_RANGE(0xc800, 0xc800) AM_WRITE(hal21_vreg1_w)
622	622	AM_RANGE(0xc900, 0xc900) AM_WRITE(hal21_vreg2_w)
r2864	r2865
646	646
647	647	static ADDRESS_MAP_START( hal21_cpuA_map, ADDRESS_SPACE_PROGRAM, 8 )
648	648	AM_RANGE(0x0000, 0x7fff) AM_ROM
649		AM_RANGE(0xc000, 0xc000) AM_READ(hal21_input_port_0_r) /* coin, start */
650		AM_RANGE(0xc100, 0xc100) AM_READ(input_port_1_r) /* P1 */
651		AM_RANGE(0xc200, 0xc200) AM_READ(input_port_2_r) /* P2 */
	649	AM_RANGE(0xc000, 0xc000) AM_READ(hal21_input_port_0_r) /* coin, start */
	650	AM_RANGE(0xc100, 0xc100) AM_READ_PORT("IN1") /* P1 */
	651	AM_RANGE(0xc200, 0xc200) AM_READ_PORT("IN2") /* P2 */
652	652	AM_RANGE(0xc300, 0xc300) AM_WRITE(hal21_soundcommand_w)
653		AM_RANGE(0xc400, 0xc400) AM_READ(input_port_3_r) /* DSW1 */
654		AM_RANGE(0xc500, 0xc500) AM_READ(input_port_4_r) /* DSW2 */
	653	AM_RANGE(0xc400, 0xc400) AM_READ_PORT("DSW1") /* DSW1 */
	654	AM_RANGE(0xc500, 0xc500) AM_READ_PORT("DSW2") /* DSW2 */
655	655	AM_RANGE(0xc600, 0xc600) AM_WRITE(hal21_vreg0_w)
656	656	AM_RANGE(0xc700, 0xc700) AM_READWRITE(snk_cpuB_nmi_trigger_r, snk_cpuA_nmi_ack_w)
657	657	AM_RANGE(0xd300, 0xd300) AM_WRITE(hal21_vreg1_w)

src/mame/drivers/fcombat.c
r2864	r2865
146	146	static READ8_HANDLER( fcombat_port01_r )
147	147	{
148	148	/* the cocktail flip bit muxes between ports 0 and 1 */
149		return fcombat_cocktail_flip ? input_port_read~~_indexed~~(machine, 1) : input_port_read~~_indexed~~(machine, 0);
	149	return fcombat_cocktail_flip ? input_port_read(machine, "IN1") : input_port_read(machine, "IN0");
150	150	}
151	151
152	152
r2864	r2865
201	201	AM_RANGE(0xd000, 0xd7ff) AM_RAM AM_BASE(&videoram) AM_SIZE(&videoram_size)
202	202	AM_RANGE(0xd800, 0xd8ff) AM_RAM AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
203	203	AM_RANGE(0xe000, 0xe000) AM_READ(fcombat_port01_r)
204		AM_RANGE(0xe100, 0xe100) AM_READ(input_port_2_r)
205		AM_RANGE(0xe200, 0xe200) AM_READ(input_port_3_r)
	204	AM_RANGE(0xe100, 0xe100) AM_READ_PORT("DSW0")
	205	AM_RANGE(0xe200, 0xe200) AM_READ_PORT("DSW1")
206	206	AM_RANGE(0xe300, 0xe300) AM_READ(e300_r)
207	207	AM_RANGE(0xe400, 0xe400) AM_READ(fcombat_protection_r) // protection?
208	208	AM_RANGE(0xe800, 0xe800) AM_WRITE(fcombat_videoreg_w) // at least bit 0 for flip screen and joystick input multiplexor

src/mame/drivers/segas16b.c
r2864	r2865
930	930	*************************************/
931	931
932	932	extern void fd1094_machine_init(void);
933		extern void fd1094_driver_init(void (set_decrypted)(UINT8 ));
	933	extern void fd1094_driver_init(running_machine machine, void (set_decrypted)(UINT8 *));
934	934
935	935	static READ16_HANDLER( misc_io_r );
936	936	static WRITE16_HANDLER( misc_io_w );
r2864	r2865
1062	1062	segaic16_memory_mapper_init(machine, 0, region_info_list[rom_board], sound_w, NULL);
1063	1063
1064	1064	/* init the FD1094 */
1065		fd1094_driver_init(segaic16_memory_mapper_set_decrypted);
	1065	fd1094_driver_init(machine, segaic16_memory_mapper_set_decrypted);
1066	1066
1067	1067	/* reset the custom handlers and other pointers */
1068	1068	custom_io_r = NULL;
r2864	r2865
5585	5585	ROM Board: 171-5704
5586	5586	*/
5587	5587	ROM_START( tetris2 )
5588		ROM_REGION( 0x020000, REGION_CPU1, 0 ) /* 68000 code */
5589		ROM_LOAD16_BYTE( "epr12193.rom", 0x000000, 0x10000, CRC(9ce15ac9) SHA1(0fdbd3ca37e4c0efa7c66415714bfc10637ced6c) )
5590		ROM_LOAD16_BYTE( "epr12192.rom", 0x000001, 0x10000, CRC(98d590ca) SHA1(4d18409c0b5734d0adcea5646d13f65b687dd05d) )
	5588	ROM_REGION( 0x040000, REGION_CPU1, 0 ) /* 68000 code */
	5589	ROM_LOAD16_BYTE( "epr12193.a7", 0x000000, 0x20000, CRC(44466ed4) SHA1(ddb4f0310987e54ce4cd9ffa2813e2d1309aeaaa) )
	5590	ROM_LOAD16_BYTE( "epr12192.a5", 0x000001, 0x20000, CRC(a1c8af00) SHA1(a8e4b289eb3939d6798bb78df1b4ae51c8ccc2d6) )
5591	5591
5592	5592	ROM_REGION( 0x2000, REGION_USER1, 0 ) /* decryption key */
5593	5593	ROM_LOAD( "317-0092.key", 0x0000, 0x2000, CRC(d10e1ad9) SHA1(26e81b5f62d96ea50bf203f66dc3643f29dd1596) )

src/mame/drivers/pktgaldx.c
r2864	r2865
205	205	/**********************************************************************************/
206	206
207	207	static INPUT_PORTS_START( pktgaldx )
208		PORT_START /* 16bit */
	208	PORT_START_TAG("IN0") /* 16bit */
209	209	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
210	210	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
211	211	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE1 )
r2864	r2865
216	216	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
217	217	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
218	218
219		PORT_START /* 16bit */
	219	PORT_START_TAG("DSW") /* 16bit */
220	220	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )
221	221	PORT_DIPSETTING( 0x0000, DEF_STR( 3C_1C ) )
222	222	PORT_DIPSETTING( 0x0001, DEF_STR( 2C_1C ) )
r2864	r2865
264	264	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
265	265	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
266	266
267		PORT_START /* 16bit */
	267	PORT_START_TAG("IN1") /* 16bit */
268	268	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
269	269	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
270	270	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)

src/mame/drivers/atarigx2.c
r2864	r2865
2039	2039	static DRIVER_INIT( spclords )
2040	2040	{
2041	2041	atarigen_eeprom_default = NULL;
2042		atarijsa_init(machine, 2, 0x0040);
	2042	atarijsa_init(machine, "IN2", 0x0040);
2043	2043	atarijsa3_init_adpcm(REGION_SOUND1);
2044	2044
2045	2045	atarigx2_playfield_base = 0x000;
r2864	r2865
2051	2051	static DRIVER_INIT( motofren )
2052	2052	{
2053	2053	atarigen_eeprom_default = NULL;
2054		atarijsa_init(machine, 2, 0x0040);
	2054	atarijsa_init(machine, "IN2", 0x0040);
2055	2055	atarijsa3_init_adpcm(REGION_SOUND1);
2056	2056
2057	2057	atarigx2_playfield_base = 0x400;
r2864	r2865
2089	2089	static DRIVER_INIT( rrreveng )
2090	2090	{
2091	2091	atarigen_eeprom_default = NULL;
2092		atarijsa_init(machine, 2, 0x0040);
	2092	atarijsa_init(machine, "IN2", 0x0040);
2093	2093	atarijsa3_init_adpcm(REGION_SOUND1);
2094	2094
2095	2095	atarigx2_playfield_base = 0x000;

src/mame/drivers/gaelco2.c
r2864	r2865
80	80
81	81
82	82	static INPUT_PORTS_START( maniacsq )
83		PORT_START /* DSW #1 + 1P INPUTS */
	83	PORT_START_TAG("IN0") /* DSW #1 + 1P INPUTS */
84	84	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
85	85	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
86	86	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
116	116	PORT_DIPSETTING( 0xa000, DEF_STR( 1C_6C ) )
117	117	PORT_DIPSETTING( 0x0000, "Disabled or Free Play (if Coin A too)" )
118	118
119		PORT_START /* DSW #2 + 2P INPUTS */
	119	PORT_START_TAG("IN1") /* DSW #2 + 2P INPUTS */
120	120	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
121	121	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
122	122	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
147	147	PORT_DIPSETTING( 0x4000, DEF_STR( On ) )
148	148	PORT_SERVICE( 0x8000, IP_ACTIVE_LOW )
149	149
150		PORT_START /* COINSW & SERVICESW */
	150	PORT_START_TAG("COIN") /* COINSW & SERVICESW */
151	151	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
152	152	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
153	153	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
243	243	}
244	244	}
245	245
246		static READ16_HANDLER(p1_gun_x) {return (input_port_read_indexed(machine, 3)*320/0x100)+1;}
247		static READ16_HANDLER(p1_gun_y) {return (input_port_read_indexed(machine, 5)*240/0x100)-4;}
248		static READ16_HANDLER(p2_gun_x) {return (input_port_read_indexed(machine, 4)*320/0x100)+1;}
249		static READ16_HANDLER(p2_gun_y) {return (input_port_read_indexed(machine, 6)*240/0x100)-4;}
	246	static READ16_HANDLER(p1_gun_x) {return (input_port_read(machine, "LIGHT0_X") * 320 / 0x100) + 1;}
	247	static READ16_HANDLER(p1_gun_y) {return (input_port_read(machine, "LIGHT0_Y") * 240 / 0x100) - 4;}
	248	static READ16_HANDLER(p2_gun_x) {return (input_port_read(machine, "LIGHT1_X") * 320 / 0x100) + 1;}
	249	static READ16_HANDLER(p2_gun_y) {return (input_port_read(machine, "LIGHT1_Y") * 240 / 0x100) - 4;}
250	250
251	251	static ADDRESS_MAP_START( bang_readmem, ADDRESS_SPACE_PROGRAM, 16 )
252	252	AM_RANGE(0x000000, 0x0fffff) AM_READ(SMH_ROM) /* ROM */
r2864	r2865
282	282
283	283
284	284	static INPUT_PORTS_START( bang )
285		PORT_START /* 1P INPUTS */
	285	PORT_START_TAG("P1") /* 1P INPUTS */
286	286	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_IMPULSE(1) PORT_PLAYER(1)
287	287
288		PORT_START /* 2P INPUTS */
	288	PORT_START_TAG("P2") /* 2P INPUTS */
289	289	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
290	290
291		PORT_START /* COINSW & Service */
	291	PORT_START_TAG("COIN") /* COINSW & Service */
292	292	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
293	293	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
294	294	PORT_SERVICE_NO_TOGGLE( 0x0004, IP_ACTIVE_LOW) /* go to service mode NOW */
r2864	r2865
297	297	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_START2 )
298	298	/* bits 6 & 7 are used for accessing the NVRAM */
299	299
300		PORT_START /* Gun 1 X */
	300	PORT_START_TAG("LIGHT0_X") /* Gun 1 X */
301	301	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(15) PORT_PLAYER(1)
302	302
303		PORT_START /* Gun 2 X */
	303	PORT_START_TAG("LIGHT1_X") /* Gun 2 X */
304	304	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(15) PORT_PLAYER(2)
305	305
306		PORT_START /* Gun 1 Y */
	306	PORT_START_TAG("LIGHT0_Y") /* Gun 1 Y */
307	307	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, -6.0 / 240, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(15) PORT_PLAYER(1)
308	308
309		PORT_START /* Gun 2 Y */
	309	PORT_START_TAG("LIGHT1_Y") /* Gun 2 Y */
310	310	PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, -6.0 / 240, 0) PORT_SENSITIVITY(35) PORT_KEYDELTA(15) PORT_PLAYER(2)
311	311	INPUT_PORTS_END
312	312
r2864	r2865
439	439
440	440	static INPUT_PORTS_START( alighunt )
441	441
442		PORT_START /* DSW #1 */
	442	PORT_START_TAG("IN0") /* DSW #1 */
443	443	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
444	444	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
445	445	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
475	475	PORT_DIPSETTING( 0xa000, DEF_STR( 1C_6C ) )
476	476	PORT_DIPSETTING( 0x0000, "Disabled or Free Play (if Coin A too)" )
477	477
478		PORT_START /* DSW #2 */
	478	PORT_START_TAG("IN1") /* DSW #2 */
479	479	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
480	480	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
481	481	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
505	505	PORT_DIPSETTING( 0x4000, DEF_STR( Standard ) )
506	506	PORT_SERVICE( 0x8000, IP_ACTIVE_LOW )
507	507
508		PORT_START /* COINSW & Service */
	508	PORT_START_TAG("COIN") /* COINSW & Service */
509	509	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
510	510	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
511	511	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
672	672
673	673	static INPUT_PORTS_START( touchgo )
674	674
675		PORT_START /* DSW #2 + 1P INPUTS */
	675	PORT_START_TAG("IN0") /* DSW #2 + 1P INPUTS */
676	676	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
677	677	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
678	678	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
701	701	PORT_DIPSETTING( 0x4000, DEF_STR( On ) )
702	702	PORT_SERVICE( 0x8000, IP_ACTIVE_LOW )
703	703
704		PORT_START /* DSW #1 + 2P INPUTS */
	704	PORT_START_TAG("IN1") /* DSW #1 + 2P INPUTS */
705	705	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
706	706	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
707	707	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
745	745	PORT_DIPSETTING( 0xb000, DEF_STR( 1C_5C ) )
746	746	PORT_DIPSETTING( 0xa000, DEF_STR( 1C_6C ) )
747	747
748		PORT_START /* COINSW + 3P */
	748	PORT_START_TAG("IN2") /* COINSW + 3P */
749	749	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
750	750	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
751	751	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
r2864	r2865
760	760	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_COIN4 )
761	761	PORT_BIT( 0xf000, IP_ACTIVE_LOW, IPT_UNKNOWN )
762	762
763		PORT_START /* SERVICESW + 4P INPUTS */
	763	PORT_START_TAG("IN3") /* SERVICESW + 4P INPUTS */
764	764	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
765	765	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
766	766	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
r2864	r2865
774	774	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_SERVICE2 )
775	775	PORT_BIT( 0xf800, IP_ACTIVE_LOW, IPT_UNKNOWN )
776	776
777		PORT_START /* Fake: To switch between monitors at run time */
778		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_SERVICE4 ) PORT_TOGGLE
	777	PORT_START_TAG("FAKE") /* Fake: To switch between monitors at run time */
	778	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SERVICE4 ) PORT_TOGGLE
779	779	INPUT_PORTS_END
780	780
781	781	static const struct gaelcosnd_interface touchgo_snd_interface =
r2864	r2865
951	951
952	952
953	953	static INPUT_PORTS_START( snowboar )
954		PORT_START /* 1P INPUTS */
	954	PORT_START_TAG("P1") /* 1P INPUTS */
955	955	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
956	956	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
957	957	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
961	961	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
962	962	PORT_BIT( 0xff80, IP_ACTIVE_LOW, IPT_UNKNOWN )
963	963
964		PORT_START /* 2P INPUTS */
	964	PORT_START_TAG("P2") /* 2P INPUTS */
965	965	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
966	966	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
967	967	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
971	971	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
972	972	PORT_BIT( 0xff80, IP_ACTIVE_LOW, IPT_UNKNOWN )
973	973
974		PORT_START /* COINSW & Service */
	974	PORT_START_TAG("COIN") /* COINSW & Service */
975	975	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
976	976	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
977	977	PORT_SERVICE_NO_TOGGLE( 0x04, IP_ACTIVE_LOW) /* go to service mode NOW */
r2864	r2865
1144	1144
1145	1145
1146	1146	static INPUT_PORTS_START( wrally2 )
1147		PORT_START /* DIPSW #2 + 1P INPUTS */
	1147	PORT_START_TAG("IN0") /* DIPSW #2 + 1P INPUTS */
1148	1148	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
1149	1149	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
1150	1150	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
r2864	r2865
1175	1175	PORT_DIPSETTING( 0x8000, DEF_STR( Hard ) )
1176	1176	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
1177	1177
1178		PORT_START /* DIPSW #1 */
	1178	PORT_START_TAG("IN1") /* DIPSW #1 */
1179	1179	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
1180	1180	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Free_Play ) )
1181	1181	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
r2864	r2865
1202	1202	PORT_DIPSETTING( 0xa000, DEF_STR( 1C_3C ) )
1203	1203	PORT_DIPSETTING( 0x2000, DEF_STR( 1C_4C ) )
1204	1204
1205		PORT_START /* 2P INPUTS */
	1205	PORT_START_TAG("IN2") /* 2P INPUTS */
1206	1206	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
1207	1207	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
1208	1208	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
r2864	r2865
1215	1215	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_COIN2 )
1216	1216	PORT_BIT( 0xfa00, IP_ACTIVE_LOW, IPT_UNKNOWN )
1217	1217
1218		PORT_START /* SERVICESW */
	1218	PORT_START_TAG("IN3") /* SERVICESW */
1219	1219	PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
1220	1220	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE1 )
1221	1221	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_SERVICE3 ) /* go to test mode NOW */
1222	1222	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_SERVICE2 )
1223	1223	PORT_BIT( 0xf800, IP_ACTIVE_LOW, IPT_UNKNOWN )
1224	1224
1225		PORT_START /* Fake: To switch between monitors at run time */
	1225	PORT_START_TAG("FAKE") /* Fake: To switch between monitors at run time */
1226	1226	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_SERVICE4 ) PORT_TOGGLE
1227	1227	INPUT_PORTS_END
1228	1228

src/mame/drivers/homerun.c
r2864	r2865
90	90	static READ8_HANDLER(homerun_40_r)
91	91	{
92	92	if(video_screen_get_vpos(machine->primary_screen)>116)
93		return input_port_read~~_indexed~~(machine, 0)\|0x40;
	93	return input_port_read(machine, "IN0") \| 0x40;
94	94	else
95		return input_port_read~~_indexed~~(machine, 0);
	95	return input_port_read(machine, "IN0");
96	96	}
97	97
98	98	static ADDRESS_MAP_START( homerun_iomap, ADDRESS_SPACE_IO, 8 )
r2864	r2865
101	101	AM_RANGE(0x20, 0x20) AM_WRITE(SMH_NOP) /* ?? */
102	102	AM_RANGE(0x30, 0x33) AM_DEVREADWRITE(PPI8255, "ppi8255", ppi8255_r, ppi8255_w)
103	103	AM_RANGE(0x40, 0x40) AM_READ(homerun_40_r)
104		AM_RANGE(0x50, 0x50) AM_READ(input_port_2_r)
105		AM_RANGE(0x60, 0x60) AM_READ(input_port_1_r)
	104	AM_RANGE(0x50, 0x50) AM_READ_PORT("IN2")
	105	AM_RANGE(0x60, 0x60) AM_READ_PORT("IN1")
106	106	AM_RANGE(0x70, 0x70) AM_READWRITE(YM2203_status_port_0_r, YM2203_control_port_0_w)
107	107	AM_RANGE(0x71, 0x71) AM_READWRITE(YM2203_read_port_0_r, YM2203_write_port_0_w)
108	108	ADDRESS_MAP_END
r2864	r2865
122	122
123	123
124	124	static INPUT_PORTS_START( homerun )
125		PORT_START
	125	PORT_START_TAG("IN0")
126	126	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
127	127	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
128		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
129		PORT_DIPSETTING( 0x80, DEF_STR( On ) )
	128	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	129	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
130	130
131		PORT_START
	131	PORT_START_TAG("IN1")
132	132	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
133	133	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
134	134	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT )
r2864	r2865
136	136	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_START1 )
137	137	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 )
138	138
139		PORT_START
	139	PORT_START_TAG("IN2")
140	140	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
141	141
142		PORT_START
	142	PORT_START_TAG("DSW")
143	143	PORT_DIPNAME( 0x03, 0x02, DEF_STR( Coin_B ) )
144		PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
145		PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) )
146		PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
147		PORT_DIPSETTING( 0x03, DEF_STR( Free_Play ) )
	144	PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
	145	PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) )
	146	PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
	147	PORT_DIPSETTING( 0x03, DEF_STR( Free_Play ) )
148	148	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Coin_A ) )
149		PORT_DIPSETTING( 0x80, DEF_STR( 1C_1C ) )
150		PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
151
	149	PORT_DIPSETTING( 0x80, DEF_STR( 1C_1C ) )
	150	PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
152	151	INPUT_PORTS_END
153	152
154	153	static INPUT_PORTS_START( dynashot )
155		PORT_START
	154	PORT_START_TAG("IN0")
156	155	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
157	156	PORT_BIT( 0xf7, IP_ACTIVE_HIGH, IPT_UNUSED )
158	157
159		PORT_START
	158	PORT_START_TAG("IN1")
160	159	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
161	160	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
162	161	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT )
r2864	r2865
166	165	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNUSED )
167	166	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 )
168	167
169		PORT_START
	168	PORT_START_TAG("IN2")
170	169	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
171	170	PORT_BIT( 0xdf, IP_ACTIVE_HIGH, IPT_UNUSED )
172	171
173		PORT_START
	172	PORT_START_TAG("DSW")
174	173	PORT_DIPNAME( 0x03, 0x02, DEF_STR( Coin_B ) )
175		PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
176		PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) )
177		PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
178		PORT_DIPSETTING( 0x03, DEF_STR( Free_Play ) )
	174	PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
	175	PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) )
	176	PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
	177	PORT_DIPSETTING( 0x03, DEF_STR( Free_Play ) )
179	178	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Coin_A ) )
180		PORT_DIPSETTING( 0x80, DEF_STR( 1C_1C ) )
181		PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
	179	PORT_DIPSETTING( 0x80, DEF_STR( 1C_1C ) )
	180	PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ) )
182	181
183
184	182	PORT_DIPNAME( 0x7c, 0x7c, "Collisions ?" ) //not all bits
185		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
186		PORT_DIPSETTING( 0x7c, DEF_STR( On ) )
187
	183	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	184	PORT_DIPSETTING( 0x7c, DEF_STR( On ) )
188	185	INPUT_PORTS_END
189	186
190	187
r2864	r2865
256	253
257	254	GAME( 1988, homerun, 0, homerun, homerun, 0, ROT0, "Jaleco", "Moero Pro Yakyuu Homerun",GAME_IMPERFECT_GRAPHICS\|GAME_IMPERFECT_SOUND)
258	255	GAME( 1988, dynashot, 0, homerun, dynashot, 0, ROT0, "Jaleco", "Dynamic Shooting",GAME_IMPERFECT_GRAPHICS\|GAME_IMPERFECT_SOUND)
259
260

src/mame/drivers/guab.c
r2864	r2865
23	23	#include "machine/6840ptm.h"
24	24	#include "video/tms34061.h"
25	25	#include "sound/sn76496.h"
26		#include "deprecat.h"
27	26
28	27
29	28	/*************************************
r2864	r2865
239	238	UINT8 pen = src[x >> 1];
240	239
241	240	/* Draw two 4-bit pixels */
242		*dest++ = Machine->pens[pen >> 4];
243		*dest++ = Machine->pens[pen & 0x0f];
	241	*dest++ = screen->machine->pens[pen >> 4];
	242	*dest++ = screen->machine->pens[pen & 0x0f];
244	243	}
245	244	}
246	245
r2864	r2865
546	545
547	546	static READ16_HANDLER( io_r )
548	547	{
	548	static const char *portnames[] = { "IN0", "IN1", "IN2" };
	549
549	550	switch (offset)
550	551	{
551	552	case 0x00:
552	553	case 0x01:
553	554	case 0x02:
554	555	{
555		return input_port_read~~_indexed~~(machine, offset);
	556	return input_port_read(machine, portnames[offset]);
556	557	}
557	558	case 0x30:
558	559	{
r2864	r2865
666	667	*************************************/
667	668
668	669	static INPUT_PORTS_START( guab )
669		PORT_START
	670	PORT_START_TAG("IN0")
670	671	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_NAME("50p")
671	672	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_NAME("100p")
672	673	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Back door") PORT_CODE(KEYCODE_R) PORT_TOGGLE
r2864	r2865
675	676	PORT_BIT( 0x20, IP_ACTIVE_HIGH,IPT_UNUSED ) PORT_NAME("50p level")
676	677	PORT_BIT( 0x40, IP_ACTIVE_HIGH,IPT_UNUSED ) PORT_NAME("100p level")
677	678	PORT_BIT( 0x80, IP_ACTIVE_HIGH,IPT_UNUSED )
678		PORT_START
	679
	680	PORT_START_TAG("IN1")
679	681	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
680	682	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
681	683	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START )
r2864	r2865
684	686	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
685	687	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("A")
686	688	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("B")
687		PORT_START
	689
	690	PORT_START_TAG("IN2")
688	691	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("Select")
689	692	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
690	693	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r2864	r2865
696	699	INPUT_PORTS_END
697	700
698	701	static INPUT_PORTS_START( tenup )
699		PORT_START
	702	PORT_START_TAG("IN0")
700	703	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_NAME("50p")
701	704	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_NAME("100p")
702	705	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Back door") PORT_CODE(KEYCODE_R) PORT_TOGGLE
r2864	r2865
705	708	PORT_BIT( 0x20, IP_ACTIVE_HIGH,IPT_UNUSED ) PORT_NAME("10p level")
706	709	PORT_BIT( 0x40, IP_ACTIVE_HIGH,IPT_UNUSED ) PORT_NAME("100p level")
707	710	PORT_BIT( 0x80, IP_ACTIVE_HIGH,IPT_UNUSED )
708		PORT_START
	711
	712	PORT_START_TAG("IN1")
709	713	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
710	714	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
711	715	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START )
r2864	r2865
714	718	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
715	719	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
716	720	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("Pass")
717		PORT_START
	721
	722	PORT_START_TAG("IN2")
718	723	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Collect")
719	724	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
720	725	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )

src/mame/drivers/ninjaw.c
r2864	r2865
190	190	***************************************************************************/
191	191
192	192	#include "driver.h"
193		#include "deprecat.h"
194	193	#include "taitoipt.h"
195	194	#include "cpu/m68000/m68000.h"
196	195	#include "video/taitoic.h"
r2864	r2865
208	207
209	208	static UINT16 cpua_ctrl = 0xff;
210	209
211		static void parse_control(void) /* assumes Z80 sandwiched between 68Ks */
	210	static void parse_control(running_machine machine) / assumes Z80 sandwiched between 68Ks */
212	211	{
213	212	/* bit 0 enables cpu B */
214	213	/* however this fails when recovering from a save state
215	214	if cpu B is disabled !! */
216		cpunum_set_input_line(Machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
	215	cpunum_set_input_line(machine, 2, INPUT_LINE_RESET, (cpua_ctrl &0x1) ? CLEAR_LINE : ASSERT_LINE);
217	216
218	217	}
219	218
r2864	r2865
223	222	data = data >> 8; /* for Wgp */
224	223	cpua_ctrl = data;
225	224
226		parse_control();
	225	parse_control(machine);
227	226
228	227	logerror("CPU #0 PC %06x: write %04x to cpu control\n",activecpu_get_pc(),data);
229	228	}
r2864	r2865
929	928
930	929	static STATE_POSTLOAD( ninjaw_postload )
931	930	{
932		parse_control();
	931	parse_control(machine);
933	932	reset_sound_region();
934	933	}
935	934

src/mame/drivers/dcheese.c
r2864	r2865
29	29
30	30
31	31	#include "driver.h"
32		#include "deprecat.h"
33	32	#include "machine/eeprom.h"
34	33	#include "machine/ticket.h"
35	34	#include "sound/bsmt2000.h"
r2864	r2865
88	87	}
89	88
90	89
91		void dcheese_signal_irq(int which)
	90	void dcheese_signal_irq(running_machine *machine, int which)
92	91	{
93	92	irq_state[which] = 1;
94		update_irq_state(Machine);
	93	update_irq_state(machine);
95	94	}
96	95
97	96
98	97	static INTERRUPT_GEN( dcheese_vblank )
99	98	{
100	99	logerror("---- VBLANK ----\n");
101		dcheese_signal_irq(4);
	100	dcheese_signal_irq(machine, 4);
102	101	}
103	102
104	103

src/mame/drivers/srmp6.c
r2864	r2865
91	91	8*64
92	92	};
93	93
94		static void update_palette(void)
	94	static void update_palette(running_machine *machine)
95	95	{
96	96	INT8 r, g ,b;
97	97	int brg = brightness - 0x60;
r2864	r2865
119	119	b += ((0x1F - b) * brg) >> 5;
120	120	if(b > 0x1F) b = 0x1F;
121	121	}
122		palette_set_color(Machine, i, MAKE_RGB(r << 3, g << 3, b << 3));
	122	palette_set_color(machine, i, MAKE_RGB(r << 3, g << 3, b << 3));
123	123	}
124	124	}
125	125
r2864	r2865
146	146
147	147	/* Debug code */
148	148	#ifdef UNUSED_FUNCTION
149		static void srmp6_decode_charram(void)
	149	static void srmp6_decode_charram(running_machine *machine)
150	150	{
151	151	if(input_code_pressed_once(KEYCODE_Z))
152	152	{
153	153	int i;
154	154	for (i=0;i<(0x100000*16)/0x40;i++)
155	155	{
156		decodechar(Machine->gfx[0], i, (UINT8*)tileram);
	156	decodechar(machine->gfx[0], i, (UINT8*)tileram);
157	157	dirty_tileram[i] = 0;
158	158	}
159	159	}
r2864	r2865
181	181
182	182	#if 0
183	183	/* debug */
184		srmp6_decode_charram();
	184	srmp6_decode_charram(screen->machine);
185	185
186	186
187	187
r2864	r2865
381	381	data = (!data)?0x60:(data == 0x5e)?0x60:data;
382	382	if(brightness != data) {
383	383	brightness = data;
384		update_palette();
	384	update_palette(machine);
385	385	}
386	386	break;
387	387

src/mame/drivers/lsasquad.c
r2864	r2865
171	171	AM_RANGE(0x0000, 0x7fff) AM_READ(SMH_ROM)
172	172	AM_RANGE(0x8000, 0x9fff) AM_READ(SMH_BANK1)
173	173	AM_RANGE(0xa000, 0xe5ff) AM_READ(SMH_RAM)
174		AM_RANGE(0xe800, 0xe800) AM_READ(input_port_0_r) /* DSWA */
175		AM_RANGE(0xe801, 0xe801) AM_READ(input_port_1_r) /* DSWB */
176		AM_RANGE(0xe802, 0xe802) AM_READ(input_port_2_r) /* DSWC */
	174	AM_RANGE(0xe800, 0xe800) AM_READ_PORT("DSWA") /* DSWA */
	175	AM_RANGE(0xe801, 0xe801) AM_READ_PORT("DSWB") /* DSWB */
	176	AM_RANGE(0xe802, 0xe802) AM_READ_PORT("DSWC") /* DSWC */
177	177	AM_RANGE(0xe803, 0xe803) AM_READ(lsasquad_mcu_status_r) /* COIN + 68705 status */
178		AM_RANGE(0xe804, 0xe804) AM_READ(input_port_4_r) /* IN0 */
179		AM_RANGE(0xe805, 0xe805) AM_READ(input_port_5_r) /* IN1 */
180		AM_RANGE(0xe806, 0xe806) AM_READ(input_port_6_r) /* START */
181		AM_RANGE(0xe807, 0xe807) AM_READ(input_port_7_r) /* SERVICE/TILT */
	178	AM_RANGE(0xe804, 0xe804) AM_READ_PORT("IN0") /* IN0 */
	179	AM_RANGE(0xe805, 0xe805) AM_READ_PORT("IN1") /* IN1 */
	180	AM_RANGE(0xe806, 0xe806) AM_READ_PORT("IN2") /* START */
	181	AM_RANGE(0xe807, 0xe807) AM_READ_PORT("IN3") /* SERVICE/TILT */
182	182	AM_RANGE(0xec00, 0xec00) AM_READ(lsasquad_sound_result_r)
183	183	AM_RANGE(0xec01, 0xec01) AM_READ(lsasquad_sound_status_r)
184	184	AM_RANGE(0xee00, 0xee00) AM_READ(lsasquad_mcu_r)

src/mame/drivers/fuukifg3.c
r2864	r2865
218	218
219	219	***************************************************************************/
220	220
	221	static const char *portnames[] = { "IN0", "IN1", "DSW0", "DSW1" };
221	222
222	223	#define FUUKI32_INPUT( _N_ ) \
223	224	\
224	225	static READ32_HANDLER( io32_##_N_##_r ) \
225	226	{ \
226		return (input_port_read~~_indexed~~(machine, _N_ ) << 16) \| input_port_read~~_indexed~~(machine, _N_ ); \
	227	return (input_port_read(machine, portnames[ _N_ ]) << 16) \| input_port_read(machine, portnames[ _N_ ]); \
227	228	}
228	229
229	230	FUUKI32_INPUT( 0 ) /* $800000.l Coins Inputs */
r2864	r2865
387	388	***************************************************************************/
388	389
389	390	static INPUT_PORTS_START( asurabld )
390		PORT_START // IN0 - $800000.w/$800002.w
	391	PORT_START_TAG("IN0") // IN0 - $800000.w/$800002.w
391	392	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
392	393	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
393	394	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
r2864	r2865
399	400	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE1 )
400	401	PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNKNOWN )
401	402
402		PORT_START // IN1 - $810000.w/$810002.w
	403	PORT_START_TAG("IN1") // IN1 - $810000.w/$810002.w
403	404	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
404	405	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
405	406	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
r2864	r2865
417	418	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
418	419	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
419	420
420		PORT_START // IN2 - $880000.w/$880002.w
	421	PORT_START_TAG("DSW0") // IN2 - $880000.w/$880002.w
421	422	PORT_SERVICE( 0x0001, 0x0001 )
422	423	PORT_DIPNAME( 0x0002, 0x0002, "Blood Colour" ) // Any other censorship? (Tested in 3 locations)
423	424	PORT_DIPSETTING( 0x0002, "Red" )
r2864	r2865
438	439	PORT_DIPSETTING( 0x0000, "Joint" )
439	440	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
440	441
441		PORT_START // IN3 - $890000.w/$890002.w
	442	PORT_START_TAG("DSW1") // IN3 - $890000.w/$890002.w
442	443	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) )
443	444	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
444	445	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )

src/mame/drivers/dec8.c
r2864	r2865
118	118	{
119	119	switch (offset) {
120	120	case 0: /* Rotary low byte */
121		return ~((1 << (input_port_read~~_indexed~~(machine, 5) * 12 / 256))&0xff);
	121	return ~((1 << (input_port_read(machine, "AN0") * 12 / 256))&0xff);
122	122	case 1: /* Joystick = bottom 4 bits, rotary = top 4 */
123		return ((~((1 << (input_port_read~~_indexed~~(machine, 5) * 12 / 256))>>4))&0xf0) \| (input_port_read~~_indexed~~(machine, 0)&0xf);
	123	return ((~((1 << (input_port_read(machine, "AN0") * 12 / 256))>>4))&0xf0) \| (input_port_read(machine, "IN0") & 0xf);
124	124	}
125	125	return 0xff;
126	126	}
r2864	r2865
129	129	{
130	130	switch (offset) {
131	131	case 0: /* Rotary low byte */
132		return ~((1 << (input_port_read~~_indexed~~(machine, 6) * 12 / 256))&0xff);
	132	return ~((1 << (input_port_read(machine, "AN1") * 12 / 256))&0xff);
133	133	case 1: /* Joystick = bottom 4 bits, rotary = top 4 */
134		return ((~((1 << (input_port_read~~_indexed~~(machine, 6) * 12 / 256))>>4))&0xf0) \| (input_port_read~~_indexed~~(machine, 1)&0xf);
	134	return ((~((1 << (input_port_read(machine, "AN1") * 12 / 256))>>4))&0xf0) \| (input_port_read(machine, "IN1") & 0xf);
135	135	}
136	136	return 0xff;
137	137	}
r2864	r2865
177	177	if (i8751_value==0x5000) i8751_return=((coins / 10) << 4) \| (coins % 10); /* Coin request */
178	178	if (i8751_value==0x6000) {i8751_value=-1; coins--; } /* Coin clear */
179	179	/* Nb: Command 0x4000 for setting coinage options is not supported */
180		if ((input_port_read_indexed(machine, 4)&1)==1) latch=1;
181		if ((input_port_read_indexed(machine, 4)&1)!=1 && latch) {coins++; latch=0;}
	180	if ((input_port_read(machine, "FAKE") & 1) == 1) latch=1;
	181	if ((input_port_read(machine, "FAKE") & 1) != 1 && latch) {coins++; latch=0;}
182	182
183	183	/* This next value is the index to a series of tables,
184	184	each table controls the end of level bad guy, wrong values crash the
r2864	r2865
245	245	}
246	246
247	247	/* Coins are controlled by the i8751 */
248		if ((input_port_read_indexed(machine, 4)&3)==3) latch=1;
249		if ((input_port_read_indexed(machine, 4)&1)!=1 && latch) {coin1++; snd=1; latch=0;}
250		if ((input_port_read_indexed(machine, 4)&2)!=2 && latch) {coin2++; snd=1; latch=0;}
	248	if ((input_port_read(machine, "I8751") & 3) == 3) latch=1;
	249	if ((input_port_read(machine, "I8751") & 1) != 1 && latch) {coin1++; snd=1; latch=0;}
	250	if ((input_port_read(machine, "I8751") & 2) != 2 && latch) {coin2++; snd=1; latch=0;}
251	251
252	252	/* Work out return values */
253	253	if (i8751_value==0x0000) {i8751_return=0; coin1=coin2=snd=0;}
r2864	r2865
278	278	}
279	279
280	280	/* Coins are controlled by the i8751 */
281		if (/(input_port_read_indexed(machine, 2)&3)==3/!latch) {latch=1;coin1=coin2=0;}
282		if ((input_port_read_indexed(machine, 2)&1)!=1 && latch) {coin1=1; latch=0;}
283		if ((input_port_read_indexed(machine, 2)&2)!=2 && latch) {coin2=1; latch=0;}
	281	if (/(input_port_read(machine, "IN2") & 3) == 3/!latch) {latch=1;coin1=coin2=0;}
	282	if ((input_port_read(machine, "IN2") & 1) != 1 && latch) {coin1=1; latch=0;}
	283	if ((input_port_read(machine, "IN2") & 2) != 2 && latch) {coin2=1; latch=0;}
284	284
285	285	if (i8751_value==0x0050) i8751_return=0; /* Breywood ID */
286	286	if (i8751_value==0x0051) i8751_return=0; /* Shackled ID */
r2864	r2865
308	308	if(offset==0)
309	309	{
310	310	/* Coins are controlled by the i8751 */
311		if ((input_port_read_indexed(machine, 2)&3)==3 && !latch) latch=1;
312		if ((input_port_read_indexed(machine, 2)&3)!=3 && latch) {coin++; latch=0;snd=0x400;i8751_return=0x400;return;}
	311	if ((input_port_read(machine, "IN2") & 3) == 3 && !latch) latch=1;
	312	if ((input_port_read(machine, "IN2") & 3) != 3 && latch) {coin++; latch=0;snd=0x400;i8751_return=0x400;return;}
313	313	if (i8751_value==0x007a) i8751_return=0x0185; /* Japan ID code */
314	314	if (i8751_value==0x007b) i8751_return=0x0184; /* USA ID code */
315	315	if (i8751_value==0x0001) {coin=snd=0;}//???
r2864	r2865
339	339	if(offset==0)
340	340	{
341	341	/* Coins are controlled by the i8751 */
342		if ((input_port_read_indexed(machine, 2)&3)==3 && !latch) latch=1;
343		if ((input_port_read_indexed(machine, 2)&3)!=3 && latch) {coin++; latch=0;snd=0x1200; i8751_return=0x1200;return;}
	342	if ((input_port_read(machine, "IN2") & 3) == 3 && !latch) latch=1;
	343	if ((input_port_read(machine, "IN2") & 3) != 3 && latch) {coin++; latch=0; snd=0x1200; i8751_return=0x1200;return;}
344	344
345	345	if (i8751_value==0x054a) {i8751_return=~(0x4a); coin=0; snd=0;} /* Captain Silver (Japan) ID */
346	346	if (i8751_value==0x054c) {i8751_return=~(0x4c); coin=0; snd=0;} /* Captain Silver (World) ID */
r2864	r2865
365	365	}
366	366
367	367	/* Coins are controlled by the i8751 */
368		if ((input_port_read_indexed(machine, 2)&3)==3) latch=1;
369		if ((input_port_read_indexed(machine, 2)&1)!=1 && latch) {coin1++; latch=0;}
370		if ((input_port_read_indexed(machine, 2)&2)!=2 && latch) {coin2++; latch=0;}
	368	if ((input_port_read(machine, "I8751") & 3) == 3) latch=1;
	369	if ((input_port_read(machine, "I8751") & 1) != 1 && latch) {coin1++; latch=0;}
	370	if ((input_port_read(machine, "I8751") & 2) != 2 && latch) {coin2++; latch=0;}
371	371
372	372	/* Work out return values */
373	373	if ((i8751_value>>8)==0x00) {i8751_return=0; coin1=coin2=0;}
r2864	r2865
542	542	AM_RANGE(0x1000, 0x17ff) AM_READ(dec8_pf1_data_r)
543	543	AM_RANGE(0x1800, 0x2fff) AM_READ(SMH_RAM)
544	544	AM_RANGE(0x3000, 0x31ff) AM_READ(SMH_RAM)
545		AM_RANGE(0x3800, 0x3800) AM_READ(input_port_0_r) /* Player 1 */
546		AM_RANGE(0x3801, 0x3801) AM_READ(input_port_1_r) /* Player 2 */
547		AM_RANGE(0x3802, 0x3802) AM_READ(input_port_3_r) /* Dip 1 */
548		AM_RANGE(0x3803, 0x3803) AM_READ(input_port_4_r) /* Dip 2 */
549		AM_RANGE(0x3a00, 0x3a00) AM_READ(input_port_2_r) /* VBL & coins */
	545	AM_RANGE(0x3800, 0x3800) AM_READ_PORT("IN0") /* Player 1 */
	546	AM_RANGE(0x3801, 0x3801) AM_READ_PORT("IN1") /* Player 2 */
	547	AM_RANGE(0x3802, 0x3802) AM_READ_PORT("DSW0") /* Dip 1 */
	548	AM_RANGE(0x3803, 0x3803) AM_READ_PORT("DSW1") /* Dip 2 */
	549	AM_RANGE(0x3a00, 0x3a00) AM_READ_PORT("IN2") /* VBL & coins */
550	550	AM_RANGE(0x4000, 0x7fff) AM_READ(SMH_BANK1)
551	551	AM_RANGE(0x8000, 0xffff) AM_READ(SMH_ROM)
552	552	ADDRESS_MAP_END
r2864	r2865
574	574	AM_RANGE(0x2000, 0x27ff) AM_READ(dec8_pf0_data_r)
575	575	AM_RANGE(0x2800, 0x2dff) AM_READ(SMH_RAM)
576	576	AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM)
577		AM_RANGE(0x3800, 0x3800) AM_READ(input_port_0_r) /* Player 1 */
578		AM_RANGE(0x3801, 0x3801) AM_READ(input_port_1_r) /* Player 2 */
579		AM_RANGE(0x3802, 0x3802) AM_READ(input_port_2_r) /* Player 3 */
580		AM_RANGE(0x3803, 0x3803) AM_READ(input_port_3_r) /* Start buttons + VBL */
581		AM_RANGE(0x3820, 0x3820) AM_READ(input_port_5_r) /* Dip */
	577	AM_RANGE(0x3800, 0x3800) AM_READ_PORT("IN0") /* Player 1 */
	578	AM_RANGE(0x3801, 0x3801) AM_READ_PORT("IN1") /* Player 2 */
	579	AM_RANGE(0x3802, 0x3802) AM_READ_PORT("IN2") /* Player 3 */
	580	AM_RANGE(0x3803, 0x3803) AM_READ_PORT("DSW0") /* Start buttons + VBL */
	581	AM_RANGE(0x3820, 0x3820) AM_READ_PORT("DSW1") /* Dip */
582	582	AM_RANGE(0x3840, 0x3840) AM_READ(i8751_h_r)
583	583	AM_RANGE(0x3860, 0x3860) AM_READ(i8751_l_r)
584	584	AM_RANGE(0x4000, 0x7fff) AM_READ(SMH_BANK1)
r2864	r2865
606	606	AM_RANGE(0x1400, 0x17ff) AM_READ(dec8_pf0_data_r)
607	607	AM_RANGE(0x2000, 0x2000) AM_READ(i8751_h_r)
608	608	AM_RANGE(0x2001, 0x2001) AM_READ(i8751_l_r)
609		AM_RANGE(0x3800, 0x3800) AM_READ(input_port_2_r) /* Dip 1 */
610		AM_RANGE(0x3801, 0x3801) AM_READ(input_port_0_r) /* Player 1 */
611		AM_RANGE(0x3802, 0x3802) AM_READ(input_port_1_r) /* Player 2 (cocktail) + VBL */
612		AM_RANGE(0x3803, 0x3803) AM_READ(input_port_3_r) /* Dip 2 */
	609	AM_RANGE(0x3800, 0x3800) AM_READ_PORT("DSW0") /* Dip 1 */
	610	AM_RANGE(0x3801, 0x3801) AM_READ_PORT("IN0") /* Player 1 */
	611	AM_RANGE(0x3802, 0x3802) AM_READ_PORT("IN1") /* Player 2 (cocktail) + VBL */
	612	AM_RANGE(0x3803, 0x3803) AM_READ_PORT("DSW1") /* Dip 2 */
613	613	AM_RANGE(0x4000, 0x7fff) AM_READ(SMH_BANK1)
614	614	AM_RANGE(0x8000, 0xffff) AM_READ(SMH_ROM)
615	615	ADDRESS_MAP_END
r2864	r2865
638	638	AM_RANGE(0x2000, 0x27ff) AM_READ(dec8_pf0_data_r)
639	639	AM_RANGE(0x2800, 0x2bff) AM_READ(SMH_RAM)
640	640	AM_RANGE(0x2c00, 0x2fff) AM_READ(SMH_RAM)
641		AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM) /* Sprites */
642		AM_RANGE(0x3800, 0x3800) AM_READ(input_port_7_r) /* Dip 1 */
643		AM_RANGE(0x3801, 0x3801) AM_READ(input_port_8_r) /* Dip 2 */
644		AM_RANGE(0x380a, 0x380b) AM_READ(gondo_player_1_r) /* Player 1 rotary */
645		AM_RANGE(0x380c, 0x380d) AM_READ(gondo_player_2_r) /* Player 2 rotary */
646		AM_RANGE(0x380e, 0x380e) AM_READ(input_port_3_r) /* VBL */
647		AM_RANGE(0x380f, 0x380f) AM_READ(input_port_2_r) /* Fire buttons */
	641	AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM) /* Sprites */
	642	AM_RANGE(0x3800, 0x3800) AM_READ_PORT("DSW0") /* Dip 1 */
	643	AM_RANGE(0x3801, 0x3801) AM_READ_PORT("DSW1") /* Dip 2 */
	644	AM_RANGE(0x380a, 0x380b) AM_READ(gondo_player_1_r) /* Player 1 rotary */
	645	AM_RANGE(0x380c, 0x380d) AM_READ(gondo_player_2_r) /* Player 2 rotary */
	646	AM_RANGE(0x380e, 0x380e) AM_READ_PORT("IN3") /* VBL */
	647	AM_RANGE(0x380f, 0x380f) AM_READ_PORT("IN2") /* Fire buttons */
648	648	AM_RANGE(0x3838, 0x3838) AM_READ(i8751_h_r)
649	649	AM_RANGE(0x3839, 0x3839) AM_READ(i8751_l_r)
650	650	AM_RANGE(0x4000, 0x7fff) AM_READ(SMH_BANK1)
r2864	r2865
671	671	AM_RANGE(0x1000, 0x1fff) AM_READ(SMH_RAM) AM_SHARE(2)
672	672	AM_RANGE(0x2000, 0x27ff) AM_READ(SMH_RAM)
673	673	AM_RANGE(0x2800, 0x2fff) AM_READ(dec8_pf0_data_r)
674		AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM) /* Sprites */
	674	AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM) /* Sprites */
675	675	AM_RANGE(0x3800, 0x3bff) AM_READ(SMH_RAM)
676		AM_RANGE(0x3c00, 0x3c00) AM_READ(input_port_0_r)
677		AM_RANGE(0x3c01, 0x3c01) AM_READ(input_port_1_r)
678		AM_RANGE(0x3c02, 0x3c02) AM_READ(input_port_2_r) /* VBL & coins */
679		AM_RANGE(0x3c03, 0x3c03) AM_READ(input_port_3_r) /* Dip 1 */
680		AM_RANGE(0x3c04, 0x3c04) AM_READ(input_port_4_r)
	676	AM_RANGE(0x3c00, 0x3c00) AM_READ_PORT("IN0")
	677	AM_RANGE(0x3c01, 0x3c01) AM_READ_PORT("IN1")
	678	AM_RANGE(0x3c02, 0x3c02) AM_READ_PORT("IN2") /* VBL & coins */
	679	AM_RANGE(0x3c03, 0x3c03) AM_READ_PORT("DSW0") /* Dip 1 */
	680	AM_RANGE(0x3c04, 0x3c04) AM_READ_PORT("DSW1")
681	681	AM_RANGE(0x4000, 0x7fff) AM_READ(SMH_BANK1)
682	682	AM_RANGE(0x8000, 0xffff) AM_READ(SMH_ROM)
683	683	ADDRESS_MAP_END
r2864	r2865
718	718	AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_RAM) AM_SHARE(1)
719	719	AM_RANGE(0x1000, 0x13ff) AM_READ(SMH_RAM) AM_SHARE(3)
720	720	AM_RANGE(0x1400, 0x17ff) AM_READ(SMH_RAM) AM_SHARE(4)
721		AM_RANGE(0x1800, 0x1800) AM_READ(input_port_0_r)
722		AM_RANGE(0x1801, 0x1801) AM_READ(input_port_1_r)
723		AM_RANGE(0x1802, 0x1802) AM_READ(input_port_2_r)
724		AM_RANGE(0x1803, 0x1803) AM_READ(input_port_3_r) /* Dip 1 */
725		AM_RANGE(0x1804, 0x1804) AM_READ(input_port_4_r) /* Dip 2 */
	721	AM_RANGE(0x1800, 0x1800) AM_READ_PORT("IN0")
	722	AM_RANGE(0x1801, 0x1801) AM_READ_PORT("IN1")
	723	AM_RANGE(0x1802, 0x1802) AM_READ_PORT("IN2")
	724	AM_RANGE(0x1803, 0x1803) AM_READ_PORT("DSW0") /* Dip 1 */
	725	AM_RANGE(0x1804, 0x1804) AM_READ_PORT("DSW1") /* Dip 2 */
726	726	AM_RANGE(0x1806, 0x1806) AM_READ(i8751_h_r)
727	727	AM_RANGE(0x1807, 0x1807) AM_READ(i8751_l_r)
728	728	AM_RANGE(0x2000, 0x27ff) AM_READ(SMH_RAM)
r2864	r2865
756	756	AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_RAM) AM_SHARE(1)
757	757	AM_RANGE(0x1000, 0x13ff) AM_READ(SMH_RAM) AM_SHARE(3)
758	758	AM_RANGE(0x1400, 0x17ff) AM_READ(SMH_RAM) AM_SHARE(4)
759		AM_RANGE(0x1800, 0x1800) AM_READ(input_port_0_r)
760		AM_RANGE(0x1801, 0x1801) AM_READ(input_port_1_r)
761		AM_RANGE(0x1802, 0x1802) AM_READ(input_port_2_r)
762		AM_RANGE(0x1803, 0x1803) AM_READ(input_port_3_r) /* Dip 1 */
763		AM_RANGE(0x1804, 0x1804) AM_READ(input_port_4_r) /* Dip 2 */
	759	AM_RANGE(0x1800, 0x1800) AM_READ_PORT("IN0")
	760	AM_RANGE(0x1801, 0x1801) AM_READ_PORT("IN1")
	761	AM_RANGE(0x1802, 0x1802) AM_READ_PORT("IN2")
	762	AM_RANGE(0x1803, 0x1803) AM_READ_PORT("DSW0") /* Dip 1 */
	763	AM_RANGE(0x1804, 0x1804) AM_READ_PORT("DSW1") /* Dip 2 */
764	764	AM_RANGE(0x2000, 0x27ff) AM_READ(SMH_RAM)
765	765	AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM) AM_SHARE(2)
766	766	AM_RANGE(0x3800, 0x3fff) AM_READ(dec8_pf0_data_r)
r2864	r2865
786	786	AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_RAM) AM_SHARE(1)
787	787	AM_RANGE(0x1000, 0x13ff) AM_READ(SMH_RAM) AM_SHARE(3)
788	788	AM_RANGE(0x1400, 0x17ff) AM_READ(SMH_RAM) AM_SHARE(4)
789		AM_RANGE(0x1800, 0x1800) AM_READ(input_port_0_r)
790		AM_RANGE(0x1801, 0x1801) AM_READ(input_port_1_r)
791		AM_RANGE(0x1802, 0x1802) AM_READ(input_port_2_r)
792		AM_RANGE(0x1803, 0x1803) AM_READ(input_port_3_r)
793		AM_RANGE(0x1804, 0x1804) AM_READ(input_port_4_r)
	789	AM_RANGE(0x1800, 0x1800) AM_READ_PORT("IN0")
	790	AM_RANGE(0x1801, 0x1801) AM_READ_PORT("IN1")
	791	AM_RANGE(0x1802, 0x1802) AM_READ_PORT("IN2")
	792	AM_RANGE(0x1803, 0x1803) AM_READ_PORT("DSW0")
	793	AM_RANGE(0x1804, 0x1804) AM_READ_PORT("DSW1")
794	794	AM_RANGE(0x2000, 0x27ff) AM_READ(SMH_RAM)
795	795	AM_RANGE(0x2800, 0x2fff) AM_READ(shackled_sprite_r)
796	796	AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM) AM_SHARE(2)
r2864	r2865
821	821	AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_RAM) AM_SHARE(1)
822	822	AM_RANGE(0x1000, 0x13ff) AM_READ(SMH_RAM) AM_SHARE(3)
823	823	AM_RANGE(0x1400, 0x17ff) AM_READ(SMH_RAM) AM_SHARE(4)
824		AM_RANGE(0x1800, 0x1800) AM_READ(input_port_0_r)
825		AM_RANGE(0x1801, 0x1801) AM_READ(input_port_1_r)
826		AM_RANGE(0x1802, 0x1802) AM_READ(input_port_2_r)
827		AM_RANGE(0x1803, 0x1803) AM_READ(input_port_3_r)
828		AM_RANGE(0x1804, 0x1804) AM_READ(input_port_4_r)
	824	AM_RANGE(0x1800, 0x1800) AM_READ_PORT("IN0")
	825	AM_RANGE(0x1801, 0x1801) AM_READ_PORT("IN1")
	826	AM_RANGE(0x1802, 0x1802) AM_READ_PORT("IN2")
	827	AM_RANGE(0x1803, 0x1803) AM_READ_PORT("DSW0")
	828	AM_RANGE(0x1804, 0x1804) AM_READ_PORT("DSW1")
829	829	AM_RANGE(0x1806, 0x1806) AM_READ(i8751_h_r)
830	830	AM_RANGE(0x1807, 0x1807) AM_READ(i8751_l_r)
831	831	AM_RANGE(0x2000, 0x27ff) AM_READ(SMH_RAM)
r2864	r2865
858	858	AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_RAM) AM_SHARE(1)
859	859	AM_RANGE(0x1000, 0x13ff) AM_READ(SMH_RAM) AM_SHARE(3)
860	860	AM_RANGE(0x1400, 0x17ff) AM_READ(SMH_RAM) AM_SHARE(4)
861		AM_RANGE(0x1800, 0x1800) AM_READ(input_port_1_r)
862		AM_RANGE(0x1801, 0x1801) AM_READ(input_port_0_r)
863		AM_RANGE(0x1803, 0x1803) AM_READ(input_port_2_r)
864		AM_RANGE(0x1804, 0x1804) AM_READ(input_port_4_r) /* Dip 2 */
865		AM_RANGE(0x1805, 0x1805) AM_READ(input_port_3_r) /* Dip 1 */
	861	AM_RANGE(0x1800, 0x1800) AM_READ_PORT("IN1")
	862	AM_RANGE(0x1801, 0x1801) AM_READ_PORT("IN0")
	863	AM_RANGE(0x1803, 0x1803) AM_READ_PORT("IN2")
	864	AM_RANGE(0x1804, 0x1804) AM_READ_PORT("DSW1") /* Dip 2 */
	865	AM_RANGE(0x1805, 0x1805) AM_READ_PORT("DSW0") /* Dip 1 */
866	866	AM_RANGE(0x1c00, 0x1c00) AM_READ(i8751_h_r)
867	867	AM_RANGE(0x1e00, 0x1e00) AM_READ(i8751_l_r)
868	868	AM_RANGE(0x2000, 0x27ff) AM_READ(SMH_RAM)
r2864	r2865
895	895	AM_RANGE(0x0000, 0x0fff) AM_READ(SMH_RAM) AM_SHARE(1)
896	896	AM_RANGE(0x1000, 0x13ff) AM_READ(SMH_RAM) AM_SHARE(3)
897	897	AM_RANGE(0x1400, 0x17ff) AM_READ(SMH_RAM) AM_SHARE(4)
898		AM_RANGE(0x1803, 0x1803) AM_READ(input_port_2_r)
899		AM_RANGE(0x1804, 0x1804) AM_READ(input_port_4_r)
900		AM_RANGE(0x1805, 0x1805) AM_READ(input_port_3_r)
	898	AM_RANGE(0x1803, 0x1803) AM_READ_PORT("IN2")
	899	AM_RANGE(0x1804, 0x1804) AM_READ_PORT("DSW1")
	900	AM_RANGE(0x1805, 0x1805) AM_READ_PORT("DSW0")
901	901	AM_RANGE(0x2000, 0x27ff) AM_READ(SMH_RAM)
902	902	AM_RANGE(0x2800, 0x2fff) AM_READ(SMH_RAM)
903	903	AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM) AM_SHARE(2)
r2864	r2865
925	925	AM_RANGE(0x2000, 0x27ff) AM_READ(dec8_pf0_data_r)
926	926	AM_RANGE(0x2800, 0x2bff) AM_READ(SMH_RAM)
927	927	AM_RANGE(0x2c00, 0x2fff) AM_READ(SMH_RAM)
928		AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM) /* Sprites */
929		AM_RANGE(0x3800, 0x3800) AM_READ(input_port_3_r) /* Dip 1 */
930		AM_RANGE(0x3801, 0x3801) AM_READ(input_port_4_r) /* Dip 2 */
931		AM_RANGE(0x3808, 0x3808) AM_READ(SMH_NOP) /* ? */
932		AM_RANGE(0x380a, 0x380a) AM_READ(input_port_1_r) /* Player 2 + VBL */
933		AM_RANGE(0x380b, 0x380b) AM_READ(input_port_0_r) /* Player 1 */
	928	AM_RANGE(0x3000, 0x37ff) AM_READ(SMH_RAM) /* Sprites */
	929	AM_RANGE(0x3800, 0x3800) AM_READ_PORT("DSW0") /* Dip 1 */
	930	AM_RANGE(0x3801, 0x3801) AM_READ_PORT("DSW1") /* Dip 2 */
	931	AM_RANGE(0x3808, 0x3808) AM_READ(SMH_NOP) /* ? */
	932	AM_RANGE(0x380a, 0x380a) AM_READ_PORT("IN1") /* Player 2 + VBL */
	933	AM_RANGE(0x380b, 0x380b) AM_READ_PORT("IN0") /* Player 1 */
934	934	AM_RANGE(0x383a, 0x383a) AM_READ(i8751_h_r)
935	935	AM_RANGE(0x383b, 0x383b) AM_READ(i8751_l_r)
936	936	AM_RANGE(0x4000, 0x7fff) AM_READ(SMH_BANK1)
r2864	r2865
1146	1146	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1147	1147	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1148	1148
1149		PORT_START_TAG("I8571") /* Dummy input for i8751 */
	1149	PORT_START_TAG("I8751") /* Dummy input for i8751 */
1150	1150	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN4 )
1151	1151	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN3 )
1152	1152	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
r2864	r2865
2045	2045	static INTERRUPT_GEN( ghostb_interrupt )
2046	2046	{
2047	2047	static int latch[4];
2048		int i8751_out=input_port_read~~_indexed~~(machine, 4);
	2048	int i8751_out=input_port_read(machine, "I8751");
2049	2049
2050	2050	/* Ghostbusters coins are controlled by the i8751 */
2051	2051	if ((i8751_out & 0x8) == 0x8) latch[0]=1;
r2864	r2865
2072	2072	{
2073	2073	static int latch=1;
2074	2074
2075		if ((input_port_read_indexed(machine, 2) & 0x7) == 0x7) latch=1;
2076		if (latch && (input_port_read_indexed(machine, 2) & 0x7) != 0x7) {
	2075	if ((input_port_read(machine, "IN2") & 0x7) == 0x7) latch=1;
	2076	if (latch && (input_port_read(machine, "IN2") & 0x7) != 0x7) {
2077	2077	latch=0;
2078	2078	cpunum_set_input_line(machine, 0, INPUT_LINE_NMI, PULSE_LINE);
2079	2079	}

src/mame/drivers/genesis.c
r2864	r2865
444	444
445	445	UINT16 *genesis_io_ram;
446	446
447		READ16_HANDLER ( genesis_io_r )
448		{
449		/* 8-bit only, data is mirrored in both halves */
450
451		UINT8 return_value = 0;
452
453		switch (offset)
454		{
455		case 0:
456		/* Charles MacDonald ( http://cgfm2.emuviews.com/ )
457		D7 : Console is 1= Export (USA, Europe, etc.) 0= Domestic (Japan)
458		D6 : Video type is 1= PAL, 0= NTSC
459		D5 : Sega CD unit is 1= not present, 0= connected.
460		D4 : Unused (always returns zero)
461		D3 : Bit 3 of version number
462		D2 : Bit 2 of version number
463		D1 : Bit 1 of version number
464		D0 : Bit 0 of version number
465		*/
466		return_value = 0x80; /* ? megatech is usa? */
467		break;
468
469		case 1: /* port A data (joypad 1) */
470
471		if (genesis_io_ram[offset] & 0x40)
472		{
473		int iport = input_port_read_indexed(machine, 9);
474		return_value = iport & 0x3f;
475		}
476		else
477		{
478		int iport1 = input_port_read_indexed(machine, 12);
479		int iport2 = input_port_read_indexed(machine, 7) >> 1;
480		return_value = (iport1 & 0x10) + (iport2 & 0x20);
481		if(iport1 & 0x10 \|\| iport2 & 0x20)
482		return_value+=1;
483		}
484
485		return_value = (genesis_io_ram[offset] & 0x80) \| return_value;
486		// logerror ("reading joypad 1 , type %02x %02x\n",genesis_io_ram[offset] & 0x80, return_value &0x7f);
487		if(bios_ctrl_inputs & 0x04) return_value = 0xff;
488		break;
489
490		case 2: /* port B data (joypad 2) */
491
492		if (genesis_io_ram[offset] & 0x40)
493		{
494		int iport1 = (input_port_read_indexed(machine, 9) & 0xc0) >> 6;
495		int iport2 = (input_port_read_indexed(machine, 8) & 0x0f) << 2;
496		return_value = (iport1 + iport2) & 0x3f;
497		}
498		else
499		{
500		int iport1 = input_port_read_indexed(machine, 12) << 2;
501		int iport2 = input_port_read_indexed(machine, 7) >> 2;
502		return_value = (iport1 & 0x10) + (iport2 & 0x20);
503		if(iport1 & 0x10 \|\| iport2 & 0x20)
504		return_value+=1;
505		}
506		return_value = (genesis_io_ram[offset] & 0x80) \| return_value;
507		// logerror ("reading joypad 2 , type %02x %02x\n",genesis_io_ram[offset] & 0x80, return_value &0x7f);
508		if(bios_ctrl_inputs & 0x04) return_value = 0xff;
509		break;
510
511		default:
512		return_value = 0xe0;
513
514		}
515		return return_value \| return_value << 8;
516		}
517
518		READ16_HANDLER ( megaplay_genesis_io_r )
519		{
520		/* 8-bit only, data is mirrored in both halves */
521
522		UINT8 return_value = 0;
523
524		switch (offset)
525		{
526		case 0:
527		/* Charles MacDonald ( http://cgfm2.emuviews.com/ )
528		D7 : Console is 1= Export (USA, Europe, etc.) 0= Domestic (Japan)
529		D6 : Video type is 1= PAL, 0= NTSC
530		D5 : Sega CD unit is 1= not present, 0= connected.
531		D4 : Unused (always returns zero)
532		D3 : Bit 3 of version number
533		D2 : Bit 2 of version number
534		D1 : Bit 1 of version number
535		D0 : Bit 0 of version number
536		*/
537		return_value = 0x80; /* ? megatech is usa? */
538		break;
539
540		case 1: /* port A data (joypad 1) */
541
542		if (genesis_io_ram[offset] & 0x40)
543		return_value = input_port_read_indexed(machine, 1) & (genesis_io_ram[4]^0xff);
544		else
545		{
546		return_value = input_port_read_indexed(machine, 2) & (genesis_io_ram[4]^0xff);
547		return_value \|= input_port_read_indexed(machine, 1) & 0x03;
548		}
549		return_value = (genesis_io_ram[offset] & 0x80) \| return_value;
550		// logerror ("reading joypad 1 , type %02x %02x\n",genesis_io_ram[offset] & 0xb0, return_value &0x7f);
551		break;
552
553		case 2: /* port B data (joypad 2) */
554
555		if (genesis_io_ram[offset] & 0x40)
556		return_value = input_port_read_indexed(machine, 3) & (genesis_io_ram[5]^0xff);
557		else
558		{
559		return_value = input_port_read_indexed(machine, 4) & (genesis_io_ram[5]^0xff);
560		return_value \|= input_port_read_indexed(machine, 3) & 0x03;
561		}
562		return_value = (genesis_io_ram[offset] & 0x80) \| return_value;
563		// logerror ("reading joypad 2 , type %02x %02x\n",genesis_io_ram[offset] & 0xb0, return_value &0x7f);
564		break;
565
566		// case 3: /* port C data */
567		// return_value = bios_6402 << 3;
568		// break;
569
570		default:
571		return_value = genesis_io_ram[offset];
572
573		}
574		return return_value \| return_value << 8;
575		}
576
	447	/* This handler is still used in hshavoc.c & topshoot.c ; */
	448	/* megaplay.c uses a local copy 'OLD_megaplay_genesis_io_w' */
577	449	WRITE16_HANDLER ( genesis_io_w )
578	450	{
579	451	// logerror ("write io offset :%02x data %04x PC: 0x%06x\n",offset,data,activecpu_get_previouspc());

src/mame/drivers/triplhnt.c
r2864	r2865
11	11	***************************************************************************/
12	12
13	13	#include "driver.h"
14		#include "deprecat.h"
15	14	#include "triplhnt.h"
16	15
17	16	static UINT8 triplhnt_cmos[16];
r2864	r2865
28	27	}
29	28
30	29
31		void triplhnt_set_collision(int code)
	30	void triplhnt_set_collision(running_machine *machine, int code)
32	31	{
33	32	triplhnt_hit_code = code;
34	33
35		cpunum_set_input_line(Machine, 0, 0, HOLD_LINE);
	34	cpunum_set_input_line(machine, 0, 0, HOLD_LINE);
36	35	}
37	36
38	37

src/mame/drivers/starwars.c
r2864	r2865
570	570	generic_nvram = auto_malloc(generic_nvram_size);
571	571
572	572	/* init the slapstic */
573		slapstic_init(101);
	573	slapstic_init(machine, 101);
574	574	slapstic_source = &memory_region(REGION_CPU1)[0x14000];
575	575	slapstic_base = &memory_region(REGION_CPU1)[0x08000];
576	576

src/mame/drivers/exerion.c
r2864	r2865
31	31	static READ8_HANDLER( exerion_port01_r )
32	32	{
33	33	/* the cocktail flip bit muxes between ports 0 and 1 */
34		return exerion_cocktail_flip ? input_port_read~~_indexed~~(machine, 1) : input_port_read~~_indexed~~(machine, 0);
	34	return exerion_cocktail_flip ? input_port_read(machine, "IN1") : input_port_read(machine, "IN0");
35	35	}
36	36
37	37
r2864	r2865
95	95	AM_RANGE(0x8800, 0x887f) AM_RAM AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
96	96	AM_RANGE(0x8800, 0x8bff) AM_RAM
97	97	AM_RANGE(0xa000, 0xa000) AM_READ(exerion_port01_r)
98		AM_RANGE(0xa800, 0xa800) AM_READ(input_port_2_r)
99		AM_RANGE(0xb000, 0xb000) AM_READ(input_port_3_r)
	98	AM_RANGE(0xa800, 0xa800) AM_READ_PORT("DSW0")
	99	AM_RANGE(0xb000, 0xb000) AM_READ_PORT("DSW1")
100	100	AM_RANGE(0xc000, 0xc000) AM_WRITE(exerion_videoreg_w)
101	101	AM_RANGE(0xc800, 0xc800) AM_WRITE(soundlatch_w)
102	102	AM_RANGE(0xd000, 0xd000) AM_WRITE(AY8910_control_port_0_w)

src/mame/drivers/segas18.c
r2864	r2865
76	76	*************************************/
77	77
78	78	extern void fd1094_machine_init(void);
79		extern void fd1094_driver_init(void (set_decrypted)(UINT8 ));
	79	extern void fd1094_driver_init(running_machine machine, void (set_decrypted)(UINT8 *));
80	80
81	81	static READ16_HANDLER( misc_io_r );
82	82	static WRITE16_HANDLER( misc_io_w );
r2864	r2865
176	176	segaic16_memory_mapper_init(machine, 0, region_info_list[rom_board], sound_w, sound_r);
177	177
178	178	/* init the FD1094 */
179		fd1094_driver_init(segaic16_memory_mapper_set_decrypted);
	179	fd1094_driver_init(machine, segaic16_memory_mapper_set_decrypted);
180	180
181	181	/* reset the custom handlers and other pointers */
182	182	custom_io_r = NULL;
r2864	r2865
218	218
219	219	static READ16_HANDLER( io_chip_r )
220	220	{
	221	static const char *portnames[] = { "P1", "P2", "PORTC", "PORTD", "SERVICE", "COINAGE", "DSW", "PORTH" };
221	222	offset &= 0x1f/2;
222	223
223	224	switch (offset)
r2864	r2865
236	237	return misc_io_data[offset];
237	238
238	239	/* otherwise, return an input port */
239		return input_port_read~~_indexed~~(machine, offset);
	240	return input_port_read(machine, portnames[offset]);
240	241
241	242	/* 'SEGA' protection */
242	243	case 0x10/2:
r2864	r2865
320	321
321	322	static READ16_HANDLER( misc_io_r )
322	323	{
	324	static const char *portnames[] = { "SERVICE", "COINAGE" };
	325
323	326	offset &= 0x1fff;
	327
324	328	switch (offset & (0x3000/2))
325	329	{
326	330	/* I/O chip */
r2864	r2865
330	334
331	335	/* video control latch */
332	336	case 0x2000/2:
333		return input_port_read~~_indexed~~(machine, ~~4 + (~~offset & 1));
	337	return input_port_read(machine, portnames[offset & 1]);
334	338	}
335	339	if (custom_io_r)
336	340	return custom_io_r(machine, offset, mem_mask);
r2864	r2865
1326	1330	/**************************************************************************************************************************
1327	1331	**************************************************************************************************************************
1328	1332	**************************************************************************************************************************
1329		Alien Storm (2 players version), Sega System 18
1330		CPU: FD1094 (317-????)
	1333	Alien Storm (2 players World version), Sega System 18
	1334	CPU: FD1094 (317-0154)
1331	1335	ROM Board: 171-5873B
1332	1336	*/
1333	1337	ROM_START( astorm )
1334	1338	ROM_REGION( 0x080000, REGION_CPU1, 0 ) /* 68000 code */
1335		ROM_LOAD16_BYTE( "epr13182.bin", 0x000000, 0x40000, CRC(e31f2a1c) SHA1(690ee10c36e5bb6175470fb5564527e0e4a94d2c) )
1336		ROM_LOAD16_BYTE( "epr13181.bin", 0x000001, 0x40000, CRC(78cd3b26) SHA1(a81b807c5da625d8e4648ae80c41e4ca3870c0fa) )
	1339	ROM_LOAD16_BYTE( "epr13182.a6", 0x000000, 0x40000, CRC(e31f2a1c) SHA1(690ee10c36e5bb6175470fb5564527e0e4a94d2c) )
	1340	ROM_LOAD16_BYTE( "epr13181.a5", 0x000001, 0x40000, CRC(78cd3b26) SHA1(a81b807c5da625d8e4648ae80c41e4ca3870c0fa) )
1337	1341
1338	1342	ROM_REGION( 0x2000, REGION_USER1, 0 ) /* decryption key */
1339		ROM_LOAD( "317-~~xxxx~~.key", 0x0000, 0x2000, ~~NO_DUMP~~ )
	1343	ROM_LOAD( "317-0154.key", 0x0000, 0x2000, CRC(b86b6b8f) SHA1(869405383d563a3f3842c89462a7b2e184928532) )
1340	1344
1341	1345	ROM_REGION( 0xc0000, REGION_GFX1, ROMREGION_DISPOSE ) /* tiles */
1342	1346	ROM_LOAD( "epr13073.bin", 0x00000, 0x40000, CRC(df5d0a61) SHA1(79ad71de348f280bad847566c507b7a31f022292) )
r2864	r2865
1354	1358	ROM_LOAD16_BYTE( "epr13086.bin", 0x180000, 0x40000, CRC(8c9a71c4) SHA1(40b774765ac888792aad46b6351a24b7ef40d2dc) )
1355	1359
1356	1360	ROM_REGION( 0x210000, REGION_CPU2, ROMREGION_ERASEFF ) /* sound CPU */
1357		ROM_LOAD( "ep13083a.bin", 0x010000, 0x20000, CRC(e7528e06) SHA1(1f4e618692c20aeb316d578c5ded12440eb072ab) )
1358		ROM_LOAD( "epr13076.bin", 0x090000, 0x40000, CRC(94e6c76e) SHA1(f99e58a9bf372c41af211bd9b9ea3ac5b924c6ed) )
1359		ROM_LOAD( "epr13077.bin", 0x110000, 0x40000, CRC(e2ec0d8d) SHA1(225b0d223b7282cba7710300a877fb4a2c6dbabb) )
1360		ROM_LOAD( "epr13078.bin", 0x190000, 0x40000, CRC(15684dc5) SHA1(595051006de24f791dae937584e502ff2fa31d9c) )
	1361	ROM_LOAD( "epr13083a.bin", 0x010000, 0x20000, CRC(e7528e06) SHA1(1f4e618692c20aeb316d578c5ded12440eb072ab) )
	1362	ROM_LOAD( "epr13076.bin", 0x090000, 0x40000, CRC(94e6c76e) SHA1(f99e58a9bf372c41af211bd9b9ea3ac5b924c6ed) )
	1363	ROM_LOAD( "epr13077.bin", 0x110000, 0x40000, CRC(e2ec0d8d) SHA1(225b0d223b7282cba7710300a877fb4a2c6dbabb) )
	1364	ROM_LOAD( "epr13078.bin", 0x190000, 0x40000, CRC(15684dc5) SHA1(595051006de24f791dae937584e502ff2fa31d9c) )
1361	1365	ROM_END
1362	1366
1363	1367	/**************************************************************************************************************************
1364		Alien Storm (3 players version), Sega System 18
	1368	Alien Storm (3 players World version), Sega System 18
1365	1369	CPU: FD1094 (317-0148)
1366	1370	ROM Board: 171-5873B
1367	1371	Game numbers: 833-7379-02 (main pcb: 834-7381-02, rom pcb: 834-7380-02)
r2864	r2865
1437	1441	*/
1438	1442	ROM_START( astormj )
1439	1443	ROM_REGION( 0x080000, REGION_CPU1, 0 ) /* 68000 code */
1440		ROM_LOAD16_BYTE( "epr13085.bin", 0x000000, 0x40000, CRC(15f74e2d) SHA1(30d9d099ec18907edd3d20df312565c3bd5a80de) )
1441		ROM_LOAD16_BYTE( "epr13084.bin", 0x000001, 0x40000, CRC(9687b38f) SHA1(cdeb5b4f06ad4ad8ca579392c1ec901487b08e76) )
	1444	ROM_LOAD16_BYTE( "epr13085.a6", 0x000000, 0x40000, CRC(15f74e2d) SHA1(30d9d099ec18907edd3d20df312565c3bd5a80de) )
	1445	ROM_LOAD16_BYTE( "epr13084.a5", 0x000001, 0x40000, CRC(9687b38f) SHA1(cdeb5b4f06ad4ad8ca579392c1ec901487b08e76) )
1442	1446
1443	1447	ROM_REGION( 0x2000, REGION_USER1, 0 ) /* decryption key */
1444	1448	ROM_LOAD( "317-0146.key", 0x0000, 0x2000, CRC(e94991c5) SHA1(c9a8b56e01792654436f24b219d7a92c0852461f) )
r2864	r2865
2248	2252	*
2249	2253	*************************************/
2250	2254
2251		GAME( 1990, astorm, 0, system18, astorm2p, generic_5874, ROT0, "Sega", "Alien Storm (set 4, 2 Players, FD1094 317-?)", ~~GAME_NOT_WORKING~~ ) ~~// not decrypted~~
	2255	GAME( 1990, astorm, 0, system18, astorm2p, generic_5874, ROT0, "Sega", "Alien Storm (set 4, World, 2 Players, FD1094 317-0154)", 0 )
2252	2256	GAME( 1990, astorm3, astorm, system18, astorm, generic_5874, ROT0, "Sega", "Alien Storm (set 3, World, 3 Players, FD1094 317-0148)", 0 )
2253	2257	GAME( 1990, astormu, astorm, system18, astorm, generic_5874, ROT0, "Sega", "Alien Storm (set 2, US, 3 Players, FD1094 317-0147)", 0 )
2254	2258	GAME( 1990, astormj, astorm, system18, astorm2p, generic_5874, ROT0, "Sega", "Alien Storm (set 1, Japan, 2 Players, FD1094 317-0146)", 0 )

src/osd/windows/drawgdi.c
r2864	r2865
13	13
14	14	// MAME headers
15	15	#include "mamecore.h"
	16	#include "restrack.h"
16	17
17	18	// MAMEOS headers
18	19	#include "window.h"

src/osd/windows/window.c
r2864	r2865
843	843	static void set_starting_view(running_machine machine, int index, win_window_info window, const char *view)
844	844	{
845	845	const char *defview = options_get_string(mame_options(), WINOPTION_VIEW);
846		int viewindex ~~= -1~~;
	846	int viewindex;
847	847
848	848	assert(GetCurrentThreadId() == main_threadid);
849	849
r2864	r2865
851	851	if (strcmp(view, "auto") == 0 && strcmp(defview, "auto") != 0)
852	852	view = defview;
853	853
854		// auto view just selects the nth view
855		if (strcmp(view, "auto") != 0)
856		{
857		// scan for a matching view name
858		for (viewindex = 0; ; viewindex++)
859		{
860		const char *name = render_target_get_view_name(window->target, viewindex);
	854	// query the video system to help us pick a view
	855	viewindex = video_get_view_for_target(machine, window->target, view, index, video_config.numscreens);
861	856
862		// stop scanning if we hit NULL
863		if (name == NULL)
864		{
865		viewindex = -1;
866		break;
867		}
868		if (mame_strnicmp(name, view, strlen(view)) == 0)
869		break;
870		}
871		}
872
873		// if we don't have a match, default to the nth view
874		if (viewindex == -1)
875		{
876		int scrcount = video_screen_count(machine->config);
877
878		// if we have enough screens to be one per monitor, assign in order
879		if (video_config.numscreens >= scrcount)
880		{
881		// find the first view with this screen and this screen only
882		for (viewindex = 0; ; viewindex++)
883		{
884		UINT32 viewscreens = render_target_get_view_screens(window->target, viewindex);
885		if (viewscreens == (1 << index))
886		break;
887		if (viewscreens == 0)
888		{
889		viewindex = -1;
890		break;
891		}
892		}
893		}
894
895		// otherwise, find the first view that has all the screens
896		if (viewindex == -1)
897		{
898		for (viewindex = 0; ; viewindex++)
899		{
900		UINT32 viewscreens = render_target_get_view_screens(window->target, viewindex);
901		if (viewscreens == (1 << scrcount) - 1)
902		break;
903		if (viewscreens == 0)
904		break;
905		}
906		}
907		}
908
909		// make sure it's a valid view
910		if (render_target_get_view_name(window->target, viewindex) == NULL)
911		viewindex = 0;
912
913	857	// set the view
914	858	render_target_set_view(window->target, viewindex);
915	859	}

src/emu/debug/debugcmd.c
r2864	r2865
2028	2028	return;
2029	2029	}
2030	2030
2031		video_screen_save_snapshot(screen, fp);
	2031	video_screen_save_snapshot(screen->machine, screen, fp);
2032	2032	mame_fclose(fp);
2033	2033	debug_console_printf("Saved screen #%d snapshot as '%s'\n", scrnum, filename);
2034	2034	}

src/emu/cpu/cpu.mak
r2864	r2865
15	15
16	16
17	17	#-------------------------------------------------
	18	# Shared code
	19	#-------------------------------------------------
	20
	21	OBJDIRS += $(CPUOBJ)
	22	CPUOBJS += $(CPUOBJ)/vtlb.o
	23
	24
	25
	26	#-------------------------------------------------
18	27	# Dynamic recompiler objects
19	28	#-------------------------------------------------
20	29

src/emu/cpu/drcuml.c
r2864	r2865
113	113	#define PTYPES_IANY (PTYPES_IRM \| PTYPES_IMV)
114	114	#define PTYPES_FANY (PTYPES_FRM)
115	115
	116	/* test result undefined */
	117	#define UNDEFINED 0x19bb7a1005fde439
	118	#define UNDEFINED_U64 U64(0x19bb7a1005fde439)
116	119
117	120
	121
118	122	/***************************************************************************
119	123	TYPE DEFINITIONS
120	124	***************************************************************************/
r2864	r2865
173	177	{
174	178	drcuml_opcode opcode;
175	179	UINT8 size;
176		UINT8 destmask;
177	180	UINT8 iflags;
178	181	UINT8 flags;
179	182	UINT64 param[4];
r2864	r2865
315	318
316	319	static void validate_instruction(drcuml_block block, const drcuml_instruction inst);
317	320
318		#if 0
319	321	static void validate_backend(drcuml_state *drcuml);
320	322	static void bevalidate_iterate_over_params(drcuml_state drcuml, drcuml_codehandle handles, const bevalidate_test test, drcuml_parameter *paramlist, int pnum);
321	323	static void bevalidate_iterate_over_flags(drcuml_state drcuml, drcuml_codehandle handles, const bevalidate_test test, drcuml_parameter *paramlist);
322	324	static void bevalidate_execute(drcuml_state drcuml, drcuml_codehandle handles, const bevalidate_test test, const drcuml_parameter *paramlist, UINT8 flagmask);
323	325	static void bevalidate_initialize_random_state(drcuml_block block, drcuml_machine_state state);
324	326	static int bevalidate_populate_state(drcuml_block block, drcuml_machine_state state, const bevalidate_test test, const drcuml_parameter paramlist, drcuml_parameter params, UINT64 parammem);
325		static int bevalidate_verify_state(drcuml_state drcuml, const drcuml_machine_state istate, drcuml_machine_state state, const bevalidate_test test, const drcuml_parameter params, const drcuml_instruction testinst, drccodeptr codestart, drccodeptr codeend, UINT8 flagmask);
326		#endif
	327	static int bevalidate_verify_state(drcuml_state drcuml, const drcuml_machine_state istate, drcuml_machine_state state, const bevalidate_test test, UINT32 flags, const drcuml_parameter params, const drcuml_instruction testinst, drccodeptr codestart, drccodeptr codeend, UINT8 flagmask);
327	328
328	329
329	330
r2864	r2865
427	428
428	429
429	430	/*-------------------------------------------------
	431	effective_test_psize - return the effective
	432	parameter size based on the size and fixed
	433	array of parameter values
	434	-------------------------------------------------*/
	435
	436	INLINE UINT8 effective_test_psize(const drcuml_opcode_info opinfo, int pnum, int instsize, const UINT64 params)
	437	{
	438	switch (opinfo->param[pnum].size)
	439	{
	440	case PSIZE_4: return 4;
	441	case PSIZE_8: return 8;
	442	case PSIZE_OP: return instsize;
	443	case PSIZE_P1: return 1 << (params[0] & 3);
	444	case PSIZE_P2: return 1 << (params[1] & 3);
	445	case PSIZE_P3: return 1 << (params[2] & 3);
	446	case PSIZE_P4: return 1 << (params[3] & 3);
	447	}
	448	return instsize;
	449	}
	450
	451
	452	/*-------------------------------------------------
430	453	param_is_immediate - return TRUE if the
431	454	given instruction parameter is an immediate
432	455	-------------------------------------------------*/
r2864	r2865
588	611	(*drcuml->beintf->be_reset)(drcuml->bestate);
589	612
590	613	/* do a one-time validation if requested */
591		/* if (VALIDATE_BACKEND)
592		{
593		static int validated = FALSE;
594		if (!validated)
595		{
596		validated = TRUE;
597		validate_backend(drcuml);
598		}
599		}*/
	614	if (VALIDATE_BACKEND)
	615	{
	616	static int validated = FALSE;
	617	if (!validated)
	618	{
	619	validated = TRUE;
	620	validate_backend(drcuml);
	621	}
	622	}
600	623	}
601	624
602	625
r2864	r2865
1861	1884
1862	1885
1863	1886
1864		#if 0
1865
1866	1887	/***************************************************************************
1867	1888	BACK-END VALIDATION
1868	1889	***************************************************************************/
1869	1890
1870		#define TEST_ENTRY_DSS(op, size, p1, p2, p3, flags) { DRCUML_OP_##op, size, 0x01, 0, flags, { U64(p1), U64(p2), U64(p3) } },
1871		#define TEST_ENTRY_DSSI(op, size, p1, p2, p3, iflags, flags) { DRCUML_OP_##op, size, 0x01, iflags, flags, { U64(p1), U64(p2), U64(p3) } },
	1891	#define TEST_ENTRY_2(op, size, p1, p2, flags) { DRCUML_OP_##op, size, 0, flags, { U64(p1), U64(p2) } },
	1892	#define TEST_ENTRY_2F(op, size, p1, p2, iflags, flags) { DRCUML_OP_##op, size, iflags, flags, { U64(p1), U64(p2) } },
	1893	#define TEST_ENTRY_3(op, size, p1, p2, p3, flags) { DRCUML_OP_##op, size, 0, flags, { U64(p1), U64(p2), U64(p3) } },
	1894	#define TEST_ENTRY_3F(op, size, p1, p2, p3, iflags, flags) { DRCUML_OP_##op, size, iflags, flags, { U64(p1), U64(p2), U64(p3) } },
	1895	#define TEST_ENTRY_4(op, size, p1, p2, p3, p4, flags) { DRCUML_OP_##op, size, 0, flags, { U64(p1), U64(p2), U64(p3), U64(p4) } },
	1896	#define TEST_ENTRY_4F(op, size, p1, p2, p3, p4, iflags, flags) { DRCUML_OP_##op, size, iflags, flags, { U64(p1), U64(p2), U64(p3), U64(p4) } },
1872	1897
1873	1898	static const bevalidate_test bevalidate_test_list[] =
1874	1899	{
1875		TEST_ENTRY_DSS(ADD, 4, 0x7fffffff, 0x12345678, 0x6dcba987, 0)
1876		TEST_ENTRY_DSS(ADD, 4, 0x80000000, 0x12345678, 0x6dcba988, FLAGS_V \| FLAGS_S)
1877		TEST_ENTRY_DSS(ADD, 4, 0xffffffff, 0x92345678, 0x6dcba987, FLAGS_S)
1878		TEST_ENTRY_DSS(ADD, 4, 0x00000000, 0x92345678, 0x6dcba988, FLAGS_C \| FLAGS_Z)
	1900	TEST_ENTRY_3(ADD, 4, 0x7fffffff, 0x12345678, 0x6dcba987, 0)
	1901	TEST_ENTRY_3(ADD, 4, 0x80000000, 0x12345678, 0x6dcba988, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1902	TEST_ENTRY_3(ADD, 4, 0xffffffff, 0x92345678, 0x6dcba987, DRCUML_FLAG_S)
	1903	TEST_ENTRY_3(ADD, 4, 0x00000000, 0x92345678, 0x6dcba988, DRCUML_FLAG_C \| DRCUML_FLAG_Z)
1879	1904
1880		TEST_ENTRY_DSS(ADD, 8, 0x7fffffffffffffff, 0x0123456789abcdef, 0x7edcba9876543210, 0)
1881		TEST_ENTRY_DSS(ADD, 8, 0x8000000000000000, 0x0123456789abcdef, 0x7edcba9876543211, FLAGS_V \| FLAGS_S)
1882		TEST_ENTRY_DSS(ADD, 8, 0xffffffffffffffff, 0x8123456789abcdef, 0x7edcba9876543210, FLAGS_S)
1883		TEST_ENTRY_DSS(ADD, 8, 0x0000000000000000, 0x8123456789abcdef, 0x7edcba9876543211, FLAGS_C \| FLAGS_Z)
	1905	TEST_ENTRY_3(ADD, 8, 0x7fffffffffffffff, 0x0123456789abcdef, 0x7edcba9876543210, 0)
	1906	TEST_ENTRY_3(ADD, 8, 0x8000000000000000, 0x0123456789abcdef, 0x7edcba9876543211, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1907	TEST_ENTRY_3(ADD, 8, 0xffffffffffffffff, 0x8123456789abcdef, 0x7edcba9876543210, DRCUML_FLAG_S)
	1908	TEST_ENTRY_3(ADD, 8, 0x0000000000000000, 0x8123456789abcdef, 0x7edcba9876543211, DRCUML_FLAG_C \| DRCUML_FLAG_Z)
1884	1909
1885		TEST_ENTRY_DSSI(ADDC, 4, 0x7fffffff, 0x12345678, 0x6dcba987, 0, 0)
1886		TEST_ENTRY_DSSI(ADDC, 4, 0x7fffffff, 0x12345678, 0x6dcba986, FLAGS_C, 0)
1887		TEST_ENTRY_DSSI(ADDC, 4, 0x80000000, 0x12345678, 0x6dcba988, 0, FLAGS_V \| FLAGS_S)
1888		TEST_ENTRY_DSSI(ADDC, 4, 0x80000000, 0x12345678, 0x6dcba987, FLAGS_C, FLAGS_V \| FLAGS_S)
1889		TEST_ENTRY_DSSI(ADDC, 4, 0xffffffff, 0x92345678, 0x6dcba987, 0, FLAGS_S)
1890		TEST_ENTRY_DSSI(ADDC, 4, 0xffffffff, 0x92345678, 0x6dcba986, FLAGS_C, FLAGS_S)
1891		TEST_ENTRY_DSSI(ADDC, 4, 0x00000000, 0x92345678, 0x6dcba988, 0, FLAGS_C \| FLAGS_Z)
1892		TEST_ENTRY_DSSI(ADDC, 4, 0x00000000, 0x92345678, 0x6dcba987, FLAGS_C, FLAGS_C \| FLAGS_Z)
1893		TEST_ENTRY_DSSI(ADDC, 4, 0x12345678, 0x12345678, 0xffffffff, FLAGS_C, FLAGS_C)
	1910	TEST_ENTRY_3F(ADDC, 4, 0x7fffffff, 0x12345678, 0x6dcba987, 0, 0)
	1911	TEST_ENTRY_3F(ADDC, 4, 0x7fffffff, 0x12345678, 0x6dcba986, DRCUML_FLAG_C, 0)
	1912	TEST_ENTRY_3F(ADDC, 4, 0x80000000, 0x12345678, 0x6dcba988, 0, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1913	TEST_ENTRY_3F(ADDC, 4, 0x80000000, 0x12345678, 0x6dcba987, DRCUML_FLAG_C, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1914	TEST_ENTRY_3F(ADDC, 4, 0xffffffff, 0x92345678, 0x6dcba987, 0, DRCUML_FLAG_S)
	1915	TEST_ENTRY_3F(ADDC, 4, 0xffffffff, 0x92345678, 0x6dcba986, DRCUML_FLAG_C, DRCUML_FLAG_S)
	1916	TEST_ENTRY_3F(ADDC, 4, 0x00000000, 0x92345678, 0x6dcba988, 0, DRCUML_FLAG_C \| DRCUML_FLAG_Z)
	1917	TEST_ENTRY_3F(ADDC, 4, 0x00000000, 0x92345678, 0x6dcba987, DRCUML_FLAG_C, DRCUML_FLAG_C \| DRCUML_FLAG_Z)
	1918	TEST_ENTRY_3F(ADDC, 4, 0x12345678, 0x12345678, 0xffffffff, DRCUML_FLAG_C, DRCUML_FLAG_C)
1894	1919
1895		TEST_ENTRY_DSSI(ADDC, 8, 0x7fffffffffffffff, 0x0123456789abcdef, 0x7edcba9876543210, 0, 0)
1896		TEST_ENTRY_DSSI(ADDC, 8, 0x7fffffffffffffff, 0x0123456789abcdef, 0x7edcba987654320f, FLAGS_C, 0)
1897		TEST_ENTRY_DSSI(ADDC, 8, 0x8000000000000000, 0x0123456789abcdef, 0x7edcba9876543211, 0, FLAGS_V \| FLAGS_S)
1898		TEST_ENTRY_DSSI(ADDC, 8, 0x8000000000000000, 0x0123456789abcdef, 0x7edcba9876543210, FLAGS_C, FLAGS_V \| FLAGS_S)
1899		TEST_ENTRY_DSSI(ADDC, 8, 0xffffffffffffffff, 0x8123456789abcdef, 0x7edcba9876543210, 0, FLAGS_S)
1900		TEST_ENTRY_DSSI(ADDC, 8, 0xffffffffffffffff, 0x8123456789abcdef, 0x7edcba987654320f, FLAGS_C, FLAGS_S)
1901		TEST_ENTRY_DSSI(ADDC, 8, 0x0000000000000000, 0x8123456789abcdef, 0x7edcba9876543211, 0, FLAGS_C \| FLAGS_Z)
1902		TEST_ENTRY_DSSI(ADDC, 8, 0x0000000000000000, 0x8123456789abcdef, 0x7edcba9876543210, FLAGS_C, FLAGS_C \| FLAGS_Z)
1903		TEST_ENTRY_DSSI(ADDC, 8, 0x123456789abcdef0, 0x123456789abcdef0, 0xffffffffffffffff, FLAGS_C, FLAGS_C)
	1920	TEST_ENTRY_3F(ADDC, 8, 0x7fffffffffffffff, 0x0123456789abcdef, 0x7edcba9876543210, 0, 0)
	1921	TEST_ENTRY_3F(ADDC, 8, 0x7fffffffffffffff, 0x0123456789abcdef, 0x7edcba987654320f, DRCUML_FLAG_C, 0)
	1922	TEST_ENTRY_3F(ADDC, 8, 0x8000000000000000, 0x0123456789abcdef, 0x7edcba9876543211, 0, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1923	TEST_ENTRY_3F(ADDC, 8, 0x8000000000000000, 0x0123456789abcdef, 0x7edcba9876543210, DRCUML_FLAG_C, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1924	TEST_ENTRY_3F(ADDC, 8, 0xffffffffffffffff, 0x8123456789abcdef, 0x7edcba9876543210, 0, DRCUML_FLAG_S)
	1925	TEST_ENTRY_3F(ADDC, 8, 0xffffffffffffffff, 0x8123456789abcdef, 0x7edcba987654320f, DRCUML_FLAG_C, DRCUML_FLAG_S)
	1926	TEST_ENTRY_3F(ADDC, 8, 0x0000000000000000, 0x8123456789abcdef, 0x7edcba9876543211, 0, DRCUML_FLAG_C \| DRCUML_FLAG_Z)
	1927	TEST_ENTRY_3F(ADDC, 8, 0x0000000000000000, 0x8123456789abcdef, 0x7edcba9876543210, DRCUML_FLAG_C, DRCUML_FLAG_C \| DRCUML_FLAG_Z)
	1928	TEST_ENTRY_3F(ADDC, 8, 0x123456789abcdef0, 0x123456789abcdef0, 0xffffffffffffffff, DRCUML_FLAG_C, DRCUML_FLAG_C)
	1929
	1930	TEST_ENTRY_3(SUB, 4, 0x12345678, 0x7fffffff, 0x6dcba987, 0)
	1931	TEST_ENTRY_3(SUB, 4, 0x12345678, 0x80000000, 0x6dcba988, DRCUML_FLAG_V)
	1932	TEST_ENTRY_3(SUB, 4, 0x92345678, 0xffffffff, 0x6dcba987, DRCUML_FLAG_S)
	1933	TEST_ENTRY_3(SUB, 4, 0x92345678, 0x00000000, 0x6dcba988, DRCUML_FLAG_C \| DRCUML_FLAG_S)
	1934	TEST_ENTRY_3(SUB, 4, 0x00000000, 0x12345678, 0x12345678, DRCUML_FLAG_Z)
	1935
	1936	TEST_ENTRY_3(SUB, 8, 0x0123456789abcdef, 0x7fffffffffffffff, 0x7edcba9876543210, 0)
	1937	TEST_ENTRY_3(SUB, 8, 0x0123456789abcdef, 0x8000000000000000, 0x7edcba9876543211, DRCUML_FLAG_V)
	1938	TEST_ENTRY_3(SUB, 8, 0x8123456789abcdef, 0xffffffffffffffff, 0x7edcba9876543210, DRCUML_FLAG_S)
	1939	TEST_ENTRY_3(SUB, 8, 0x8123456789abcdef, 0x0000000000000000, 0x7edcba9876543211, DRCUML_FLAG_C \| DRCUML_FLAG_S)
	1940	TEST_ENTRY_3(SUB, 8, 0x0000000000000000, 0x0123456789abcdef, 0x0123456789abcdef, DRCUML_FLAG_Z)
	1941
	1942	TEST_ENTRY_3F(SUBB, 4, 0x12345678, 0x7fffffff, 0x6dcba987, 0, 0)
	1943	TEST_ENTRY_3F(SUBB, 4, 0x12345678, 0x7fffffff, 0x6dcba986, DRCUML_FLAG_C, 0)
	1944	TEST_ENTRY_3F(SUBB, 4, 0x12345678, 0x80000000, 0x6dcba988, 0, DRCUML_FLAG_V)
	1945	TEST_ENTRY_3F(SUBB, 4, 0x12345678, 0x80000000, 0x6dcba987, DRCUML_FLAG_C, DRCUML_FLAG_V)
	1946	TEST_ENTRY_3F(SUBB, 4, 0x92345678, 0xffffffff, 0x6dcba987, 0, DRCUML_FLAG_S)
	1947	TEST_ENTRY_3F(SUBB, 4, 0x92345678, 0xffffffff, 0x6dcba986, DRCUML_FLAG_C, DRCUML_FLAG_S)
	1948	TEST_ENTRY_3F(SUBB, 4, 0x92345678, 0x00000000, 0x6dcba988, 0, DRCUML_FLAG_C \| DRCUML_FLAG_S)
	1949	TEST_ENTRY_3F(SUBB, 4, 0x92345678, 0x00000000, 0x6dcba987, DRCUML_FLAG_C, DRCUML_FLAG_C \| DRCUML_FLAG_S)
	1950	TEST_ENTRY_3F(SUBB, 4, 0x12345678, 0x12345678, 0xffffffff, DRCUML_FLAG_C, DRCUML_FLAG_C)
	1951	TEST_ENTRY_3F(SUBB, 4, 0x00000000, 0x12345678, 0x12345677, DRCUML_FLAG_C, DRCUML_FLAG_Z)
	1952
	1953	TEST_ENTRY_3F(SUBB, 8, 0x0123456789abcdef, 0x7fffffffffffffff, 0x7edcba9876543210, 0, 0)
	1954	TEST_ENTRY_3F(SUBB, 8, 0x0123456789abcdef, 0x7fffffffffffffff, 0x7edcba987654320f, DRCUML_FLAG_C, 0)
	1955	TEST_ENTRY_3F(SUBB, 8, 0x0123456789abcdef, 0x8000000000000000, 0x7edcba9876543211, 0, DRCUML_FLAG_V)
	1956	TEST_ENTRY_3F(SUBB, 8, 0x0123456789abcdef, 0x8000000000000000, 0x7edcba9876543210, DRCUML_FLAG_C, DRCUML_FLAG_V)
	1957	TEST_ENTRY_3F(SUBB, 8, 0x8123456789abcdef, 0xffffffffffffffff, 0x7edcba9876543210, 0, DRCUML_FLAG_S)
	1958	TEST_ENTRY_3F(SUBB, 8, 0x8123456789abcdef, 0xffffffffffffffff, 0x7edcba987654320f, DRCUML_FLAG_C, DRCUML_FLAG_S)
	1959	TEST_ENTRY_3F(SUBB, 8, 0x8123456789abcdef, 0x0000000000000000, 0x7edcba9876543211, 0, DRCUML_FLAG_C \| DRCUML_FLAG_S)
	1960	TEST_ENTRY_3F(SUBB, 8, 0x8123456789abcdef, 0x0000000000000000, 0x7edcba9876543210, DRCUML_FLAG_C, DRCUML_FLAG_C \| DRCUML_FLAG_S)
	1961	TEST_ENTRY_3F(SUBB, 8, 0x123456789abcdef0, 0x123456789abcdef0, 0xffffffffffffffff, DRCUML_FLAG_C, DRCUML_FLAG_C)
	1962	TEST_ENTRY_3F(SUBB, 8, 0x0000000000000000, 0x123456789abcdef0, 0x123456789abcdeef, DRCUML_FLAG_C, DRCUML_FLAG_Z)
	1963
	1964	TEST_ENTRY_2(CMP, 4, 0x7fffffff, 0x6dcba987, 0)
	1965	TEST_ENTRY_2(CMP, 4, 0x80000000, 0x6dcba988, DRCUML_FLAG_V)
	1966	TEST_ENTRY_2(CMP, 4, 0xffffffff, 0x6dcba987, DRCUML_FLAG_S)
	1967	TEST_ENTRY_2(CMP, 4, 0x00000000, 0x6dcba988, DRCUML_FLAG_C \| DRCUML_FLAG_S)
	1968	TEST_ENTRY_2(CMP, 4, 0x12345678, 0x12345678, DRCUML_FLAG_Z)
	1969
	1970	TEST_ENTRY_2(CMP, 8, 0x7fffffffffffffff, 0x7edcba9876543210, 0)
	1971	TEST_ENTRY_2(CMP, 8, 0x8000000000000000, 0x7edcba9876543211, DRCUML_FLAG_V)
	1972	TEST_ENTRY_2(CMP, 8, 0xffffffffffffffff, 0x7edcba9876543210, DRCUML_FLAG_S)
	1973	TEST_ENTRY_2(CMP, 8, 0x0000000000000000, 0x7edcba9876543211, DRCUML_FLAG_C \| DRCUML_FLAG_S)
	1974	TEST_ENTRY_2(CMP, 8, 0x0123456789abcdef, 0x0123456789abcdef, DRCUML_FLAG_Z)
	1975
	1976	TEST_ENTRY_4(MULU, 4, 0x77777777, 0x00000000, 0x11111111, 0x00000007, 0)
	1977	TEST_ENTRY_4(MULU, 4, 0xffffffff, 0x00000000, 0x11111111, 0x0000000f, 0)
	1978	TEST_ENTRY_4(MULU, 4, 0x00000000, 0x00000000, 0x11111111, 0x00000000, DRCUML_FLAG_Z)
	1979	TEST_ENTRY_4(MULU, 4, 0xea61d951, 0x37c048d0, 0x77777777, 0x77777777, DRCUML_FLAG_V)
	1980	TEST_ENTRY_4(MULU, 4, 0x32323233, 0xcdcdcdcc, 0xcdcdcdcd, 0xffffffff, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1981
	1982	TEST_ENTRY_4(MULU, 8, 0x7777777777777777, 0x0000000000000000, 0x1111111111111111, 0x0000000000000007, 0)
	1983	TEST_ENTRY_4(MULU, 8, 0xffffffffffffffff, 0x0000000000000000, 0x1111111111111111, 0x000000000000000f, 0)
	1984	TEST_ENTRY_4(MULU, 8, 0x0000000000000000, 0x0000000000000000, 0x1111111111111111, 0x0000000000000000, DRCUML_FLAG_Z)
	1985	TEST_ENTRY_4(MULU, 8, 0x0c83fb72ea61d951, 0x37c048d159e26af3, 0x7777777777777777, 0x7777777777777777, DRCUML_FLAG_V)
	1986	TEST_ENTRY_4(MULU, 8, 0x3232323232323233, 0xcdcdcdcdcdcdcdcc, 0xcdcdcdcdcdcdcdcd, 0xffffffffffffffff, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1987
	1988	TEST_ENTRY_4(MULS, 4, 0x77777777, 0x00000000, 0x11111111, 0x00000007, 0)
	1989	TEST_ENTRY_4(MULS, 4, 0xffffffff, 0x00000000, 0x11111111, 0x0000000f, DRCUML_FLAG_V)
	1990	TEST_ENTRY_4(MULS, 4, 0x00000000, 0x00000000, 0x11111111, 0x00000000, DRCUML_FLAG_Z)
	1991	TEST_ENTRY_4(MULS, 4, 0x9e26af38, 0xc83fb72e, 0x77777777, 0x88888888, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1992	TEST_ENTRY_4(MULS, 4, 0x32323233, 0x00000000, 0xcdcdcdcd, 0xffffffff, 0)
	1993
	1994	TEST_ENTRY_4(MULS, 8, 0x7777777777777777, 0x0000000000000000, 0x1111111111111111, 0x0000000000000007, 0)
	1995	TEST_ENTRY_4(MULS, 8, 0xffffffffffffffff, 0x0000000000000000, 0x1111111111111111, 0x000000000000000f, DRCUML_FLAG_V)
	1996	TEST_ENTRY_4(MULS, 8, 0x0000000000000000, 0x0000000000000000, 0x1111111111111111, 0x0000000000000000, DRCUML_FLAG_Z)
	1997	TEST_ENTRY_4(MULS, 8, 0x7c048d159e26af38, 0xc83fb72ea61d950c, 0x7777777777777777, 0x8888888888888888, DRCUML_FLAG_V \| DRCUML_FLAG_S)
	1998	TEST_ENTRY_4(MULS, 8, 0x3232323232323233, 0x0000000000000000, 0xcdcdcdcdcdcdcdcd, 0xffffffffffffffff, 0)
	1999
	2000	TEST_ENTRY_4(DIVU, 4, 0x02702702, 0x00000003, 0x11111111, 0x00000007, 0)
	2001	TEST_ENTRY_4(DIVU, 4, 0x00000000, 0x11111111, 0x11111111, 0x11111112, DRCUML_FLAG_Z)
	2002	TEST_ENTRY_4(DIVU, 4, 0x7fffffff, 0x00000000, 0xfffffffe, 0x00000002, 0)
	2003	TEST_ENTRY_4(DIVU, 4, 0xfffffffe, 0x00000000, 0xfffffffe, 0x00000001, DRCUML_FLAG_S)
	2004	TEST_ENTRY_4(DIVU, 4, UNDEFINED, UNDEFINED, 0xffffffff, 0x00000000, DRCUML_FLAG_V)
	2005
	2006	TEST_ENTRY_4(DIVU, 8, 0x0270270270270270, 0x0000000000000001, 0x1111111111111111, 0x0000000000000007, 0)
	2007	TEST_ENTRY_4(DIVU, 8, 0x0000000000000000, 0x1111111111111111, 0x1111111111111111, 0x1111111111111112, DRCUML_FLAG_Z)
	2008	TEST_ENTRY_4(DIVU, 8, 0x7fffffffffffffff, 0x0000000000000000, 0xfffffffffffffffe, 0x0000000000000002, 0)
	2009	TEST_ENTRY_4(DIVU, 8, 0xfffffffffffffffe, 0x0000000000000000, 0xfffffffffffffffe, 0x0000000000000001, DRCUML_FLAG_S)
	2010	TEST_ENTRY_4(DIVU, 8, UNDEFINED, UNDEFINED, 0xffffffffffffffff, 0x0000000000000000, DRCUML_FLAG_V)
	2011
	2012	TEST_ENTRY_4(DIVS, 4, 0x02702702, 0x00000003, 0x11111111, 0x00000007, 0)
	2013	TEST_ENTRY_4(DIVS, 4, 0x00000000, 0x11111111, 0x11111111, 0x11111112, DRCUML_FLAG_Z)
	2014	TEST_ENTRY_4(DIVS, 4, 0xffffffff, 0x00000000, 0xfffffffe, 0x00000002, DRCUML_FLAG_S)
	2015	TEST_ENTRY_4(DIVS, 4, UNDEFINED, UNDEFINED, 0xffffffff, 0x00000000, DRCUML_FLAG_V)
	2016
	2017	TEST_ENTRY_4(DIVS, 8, 0x0270270270270270, 0x0000000000000001, 0x1111111111111111, 0x0000000000000007, 0)
	2018	TEST_ENTRY_4(DIVS, 8, 0x0000000000000000, 0x1111111111111111, 0x1111111111111111, 0x1111111111111112, DRCUML_FLAG_Z)
	2019	TEST_ENTRY_4(DIVS, 8, 0xffffffffffffffff, 0x0000000000000000, 0xfffffffffffffffe, 0x0000000000000002, DRCUML_FLAG_S)
	2020	TEST_ENTRY_4(DIVS, 8, UNDEFINED, UNDEFINED, 0xffffffffffffffff, 0x0000000000000000, DRCUML_FLAG_V)
1904	2021	};
1905	2022
1906	2023
r2864	r2865
1921	2038
1922	2039	/* iterate over test entries */
1923	2040	printf("Backend validation....\n");
1924		for (tnum = 0; tnum < ARRAY_LENGTH(bevalidate_test_list); tnum++)
	2041	for (tnum = 31; tnum < ARRAY_LENGTH(bevalidate_test_list); tnum++)
1925	2042	{
1926	2043	const bevalidate_test *test = &bevalidate_test_list[tnum];
1927	2044	drcuml_parameter param[ARRAY_LENGTH(test->param)];
	2045	char mnemonic[20], *dst;
	2046	const char *src;
1928	2047
	2048	/* progress */
	2049	dst = mnemonic;
	2050	for (src = opcode_info_table[test->opcode]->mnemonic; *src != 0; src++)
	2051	{
	2052	if (*src == '!')
	2053	{
	2054	if (test->size == 8)
	2055	*dst++ = 'd';
	2056	}
	2057	else if (*src == '#')
	2058	*dst++ = (test->size == 8) ? 'd' : 's';
	2059	else
	2060	dst++ = src;
	2061	}
	2062	*dst = 0;
	2063	printf("Executing test %d/%d (%s)", tnum + 1, (int)ARRAY_LENGTH(bevalidate_test_list), mnemonic);
	2064
1929	2065	/* reset parameter list and iterate */
1930	2066	memset(param, 0, sizeof(param));
1931		printf("Executing test %d/%d", tnum + 1, (int)ARRAY_LENGTH(bevalidate_test_list));
1932	2067	bevalidate_iterate_over_params(drcuml, handles, test, param, 0);
1933	2068	printf("\n");
1934	2069	}
r2864	r2865
1946	2081	static void bevalidate_iterate_over_params(drcuml_state drcuml, drcuml_codehandle handles, const bevalidate_test test, drcuml_parameter *paramlist, int pnum)
1947	2082	{
1948	2083	const drcuml_opcode_info *opinfo = opcode_info_table[test->opcode];
	2084	drcuml_ptype ptype;
1949	2085
1950	2086	/* if no parameters, execute now */
1951		if (pnum >= ARRAY_LENGTH(opinfo->p~~types~~) \|\| opinfo->p~~types~~[pnum] == ~~OV_~~P~~ARAM_ALLOW~~ED_NONE)
	2087	if (pnum >= ARRAY_LENGTH(opinfo->param) \|\| opinfo->param[pnum].typemask == PTYPES_NONE)
1952	2088	{
1953	2089	bevalidate_iterate_over_flags(drcuml, handles, test, paramlist);
1954	2090	return;
1955	2091	}
1956	2092
1957	2093	/* iterate over valid parameter types */
1958		for (paramlist[pnum].type = DRCUML_PTYPE_IMMEDIATE; paramlist[pnum].type < DRCUML_PTYPE_MAX; paramlist[pnum].type++)
1959		if (opinfo->ptypes[pnum] & (1 << paramlist[pnum].type))
	2094	for (ptype = DRCUML_PTYPE_IMMEDIATE; ptype < DRCUML_PTYPE_MAX; ptype++)
	2095	if (opinfo->param[pnum].typemask & (1 << ptype))
1960	2096	{
1961	2097	int pindex, pcount;
1962	2098
1963	2099	/* mapvars can only do 32-bit tests */
1964		if (p~~aramlis~~t~~[pnum].t~~ype == DRCUML_PTYPE_MAPVAR && size_for_p~~ara~~m(test->size, ~~opinfo->p~~types[pnum]) == 8)
	2100	if (ptype == DRCUML_PTYPE_MAPVAR && effective_test_psize(opinfo, pnum, test->size, test->param) == 8)
1965	2101	continue;
1966	2102
1967	2103	/* for some parameter types, we wish to iterate over all possibilities */
1968		switch (p~~aramlist[pnum].~~type)
	2104	switch (ptype)
1969	2105	{
1970	2106	case DRCUML_PTYPE_INT_REGISTER: pcount = DRCUML_REG_I_END - DRCUML_REG_I0; break;
1971	2107	case DRCUML_PTYPE_FLOAT_REGISTER: pcount = DRCUML_REG_F_END - DRCUML_REG_F0; break;
1972		case DRCUML_PTYPE_MAPVAR: pcount = DRCUML_MAPVAR_END - DRCUML_MAPVAR_M0; break;
1973	2108	default: pcount = 1; break;
1974	2109	}
1975	2110
r2864	r2865
1984	2119	printf(".");
1985	2120
1986	2121	/* can't duplicate multiple source parameters unless they are immediates */
1987		if (p~~aramlis~~t~~[pnum].t~~ype != DRCUML_PTYPE_IMMEDIATE && (~~(test~~->~~destm~~a~~sk >>~~ pnum) & 1) ~~== 0~~)
	2122	if (ptype != DRCUML_PTYPE_IMMEDIATE && (opinfo->param[pnum].output & PIO_IN))
1988	2123
1989	2124	/* loop over all parameters we've done before; if the parameter is a source and matches us, skip this case */
1990	2125	for (pscannum = 0; pscannum < pnum; pscannum++)
1991		if ((~~(test~~->~~destm~~a~~sk >>~~ pscannum) & 1) ~~== 0~~ && p~~aramlist[pnum].~~type == paramlist[pscannum].type && pindex == paramlist[pscannum].value)
	2126	if ((opinfo->param[pscannum].output & PIO_IN) && ptype == paramlist[pscannum].type && pindex == paramlist[pscannum].value)
1992	2127	skip = TRUE;
1993	2128
	2129	/* can't duplicate multiple dest parameters */
	2130	if (opinfo->param[pnum].output & PIO_OUT)
	2131
	2132	/* loop over all parameters we've done before; if the parameter is a source and matches us, skip this case */
	2133	for (pscannum = 0; pscannum < pnum; pscannum++)
	2134	if ((opinfo->param[pscannum].output & PIO_OUT) && ptype == paramlist[pscannum].type && pindex == paramlist[pscannum].value)
	2135	skip = TRUE;
	2136
1994	2137	/* iterate over the next parameter in line */
1995	2138	if (!skip)
1996	2139	{
	2140	paramlist[pnum].type = ptype;
1997	2141	paramlist[pnum].value = pindex;
1998	2142	bevalidate_iterate_over_params(drcuml, handles, test, paramlist, pnum + 1);
1999	2143	}
r2864	r2865
2010	2154	static void bevalidate_iterate_over_flags(drcuml_state drcuml, drcuml_codehandle handles, const bevalidate_test test, drcuml_parameter *paramlist)
2011	2155	{
2012	2156	const drcuml_opcode_info *opinfo = opcode_info_table[test->opcode];
2013		UINT8 flagmask = opinfo->flags ~~& 0x1f~~;
	2157	UINT8 flagmask = opinfo->outflags;
2014	2158	UINT8 curmask;
2015	2159
2016	2160	/* iterate over all possible flag combinations */
r2864	r2865
2036	2180	int numparams;
2037	2181
2038	2182	/* allocate memory for parameters */
2039		parammem = drccache_memory_alloc_near(drcuml->cache, sizeof(UINT64) * ARRAY_LENGTH(test->param));
	2183	parammem = drccache_memory_alloc_near(drcuml->cache, sizeof(UINT64) * (ARRAY_LENGTH(test->param) + 1));
2040	2184
2041	2185	/* flush the cache */
2042	2186	drcuml_reset(drcuml);
r2864	r2865
2057	2201	switch (numparams)
2058	2202	{
2059	2203	case 0:
2060		drcuml_block_append_0(block, test->opcode, test->size, DRCUML_COND_ALWAYS~~, flagmask~~);
	2204	drcuml_block_append_0(block, test->opcode, test->size, DRCUML_COND_ALWAYS);
2061	2205	break;
2062	2206
2063	2207	case 1:
2064		drcuml_block_append_1(block, test->opcode, test->size, DRCUML_COND_ALWAYS, ~~flagmask,~~ params[0].type, params[0].value);
	2208	drcuml_block_append_1(block, test->opcode, test->size, DRCUML_COND_ALWAYS, params[0].type, params[0].value);
2065	2209	break;
2066	2210
2067	2211	case 2:
2068		drcuml_block_append_2(block, test->opcode, test->size, DRCUML_COND_ALWAYS, ~~flagmask,~~ params[0].type, params[0].value, params[1].type, params[1].value);
	2212	drcuml_block_append_2(block, test->opcode, test->size, DRCUML_COND_ALWAYS, params[0].type, params[0].value, params[1].type, params[1].value);
2069	2213	break;
2070	2214
2071	2215	case 3:
2072		drcuml_block_append_3(block, test->opcode, test->size, DRCUML_COND_ALWAYS, ~~flagmask,~~ params[0].type, params[0].value, params[1].type, params[1].value, params[2].type, params[2].value);
	2216	drcuml_block_append_3(block, test->opcode, test->size, DRCUML_COND_ALWAYS, params[0].type, params[0].value, params[1].type, params[1].value, params[2].type, params[2].value);
2073	2217	break;
2074	2218
2075	2219	case 4:
2076		drcuml_block_append_4(block, test->opcode, test->size, DRCUML_COND_ALWAYS, ~~flagmask,~~ params[0].type, params[0].value, params[1].type, params[1].value, params[2].type, params[2].value, params[3].type, params[3].value);
	2220	drcuml_block_append_4(block, test->opcode, test->size, DRCUML_COND_ALWAYS, params[0].type, params[0].value, params[1].type, params[1].value, params[2].type, params[2].value, params[3].type, params[3].value);
2077	2221	break;
2078	2222	}
2079	2223	testinst = block->inst[block->nextinst - 1];
2080	2224	UML_HANDLE(block, handles[2]);
	2225	UML_GETFLGS(block, MEM(&parammem[ARRAY_LENGTH(test->param)]), flagmask);
2081	2226	UML_SAVE(block, &fstate);
2082	2227	UML_EXIT(block, IMM(0));
2083	2228
r2864	r2865
2088	2233	drcuml_execute(drcuml, handles[0]);
2089	2234
2090	2235	/* verify the results */
2091		bevalidate_verify_state(drcuml, &istate, &fstate, test, params, &testinst, handles[1]->code, handles[2]->code, flagmask);
	2236	bevalidate_verify_state(drcuml, &istate, &fstate, test, (UINT32 )&parammem[ARRAY_LENGTH(test->param)], params, &testinst, handles[1]->code, handles[2]->code, flagmask);
2092	2237
2093	2238	/* free memory */
2094		drccache_memory_free(drcuml->cache, parammem, sizeof(UINT64) * ARRAY_LENGTH(test->param));
	2239	drccache_memory_free(drcuml->cache, parammem, sizeof(UINT64) * (ARRAY_LENGTH(test->param) + 1));
2095	2240	}
2096	2241
2097	2242
r2864	r2865
2147	2292	/* iterate over parameters */
2148	2293	for (pnum = 0; pnum < ARRAY_LENGTH(test->param); pnum++)
2149	2294	{
2150		int psize = size_for_p~~ara~~m(test->size, ~~opinfo->p~~types[pnum]);
	2295	int psize = effective_test_psize(opinfo, pnum, test->size, test->param);
2151	2296	drcuml_parameter *curparam = &params[pnum];
2152	2297
2153	2298	/* start with a copy of the parameter from the list */
r2864	r2865
2206	2351	discrepancies
2207	2352	-------------------------------------------------*/
2208	2353
2209		static int bevalidate_verify_state(drcuml_state drcuml, const drcuml_machine_state istate, drcuml_machine_state state, const bevalidate_test test, const drcuml_parameter params, const drcuml_instruction testinst, drccodeptr codestart, drccodeptr codeend, UINT8 flagmask)
	2354	static int bevalidate_verify_state(drcuml_state drcuml, const drcuml_machine_state istate, drcuml_machine_state state, const bevalidate_test test, UINT32 flags, const drcuml_parameter params, const drcuml_instruction testinst, drccodeptr codestart, drccodeptr codeend, UINT8 flagmask)
2210	2355	{
2211	2356	const drcuml_opcode_info *opinfo = opcode_info_table[test->opcode];
2212	2357	UINT8 ireg[DRCUML_REG_I_END - DRCUML_REG_I0] = { 0 };
r2864	r2865
2218	2363	*errend = 0;
2219	2364
2220	2365	/* check flags */
2221		if (~~(state->~~flags ~~& flagmask)~~ != (test->flags & flagmask))
	2366	if (flags != (test->flags & flagmask))
2222	2367	{
2223	2368	errend += sprintf(errend, " Flags ... result:%c%c%c%c%c expected:%c%c%c%c%c\n",
2224		(flagmask & DRCUML_FLAG_U) ? ((state->flags & DRCUML_FLAG_U) ? 'U' : '.') : '-',
2225		(flagmask & DRCUML_FLAG_S) ? ((state->flags & DRCUML_FLAG_S) ? 'S' : '.') : '-',
2226		(flagmask & DRCUML_FLAG_Z) ? ((state->flags & DRCUML_FLAG_Z) ? 'Z' : '.') : '-',
2227		(flagmask & DRCUML_FLAG_V) ? ((state->flags & DRCUML_FLAG_V) ? 'V' : '.') : '-',
2228		(flagmask & DRCUML_FLAG_C) ? ((state->flags & DRCUML_FLAG_C) ? 'C' : '.') : '-',
	2369	(flagmask & DRCUML_FLAG_U) ? ((flags & DRCUML_FLAG_U) ? 'U' : '.') : '-',
	2370	(flagmask & DRCUML_FLAG_S) ? ((flags & DRCUML_FLAG_S) ? 'S' : '.') : '-',
	2371	(flagmask & DRCUML_FLAG_Z) ? ((flags & DRCUML_FLAG_Z) ? 'Z' : '.') : '-',
	2372	(flagmask & DRCUML_FLAG_V) ? ((flags & DRCUML_FLAG_V) ? 'V' : '.') : '-',
	2373	(flagmask & DRCUML_FLAG_C) ? ((flags & DRCUML_FLAG_C) ? 'C' : '.') : '-',
2229	2374	(flagmask & DRCUML_FLAG_U) ? ((test->flags & DRCUML_FLAG_U) ? 'U' : '.') : '-',
2230	2375	(flagmask & DRCUML_FLAG_S) ? ((test->flags & DRCUML_FLAG_S) ? 'S' : '.') : '-',
2231	2376	(flagmask & DRCUML_FLAG_Z) ? ((test->flags & DRCUML_FLAG_Z) ? 'Z' : '.') : '-',
r2864	r2865
2235	2380
2236	2381	/* check destination parameters */
2237	2382	for (pnum = 0; pnum < ARRAY_LENGTH(test->param); pnum++)
2238		if (~~test~~->~~destm~~a~~sk & (1 <<~~ pnum))
	2383	if (opinfo->param[pnum].output & PIO_OUT)
2239	2384	{
2240		UINT64 mask = mask_for_param(test->size, opinfo->ptypes[pnum]);
2241		int psize = size_for_param(test->size, opinfo->ptypes[pnum]);
	2385	int psize = effective_test_psize(opinfo, pnum, test->size, test->param);
	2386	UINT64 mask = U64(0xffffffffffffffff) >> (64 - 8 * psize);
2242	2387	UINT64 result = 0;
2243	2388
2244	2389	/* fetch the result from the parameters */
r2864	r2865
2269	2414	}
2270	2415
2271	2416	/* check against the mask */
2272		if ((result & mask) != (test->param[pnum] & mask))
	2417	if (test->param[pnum] != UNDEFINED_U64 && (result & mask) != (test->param[pnum] & mask))
2273	2418	{
2274	2419	if ((UINT32)mask == mask)
2275	2420	errend += sprintf(errend, " Parameter %d ... result:%08X expected:%08X\n", pnum,
r2864	r2865
2315	2460	}
2316	2461	return errend != errorbuf;
2317	2462	}
2318
2319		#endif

src/emu/cpu/drcbex64.c
r2864	r2865
3729	3729	/* validate instruction */
3730	3730	assert(inst->size == 4);
3731	3731	assert_no_condition(inst);
3732		assert_no_flags(inst);
3733	3732
3734	3733	/* normalize parameters */
3735	3734	param_normalize_1(drcbe, inst, &dstp, PTYPE_M);
r2864	r2865
4483	4482
4484	4483	/* normalize parameters */
4485	4484	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI, &sizep, PTYPE_I);
4486		assert(srcp.type != DRCUML_PTYPE_IMMEDIATE);
4487	4485
4488	4486	/* pick a target register for the general case */
4489	4487	dstreg = param_select_register(REG_EAX, &dstp, NULL);
r2864	r2865
4665	4663
4666	4664	/* normalize parameters */
4667	4665	param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
4668		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
4669	4666
4670	4667	/* pick a target register for the general case */
4671	4668	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
4792	4789
4793	4790	/* normalize parameters */
4794	4791	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
4795		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
4796	4792
4797	4793	/* pick a target register for the general case */
4798	4794	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
4825	4821	emit_sub_m64_p64(drcbe, &dst, MABS(drcbe, dstp.value), &src2p, inst); // sub [dstp],src2p
4826	4822
4827	4823	/* reg = reg - imm */
4828		else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && short_immediate(src2p.~~typ~~e) && inst->flags == 0)
	4824	else if (dstp.type == DRCUML_PTYPE_INT_REGISTER && src1p.type == DRCUML_PTYPE_INT_REGISTER && src2p.type == DRCUML_PTYPE_IMMEDIATE && short_immediate(src2p.value) && inst->flags == 0)
4829	4825	emit_lea_r64_m64(&dst, dstp.value, MBD(src1p.value, -src2p.value)); // lea dstp,[src1p-src2p]
4830	4826
4831	4827	/* general case */
r2864	r2865
4956	4952
4957	4953	static x86code op_mulu(drcbe_state drcbe, x86code dst, const drcuml_instruction inst)
4958	4954	{
	4955	UINT8 zsflags = inst->flags & (DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	4956	UINT8 vflag = inst->flags & DRCUML_FLAG_V;
4959	4957	drcuml_parameter dstp, edstp, src1p, src2p;
4960	4958	int compute_hi;
4961	4959
4962	4960	/* validate instruction */
4963	4961	assert(inst->size == 4 \|\| inst->size == 8);
4964	4962	assert_no_condition(inst);
4965		assert_flags(inst, /DRCUML_FLAG_V \|/ DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	4963	assert_flags(inst, DRCUML_FLAG_V \| DRCUML_FLAG_Z \| DRCUML_FLAG_S);
4966	4964
4967	4965	/* normalize parameters */
4968	4966	param_normalize_4_commutative(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
r2864	r2865
4989	4987	/* compute flags */
4990	4988	if (inst->flags != 0)
4991	4989	{
4992		if (~~compute_hi~~)
	4990	if (zsflags != 0)
4993	4991	{
4994		if (inst->flags == DRCUML_FLAG_Z)
4995		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
4996		else if (inst->flags == DRCUML_FLAG_S)
4997		emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
	4992	if (vflag)
	4993	emit_pushf(&dst); // pushf
	4994	if (compute_hi)
	4995	{
	4996	if (zsflags == DRCUML_FLAG_Z)
	4997	emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	4998	else if (zsflags == DRCUML_FLAG_S)
	4999	emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
	5000	else
	5001	{
	5002	emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
	5003	emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
	5004	emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
	5005	emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5006	}
	5007	}
4998	5008	else
	5009	emit_test_r32_r32(&dst, REG_EAX, REG_EAX); // test eax,eax
	5010
	5011	/* we rely on the fact that OF is cleared by all logical operations above */
	5012	if (vflag)
4999	5013	{
5000		emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
5001		emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
5002		emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
5003		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5014	emit_pushf(&dst); // pushf
	5015	emit_pop_r64(&dst, REG_RAX); // pop rax
	5016	emit_and_m64_imm(&dst, MBD(REG_RSP, 0), ~0x84); // and [rsp],~0x84
	5017	emit_or_m64_r64(&dst, MBD(REG_RSP, 0), REG_RAX); // or [rsp],rax
	5018	emit_popf(&dst); // popf
5004	5019	}
5005	5020	}
5006		else
5007		emit_test_r32_r32(&dst, REG_EAX, REG_EAX); // test eax,eax
5008	5021	}
5009	5022	}
5010	5023
r2864	r2865
5029	5042	/* compute flags */
5030	5043	if (inst->flags != 0)
5031	5044	{
5032		if (~~compute_hi~~)
	5045	if (zsflags != 0)
5033	5046	{
5034		if (inst->flags == DRCUML_FLAG_Z)
5035		emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax
5036		else if (inst->flags == DRCUML_FLAG_S)
5037		emit_test_r64_r64(&dst, REG_RDX, REG_RDX); // test rdx,rdx
	5047	if (vflag)
	5048	emit_pushf(&dst); // pushf
	5049	if (compute_hi)
	5050	{
	5051	if (zsflags == DRCUML_FLAG_Z)
	5052	emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax
	5053	else if (zsflags == DRCUML_FLAG_S)
	5054	emit_test_r64_r64(&dst, REG_RDX, REG_RDX); // test rdx,rdx
	5055	else
	5056	{
	5057	emit_mov_r32_r32(&dst, REG_ECX, REG_EAX); // mov ecx,eax
	5058	emit_shr_r64_imm(&dst, REG_RAX, 32); // shr rax,32
	5059	emit_or_r64_r64(&dst, REG_RDX, REG_RCX); // or rdx,rcx
	5060	emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax
	5061	}
	5062	}
5038	5063	else
	5064	emit_test_r64_r64(&dst, REG_RAX, REG_RAX); // test rax,rax
	5065
	5066	/* we rely on the fact that OF is cleared by all logical operations above */
	5067	if (vflag)
5039	5068	{
5040		emit_mov_r32_r32(&dst, REG_ECX, REG_EAX); // mov ecx,eax
5041		emit_shr_r64_imm(&dst, REG_RAX, 32); // shr rax,32
5042		emit_or_r64_r64(&dst, REG_RDX, REG_RCX); // or rdx,rcx
5043		emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax
	5069	emit_pushf(&dst); // pushf
	5070	emit_pop_r64(&dst, REG_RAX); // pop rax
	5071	emit_and_m64_imm(&dst, MBD(REG_RSP, 0), ~0x84); // and [rsp],~0x84
	5072	emit_or_m64_r64(&dst, MBD(REG_RSP, 0), REG_RAX); // or [rsp],rax
	5073	emit_popf(&dst); // popf
5044	5074	}
5045	5075	}
5046		else
5047		emit_test_r64_r64(&dst, REG_RAX, REG_RAX); // test rax,rax
5048	5076	}
5049	5077	}
5050	5078	return dst;
r2864	r2865
5057	5085
5058	5086	static x86code op_muls(drcbe_state drcbe, x86code dst, const drcuml_instruction inst)
5059	5087	{
	5088	UINT8 zsflags = inst->flags & (DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5089	UINT8 vflag = inst->flags & DRCUML_FLAG_V;
5060	5090	drcuml_parameter dstp, edstp, src1p, src2p;
5061	5091	int compute_hi;
5062	5092
5063	5093	/* validate instruction */
5064	5094	assert(inst->size == 4 \|\| inst->size == 8);
5065	5095	assert_no_condition(inst);
5066		assert_flags(inst, /DRCUML_FLAG_V \|/ DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5096	assert_flags(inst, DRCUML_FLAG_V \| DRCUML_FLAG_Z \| DRCUML_FLAG_S);
5067	5097
5068	5098	/* normalize parameters */
5069	5099	param_normalize_4_commutative(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
r2864	r2865
5113	5143	/* compute flags */
5114	5144	if (inst->flags != 0)
5115	5145	{
5116		if (~~compute_hi~~)
	5146	if (zsflags != 0)
5117	5147	{
5118		if (inst->flags == DRCUML_FLAG_Z)
5119		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5120		else if (inst->flags == DRCUML_FLAG_S)
5121		emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
	5148	if (vflag)
	5149	emit_pushf(&dst); // pushf
	5150	if (compute_hi)
	5151	{
	5152	if (zsflags == DRCUML_FLAG_Z)
	5153	emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5154	else if (zsflags == DRCUML_FLAG_S)
	5155	emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
	5156	else
	5157	{
	5158	emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
	5159	emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
	5160	emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
	5161	emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5162	}
	5163	}
5122	5164	else
	5165	emit_test_r32_r32(&dst, REG_EAX, REG_EAX); // test eax,eax
	5166
	5167	/* we rely on the fact that OF is cleared by all logical operations above */
	5168	if (vflag)
5123	5169	{
5124		emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
5125		emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
5126		emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
5127		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5170	emit_pushf(&dst); // pushf
	5171	emit_pop_r64(&dst, REG_RAX); // pop rax
	5172	emit_and_m64_imm(&dst, MBD(REG_RSP, 0), ~0x84); // and [rsp],~0x84
	5173	emit_or_m64_r64(&dst, MBD(REG_RSP, 0), REG_RAX); // or [rsp],rax
	5174	emit_popf(&dst); // popf
5128	5175	}
5129	5176	}
5130		else
5131		emit_test_r32_r32(&dst, REG_EAX, REG_EAX); // test eax,eax
5132	5177	}
5133	5178	}
5134	5179
r2864	r2865
5176	5221	/* compute flags */
5177	5222	if (inst->flags != 0)
5178	5223	{
5179		if (~~compute_hi~~)
	5224	if (zsflags != 0)
5180	5225	{
5181		if (inst->flags == DRCUML_FLAG_Z)
5182		emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax
5183		else if (inst->flags == DRCUML_FLAG_S)
5184		emit_test_r64_r64(&dst, REG_RDX, REG_RDX); // test rdx,rdx
	5226	if (vflag)
	5227	emit_pushf(&dst); // pushf
	5228	if (compute_hi)
	5229	{
	5230	if (zsflags == DRCUML_FLAG_Z)
	5231	emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax
	5232	else if (zsflags == DRCUML_FLAG_S)
	5233	emit_test_r64_r64(&dst, REG_RDX, REG_RDX); // test rdx,rdx
	5234	else
	5235	{
	5236	emit_mov_r32_r32(&dst, REG_ECX, REG_EAX); // mov ecx,eax
	5237	emit_shr_r64_imm(&dst, REG_RAX, 32); // shr rax,32
	5238	emit_or_r64_r64(&dst, REG_RDX, REG_RCX); // or rdx,rcx
	5239	emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax
	5240	}
	5241	}
5185	5242	else
	5243	emit_test_r64_r64(&dst, REG_RAX, REG_RAX); // test rax,rax
	5244
	5245	/* we rely on the fact that OF is cleared by all logical operations above */
	5246	if (vflag)
5186	5247	{
5187		emit_mov_r32_r32(&dst, REG_ECX, REG_EAX); // mov ecx,eax
5188		emit_shr_r64_imm(&dst, REG_RAX, 32); // shr rax,32
5189		emit_or_r64_r64(&dst, REG_RDX, REG_RCX); // or rdx,rcx
5190		emit_or_r64_r64(&dst, REG_RDX, REG_RAX); // or rdx,rax
	5248	emit_pushf(&dst); // pushf
	5249	emit_pop_r64(&dst, REG_RAX); // pop rax
	5250	emit_and_m64_imm(&dst, MBD(REG_RSP, 0), ~0x84); // and [rsp],~0x84
	5251	emit_or_m64_r64(&dst, MBD(REG_RSP, 0), REG_RAX); // or [rsp],rax
	5252	emit_popf(&dst); // popf
5191	5253	}
5192	5254	}
5193		else
5194		emit_test_r64_r64(&dst, REG_RAX, REG_RAX); // test rax,rax
5195	5255	}
5196	5256	}
5197	5257	return dst;
r2864	r2865
5211	5271	/* validate instruction */
5212	5272	assert(inst->size == 4 \|\| inst->size == 8);
5213	5273	assert_no_condition(inst);
5214		assert_flags(inst, /DRCUML_FLAG_V \|/ DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5274	assert_flags(inst, DRCUML_FLAG_V \| DRCUML_FLAG_Z \| DRCUML_FLAG_S);
5215	5275
5216	5276	/* normalize parameters */
5217	5277	param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
r2864	r2865
5222	5282	{
5223	5283	/* general case */
5224	5284	emit_mov_r32_p32(drcbe, &dst, REG_ECX, &src2p); // mov ecx,src2p
	5285	if (inst->flags != 0)
	5286	{
	5287	emit_mov_r32_imm(&dst, REG_EAX, 0xa0000000); // mov eax,0xa0000000
	5288	emit_add_r32_r32(&dst, REG_EAX, REG_EAX); // add eax,eax
	5289	}
5225	5290	emit_jecxz_link(&dst, &skip); // jecxz skip
5226	5291	emit_mov_r32_p32(drcbe, &dst, REG_EAX, &src1p); // mov eax,src1p
5227	5292	emit_xor_r32_r32(&dst, REG_EDX, REG_EDX); // xor edx,edx
r2864	r2865
5239	5304	{
5240	5305	/* general case */
5241	5306	emit_mov_r64_p64(drcbe, &dst, REG_RCX, &src2p); // mov rcx,src2p
	5307	if (inst->flags != 0)
	5308	{
	5309	emit_mov_r32_imm(&dst, REG_EAX, 0xa0000000); // mov eax,0xa0000000
	5310	emit_add_r32_r32(&dst, REG_EAX, REG_EAX); // add eax,eax
	5311	}
5242	5312	emit_jrcxz_link(&dst, &skip); // jrcxz skip
5243	5313	emit_mov_r64_p64(drcbe, &dst, REG_RAX, &src1p); // mov rax,src1p
5244	5314	emit_xor_r32_r32(&dst, REG_EDX, REG_EDX); // xor edx,edx
r2864	r2865
5267	5337	/* validate instruction */
5268	5338	assert(inst->size == 4 \|\| inst->size == 8);
5269	5339	assert_no_condition(inst);
5270		assert_flags(inst, /DRCUML_FLAG_V \|/ DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5340	assert_flags(inst, DRCUML_FLAG_V \| DRCUML_FLAG_Z \| DRCUML_FLAG_S);
5271	5341
5272	5342	/* normalize parameters */
5273	5343	param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
r2864	r2865
5278	5348	{
5279	5349	/* general case */
5280	5350	emit_mov_r32_p32(drcbe, &dst, REG_ECX, &src2p); // mov ecx,src2p
	5351	if (inst->flags != 0)
	5352	{
	5353	emit_mov_r32_imm(&dst, REG_EAX, 0xa0000000); // mov eax,0xa0000000
	5354	emit_add_r32_r32(&dst, REG_EAX, REG_EAX); // add eax,eax
	5355	}
5281	5356	emit_jecxz_link(&dst, &skip); // jecxz skip
5282	5357	emit_mov_r32_p32(drcbe, &dst, REG_EAX, &src1p); // mov eax,src1p
5283	5358	emit_cdq(&dst); // cdq
r2864	r2865
5295	5370	{
5296	5371	/* general case */
5297	5372	emit_mov_r64_p64(drcbe, &dst, REG_RCX, &src2p); // mov rcx,src2p
	5373	if (inst->flags != 0)
	5374	{
	5375	emit_mov_r32_imm(&dst, REG_EAX, 0xa0000000); // mov eax,0xa0000000
	5376	emit_add_r32_r32(&dst, REG_EAX, REG_EAX); // add eax,eax
	5377	}
5298	5378	emit_jrcxz_link(&dst, &skip); // jrcxz skip
5299	5379	emit_mov_r64_p64(drcbe, &dst, REG_RAX, &src1p); // mov rax,src1p
5300	5380	emit_cqo(&dst); // cqo
r2864	r2865
5326	5406
5327	5407	/* normalize parameters */
5328	5408	param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5329		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5330	5409
5331	5410	/* pick a target register for the general case */
5332	5411	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5435	5514
5436	5515	/* normalize parameters */
5437	5516	param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5438		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5439	5517
5440	5518	/* pick a target register for the general case */
5441	5519	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5491	5569
5492	5570	/* normalize parameters */
5493	5571	param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5494		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5495	5572
5496	5573	/* pick a target register for the general case */
5497	5574	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5547	5624
5548	5625	/* normalize parameters */
5549	5626	param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI);
5550		assert(srcp.type != DRCUML_PTYPE_IMMEDIATE);
5551	5627
5552	5628	/* pick a target register for the general case */
5553	5629	dstreg = param_select_register(REG_EAX, &dstp, NULL);
r2864	r2865
5591	5667
5592	5668	/* normalize parameters */
5593	5669	param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI);
5594		assert(srcp.type != DRCUML_PTYPE_IMMEDIATE);
5595	5670
5596	5671	/* pick a target register for the general case */
5597	5672	dstreg = param_select_register(REG_RAX, &dstp, NULL);
r2864	r2865
5631	5706
5632	5707	/* normalize parameters */
5633	5708	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5634		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5635	5709
5636	5710	/* pick a target register for the general case */
5637	5711	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5687	5761
5688	5762	/* normalize parameters */
5689	5763	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5690		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5691	5764
5692	5765	/* pick a target register for the general case */
5693	5766	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5743	5816
5744	5817	/* normalize parameters */
5745	5818	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5746		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5747	5819
5748	5820	/* pick a target register for the general case */
5749	5821	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5799	5871
5800	5872	/* normalize parameters */
5801	5873	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5802		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5803	5874
5804	5875	/* pick a target register for the general case */
5805	5876	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5855	5926
5856	5927	/* normalize parameters */
5857	5928	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5858		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5859	5929
5860	5930	/* pick a target register for the general case */
5861	5931	dstreg = param_select_register(REG_EAX, &dstp, &src2p);

src/emu/cpu/drcbec.c
r2864	r2865
710	710	break;
711	711
712	712	case MAKE_OPCODE_SHORT(DRCUML_OP_RESTORE, 4, 0): /* RESTORE dst */
	713	case MAKE_OPCODE_SHORT(DRCUML_OP_RESTORE, 4, 1): /* RESTORE dst */
713	714	drcbe->state = *inst[0].state;
714	715	flags = inst[0].state->flags;
715	716	break;
r2864	r2865
916	917	flags = FLAGS64_NZ(temp64);
917	918	PARAM1 = temp64 >> 32;
918	919	PARAM0 = (UINT32)temp64;
	920	if (temp64 != (UINT32)temp64)
	921	flags \|= DRCUML_FLAG_V;
919	922	break;
920	923
921	924	case MAKE_OPCODE_SHORT(DRCUML_OP_MULS, 4, 0): /* MULS dst,edst,src1,src2[,f] */
r2864	r2865
929	932	flags = FLAGS64_NZ(temp64);
930	933	PARAM1 = temp64 >> 32;
931	934	PARAM0 = (UINT32)temp64;
	935	if (temp64 != (INT32)temp64)
	936	flags \|= DRCUML_FLAG_V;
932	937	break;
933	938
934	939	case MAKE_OPCODE_SHORT(DRCUML_OP_DIVU, 4, 0): /* DIVU dst,edst,src1,src2[,f] */
r2864	r2865
948	953	flags = FLAGS32_NZ(temp32);
949	954	PARAM0 = temp32;
950	955	}
	956	else
	957	flags = DRCUML_FLAG_V;
951	958	break;
952	959
953	960	case MAKE_OPCODE_SHORT(DRCUML_OP_DIVS, 4, 0): /* DIVS dst,edst,src1,src2[,f] */
r2864	r2865
967	974	flags = FLAGS32_NZ(temp32);
968	975	PARAM0 = temp32;
969	976	}
	977	else
	978	flags = DRCUML_FLAG_V;
970	979	break;
971	980
972	981	case MAKE_OPCODE_SHORT(DRCUML_OP_AND, 4, 0): /* AND dst,src1,src2[,f] */
r2864	r2865
1387	1396	flags = FLAGS64_NZ(temp64);
1388	1397	DPARAM0 = temp64;
1389	1398	}
	1399	else
	1400	flags = DRCUML_FLAG_V;
1390	1401	break;
1391	1402
1392	1403	case MAKE_OPCODE_SHORT(DRCUML_OP_DIVS, 8, 0): /* DDIVS dst,edst,src1,src2[,f] */
r2864	r2865
1406	1417	flags = FLAGS64_NZ(temp64);
1407	1418	DPARAM0 = temp64;
1408	1419	}
	1420	else
	1421	flags = DRCUML_FLAG_V;
1409	1422	break;
1410	1423
1411	1424	case MAKE_OPCODE_SHORT(DRCUML_OP_AND, 8, 0): /* DAND dst,src1,src2[,f] */
r2864	r2865
1952	1965	UINT64 a, b, temp;
1953	1966
1954	1967	/* shortcut if we don't care about the high bits or the flags */
1955		if (dstlo == dsthi && !flags)
	1968	if (dstlo == dsthi && flags == 0)
1956	1969	{
1957	1970	dstlo = src1 src2;
1958	1971	return 0;
r2864	r2865
1985	1998	/* store the results */
1986	1999	*dsthi = hi;
1987	2000	*dstlo = lo;
1988		return ((hi >> 60) & DRCUML_FLAG_S);
	2001	return ((hi >> 60) & DRCUML_FLAG_S) \| ((*dsthi != 0) << 1);
1989	2002	}
1990	2003
1991	2004
r2864	r2865
1999	2012	UINT64 a, b, temp;
2000	2013
2001	2014	/* shortcut if we don't care about the high bits or the flags */
2002		if (dstlo == dsthi && !flags)
	2015	if (dstlo == dsthi && flags == 0)
2003	2016	{
2004	2017	dstlo = src1 src2;
2005	2018	return 0;
r2864	r2865
2039	2052	/* store the results */
2040	2053	*dsthi = hi;
2041	2054	*dstlo = lo;
2042		return ((hi >> 60) & DRCUML_FLAG_S);
	2055	return ((hi >> 60) & DRCUML_FLAG_S) \| ((*dsthi != ((INT64)lo >> 63)) << 1);
2043	2056	}

src/emu/cpu/cop400/cop420ds.c
r2864	r2865
269	269	break;
270	270
271	271	case 0x2C:
272		sprintf(buffer, "COMA");
	272	sprintf(buffer, "CQMA");
273	273	break;
274	274
275	275	case 0x2E:

src/emu/cpu/powerpc/ppcdrc.c
r2864	r2865
199	199	drcuml_codehandle * out_of_cycles; /* out of cycles exception handler */
200	200	drcuml_codehandle * tlb_mismatch; /* tlb mismatch handler */
201	201	drcuml_codehandle * swap_tgpr; /* swap TGPR handler */
202		drcuml_codehandle * lsw[4][32]; /* lsw entries */
203		drcuml_codehandle * stsw[4][32]; /* stsw entries */
204		drcuml_codehandle * read8[4]; /* read byte */
205		drcuml_codehandle * write8[4]; /* write byte */
206		drcuml_codehandle * read16[4]; /* read half */
207		drcuml_codehandle * read16mask[4]; /* read half */
208		drcuml_codehandle * write16[4]; /* write half */
209		drcuml_codehandle * write16mask[4]; /* write half */
210		drcuml_codehandle * read32[4]; /* read word */
211		drcuml_codehandle * read32align[4]; /* read word aligned */
212		drcuml_codehandle * read32mask[4]; /* read word */
213		drcuml_codehandle * write32[4]; /* write word */
214		drcuml_codehandle * write32align[4]; /* write word aligned */
215		drcuml_codehandle * write32mask[4]; /* write word */
216		drcuml_codehandle * read64[4]; /* read double */
217		drcuml_codehandle * read64mask[4]; /* read double */
218		drcuml_codehandle * write64[4]; /* write double */
219		drcuml_codehandle * write64mask[4]; /* write double */
	202	drcuml_codehandle * lsw[8][32]; /* lsw entries */
	203	drcuml_codehandle * stsw[8][32]; /* stsw entries */
	204	drcuml_codehandle * read8[8]; /* read byte */
	205	drcuml_codehandle * write8[8]; /* write byte */
	206	drcuml_codehandle * read16[8]; /* read half */
	207	drcuml_codehandle * read16mask[8]; /* read half */
	208	drcuml_codehandle * write16[8]; /* write half */
	209	drcuml_codehandle * write16mask[8]; /* write half */
	210	drcuml_codehandle * read32[8]; /* read word */
	211	drcuml_codehandle * read32align[8]; /* read word aligned */
	212	drcuml_codehandle * read32mask[8]; /* read word */
	213	drcuml_codehandle * write32[8]; /* write word */
	214	drcuml_codehandle * write32align[8]; /* write word aligned */
	215	drcuml_codehandle * write32mask[8]; /* write word */
	216	drcuml_codehandle * read64[8]; /* read double */
	217	drcuml_codehandle * read64mask[8]; /* read double */
	218	drcuml_codehandle * write64[8]; /* write double */
	219	drcuml_codehandle * write64mask[8]; /* write double */
220	220	drcuml_codehandle * exception[EXCEPTION_COUNT]; /* array of exception handlers */
221	221	drcuml_codehandle * exception_norecover[EXCEPTION_COUNT]; /* array of exception handlers */
222	222
r2864	r2865
545	545	};
546	546	drcbe_info beinfo;
547	547	UINT32 flags = 0;
548		size_t extrasize;
549	548	drccache *cache;
550		void *extramem;
551	549	int regnum;
552	550
553		/* determine how much memory beyond the core size we need */
554		extrasize = ppccom_init(NULL, flavor, cap, tb_divisor, clock, config, irqcallback, NULL);
555
556	551	/* allocate enough space for the cache and the core */
557		cache = drccache_alloc(CACHE_SIZE + sizeof(*ppc) ~~+ extrasize~~);
	552	cache = drccache_alloc(CACHE_SIZE + sizeof(*ppc));
558	553	if (cache == NULL)
559		fatalerror("Unable to allocate cache of size %d", (UINT32)(CACHE_SIZE + sizeof(*ppc) ~~+ extrasize~~));
	554	fatalerror("Unable to allocate cache of size %d", (UINT32)(CACHE_SIZE + sizeof(*ppc)));
560	555
561		/* allocate the core from the near cache~~, and the extra memory from the full cache~~ */
	556	/* allocate the core from the near cache */
562	557	ppc = drccache_memory_alloc_near(cache, sizeof(*ppc));
563	558	memset(ppc, 0, sizeof(*ppc));
564		extramem = drccache_memory_alloc(cache, extrasize);
565		memset(extramem, 0, extrasize);
566	559
567	560	/* initialize the core */
568		ppccom_init(ppc, flavor, cap, tb_divisor, clock, config, irqcallback~~, extramem~~);
	561	ppccom_init(ppc, flavor, cap, tb_divisor, clock, config, irqcallback);
569	562
570	563	/* allocate the implementation-specific state from the full cache */
571	564	ppc->impstate = drccache_memory_alloc_near(cache, sizeof(*ppc->impstate));
r2864	r2865
729	722
730	723	static void ppcdrc_exit(void)
731	724	{
	725	ppccom_exit(ppc);
	726
732	727	/* clean up the DRC */
733	728	drcfe_exit(ppc->impstate->drcfe);
734	729	drcuml_free(ppc->impstate->drcuml);
r2864	r2865
897	892	}
898	893
899	894	/* add subroutines for memory accesses */
900		for (mode = 0; mode < 4; mode++)
	895	for (mode = 0; mode < 8; mode++)
901	896	{
902	897	static_generate_memory_accessor(drcuml, mode, 1, FALSE, FALSE, "read8", &ppc->impstate->read8[mode], NULL);
903	898	static_generate_memory_accessor(drcuml, mode, 1, TRUE, FALSE, "write8", &ppc->impstate->write8[mode], NULL);
r2864	r2865
1232	1227	UML_MOV(block, MEM(&ppc->param0), IREG(0)); // mov [param0],i0
1233	1228	UML_MOV(block, MEM(&ppc->param1), IMM(TRANSLATE_FETCH)); // mov [param1],TRANSLATE_FETCH
1234	1229	UML_CALLC(block, ppccom_tlb_fill, ppc); // callc tlbfill,ppc
1235		UML_CMP(block, MEM(&ppc->param0), IMM(1)); // cmp [param0],1
1236		UML_JMPc(block, IF_A, isi = label++); // jmp isi,A
	1230	UML_SHR(block, IREG(1), IREG(0), IMM(12)); // shr i1,i0,11
	1231	UML_LOAD(block, IREG(1), (void *)vtlb_table(ppc->vtlb), IREG(1), DWORD); // load i1,[vtlb],i1,dword
	1232	UML_TEST(block, IREG(1), IMM(VTLB_FETCH_ALLOWED)); // test i1,VTLB_FETCH_ALLOWED
	1233	UML_JMPc(block, IF_Z, isi = label++); // jmp isi,z
1237	1234	UML_MOV(block, MEM(&ppc->pc), IREG(0)); // mov <pc>,i0
1238	1235	save_fast_iregs(block); // <save fastregs>
1239	1236	UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE
r2864	r2865
1447	1444	int fastxor = BYTE8_XOR_BE(0) >> (activecpu_databus_width(ADDRESS_SPACE_PROGRAM) < 64);
1448	1445	drcuml_block *block;
1449	1446	jmp_buf errorbuf;
	1447	int translate_type;
1450	1448	int tlbreturn = 0;
1451	1449	int unaligned = 0;
1452	1450	int alignex = 0;
r2864	r2865
1454	1452	int label = 1;
1455	1453	int ramnum;
1456	1454
	1455	if (mode & MODE_USER)
	1456	translate_type = iswrite ? TRANSLATE_WRITE_USER : TRANSLATE_READ_USER;
	1457	else
	1458	translate_type = iswrite ? TRANSLATE_WRITE : TRANSLATE_READ;
	1459
1457	1460	/* if we get an error back, we're screwed */
1458	1461	if (setjmp(errorbuf) != 0)
1459	1462	fatalerror("Unrecoverable error in static_generate_exception");
r2864	r2865
1498	1501	if (((ppc->cap & PPCCAP_OEA) && (mode & MODE_DATA_TRANSLATION)) \|\| (iswrite && (ppc->cap & PPCCAP_4XX) && (mode & MODE_PROTECTION)))
1499	1502	{
1500	1503	UML_SHR(block, IREG(3), IREG(0), IMM(12)); // shr i3,i0,12
1501		UML_LOAD(block, IREG(3), ppc->tlb_table, IREG(3), DWORD); // load i3,[tlb_table],i3,dword
1502		UML_TEST(block, IREG(3), IMM(iswrite ? TLB_WRITE : TLB_READ)); // test i3,iswrite ? TLB_WRITE : TLB_READ
	1504	UML_LOAD(block, IREG(3), (void *)vtlb_table(ppc->vtlb), IREG(3), DWORD); // load i3,[vtlb],i3,dword
	1505	UML_TEST(block, IREG(3), IMM((UINT64)1 << translate_type)); // test i3,1 << translate_type
1503	1506	UML_JMPc(block, IF_Z, tlbmiss = label++); // jmp tlbmiss,z
1504	1507	UML_LABEL(block, tlbreturn = label++); // tlbreturn:
1505	1508	UML_ROLINS(block, IREG(0), IREG(3), IMM(0), IMM(0xfffff000)); // rolins i0,i3,0,0xfffff000
r2864	r2865
1786	1789	/* handle a TLB miss */
1787	1790	if (tlbmiss != 0)
1788	1791	{
1789		int dsi;
1790
1791	1792	UML_LABEL(block, tlbmiss); // tlbmiss:
1792	1793	UML_MOV(block, MEM(&ppc->param0), IREG(0)); // mov [param0],i0
1793		UML_MOV(block, MEM(&ppc->param1), IMM(~~isw~~rite ~~? TRANSLATE~~_~~WRITE : TRANSLATE_READ~~)); // mov [param1],~~TRANSLATE~~_~~READ/WRITE~~
	1794	UML_MOV(block, MEM(&ppc->param1), IMM(translate_type)); // mov [param1],translate_type
1794	1795	UML_CALLC(block, ppccom_tlb_fill, ppc); // callc tlbfill,ppc
1795		UML_CMP(block, MEM(&ppc->param0), IMM(1)); // cmp [param0],1
1796		UML_JMPc(block, IF_A, dsi = label++); // jmp dsi,A
1797	1796	UML_SHR(block, IREG(3), IREG(0), IMM(12)); // shr i3,i0,12
1798		UML_LOAD(block, IREG(3), ppc->tlb_table, IREG(3), DWORD); // load i3,[tlb_table],i3,dword
1799		UML_JMP(block, tlbreturn); // jmp tlbreturn
1800		UML_LABEL(block, dsi); // dsi:
	1797	UML_LOAD(block, IREG(3), (void *)vtlb_table(ppc->vtlb), IREG(3), DWORD); // load i3,[vtlb],i3,dword
	1798	UML_TEST(block, IREG(3), IMM((UINT64)1 << translate_type)); // test i3,1 << translate_type
	1799	UML_JMPc(block, IF_NZ, tlbreturn); // jmp tlbreturn,nz
1801	1800
1802	1801	/* 4XX case: protection exception */
1803	1802	if (ppc->cap & PPCCAP_4XX)
r2864	r2865
2166	2165	/* validate our TLB entry at this PC; if we fail, we need to handle it */
2167	2166	if ((desc->flags & OPFLAG_VALIDATE_TLB) && (ppc->impstate->mode & MODE_DATA_TRANSLATION))
2168	2167	{
	2168	const vtlb_entry *tlbtable = vtlb_table(ppc->vtlb);
	2169
2169	2170	/* if we currently have a valid TLB read entry, we just verify */
2170		if (~~ppc->~~tlb_table[desc->pc >> 12] != 0)
	2171	if (tlbtable[desc->pc >> 12] != 0)
2171	2172	{
2172	2173	if (PRINTF_MMU)
2173	2174	{
2174	2175	UML_MOV(block, MEM(&ppc->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc
2175	2176	UML_CALLC(block, cfunc_printf_debug, "Checking TLB at @ %08X\n"); // callc printf_debug
2176	2177	}
2177		UML_LOAD(block, IREG(0), &ppc->tlb_table[desc->pc >> 12], IMM(0), DWORD); // load i0,tlb_table[desc->pc >> 12],dword
2178		UML_CMP(block, IREG(0), IMM(ppc->tlb_table[desc->pc >> 12])); // cmp i0,*tlbentry
	2178	UML_LOAD(block, IREG(0), &tlbtable[desc->pc >> 12], IMM(0), DWORD); // load i0,tlbtable[desc->pc >> 12],dword
	2179	UML_CMP(block, IREG(0), IMM(tlbtable[desc->pc >> 12])); // cmp i0,*tlbentry
2179	2180	UML_EXHc(block, IF_NE, ppc->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0,NE
2180	2181	}
2181	2182
r2864	r2865
2184	2185	{
2185	2186	if (PRINTF_MMU)
2186	2187	{
2187		UML_MOV(block, MEM(&ppc->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc
	2188	UML_MOV(block, MEM(&ppc->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc
2188	2189	UML_CALLC(block, cfunc_printf_debug, "No valid TLB @ %08X\n"); // callc printf_debug
2189	2190	}
2190		UML_EXH(block, ppc->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0
	2191	UML_EXH(block, ppc->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0
2191	2192	}
2192	2193	}
2193	2194
2194	2195	/* if this is an invalid opcode, generate the exception now */
2195	2196	if (desc->flags & OPFLAG_INVALID_OPCODE)
2196		UML_EXH(block, ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x80000)); // exh exception_program,0x80000
	2197	UML_EXH(block, ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x80000)); // exh exception_program,0x80000
2197	2198
2198	2199	/* if this is a privileged opcode in user mode, generate the exception */
2199	2200	else if ((desc->flags & OPFLAG_PRIVILEGED) && (ppc->impstate->mode & MODE_USER))
2200		UML_EXH(block, ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x40000)); // exh exception_program,0x40000
	2201	UML_EXH(block, ppc->impstate->exception[EXCEPTION_PROGRAM], IMM(0x40000)); // exh exception_program,0x40000
2201	2202
2202	2203	/* otherwise, unless this is a virtual no-op, it's a regular instruction */
2203	2204	else if (!(desc->flags & OPFLAG_VIRTUAL_NOOP))
r2864	r2865
2205	2206	/* compile the instruction */
2206	2207	if (!generate_opcode(block, compiler, desc))
2207	2208	{
2208		UML_MOV(block, MEM(&ppc->pc), IMM(desc->pc)); // mov [pc],desc->pc
	2209	UML_MOV(block, MEM(&ppc->pc), IMM(desc->pc)); // mov [pc],desc->pc
2209	2210	UML_CALLC(block, cfunc_unimplemented, (void )(FPTR)desc->opptr.l); // callc cfunc_unimplemented
2210	2211	}
2211	2212	}
r2864	r2865
2493	2494	case 0x22: /* LBZ */
2494	2495	UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2495	2496	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2496		UML_CALLH(block, ppc->impstate->read8[ppc->impstate->mode ~~& 3~~]); // callh read8
	2497	UML_CALLH(block, ppc->impstate->read8[ppc->impstate->mode]); // callh read8
2497	2498	UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xff)); // and rd,i0,0xff
2498	2499	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2499	2500	return TRUE;
r2864	r2865
2501	2502	case 0x28: /* LHZ */
2502	2503	UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2503	2504	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2504		UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode ~~& 3~~]); // callh read16
	2505	UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode]); // callh read16
2505	2506	UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xffff)); // and rd,i0,0xffff
2506	2507	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2507	2508	return TRUE;
r2864	r2865
2509	2510	case 0x2a: /* LHA */
2510	2511	UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2511	2512	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2512		UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode ~~& 3~~]); // callh read16
	2513	UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode]); // callh read16
2513	2514	UML_SEXT(block, R32(G_RD(op)), IREG(0), WORD); // sext rd,i0,word
2514	2515	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2515	2516	return TRUE;
r2864	r2865
2517	2518	case 0x20: /* LWZ */
2518	2519	UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2519	2520	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2520		UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode ~~& 3~~]); // callh read32
	2521	UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode]); // callh read32
2521	2522	UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0
2522	2523	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2523	2524	return TRUE;
r2864	r2865
2526	2527	UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2527	2528	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2528	2529	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2529		UML_CALLH(block, ppc->impstate->read8[ppc->impstate->mode ~~& 3~~]); // callh read8
	2530	UML_CALLH(block, ppc->impstate->read8[ppc->impstate->mode]); // callh read8
2530	2531	UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xff)); // and rd,i0,0xff
2531	2532	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
2532	2533	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
2536	2537	UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2537	2538	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2538	2539	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2539		UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode ~~& 3~~]); // callh read16
	2540	UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode]); // callh read16
2540	2541	UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xffff)); // and rd,i0,0xffff
2541	2542	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
2542	2543	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
2546	2547	UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2547	2548	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2548	2549	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2549		UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode ~~& 3~~]); // callh read16
	2550	UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode]); // callh read16
2550	2551	UML_SEXT(block, R32(G_RD(op)), IREG(0), WORD); // sext rd,i0,word
2551	2552	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
2552	2553	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
2556	2557	UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2557	2558	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2558	2559	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2559		UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode ~~& 3~~]); // callh read32
	2560	UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode]); // callh read32
2560	2561	UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0
2561	2562	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
2562	2563	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
2566	2567	UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2567	2568	UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xff)); // and i1,rs,0xff
2568	2569	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2569		UML_CALLH(block, ppc->impstate->write8[ppc->impstate->mode ~~& 3~~]); // callh write8
	2570	UML_CALLH(block, ppc->impstate->write8[ppc->impstate->mode]); // callh write8
2570	2571	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2571	2572	return TRUE;
2572	2573
r2864	r2865
2574	2575	UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2575	2576	UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xffff)); // and i1,rs,0xffff
2576	2577	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2577		UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode ~~& 3~~]); // callh write16
	2578	UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode]); // callh write16
2578	2579	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2579	2580	return TRUE;
2580	2581
r2864	r2865
2582	2583	UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2583	2584	UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs
2584	2585	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2585		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	2586	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
2586	2587	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2587	2588	return TRUE;
2588	2589
r2864	r2865
2591	2592	UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xff)); // and i1,rs,0xff
2592	2593	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2593	2594	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2594		UML_CALLH(block, ppc->impstate->write8[ppc->impstate->mode ~~& 3~~]); // callh write8
	2595	UML_CALLH(block, ppc->impstate->write8[ppc->impstate->mode]); // callh write8
2595	2596	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
2596	2597	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2597	2598	return TRUE;
r2864	r2865
2601	2602	UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xffff)); // and i1,rs,0xffff
2602	2603	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2603	2604	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2604		UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode ~~& 3~~]); // callh write16
	2605	UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode]); // callh write16
2605	2606	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
2606	2607	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2607	2608	return TRUE;
r2864	r2865
2611	2612	UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs
2612	2613	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2613	2614	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2614		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	2615	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
2615	2616	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
2616	2617	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2617	2618	return TRUE;
r2864	r2865
2623	2624	{
2624	2625	UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM((INT16)G_SIMM(op) + 4 * (regnum - G_RD(op))));
2625	2626	// add i0,[tempaddr],simm + 4*(regnum-rd)
2626		UML_CALLH(block, ppc->impstate->read32align[ppc->impstate->mode ~~& 3~~]); // callh read32align
	2627	UML_CALLH(block, ppc->impstate->read32align[ppc->impstate->mode]); // callh read32align
2627	2628	UML_MOV(block, R32(regnum), IREG(0)); // mov regnum,i0
2628	2629	}
2629	2630	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
2637	2638	UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM((INT16)G_SIMM(op) + 4 * (regnum - G_RS(op))));
2638	2639	// add i0,[tempaddr],simm + 4*(regnum-rs)
2639	2640	UML_MOV(block, IREG(1), R32(regnum)); // mov i1,regnum
2640		UML_CALLH(block, ppc->impstate->write32align[ppc->impstate->mode ~~& 3~~]); // callh write32align
	2641	UML_CALLH(block, ppc->impstate->write32align[ppc->impstate->mode]); // callh write32align
2641	2642	}
2642	2643	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2643	2644	return TRUE;
r2864	r2865
2645	2646	case 0x30: /* LFS */
2646	2647	UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2647	2648	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2648		UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode ~~& 3~~]); // callh read32
	2649	UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode]); // callh read32
2649	2650	UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0)); // mov [tempdata],i0
2650	2651	UML_FDFRFLT(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l), DWORD); // fdfrflt fd,[tempdata],dword
2651	2652	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
2654	2655	case 0x32: /* LFD */
2655	2656	UML_ADD(block, IREG(0), R32Z(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2656	2657	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2657		UML_CALLH(block, ppc->impstate->read64[ppc->impstate->mode ~~& 3~~]); // callh read64
	2658	UML_CALLH(block, ppc->impstate->read64[ppc->impstate->mode]); // callh read64
2658	2659	UML_DMOV(block, MEM(&ppc->impstate->tempdata.d), IREG(0)); // dmov [tempdata],i0
2659	2660	UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata]
2660	2661	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
2664	2665	UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2665	2666	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2666	2667	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2667		UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode ~~& 3~~]); // callh read32
	2668	UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode]); // callh read32
2668	2669	UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0)); // mov [tempdata],i0
2669	2670	UML_FDFRFLT(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l), DWORD); // fdfrflt fd,[tempdata],dword
2670	2671	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
r2864	r2865
2675	2676	UML_ADD(block, IREG(0), R32(G_RA(op)), IMM((INT16)G_SIMM(op))); // add i0,ra,simm
2676	2677	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2677	2678	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2678		UML_CALLH(block, ppc->impstate->read64[ppc->impstate->mode ~~& 3~~]); // callh read64
	2679	UML_CALLH(block, ppc->impstate->read64[ppc->impstate->mode]); // callh read64
2679	2680	UML_DMOV(block, MEM(&ppc->impstate->tempdata.d), IREG(0)); // dmov [tempdata],i0
2680	2681	UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata]
2681	2682	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
r2864	r2865
2687	2688	UML_FSFRFLT(block, MEM(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), QWORD); // fsfrflt [tempdata],rs,qword
2688	2689	UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata]
2689	2690	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2690		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	2691	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
2691	2692	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2692	2693	return TRUE;
2693	2694
r2864	r2865
2696	2697	UML_FDMOV(block, MEM(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs
2697	2698	UML_DMOV(block, IREG(1), MEM(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata]
2698	2699	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMM(op)); // mapvar dsisr,DSISR_IMM(op)
2699		UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode ~~& 3~~]); // callh write64
	2700	UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode]); // callh write64
2700	2701	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2701	2702	return TRUE;
2702	2703
r2864	r2865
2706	2707	UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata]
2707	2708	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2708	2709	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2709		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	2710	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
2710	2711	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
2711	2712	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2712	2713	return TRUE;
r2864	r2865
2717	2718	UML_DMOV(block, IREG(1), MEM(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata]
2718	2719	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
2719	2720	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IMMU(op)); // mapvar dsisr,DSISR_IMMU(op)
2720		UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode ~~& 3~~]); // callh write64
	2721	UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode]); // callh write64
2721	2722	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
2722	2723	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
2723	2724	return TRUE;
r2864	r2865
3169	3170	case 0x057: /* LBZX */
3170	3171	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3171	3172	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3172		UML_CALLH(block, ppc->impstate->read8[ppc->impstate->mode ~~& 3~~]); // callh read8
	3173	UML_CALLH(block, ppc->impstate->read8[ppc->impstate->mode]); // callh read8
3173	3174	UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xff)); // and rd,i0,0xff
3174	3175	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3175	3176	return TRUE;
r2864	r2865
3177	3178	case 0x117: /* LHZX */
3178	3179	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3179	3180	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3180		UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode ~~& 3~~]); // callh read16
	3181	UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode]); // callh read16
3181	3182	UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xffff)); // and rd,i0,0xffff
3182	3183	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3183	3184	return TRUE;
r2864	r2865
3185	3186	case 0x157: /* LHAX */
3186	3187	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3187	3188	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3188		UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode ~~& 3~~]); // callh read16
	3189	UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode]); // callh read16
3189	3190	UML_SEXT(block, R32(G_RD(op)), IREG(0), WORD); // sext rd,i0,word
3190	3191	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3191	3192	return TRUE;
r2864	r2865
3193	3194	case 0x017: /* LWZX */
3194	3195	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3195	3196	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3196		UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode ~~& 3~~]); // callh read32
	3197	UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode]); // callh read32
3197	3198	UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0
3198	3199	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3199	3200	return TRUE;
r2864	r2865
3201	3202	case 0x217: /* LFSX */
3202	3203	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3203	3204	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3204		UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode ~~& 3~~]); // callh read32
	3205	UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode]); // callh read32
3205	3206	UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0)); // mov [tempdata],i0
3206	3207	UML_FDFRFLT(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l), DWORD); // fdfrflt fd,[tempdata],dword
3207	3208	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
3210	3211	case 0x257: /* LFDX */
3211	3212	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3212	3213	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3213		UML_CALLH(block, ppc->impstate->read64[ppc->impstate->mode ~~& 3~~]); // callh read64
	3214	UML_CALLH(block, ppc->impstate->read64[ppc->impstate->mode]); // callh read64
3214	3215	UML_DMOV(block, MEM(&ppc->impstate->tempdata.d), IREG(0)); // dmov [tempdata],i0
3215	3216	UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata]
3216	3217	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
3219	3220	case 0x316: /* LHBRX */
3220	3221	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3221	3222	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3222		UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode ~~& 3~~]); // callh read16
	3223	UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode]); // callh read16
3223	3224	UML_BSWAP(block, IREG(0), IREG(0)); // bswap i0,i0
3224	3225	UML_SHR(block, R32(G_RD(op)), IREG(0), IMM(16)); // shr rd,i0,16
3225	3226	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
3228	3229	case 0x216: /* LWBRX */
3229	3230	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3230	3231	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3231		UML_CALLH(block, ppc->impstate->read32align[ppc->impstate->mode ~~& 3~~]); // callh read32align
	3232	UML_CALLH(block, ppc->impstate->read32align[ppc->impstate->mode]); // callh read32align
3232	3233	UML_BSWAP(block, R32(G_RD(op)), IREG(0)); // bswap rd,i0
3233	3234	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3234	3235	return TRUE;
r2864	r2865
3237	3238	UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3238	3239	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3239	3240	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op)
3240		UML_CALLH(block, ppc->impstate->read8[ppc->impstate->mode ~~& 3~~]); // callh read8
	3241	UML_CALLH(block, ppc->impstate->read8[ppc->impstate->mode]); // callh read8
3241	3242	UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xff)); // and rd,i0,0xff
3242	3243	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
3243	3244	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
3247	3248	UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3248	3249	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3249	3250	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op)
3250		UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode ~~& 3~~]); // callh read16
	3251	UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode]); // callh read16
3251	3252	UML_AND(block, R32(G_RD(op)), IREG(0), IMM(0xffff)); // and rd,i0,0xffff
3252	3253	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
3253	3254	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
3257	3258	UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3258	3259	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3259	3260	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op)
3260		UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode ~~& 3~~]); // callh read16
	3261	UML_CALLH(block, ppc->impstate->read16[ppc->impstate->mode]); // callh read16
3261	3262	UML_SEXT(block, R32(G_RD(op)), IREG(0), WORD); // sext rd,i0,word
3262	3263	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
3263	3264	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
3267	3268	UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3268	3269	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3269	3270	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op)
3270		UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode ~~& 3~~]); // callh read32
	3271	UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode]); // callh read32
3271	3272	UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0
3272	3273	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
3273	3274	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
r2864	r2865
3277	3278	UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3278	3279	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3279	3280	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3280		UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode ~~& 3~~]); // callh read32
	3281	UML_CALLH(block, ppc->impstate->read32[ppc->impstate->mode]); // callh read32
3281	3282	UML_MOV(block, MEM(&ppc->impstate->tempdata.w.l), IREG(0)); // mov [tempdata],i0
3282	3283	UML_FDFRFLT(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.w.l), DWORD); // fdfrflt fd,[tempdata],dword
3283	3284	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
r2864	r2865
3288	3289	UML_ADD(block, IREG(0), R32(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3289	3290	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3290	3291	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3291		UML_CALLH(block, ppc->impstate->read64[ppc->impstate->mode ~~& 3~~]); // callh read64
	3292	UML_CALLH(block, ppc->impstate->read64[ppc->impstate->mode]); // callh read64
3292	3293	UML_DMOV(block, MEM(&ppc->impstate->tempdata.d), IREG(0)); // dmov [tempdata],i0
3293	3294	UML_FDMOV(block, F64(G_RD(op)), MEM(&ppc->impstate->tempdata.d)); // fdmov fd,[tempdata]
3294	3295	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
r2864	r2865
3298	3299	case 0x014: /* LWARX */
3299	3300	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3300	3301	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3301		UML_CALLH(block, ppc->impstate->read32align[ppc->impstate->mode ~~& 3~~]); // callh read32align
	3302	UML_CALLH(block, ppc->impstate->read32align[ppc->impstate->mode]); // callh read32align
3302	3303	UML_MOV(block, R32(G_RD(op)), IREG(0)); // mov rd,i0
3303	3304	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3304	3305	return TRUE;
r2864	r2865
3306	3307	case 0x255: /* LSWI */
3307	3308	UML_MOV(block, MEM(&ppc->impstate->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra
3308	3309	UML_MOV(block, MEM(&ppc->impstate->swcount), IMM(((G_NB(op) - 1) & 0x1f) + 1)); // mov [swcount],G_NB
3309		UML_CALLH(block, ppc->impstate->lsw[ppc->impstate->mode ~~& 3~~][G_RD(op)]); // call lsw[rd]
	3310	UML_CALLH(block, ppc->impstate->lsw[ppc->impstate->mode][G_RD(op)]); // call lsw[rd]
3310	3311	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3311	3312	return TRUE;
3312	3313
r2864	r2865
3314	3315	UML_ADD(block, MEM(&ppc->impstate->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb
3315	3316	UML_AND(block, MEM(&ppc->impstate->swcount), SPR32(SPR_XER), IMM(0x7f)); // and [swcount],[xer],0x7f
3316	3317	UML_SUB(block, MEM(&ppc->icount), MEM(&ppc->icount), MEM(&ppc->impstate->swcount));// sub icount,icount,[swcount]
3317		UML_CALLHc(block, IF_NZ, ppc->impstate->lsw[ppc->impstate->mode ~~& 3~~][G_RD(op)]);// call lsw[rd],nz
	3318	UML_CALLHc(block, IF_NZ, ppc->impstate->lsw[ppc->impstate->mode][G_RD(op)]);// call lsw[rd],nz
3318	3319	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3319	3320	return TRUE;
3320	3321
r2864	r2865
3326	3327	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3327	3328	UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xff)); // and i1,rs,0xff
3328	3329	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3329		UML_CALLH(block, ppc->impstate->write8[ppc->impstate->mode ~~& 3~~]); // callh write8
	3330	UML_CALLH(block, ppc->impstate->write8[ppc->impstate->mode]); // callh write8
3330	3331	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3331	3332	return TRUE;
3332	3333
r2864	r2865
3334	3335	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3335	3336	UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xffff)); // and i1,rs
3336	3337	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3337		UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode ~~& 3~~]); // callh write16
	3338	UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode]); // callh write16
3338	3339	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3339	3340	return TRUE;
3340	3341
r2864	r2865
3342	3343	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3343	3344	UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs
3344	3345	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3345		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	3346	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
3346	3347	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3347	3348	return TRUE;
3348	3349
r2864	r2865
3351	3352	UML_FSFRFLT(block, MEM(&ppc->impstate->tempdata.w.l), F64(G_RS(op)), QWORD); // fsfrflt [tempdata],rs,qword
3352	3353	UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata]
3353	3354	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3354		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	3355	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
3355	3356	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3356	3357	return TRUE;
3357	3358
r2864	r2865
3360	3361	UML_FDMOV(block, MEM(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs
3361	3362	UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata.lo]
3362	3363	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3363		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	3364	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
3364	3365	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3365	3366	return TRUE;
3366	3367
r2864	r2865
3369	3370	UML_FDMOV(block, MEM(&ppc->impstate->tempdata.d), F64(G_RS(op))); // fdmov [tempdata],rs
3370	3371	UML_DMOV(block, IREG(1), MEM(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata]
3371	3372	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3372		UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode ~~& 3~~]); // callh write64
	3373	UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode]); // callh write64
3373	3374	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3374	3375	return TRUE;
3375	3376
r2864	r2865
3378	3379	UML_BSWAP(block, IREG(1), R32(G_RS(op))); // bswap i1,rs
3379	3380	UML_SHR(block, IREG(1), IREG(1), IMM(16)); // shr i1,i1,16
3380	3381	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3381		UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode ~~& 3~~]); // callh write16
	3382	UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode]); // callh write16
3382	3383	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3383	3384	return TRUE;
3384	3385
r2864	r2865
3386	3387	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3387	3388	UML_BSWAP(block, IREG(1), R32(G_RS(op))); // bswap i1,rs
3388	3389	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3389		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	3390	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
3390	3391	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3391	3392	return TRUE;
3392	3393
r2864	r2865
3395	3396	UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xff)); // and i1,rs,0xff
3396	3397	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3397	3398	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3398		UML_CALLH(block, ppc->impstate->write8[ppc->impstate->mode ~~& 3~~]); // callh write8
	3399	UML_CALLH(block, ppc->impstate->write8[ppc->impstate->mode]); // callh write8
3399	3400	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
3400	3401	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3401	3402	return TRUE;
r2864	r2865
3405	3406	UML_AND(block, IREG(1), R32(G_RS(op)), IMM(0xffff)); // and i1,rs,0xffff
3406	3407	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3407	3408	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3408		UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode ~~& 3~~]); // callh write16
	3409	UML_CALLH(block, ppc->impstate->write16[ppc->impstate->mode]); // callh write16
3409	3410	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
3410	3411	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3411	3412	return TRUE;
r2864	r2865
3415	3416	UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs
3416	3417	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3417	3418	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDXU(op)); // mapvar dsisr,DSISR_IDXU(op)
3418		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	3419	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
3419	3420	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
3420	3421	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3421	3422	return TRUE;
r2864	r2865
3426	3427	UML_MOV(block, IREG(1), MEM(&ppc->impstate->tempdata.w.l)); // mov i1,[tempdata]
3427	3428	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3428	3429	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3429		UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode ~~& 3~~]); // callh write32
	3430	UML_CALLH(block, ppc->impstate->write32[ppc->impstate->mode]); // callh write32
3430	3431	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
3431	3432	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3432	3433	return TRUE;
r2864	r2865
3437	3438	UML_DMOV(block, IREG(1), MEM(&ppc->impstate->tempdata.d)); // dmov i1,[tempdata]
3438	3439	UML_MOV(block, MEM(&ppc->impstate->updateaddr), IREG(0)); // mov [updateaddr],i0
3439	3440	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3440		UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode ~~& 3~~]); // callh write64
	3441	UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode]); // callh write64
3441	3442	UML_MOV(block, R32(G_RA(op)), MEM(&ppc->impstate->updateaddr)); // mov ra,[updateaddr]
3442	3443	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3443	3444	return TRUE;
r2864	r2865
3446	3447	UML_ADD(block, IREG(0), R32Z(G_RA(op)), R32(G_RB(op))); // add i0,ra,rb
3447	3448	UML_MOV(block, IREG(1), R32(G_RS(op))); // mov i1,rs
3448	3449	UML_MAPVAR(block, MAPVAR_DSISR, DSISR_IDX(op)); // mapvar dsisr,DSISR_IDX(op)
3449		UML_CALLH(block, ppc->impstate->write32align[ppc->impstate->mode ~~& 3~~]); // callh write32align
	3450	UML_CALLH(block, ppc->impstate->write32align[ppc->impstate->mode]); // callh write32align
3450	3451	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3451	3452	UML_CMP(block, IREG(0), IREG(0)); // cmp i0,i0
3452	3453	generate_compute_flags(block, desc, TRUE, 0, FALSE); // <update flags>
r2864	r2865
3455	3456	case 0x2d5: /* STSWI */
3456	3457	UML_MOV(block, MEM(&ppc->impstate->updateaddr), R32Z(G_RA(op))); // mov [updateaddr],ra
3457	3458	UML_MOV(block, MEM(&ppc->impstate->swcount), IMM(((G_NB(op) - 1) & 0x1f) + 1)); // mov [swcount],G_NB
3458		UML_CALLH(block, ppc->impstate->stsw[ppc->impstate->mode ~~& 3~~][G_RD(op)]); // call stsw[rd]
	3459	UML_CALLH(block, ppc->impstate->stsw[ppc->impstate->mode][G_RD(op)]); // call stsw[rd]
3459	3460	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3460	3461	return TRUE;
3461	3462
r2864	r2865
3463	3464	UML_ADD(block, MEM(&ppc->impstate->updateaddr), R32Z(G_RA(op)), R32(G_RB(op))); // add [updateaddr],ra,rb
3464	3465	UML_AND(block, MEM(&ppc->impstate->swcount), SPR32(SPR_XER), IMM(0x7f)); // and [swcount],[xer],0x7f
3465	3466	UML_SUB(block, MEM(&ppc->icount), MEM(&ppc->icount), MEM(&ppc->impstate->swcount));// sub icount,icount,[swcount]
3466		UML_CALLHc(block, IF_NZ, ppc->impstate->stsw[ppc->impstate->mode ~~& 3~~][G_RD(op)]);// call stsw[rd]
	3467	UML_CALLHc(block, IF_NZ, ppc->impstate->stsw[ppc->impstate->mode][G_RD(op)]);// call stsw[rd]
3467	3468	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); // <update cycles>
3468	3469	return TRUE;
3469	3470
r2864	r2865
3491	3492	{
3492	3493	UML_ADD(block, IREG(0), MEM(&ppc->impstate->tempaddr), IMM(8 * item)); // add i0,[tempaddr],8*item
3493	3494	UML_DMOV(block, IREG(1), IMM(0)); // dmov i1,0
3494		UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode ~~& 3~~]); // callh write64
	3495	UML_CALLH(block, ppc->impstate->write64[ppc->impstate->mode]); // callh write64
3495	3496	}
3496	3497	return TRUE;
3497	3498

src/emu/cpu/powerpc/ppccom.c
r2864	r2865
14	14	DEBUGGING
15	15	***************************************************************************/
16	16
17		#define PRINTF_TLB_FILL (1)
18	17	#define PRINTF_SPU (0)
19	18	#define PRINTF_DECREMENTER (0)
20	19
r2864	r2865
61	60
62	61
63	62	/*-------------------------------------------------
64		tlb_entry_free - free an entry from the TLB,
65		by index
66		-------------------------------------------------*/
67
68		INLINE void tlb_entry_free(powerpc_state *ppc, int entrynum)
69		{
70		int oldentry = ppc->tlb_entries[entrynum];
71
72		/* if we're mapped to something, free the entry in the table */
73		if (oldentry != 0)
74		{
75		ppc->tlb_table[oldentry - 1] = 0;
76		ppc->tlb_entries[entrynum] = 0;
77		}
78		}
79
80
81		/*-------------------------------------------------
82		tlb_entry_allocate - allocate a TLB entry
83		for the given address, if needed, and set its
84		new value
85		-------------------------------------------------*/
86
87		INLINE int tlb_entry_allocate(powerpc_state *ppc, int entrynum, offs_t address, UINT32 value)
88		{
89		UINT32 *entry = &ppc->tlb_table[address >> 12];
90		int allocated = FALSE;
91
92		/* only need to allocate if we are empty */
93		if (*entry == 0)
94		{
95		/* if there's already a TLB entry at the current index, zap it */
96		tlb_entry_free(ppc, entrynum);
97
98		/* allocate a new entry and advance to the next one */
99		ppc->tlb_entries[entrynum] = (address >> 12) + 1;
100		allocated = TRUE;
101		}
102		*entry = value;
103
104		return allocated;
105		}
106
107
108		/*-------------------------------------------------
109	63	get_cr - return the current CR value
110	64	-------------------------------------------------*/
111	65
r2864	r2865
229	183	structure based on the configured type
230	184	-------------------------------------------------*/
231	185
232		si~~ze_t~~ ppccom_init(powerpc_state ppc, powerpc_flavor flavor, UINT8 cap, int tb_divisor, int clock, const powerpc_config config, int (irqcallback)(int)~~, void memory~~)
	186	void ppccom_init(powerpc_state ppc, powerpc_flavor flavor, UINT8 cap, int tb_divisor, int clock, const powerpc_config config, int (*irqcallback)(int))
233	187	{
234		/* if no memory, return the amount needed */
235		if (memory == NULL)
236		return sizeof(ppc->tlb_table[0]) * (POWERPC_TLB_ENTRIES + PPC603_FIXED_TLB_ENTRIES + (1 << (32 - POWERPC_MIN_PAGE_SHIFT)));
237
238	188	/* initialize based on the config */
239	189	memset(ppc, 0, sizeof(*ppc));
240	190	ppc->cpunum = cpu_getactivecpu();
r2864	r2865
247	197	ppc->system_clock = (config != NULL) ? config->bus_frequency : clock;
248	198	ppc->tb_divisor = (ppc->tb_divisor * clock + ppc->system_clock / 2 - 1) / ppc->system_clock;
249	199
250		/* initialize the TLB state */
251		ppc->tlb_entries = memory;
252		ppc->tlb_table = ppc->tlb_entries + POWERPC_TLB_ENTRIES + PPC603_FIXED_TLB_ENTRIES;
	200	/* allocate the virtual TLB */
	201	ppc->vtlb = vtlb_alloc(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, (cap & PPCCAP_603_MMU) ? PPC603_FIXED_TLB_ENTRIES : 0, POWERPC_TLB_ENTRIES);
253	202
254	203	/* allocate a timer for the compare interrupt */
255	204	if (cap & PPCCAP_OEA)
r2864	r2865
265	214
266	215	/* reset the state */
267	216	ppccom_reset(ppc);
268		return 0;
269	217	}
270	218
271	219
272	220	/*-------------------------------------------------
	221	ppccom_exit - common cleanup/exit
	222	-------------------------------------------------*/
	223
	224	void ppccom_exit(powerpc_state *ppc)
	225	{
	226	if (ppc->vtlb != NULL)
	227	vtlb_free(ppc->vtlb);
	228	}
	229
	230
	231	/*-------------------------------------------------
273	232	ppccom_reset - reset the state of all the
274	233	registers
275	234	-------------------------------------------------*/
276	235
277	236	void ppccom_reset(powerpc_state *ppc)
278	237	{
	238	int tlbindex;
	239
279	240	/* initialize the OEA state */
280	241	if (ppc->cap & PPCCAP_OEA)
281	242	{
r2864	r2865
307	268	ppc->irq_pending = 0;
308	269
309	270	/* flush the TLB */
310		ppc->tlb_index = 0;
311		memset(ppc->tlb_entries, 0, sizeof(ppc->tlb_entries[0]) * (POWERPC_TLB_ENTRIES + PPC603_FIXED_TLB_ENTRIES));
312		memset(ppc->tlb_table, 0, sizeof(ppc->tlb_table[0]) * (1 << (32 - POWERPC_MIN_PAGE_SHIFT)));
	271	vtlb_flush_dynamic(ppc->vtlb);
	272	if (ppc->cap & PPCCAP_603_MMU)
	273	for (tlbindex = 0; tlbindex < PPC603_FIXED_TLB_ENTRIES; tlbindex++)
	274	vtlb_load(ppc->vtlb, tlbindex, 0, 0, 0);
313	275	}
314	276
315	277
r2864	r2865
349	311	int batbase, batnum, hashnum;
350	312	UINT32 segreg;
351	313
	314	/* 4xx case: "TLB" really just caches writes and checks compare registers */
	315	if (ppc->cap & PPCCAP_4XX)
	316	{
	317	/* we don't support the MMU of the 403GCX */
	318	if (ppc->flavor == PPC_MODEL_403GCX && (ppc->msr & MSROEA_DR))
	319	fatalerror("MMU enabled but not supported!");
	320
	321	/* only check if PE is enabled */
	322	if (transtype == TRANSLATE_WRITE && (ppc->msr & MSR4XX_PE))
	323	{
	324	/* are we within one of the protection ranges? */
	325	int inrange1 = ((address >> 12) >= (ppc->spr[SPR4XX_PBL1] >> 12) && (address >> 12) < (ppc->spr[SPR4XX_PBU1] >> 12));
	326	int inrange2 = ((address >> 12) >= (ppc->spr[SPR4XX_PBL2] >> 12) && (address >> 12) < (ppc->spr[SPR4XX_PBU2] >> 12));
	327
	328	/* if PX == 1, writes are only allowed OUTSIDE of the bounds */
	329	if (((ppc->msr & MSR4XX_PX) && (inrange1 \|\| inrange2)) \|\| (!(ppc->msr & MSR4XX_PX) && (!inrange1 && !inrange2)))
	330	return 0x002;
	331	}
	332	*address &= 0x7fffffff;
	333	return 0x001;
	334	}
	335
352	336	/* only applies if we support the OEA */
353	337	if (!(ppc->cap & PPCCAP_OEA))
354	338	return 0x001;
r2864	r2865
471	455
472	456	void ppccom_tlb_fill(powerpc_state *ppc)
473	457	{
474		int transuser = (ppc->msr & MSR_PR) ? TRANSLATE_USER_MASK : 0;
475		offs_t address = ppc->param0;
476		int transtype = ppc->param1;
477		offs_t transaddr = address;
478		UINT32 entryval;
479
480		/* 4xx case: "TLB" really just caches writes and checks compare registers */
481		if (ppc->cap & PPCCAP_4XX)
482		{
483		/* assume success and direct translation */
484		ppc->param0 = 1;
485		transaddr = address & 0x7fffffff;
486
487		/* we don't support the MMU of the 403GCX */
488		if (ppc->flavor == PPC_MODEL_403GCX && (ppc->msr & MSROEA_DR))
489		fatalerror("MMU enabled but not supported!");
490
491		/* only check if PE is enabled */
492		if (transtype == TRANSLATE_WRITE && (ppc->msr & MSR4XX_PE))
493		{
494		/* are we within one of the protection ranges? */
495		int inrange1 = ((address >> 12) >= (ppc->spr[SPR4XX_PBL1] >> 12) && (address >> 12) < (ppc->spr[SPR4XX_PBU1] >> 12));
496		int inrange2 = ((address >> 12) >= (ppc->spr[SPR4XX_PBL2] >> 12) && (address >> 12) < (ppc->spr[SPR4XX_PBU2] >> 12));
497
498		/* if PX == 1, writes are only allowed OUTSIDE of the bounds */
499		if (((ppc->msr & MSR4XX_PX) && (inrange1 \|\| inrange2)) \|\| (!(ppc->msr & MSR4XX_PX) && (!inrange1 && !inrange2)))
500		ppc->param0 = 2;
501		}
502		}
503
504		/* OEA case: perform an address translation */
505		else
506		ppc->param0 = ppccom_translate_address_internal(ppc, transtype \| transuser, &transaddr);
507
508		/* log information and return upon failure */
509		if (PRINTF_TLB_FILL)
510		printf("tlb_fill: %08X (%s%s) -> ", address, (transtype == TRANSLATE_READ) ? "R" : (transtype == TRANSLATE_WRITE) ? "W" : "F", transuser ? "U" : "S");
511		if (ppc->param0 > 1)
512		{
513		if (PRINTF_TLB_FILL)
514		printf("failed(%08X)\n", ppc->param0);
515		return;
516		}
517
518		/* if we did translate the address, get a pointer to our entry in the TLB table and fill it in */
519		if (PRINTF_TLB_FILL)
520		printf("succeeded(%d) -> %08X\n", ppc->param0, transaddr);
521		entryval = (transaddr & 0xfffff000) \| TLB_READ \| ((ppc->param0 & 1) ? TLB_WRITE : 0);
522		if (tlb_entry_allocate(ppc, ppc->tlb_index, address, entryval))
523		ppc->tlb_index = (ppc->tlb_index + 1) % POWERPC_TLB_ENTRIES;
	458	vtlb_fill(ppc->vtlb, ppc->param0, ppc->param1);
524	459	}
525	460
526	461
r2864	r2865
531	466
532	467	void ppccom_tlb_flush(powerpc_state *ppc)
533	468	{
534		int entnum;
535
536		/* iterate over entries and invalidate them */
537		for (entnum = 0; entnum < POWERPC_TLB_ENTRIES; entnum++)
538		tlb_entry_free(ppc, entnum);
	469	vtlb_flush_dynamic(ppc->vtlb);
539	470	}
540	471
541	472
r2864	r2865
551	482
552	483	void ppccom_execute_tlbie(powerpc_state *ppc)
553	484	{
554		offs_t address = ppc->param0;
555
556		/* just nuke it in the table; we may have spare entries referencing it, but no harm */
557		ppc->tlb_table[address >> 12] = 0;
	485	vtlb_flush_address(ppc->vtlb, ppc->param0);
558	486	}
559	487
560	488
r2864	r2865
565	493
566	494	void ppccom_execute_tlbia(powerpc_state *ppc)
567	495	{
568		~~ppccom_~~tlb_flush(ppc);
	496	vtlb_flush_dynamic(ppc->vtlb);
569	497	}
570	498
571	499
r2864	r2865
578	506	{
579	507	UINT32 address = ppc->param0;
580	508	int isitlb = ppc->param1;
581		UINT32 entrynum, entryval;
	509	vtlb_entry flags = 0;
	510	int entrynum;
582	511
583	512	/* determine entry number; we use rand() for associativity */
584	513	entrynum = ((address >> 12) & 0x1f) \| (mame_rand(Machine) & 0x20) \| (isitlb ? 0x40 : 0);
585	514
586		/* invalidate any existing TLB entry here */
587		ppc->tlb_table[address >> 12] = 0;
	515	/* determine the flags */
	516	flags = VTLB_FLAG_VALID \| VTLB_READ_ALLOWED \| VTLB_FETCH_ALLOWED;
	517	if (ppc->spr[SPR603_RPA] & 0x80)
	518	flags \|= VTLB_WRITE_ALLOWED;
	519	if (isitlb)
	520	flags \|= VTLB_FETCH_ALLOWED;
588	521
589		/* allocate this entry */
590		entryval = (ppc->spr[SPR603_RPA] & 0xfffff000) \| TLB_READ \| ((ppc->spr[SPR603_RPA] & 0x80) ? TLB_WRITE : 0);
591		tlb_entry_allocate(ppc, POWERPC_TLB_ENTRIES + entrynum, address, entryval);
592		if (PRINTF_TLB_FILL)
593		printf("tlb_load: %08X (%sS) -> %08X\n", address, isitlb ? "F" : "R", ppc->spr[SPR603_RPA] & 0xfffff000);
	522	/* load the entry */
	523	vtlb_load(ppc->vtlb, entrynum, 1, address, (ppc->spr[SPR603_RPA] & 0xfffff000) \| flags);
594	524	}
595	525
596	526
r2864	r2865
1897	1827
1898	1828	case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
1899	1829	case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 31; break;
1900		case CPUINFO_INT_LOGADDR_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
1901		case CPUINFO_INT_PAGE_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
	1830	case CPUINFO_INT_LOGADDR_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
	1831	case CPUINFO_INT_PAGE_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = POWERPC_MIN_PAGE_SHIFT;break;
1902	1832
1903	1833	/* --- the following bits of info are returned as pointers to data or functions --- */
1904	1834	case CPUINFO_PTR_INIT: /* provided per-CPU */ break;

src/emu/cpu/powerpc/ppccom.h
r2864	r2865
11	11
12	12	#include "cpuintrf.h"
13	13	#include "ppc.h"
	14	#include "cpu/vtlb.h"
14	15
15	16
16	17	/***************************************************************************
r2864	r2865
39	40	#define PPCCAP_603_MMU 0x20 /* TRUE if we have 603-class MMU features */
40	41
41	42
42		/* bits in our internal TLB */
43		#define TLB_READ 0x01 /* reads are allowed */
44		#define TLB_WRITE 0x02 /* writes are allowed */
45
46
47	43	/* PowerPC flavors */
48	44	enum _powerpc_flavor
49	45	{
r2864	r2865
531	527	UINT32 param1;
532	528
533	529	/* MMU */
534		UINT32 * tlb_table;
535		UINT32 * tlb_entries;
536		UINT32 tlb_index;
	530	vtlb_state * vtlb;
537	531
538	532	/* architectural distinctions */
539	533	powerpc_flavor flavor;
r2864	r2865
574	568	FUNCTION PROTOTYPES
575	569	***************************************************************************/
576	570
577		size_t ppccom_init(powerpc_state ppc, powerpc_flavor flavor, UINT8 cap, int tb_divisor, int clock, const powerpc_config config, int (irqcallback)(int), void memory);
	571	void ppccom_init(powerpc_state ppc, powerpc_flavor flavor, UINT8 cap, int tb_divisor, int clock, const powerpc_config config, int (*irqcallback)(int));
	572	void ppccom_exit(powerpc_state *ppc);
	573
578	574	void ppccom_reset(powerpc_state *ppc);
579	575	#ifdef ENABLE_DEBUGGER
580	576	offs_t ppccom_dasm(powerpc_state ppc, char buffer, offs_t pc, const UINT8 oprom, const UINT8 opram);

src/emu/cpu/vtlb.c
r0	r2865
	1	/***************************************************************************
	2
	3	vtlb.c
	4
	5	Generic virtual TLB implementation.
	6
	7	Copyright Aaron Giles
	8	Released for general non-commercial use under the MAME license
	9	Visit http://mamedev.org for licensing and usage restrictions.
	10
	11	***************************************************************************/
	12
	13	#include "vtlb.h"
	14
	15
	16
	17	/***************************************************************************
	18	DEBUGGING
	19	***************************************************************************/
	20
	21	#define PRINTF_TLB (0)
	22
	23
	24
	25	/***************************************************************************
	26	TYPE DEFINITIONS
	27	***************************************************************************/
	28
	29	/* VTLB state */
	30	struct _vtlb_state
	31	{
	32	int space; /* address space */
	33	int dynamic; /* number of dynamic entries */
	34	int fixed; /* number of fixed entries */
	35	int dynindex; /* index of next dynamic entry */
	36	int pageshift; /* bits to shift to get page index */
	37	int addrwidth; /* logical address bus width */
	38	offs_t * live; /* array of live entries by table index */
	39	int * fixedpages; /* number of pages each fixed entry covers */
	40	vtlb_entry * table; /* table of entries by address */
	41	cpu_translate_func translate; /* translate function */
	42	};
	43
	44
	45
	46	/***************************************************************************
	47	INITIALIZATION/TEARDOWN
	48	***************************************************************************/
	49
	50	/*-------------------------------------------------
	51	vtlb_alloc - allocate a new VTLB for the
	52	given CPU
	53	-------------------------------------------------*/
	54
	55	vtlb_state *vtlb_alloc(int cpunum, int space, int fixed_entries, int dynamic_entries)
	56	{
	57	vtlb_state *vtlb;
	58
	59	/* allocate memory for the core structure */
	60	vtlb = malloc_or_die(sizeof(*vtlb));
	61	memset(vtlb, 0, sizeof(*vtlb));
	62
	63	/* fill in CPU information */
	64	vtlb->space = space;
	65	vtlb->dynamic = dynamic_entries;
	66	vtlb->fixed = fixed_entries;
	67	vtlb->pageshift = cpunum_page_shift(cpunum, space);
	68	vtlb->addrwidth = cpunum_logaddr_width(cpunum, space);
	69	vtlb->translate = (cpu_translate_func)cpunum_get_info_fct(cpunum, CPUINFO_PTR_TRANSLATE);
	70
	71	/* validate CPU information */
	72	assert((1 << vtlb->pageshift) > VTLB_FLAGS_MASK);
	73	assert(vtlb->translate != NULL);
	74	assert(vtlb->addrwidth > vtlb->pageshift);
	75
	76	/* allocate the entry array */
	77	vtlb->live = malloc_or_die(sizeof(vtlb->live[0]) * (fixed_entries + dynamic_entries));
	78	memset(vtlb->live, 0, sizeof(vtlb->live[0]) * (fixed_entries + dynamic_entries));
	79
	80	/* allocate the lookup table */
	81	vtlb->table = malloc_or_die(sizeof(vtlb->table[0]) << (vtlb->addrwidth - vtlb->pageshift));
	82	memset(vtlb->table, 0, sizeof(vtlb->table[0]) << (vtlb->addrwidth - vtlb->pageshift));
	83
	84	/* allocate the fixed page count array */
	85	if (fixed_entries > 0)
	86	{
	87	vtlb->fixedpages = malloc_or_die(sizeof(vtlb->fixedpages[0]) * fixed_entries);
	88	memset(vtlb->fixedpages, 0, sizeof(vtlb->fixedpages[0]) * fixed_entries);
	89	}
	90
	91	return vtlb;
	92	}
	93
	94
	95	/*-------------------------------------------------
	96	vtlb_free - free an allocated VTLB
	97	-------------------------------------------------*/
	98
	99	void vtlb_free(vtlb_state *vtlb)
	100	{
	101	/* free the fixed pages if allocated */
	102	if (vtlb->fixedpages != NULL)
	103	free(vtlb->fixedpages);
	104
	105	/* free the table and array if they exist */
	106	if (vtlb->live != NULL)
	107	free(vtlb->live);
	108	if (vtlb->table != NULL)
	109	free(vtlb->table);
	110
	111	/* and then the VTLB object itself */
	112	free(vtlb);
	113	}
	114
	115
	116
	117	/***************************************************************************
	118	FILLING
	119	***************************************************************************/
	120
	121	/*-------------------------------------------------
	122	vtlb_fill - rcalled by the CPU core in
	123	response to an unmapped access
	124	-------------------------------------------------*/
	125
	126	int vtlb_fill(vtlb_state *vtlb, offs_t address, int intention)
	127	{
	128	offs_t tableindex = address >> vtlb->pageshift;
	129	vtlb_entry entry = vtlb->table[tableindex];
	130	offs_t taddress;
	131
	132	if (PRINTF_TLB)
	133	printf("vtlb_fill: %08X(%X) ... ", address, intention);
	134
	135	/* should not be called here if the entry is in the table already */
	136	// assert((entry & (1 << intention)) == 0);
	137
	138	/* if we have no dynamic entries, we always fail */
	139	if (vtlb->dynamic == 0)
	140	{
	141	if (PRINTF_TLB)
	142	printf("failed: no dynamic entries\n");
	143	return FALSE;
	144	}
	145
	146	/* ask the CPU core to translate for us */
	147	taddress = address;
	148	if (!(*vtlb->translate)(vtlb->space, intention, &taddress))
	149	{
	150	if (PRINTF_TLB)
	151	printf("failed: no translation\n");
	152	return FALSE;
	153	}
	154
	155	/* if this is the first successful translation for this address, allocate a new entry */
	156	if ((entry & VTLB_FLAGS_MASK) == 0)
	157	{
	158	int liveindex = vtlb->dynindex++ % vtlb->dynamic;
	159
	160	/* if an entry already exists at this index, free it */
	161	if (vtlb->live[liveindex] != 0)
	162	vtlb->table[vtlb->live[liveindex] - 1] = 0;
	163
	164	/* claim this new entry */
	165	vtlb->live[liveindex] = tableindex + 1;
	166
	167	/* form a new blank entry */
	168	entry = (taddress >> vtlb->pageshift) << vtlb->pageshift;
	169	entry \|= VTLB_FLAG_VALID;
	170
	171	if (PRINTF_TLB)
	172	printf("success (%08X), new entry\n", taddress);
	173	}
	174
	175	/* otherwise, ensure that different intentions do not produce different addresses */
	176	else
	177	{
	178	assert((entry >> vtlb->pageshift) == (taddress >> vtlb->pageshift));
	179	assert(entry & VTLB_FLAG_VALID);
	180
	181	if (PRINTF_TLB)
	182	printf("success (%08X), existing entry\n", taddress);
	183	}
	184
	185	/* add the intention to the list of valid intentions and store */
	186	entry \|= 1 << (intention & (TRANSLATE_TYPE_MASK \| TRANSLATE_USER_MASK));
	187	vtlb->table[tableindex] = entry;
	188	return TRUE;
	189	}
	190
	191
	192	/*-------------------------------------------------
	193	vtlb_load - load a fixed VTLB entry
	194	-------------------------------------------------*/
	195
	196	void vtlb_load(vtlb_state *vtlb, int entrynum, int numpages, offs_t address, vtlb_entry value)
	197	{
	198	offs_t tableindex = address >> vtlb->pageshift;
	199	int liveindex = vtlb->dynamic + entrynum;
	200	int pagenum;
	201
	202	/* must be in range */
	203	assert(entrynum >= 0 && entrynum < vtlb->fixed);
	204
	205	if (PRINTF_TLB)
	206	printf("vtlb_load %d for %d pages at %08X == %08X\n", entrynum, numpages, address, value);
	207
	208	/* if an entry already exists at this index, free it */
	209	if (vtlb->live[liveindex] != 0)
	210	{
	211	int pagecount = vtlb->fixedpages[entrynum];
	212	for (pagenum = 0; pagenum < pagecount; pagenum++)
	213	vtlb->table[vtlb->live[liveindex] - 1 + pagenum] = 0;
	214	}
	215
	216	/* claim this new entry */
	217	vtlb->live[liveindex] = tableindex + 1;
	218
	219	/* store the raw value, making sure the "fixed" flag is set */
	220	value \|= VTLB_FLAG_FIXED;
	221	for (pagenum = 0; pagenum < numpages; pagenum++)
	222	vtlb->table[tableindex + pagenum] = value + (pagenum << vtlb->pageshift);
	223	}
	224
	225
	226
	227	/***************************************************************************
	228	FLUSHING
	229	***************************************************************************/
	230
	231	/*-------------------------------------------------
	232	vtlb_flush_dynamic - flush all knowledge
	233	from the dynamic part of the VTLB
	234	-------------------------------------------------*/
	235
	236	void vtlb_flush_dynamic(vtlb_state *vtlb)
	237	{
	238	int liveindex;
	239
	240	if (PRINTF_TLB)
	241	printf("vtlb_flush_dynamic\n");
	242
	243	/* loop over live entries and release them from the table */
	244	for (liveindex = 0; liveindex < vtlb->dynamic; liveindex++)
	245	if (vtlb->live[liveindex] != 0)
	246	{
	247	offs_t tableindex = vtlb->live[liveindex] - 1;
	248	vtlb->table[tableindex] = 0;
	249	vtlb->live[liveindex] = 0;
	250	}
	251	}
	252
	253
	254	/*-------------------------------------------------
	255	vtlb_flush_address - flush knowledge of a
	256	particular address from the VTLB
	257	-------------------------------------------------*/
	258
	259	void vtlb_flush_address(vtlb_state *vtlb, offs_t address)
	260	{
	261	offs_t tableindex = address >> vtlb->pageshift;
	262
	263	if (PRINTF_TLB)
	264	printf("vtlb_flush_address %08X\n", address);
	265
	266	/* free the entry in the table; for speed, we leave the entry in the live array */
	267	vtlb->table[tableindex] = 0;
	268	}
	269
	270
	271
	272	/***************************************************************************
	273	ACCESSORS
	274	***************************************************************************/
	275
	276	/*-------------------------------------------------
	277	vtlb_table - return a pointer to the base of
	278	the linear VTLB lookup table
	279	-------------------------------------------------*/
	280
	281	const vtlb_entry vtlb_table(vtlb_state vtlb)
	282	{
	283	return vtlb->table;
	284	}

src/emu/cpu/vtlb.h
r0	r2865
	1	/***************************************************************************
	2
	3	vtlb.h
	4
	5	Generic virtual TLB implementation.
	6
	7	Copyright Aaron Giles
	8	Released for general non-commercial use under the MAME license
	9	Visit http://mamedev.org for licensing and usage restrictions.
	10
	11	***************************************************************************/
	12
	13	#pragma once
	14
	15	#ifndef __VTLB_H__
	16	#define __VTLB_H__
	17
	18	#include "cpuintrf.h"
	19
	20
	21	/***************************************************************************
	22	CONSTANTS
	23	***************************************************************************/
	24
	25	#define VTLB_FLAGS_MASK 0xff
	26
	27	#define VTLB_READ_ALLOWED 0x01 /* (1 << TRANSLATE_READ) */
	28	#define VTLB_WRITE_ALLOWED 0x02 /* (1 << TRANSLATE_WRITE) */
	29	#define VTLB_FETCH_ALLOWED 0x04 /* (1 << TRANSLATE_FETCH) */
	30	#define VTLB_FLAG_VALID 0x08
	31	#define VTLB_USER_READ_ALLOWED 0x10 /* (1 << TRANSLATE_READ_USER) */
	32	#define VTLB_USER_WRITE_ALLOWED 0x20 /* (1 << TRANSLATE_WRITE_USER) */
	33	#define VTLB_USER_FETCH_ALLOWED 0x40 /* (1 << TRANSLATE_FETCH_USER) */
	34	#define VTLB_FLAG_FIXED 0x80
	35
	36
	37
	38	/***************************************************************************
	39	TYPE DEFINITIONS
	40	***************************************************************************/
	41
	42	/* represents an entry in the VTLB */
	43	typedef UINT32 vtlb_entry;
	44
	45
	46	/* opaque structure describing VTLB state */
	47	typedef struct _vtlb_state vtlb_state;
	48
	49
	50
	51	/***************************************************************************
	52	FUNCTION PROTOTYPES
	53	***************************************************************************/
	54
	55
	56	/* ----- initialization/teardown ----- */
	57
	58	/* allocate a new VTLB for the given CPU */
	59	vtlb_state *vtlb_alloc(int cpunum, int space, int fixed_entries, int dynamic_entries);
	60
	61	/* free an allocated VTLB */
	62	void vtlb_free(vtlb_state *vtlb);
	63
	64
	65	/* ----- filling ----- */
	66
	67	/* called by the CPU core in response to an unmapped access */
	68	int vtlb_fill(vtlb_state *vtlb, offs_t address, int intention);
	69
	70	/* load a fixed VTLB entry */
	71	void vtlb_load(vtlb_state *vtlb, int entrynum, int numpages, offs_t address, vtlb_entry value);
	72
	73
	74	/* ----- flushing ----- */
	75
	76	/* flush all knowledge from the dynamic part of the VTLB */
	77	void vtlb_flush_dynamic(vtlb_state *vtlb);
	78
	79	/* flush knowledge of a particular address from the VTLB */
	80	void vtlb_flush_address(vtlb_state *vtlb, offs_t address);
	81
	82
	83	/* ----- accessors ----- */
	84
	85	/* return a pointer to the base of the linear VTLB lookup table */
	86	const vtlb_entry vtlb_table(vtlb_state vtlb);
	87
	88
	89	#endif

src/emu/cpu/mips/mips3com.h
r2864	r2865
11	11
12	12	#include "cpuintrf.h"
13	13	#include "mips3.h"
	14	#include "cpu/vtlb.h"
14	15
15	16
16	17	/***************************************************************************
r2864	r2865
186	187	/* COP registers */
187	188	UINT64 cpr[3][32];
188	189	UINT64 ccr[3][32];
189		UINT8 ~~cf[3][8]~~;
	190	UINT32 llbit;
190	191
191	192	/* internal stuff */
192	193	mips3_flavor flavor;
r2864	r2865
201	202	data_accessors memory;
202	203
203	204	/* cache memory */
204		UINT32 * icache;
205		UINT32 * dcache;
206	205	size_t icache_size;
207	206	size_t dcache_size;
208	207
209	208	/* MMU */
	209	vtlb_state * vtlb;
210	210	mips3_tlb_entry tlb[MIPS3_TLB_ENTRIES];
211		UINT32 * tlb_table;
212	211
213	212	/* for use by specific implementations */
214	213	mips3imp_state *impstate;
r2864	r2865
220	219	FUNCTION PROTOTYPES
221	220	***************************************************************************/
222	221
223		size_t mips3com_init(mips3_state mips, mips3_flavor flavor, int bigendian, int index, int clock, const mips3_config config, int (irqcallback)(int), void memory);
	222	void mips3com_init(mips3_state mips, mips3_flavor flavor, int bigendian, int index, int clock, const mips3_config config, int (*irqcallback)(int));
	223	void mips3com_exit(mips3_state *mips);
	224
224	225	void mips3com_reset(mips3_state *mips);
225	226	#ifdef ENABLE_DEBUGGER
226	227	offs_t mips3com_dasm(mips3_state mips, char buffer, offs_t pc, const UINT8 oprom, const UINT8 opram);
227	228	#endif
228	229	void mips3com_update_cycle_counting(mips3_state *mips);
229	230
	231	void mips3com_map_tlb_entry(mips3_state *mips, int tlbindex);
230	232	void mips3com_map_tlb_entries(mips3_state *mips);
231		void mips3com_unmap_tlb_entries(mips3_state *mips);
232		void mips3com_recompute_tlb_table(mips3_state *mips);
	233	void mips3com_asid_changed(mips3_state *mips);
233	234	int mips3com_translate_address(mips3_state mips, int space, int intention, offs_t address);
234	235	void mips3com_tlbr(mips3_state *mips);
235	236	void mips3com_tlbwi(mips3_state *mips);

src/emu/cpu/mips/mips3fe.c
r2864	r2865
168	168	case 0x2c: /* SDL */
169	169	case 0x2d: /* SDR */
170	170	case 0x2e: /* SWR */
	171	case 0x3f: /* SD */
	172	desc->regin[0] \|= REGFLAG_R(RSREG) \| REGFLAG_R(RTREG);
	173	desc->flags \|= OPFLAG_WRITES_MEMORY \| OPFLAG_CAN_CAUSE_EXCEPTION;
	174	return TRUE;
	175
171	176	case 0x38: /* SC */
172	177	case 0x3c: /* SCD */
173		case 0x3f: /* SD */
174	178	desc->regin[0] \|= REGFLAG_R(RSREG) \| REGFLAG_R(RTREG);
	179	desc->regout[0] \|= REGFLAG_R(RTREG);
175	180	desc->flags \|= OPFLAG_WRITES_MEMORY \| OPFLAG_CAN_CAUSE_EXCEPTION;
176	181	return TRUE;
177	182

src/emu/cpu/mips/mips3drc.c
r2864	r2865
44	44	***************************************************************************/
45	45
46	46	#define FORCE_C_BACKEND (0)
47		#define LOG_UML (1)
48		#define LOG_NATIVE (1)
	47	#define LOG_UML (0)
	48	#define LOG_NATIVE (0)
49	49
50	50	#define DISABLE_FAST_REGISTERS (0)
51	51	#define SINGLE_INSTRUCTION_MODE (0)
r2864	r2865
353	353	drccache *cache;
354	354	drcbe_info beinfo;
355	355	UINT32 flags = 0;
356		size_t extrasize;
357		void *extramem;
358	356	int regnum;
359	357
360		/* determine how much memory beyond the core size we need */
361		extrasize = mips3com_init(NULL, flavor, bigendian, index, clock, config, irqcallback, NULL);
362
363	358	/* allocate enough space for the cache and the core */
364		cache = drccache_alloc(CACHE_SIZE + sizeof(*mips3) ~~+ extrasize~~);
	359	cache = drccache_alloc(CACHE_SIZE + sizeof(*mips3));
365	360	if (cache == NULL)
366		fatalerror("Unable to allocate cache of size %d", (UINT32)(CACHE_SIZE + sizeof(*mips3) ~~+ extrasize~~));
	361	fatalerror("Unable to allocate cache of size %d", (UINT32)(CACHE_SIZE + sizeof(*mips3)));
367	362
368		/* allocate the core ~~and the extra~~ memory */
	363	/* allocate the core memory */
369	364	mips3 = drccache_memory_alloc_near(cache, sizeof(*mips3));
370	365	memset(mips3, 0, sizeof(*mips3));
371		extramem = drccache_memory_alloc(cache, extrasize);
372		memset(extramem, 0, extrasize);
373	366
374	367	/* initialize the core */
375		mips3com_init(mips3, flavor, bigendian, index, clock, config, irqcallback~~, extramem~~);
	368	mips3com_init(mips3, flavor, bigendian, index, clock, config, irqcallback);
376	369
377	370	/* allocate the implementation-specific state from the full cache */
378	371	mips3->impstate = drccache_memory_alloc_near(cache, sizeof(*mips3->impstate));
r2864	r2865
390	383	if (mips3->impstate->drcuml == NULL)
391	384	fatalerror("Error initializing the UML");
392	385
	386	/* add symbols for our stuff */
	387	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->pc, sizeof(mips3->pc), "pc");
	388	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->icount, sizeof(mips3->icount), "icount");
	389	for (regnum = 0; regnum < 32; regnum++)
	390	{
	391	char buf[10];
	392	sprintf(buf, "r%d", regnum);
	393	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->r[regnum], sizeof(mips3->r[regnum]), buf);
	394	sprintf(buf, "f%d", regnum);
	395	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[1][regnum], sizeof(mips3->cpr[1][regnum]), buf);
	396	}
	397	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->r[REG_LO], sizeof(mips3->r[REG_LO]), "lo");
	398	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->r[REG_HI], sizeof(mips3->r[REG_LO]), "hi");
	399	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_Index], sizeof(mips3->cpr[0][COP0_Index]), "Index");
	400	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_Random], sizeof(mips3->cpr[0][COP0_Random]), "Random");
	401	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_EntryLo0], sizeof(mips3->cpr[0][COP0_EntryLo0]), "EntryLo0");
	402	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_EntryLo1], sizeof(mips3->cpr[0][COP0_EntryLo1]), "EntryLo1");
	403	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_Context], sizeof(mips3->cpr[0][COP0_Context]), "Context");
	404	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_PageMask], sizeof(mips3->cpr[0][COP0_PageMask]), "PageMask");
	405	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_Wired], sizeof(mips3->cpr[0][COP0_Wired]), "Wired");
	406	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_BadVAddr], sizeof(mips3->cpr[0][COP0_BadVAddr]), "BadVAddr");
	407	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_Count], sizeof(mips3->cpr[0][COP0_Count]), "Count");
	408	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_EntryHi], sizeof(mips3->cpr[0][COP0_EntryHi]), "EntryHi");
	409	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_Compare], sizeof(mips3->cpr[0][COP0_Compare]), "Compare");
	410	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_Status], sizeof(mips3->cpr[0][COP0_Status]), "Status");
	411	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_Cause], sizeof(mips3->cpr[0][COP0_Cause]), "Cause");
	412	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_EPC], sizeof(mips3->cpr[0][COP0_EPC]), "EPC");
	413	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_PRId], sizeof(mips3->cpr[0][COP0_PRId]), "PRId");
	414	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_Config], sizeof(mips3->cpr[0][COP0_Config]), "Config");
	415	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_LLAddr], sizeof(mips3->cpr[0][COP0_LLAddr]), "LLAddr");
	416	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_XContext], sizeof(mips3->cpr[0][COP0_XContext]), "XContext");
	417	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_ECC], sizeof(mips3->cpr[0][COP0_ECC]), "ECC");
	418	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_CacheErr], sizeof(mips3->cpr[0][COP0_CacheErr]), "CacheErr");
	419	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_TagLo], sizeof(mips3->cpr[0][COP0_TagLo]), "TagLo");
	420	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_TagHi], sizeof(mips3->cpr[0][COP0_TagHi]), "TagHi");
	421	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->cpr[0][COP0_ErrorPC], sizeof(mips3->cpr[0][COP0_ErrorPC]), "ErrorPC");
	422	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->ccr[1][31], sizeof(mips3->cpr[1][31]), "fcr31");
	423	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->impstate->mode, sizeof(mips3->impstate->mode), "mode");
	424	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->impstate->arg0, sizeof(mips3->impstate->arg0), "arg0");
	425	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->impstate->arg1, sizeof(mips3->impstate->arg1), "arg1");
	426	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->impstate->numcycles, sizeof(mips3->impstate->numcycles), "numcycles");
	427	drcuml_symbol_add(mips3->impstate->drcuml, &mips3->impstate->fpmode, sizeof(mips3->impstate->fpmode), "fpmode");
	428
393	429	/* initialize the front-end helper */
394	430	if (SINGLE_INSTRUCTION_MODE)
395	431	feconfig.max_sequence = 1;
r2864	r2865
489	525
490	526	static void mips3_exit(void)
491	527	{
	528	mips3com_exit(mips3);
	529
492	530	/* clean up the DRC */
493	531	drcfe_exit(mips3->impstate->drcfe);
494	532	drcuml_free(mips3->impstate->drcuml);
r2864	r2865
1020	1058	UML_RECOVER(block, IREG(0), MAPVAR_PC); // recover i0,PC
1021	1059	UML_MOV(block, MEM(&mips3->pc), IREG(0)); // mov <pc>,i0
1022	1060	UML_SHR(block, IREG(1), IREG(0), IMM(12)); // shr i1,i0,12
1023		UML_LOAD(block, IREG(1), mi~~ps3->~~tlb_table, IREG(1), DWORD); // load i1,[tlb_table],i1,dword
	1061	UML_LOAD(block, IREG(1), (void *)vtlb_table(mips3->vtlb), IREG(1), DWORD); // load i1,[vtlb_table],i1,dword
1024	1062	if (PRINTF_MMU)
1025	1063	{
1026	1064	UML_MOV(block, MEM(&mips3->impstate->arg0), IREG(0)); // mov [arg0],i0
1027	1065	UML_MOV(block, MEM(&mips3->impstate->arg1), IREG(1)); // mov [arg1],i1
1028	1066	UML_CALLC(block, cfunc_printf_debug, "TLB mismatch @ %08X (ent=%08X)\n"); // callc printf_debug
1029	1067	}
1030		UML_TEST(block, IREG(1), IMM(TLB_VALID)); // test i1,TLB_VALID
	1068	UML_TEST(block, IREG(1), IMM(VTLB_FETCH_ALLOWED)); // test i1,VTLB_FETCH_ALLOWED
1031	1069	UML_JMPc(block, IF_NZ, 1); // jmp 1,nz
1032		UML_TEST(block, IREG(1), IMM(TLB_PRESENT)); // test i1,TLB_PRESENT
1033		UML_EXHc(block, IF_NZ, mips3->impstate->exception[EXCEPTION_TLBLOAD], IREG(0)); // exh exception[TLBLOAD],i0,nz
	1070	UML_TEST(block, IREG(1), IMM(VTLB_FLAG_VALID)); // test i1,VTLB_FLAG_VALID
	1071	UML_EXHc(block, IF_Z, mips3->impstate->exception[EXCEPTION_TLBLOAD], IREG(0)); // exh exception[TLBLOAD],i0,z
1034	1072	UML_EXH(block, mips3->impstate->exception[EXCEPTION_TLBLOAD_FILL], IREG(0)); // exh exception[TLBLOAD_FILL],i0
1035	1073	UML_LABEL(block, 1); // 1:
1036	1074	save_fast_iregs(block);
r2864	r2865
1186	1224
1187	1225	/* general case: assume paging and perform a translation */
1188	1226	UML_SHR(block, IREG(3), IREG(0), IMM(12)); // shr i3,i0,12
1189		UML_LOAD(block, IREG(3), mips3->tlb_table, IREG(3), DWORD); // load i3,[tlb_table],i3,dword
1190		UML_TEST(block, IREG(3), IMM(iswrite ? TLB_DIRTY : TLB_VALID)); // test i3,iswrite ? TLB_DIRTY : TLB_VALID
	1227	UML_LOAD(block, IREG(3), (void *)vtlb_table(mips3->vtlb), IREG(3), DWORD); // load i3,[vtlb_table],i3,dword
	1228	UML_TEST(block, IREG(3), IMM(iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED));// test i3,iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED
1191	1229	UML_JMPc(block, IF_Z, tlbmiss = label++); // jmp tlbmiss,z
1192	1230	UML_ROLINS(block, IREG(0), IREG(3), IMM(0), IMM(0xfffff000)); // rolins i0,i3,0,0xfffff000
1193	1231
r2864	r2865
1342	1380	UML_LABEL(block, tlbmiss); // tlbmiss:
1343	1381	if (iswrite)
1344	1382	{
1345		UML_TEST(block, IREG(3), IMM(TLB_VALID)); // test i3,TLB_VALID
	1383	UML_TEST(block, IREG(3), IMM(VTLB_READ_ALLOWED)); // test i3,VTLB_READ_ALLOWED
1346	1384	UML_EXHc(block, IF_NZ, mips3->impstate->exception[EXCEPTION_TLBMOD], IREG(0));
1347	1385	// exh tlbmod,i0,nz
1348	1386	}
1349		UML_TEST(block, IREG(3), IMM(TLB_PRESENT)); // test i3,TLB_PRESENT
1350		UML_EXHc(block, IF_NZ, exception_tlb, IREG(0)); // exh tlb,i0,nz
	1387	UML_TEST(block, IREG(3), IMM(VTLB_FLAG_VALID)); // test i3,VTLB_FLAG_VALID
	1388	UML_EXHc(block, IF_Z, exception_tlb, IREG(0)); // exh tlb,i0,z
1351	1389	UML_EXH(block, exception_tlbfill, IREG(0)); // exh tlbfill,i0
1352	1390	}
1353	1391
r2864	r2865
1547	1585	/* validate our TLB entry at this PC; if we fail, we need to handle it */
1548	1586	if ((desc->flags & OPFLAG_VALIDATE_TLB) && (desc->pc < 0x80000000 \|\| desc->pc >= 0xc0000000))
1549	1587	{
	1588	const vtlb_entry *tlbtable = vtlb_table(mips3->vtlb);
	1589
1550	1590	/* if we currently have a valid TLB read entry, we just verify */
1551		if (~~mips3->~~tlb_table[desc->pc >> 12] & TLB_VALID)
	1591	if (tlbtable[desc->pc >> 12] & VTLB_FETCH_ALLOWED)
1552	1592	{
1553	1593	if (PRINTF_MMU)
1554	1594	{
1555	1595	UML_MOV(block, MEM(&mips3->impstate->arg0), IMM(desc->pc)); // mov [arg0],desc->pc
1556	1596	UML_CALLC(block, cfunc_printf_debug, "Checking TLB at @ %08X\n"); // callc printf_debug
1557	1597	}
1558		UML_LOAD(block, IREG(0), &mips3->tlb_table[desc->pc >> 12], IMM(0), DWORD);// load i0,tlb_table[desc->pc >> 12],0,dword
1559		UML_CMP(block, IREG(0), IMM(mips3->tlb_table[desc->pc >> 12])); // cmp i0,*tlbentry
	1598	UML_LOAD(block, IREG(0), &tlbtable[desc->pc >> 12], IMM(0), DWORD); // load i0,tlbtable[desc->pc >> 12],0,dword
	1599	UML_CMP(block, IREG(0), IMM(tlbtable[desc->pc >> 12])); // cmp i0,*tlbentry
1560	1600	UML_EXHc(block, IF_NE, mips3->impstate->tlb_mismatch, IMM(0)); // exh tlb_mismatch,0,NE
1561	1601	}
1562	1602
r2864	r2865
1805	1845	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
1806	1846	return TRUE;
1807	1847
	1848	case 0x30: /* LL - MIPS II */
	1849	UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
	1850	UML_CALLH(block, mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh read32
	1851	if (RTREG != 0)
	1852	UML_DSEXT(block, R64(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0
	1853	UML_MOV(block, MEM(&mips3->llbit), IMM(1)); // mov [llbit],1
	1854	if (!in_delay_slot)
	1855	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
	1856	return TRUE;
	1857
1808	1858	case 0x24: /* LBU - MIPS I */
1809	1859	UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
1810	1860	UML_CALLH(block, mips3->impstate->read8[mips3->impstate->mode >> 1]); // callh read8
r2864	r2865
1841	1891	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
1842	1892	return TRUE;
1843	1893
	1894	case 0x34: /* LLD - MIPS III */
	1895	UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
	1896	UML_CALLH(block, mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh read64
	1897	if (RTREG != 0)
	1898	UML_DMOV(block, R64(RTREG), IREG(0)); // dmov <rtreg>,i0
	1899	UML_MOV(block, MEM(&mips3->llbit), IMM(1)); // mov [llbit],1
	1900	if (!in_delay_slot)
	1901	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
	1902	return TRUE;
	1903
1844	1904	case 0x22: /* LWL - MIPS I */
1845	1905	UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
1846	1906	UML_SHL(block, IREG(1), IREG(0), IMM(3)); // shl i1,i0,3
r2864	r2865
1978	2038	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
1979	2039	return TRUE;
1980	2040
	2041	case 0x38: /* SC - MIPS II */
	2042	UML_CMP(block, MEM(&mips3->llbit), IMM(0)); // cmp [llbit],0
	2043	UML_JMPc(block, IF_E, skip = compiler->labelnum++); // je skip
	2044	UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
	2045	UML_MOV(block, IREG(1), R32(RTREG)); // mov i1,<rtreg>
	2046	UML_CALLH(block, mips3->impstate->write32[mips3->impstate->mode >> 1]); // callh write32
	2047	UML_LABEL(block, skip); // skip:
	2048	UML_DSEXT(block, R64(RTREG), MEM(&mips3->llbit), DWORD); // dsext <rtreg>,[llbit],dword
	2049	if (!in_delay_slot)
	2050	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
	2051	return TRUE;
	2052
1981	2053	case 0x3f: /* SD - MIPS III */
1982	2054	UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
1983	2055	UML_DMOV(block, IREG(1), R64(RTREG)); // dmov i1,<rtreg>
r2864	r2865
1986	2058	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
1987	2059	return TRUE;
1988	2060
	2061	case 0x3c: /* SCD - MIPS III */
	2062	UML_CMP(block, MEM(&mips3->llbit), IMM(0)); // cmp [llbit],0
	2063	UML_JMPc(block, IF_E, skip = compiler->labelnum++); // je skip
	2064	UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
	2065	UML_DMOV(block, IREG(1), R64(RTREG)); // dmov i1,<rtreg>
	2066	UML_CALLH(block, mips3->impstate->write64[mips3->impstate->mode >> 1]); // callh write64
	2067	UML_LABEL(block, skip); // skip:
	2068	UML_DSEXT(block, R64(RTREG), MEM(&mips3->llbit), DWORD); // dsext <rtreg>,[llbit],dword
	2069	if (!in_delay_slot)
	2070	generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
	2071	return TRUE;
	2072
1989	2073	case 0x2a: /* SWL - MIPS I */
1990	2074	UML_ADD(block, IREG(0), R32(RSREG), IMM(SIMMVAL)); // add i0,<rsreg>,SIMMVAL
1991	2075	UML_SHL(block, IREG(3), IREG(0), IMM(3)); // shl i3,i0,3
r2864	r2865
2104	2188
2105	2189	/* ----- unimplemented/illegal instructions ----- */
2106	2190
2107		// case 0x30: /* LL - MIPS II */ logerror("mips3 Unhandled op: LL\n"); break;
2108		// case 0x34: /* LLD - MIPS III */ logerror("mips3 Unhandled op: LLD\n"); break;
2109		// case 0x38: /* SC - MIPS II */ logerror("mips3 Unhandled op: SC\n"); break;
2110		// case 0x3c: /* SCD - MIPS III */ logerror("mips3 Unhandled op: SCD\n"); break;
2111	2191	// default: /* ??? */ invalid_instruction(op); break;
2112	2192	}
2113	2193
r2864	r2865
2698	2778	UML_MOV(block, CPR032(reg), IREG(0)); // mov cpr0[reg],i0
2699	2779	UML_TEST(block, IREG(1), IMM(0xff)); // test i1,0xff
2700	2780	UML_JMPc(block, IF_Z, link = compiler->labelnum++); // jmp link,z
2701		UML_CALLC(block, mips3com_unmap_tlb_entries, mips3); // callc mips3com_unmap_tlb_entries
2702		UML_CALLC(block, mips3com_map_tlb_entries, mips3); // callc mips3com_map_tlb_entries
	2781	UML_CALLC(block, mips3com_asid_changed, mips3); // callc mips3com_asid_changed
2703	2782	UML_LABEL(block, link); // link:
2704	2783	return TRUE;
2705	2784
r2864	r2865
2844	2923	return TRUE;
2845	2924
2846	2925	case 0x18: /* ERET */
	2926	UML_MOV(block, MEM(&mips3->llbit), IMM(0)); // mov [llbit],0
2847	2927	UML_MOV(block, IREG(0), CPR032(COP0_Status)); // mov i0,[Status]
2848	2928	UML_TEST(block, IREG(0), IMM(SR_ERL)); // test i0,SR_ERL
2849	2929	UML_JMPc(block, IF_NZ, skip = compiler->labelnum++); // jmp skip,nz

src/emu/cpu/mips/mips3com.c
r2864	r2865
13	13	DEBUGGING
14	14	***************************************************************************/
15	15
16		#define PRINTF_TLB (1)
	16	#define PRINTF_TLB (0)
17	17
18	18
19	19
r2864	r2865
26	26	static UINT32 compute_config_register(const mips3_state *mips);
27	27	static UINT32 compute_prid_register(const mips3_state *mips);
28	28
29		static void tlb_write_common(mips3_state *mips, int index);
30		static void tlb_entry_log_half(mips3_tlb_entry *tlbent, int index, int which);
	29	static void tlb_map_entry(mips3_state *mips, int tlbindex);
	30	static void tlb_write_common(mips3_state *mips, int tlbindex);
	31	static void tlb_entry_log_half(mips3_tlb_entry *entry, int tlbindex, int which);
31	32
32	33
33	34
34	35	/***************************************************************************
	36	INLINE FUNCTIONS
	37	***************************************************************************/
	38
	39	/*-------------------------------------------------
	40	tlb_entry_matches_asid - TRUE if the given
	41	TLB entry matches the provided ASID
	42	-------------------------------------------------*/
	43
	44	INLINE int tlb_entry_matches_asid(const mips3_tlb_entry *entry, UINT8 asid)
	45	{
	46	return (entry->entry_hi & 0xff) == asid;
	47	}
	48
	49
	50	/*-------------------------------------------------
	51	tlb_entry_is_global - TRUE if the given
	52	TLB entry is global
	53	-------------------------------------------------*/
	54
	55	INLINE int tlb_entry_is_global(const mips3_tlb_entry *entry)
	56	{
	57	return (entry->entry_lo[0] & entry->entry_lo[1] & TLB_GLOBAL);
	58	}
	59
	60
	61
	62	/***************************************************************************
35	63	INITIALIZATION AND SHUTDOWN
36	64	***************************************************************************/
37	65
r2864	r2865
40	68	structure based on the configured type
41	69	-------------------------------------------------*/
42	70
43		si~~ze_t~~ mips3com_init(mips3_state mips, mips3_flavor flavor, int bigendian, int index, int clock, const mips3_config config, int (irqcallback)(int)~~, void memory~~)
	71	void mips3com_init(mips3_state mips, mips3_flavor flavor, int bigendian, int index, int clock, const mips3_config config, int (*irqcallback)(int))
44	72	{
45		int tlbindex;
46
47		/* if no memory, return the amount needed */
48		if (memory == NULL)
49		return config->icache + config->dcache + (sizeof(mips->tlb_table[0]) * (1 << (MIPS3_MAX_PADDR_SHIFT - MIPS3_MIN_PAGE_SHIFT)));
50
51	73	/* initialize based on the config */
52	74	memset(mips, 0, sizeof(*mips));
53	75	mips->flavor = flavor;
r2864	r2865
61	83	/* set up the endianness */
62	84	mips->memory = *memory_get_accessors(ADDRESS_SPACE_PROGRAM, 32, mips->bigendian ? CPU_IS_BE : CPU_IS_LE);
63	85
64		/* allocate memory */
65		mips->icache = memory;
66		mips->dcache = (void )((UINT8 )memory + config->icache);
67		mips->tlb_table = (void )((UINT8 )memory + config->dcache);
	86	/* allocate the virtual TLB */
	87	mips->vtlb = vtlb_alloc(cpu_getactivecpu(), ADDRESS_SPACE_PROGRAM, 2 * MIPS3_TLB_ENTRIES + 2, 0);
68	88
69		/* initialize the TLB state */
70		for (tlbindex = 0; tlbindex < ARRAY_LENGTH(mips->tlb); tlbindex++)
71		{
72		mips3_tlb_entry *tlbent = &mips->tlb[tlbindex];
73		tlbent->page_mask = 0;
74		tlbent->entry_hi = 0xffffffff;
75		tlbent->entry_lo[0] = 0xfffffff8;
76		tlbent->entry_lo[1] = 0xfffffff8;
77		}
78
79	89	/* allocate a timer for the compare interrupt */
80	90	mips->compare_int_timer = timer_alloc(compare_int_callback, NULL);
81	91
82	92	/* reset the state */
83	93	mips3com_reset(mips);
84		return 0;
85	94	}
86	95
87	96
88	97	/*-------------------------------------------------
	98	mips3com_exit - common cleanup/exit
	99	-------------------------------------------------*/
	100
	101	void mips3com_exit(mips3_state *mips)
	102	{
	103	if (mips->vtlb != NULL)
	104	vtlb_free(mips->vtlb);
	105	}
	106
	107
	108	/*-------------------------------------------------
89	109	mips3com_reset - reset the state of all the
90	110	registers
91	111	-------------------------------------------------*/
92	112
93	113	void mips3com_reset(mips3_state *mips)
94	114	{
	115	int tlbindex;
	116
95	117	/* initialize the state */
96	118	mips->pc = 0xbfc00000;
97	119	mips->cpr[0][COP0_Status] = SR_BEV \| SR_ERL;
r2864	r2865
102	124	mips->cpr[0][COP0_PRId] = compute_prid_register(mips);
103	125	mips->count_zero_time = activecpu_gettotalcycles();
104	126
105		/* recompute the TLB table */
106		mips3com_recompute_tlb_table(mips);
	127	/* initialize the TLB state */
	128	for (tlbindex = 0; tlbindex < ARRAY_LENGTH(mips->tlb); tlbindex++)
	129	{
	130	mips3_tlb_entry *entry = &mips->tlb[tlbindex];
	131	entry->page_mask = 0;
	132	entry->entry_hi = 0xffffffff;
	133	entry->entry_lo[0] = 0xfffffff8;
	134	entry->entry_lo[1] = 0xfffffff8;
	135	vtlb_load(mips->vtlb, 2 * tlbindex + 0, 0, 0, 0);
	136	vtlb_load(mips->vtlb, 2 * tlbindex + 1, 0, 0, 0);
	137	}
	138
	139	/* load the fixed TLB range */
	140	vtlb_load(mips->vtlb, 2 * MIPS3_TLB_ENTRIES + 0, (0xa0000000 - 0x80000000) >> MIPS3_MIN_PAGE_SHIFT, 0x80000000, 0x00000000 \| VTLB_READ_ALLOWED \| VTLB_WRITE_ALLOWED \| VTLB_FETCH_ALLOWED \| VTLB_FLAG_VALID);
	141	vtlb_load(mips->vtlb, 2 * MIPS3_TLB_ENTRIES + 1, (0xc0000000 - 0xa0000000) >> MIPS3_MIN_PAGE_SHIFT, 0xa0000000, 0x00000000 \| VTLB_READ_ALLOWED \| VTLB_WRITE_ALLOWED \| VTLB_FETCH_ALLOWED \| VTLB_FLAG_VALID);
107	142	}
108	143
109	144
r2864	r2865
156	191	***************************************************************************/
157	192
158	193	/*-------------------------------------------------
159		mips3com_map_tlb_entries - map entries from the
160		TLB into the tlb_table
	194	mips3com_asid_changed - remap all non-global
	195	TLB entries
161	196	-------------------------------------------------*/
162	197
163		void mips3com_map_~~tlb_e~~n~~tri~~es(mips3_state *mips)
	198	void mips3com_asid_changed(mips3_state *mips)
164	199	{
165		int valid_asid = mips->cpr[0][COP0_EntryHi] & 0xff;
166		int index;
	200	int tlbindex;
167	201
168		/* iterate over all TLB entries */
169		for (index = 0; index < ARRAY_LENGTH(mips->tlb); index++)
170		{
171		mips3_tlb_entry *tlbent = &mips->tlb[index];
172
173		/* only process if the ASID matches or if global */
174		if (valid_asid == (tlbent->entry_hi & 0xff) \|\| ((tlbent->entry_lo[0] & tlbent->entry_lo[1]) & TLB_GLOBAL))
175		{
176		UINT32 count = (tlbent->page_mask >> 13) & 0x00fff;
177		UINT32 vpn = ((tlbent->entry_hi >> 13) & 0x07ffffff) << 1;
178		int which, i;
179
180		/* ignore if the virtual address is beyond 32 bits */
181		if (vpn < (1 << (MIPS3_MAX_PADDR_SHIFT - MIPS3_MIN_PAGE_SHIFT)))
182
183		/* loop over both the even and odd pages */
184		for (which = 0; which < 2; which++)
185		{
186		UINT64 lo = tlbent->entry_lo[which];
187		UINT32 pfn = (lo >> 6) & 0x00ffffff;
188		UINT32 wp = (lo & 7) \| TLB_PRESENT;
189
190		/* ensure that if the valid bit is clear, the dirty bit is as well */
191		/* this way we can always test dirty for writes, and valid for reads */
192		if (!(wp & TLB_VALID))
193		wp &= ~TLB_DIRTY;
194
195		for (i = 0; i <= count; i++, vpn++, pfn++)
196		if (vpn < 0x80000 \|\| vpn >= 0xc0000)
197		mips->tlb_table[vpn] = (pfn << MIPS3_MIN_PAGE_SHIFT) \| wp;
198		}
199		}
200		}
	202	/* iterate over all non-global TLB entries and remap them */
	203	for (tlbindex = 0; tlbindex < ARRAY_LENGTH(mips->tlb); tlbindex++)
	204	if (!tlb_entry_is_global(&mips->tlb[tlbindex]))
	205	tlb_map_entry(mips, tlbindex);
201	206	}
202	207
203	208
204	209	/*-------------------------------------------------
205		mips3com_unmap_tlb_entries - unmap entries from
206		the TLB into the tlb_table
207		-------------------------------------------------*/
208
209		void mips3com_unmap_tlb_entries(mips3_state *mips)
210		{
211		int index;
212
213		/* iterate over all TLB entries */
214		for (index = 0; index < ARRAY_LENGTH(mips->tlb); index++)
215		{
216		mips3_tlb_entry *tlbent = &mips->tlb[index];
217		UINT32 count = (tlbent->page_mask >> 13) & 0x00fff;
218		UINT32 vpn = ((tlbent->entry_hi >> 13) & 0x07ffffff) << 1;
219		int which, i;
220
221		/* ignore if the virtual address is beyond 32 bits */
222		if (vpn < (1 << (MIPS3_MAX_PADDR_SHIFT - MIPS3_MIN_PAGE_SHIFT)))
223
224		/* loop over both the even and odd pages */
225		for (which = 0; which < 2; which++)
226		for (i = 0; i <= count; i++, vpn++)
227		if (vpn < 0x80000 \|\| vpn >= 0xc0000)
228		mips->tlb_table[vpn] = 0;
229		}
230		}
231
232
233		/*-------------------------------------------------
234		mips3com_recompute_tlb_table - recompute the TLB
235		table from scratch
236		-------------------------------------------------*/
237
238		void mips3com_recompute_tlb_table(mips3_state *mips)
239		{
240		UINT32 addr;
241
242		/* map in the hard-coded spaces */
243		for (addr = 0x80000000; addr < 0xc0000000; addr += MIPS3_MIN_PAGE_SIZE)
244		mips->tlb_table[addr >> MIPS3_MIN_PAGE_SHIFT] = (addr & 0x1ffff000) \| TLB_PRESENT \| TLB_DIRTY \| TLB_VALID \| TLB_GLOBAL;
245
246		/* reset everything else to unmapped */
247		memset(&mips->tlb_table[0x00000000 >> MIPS3_MIN_PAGE_SHIFT], 0, sizeof(mips->tlb_table[0]) * (0x80000000 >> MIPS3_MIN_PAGE_SHIFT));
248		memset(&mips->tlb_table[0xc0000000 >> MIPS3_MIN_PAGE_SHIFT], 0, sizeof(mips->tlb_table[0]) * (0x40000000 >> MIPS3_MIN_PAGE_SHIFT));
249
250		/* remap all the entries in the TLB */
251		mips3com_map_tlb_entries(mips);
252		}
253
254
255		/*-------------------------------------------------
256	210	mips3com_translate_address - translate an address
257	211	from logical to physical
258	212	-------------------------------------------------*/
r2864	r2865
262	216	/* only applies to the program address space */
263	217	if (space == ADDRESS_SPACE_PROGRAM)
264	218	{
265		UINT32 result = mips->tlb_table[*address >> MIPS3_MIN_PAGE_SHIFT];
266		if (!(result & TLB_PRESENT) \|\| !(result & TLB_VALID))
	219	const vtlb_entry *table = vtlb_table(mips->vtlb);
	220	vtlb_entry entry = table[*address >> MIPS3_MIN_PAGE_SHIFT];
	221	if ((entry & (1 << (intention & (TRANSLATE_TYPE_MASK \| TRANSLATE_USER_MASK)))) == 0)
267	222	return FALSE;
268		address = (re~~sul~~t & ~MIPS3_MIN_PAGE_MASK) \| (address & MIPS3_MIN_PAGE_MASK);
	223	address = (entry & ~MIPS3_MIN_PAGE_MASK) \| (address & MIPS3_MIN_PAGE_MASK);
269	224	}
270	225	return TRUE;
271	226	}
r2864	r2865
277	232
278	233	void mips3com_tlbr(mips3_state *mips)
279	234	{
280		UINT32 index = mips->cpr[0][COP0_Index] & 0x3f;
	235	UINT32 tlbindex = mips->cpr[0][COP0_Index] & 0x3f;
281	236
282	237	/* only handle entries within the TLB */
283		if (index < ARRAY_LENGTH(mips->tlb))
	238	if (tlbindex < ARRAY_LENGTH(mips->tlb))
284	239	{
285		mips3_tlb_entry *~~tlb~~ent = &mips->tlb[index];
	240	mips3_tlb_entry *entry = &mips->tlb[tlbindex];
286	241
287	242	/* copy data from the TLB entry into the COP0 registers */
288		mips->cpr[0][COP0_PageMask] = tlbent->page_mask;
289		mips->cpr[0][COP0_EntryHi] = tlbent->entry_hi;
290		mips->cpr[0][COP0_EntryLo0] = tlbent->entry_lo[0];
291		mips->cpr[0][COP0_EntryLo1] = tlbent->entry_lo[1];
	243	mips->cpr[0][COP0_PageMask] = entry->page_mask;
	244	mips->cpr[0][COP0_EntryHi] = entry->entry_hi;
	245	mips->cpr[0][COP0_EntryLo0] = entry->entry_lo[0];
	246	mips->cpr[0][COP0_EntryLo1] = entry->entry_lo[1];
292	247	}
293	248	}
294	249
r2864	r2865
312	267	{
313	268	UINT32 wired = mips->cpr[0][COP0_Wired] & 0x3f;
314	269	UINT32 unwired = ARRAY_LENGTH(mips->tlb) - wired;
315		UINT32 index = ARRAY_LENGTH(mips->tlb) - 1;
	270	UINT32 tlbindex = ARRAY_LENGTH(mips->tlb) - 1;
316	271
317	272	/* "random" is based off of the current cycle counting through the non-wired pages */
318	273	if (unwired > 0)
319		index = ((activecpu_gettotalcycles() - mips->count_zero_time) % unwired + wired) & 0x3f;
	274	tlbindex = ((activecpu_gettotalcycles() - mips->count_zero_time) % unwired + wired) & 0x3f;
320	275
321		/* use the common handler to write to this index */
322		tlb_write_common(mips, index);
	276	/* use the common handler to write to this tlbindex */
	277	tlb_write_common(mips, tlbindex);
323	278	}
324	279
325	280
r2864	r2865
329	284
330	285	void mips3com_tlbp(mips3_state *mips)
331	286	{
332		UINT32 index;
	287	UINT32 tlbindex;
333	288	UINT64 vpn;
334	289
335	290	/* iterate over TLB entries */
336		for (index = 0; index < ARRAY_LENGTH(mips->tlb); index++)
	291	for (tlbindex = 0; tlbindex < ARRAY_LENGTH(mips->tlb); tlbindex++)
337	292	{
338		mips3_tlb_entry *tlbent = &mips->tlb[index];
339		UINT64 mask = ~((tlbent->page_mask >> 13) & 0xfff) << 13;
	293	mips3_tlb_entry *entry = &mips->tlb[tlbindex];
	294	UINT64 mask = ~((entry->page_mask >> 13) & 0xfff) << 13;
340	295
341	296	/* if the relevant bits of EntryHi match the relevant bits of the TLB */
342		if ((~~tlb~~ent->entry_hi & mask) == (mips->cpr[0][COP0_EntryHi] & mask))
	297	if ((entry->entry_hi & mask) == (mips->cpr[0][COP0_EntryHi] & mask))
343	298
344	299	/* and if we are either global or matching the current ASID, then stop */
345		if ((~~tlb~~ent->entry_hi & 0xff) == (mips->cpr[0][COP0_EntryHi] & 0xff) \|\| ((~~tlb~~ent->entry_lo[0] & ~~tlb~~ent->entry_lo[1]) & TLB_GLOBAL))
	300	if ((entry->entry_hi & 0xff) == (mips->cpr[0][COP0_EntryHi] & 0xff) \|\| ((entry->entry_lo[0] & entry->entry_lo[1]) & TLB_GLOBAL))
346	301	break;
347	302	}
348	303
349	304	/* validate that our tlb_table was in sync */
350	305	vpn = ((mips->cpr[0][COP0_EntryHi] >> 13) & 0x07ffffff) << 1;
351		if (index != ARRAY_LENGTH(mips->tlb))
352		{
353		assert(mips->tlb_table[vpn & 0xfffff] & TLB_PRESENT);
354		mips->cpr[0][COP0_Index] = index;
355		}
	306	if (tlbindex != ARRAY_LENGTH(mips->tlb))
	307	mips->cpr[0][COP0_Index] = tlbindex;
356	308	else
357		{
358		assert(!(mips->tlb_table[vpn & 0xfffff] & TLB_PRESENT));
359	309	mips->cpr[0][COP0_Index] = 0x80000000;
360		}
361	310	}
362	311
363	312
r2864	r2865
830	779
831	780
832	781	/*-------------------------------------------------
	782	tlb_map_entry - map a single TLB
	783	entry
	784	-------------------------------------------------*/
	785
	786	static void tlb_map_entry(mips3_state *mips, int tlbindex)
	787	{
	788	int current_asid = mips->cpr[0][COP0_EntryHi] & 0xff;
	789	mips3_tlb_entry *entry = &mips->tlb[tlbindex];
	790	UINT32 count, vpn;
	791	int which;
	792
	793	/* the ASID doesn't match the current ASID, and if the page isn't global, unmap it from the TLB */
	794	if (!tlb_entry_matches_asid(entry, current_asid) && !tlb_entry_is_global(entry))
	795	{
	796	vtlb_load(mips->vtlb, 2 * tlbindex + 0, 0, 0, 0);
	797	vtlb_load(mips->vtlb, 2 * tlbindex + 1, 0, 0, 0);
	798	return;
	799	}
	800
	801	/* extract the VPN index; ignore if the virtual address is beyond 32 bits */
	802	vpn = ((entry->entry_hi >> 13) & 0x07ffffff) << 1;
	803	if (vpn >= (1 << (MIPS3_MAX_PADDR_SHIFT - MIPS3_MIN_PAGE_SHIFT)))
	804	{
	805	vtlb_load(mips->vtlb, 2 * tlbindex + 0, 0, 0, 0);
	806	vtlb_load(mips->vtlb, 2 * tlbindex + 1, 0, 0, 0);
	807	return;
	808	}
	809
	810	/* get the number of pages from the page mask */
	811	count = ((entry->page_mask >> 13) & 0x00fff) + 1;
	812
	813	/* loop over both the even and odd pages */
	814	for (which = 0; which < 2; which++)
	815	{
	816	UINT32 effvpn = vpn + count * which;
	817	UINT64 lo = entry->entry_lo[which];
	818	UINT32 pfn = (lo >> 6) & 0x00ffffff;
	819	UINT32 flags = 0;
	820
	821	/* valid? */
	822	if ((lo & 2) != 0)
	823	{
	824	flags \|= VTLB_FLAG_VALID \| VTLB_READ_ALLOWED \| VTLB_FETCH_ALLOWED;
	825
	826	/* writable? */
	827	if ((lo & 4) != 0)
	828	flags \|= VTLB_WRITE_ALLOWED;
	829
	830	/* mirror the flags for user mode if the VPN is in user space */
	831	if (effvpn < (0x80000000 >> MIPS3_MIN_PAGE_SHIFT))
	832	flags \|= (flags << 4) & (VTLB_USER_READ_ALLOWED \| VTLB_USER_WRITE_ALLOWED \| VTLB_USER_FETCH_ALLOWED);
	833	}
	834
	835	/* load the virtual TLB with the corresponding entries */
	836	if ((effvpn + count) <= (0x80000000 >> MIPS3_MIN_PAGE_SHIFT) \|\| effvpn >= (0xc0000000 >> MIPS3_MIN_PAGE_SHIFT))
	837	vtlb_load(mips->vtlb, 2 * tlbindex + which, count, effvpn << MIPS3_MIN_PAGE_SHIFT, (pfn << MIPS3_MIN_PAGE_SHIFT) \| flags);
	838	}
	839	}
	840
	841
	842	/*-------------------------------------------------
833	843	tlb_write_common - common routine for writing
834	844	a TLB entry
835	845	-------------------------------------------------*/
836	846
837		static void tlb_write_common(mips3_state *mips, int index)
	847	static void tlb_write_common(mips3_state *mips, int tlbindex)
838	848	{
839	849	/* only handle entries within the TLB */
840		if (index < ARRAY_LENGTH(mips->tlb))
	850	if (tlbindex < ARRAY_LENGTH(mips->tlb))
841	851	{
842		mips3_tlb_entry *~~tlb~~ent = &mips->tlb[index];
	852	mips3_tlb_entry *entry = &mips->tlb[tlbindex];
843	853
844		/* unmap what we have */
845		mips3com_unmap_tlb_entries(mips);
846
847	854	/* fill in the new TLB entry from the COP0 registers */
848		tlbent->page_mask = mips->cpr[0][COP0_PageMask];
849		tlbent->entry_hi = mips->cpr[0][COP0_EntryHi] & ~(tlbent->page_mask & U64(0x0000000001ffe000));
850		tlbent->entry_lo[0] = mips->cpr[0][COP0_EntryLo0];
851		tlbent->entry_lo[1] = mips->cpr[0][COP0_EntryLo1];
	855	entry->page_mask = mips->cpr[0][COP0_PageMask];
	856	entry->entry_hi = mips->cpr[0][COP0_EntryHi] & ~(entry->page_mask & U64(0x0000000001ffe000));
	857	entry->entry_lo[0] = mips->cpr[0][COP0_EntryLo0];
	858	entry->entry_lo[1] = mips->cpr[0][COP0_EntryLo1];
852	859
853		/* remap the TLB */
854		mips3com_map_tlb_entries(mips);
	860	/* remap this TLB entry */
	861	tlb_map_entry(mips, tlbindex);
855	862
856	863	/* log the two halves once they are in */
857		tlb_entry_log_half(tlbent, index, 0);
858		tlb_entry_log_half(tlbent, index, 1);
	864	tlb_entry_log_half(entry, tlbindex, 0);
	865	tlb_entry_log_half(entry, tlbindex, 1);
859	866	}
860	867	}
861	868
r2864	r2865
865	872	entry
866	873	-------------------------------------------------*/
867	874
868		static void tlb_entry_log_half(mips3_tlb_entry *~~tlb~~ent, int index, int which)
	875	static void tlb_entry_log_half(mips3_tlb_entry *entry, int tlbindex, int which)
869	876	{
870	877	#if PRINTF_TLB
871		UINT64 hi = tlbent->entry_hi;
872		UINT64 lo = tlbent->entry_lo[which];
	878	UINT64 hi = entry->entry_hi;
	879	UINT64 lo = entry->entry_lo[which];
873	880	UINT32 vpn = (((hi >> 13) & 0x07ffffff) << 1);
874	881	UINT32 asid = hi & 0xff;
875	882	UINT32 r = (hi >> 62) & 3;
876	883	UINT32 pfn = (lo >> 6) & 0x00ffffff;
877	884	UINT32 c = (lo >> 3) & 7;
878		UINT32 pagesize = (((~~tlb~~ent->page_mask >> 13) & 0xfff) + 1) << MIPS3_MIN_PAGE_SHIFT;
	885	UINT32 pagesize = (((entry->page_mask >> 13) & 0xfff) + 1) << MIPS3_MIN_PAGE_SHIFT;
879	886	UINT64 vaddr = (UINT64)vpn * MIPS3_MIN_PAGE_SIZE;
880	887	UINT64 paddr = (UINT64)pfn * MIPS3_MIN_PAGE_SIZE;
881	888
882	889	vaddr += pagesize * which;
883	890
884		mame_printf_debug("index=%08X pagesize=%08X vaddr=%08X%08X paddr=%08X%08X asid=%02X r=%X c=%X dvg=%c%c%c\n",
885		index, pagesize, (UINT32)(vaddr >> 32), (UINT32)vaddr, (UINT32)(paddr >> 32), (UINT32)paddr,
	891	printf("index=%08X pagesize=%08X vaddr=%08X%08X paddr=%08X%08X asid=%02X r=%X c=%X dvg=%c%c%c\n",
	892	tlbindex, pagesize, (UINT32)(vaddr >> 32), (UINT32)vaddr, (UINT32)(paddr >> 32), (UINT32)paddr,
886	893	asid, r, c, (lo & 4) ? 'd' : '.', (lo & 2) ? 'v' : '.', (lo & 1) ? 'g' : '.');
887	894	#endif
888	895	}

src/emu/cpu/mips/mips3.c
r2864	r2865
556	556	if ((mips3.core.cpr[0][idx] ^ val) & 0xff)
557	557	{
558	558	mips3.core.cpr[0][idx] = val;
559		mips3com_unmap_tlb_entries(&mips3.core);
560		mips3com_map_tlb_entries(&mips3.core);
	559	mips3com_asid_changed(&mips3.core);
561	560	}
562	561	mips3.core.cpr[0][idx] = val;
563	562	break;

src/emu/cpu/drcbex86.c
r2864	r2865
169	169	x86_entry_point_func entry; /* entry point */
170	170	x86code * exit; /* exit point */
171	171	x86code * nocode; /* nocode handler */
	172	x86code * save; /* save handler */
	173	x86code * restore; /* restore handler */
172	174
173	175	UINT32 * reglo[REG_MAX]; /* pointer to low part of data for each register */
174	176	UINT32 * reghi[REG_MAX]; /* pointer to high part of data for each register */
r2864	r2865
184	186	UINT64 reshi; /* extended high result */
185	187
186	188	x86log_context * log; /* logging */
	189	UINT8 logged_common; /* logged common code already? */
187	190	};
188	191
189	192
r2864	r2865
205	208	static void fixup_label(void *parameter, drccodeptr labelcodeptr);
206	209
207	210	/* miscellaneous functions */
208		static void dmulu(UINT64 dstlo, UINT64 dsthi, UINT64 src1, UINT64 src2);
209		static void dmuls(UINT64 dstlo, UINT64 dsthi, INT64 src1, INT64 src2);
210		static void ddivu(UINT64 dstlo, UINT64 dsthi, UINT64 src1, UINT64 src2);
211		static void ddivs(UINT64 dstlo, UINT64 dsthi, INT64 src1, INT64 src2);
	211	static int dmulu(UINT64 dstlo, UINT64 dsthi, UINT64 src1, UINT64 src2, int flags);
	212	static int dmuls(UINT64 dstlo, UINT64 dsthi, INT64 src1, INT64 src2, int flags);
	213	static int ddivu(UINT64 dstlo, UINT64 dsthi, UINT64 src1, UINT64 src2);
	214	static int ddivs(UINT64 dstlo, UINT64 dsthi, INT64 src1, INT64 src2);
212	215
213	216
214	217
r2864	r2865
619	622	{
620	623	UINT32 (*cpuid_ecx_stub)(void);
621	624	x86code **dst;
	625	int regnum;
622	626
623	627	/* output a note to the log */
624	628	if (drcbe->log != NULL)
r2864	r2865
654	658	emit_mov_m32_r32(dst, MABS(&drcbe->stacksave), REG_ESP); // mov [stacksave],esp
655	659	emit_fstcw_m16(dst, MABS(&drcbe->fpumode)); // fstcw [fpumode]
656	660	emit_jmp_r32(dst, REG_EAX); // jmp eax
657		if (drcbe->log != NULL)
	661	if (drcbe->log != NULL && !drcbe->logged_common)
658	662	x86log_disasm_code_range(drcbe->log, "entry_point", (x86code )drcbe->entry, dst);
659	663
660	664	/* generate an exit point */
r2864	r2865
667	671	emit_pop_r32(dst, REG_ESI); // pop esi
668	672	emit_pop_r32(dst, REG_EBX); // pop ebx
669	673	emit_ret(dst); // ret
670		if (drcbe->log != NULL)
	674	if (drcbe->log != NULL && !drcbe->logged_common)
671	675	x86log_disasm_code_range(drcbe->log, "exit_point", drcbe->exit, *dst);
672	676
673	677	/* generate a no code point */
674	678	drcbe->nocode = *dst;
675	679	emit_ret(dst); // ret
676		if (drcbe->log != NULL)
	680	if (drcbe->log != NULL && !drcbe->logged_common)
677	681	x86log_disasm_code_range(drcbe->log, "nocode", drcbe->nocode, *dst);
678	682
	683	/* generate a save subroutine */
	684	drcbe->save = *dst;
	685	emit_pushf(dst); // pushf
	686	emit_pop_r32(dst, REG_EAX); // pop eax
	687	emit_and_r32_imm(dst, REG_EAX, 0x8c5); // and eax,0x8c5
	688	emit_mov_r8_m8(dst, REG_AL, MBD(REG_EAX, flags_map)); // mov al,[flags_map]
	689	emit_mov_m8_r8(dst, MBD(REG_ECX, offsetof(drcuml_machine_state, flags)), REG_AL); // mov state->flags,al
	690	emit_mov_r8_m8(dst, REG_AL, MABS(&drcbe->state.fmod)); // mov al,[fmod]
	691	emit_mov_m8_r8(dst, MBD(REG_ECX, offsetof(drcuml_machine_state, fmod)), REG_AL); // mov state->fmod,al
	692	emit_mov_r32_m32(dst, REG_EAX, MABS(&drcbe->state.exp)); // mov eax,[exp]
	693	emit_mov_m32_r32(dst, MBD(REG_ECX, offsetof(drcuml_machine_state, exp)), REG_EAX); // mov state->exp,eax
	694	for (regnum = 0; regnum < ARRAY_LENGTH(drcbe->state.r); regnum++)
	695	{
	696	if (int_register_map[regnum] != 0)
	697	emit_mov_m32_r32(dst, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.l)), int_register_map[regnum]);
	698	else
	699	{
	700	emit_mov_r32_m32(dst, REG_EAX, MABS(&drcbe->state.r[regnum].w.l));
	701	emit_mov_m32_r32(dst, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.l)), REG_EAX);
	702	}
	703	emit_mov_r32_m32(dst, REG_EAX, MABS(&drcbe->state.r[regnum].w.h));
	704	emit_mov_m32_r32(dst, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.h)), REG_EAX);
	705	}
	706	for (regnum = 0; regnum < ARRAY_LENGTH(drcbe->state.f); regnum++)
	707	{
	708	emit_mov_r32_m32(dst, REG_EAX, MABS(&drcbe->state.f[regnum].s.l));
	709	emit_mov_m32_r32(dst, MBD(REG_ECX, offsetof(drcuml_machine_state, f[regnum].s.l)), REG_EAX);
	710	emit_mov_r32_m32(dst, REG_EAX, MABS(&drcbe->state.f[regnum].s.h));
	711	emit_mov_m32_r32(dst, MBD(REG_ECX, offsetof(drcuml_machine_state, f[regnum].s.h)), REG_EAX);
	712	}
	713	emit_ret(dst); // ret
	714	if (drcbe->log != NULL && !drcbe->logged_common)
	715	x86log_disasm_code_range(drcbe->log, "save", drcbe->save, *dst);
	716
	717	/* generate a restore subroutine */
	718	drcbe->restore = *dst;
	719	for (regnum = 0; regnum < ARRAY_LENGTH(drcbe->state.r); regnum++)
	720	{
	721	if (int_register_map[regnum] != 0)
	722	emit_mov_r32_m32(dst, int_register_map[regnum], MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.l)));
	723	else
	724	{
	725	emit_mov_r32_m32(dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.l)));
	726	emit_mov_m32_r32(dst, MABS(&drcbe->state.r[regnum].w.l), REG_EAX);
	727	}
	728	emit_mov_r32_m32(dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.h)));
	729	emit_mov_m32_r32(dst, MABS(&drcbe->state.r[regnum].w.h), REG_EAX);
	730	}
	731	for (regnum = 0; regnum < ARRAY_LENGTH(drcbe->state.f); regnum++)
	732	{
	733	emit_mov_r32_m32(dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, f[regnum].s.l)));
	734	emit_mov_m32_r32(dst, MABS(&drcbe->state.f[regnum].s.l), REG_EAX);
	735	emit_mov_r32_m32(dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, f[regnum].s.h)));
	736	emit_mov_m32_r32(dst, MABS(&drcbe->state.f[regnum].s.h), REG_EAX);
	737	}
	738	emit_movzx_r32_m8(dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, fmod)));// movzx eax,state->fmod
	739	emit_and_r32_imm(dst, REG_EAX, 3); // and eax,3
	740	emit_mov_m8_r8(dst, MABS(&drcbe->state.fmod), REG_AL); // mov [fmod],al
	741	emit_fldcw_m16(dst, MISD(REG_EAX, 2, &fp_control[0])); // fldcw fp_control[eax]
	742	emit_mov_r32_m32(dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, exp))); // mov eax,state->exp
	743	emit_mov_m32_r32(dst, MABS(&drcbe->state.exp), REG_EAX); // mov [exp],eax
	744	emit_movzx_r32_m8(dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, flags)));// movzx eax,state->flags
	745	emit_push_m32(dst, MISD(REG_EAX, 4, flags_unmap)); // push flags_unmap[eax*4]
	746	emit_popf(dst); // popf
	747	emit_ret(dst); // ret
	748	if (drcbe->log != NULL && !drcbe->logged_common)
	749	x86log_disasm_code_range(drcbe->log, "restore", drcbe->restore, *dst);
	750
679	751	/* finish up codegen */
680	752	drccache_end_codegen(drcbe->cache);
	753	drcbe->logged_common = TRUE;
681	754
682	755	/* reset our hash tables */
683	756	drchash_reset(drcbe->hash);
r2864	r2865
3717	3790	static x86code op_save(drcbe_state drcbe, x86code dst, const drcuml_instruction inst)
3718	3791	{
3719	3792	drcuml_parameter dstp;
3720		int regnum;
3721	3793
3722	3794	/* validate instruction */
3723	3795	assert(inst->size == 4);
r2864	r2865
3729	3801
3730	3802	/* copy live state to the destination */
3731	3803	emit_mov_r32_imm(&dst, REG_ECX, dstp.value); // mov ecx,dstp
3732
3733		/* copy flags */
3734		emit_pushf(&dst); // pushf
3735		emit_pop_r32(&dst, REG_EAX); // pop eax
3736		emit_and_r32_imm(&dst, REG_EAX, 0x8c5); // and eax,0x8c5
3737		emit_mov_r8_m8(&dst, REG_AL, MBD(REG_EAX, flags_map)); // mov al,[flags_map]
3738		emit_mov_m8_r8(&dst, MBD(REG_ECX, offsetof(drcuml_machine_state, flags)), REG_AL); // mov state->flags,al
3739
3740		/* copy fmod and exp */
3741		emit_mov_r8_m8(&dst, REG_AL, MABS(&drcbe->state.fmod)); // mov al,[fmod]
3742		emit_mov_m8_r8(&dst, MBD(REG_ECX, offsetof(drcuml_machine_state, fmod)), REG_AL); // mov state->fmod,al
3743		emit_mov_r32_m32(&dst, REG_EAX, MABS(&drcbe->state.exp)); // mov eax,[exp]
3744		emit_mov_m32_r32(&dst, MBD(REG_ECX, offsetof(drcuml_machine_state, exp)), REG_EAX); // mov state->exp,eax
3745
3746		/* copy integer registers */
3747		for (regnum = 0; regnum < ARRAY_LENGTH(drcbe->state.r); regnum++)
3748		{
3749		if (int_register_map[regnum] != 0)
3750		emit_mov_m32_r32(&dst, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.l)), int_register_map[regnum]);
3751		else
3752		{
3753		emit_mov_r32_m32(&dst, REG_EAX, MABS(&drcbe->state.r[regnum].w.l));
3754		emit_mov_m32_r32(&dst, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.l)), REG_EAX);
3755		}
3756		emit_mov_r32_m32(&dst, REG_EAX, MABS(&drcbe->state.r[regnum].w.h));
3757		emit_mov_m32_r32(&dst, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.h)), REG_EAX);
3758		}
3759
3760		/* copy FP registers */
3761		for (regnum = 0; regnum < ARRAY_LENGTH(drcbe->state.f); regnum++)
3762		{
3763		emit_mov_r32_m32(&dst, REG_EAX, MABS(&drcbe->state.f[regnum].s.l));
3764		emit_mov_m32_r32(&dst, MBD(REG_ECX, offsetof(drcuml_machine_state, f[regnum].s.l)), REG_EAX);
3765		emit_mov_r32_m32(&dst, REG_EAX, MABS(&drcbe->state.f[regnum].s.h));
3766		emit_mov_m32_r32(&dst, MBD(REG_ECX, offsetof(drcuml_machine_state, f[regnum].s.h)), REG_EAX);
3767		}
3768
	3804	emit_call(&dst, drcbe->save); // call save
3769	3805	return dst;
3770	3806	}
3771	3807
r2864	r2865
3777	3813	static x86code op_restore(drcbe_state drcbe, x86code dst, const drcuml_instruction inst)
3778	3814	{
3779	3815	drcuml_parameter dstp;
3780		int regnum;
3781	3816
3782	3817	/* validate instruction */
3783	3818	assert(inst->size == 4);
3784	3819	assert_no_condition(inst);
3785		assert_no_flags(inst);
3786	3820
3787	3821	/* normalize parameters */
3788	3822	param_normalize_1(drcbe, inst, &dstp, PTYPE_M);
3789	3823
3790	3824	/* copy live state from the destination */
3791	3825	emit_mov_r32_imm(&dst, REG_ECX, dstp.value); // mov ecx,dstp
3792
3793		/* copy integer registers */
3794		for (regnum = 0; regnum < ARRAY_LENGTH(drcbe->state.r); regnum++)
3795		{
3796		if (int_register_map[regnum] != 0)
3797		emit_mov_r32_m32(&dst, int_register_map[regnum], MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.l)));
3798		else
3799		{
3800		emit_mov_r32_m32(&dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.l)));
3801		emit_mov_m32_r32(&dst, MABS(&drcbe->state.r[regnum].w.l), REG_EAX);
3802		}
3803		emit_mov_r32_m32(&dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, r[regnum].w.h)));
3804		emit_mov_m32_r32(&dst, MABS(&drcbe->state.r[regnum].w.h), REG_EAX);
3805		}
3806
3807		/* copy FP registers */
3808		for (regnum = 0; regnum < ARRAY_LENGTH(drcbe->state.f); regnum++)
3809		{
3810		emit_mov_r32_m32(&dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, f[regnum].s.l)));
3811		emit_mov_m32_r32(&dst, MABS(&drcbe->state.f[regnum].s.l), REG_EAX);
3812		emit_mov_r32_m32(&dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, f[regnum].s.h)));
3813		emit_mov_m32_r32(&dst, MABS(&drcbe->state.f[regnum].s.h), REG_EAX);
3814		}
3815
3816		/* copy fmod and exp */
3817		emit_movzx_r32_m8(&dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, fmod)));// movzx eax,state->fmod
3818		emit_and_r32_imm(&dst, REG_EAX, 3); // and eax,3
3819		emit_mov_m8_r8(&dst, MABS(&drcbe->state.fmod), REG_AL); // mov [fmod],al
3820		emit_fldcw_m16(&dst, MISD(REG_EAX, 2, &fp_control[0])); // fldcw fp_control[eax]
3821		emit_mov_r32_m32(&dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, exp))); // mov eax,state->exp
3822		emit_mov_m32_r32(&dst, MABS(&drcbe->state.exp), REG_EAX); // mov [exp],eax
3823
3824		/* copy flags */
3825		emit_movzx_r32_m8(&dst, REG_EAX, MBD(REG_ECX, offsetof(drcuml_machine_state, flags)));// movzx eax,state->flags
3826		emit_push_m32(&dst, MISD(REG_EAX, 4, flags_unmap)); // push flags_unmap[eax*4]
3827		emit_popf(&dst); // popf
3828
	3826	emit_call(&dst, drcbe->restore); // call restore
3829	3827	return dst;
3830	3828	}
3831	3829
r2864	r2865
4562	4560
4563	4561	/* normalize parameters */
4564	4562	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI, &sizep, PTYPE_I);
4565		assert(srcp.type != DRCUML_PTYPE_IMMEDIATE);
4566	4563
4567	4564	/* pick a target register for the general case */
4568	4565	dstreg = (inst->size == 8) ? REG_EAX : param_select_register(REG_EAX, &dstp, NULL);
r2864	r2865
4773	4770
4774	4771	/* normalize parameters */
4775	4772	param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
4776		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
4777	4773
4778	4774	/* pick a target register for the general case */
4779	4775	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
4892	4888
4893	4889	/* normalize parameters */
4894	4890	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
4895		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
4896	4891
4897	4892	/* pick a target register for the general case */
4898	4893	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5065	5060
5066	5061	static x86code op_mulu(drcbe_state drcbe, x86code dst, const drcuml_instruction inst)
5067	5062	{
	5063	UINT8 zsflags = inst->flags & (DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5064	UINT8 vflag = inst->flags & DRCUML_FLAG_V;
5068	5065	drcuml_parameter dstp, edstp, src1p, src2p;
5069	5066	int compute_hi;
5070	5067
5071	5068	/* validate instruction */
5072	5069	assert(inst->size == 4 \|\| inst->size == 8);
5073	5070	assert_no_condition(inst);
5074		assert_flags(inst, /DRCUML_FLAG_V \|/ DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5071	assert_flags(inst, DRCUML_FLAG_V \| DRCUML_FLAG_Z \| DRCUML_FLAG_S);
5075	5072
5076	5073	/* normalize parameters */
5077	5074	param_normalize_4_commutative(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
r2864	r2865
5098	5095	/* compute flags */
5099	5096	if (inst->flags != 0)
5100	5097	{
5101		if (~~compute_hi~~)
	5098	if (zsflags != 0)
5102	5099	{
5103		if (inst->flags == DRCUML_FLAG_Z)
5104		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5105		else if (inst->flags == DRCUML_FLAG_S)
5106		emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
	5100	if (vflag)
	5101	emit_pushf(&dst); // pushf
	5102	if (compute_hi)
	5103	{
	5104	if (zsflags == DRCUML_FLAG_Z)
	5105	emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5106	else if (zsflags == DRCUML_FLAG_S)
	5107	emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
	5108	else
	5109	{
	5110	emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
	5111	emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
	5112	emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
	5113	emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5114	}
	5115	}
5107	5116	else
	5117	emit_test_r32_r32(&dst, REG_EAX, REG_EAX); // test eax,eax
	5118
	5119	/* we rely on the fact that OF is cleared by all logical operations above */
	5120	if (vflag)
5108	5121	{
5109		emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
5110		emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
5111		emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
5112		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5122	emit_pushf(&dst); // pushf
	5123	emit_pop_r32(&dst, REG_EAX); // pop eax
	5124	emit_and_m32_imm(&dst, MBD(REG_ESP, 0), ~0x84); // and [esp],~0x84
	5125	emit_or_m32_r32(&dst, MBD(REG_ESP, 0), REG_EAX); // or [esp],eax
	5126	emit_popf(&dst); // popf
5113	5127	}
5114	5128	}
5115		else
5116		emit_test_r32_r32(&dst, REG_EAX, REG_EAX); // test eax,eax
5117	5129	}
5118	5130	}
5119	5131
r2864	r2865
5121	5133	else if (inst->size == 8)
5122	5134	{
5123	5135	/* general case */
	5136	emit_mov_m32_imm(&dst, MBD(REG_ESP, 24), inst->flags); // mov [esp+24],flags
5124	5137	emit_mov_m64_p64(drcbe, &dst, MBD(REG_ESP, 16), &src2p); // mov [esp+16],src2p
5125	5138	emit_mov_m64_p64(drcbe, &dst, MBD(REG_ESP, 8), &src1p); // mov [esp+8],src1p
5126	5139	if (!compute_hi)
5127	5140	emit_mov_m32_imm(&dst, MBD(REG_ESP, 4), (FPTR)&drcbe->reslo); // mov [esp+4],&reslo
5128	5141	else
5129		emit_mov_m32_imm(&dst, MBD(REG_ESP, 4), (FPTR)&drcbe->reshi); // ~~push~~ [esp+4],&reshi
	5142	emit_mov_m32_imm(&dst, MBD(REG_ESP, 4), (FPTR)&drcbe->reshi); // mov [esp+4],&reshi
5130	5143	emit_mov_m32_imm(&dst, MBD(REG_ESP, 0), (FPTR)&drcbe->reslo); // mov [esp],&reslo
5131	5144	emit_call(&dst, (x86code *)dmulu); // call dmulu
	5145	if (inst->flags != 0)
	5146	emit_push_m32(&dst, MISD(REG_EAX, 4, flags_unmap)); // push flags_unmap[eax*4]
5132	5147	emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reslo + 0)); // mov eax,reslo.lo
5133	5148	emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reslo + 1)); // mov edx,reslo.hi
5134	5149	emit_mov_p64_r64(drcbe, &dst, &dstp, REG_EAX, REG_EDX); // mov dstp,edx:eax
5135		if (inst->flags != 0 && !compute_hi)
5136		{
5137		if (inst->flags == DRCUML_FLAG_Z)
5138		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5139		else if (inst->flags == DRCUML_FLAG_S)
5140		emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
5141		else
5142		{
5143		emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
5144		emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
5145		emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
5146		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5147		}
5148		}
5149	5150	if (compute_hi)
5150	5151	{
5151		if (inst->flags & DRCUML_FLAG_Z)
5152		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5153	5152	emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reshi + 0)); // mov eax,reshi.lo
5154	5153	emit_mov_r32_m32(&dst, REG_ECX, MABS((UINT32 *)&drcbe->reshi + 1)); // mov ecx,reshi.hi
5155	5154	emit_mov_p64_r64(drcbe, &dst, &edstp, REG_EAX, REG_ECX); // mov edstp,ecx:eax
5156		if (inst->flags != 0)
5157		{
5158		if (inst->flags == DRCUML_FLAG_Z)
5159		{
5160		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5161		emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
5162		}
5163		else if (inst->flags == DRCUML_FLAG_S)
5164		emit_test_r32_r32(&dst, REG_ECX, REG_ECX); // test ecx,ecx
5165		else
5166		{
5167		emit_or_r32_r32(&dst, REG_EAX, REG_EDX); // or eax,edx
5168		emit_movzx_r32_r16(&dst, REG_EDX, REG_AX); // movzx edx,ax
5169		emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
5170		emit_or_r32_r32(&dst, REG_ECX, REG_EDX); // or edx,ecx
5171		emit_or_r32_r32(&dst, REG_ECX, REG_EAX); // or edx,eax
5172		}
5173		}
5174	5155	}
	5156	if (inst->flags != 0)
	5157	emit_popf(&dst); // popf
5175	5158	}
5176	5159	return dst;
5177	5160	}
r2864	r2865
5183	5166
5184	5167	static x86code op_muls(drcbe_state drcbe, x86code dst, const drcuml_instruction inst)
5185	5168	{
	5169	UINT8 zsflags = inst->flags & (DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5170	UINT8 vflag = inst->flags & DRCUML_FLAG_V;
5186	5171	drcuml_parameter dstp, edstp, src1p, src2p;
5187	5172	int compute_hi;
5188	5173
5189	5174	/* validate instruction */
5190	5175	assert(inst->size == 4 \|\| inst->size == 8);
5191	5176	assert_no_condition(inst);
5192		assert_flags(inst, /DRCUML_FLAG_V \|/ DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5177	assert_flags(inst, DRCUML_FLAG_V \| DRCUML_FLAG_Z \| DRCUML_FLAG_S);
5193	5178
5194	5179	/* normalize parameters */
5195	5180	param_normalize_4_commutative(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
r2864	r2865
5239	5224	/* compute flags */
5240	5225	if (inst->flags != 0)
5241	5226	{
5242		if (~~compute_hi~~)
	5227	if (zsflags != 0)
5243	5228	{
5244		if (inst->flags == DRCUML_FLAG_Z)
5245		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5246		else if (inst->flags == DRCUML_FLAG_S)
5247		emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
	5229	if (vflag)
	5230	emit_pushf(&dst); // pushf
	5231	if (compute_hi)
	5232	{
	5233	if (inst->flags == DRCUML_FLAG_Z)
	5234	emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5235	else if (inst->flags == DRCUML_FLAG_S)
	5236	emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
	5237	else
	5238	{
	5239	emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
	5240	emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
	5241	emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
	5242	emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5243	}
	5244	}
5248	5245	else
	5246	emit_test_r32_r32(&dst, REG_EAX, REG_EAX); // test eax,eax
	5247
	5248	/* we rely on the fact that OF is cleared by all logical operations above */
	5249	if (vflag)
5249	5250	{
5250		emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
5251		emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
5252		emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
5253		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
	5251	emit_pushf(&dst); // pushf
	5252	emit_pop_r32(&dst, REG_EAX); // pop eax
	5253	emit_and_m32_imm(&dst, MBD(REG_ESP, 0), ~0x84); // and [esp],~0x84
	5254	emit_or_m32_r32(&dst, MBD(REG_ESP, 0), REG_EAX); // or [esp],eax
	5255	emit_popf(&dst); // popf
5254	5256	}
5255	5257	}
5256		else
5257		emit_test_r32_r32(&dst, REG_EAX, REG_EAX); // test eax,eax
5258	5258	}
5259	5259	}
5260	5260
r2864	r2865
5262	5262	else if (inst->size == 8)
5263	5263	{
5264	5264	/* general case */
	5265	emit_mov_m32_imm(&dst, MBD(REG_ESP, 24), inst->flags); // mov [esp+24],flags
5265	5266	emit_mov_m64_p64(drcbe, &dst, MBD(REG_ESP, 16), &src2p); // mov [esp+16],src2p
5266	5267	emit_mov_m64_p64(drcbe, &dst, MBD(REG_ESP, 8), &src1p); // mov [esp+8],src1p
5267	5268	if (!compute_hi)
r2864	r2865
5270	5271	emit_mov_m32_imm(&dst, MBD(REG_ESP, 4), (FPTR)&drcbe->reshi); // push [esp+4],&reshi
5271	5272	emit_mov_m32_imm(&dst, MBD(REG_ESP, 0), (FPTR)&drcbe->reslo); // mov [esp],&reslo
5272	5273	emit_call(&dst, (x86code *)dmuls); // call dmuls
	5274	if (inst->flags != 0)
	5275	emit_push_m32(&dst, MISD(REG_EAX, 4, flags_unmap)); // push flags_unmap[eax*4]
5273	5276	emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reslo + 0)); // mov eax,reslo.lo
5274	5277	emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reslo + 1)); // mov edx,reslo.hi
5275	5278	emit_mov_p64_r64(drcbe, &dst, &dstp, REG_EAX, REG_EDX); // mov dstp,edx:eax
5276		if (inst->flags != 0 && !compute_hi)
5277		{
5278		if (inst->flags == DRCUML_FLAG_Z)
5279		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5280		else if (inst->flags == DRCUML_FLAG_S)
5281		emit_test_r32_r32(&dst, REG_EDX, REG_EDX); // test edx,edx
5282		else
5283		{
5284		emit_movzx_r32_r16(&dst, REG_ECX, REG_AX); // movzx ecx,ax
5285		emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
5286		emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
5287		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5288		}
5289		}
5290	5279	if (compute_hi)
5291	5280	{
5292	5281	emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reshi + 0)); // mov eax,reshi.lo
5293	5282	emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reshi + 1)); // mov edx,reshi.hi
5294	5283	emit_mov_p64_r64(drcbe, &dst, &edstp, REG_EAX, REG_EDX); // mov edstp,edx:eax
5295		if (inst->flags != 0)
5296		{
5297		if (inst->flags == DRCUML_FLAG_Z)
5298		{
5299		emit_or_r32_r32(&dst, REG_EDX, REG_EAX); // or edx,eax
5300		emit_or_r32_r32(&dst, REG_EDX, REG_ECX); // or edx,ecx
5301		}
5302		else if (inst->flags == DRCUML_FLAG_S)
5303		emit_test_r32_r32(&dst, REG_ECX, REG_ECX); // test ecx,ecx
5304		else
5305		{
5306		emit_or_r32_r32(&dst, REG_EAX, REG_EDX); // or eax,edx
5307		emit_movzx_r32_r16(&dst, REG_EDX, REG_AX); // movzx edx,ax
5308		emit_shr_r32_imm(&dst, REG_EAX, 16); // shr eax,16
5309		emit_or_r32_r32(&dst, REG_ECX, REG_EDX); // or edx,ecx
5310		emit_or_r32_r32(&dst, REG_ECX, REG_EAX); // or edx,eax
5311		}
5312		}
5313	5284	}
	5285	if (inst->flags != 0)
	5286	emit_popf(&dst); // popf
5314	5287	}
5315	5288	return dst;
5316	5289	}
r2864	r2865
5329	5302	/* validate instruction */
5330	5303	assert(inst->size == 4 \|\| inst->size == 8);
5331	5304	assert_no_condition(inst);
5332		assert_flags(inst, /DRCUML_FLAG_V \|/ DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5305	assert_flags(inst, DRCUML_FLAG_V \| DRCUML_FLAG_Z \| DRCUML_FLAG_S);
5333	5306
5334	5307	/* normalize parameters */
5335	5308	param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
r2864	r2865
5340	5313	{
5341	5314	/* general case */
5342	5315	emit_mov_r32_p32(drcbe, &dst, REG_ECX, &src2p); // mov ecx,src2p
	5316	if (inst->flags != 0)
	5317	{
	5318	emit_mov_r32_imm(&dst, REG_EAX, 0xa0000000); // mov eax,0xa0000000
	5319	emit_add_r32_r32(&dst, REG_EAX, REG_EAX); // add eax,eax
	5320	}
5343	5321	emit_jecxz_link(&dst, &skip); // jecxz skip
5344	5322	emit_mov_r32_p32(drcbe, &dst, REG_EAX, &src1p); // mov eax,src1p
5345	5323	emit_xor_r32_r32(&dst, REG_EDX, REG_EDX); // xor edx,edx
r2864	r2865
5364	5342	emit_mov_m32_imm(&dst, MBD(REG_ESP, 4), (FPTR)&drcbe->reshi); // push [esp+4],&reshi
5365	5343	emit_mov_m32_imm(&dst, MBD(REG_ESP, 0), (FPTR)&drcbe->reslo); // mov [esp],&reslo
5366	5344	emit_call(&dst, (x86code *)ddivu); // call ddivu
	5345	if (inst->flags != 0)
	5346	emit_push_m32(&dst, MISD(REG_EAX, 4, flags_unmap)); // push flags_unmap[eax*4]
5367	5347	emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reslo + 0)); // mov eax,reslo.lo
5368	5348	emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reslo + 1)); // mov edx,reslo.hi
5369	5349	emit_mov_p64_r64(drcbe, &dst, &dstp, REG_EAX, REG_EDX); // mov dstp,edx:eax
5370		if (inst->flags != 0)
5371		emit_or_r32_r32(&dst, REG_EAX, REG_EDX); // or eax,edx
5372	5350	if (compute_rem)
5373	5351	{
5374	5352	emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reshi + 0)); // mov eax,reshi.lo
5375	5353	emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reshi + 1)); // mov edx,reshi.hi
5376	5354	emit_mov_p64_r64(drcbe, &dst, &edstp, REG_EAX, REG_EDX); // mov edstp,edx:eax
5377	5355	}
	5356	if (inst->flags != 0)
	5357	emit_popf(&dst); // popf
5378	5358	}
5379	5359	return dst;
5380	5360	}
r2864	r2865
5393	5373	/* validate instruction */
5394	5374	assert(inst->size == 4 \|\| inst->size == 8);
5395	5375	assert_no_condition(inst);
5396		assert_flags(inst, /DRCUML_FLAG_V \|/ DRCUML_FLAG_Z \| DRCUML_FLAG_S);
	5376	assert_flags(inst, DRCUML_FLAG_V \| DRCUML_FLAG_Z \| DRCUML_FLAG_S);
5397	5377
5398	5378	/* normalize parameters */
5399	5379	param_normalize_4(drcbe, inst, &dstp, PTYPE_MR, &edstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
r2864	r2865
5404	5384	{
5405	5385	/* general case */
5406	5386	emit_mov_r32_p32(drcbe, &dst, REG_ECX, &src2p); // mov ecx,src2p
	5387	if (inst->flags != 0)
	5388	{
	5389	emit_mov_r32_imm(&dst, REG_EAX, 0xa0000000); // mov eax,0xa0000000
	5390	emit_add_r32_r32(&dst, REG_EAX, REG_EAX); // add eax,eax
	5391	}
5407	5392	emit_jecxz_link(&dst, &skip); // jecxz skip
5408	5393	emit_mov_r32_p32(drcbe, &dst, REG_EAX, &src1p); // mov eax,src1p
5409	5394	emit_cdq(&dst); // cdq
r2864	r2865
5428	5413	emit_mov_m32_imm(&dst, MBD(REG_ESP, 4), (FPTR)&drcbe->reshi); // push [esp+4],&reshi
5429	5414	emit_mov_m32_imm(&dst, MBD(REG_ESP, 0), (FPTR)&drcbe->reslo); // mov [esp],&reslo
5430	5415	emit_call(&dst, (x86code *)ddivs); // call ddivs
	5416	if (inst->flags != 0)
	5417	emit_push_m32(&dst, MISD(REG_EAX, 4, flags_unmap)); // push flags_unmap[eax*4]
5431	5418	emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reslo + 0)); // mov eax,reslo.lo
5432	5419	emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reslo + 1)); // mov edx,reslo.hi
5433	5420	emit_mov_p64_r64(drcbe, &dst, &dstp, REG_EAX, REG_EDX); // mov dstp,edx:eax
5434		if (inst->flags != 0)
5435		emit_or_r32_r32(&dst, REG_EAX, REG_EDX); // or eax,edx
5436	5421	if (compute_rem)
5437	5422	{
5438	5423	emit_mov_r32_m32(&dst, REG_EAX, MABS((UINT32 *)&drcbe->reshi + 0)); // mov eax,reshi.lo
5439	5424	emit_mov_r32_m32(&dst, REG_EDX, MABS((UINT32 *)&drcbe->reshi + 1)); // mov edx,reshi.hi
5440	5425	emit_mov_p64_r64(drcbe, &dst, &edstp, REG_EAX, REG_EDX); // mov edstp,edx:eax
5441	5426	}
	5427	if (inst->flags != 0)
	5428	emit_popf(&dst); // popf
5442	5429	}
5443	5430	return dst;
5444	5431	}
r2864	r2865
5460	5447
5461	5448	/* normalize parameters */
5462	5449	param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5463		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5464	5450
5465	5451	/* pick a target register for the general case */
5466	5452	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5569	5555
5570	5556	/* normalize parameters */
5571	5557	param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5572		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5573	5558
5574	5559	/* pick a target register for the general case */
5575	5560	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5625	5610
5626	5611	/* normalize parameters */
5627	5612	param_normalize_3_commutative(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5628		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5629	5613
5630	5614	/* pick a target register for the general case */
5631	5615	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5681	5665
5682	5666	/* normalize parameters */
5683	5667	param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI);
5684		assert(srcp.type != DRCUML_PTYPE_IMMEDIATE);
5685	5668
5686	5669	/* pick a target register for the general case */
5687	5670	dstreg = param_select_register(REG_EAX, &dstp, NULL);
r2864	r2865
5732	5715
5733	5716	/* normalize parameters */
5734	5717	param_normalize_2(drcbe, inst, &dstp, PTYPE_MR, &srcp, PTYPE_MRI);
5735		assert(srcp.type != DRCUML_PTYPE_IMMEDIATE);
5736	5718
5737	5719	/* pick a target register for the general case */
5738	5720	dstreg = param_select_register(REG_EAX, &dstp, NULL);
r2864	r2865
5773	5755
5774	5756	/* normalize parameters */
5775	5757	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5776		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5777	5758
5778	5759	/* pick a target register for the general case */
5779	5760	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5822	5803
5823	5804	/* normalize parameters */
5824	5805	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5825		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5826	5806
5827	5807	/* pick a target register for the general case */
5828	5808	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5871	5851
5872	5852	/* normalize parameters */
5873	5853	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5874		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5875	5854
5876	5855	/* pick a target register for the general case */
5877	5856	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5920	5899
5921	5900	/* normalize parameters */
5922	5901	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5923		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5924	5902
5925	5903	/* pick a target register for the general case */
5926	5904	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
5969	5947
5970	5948	/* normalize parameters */
5971	5949	param_normalize_3(drcbe, inst, &dstp, PTYPE_MR, &src1p, PTYPE_MRI, &src2p, PTYPE_MRI);
5972		assert(src1p.type != DRCUML_PTYPE_IMMEDIATE \|\| src2p.type != DRCUML_PTYPE_IMMEDIATE);
5973	5950
5974	5951	/* pick a target register for the general case */
5975	5952	dstreg = param_select_register(REG_EAX, &dstp, &src2p);
r2864	r2865
6738	6715	dmulu - perform a double-wide unsigned multiply
6739	6716	-------------------------------------------------*/
6740	6717
6741		static void dmulu(UINT64 dstlo, UINT64 dsthi, UINT64 src1, UINT64 src2)
	6718	static int dmulu(UINT64 dstlo, UINT64 dsthi, UINT64 src1, UINT64 src2, int flags)
6742	6719	{
6743	6720	UINT64 lo, hi, prevlo;
6744	6721	UINT64 a, b, temp;
6745	6722
6746		/* shortcut if we don't care about the high bits */
6747		if (dstlo == dsthi)
	6723	/* shortcut if we don't care about the high bits or the flags */
	6724	if (dstlo == dsthi && flags == 0)
6748	6725	{
6749	6726	dstlo = src1 src2;
6750		return;
	6727	return 0;
6751	6728	}
6752	6729
6753	6730	/* fetch source values */
r2864	r2865
6756	6733	if (a == 0 \|\| b == 0)
6757	6734	{
6758	6735	dsthi = dstlo = 0;
6759		return;
	6736	return DRCUML_FLAG_Z;
6760	6737	}
6761	6738
6762	6739	/* compute high and low parts first */
r2864	r2865
6777	6754	/* store the results */
6778	6755	*dsthi = hi;
6779	6756	*dstlo = lo;
	6757	return ((hi >> 60) & DRCUML_FLAG_S) \| ((*dsthi != 0) << 1);
6780	6758	}
6781	6759
6782	6760
r2864	r2865
6784	6762	dmuls - perform a double-wide signed multiply
6785	6763	-------------------------------------------------*/
6786	6764
6787		static void dmuls(UINT64 dstlo, UINT64 dsthi, INT64 src1, INT64 src2)
	6765	static int dmuls(UINT64 dstlo, UINT64 dsthi, INT64 src1, INT64 src2, int flags)
6788	6766	{
6789	6767	UINT64 lo, hi, prevlo;
6790	6768	UINT64 a, b, temp;
6791	6769
6792		/* shortcut if we don't care about the high bits */
6793		if (dstlo == dsthi)
	6770	/* shortcut if we don't care about the high bits or the flags */
	6771	if (dstlo == dsthi && flags == 0)
6794	6772	{
6795	6773	dstlo = src1 src2;
6796		return;
	6774	return 0;
6797	6775	}
6798	6776
6799	6777	/* fetch absolute source values */
r2864	r2865
6802	6780	if (a == 0 \|\| b == 0)
6803	6781	{
6804	6782	dsthi = dstlo = 0;
6805		return;
	6783	return DRCUML_FLAG_Z;
6806	6784	}
6807	6785
6808	6786	/* compute high and low parts first */
r2864	r2865
6830	6808	/* store the results */
6831	6809	*dsthi = hi;
6832	6810	*dstlo = lo;
	6811	return ((hi >> 60) & DRCUML_FLAG_S) \| ((*dsthi != ((INT64)lo >> 63)) << 1);
6833	6812	}
6834	6813
6835	6814
r2864	r2865
6837	6816	ddivu - perform a double-wide unsigned divide
6838	6817	-------------------------------------------------*/
6839	6818
6840		static void ddivu(UINT64 dstlo, UINT64 dsthi, UINT64 src1, UINT64 src2)
	6819	static int ddivu(UINT64 dstlo, UINT64 dsthi, UINT64 src1, UINT64 src2)
6841	6820	{
6842	6821	/* do nothing if src2 == 0 */
6843	6822	if (src2 == 0)
6844		return;
	6823	return DRCUML_FLAG_V;
6845	6824
6846	6825	/* shortcut if no remainder */
6847	6826	*dstlo = src1 / src2;
6848	6827	if (dstlo != dsthi)
6849	6828	*dsthi = src1 % src2;
	6829	return ((dstlo == 0) << 2) \| ((dstlo >> 60) & DRCUML_FLAG_S);
6850	6830	}
6851	6831
6852	6832
r2864	r2865
6854	6834	ddivs - perform a double-wide signed divide
6855	6835	-------------------------------------------------*/
6856	6836
6857		static void ddivs(UINT64 dstlo, UINT64 dsthi, INT64 src1, INT64 src2)
	6837	static int ddivs(UINT64 dstlo, UINT64 dsthi, INT64 src1, INT64 src2)
6858	6838	{
6859	6839	/* do nothing if src2 == 0 */
6860	6840	if (src2 == 0)
6861		return;
	6841	return DRCUML_FLAG_V;
6862	6842
6863	6843	/* shortcut if no remainder */
6864	6844	*dstlo = src1 / src2;
6865	6845	if (dstlo != dsthi)
6866	6846	*dsthi = src1 % src2;
	6847	return ((dstlo == 0) << 2) \| ((dstlo >> 60) & DRCUML_FLAG_S);
6867	6848	}

src/emu/audio/generic.h
r2864	r2865
55	55	/* If you're going to use soundlatchX_clear_w, and the cleared value is
56	56	something other than 0x00, use this function from machine_init. Note
57	57	that this one call effects all 4 latches */
58		void soundlatch_setclearedvalue(int value);
	58	void soundlatch_setclearedvalue(running_machine *machine, int value);
59	59
60	60
61	61	#endif /* __SOUND_GENERIC_H__ */

src/emu/audio/generic.c
r2864	r2865
11	11
12	12	#include "driver.h"
13	13	#include "generic.h"
14		#include "deprecat.h"
15	14
16	15
17	16
r2864	r2865
157	156	value for all sound latches
158	157	-------------------------------------------------*/
159	158
160		void soundlatch_setclearedvalue(int value)
	159	void soundlatch_setclearedvalue(running_machine *machine, int value)
161	160	{
162		assert_always(mame_get_phase(Machine) == MAME_PHASE_INIT, "Can only call soundlatch_setclearedvalue at init time!");
	161	assert_always(mame_get_phase(machine) == MAME_PHASE_INIT, "Can only call soundlatch_setclearedvalue at init time!");
163	162	latch_clear_value = value;
164	163	}

src/emu/emuopts.c
r2864	r2865
64	64	{ "autosave", "0", OPTION_BOOLEAN, "enable automatic restore at startup, and automatic save at exit time" },
65	65	{ "playback;pb", NULL, 0, "playback an input file" },
66	66	{ "record;rec", NULL, 0, "record an input file" },
67		{ "snapname", "%g/%i", 0, "override of the default snapshot naming; %g == gamename, %i == index" },
68	67	{ "mngwrite", NULL, 0, "optional filename to write a MNG movie of the current session" },
69	68	{ "aviwrite", NULL, 0, "optional filename to write an AVI movie of the current session" },
70	69	{ "wavwrite", NULL, 0, "optional filename to write a WAV file of the current session" },
	70	{ "snapname", "%g/%i", 0, "override of the default snapshot/movie naming; %g == gamename, %i == index" },
	71	{ "snapsize", "auto", 0, "specify snapshot/movie resolution (<width>x<height>) or 'auto' to use minimal size " },
	72	{ "snapview", "internal", 0, "specify snapshot/movie view or 'internal' to use internal pixel-aspect views" },
71	73
72	74	/* performance options */
73	75	{ NULL, NULL, OPTION_HEADER, "CORE PERFORMANCE OPTIONS" },

src/emu/emuopts.h
r2864	r2865
63	63	#define OPTION_AUTOSAVE "autosave"
64	64	#define OPTION_PLAYBACK "playback"
65	65	#define OPTION_RECORD "record"
66		#define OPTION_SNAPNAME "snapname"
67	66	#define OPTION_MNGWRITE "mngwrite"
68	67	#define OPTION_AVIWRITE "aviwrite"
69	68	#define OPTION_WAVWRITE "wavwrite"
	69	#define OPTION_SNAPNAME "snapname"
	70	#define OPTION_SNAPSIZE "snapsize"
	71	#define OPTION_SNAPVIEW "snapview"
70	72
71	73	/* core performance options */
72	74	#define OPTION_AUTOFRAMESKIP "autoframeskip"

src/emu/video.c
r2864	r2865
38	38	#define SUBSECONDS_PER_SPEED_UPDATE (ATTOSECONDS_PER_SECOND / 4)
39	39	#define PAUSED_REFRESH_RATE (30)
40	40	#define MAX_VBLANK_CALLBACKS (10)
41		#define DEFAULT_FRAME_PERIOD ATTOTIME_IN_HZ(60)
	41	#define DEFAULT_FRAME_RATE 60
	42	#define DEFAULT_FRAME_PERIOD ATTOTIME_IN_HZ(DEFAULT_FRAME_RATE)
42	43
43	44
44	45
r2864	r2865
78	79
79	80	/* screen specific VBLANK callbacks */
80	81	vblank_state_changed_func vblank_callback[MAX_VBLANK_CALLBACKS]; /* the array of callbacks */
81
82		/* movie recording */
83		mame_file * mng_file; /* handle to the open movie file */
84		avi_file * avi_file; /* handle to the open movie file */
85		UINT32 movie_frame; /* current movie frame number */
86	82	};
87	83
88	84
r2864	r2865
128	124	/* snapshot stuff */
129	125	render_target * snap_target; /* screen shapshot target */
130	126	bitmap_t * snap_bitmap; /* screen snapshot bitmap */
	127	UINT8 snap_native; /* are we using native per-screen layouts? */
	128	INT32 snap_width; /* width of snapshots (0 == auto) */
	129	INT32 snap_height; /* height of snapshots (0 == auto) */
	130
	131	/* movie recording */
	132	mame_file * mng_file; /* handle to the open movie file */
	133	avi_file * avi_file; /* handle to the open movie file */
	134	attotime movie_frame_period; /* period of a single movie frame */
	135	attotime movie_next_frame_time; /* time of next frame */
	136	UINT32 movie_frame; /* current movie frame number */
131	137	};
132	138
133	139
r2864	r2865
190	196	static file_error mame_fopen_next(running_machine machine, const char pathoption, const char extension, mame_file *file);
191	197
192	198	/* movie recording */
193		static void video_mng_record_frame(const device_config *screen);
194		static void video_avi_record_frame(const device_config *screen);
	199	static void video_mng_record_frame(running_machine *machine);
	200	static void video_avi_record_frame(running_machine *machine);
195	201
196	202	/* software rendering */
197	203	static void rgb888_draw_primitives(const render_primitive primlist, void dstdata, UINT32 width, UINT32 height, UINT32 pitch);
r2864	r2865
295	301	void video_init(running_machine *machine)
296	302	{
297	303	const char *filename;
	304	const char *viewname;
298	305
299	306	/* validate */
300	307	assert(machine != NULL);
r2864	r2865
339	346	pdrawgfx_shadow_lowpri = 0;
340	347
341	348	/* create a render target for snapshots */
342		if (machine->primary_screen != NULL)
343		{
	349	viewname = options_get_string(mame_options(), OPTION_SNAPVIEW);
	350	global.snap_native = (machine->primary_screen != NULL && (viewname[0] == 0 \|\| strcmp(viewname, "native") == 0));
	351	if (global.snap_native)
344	352	global.snap_target = render_target_alloc(layout_snap, RENDER_CREATE_SINGLE_FILE \| RENDER_CREATE_HIDDEN);
345		assert(global.snap_target != NULL);
	353	else
	354	global.snap_target = render_target_alloc(NULL, RENDER_CREATE_HIDDEN);
	355	assert(global.snap_target != NULL);
	356
	357	/* if we are using the native layout, turn off all accoutrements */
	358	if (global.snap_native)
346	359	render_target_set_layer_config(global.snap_target, 0);
347		}
348	360
	361	/* otherwise, find the requested view and select it */
	362	else
	363	render_target_set_view(global.snap_target, video_get_view_for_target(machine, global.snap_target, viewname, 0, 1));
	364
	365	/* extract snap resolution if present */
	366	if (sscanf(options_get_string(mame_options(), OPTION_SNAPSIZE), "%dx%d", &global.snap_width, &global.snap_height) != 2)
	367	global.snap_width = global.snap_height = 0;
	368
349	369	/* start recording movie if specified */
350	370	filename = options_get_string(mame_options(), OPTION_MNGWRITE);
351		if (filename[0] != 0 && machine->primary_screen != NULL)
352		video_mng_begin_recording(machine->primary_screen, filename);
	371	if (filename[0] != 0)
	372	video_mng_begin_recording(machine, filename);
353	373
354	374	filename = options_get_string(mame_options(), OPTION_AVIWRITE);
355		if (filename[0] != 0 && machine->primary_screen != NULL)
356		video_avi_begin_recording(machine->primary_screen, filename);
	375	if (filename[0] != 0)
	376	video_avi_begin_recording(machine, filename);
357	377
358	378	/* if no screens, create a periodic timer to drive updates */
359	379	if (machine->primary_screen == NULL)
r2864	r2865
379	399	/* stop recording any movie */
380	400	if (machine->primary_screen != NULL)
381	401	{
382		video_mng_end_recording(machine->primary_screen);
383		video_avi_end_recording(machine->primary_screen);
	402	video_mng_end_recording(machine);
	403	video_avi_end_recording(machine);
384	404	}
385	405
386	406	/* free all the graphics elements */
r2864	r2865
1515	1535	render_container_empty(render_container_get_screen(screen));
1516	1536	render_screen_add_quad(screen, 0.0f, 0.0f, 1.0f, 1.0f, MAKE_ARGB(0xff,0xff,0xff,0xff), state->texture[state->curtexture], PRIMFLAG_BLENDMODE(BLENDMODE_NONE) \| PRIMFLAG_SCREENTEX(1));
1517	1537	}
1518
1519		/* update our movie recording state */
1520		if (!mame_is_paused(machine))
1521		{
1522		video_mng_record_frame(screen);
1523		video_avi_record_frame(screen);
1524		}
1525	1538	}
1526	1539
1527	1540	/* reset the screen changed flags */
r2864	r2865
1530	1543	state->changed = FALSE;
1531	1544	}
1532	1545
	1546	/* update our movie recording state */
	1547	if (!mame_is_paused(machine))
	1548	{
	1549	video_mng_record_frame(machine);
	1550	video_avi_record_frame(machine);
	1551	}
	1552
1533	1553	/* draw any crosshairs */
1534	1554	for (screen = video_screen_first(machine->config); screen != NULL; screen = video_screen_next(screen))
1535	1555	crosshair_render(screen);
r2864	r2865
2089	2109	filerr = mame_fopen(SEARCHPATH_SCREENSHOT, astring_c(fname), OPEN_FLAG_WRITE \| OPEN_FLAG_CREATE \| OPEN_FLAG_CREATE_PATHS, &file);
2090	2110	if (filerr == FILERR_NONE)
2091	2111	{
2092		video_screen_save_snapshot(machine->primary_screen, file);
	2112	video_screen_save_snapshot(machine, machine->primary_screen, file);
2093	2113	mame_fclose(file);
2094	2114	}
2095	2115	astring_free(fname);
r2864	r2865
2111	2131	to the given file handle
2112	2132	-------------------------------------------------*/
2113	2133
2114		void video_screen_save_snapshot(const device_config screen, mame_file fp)
	2134	void video_screen_save_snapshot(running_machine machine, const device_config screen, mame_file *fp)
2115	2135	{
	2136	png_info pnginfo = { 0 };
2116	2137	const rgb_t *palette;
2117		png_info pnginfo = { 0 };
2118	2138	png_error error;
2119	2139	char text[256];
2120	2140
2121	2141	/* validate */
2122		assert(screen != NULL);
	2142	assert(!global.snap_native \|\| screen != NULL);
2123	2143	assert(fp != NULL);
2124	2144
2125	2145	/* create the bitmap to pass in */
r2864	r2865
2128	2148	/* add two text entries describing the image */
2129	2149	sprintf(text, APPNAME " %s", build_version);
2130	2150	png_add_text(&pnginfo, "Software", text);
2131		sprintf(text, "%s %s", ~~screen->~~machine->gamedrv->manufacturer, ~~screen->~~machine->gamedrv->description);
	2151	sprintf(text, "%s %s", machine->gamedrv->manufacturer, machine->gamedrv->description);
2132	2152	png_add_text(&pnginfo, "System", text);
2133	2153
2134	2154	/* now do the actual work */
2135		palette = (screen->machine->palette != NULL) ? palette_entry_list_adjusted(screen->machine->palette) : NULL;
2136		error = png_write_bitmap(mame_core_file(fp), &pnginfo, global.snap_bitmap, screen->machine->config->total_colors, palette);
	2155	palette = (machine->palette != NULL) ? palette_entry_list_adjusted(machine->palette) : NULL;
	2156	error = png_write_bitmap(mame_core_file(fp), &pnginfo, global.snap_bitmap, machine->config->total_colors, palette);
2137	2157
2138	2158	/* free any data allocated */
2139	2159	png_free(&pnginfo);
r2864	r2865
2154	2174	assert(machine != NULL);
2155	2175	assert(machine->config != NULL);
2156	2176
2157		/* write one snapshot per visible screen */
2158		for (screen = video_screen_first(machine->config); screen != NULL; screen = video_screen_next(screen))
2159		if (render_is_live_screen(screen))
2160		{
2161		file_error filerr = mame_fopen_next(machine, SEARCHPATH_SCREENSHOT, "png", &fp);
2162		if (filerr == FILERR_NONE)
	2177	/* if we're native, then write one snapshot per visible screen */
	2178	if (global.snap_native)
	2179	{
	2180	/* write one snapshot per visible screen */
	2181	for (screen = video_screen_first(machine->config); screen != NULL; screen = video_screen_next(screen))
	2182	if (render_is_live_screen(screen))
2163	2183	{
2164		video_screen_save_snapshot(screen, fp);
2165		mame_fclose(fp);
	2184	file_error filerr = mame_fopen_next(machine, SEARCHPATH_SCREENSHOT, "png", &fp);
	2185	if (filerr == FILERR_NONE)
	2186	{
	2187	video_screen_save_snapshot(machine, screen, fp);
	2188	mame_fclose(fp);
	2189	}
2166	2190	}
	2191	}
	2192
	2193	/* otherwise, just write a single snapshot */
	2194	else
	2195	{
	2196	file_error filerr = mame_fopen_next(machine, SEARCHPATH_SCREENSHOT, "png", &fp);
	2197	if (filerr == FILERR_NONE)
	2198	{
	2199	video_screen_save_snapshot(machine, NULL, fp);
	2200	mame_fclose(fp);
2167	2201	}
	2202	}
2168	2203	}
2169	2204
2170	2205
r2864	r2865
2181	2216	int view_index;
2182	2217
2183	2218	/* select the appropriate view in our dummy target */
2184		view_index = device_list_index(screen->machine->config->devicelist, VIDEO_SCREEN, screen->tag);
2185		assert(view_index != -1);
2186		render_target_set_view(global.snap_target, view_index);
	2219	if (global.snap_native && screen != NULL)
	2220	{
	2221	view_index = device_list_index(screen->machine->config->devicelist, VIDEO_SCREEN, screen->tag);
	2222	assert(view_index != -1);
	2223	render_target_set_view(global.snap_target, view_index);
	2224	}
2187	2225
2188	2226	/* get the minimum width/height and set it on the target */
2189		render_target_get_minimum_size(global.snap_target, &width, &height);
	2227	width = global.snap_width;
	2228	height = global.snap_height;
	2229	if (width == 0 \|\| height == 0)
	2230	render_target_get_minimum_size(global.snap_target, &width, &height);
2190	2231	render_target_set_bounds(global.snap_target, width, height, 0);
2191	2232
2192	2233	/* if we don't have a bitmap, or if it's not the right size, allocate a new one */
r2864	r2865
2285	2326	MNG movie is currently being recorded
2286	2327	-------------------------------------------------*/
2287	2328
2288		int video_mng_is_movie_active(con~~st dev~~ice_c~~onf~~ig *sc~~ree~~n)
	2329	int video_mng_is_movie_active(running_machine *machine)
2289	2330	{
2290		screen_state *state = get_safe_token(screen);
2291		return (state->mng_file != NULL);
	2331	return (global.mng_file != NULL);
2292	2332	}
2293	2333
2294	2334
r2864	r2865
2297	2337	of a MNG movie
2298	2338	-------------------------------------------------*/
2299	2339
2300		void video_mng_begin_recording(con~~st dev~~ice_c~~onf~~ig sc~~ree~~n, const char name)
	2340	void video_mng_begin_recording(running_machine machine, const char name)
2301	2341	{
2302		screen_state *state = ~~get_safe_token(screen)~~;
	2342	screen_state *state = NULL;
2303	2343	file_error filerr;
	2344	png_error pngerr;
	2345	int rate;
2304	2346
2305	2347	/* close any existing movie file */
2306		if (state->mng_file != NULL)
2307		video_mng_end_recording(screen);
	2348	if (global.mng_file != NULL)
	2349	video_mng_end_recording(machine);
2308	2350
	2351	/* look up the primary screen */
	2352	if (machine->primary_screen != NULL)
	2353	state = get_safe_token(machine->primary_screen);
	2354
	2355	/* create a snapshot bitmap so we know what the target size is */
	2356	create_snapshot_bitmap(NULL);
	2357
2309	2358	/* create a new movie file and start recording */
2310	2359	if (name != NULL)
2311		filerr = mame_fopen(SEARCHPATH_MOVIE, name, OPEN_FLAG_WRITE \| OPEN_FLAG_CREATE \| OPEN_FLAG_CREATE_PATHS, &sta~~te->~~mng_file);
	2360	filerr = mame_fopen(SEARCHPATH_MOVIE, name, OPEN_FLAG_WRITE \| OPEN_FLAG_CREATE \| OPEN_FLAG_CREATE_PATHS, &global.mng_file);
2312	2361	else
2313		filerr = mame_fopen_next(screen->machine, SEARCHPATH_MOVIE, "mng", &state->mng_file);
2314		state->movie_frame = 0;
	2362	filerr = mame_fopen_next(machine, SEARCHPATH_MOVIE, "mng", &global.mng_file);
	2363
	2364	/* start the capture */
	2365	rate = (state != NULL) ? ATTOSECONDS_TO_HZ(state->frame_period) : DEFAULT_FRAME_RATE;
	2366	pngerr = mng_capture_start(mame_core_file(global.mng_file), global.snap_bitmap, rate);
	2367	if (pngerr != PNGERR_NONE)
	2368	{
	2369	video_mng_end_recording(machine);
	2370	return;
	2371	}
	2372
	2373	/* compute the frame time */
	2374	global.movie_next_frame_time = timer_get_time();
	2375	global.movie_frame_period = ATTOTIME_IN_HZ(rate);
	2376	global.movie_frame = 0;
2315	2377	}
2316	2378
2317	2379
r2864	r2865
2320	2382	a MNG movie
2321	2383	-------------------------------------------------*/
2322	2384
2323		void video_mng_end_recording(con~~st dev~~ice_c~~onf~~ig *sc~~ree~~n)
	2385	void video_mng_end_recording(running_machine *machine)
2324	2386	{
2325		screen_state *state = get_safe_token(screen);
2326
2327	2387	/* close the file if it exists */
2328		if (sta~~te->~~mng_file != NULL)
	2388	if (global.mng_file != NULL)
2329	2389	{
2330		mng_capture_stop(mame_core_file(state->mng_file));
2331		mame_fclose(state->mng_file);
2332		state->mng_file = NULL;
2333		state->movie_frame = 0;
	2390	mng_capture_stop(mame_core_file(global.mng_file));
	2391	mame_fclose(global.mng_file);
	2392	global.mng_file = NULL;
	2393	global.movie_frame = 0;
2334	2394	}
2335	2395	}
2336	2396
r2864	r2865
2340	2400	movie
2341	2401	-------------------------------------------------*/
2342	2402
2343		static void video_mng_record_frame(con~~st dev~~ice_c~~onf~~ig *sc~~ree~~n)
	2403	static void video_mng_record_frame(running_machine *machine)
2344	2404	{
2345		screen_state *state = get_safe_token(screen);
2346		const rgb_t *palette;
2347
2348	2405	/* only record if we have a file */
2349		if (sta~~te->~~mng_file != NULL)
	2406	if (global.mng_file != NULL)
2350	2407	{
	2408	attotime curtime = timer_get_time();
2351	2409	png_info pnginfo = { 0 };
2352	2410	png_error error;
2353	2411
2354	2412	profiler_mark(PROFILER_MOVIE_REC);
2355	2413
2356	2414	/* create the bitmap */
2357		create_snapshot_bitmap(~~screen~~);
	2415	create_snapshot_bitmap(NULL);
2358	2416
2359		/* track frames */
2360		if (state->movie_frame++ == 0)
	2417	/* loop until we hit the right time */
	2418	while (attotime_compare(global.movie_next_frame_time, curtime) <= 0)
2361	2419	{
2362		c~~har~~ text~~[256]~~;
	2420	const rgb_t *palette;
2363	2421
2364	2422	/* set up the text fields in the movie info */
2365		sprintf(text, APPNAME " %s", build_version);
2366		png_add_text(&pnginfo, "Software", text);
2367		sprintf(text, "%s %s", screen->machine->gamedrv->manufacturer, screen->machine->gamedrv->description);
2368		png_add_text(&pnginfo, "System", text);
	2423	if (global.movie_frame == 0)
	2424	{
	2425	char text[256];
2369	2426
2370		/* start the capture */
2371		error = mng_capture_start(mame_core_file(state->mng_file), global.snap_bitmap, ATTOSECONDS_TO_HZ(state->frame_period));
	2427	sprintf(text, APPNAME " %s", build_version);
	2428	png_add_text(&pnginfo, "Software", text);
	2429	sprintf(text, "%s %s", machine->gamedrv->manufacturer, machine->gamedrv->description);
	2430	png_add_text(&pnginfo, "System", text);
	2431	}
	2432
	2433	/* write the next frame */
	2434	palette = (machine->palette != NULL) ? palette_entry_list_adjusted(machine->palette) : NULL;
	2435	error = mng_capture_frame(mame_core_file(global.mng_file), &pnginfo, global.snap_bitmap, machine->config->total_colors, palette);
	2436	png_free(&pnginfo);
2372	2437	if (error != PNGERR_NONE)
2373	2438	{
2374		png_free(&pnginfo);
2375		video_mng_end_recording(screen);
2376		return;
	2439	video_mng_end_recording(machine);
	2440	break;
2377	2441	}
	2442
	2443	/* advance time */
	2444	global.movie_next_frame_time = attotime_add(global.movie_next_frame_time, global.movie_frame_period);
	2445	global.movie_frame++;
2378	2446	}
2379	2447
2380		/* write the next frame */
2381		palette = (screen->machine->palette != NULL) ? palette_entry_list_adjusted(screen->machine->palette) : NULL;
2382		error = mng_capture_frame(mame_core_file(state->mng_file), &pnginfo, global.snap_bitmap, screen->machine->config->total_colors, palette);
2383		png_free(&pnginfo);
2384		if (error != PNGERR_NONE)
2385		video_mng_end_recording(screen);
2386
2387	2448	profiler_mark(PROFILER_END);
2388	2449	}
2389	2450	}
r2864	r2865
2399	2460	of an AVI movie
2400	2461	-------------------------------------------------*/
2401	2462
2402		void video_avi_begin_recording(con~~st dev~~ice_c~~onf~~ig sc~~ree~~n, const char name)
	2463	void video_avi_begin_recording(running_machine machine, const char name)
2403	2464	{
2404		screen_state *state = ~~get_safe_token(screen)~~;
	2465	screen_state *state = NULL;
2405	2466	avi_movie_info info;
2406	2467	mame_file *tempfile;
2407	2468	file_error filerr;
2408	2469	avi_error avierr;
2409	2470
2410	2471	/* close any existing movie file */
2411		if (state->avi_file != NULL)
2412		video_avi_end_recording(screen);
	2472	if (global.avi_file != NULL)
	2473	video_avi_end_recording(machine);
2413	2474
	2475	/* look up the primary screen */
	2476	if (machine->primary_screen != NULL)
	2477	state = get_safe_token(machine->primary_screen);
	2478
2414	2479	/* create a snapshot bitmap so we know what the target size is */
2415		create_snapshot_bitmap(~~screen~~);
	2480	create_snapshot_bitmap(NULL);
2416	2481
2417	2482	/* build up information about this new movie */
2418	2483	info.video_format = 0;
2419		info.video_timescale = 1000 * ATTOSECONDS_TO_HZ(state->frame_period);
	2484	info.video_timescale = 1000 * ((state != NULL) ? ATTOSECONDS_TO_HZ(state->frame_period) : DEFAULT_FRAME_RATE);
2420	2485	info.video_sampletime = 1000;
2421	2486	info.video_numsamples = 0;
2422	2487	info.video_width = global.snap_bitmap->width;
r2864	r2865
2425	2490
2426	2491	info.audio_format = 0;
2427	2492	info.audio_timescale = 1;
2428		info.audio_sampletime = ~~screen->~~machine->sample_rate;
	2493	info.audio_sampletime = machine->sample_rate;
2429	2494	info.audio_numsamples = 0;
2430	2495	info.audio_channels = 2;
2431	2496	info.audio_samplebits = 16;
2432		info.audio_samplerate = ~~screen->~~machine->sample_rate;
	2497	info.audio_samplerate = machine->sample_rate;
2433	2498
2434	2499	/* create a new temporary movie file */
2435	2500	if (name != NULL)
2436	2501	filerr = mame_fopen(SEARCHPATH_MOVIE, name, OPEN_FLAG_WRITE \| OPEN_FLAG_CREATE \| OPEN_FLAG_CREATE_PATHS, &tempfile);
2437	2502	else
2438		filerr = mame_fopen_next(screen->machine, SEARCHPATH_MOVIE, "avi", &tempfile);
2439		state->movie_frame = 0;
	2503	filerr = mame_fopen_next(machine, SEARCHPATH_MOVIE, "avi", &tempfile);
2440	2504
	2505	/* reset our tracking */
	2506	global.movie_frame = 0;
	2507	global.movie_next_frame_time = timer_get_time();
	2508	global.movie_frame_period = attotime_div(ATTOTIME_IN_SEC(1000), info.video_timescale);
	2509
2441	2510	/* if we succeeded, make a copy of the name and create the real file over top */
2442	2511	if (filerr == FILERR_NONE)
2443	2512	{
r2864	r2865
2445	2514	mame_fclose(tempfile);
2446	2515
2447	2516	/* create the file and free the string */
2448		avierr = avi_create(astring_c(fullname), &info, &sta~~te->~~avi_file);
	2517	avierr = avi_create(astring_c(fullname), &info, &global.avi_file);
2449	2518	astring_free(fullname);
2450	2519	}
2451	2520	}
r2864	r2865
2456	2525	a avi movie
2457	2526	-------------------------------------------------*/
2458	2527
2459		void video_avi_end_recording(con~~st dev~~ice_c~~onf~~ig *sc~~ree~~n)
	2528	void video_avi_end_recording(running_machine *machine)
2460	2529	{
2461		screen_state *state = get_safe_token(screen);
2462
2463	2530	/* close the file if it exists */
2464		if (sta~~te->~~avi_file != NULL)
	2531	if (global.avi_file != NULL)
2465	2532	{
2466		avi_close(state->avi_file);
2467		state->avi_file = NULL;
2468		state->movie_frame = 0;
	2533	avi_close(global.avi_file);
	2534	global.avi_file = NULL;
	2535	global.movie_frame = 0;
2469	2536	}
2470	2537	}
2471	2538
r2864	r2865
2475	2542	movie
2476	2543	-------------------------------------------------*/
2477	2544
2478		static void video_avi_record_frame(con~~st dev~~ice_c~~onf~~ig *sc~~ree~~n)
	2545	static void video_avi_record_frame(running_machine *machine)
2479	2546	{
2480		screen_state *state = get_safe_token(screen);
2481
2482	2547	/* only record if we have a file */
2483		if (sta~~te->~~avi_file != NULL)
	2548	if (global.avi_file != NULL)
2484	2549	{
	2550	attotime curtime = timer_get_time();
2485	2551	avi_error avierr;
2486	2552
2487	2553	profiler_mark(PROFILER_MOVIE_REC);
2488	2554
2489	2555	/* create the bitmap */
2490		create_snapshot_bitmap(~~screen~~);
	2556	create_snapshot_bitmap(NULL);
2491	2557
2492		/* write the next frame */
2493		avierr = avi_append_video_frame_rgb32(state->avi_file, global.snap_bitmap);
2494		if (avierr != AVIERR_NONE)
2495		video_avi_end_recording(screen);
	2558	/* loop until we hit the right time */
	2559	while (attotime_compare(global.movie_next_frame_time, curtime) <= 0)
	2560	{
	2561	/* write the next frame */
	2562	avierr = avi_append_video_frame_rgb32(global.avi_file, global.snap_bitmap);
	2563	if (avierr != AVIERR_NONE)
	2564	{
	2565	video_avi_end_recording(machine);
	2566	break;
	2567	}
2496	2568
	2569	/* advance time */
	2570	global.movie_next_frame_time = attotime_add(global.movie_next_frame_time, global.movie_frame_period);
	2571	global.movie_frame++;
	2572	}
	2573
2497	2574	profiler_mark(PROFILER_END);
2498	2575	}
2499	2576	}
r2864	r2865
2506	2583
2507	2584	void video_avi_add_sound(running_machine machine, const INT16 sound, int numsamples)
2508	2585	{
2509		const device_config *screen;
	2586	/* only record if we have a file */
	2587	if (global.avi_file != NULL)
	2588	{
	2589	avi_error avierr;
2510	2590
2511		/* loop over screens that might be recording */
2512		for (screen = video_screen_first(machine->config); screen != NULL; screen = video_screen_next(screen))
	2591	profiler_mark(PROFILER_MOVIE_REC);
	2592
	2593	/* write the next frame */
	2594	avierr = avi_append_sound_samples(global.avi_file, 0, sound + 0, numsamples, 1);
	2595	if (avierr == AVIERR_NONE)
	2596	avierr = avi_append_sound_samples(global.avi_file, 1, sound + 1, numsamples, 1);
	2597	if (avierr != AVIERR_NONE)
	2598	video_avi_end_recording(machine);
	2599
	2600	profiler_mark(PROFILER_END);
	2601	}
	2602	}
	2603
	2604
	2605
	2606	/***************************************************************************
	2607	CONFIGURATION HELPERS
	2608	***************************************************************************/
	2609
	2610	/*-------------------------------------------------
	2611	video_get_view_for_target - select a view
	2612	for a given target
	2613	-------------------------------------------------*/
	2614
	2615	int video_get_view_for_target(running_machine machine, render_target target, const char *viewname, int targetindex, int numtargets)
	2616	{
	2617	int viewindex = -1;
	2618
	2619	/* auto view just selects the nth view */
	2620	if (strcmp(viewname, "auto") != 0)
2513	2621	{
2514		screen_state *state = get_safe_token(screen);
2515
2516		/* only record if we have a file */
2517		if (state->avi_file != NULL)
	2622	/* scan for a matching view name */
	2623	for (viewindex = 0; ; viewindex++)
2518	2624	{
2519		avi_er~~ror~~ avierr;
	2625	const char *name = render_target_get_view_name(target, viewindex);
2520	2626
2521		profiler_mark(PROFILER_MOVIE_REC);
	2627	/* stop scanning when we hit NULL */
	2628	if (name == NULL)
	2629	{
	2630	viewindex = -1;
	2631	break;
	2632	}
	2633	if (mame_strnicmp(name, viewname, strlen(viewname)) == 0)
	2634	break;
	2635	}
	2636	}
2522	2637
2523		/* write the next frame */
2524		avierr = avi_append_sound_samples(state->avi_file, 0, sound + 0, numsamples, 1);
2525		if (avierr == AVIERR_NONE)
2526		avierr = avi_append_sound_samples(state->avi_file, 1, sound + 1, numsamples, 1);
2527		if (avierr != AVIERR_NONE)
2528		video_avi_end_recording(screen);
	2638	/* if we don't have a match, default to the nth view */
	2639	if (viewindex == -1)
	2640	{
	2641	int scrcount = video_screen_count(machine->config);
2529	2642
2530		profiler_mark(PROFILER_END);
	2643	/* if we have enough targets to be one per screen, assign in order */
	2644	if (numtargets >= scrcount)
	2645	{
	2646	/* find the first view with this screen and this screen only */
	2647	for (viewindex = 0; ; viewindex++)
	2648	{
	2649	UINT32 viewscreens = render_target_get_view_screens(target, viewindex);
	2650	if (viewscreens == (1 << targetindex))
	2651	break;
	2652	if (viewscreens == 0)
	2653	{
	2654	viewindex = -1;
	2655	break;
	2656	}
	2657	}
2531	2658	}
	2659
	2660	/* otherwise, find the first view that has all the screens */
	2661	if (viewindex == -1)
	2662	{
	2663	for (viewindex = 0; ; viewindex++)
	2664	{
	2665	UINT32 viewscreens = render_target_get_view_screens(target, viewindex);
	2666	if (viewscreens == (1 << scrcount) - 1)
	2667	break;
	2668	if (viewscreens == 0)
	2669	break;
	2670	}
	2671	}
2532	2672	}
	2673
	2674	/* make sure it's a valid view */
	2675	if (render_target_get_view_name(target, viewindex) == NULL)
	2676	viewindex = 0;
	2677
	2678	return viewindex;
2533	2679	}
2534	2680
2535	2681
r2864	r2865
2546	2692	#define DSTSHIFT_R 16
2547	2693	#define DSTSHIFT_G 8
2548	2694	#define DSTSHIFT_B 0
	2695	#define BILINEAR_FILTER 1
2549	2696
2550	2697	#include "rendersw.c"

src/emu/video.h
r2864	r2865
17	17	#include "mamecore.h"
18	18	#include "devintrf.h"
19	19	#include "timer.h"
	20	#include "render.h"
20	21
21	22
22	23	/***************************************************************************
r2864	r2865
255	256	/* ----- snapshots ----- */
256	257
257	258	/* save a snapshot of a given screen */
258		void video_screen_save_snapshot(const device_config screen, mame_file fp);
	259	void video_screen_save_snapshot(running_machine machine, const device_config screen, mame_file *fp);
259	260
260	261	/* save a snapshot of all the active screens */
261	262	void video_save_active_screen_snapshots(running_machine *machine);
r2864	r2865
263	264
264	265	/* ----- movie recording ----- */
265	266
266		int video_mng_is_movie_active(const device_config *screen);
267		void video_mng_begin_recording(const device_config screen, const char name);
268		void video_mng_end_recording(const device_config *screen);
	267	int video_mng_is_movie_active(running_machine *machine);
	268	void video_mng_begin_recording(running_machine machine, const char name);
	269	void video_mng_end_recording(running_machine *machine);
269	270
270		void video_avi_begin_recording(const device_config screen, const char name);
271		void video_avi_end_recording(const device_config *screen);
	271	void video_avi_begin_recording(running_machine machine, const char name);
	272	void video_avi_end_recording(running_machine *machine);
272	273	void video_avi_add_sound(running_machine machine, const INT16 sound, int numsamples);
273	274
	275
	276	/* ----- configuration helpers ----- */
	277
	278	/* select a view for a given target */
	279	int video_get_view_for_target(running_machine machine, render_target target, const char *viewname, int targetindex, int numtargets);
	280
274	281	#endif /* __VIDEO_H__ */

src/emu/inptport.c
r2864	r2865
1275	1275	input_port_value input_port_read(running_machine machine, const char tag)
1276	1276	{
1277	1277	const input_port_config *port = input_port_by_tag(machine->portconfig, tag);
	1278	assert_always(mame_get_phase(machine) != MAME_PHASE_INIT, "Input ports cannot be read at init time!");
1278	1279	if (port == NULL)
1279	1280	fatalerror("Unable to locate input port '%s'", tag);
1280	1281	return input_port_read_direct(port);
r2864	r2865
1290	1291	input_port_value input_port_read_safe(running_machine machine, const char tag, UINT32 defvalue)
1291	1292	{
1292	1293	const input_port_config *port = input_port_by_tag(machine->portconfig, tag);
	1294	assert_always(mame_get_phase(machine) != MAME_PHASE_INIT, "Input ports cannot be read at init time!");
1293	1295	return (port == NULL) ? defvalue : input_port_read_direct(port);
1294	1296	}
1295	1297
r2864	r2865
1302	1304	input_port_value input_port_read_indexed(running_machine *machine, int portnum)
1303	1305	{
1304	1306	const input_port_config *port = input_port_by_index(machine->portconfig, portnum);
	1307	assert_always(mame_get_phase(machine) != MAME_PHASE_INIT, "Input ports cannot be read at init time!");
1305	1308	return (port == NULL) ? 0 : input_port_read_direct(port);
1306	1309	}
1307	1310

src/emu/rendersw.c
r2864	r2865
171	171	16bpp source
172	172	-------------------------------------------------*/
173	173
174		INLINE UINT32 get_texel_palette16_nearest(const UINT16 tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv~~, const rgb_t palbase~~)
	174	INLINE UINT32 get_texel_palette16_nearest(const render_texinfo *texture, INT32 curu, INT32 curv)
175	175	{
176		return palbase[texbase[(curv >> 16) * texrp + (curu >> 16)]];
	176	const UINT16 texbase = (const UINT16 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 16);
	177	return texture->palette[texbase[0]];
177	178	}
178	179
179	180
r2864	r2865
183	184	16bpp source
184	185	-------------------------------------------------*/
185	186
186		INLINE UINT32 get_texel_palette16_bilinear(const UINT16 tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv~~, const rgb_t palbase~~)
	187	INLINE UINT32 get_texel_palette16_bilinear(const render_texinfo *texture, INT32 curu, INT32 curv)
187	188	{
	189	const UINT16 texbase = (const UINT16 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 16);
	190	INT32 u1 = (((curu >> 16) + 1) < texture->width) ? 1 : 0;
	191	INT32 v1 = (((curv >> 16) + 1) < texture->height) ? texture->rowpixels : 0;
188	192	rgb_t pix00, pix01, pix10, pix11;
189		texbase += (curv >> 16) * texrp + (curu >> 16);
190		pix00 = palbase[texbase[0]];
191		pix01 = palbase[texbase[1]];
192		pix10 = palbase[texbase[texrp + 0]];
193		pix11 = palbase[texbase[texrp + 1]];
	193
	194	pix00 = texture->palette[texbase[0]];
	195	pix01 = texture->palette[texbase[u1]];
	196	pix10 = texture->palette[texbase[v1]];
	197	pix11 = texture->palette[texbase[u1 + v1]];
194	198	return rgb_bilinear_filter(pix00, pix01, pix10, pix11, curu >> 8, curv >> 8);
195	199	}
196	200
r2864	r2865
200	204	nearest neighbor texel from a 15bpp RGB source
201	205	-------------------------------------------------*/
202	206
203		INLINE UINT32 get_texel_rgb15_nearest(const UINT16 *tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv)
	207	INLINE UINT32 get_texel_rgb15_nearest(const render_texinfo *texture, INT32 curu, INT32 curv)
204	208	{
205		return texbase[(curv >> 16) * texrp + (curu >> 16)];
	209	const UINT16 texbase = (const UINT16 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 16);
	210	return texbase[0];
206	211	}
207	212
208	213
r2864	r2865
212	217	source
213	218	-------------------------------------------------*/
214	219
215		INLINE UINT32 get_texel_rgb15_bilinear(const UINT16 *tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv)
	220	INLINE UINT32 get_texel_rgb15_bilinear(const render_texinfo *texture, INT32 curu, INT32 curv)
216	221	{
	222	const UINT16 texbase = (const UINT16 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 16);
	223	INT32 u1 = (((curu >> 16) + 1) < texture->width) ? 1 : 0;
	224	INT32 v1 = (((curv >> 16) + 1) < texture->height) ? texture->rowpixels : 0;
217	225	rgb_t pix00, pix01, pix10, pix11, filtered;
218		~~texbase += (curv >> 16) * texrp + (curu >> 16);~~
	226
219	227	pix00 = texbase[0];
220		pix01 = texbase[1];
221		pix10 = texbase[texrp + 0];
222		pix11 = texbase[texrp + 1];
	228	pix01 = texbase[u1];
	229	pix10 = texbase[v1];
	230	pix11 = texbase[u1 + v1];
223	231	pix00 = ((pix00 & 0x7fe0) << 6) \| (pix00 & 0x1f);
224	232	pix01 = ((pix01 & 0x7fe0) << 6) \| (pix01 & 0x1f);
225	233	pix10 = ((pix10 & 0x7fe0) << 6) \| (pix10 & 0x1f);
r2864	r2865
235	243	source (pixel is returned as Cr-Cb-Y
236	244	-------------------------------------------------*/
237	245
238		INLINE UINT32 get_texel_yuy16_nearest(const UINT16 *tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv)
	246	INLINE UINT32 get_texel_yuy16_nearest(const render_texinfo *texture, INT32 curu, INT32 curv)
239	247	{
240		const UINT16 spix = &texbase[(curv >> 16) texrp + (curu >> 17) * 2];
241		return (spix[(curu >> 16) & 1] >> 8) \| ((spix[0] & 0xff) << 8) \| ((spix[1] & 0xff) << 16);
	248	const UINT16 texbase = (const UINT16 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 17) * 2;
	249	return (texbase[(curu >> 16) & 1] >> 8) \| ((texbase[0] & 0xff) << 8) \| ((texbase[1] & 0xff) << 16);
242	250	}
243	251
244	252
r2864	r2865
248	256	source (pixel is returned as Cr-Cb-Y
249	257	-------------------------------------------------*/
250	258
251		INLINE UINT32 get_texel_yuy16_bilinear(const UINT16 *tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv)
	259	INLINE UINT32 get_texel_yuy16_bilinear(const render_texinfo *texture, INT32 curu, INT32 curv)
252	260	{
	261	const UINT16 texbase = (const UINT16 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 17) * 2;
	262	INT32 u1 = (((curu >> 16) + 1) < texture->width) ? 1 : 0;
	263	INT32 v1 = (((curv >> 16) + 1) < texture->height) ? texture->rowpixels : 0;
253	264	rgb_t pix00, pix01, pix10, pix11;
254		~~texbase += (curv >> 16) * texrp + (curu >> 17) * 2;~~
	265
255	266	if ((curu & 0x10000) == 0)
256	267	{
257	268	rgb_t cbcr = ((texbase[0] & 0xff) << 8) \| ((texbase[1] & 0xff) << 16);
258	269	pix00 = (texbase[0] >> 8) \| cbcr;
259		pix01 = (texbase[1] >> 8) \| cbcr;
260		cbcr = ((texbase[texrp + 0] & 0xff) << 8) \| ((texbase[texrp + 1] & 0xff) << 16);
261		pix10 = (texbase[texrp + 0] >> 8) \| cbcr;
262		pix11 = (texbase[texrp + 1] >> 8) \| cbcr;
	270	pix01 = u1 ? ((texbase[1] >> 8) \| cbcr) : pix00;
	271	cbcr = ((texbase[v1 + 0] & 0xff) << 8) \| ((texbase[v1 + 1] & 0xff) << 16);
	272	pix10 = (texbase[v1 + 0] >> 8) \| cbcr;
	273	pix11 = u1 ? ((texbase[v1 + 1] >> 8) \| cbcr) : pix10;
263	274	}
264	275	else
265	276	{
266	277	rgb_t cbcr = ((texbase[0] & 0xff) << 8) \| ((texbase[1] & 0xff) << 16);
267	278	pix00 = (texbase[1] >> 8) \| cbcr;
268		cbcr = ((texbase[2] & 0xff) << 8) \| ((texbase[3] & 0xff) << 16);
269		pix01 = (texbase[2] >> 8) \| cbcr;
270		cbcr = ((texbase[texrp + 0] & 0xff) << 8) \| ((texbase[texrp + 1] & 0xff) << 16);
271		pix10 = (texbase[texrp + 1] >> 8) \| cbcr;
272		cbcr = ((texbase[texrp + 2] & 0xff) << 8) \| ((texbase[texrp + 3] & 0xff) << 16);
273		pix11 = (texbase[texrp + 2] >> 8) \| cbcr;
	279	if (u1)
	280	{
	281	cbcr = ((texbase[2] & 0xff) << 8) \| ((texbase[3] & 0xff) << 16);
	282	pix01 = (texbase[2] >> 8) \| cbcr;
	283	}
	284	else
	285	pix01 = pix00;
	286	cbcr = ((texbase[v1 + 0] & 0xff) << 8) \| ((texbase[v1 + 1] & 0xff) << 16);
	287	pix10 = (texbase[v1 + 1] >> 8) \| cbcr;
	288	if (u1)
	289	{
	290	cbcr = ((texbase[v1 + 2] & 0xff) << 8) \| ((texbase[v1 + 3] & 0xff) << 16);
	291	pix11 = (texbase[v1 + 2] >> 8) \| cbcr;
	292	}
	293	else
	294	pix11 = pix10;
274	295	}
275	296	return rgb_bilinear_filter(pix00, pix01, pix10, pix11, curu >> 8, curv >> 8);
276	297	}
r2864	r2865
281	302	nearest neighbor texel from a 32bpp RGB source
282	303	-------------------------------------------------*/
283	304
284		INLINE UINT32 get_texel_rgb32_nearest(const UINT32 *tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv)
	305	INLINE UINT32 get_texel_rgb32_nearest(const render_texinfo *texture, INT32 curu, INT32 curv)
285	306	{
286		return texbase[(curv >> 16) * texrp + (curu >> 16)];
	307	const UINT32 texbase = (const UINT32 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 16);
	308	return texbase[0];
287	309	}
288	310
289	311
r2864	r2865
293	315	source
294	316	-------------------------------------------------*/
295	317
296		INLINE UINT32 get_texel_rgb32_bilinear(const UINT32 *tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv)
	318	INLINE UINT32 get_texel_rgb32_bilinear(const render_texinfo *texture, INT32 curu, INT32 curv)
297	319	{
	320	const UINT32 texbase = (const UINT32 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 16);
	321	INT32 u1 = (((curu >> 16) + 1) < texture->width) ? 1 : 0;
	322	INT32 v1 = (((curv >> 16) + 1) < texture->height) ? texture->rowpixels : 0;
298	323	rgb_t pix00, pix01, pix10, pix11;
299		~~texbase += (curv >> 16) * texrp + (curu >> 16);~~
	324
300	325	pix00 = texbase[0];
301		pix01 = texbase[1];
302		pix10 = texbase[texrp + 0];
303		pix11 = texbase[texrp + 1];
	326	pix01 = texbase[u1];
	327	pix10 = texbase[v1];
	328	pix11 = texbase[u1 + v1];
304	329	return rgb_bilinear_filter(pix00, pix01, pix10, pix11, curu >> 8, curv >> 8);
305	330	}
306	331
r2864	r2865
311	336	source
312	337	-------------------------------------------------*/
313	338
314		INLINE UINT32 get_texel_argb32_nearest(const UINT32 *tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv)
	339	INLINE UINT32 get_texel_argb32_nearest(const render_texinfo *texture, INT32 curu, INT32 curv)
315	340	{
316		return texbase[(curv >> 16) * texrp + (curu >> 16)];
	341	const UINT32 texbase = (const UINT32 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 16);
	342	return texbase[0];
317	343	}
318	344
319	345
r2864	r2865
323	349	source
324	350	-------------------------------------------------*/
325	351
326		INLINE UINT32 get_texel_argb32_bilinear(const UINT32 *tex~~base,~~ ~~INT32~~ texrp, INT32 curu, INT32 curv)
	352	INLINE UINT32 get_texel_argb32_bilinear(const render_texinfo *texture, INT32 curu, INT32 curv)
327	353	{
	354	const UINT32 texbase = (const UINT32 )texture->base + (curv >> 16) * texture->rowpixels + (curu >> 16);
	355	INT32 u1 = (((curu >> 16) + 1) < texture->width) ? 1 : 0;
	356	INT32 v1 = (((curv >> 16) + 1) < texture->height) ? texture->rowpixels : 0;
328	357	rgb_t pix00, pix01, pix10, pix11;
329		~~texbase += (curv >> 16) * texrp + (curu >> 16);~~
	358
330	359	pix00 = texbase[0];
331		pix01 = texbase[1];
332		pix10 = texbase[texrp + 0];
333		pix11 = texbase[texrp + 1];
	360	pix01 = texbase[u1];
	361	pix10 = texbase[v1];
	362	pix11 = texbase[u1 + v1];
334	363	return rgba_bilinear_filter(pix00, pix01, pix10, pix11, curu >> 8, curv >> 8);
335	364	}
336	365
r2864	r2865
701	730
702	731	static void FUNC_PREFIX(draw_quad_palette16_none)(const render_primitive prim, void dstdata, UINT32 pitch, quad_setup_data *setup)
703	732	{
704		UINT16 *texbase = prim->texture.base;
705		const rgb_t *palbase = prim->texture.palette;
706		UINT32 texrp = prim->texture.rowpixels;
707	733	INT32 dudx = setup->dudx;
708	734	INT32 dvdx = setup->dvdx;
709	735	INT32 endx = setup->endx;
710	736	INT32 x, y;
711	737
712	738	/* ensure all parameters are valid */
713		assert(pal~~bas~~e != NULL);
	739	assert(prim->texture.palette != NULL);
714	740
715	741	/* fast case: no coloring, no alpha */
716	742	if (prim->color.r >= 1.0f && prim->color.g >= 1.0f && prim->color.b >= 1.0f && IS_OPAQUE(prim->color.a))
r2864	r2865
725	751	/* loop over cols */
726	752	for (x = setup->startx; x < endx; x++)
727	753	{
728		UINT32 pix = GET_TEXEL(palette16)(tex~~base,~~ texrp, curu, curv~~, palbase~~);
	754	UINT32 pix = GET_TEXEL(palette16)(&prim->texture, curu, curv);
729	755	*dest++ = SOURCE32_TO_DEST(pix);
730	756	curu += dudx;
731	757	curv += dvdx;
r2864	r2865
755	781	/* loop over cols */
756	782	for (x = setup->startx; x < endx; x++)
757	783	{
758		UINT32 pix = GET_TEXEL(palette16)(tex~~base,~~ texrp, curu, curv~~, palbase~~);
	784	UINT32 pix = GET_TEXEL(palette16)(&prim->texture, curu, curv);
759	785	UINT32 r = (SOURCE32_R(pix) * sr) >> 8;
760	786	UINT32 g = (SOURCE32_G(pix) * sg) >> 8;
761	787	UINT32 b = (SOURCE32_B(pix) * sb) >> 8;
r2864	r2865
791	817	/* loop over cols */
792	818	for (x = setup->startx; x < endx; x++)
793	819	{
794		UINT32 pix = GET_TEXEL(palette16)(tex~~base,~~ texrp, curu, curv~~, palbase~~);
	820	UINT32 pix = GET_TEXEL(palette16)(&prim->texture, curu, curv);
795	821	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
796	822	UINT32 r = (SOURCE32_R(pix) * sr + DEST_R(dpix) * invsa) >> 8;
797	823	UINT32 g = (SOURCE32_G(pix) * sg + DEST_G(dpix) * invsa) >> 8;
r2864	r2865
813	839
814	840	static void FUNC_PREFIX(draw_quad_palette16_add)(const render_primitive prim, void dstdata, UINT32 pitch, quad_setup_data *setup)
815	841	{
816		UINT16 *texbase = prim->texture.base;
817		const rgb_t *palbase = prim->texture.palette;
818		UINT32 texrp = prim->texture.rowpixels;
819	842	INT32 dudx = setup->dudx;
820	843	INT32 dvdx = setup->dvdx;
821	844	INT32 endx = setup->endx;
822	845	INT32 x, y;
823	846
824	847	/* ensure all parameters are valid */
825		assert(pal~~bas~~e != NULL);
	848	assert(prim->texture.palette != NULL);
826	849
827	850	/* fast case: no coloring, no alpha */
828	851	if (prim->color.r >= 1.0f && prim->color.g >= 1.0f && prim->color.b >= 1.0f && IS_OPAQUE(prim->color.a))
r2864	r2865
837	860	/* loop over cols */
838	861	for (x = setup->startx; x < endx; x++)
839	862	{
840		UINT32 pix = GET_TEXEL(palette16)(tex~~base,~~ texrp, curu, curv~~, palbase~~);
	863	UINT32 pix = GET_TEXEL(palette16)(&prim->texture, curu, curv);
841	864	if ((pix & 0xffffff) != 0)
842	865	{
843	866	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
r2864	r2865
878	901	/* loop over cols */
879	902	for (x = setup->startx; x < endx; x++)
880	903	{
881		UINT32 pix = GET_TEXEL(palette16)(tex~~base,~~ texrp, curu, curv~~, palbase~~);
	904	UINT32 pix = GET_TEXEL(palette16)(&prim->texture, curu, curv);
882	905	if ((pix & 0xffffff) != 0)
883	906	{
884	907	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
r2864	r2865
910	933
911	934	static void FUNC_PREFIX(draw_quad_palettea16_alpha)(const render_primitive prim, void dstdata, UINT32 pitch, quad_setup_data *setup)
912	935	{
913		UINT16 *texbase = prim->texture.base;
914		const rgb_t *palbase = prim->texture.palette;
915		UINT32 texrp = prim->texture.rowpixels;
916	936	INT32 dudx = setup->dudx;
917	937	INT32 dvdx = setup->dvdx;
918	938	INT32 endx = setup->endx;
919	939	INT32 x, y;
920	940
921	941	/* ensure all parameters are valid */
922		assert(pal~~bas~~e != NULL);
	942	assert(prim->texture.palette != NULL);
923	943
924	944	/* fast case: no coloring, no alpha */
925	945	if (prim->color.r >= 1.0f && prim->color.g >= 1.0f && prim->color.b >= 1.0f && IS_OPAQUE(prim->color.a))
r2864	r2865
934	954	/* loop over cols */
935	955	for (x = setup->startx; x < endx; x++)
936	956	{
937		UINT32 pix = GET_TEXEL(palette16)(tex~~base,~~ texrp, curu, curv~~, palbase~~);
	957	UINT32 pix = GET_TEXEL(palette16)(&prim->texture, curu, curv);
938	958	UINT32 ta = pix >> 24;
939	959	if (ta != 0)
940	960	{
r2864	r2865
977	997	/* loop over cols */
978	998	for (x = setup->startx; x < endx; x++)
979	999	{
980		UINT32 pix = GET_TEXEL(palette16)(tex~~base,~~ texrp, curu, curv~~, palbase~~);
	1000	UINT32 pix = GET_TEXEL(palette16)(&prim->texture, curu, curv);
981	1001	UINT32 ta = (pix >> 24) * sa;
982	1002	if (ta != 0)
983	1003	{
r2864	r2865
1010	1030
1011	1031	static void FUNC_PREFIX(draw_quad_yuy16_none)(const render_primitive prim, void dstdata, UINT32 pitch, quad_setup_data *setup)
1012	1032	{
1013		UINT16 *texbase = prim->texture.base;
1014	1033	const rgb_t *palbase = prim->texture.palette;
1015		UINT32 texrp = prim->texture.rowpixels;
1016	1034	INT32 dudx = setup->dudx;
1017	1035	INT32 dvdx = setup->dvdx;
1018	1036	INT32 endx = setup->endx;
r2864	r2865
1034	1052	/* loop over cols */
1035	1053	for (x = setup->startx; x < endx; x++)
1036	1054	{
1037		UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(tex~~base,~~ texrp, curu, curv));
	1055	UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(&prim->texture, curu, curv));
1038	1056	*dest++ = SOURCE32_TO_DEST(pix);
1039	1057	curu += dudx;
1040	1058	curv += dvdx;
r2864	r2865
1047	1065	/* loop over cols */
1048	1066	for (x = setup->startx; x < endx; x++)
1049	1067	{
1050		UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(tex~~base,~~ texrp, curu, curv));
	1068	UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(&prim->texture, curu, curv));
1051	1069	*dest++ = SOURCE32_TO_DEST(pix);
1052	1070	curu += dudx;
1053	1071	curv += dvdx;
r2864	r2865
1081	1099	/* loop over cols */
1082	1100	for (x = setup->startx; x < endx; x++)
1083	1101	{
1084		UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(tex~~base,~~ texrp, curu, curv));
	1102	UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(&prim->texture, curu, curv));
1085	1103	UINT32 r = (SOURCE32_R(pix) * sr) >> 8;
1086	1104	UINT32 g = (SOURCE32_G(pix) * sg) >> 8;
1087	1105	UINT32 b = (SOURCE32_B(pix) * sb) >> 8;
r2864	r2865
1098	1116	/* loop over cols */
1099	1117	for (x = setup->startx; x < endx; x++)
1100	1118	{
1101		UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(tex~~base,~~ texrp, curu, curv));
	1119	UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(&prim->texture, curu, curv));
1102	1120	UINT32 r = (SOURCE32_R(pix) * sr) >> 8;
1103	1121	UINT32 g = (SOURCE32_G(pix) * sg) >> 8;
1104	1122	UINT32 b = (SOURCE32_B(pix) * sb) >> 8;
r2864	r2865
1138	1156	/* loop over cols */
1139	1157	for (x = setup->startx; x < endx; x++)
1140	1158	{
1141		UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(tex~~base,~~ texrp, curu, curv));
	1159	UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(&prim->texture, curu, curv));
1142	1160	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1143	1161	UINT32 r = (SOURCE32_R(pix) * sr + DEST_R(dpix) * invsa) >> 8;
1144	1162	UINT32 g = (SOURCE32_G(pix) * sg + DEST_G(dpix) * invsa) >> 8;
r2864	r2865
1156	1174	/* loop over cols */
1157	1175	for (x = setup->startx; x < endx; x++)
1158	1176	{
1159		UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(tex~~base,~~ texrp, curu, curv));
	1177	UINT32 pix = ycc_to_rgb(GET_TEXEL(yuy16)(&prim->texture, curu, curv));
1160	1178	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1161	1179	UINT32 r = (SOURCE32_R(pix) * sr + DEST_R(dpix) * invsa) >> 8;
1162	1180	UINT32 g = (SOURCE32_G(pix) * sg + DEST_G(dpix) * invsa) >> 8;
r2864	r2865
1183	1201
1184	1202	static void FUNC_PREFIX(draw_quad_rgb15)(const render_primitive prim, void dstdata, UINT32 pitch, quad_setup_data *setup)
1185	1203	{
1186		UINT16 *texbase = prim->texture.base;
1187	1204	const rgb_t *palbase = prim->texture.palette;
1188		UINT32 texrp = prim->texture.rowpixels;
1189	1205	INT32 dudx = setup->dudx;
1190	1206	INT32 dvdx = setup->dvdx;
1191	1207	INT32 endx = setup->endx;
r2864	r2865
1207	1223	/* loop over cols */
1208	1224	for (x = setup->startx; x < endx; x++)
1209	1225	{
1210		UINT32 pix = GET_TEXEL(rgb15)(tex~~base,~~ texrp, curu, curv);
	1226	UINT32 pix = GET_TEXEL(rgb15)(&prim->texture, curu, curv);
1211	1227	*dest++ = SOURCE15_TO_DEST(pix);
1212	1228	curu += dudx;
1213	1229	curv += dvdx;
r2864	r2865
1220	1236	/* loop over cols */
1221	1237	for (x = setup->startx; x < endx; x++)
1222	1238	{
1223		UINT32 pix = GET_TEXEL(rgb15)(tex~~base,~~ texrp, curu, curv);
	1239	UINT32 pix = GET_TEXEL(rgb15)(&prim->texture, curu, curv);
1224	1240	UINT32 r = palbase[(pix >> 10) & 0x1f] >> SRCSHIFT_R;
1225	1241	UINT32 g = palbase[(pix >> 5) & 0x1f] >> SRCSHIFT_G;
1226	1242	UINT32 b = palbase[(pix >> 0) & 0x1f] >> SRCSHIFT_B;
r2864	r2865
1258	1274	/* loop over cols */
1259	1275	for (x = setup->startx; x < endx; x++)
1260	1276	{
1261		UINT32 pix = GET_TEXEL(rgb15)(tex~~base,~~ texrp, curu, curv);
	1277	UINT32 pix = GET_TEXEL(rgb15)(&prim->texture, curu, curv);
1262	1278	UINT32 r = (SOURCE15_R(pix) * sr) >> 8;
1263	1279	UINT32 g = (SOURCE15_G(pix) * sg) >> 8;
1264	1280	UINT32 b = (SOURCE15_B(pix) * sb) >> 8;
r2864	r2865
1275	1291	/* loop over cols */
1276	1292	for (x = setup->startx; x < endx; x++)
1277	1293	{
1278		UINT32 pix = GET_TEXEL(rgb15)(tex~~base,~~ texrp, curu, curv);
	1294	UINT32 pix = GET_TEXEL(rgb15)(&prim->texture, curu, curv);
1279	1295	UINT32 r = (palbase[(pix >> 10) & 0x1f] * sr) >> (8 + SRCSHIFT_R);
1280	1296	UINT32 g = (palbase[(pix >> 5) & 0x1f] * sg) >> (8 + SRCSHIFT_G);
1281	1297	UINT32 b = (palbase[(pix >> 0) & 0x1f] * sb) >> (8 + SRCSHIFT_B);
r2864	r2865
1315	1331	/* loop over cols */
1316	1332	for (x = setup->startx; x < endx; x++)
1317	1333	{
1318		UINT32 pix = GET_TEXEL(rgb15)(tex~~base,~~ texrp, curu, curv);
	1334	UINT32 pix = GET_TEXEL(rgb15)(&prim->texture, curu, curv);
1319	1335	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1320	1336	UINT32 r = (SOURCE15_R(pix) * sr + DEST_R(dpix) * invsa) >> 8;
1321	1337	UINT32 g = (SOURCE15_G(pix) * sg + DEST_G(dpix) * invsa) >> 8;
r2864	r2865
1333	1349	/* loop over cols */
1334	1350	for (x = setup->startx; x < endx; x++)
1335	1351	{
1336		UINT32 pix = GET_TEXEL(rgb15)(tex~~base,~~ texrp, curu, curv);
	1352	UINT32 pix = GET_TEXEL(rgb15)(&prim->texture, curu, curv);
1337	1353	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1338	1354	UINT32 r = ((palbase[(pix >> 10) & 0x1f] >> SRCSHIFT_R) * sr + DEST_R(dpix) * invsa) >> 8;
1339	1355	UINT32 g = ((palbase[(pix >> 5) & 0x1f] >> SRCSHIFT_G) * sg + DEST_G(dpix) * invsa) >> 8;
r2864	r2865
1361	1377
1362	1378	static void FUNC_PREFIX(draw_quad_rgb32)(const render_primitive prim, void dstdata, UINT32 pitch, quad_setup_data *setup)
1363	1379	{
1364		UINT32 *texbase = prim->texture.base;
1365	1380	const rgb_t *palbase = prim->texture.palette;
1366		UINT32 texrp = prim->texture.rowpixels;
1367	1381	INT32 dudx = setup->dudx;
1368	1382	INT32 dvdx = setup->dvdx;
1369	1383	INT32 endx = setup->endx;
r2864	r2865
1385	1399	/* loop over cols */
1386	1400	for (x = setup->startx; x < endx; x++)
1387	1401	{
1388		UINT32 pix = GET_TEXEL(rgb32)(tex~~base,~~ texrp, curu, curv);
	1402	UINT32 pix = GET_TEXEL(rgb32)(&prim->texture, curu, curv);
1389	1403	*dest++ = SOURCE32_TO_DEST(pix);
1390	1404	curu += dudx;
1391	1405	curv += dvdx;
r2864	r2865
1398	1412	/* loop over cols */
1399	1413	for (x = setup->startx; x < endx; x++)
1400	1414	{
1401		UINT32 pix = GET_TEXEL(rgb32)(tex~~base,~~ texrp, curu, curv);
	1415	UINT32 pix = GET_TEXEL(rgb32)(&prim->texture, curu, curv);
1402	1416	UINT32 r = palbase[(pix >> 16) & 0xff] >> SRCSHIFT_R;
1403	1417	UINT32 g = palbase[(pix >> 8) & 0xff] >> SRCSHIFT_G;
1404	1418	UINT32 b = palbase[(pix >> 0) & 0xff] >> SRCSHIFT_B;
r2864	r2865
1436	1450	/* loop over cols */
1437	1451	for (x = setup->startx; x < endx; x++)
1438	1452	{
1439		UINT32 pix = GET_TEXEL(rgb32)(tex~~base,~~ texrp, curu, curv);
	1453	UINT32 pix = GET_TEXEL(rgb32)(&prim->texture, curu, curv);
1440	1454	UINT32 r = (SOURCE32_R(pix) * sr) >> 8;
1441	1455	UINT32 g = (SOURCE32_G(pix) * sg) >> 8;
1442	1456	UINT32 b = (SOURCE32_B(pix) * sb) >> 8;
r2864	r2865
1453	1467	/* loop over cols */
1454	1468	for (x = setup->startx; x < endx; x++)
1455	1469	{
1456		UINT32 pix = GET_TEXEL(rgb32)(tex~~base,~~ texrp, curu, curv);
	1470	UINT32 pix = GET_TEXEL(rgb32)(&prim->texture, curu, curv);
1457	1471	UINT32 r = (palbase[(pix >> 16) & 0xff] * sr) >> (8 + SRCSHIFT_R);
1458	1472	UINT32 g = (palbase[(pix >> 8) & 0xff] * sg) >> (8 + SRCSHIFT_G);
1459	1473	UINT32 b = (palbase[(pix >> 0) & 0xff] * sb) >> (8 + SRCSHIFT_B);
r2864	r2865
1493	1507	/* loop over cols */
1494	1508	for (x = setup->startx; x < endx; x++)
1495	1509	{
1496		UINT32 pix = GET_TEXEL(rgb32)(tex~~base,~~ texrp, curu, curv);
	1510	UINT32 pix = GET_TEXEL(rgb32)(&prim->texture, curu, curv);
1497	1511	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1498	1512	UINT32 r = (SOURCE32_R(pix) * sr + DEST_R(dpix) * invsa) >> 8;
1499	1513	UINT32 g = (SOURCE32_G(pix) * sg + DEST_G(dpix) * invsa) >> 8;
r2864	r2865
1511	1525	/* loop over cols */
1512	1526	for (x = setup->startx; x < endx; x++)
1513	1527	{
1514		UINT32 pix = GET_TEXEL(rgb32)(tex~~base,~~ texrp, curu, curv);
	1528	UINT32 pix = GET_TEXEL(rgb32)(&prim->texture, curu, curv);
1515	1529	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1516	1530	UINT32 r = ((palbase[(pix >> 16) & 0xff] >> SRCSHIFT_R) * sr + DEST_R(dpix) * invsa) >> 8;
1517	1531	UINT32 g = ((palbase[(pix >> 8) & 0xff] >> SRCSHIFT_G) * sg + DEST_G(dpix) * invsa) >> 8;
r2864	r2865
1539	1553
1540	1554	static void FUNC_PREFIX(draw_quad_argb32_alpha)(const render_primitive prim, void dstdata, UINT32 pitch, quad_setup_data *setup)
1541	1555	{
1542		UINT32 *texbase = prim->texture.base;
1543	1556	const rgb_t *palbase = prim->texture.palette;
1544		UINT32 texrp = prim->texture.rowpixels;
1545	1557	INT32 dudx = setup->dudx;
1546	1558	INT32 dvdx = setup->dvdx;
1547	1559	INT32 endx = setup->endx;
r2864	r2865
1563	1575	/* loop over cols */
1564	1576	for (x = setup->startx; x < endx; x++)
1565	1577	{
1566		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1578	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1567	1579	UINT32 ta = pix >> 24;
1568	1580	if (ta != 0)
1569	1581	{
r2864	r2865
1587	1599	/* loop over cols */
1588	1600	for (x = setup->startx; x < endx; x++)
1589	1601	{
1590		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1602	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1591	1603	UINT32 ta = pix >> 24;
1592	1604	if (ta != 0)
1593	1605	{
r2864	r2865
1634	1646	/* loop over cols */
1635	1647	for (x = setup->startx; x < endx; x++)
1636	1648	{
1637		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1649	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1638	1650	UINT32 ta = (pix >> 24) * sa;
1639	1651	if (ta != 0)
1640	1652	{
r2864	r2865
1659	1671	/* loop over cols */
1660	1672	for (x = setup->startx; x < endx; x++)
1661	1673	{
1662		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1674	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1663	1675	UINT32 ta = (pix >> 24) * sa;
1664	1676	if (ta != 0)
1665	1677	{
r2864	r2865
1688	1700
1689	1701	static void FUNC_PREFIX(draw_quad_argb32_multiply)(const render_primitive prim, void dstdata, UINT32 pitch, quad_setup_data *setup)
1690	1702	{
1691		UINT32 *texbase = prim->texture.base;
1692	1703	const rgb_t *palbase = prim->texture.palette;
1693		UINT32 texrp = prim->texture.rowpixels;
1694	1704	INT32 dudx = setup->dudx;
1695	1705	INT32 dvdx = setup->dvdx;
1696	1706	INT32 endx = setup->endx;
r2864	r2865
1716	1726	/* loop over cols */
1717	1727	for (x = setup->startx; x < endx; x++)
1718	1728	{
1719		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1729	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1720	1730	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1721	1731	UINT32 r = (SOURCE32_R(pix) * DEST_R(dpix)) >> (8 - SRCSHIFT_R);
1722	1732	UINT32 g = (SOURCE32_G(pix) * DEST_G(dpix)) >> (8 - SRCSHIFT_G);
r2864	r2865
1732	1742	/* loop over cols */
1733	1743	for (x = setup->startx; x < endx; x++)
1734	1744	{
1735		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1745	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1736	1746	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1737	1747	UINT32 r = (palbase[(pix >> 16) & 0xff] * DEST_R(dpix)) >> 8;
1738	1748	UINT32 g = (palbase[(pix >> 8) & 0xff] * DEST_G(dpix)) >> 8;
r2864	r2865
1771	1781	/* loop over cols */
1772	1782	for (x = setup->startx; x < endx; x++)
1773	1783	{
1774		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1784	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1775	1785	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1776	1786	UINT32 r = (SOURCE32_R(pix) * sr * DEST_R(dpix)) >> (16 - SRCSHIFT_R);
1777	1787	UINT32 g = (SOURCE32_G(pix) * sg * DEST_G(dpix)) >> (16 - SRCSHIFT_G);
r2864	r2865
1787	1797	/* loop over cols */
1788	1798	for (x = setup->startx; x < endx; x++)
1789	1799	{
1790		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1800	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1791	1801	UINT32 dpix = NO_DEST_READ ? 0 : *dest;
1792	1802	UINT32 r = (palbase[(pix >> 16) & 0xff] * sr * DEST_R(dpix)) >> 16;
1793	1803	UINT32 g = (palbase[(pix >> 8) & 0xff] * sg * DEST_G(dpix)) >> 16;
r2864	r2865
1810	1820
1811	1821	static void FUNC_PREFIX(draw_quad_argb32_add)(const render_primitive prim, void dstdata, UINT32 pitch, quad_setup_data *setup)
1812	1822	{
1813		UINT32 *texbase = prim->texture.base;
1814	1823	const rgb_t *palbase = prim->texture.palette;
1815		UINT32 texrp = prim->texture.rowpixels;
1816	1824	INT32 dudx = setup->dudx;
1817	1825	INT32 dvdx = setup->dvdx;
1818	1826	INT32 endx = setup->endx;
r2864	r2865
1838	1846	/* loop over cols */
1839	1847	for (x = setup->startx; x < endx; x++)
1840	1848	{
1841		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1849	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1842	1850	UINT32 ta = pix >> 24;
1843	1851	if (ta != 0)
1844	1852	{
r2864	r2865
1863	1871	/* loop over cols */
1864	1872	for (x = setup->startx; x < endx; x++)
1865	1873	{
1866		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1874	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1867	1875	UINT32 ta = pix >> 24;
1868	1876	if (ta != 0)
1869	1877	{
r2864	r2865
1911	1919	/* loop over cols */
1912	1920	for (x = setup->startx; x < endx; x++)
1913	1921	{
1914		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1922	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1915	1923	UINT32 ta = (pix >> 24) * sa;
1916	1924	if (ta != 0)
1917	1925	{
r2864	r2865
1936	1944	/* loop over cols */
1937	1945	for (x = setup->startx; x < endx; x++)
1938	1946	{
1939		UINT32 pix = GET_TEXEL(argb32)(tex~~base,~~ texrp, curu, curv);
	1947	UINT32 pix = GET_TEXEL(argb32)(&prim->texture, curu, curv);
1940	1948	UINT32 ta = (pix >> 24) * sa;
1941	1949	if (ta != 0)
1942	1950	{

src/emu/ui.c
r2864	r2865
322	322	show_disclaimer = FALSE;
323	323	#endif /* MESS */
324	324
325		/* disable everything if we are using -str */
326		if (!first_time \|\| (str > 0 && str < 60*5) \|\| machine->gamedrv == &driver_empty)
	325	/* disable everything if we are using -str for 300 or fewer seconds, or if we're the empty driver,
	326	or if we are debugging */
	327	if (!first_time \|\| (str > 0 && str < 60*5) \|\| machine->gamedrv == &driver_empty \|\| machine->debug_mode)
327	328	show_gameinfo = show_warnings = show_disclaimer = FALSE;
328	329
329	330	/* initialize the on-screen display system */
r2864	r2865
1321	1322	/* toggle movie recording */
1322	1323	if (input_ui_pressed(machine, IPT_UI_RECORD_MOVIE))
1323	1324	{
1324		if (!video_mng_is_movie_active(machine~~->primary_screen~~))
	1325	if (!video_mng_is_movie_active(machine))
1325	1326	{
1326		video_mng_begin_recording(machine~~->primary_screen~~, NULL);
	1327	video_mng_begin_recording(machine, NULL);
1327	1328	popmessage("REC START");
1328	1329	}
1329	1330	else
1330	1331	{
1331		video_mng_end_recording(machine~~->primary_screen~~);
	1332	video_mng_end_recording(machine);
1332	1333	popmessage("REC STOP");
1333	1334	}
1334	1335	}

src/emu/render.h
r2864	r2865
12	12	#ifndef __RENDER_H__
13	13	#define __RENDER_H__
14	14
15		#include "driver.h"
16	15	#include "osdepend.h"
17	16
18	17	#include <math.h>

src/mess/tools/messtest/testmess.c
r2864	r2865
235	235	/* did we find a live screen? */
236	236	if (screen != NULL)
237	237	{
238		video_screen_save_snapshot(screen, fp);
	238	video_screen_save_snapshot(screen->machine, screen, fp);
239	239	report_message(MSG_INFO, "Saved screenshot as %s", buf);
240	240	}
241	241	else

src/mess/osd/windows/tapedlg.c
r2864	r2865
17	17	#include "window.h"
18	18	#include "winutf8.h"
19	19	#include "uimess.h"
	20	#include "device.h"
20	21
21	22
	23
22	24	//============================================================
23	25	// STRUCTURES
24	26	//============================================================

src/mess/machine/pc.c
r2864	r2865
807	807	pc_set_irq_line( 1, state );
808	808	}
809	809
810		void mess_init_pc_common(UINT32 flags, void (set_keyb_int_func)(int), void (set_hdc_int_func)(int,int)) {
811		init_pc_common(flags, set_keyb_int_func);
	810	void mess_init_pc_common(UINT32 flags, void (set_keyb_int_func)(int), void (set_hdc_int_func)(int,int))
	811	{
	812	init_pc_common(Machine, flags, set_keyb_int_func);
812	813
813	814	/* MESS managed RAM */
814	815	if ( mess_ram )

src/mess/drivers/pcw16.c
r2864	r2865
1364	1364	pc_mouse_set_serial_port( device_list_find_by_tag( machine->config->devicelist, NS16550, "ns16550_0" ) );
1365	1365
1366	1366	/* initialise keyboard */
1367		at_keyboard_init(AT_KEYBOARD_TYPE_AT);
	1367	at_keyboard_init(machine, AT_KEYBOARD_TYPE_AT);
1368	1368	at_keyboard_set_scan_code_set(3);
1369	1369
1370	1370	pcw16_reset(machine);

src/mess/drivers/n64.c
r2864	r2865
71	71
72	72	static INTERRUPT_GEN( n64_vblank )
73	73	{
74		signal_rcp_interrupt(VI_INTERRUPT);
	74	signal_rcp_interrupt(machine, VI_INTERRUPT);
75	75	}
76	76
77	77	static MACHINE_RESET( n64 )
78	78	{
79		n64_machine_reset();
	79	n64_machine_reset(machine);
80	80	}
81	81
82	82	static MACHINE_DRIVER_START( n64 )

src/mess/drivers/ip22.c
r2864	r2865
1457	1457
1458	1458	// IP22 uses 2 pieces of PC-compatible hardware: the 8042 PS/2 keyboard/mouse
1459	1459	// interface and the 8254 PIT. Both are licensed cores embedded in the IOC custom chip.
1460		init_pc_common(PCCOMMON_KEYBOARD_AT, NULL);
	1460	init_pc_common(machine, PCCOMMON_KEYBOARD_AT, NULL);
1461	1461	kbdc8042_init(&at8042);
1462	1462
1463	1463	nIOC_ParReadCnt = 0;

src/mess/drivers/saturn.c
r2864	r2865
1238	1238	/DSP section/
1239	1239	/Use functions so it is easier to work out/
1240	1240	case 32:
1241		dsp_prg_ctrl(data);
	1241	dsp_prg_ctrl(machine, data);
1242	1242	if(LOG_SCU) logerror("SCU DSP: Program Control Port Access %08x\n",data);
1243	1243	break;
1244	1244	case 33:

docs/messnew.txt
r2864	r2865
130	130
131	131	Source Changes:
132	132	----------------
133		- The core is based on MAME 0.125u5. This incorporates all features of the
	133	- The core is based on MAME 0.125u6. This incorporates all features of the
134	134	update to this core. [MAME team]
135	135
136	136	- Fixed performance problems with -triplebuffer. (bug #1539) [Justin Kerk]

15994 Revisions