src/mess/machine/c128.c
| r2802 | r2803 | |
|---|
| 133 | 133 | |
| 134 | 134 | static READ8_HANDLER( c128_read_io ) |
| 135 | 135 | { |
| 136 | | switch ((offset&0xf00)>>8) { |
| 137 | | case 0:case 1: case 2: case 3: |
| 136 | if (offset < 0x400) |
| 138 | 137 | return vic2_port_r (machine, offset & 0x3ff); |
| 139 | | case 4: |
| 138 | else if (offset < 0x500) |
| 140 | 139 | return sid6581_0_port_r (machine, offset & 0xff); |
| 141 | | case 5: |
| 140 | else if (offset < 0x600) |
| 142 | 141 | return c128_mmu8722_port_r (machine, offset & 0xff); |
| 143 | | case 6:case 7: |
| 142 | else if (offset < 0x800) |
| 144 | 143 | return vdc8563_port_r (machine, offset & 0xff); |
| 145 | | case 8: case 9: case 0xa: case 0xb: |
| 144 | |
| 146 | 145 | return c64_colorram[offset & 0x3ff]; |
| 147 | | case 0xc: |
| 146 | else if (offset == 0xc00) |
| 147 | { |
| 148 | cia_set_port_mask_value(0, 0, input_port_read(Machine, "DSW0") & 0x0100 ? c64_keyline[8] : c64_keyline[9] ); |
| 149 | return cia_0_r(machine, offset); |
| 150 | } |
| 151 | else if (offset == 0xc01) |
| 152 | { |
| 153 | cia_set_port_mask_value(0, 1, input_port_read(Machine, "DSW0") & 0x0100 ? c64_keyline[9] : c64_keyline[8] ); |
| 154 | return cia_0_r(machine, offset); |
| 155 | } |
| 156 | else if (offset < 0xd00) |
| 148 | 157 | return cia_0_r(machine, offset); |
| 149 | | case 0xd: |
| 158 | else if (offset < 0xe00) |
| 150 | 159 | return cia_1_r(machine, offset); |
| 151 | | case 0xf: |
| 160 | else if ((offset >= 0xf00) & (offset <= 0xfff)) |
| 152 | 161 | return c128_dma8726_port_r(machine, offset&0xff); |
| 153 | | case 0xe:default: |
| 154 | | DBG_LOG (1, "io read", ("%.3x\n", offset)); |
| 155 | | return 0xff; |
| 156 | | } |
| 162 | DBG_LOG (1, "io read", ("%.3x\n", offset)); |
| 163 | return 0xff; |
| 157 | 164 | } |
| 158 | 165 | |
| 159 | 166 | void c128_bankswitch_64 (running_machine *machine, int reset) |