src/mess/machine/hd63450.c
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| 5 | 5 | */ |
| 6 | 6 | |
| 7 | 7 | #include "machine/hd63450.h" |
| 8 | | #include "deprecat.h" |
| 9 | 8 | |
| 10 | 9 | |
| 11 | 10 | static struct hd63450 dmac; |
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| 29 | 28 | } |
| 30 | 29 | } |
| 31 | 30 | |
| 32 | | int hd63450_read(int offset, UINT16 mem_mask) |
| 31 | int hd63450_read(running_machine *machine, int offset, UINT16 mem_mask) |
| 33 | 32 | { |
| 34 | 33 | int channel,reg; |
| 35 | 34 | |
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| 78 | 77 | return 0xff; |
| 79 | 78 | } |
| 80 | 79 | |
| 81 | | void hd63450_write(int offset, int data, UINT16 mem_mask) |
| 80 | void hd63450_write(running_machine *machine, int offset, int data, UINT16 mem_mask) |
| 82 | 81 | { |
| 83 | 82 | int channel,reg; |
| 84 | 83 | |
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| 116 | 115 | { |
| 117 | 116 | dmac.reg[channel].ccr = data & 0x00ff; |
| 118 | 117 | if((data & 0x0080))// && !dmac.intf->dma_read[channel] && !dmac.intf->dma_write[channel]) |
| 119 | | dma_transfer_start(Machine, channel,0); |
| 118 | dma_transfer_start(machine, channel,0); |
| 120 | 119 | if(data & 0x0010) // software abort |
| 121 | 120 | dma_transfer_abort(channel); |
| 122 | 121 | if(data & 0x0020) // halt operation |
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| 388 | 387 | } |
| 389 | 388 | |
| 390 | 389 | |
| 391 | | READ16_HANDLER(hd63450_r) { return hd63450_read(offset,mem_mask); } |
| 392 | | WRITE16_HANDLER(hd63450_w) { hd63450_write(offset,data,mem_mask); } |
| 390 | READ16_HANDLER(hd63450_r) { return hd63450_read(machine,offset,mem_mask); } |
| 391 | WRITE16_HANDLER(hd63450_w) { hd63450_write(machine,offset,data,mem_mask); } |
| 393 | 392 | |
src/mess/machine/hd63450.h
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| 46 | 46 | }; |
| 47 | 47 | |
| 48 | 48 | void hd63450_init(const struct hd63450_interface* intf); |
| 49 | | int hd63450_read(int offset, UINT16 mem_mask); |
| 50 | | void hd63450_write(int offset, int data, UINT16 mem_mask); |
| 49 | int hd63450_read(running_machine *machine, int offset, UINT16 mem_mask); |
| 50 | void hd63450_write(running_machine *machine,int offset, int data, UINT16 mem_mask); |
| 51 | 51 | void hd63450_single_transfer(running_machine *machine, int x); |
| 52 | 52 | |
| 53 | 53 | void dma_transfer_start(running_machine *machine, int channel, int dir); |