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r15892 Tuesday 14th August, 2012 at 10:30:53 UTC by Barry Rodewald
pcw16: Fixed power switch regression, and reworked memory banking to be faster under heavy use. (no whatsnew)
[src/mess/drivers]pcw16.c
[src/mess/includes]pcw16.h

src/mess/includes/pcw16.h
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8080   DECLARE_READ8_MEMBER(pcw16_superio_fdc_data_r);
8181   DECLARE_READ8_MEMBER(pcw16_superio_fdc_main_status_register_r);
8282   DECLARE_READ8_MEMBER(pcw16_superio_fdc_digital_input_register_r);
83   DECLARE_READ8_MEMBER(pcw16_mem_r);
84   DECLARE_WRITE8_MEMBER(pcw16_mem_w);
8385   void pcw16_keyboard_init();
8486   void pcw16_keyboard_refresh_outputs();
8587   void pcw16_keyboard_set_clock_state(int state);
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8991   void pcw16_keyboard_signal_byte_received(int data);
9092   void pcw16_refresh_ints();
9193   void rtc_setup_max_days();
94   UINT8 pcw16_read_mem(UINT8 bank, UINT16 offset);
95   void pcw16_write_mem(UINT8 bank, UINT16 offset, UINT8 data);
96   UINT8 read_bank_data(UINT8 type, UINT16 offset);
97   void write_bank_data(UINT8 type, UINT16 offset, UINT8 data);
9298};
9399
94100
src/mess/drivers/pcw16.c
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152152}
153153
154154static ADDRESS_MAP_START(pcw16_map, AS_PROGRAM, 8, pcw16_state )
155   AM_RANGE(0x0000, 0x3fff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank5")
156   AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE_BANK("bank6")
157   AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank7")
158   AM_RANGE(0xc000, 0xffff) AM_READ_BANK("bank4") AM_WRITE_BANK("bank8")
155   AM_RANGE(0x0000, 0xffff) AM_READWRITE(pcw16_mem_r, pcw16_mem_w)
156//   AM_RANGE(0x0000, 0x3fff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank5")
157//   AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE_BANK("bank6")
158//   AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank7")
159//   AM_RANGE(0xc000, 0xffff) AM_READ_BANK("bank4") AM_WRITE_BANK("bank8")
159160ADDRESS_MAP_END
160161
161162
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365366   return 0x0ff;
366367}
367368
369/*
368370static void pcw16_set_bank_handlers(running_machine &machine, int bank, PCW16_RAM_TYPE type)
369371{
370372   address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
371373   pcw16_state *state = machine.driver_data<pcw16_state>();
372374   switch (type) {
373375   case PCW16_MEM_ROM:
374      /* rom */
376      // rom
375377      space->install_read_bank((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_read_handler_dram[bank]);
376378      space->nop_write((bank * 0x4000), (bank * 0x4000) + 0x3fff);
377379      break;
378380
379381   case PCW16_MEM_FLASH_1:
380      /* sram */
382      // sram
381383      space->install_legacy_read_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash0_bank_handlers_r[bank].func, pcw16_flash0_bank_handlers_r[bank].name);
382384      space->install_legacy_write_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash0_bank_handlers_w[bank].func, pcw16_flash0_bank_handlers_w[bank].name);
383385      break;
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394396
395397   default:
396398   case PCW16_MEM_DRAM:
397      /* dram */
399      // dram
398400      space->install_read_bank((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_read_handler_dram[bank]);
399401      space->install_write_bank((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_write_handler_dram[bank]);
400402      break;
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411413   char bank1[10];
412414   char bank2[10];
413415
414   /* get memory bank */
416   // get memory bank
415417   bank_id = state->m_banks[bank];
416418
417419
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421423
422424      if (bank_id<4)
423425      {
424         /* lower 4 banks are write protected. Use the rom
425            loaded */
426         //lower 4 banks are write protected. Use the rom
427            //loaded
426428         mem_ptr = &state->memregion("maincpu")->base()[0x010000];
427429      }
428430      else
429431      {
430432         intelfsh8_device *flashdev;
431433
432         /* nvram */
434         // nvram
433435         if ((bank_id & 0x040)==0)
434436         {
435437            flashdev = machine.device<intelfsh8_device>("flash0");
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446448   else
447449   {
448450      bank_offs = 128;
449      /* dram */
451      //dram
450452      mem_ptr = machine.device<ram_device>(RAM_TAG)->pointer();
451453   }
452454
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459461
460462   if ((bank_id & 0x080)==0)
461463   {
462      /* selections 0-3 within the first 64k are write protected */
464      // selections 0-3 within the first 64k are write protected
463465      if (bank_id<4)
464466      {
465         /* rom */
467         // rom
466468         pcw16_set_bank_handlers(machine, bank, PCW16_MEM_ROM);
467469      }
468470      else
469471      {
470         /* selections 0-63 are for flash-rom 0, selections
471            64-128 are for flash-rom 1 */
472         // selections 0-63 are for flash-rom 0, selections
473            // 64-128 are for flash-rom 1
472474         if ((bank_id & 0x040)==0)
473475         {
474476            pcw16_set_bank_handlers(machine, bank, PCW16_MEM_FLASH_1);
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484486      pcw16_set_bank_handlers(machine, bank, PCW16_MEM_DRAM);
485487   }
486488}
489*/
487490
488
489491/* update memory h/w */
490492static void pcw16_update_memory(running_machine &machine)
491493{
492   pcw16_update_bank(machine, 0);
493   pcw16_update_bank(machine, 1);
494   pcw16_update_bank(machine, 2);
495   pcw16_update_bank(machine, 3);
494//   pcw16_update_bank(machine, 0);
495//   pcw16_update_bank(machine, 1);
496//   pcw16_update_bank(machine, 2);
497//   pcw16_update_bank(machine, 3);
496498
497499}
498500
501UINT8 pcw16_state::read_bank_data(UINT8 type, UINT16 offset)
502{
503   if(type & 0x80) // DRAM
504   {
505      UINT8* RAM = machine().device<ram_device>(RAM_TAG)->pointer();
506      return RAM[((type & 0x7f)*0x4000) + offset];
507   }
508   else  // ROM / Flash
509   {
510      if(type < 4)
511      {
512         UINT8* ROM = memregion("maincpu")->base();
513         return ROM[((type & 0x03)*0x4000)+offset+0x10000];
514      }
515      if(type < 0x40)  // first flash
516      {
517         intel_e28f008sa_device* flash = machine().device<intel_e28f008sa_device>("flash0");
518         return flash->read(((type & 0x3f)*0x4000)+offset);
519      }
520      else  // second flash
521      {
522         intel_e28f008sa_device* flash = machine().device<intel_e28f008sa_device>("flash1");
523         return flash->read(((type & 0x3f)*0x4000)+offset);
524      }
525   }
526}
527
528void pcw16_state::write_bank_data(UINT8 type, UINT16 offset, UINT8 data)
529{
530   if(type & 0x80) // DRAM
531   {
532      UINT8* RAM = machine().device<ram_device>(RAM_TAG)->pointer();
533      RAM[((type & 0x7f)*0x4000) + offset] = data;
534   }
535   else  // ROM / Flash
536   {
537      if(type < 4)
538         return;  // first four sectors are write protected
539      if(type < 0x40)  // first flash
540      {
541         intel_e28f008sa_device* flash = machine().device<intel_e28f008sa_device>("flash0");
542         flash->write(((type & 0x3f)*0x4000)+offset,data);
543      }
544      else  // second flash
545      {
546         intel_e28f008sa_device* flash = machine().device<intel_e28f008sa_device>("flash1");
547         flash->write(((type & 0x3f)*0x4000)+offset,data);
548      }
549   }
550}
551
552UINT8 pcw16_state::pcw16_read_mem(UINT8 bank, UINT16 offset)
553{
554   switch(bank)
555   {
556   case 0:
557      return read_bank_data(m_banks[bank],offset);
558   case 1:
559      return read_bank_data(m_banks[bank],offset);
560   case 2:
561      return read_bank_data(m_banks[bank],offset);
562   case 3:
563      return read_bank_data(m_banks[bank],offset);
564   }
565   return 0xff;
566}
567
568void pcw16_state::pcw16_write_mem(UINT8 bank, UINT16 offset, UINT8 data)
569{
570   switch(bank)
571   {
572   case 0:
573      write_bank_data(m_banks[bank],offset,data);
574      break;
575   case 1:
576      write_bank_data(m_banks[bank],offset,data);
577      break;
578   case 2:
579      write_bank_data(m_banks[bank],offset,data);
580      break;
581   case 3:
582      write_bank_data(m_banks[bank],offset,data);
583      break;
584   }
585}
586
587READ8_MEMBER(pcw16_state::pcw16_mem_r)
588{
589   if(offset < 0x4000)
590      return pcw16_read_mem(0,offset);
591   if(offset >= 0x4000 && offset < 0x8000)
592      return pcw16_read_mem(1,offset-0x4000);
593   if(offset >= 0x8000 && offset < 0xc000)
594      return pcw16_read_mem(2,offset-0x8000);
595   if(offset >= 0xc000 && offset < 0x10000)
596      return pcw16_read_mem(3,offset-0xc000);
597
598   return 0xff;
599}
600
601WRITE8_MEMBER(pcw16_state::pcw16_mem_w)
602{
603   if(offset < 0x4000)
604      pcw16_write_mem(0,offset,data);
605   if(offset >= 0x4000 && offset < 0x8000)
606      pcw16_write_mem(1,offset-0x4000,data);
607   if(offset >= 0x8000 && offset < 0xc000)
608      pcw16_write_mem(2,offset-0x8000,data);
609   if(offset >= 0xc000 && offset < 0x10000)
610      pcw16_write_mem(3,offset-0xc000,data);
611}
612
499613READ8_MEMBER(pcw16_state::pcw16_bankhw_r)
500614{
501615//  logerror("bank r: %d \n", offset);
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785899      }
786900   }
787901   // TODO: fix
788   state->subdevice<ns16550_device>("ns16550_2")->ri_w(timer.machine().root_device().ioport("EXTRA")->read() & 0x040);
902   state->subdevice<ns16550_device>("ns16550_2")->ri_w((timer.machine().root_device().ioport("EXTRA")->read() & 0x040) ? 0 : 1);
789903}
790904
791905
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12921406   pc_fdc_set_tc_state(machine, 0);
12931407   /* select first rom page */
12941408   state->m_banks[0] = 0;
1295   pcw16_update_memory(machine);
1409//   pcw16_update_memory(machine);
12961410
12971411   /* temp rtc setup */
12981412   state->m_rtc_seconds = 0;

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