src/mess/drivers/vk100.c
| r15801 | r15802 | |
|---|
| 158 | 158 | UINT16 m_vgERR; // error register can cause carries which need to be caught |
| 159 | 159 | UINT8 m_vgSOPS; |
| 160 | 160 | UINT8 m_vgPAT; |
| 161 | | UINT16 m_vgPAT_Mask; // current mask for PAT but <<1 |
| 161 | UINT16 m_vgPAT_Mask; // current mask for PAT |
| 162 | 162 | UINT8 m_vgPMUL; // reload value for PMUL_Count |
| 163 | 163 | UINT8 m_vgPMUL_Count; |
| 164 | 164 | UINT8 m_vgDownCount; // down counter = number of pixels, loaded from vgDU on execute |
| r15801 | r15802 | |
|---|
| 1072 | 1072 | * the vector rom bits are complex and are unfortunately poorly documented |
| 1073 | 1073 | * in the tech manual. see figure 5-23. |
| 1074 | 1074 | * control bits: |
| 1075 | | * /CE1 ----- ? |
| 1076 | | * /CE2 ----- ? |
| 1075 | * /CE1 ----- /GO aka GO L |
| 1076 | * /CE2 ----- GND |
| 1077 | 1077 | * addr bits: 76543210 |
| 1078 | 1078 | * ||||\\\\-- To sync counter, which counts 0xC 0x3 0x2 0x1 0x0 0x5 0x4 0xB 0xA 0x9 0x8 0xD in that order |
| 1079 | 1079 | * |||\------ A0\__Address lsb bits of the execute write, i.e. VG_MODE; these are INVERTED FIRST. |
| r15801 | r15802 | |
|---|
| 1083 | 1083 | * |
| 1084 | 1084 | * data bits: 76543210 |
| 1085 | 1085 | * |||||||\-- /WRITE aka WRITE L (fig 5-20, page 5-32, writes the post-pattern-converted value back to vram at X,Y) |
| 1086 | | * ||||||\--- ? vector clk |
| 1087 | | * |||||\---- ? vector clk |
| 1086 | * ||||||\--- DONE L [verified via tracing] |
| 1087 | * |||||\---- VECTOR CLK [verified via tracing] |
| 1088 | 1088 | * ||||\----- /LD ERROR aka STROBE ERROR L (strobes the adder result value into the vgERR register) |
| 1089 | | * |||\------ ? done l? |
| 1089 | * |||\------ D-LOAD [by process of elimination and limited tracing] |
| 1090 | 1090 | * ||\------- ERASE L (latched, forces a4 on the sync rom low and also forces a7 on the ras/erase rom; the counter rom may be involved in blanking all of vram) [verified from tracing] |
| 1091 | | * |\-------- C0 aka C IN (high during DVM read, low otherwise, likely a carry in to the adder so DVM is converted from 1s to 2s complement) |
| 1092 | | * \--------- ?D LOAD? (goes to the clock of a d-latch near the register file) |
| 1093 | | * |
| 1091 | * |\-------- C0 aka C IN (high during DVM read, low otherwise, a carry in to the adder so DVM is converted from 1s to 2s complement) |
| 1092 | * \--------- SHIFT ENA [verified via tracing] |
| 1093 | * The data bits all have pull-ups to +5v if the /CE1 pin is not low |
| 1094 | 1094 | * According to the VT125 tech manual (vt100 tech manual rev 3, page 6-85) the 8 signals here are: |
| 1095 | 1095 | * ERASE L - d5 |
| 1096 | | * SHIFT ENA |
| 1096 | * SHIFT ENA - d7 |
| 1097 | 1097 | * C IN - d6 |
| 1098 | | * D LOAD - possibly d7? |
| 1098 | * D LOAD - |
| 1099 | 1099 | * WRITE L - d0 |
| 1100 | | * DONE L |
| 1101 | | * VECTOR CLK - likely d2 or d1 |
| 1100 | * DONE L - d1 |
| 1101 | * VECTOR CLK - d2 |
| 1102 | 1102 | * STROBE ERROR L - d3 |
| 1103 | 1103 | * |
| 1104 | 1104 | * it is possible d2 or d1 is the SYNC bit instead of one of the above |