MESS SVN History

15994 Revisions

r15705 Monday 30th July, 2012 at 08:40:42 UTC by Miodrag Milanović
Clean-ups and version bump

[src]	version.c
[src/emu/cpu/f8]	f8.c
[src/emu/cpu/m6800]	m6800.c
[src/emu/cpu/powerpc]	ppccom.c
[src/emu/cpu/tlcs900]	tlcs900.c
[src/emu/cpu/tms32025]	tms32025.c
[src/emu/cpu/tms32051]	32051ops.c
[src/emu/cpu/v30mz]	v30mz.c
[src/emu/machine]	am9517a.c net_lib.c net_lib.h netlist.c netlist.h roc10937.c roc10937.h tc009xlvc.c tc009xlvc.h
[src/mame]	mame.lst mame.mak
[src/mame/drivers]	aces1.c acesp.c bfm_sc1.c bfm_sc2.c bfmsys85.c cobra.c cybertnk.c cyclemb.c dfruit.c esd16.c globalfr.c globalvr.c jpmmps.c jpms80.c jpmsru.c lastbank.c mpu3.c mpu4.c mpu5.c namcos21.c pokechmp.c pong.c proconn.c segaxbd.c sfbonus.c taito_l.c taitotz.c tasman.c wardner.c
[src/mame/includes]	esd16.h
[src/mame/machine]	bfm_bd1.c bfm_bd1.h bfm_bda.c bfm_bda.h
[src/mame/video]	taitojc.c
[src/mess/drivers]	alesis.c digel804.c pc.c pc8801.c vk100.c vt100.c x1.c
[src/mess/machine]	llc.c pc.c
[src/mess/video]	uv201.c
[src/osd/sdl]	input.c sdl.mak

src/mame/mame.lst
r15704	r15705
19369	19369	m5clubsn14 //
19370	19370	m5clubsn16 //
19371	19371	m5dick // Dick Turnip (Bwb)
	19372	m5dick10
19372	19373	m5donna // Donna Kebab (Bwb)
19373	19374	m5donnad //
19374	19375	m5donnaa //
r15704	r15705
19413	19414	m5sil7 // Silver 7s (Bwb)
19414	19415	m5sil7a //
19415	19416	m5smobik // Smokey Bikin (Bwb)
	19417	m5smobik12
19416	19418	m5tictac // Tic Tac Tut (Vivid)
19417	19419	m5tictacbwb // Tic Tac Tut (Bwb)
19418	19420	m5tictacbwb16 //
r15704	r15705
19761	19763	sp_tzfet //
19762	19764	sp_tzfeu //
19763	19765	sp_beau // Beau Peep (Ace)
19764		sp_beaua //
19765		sp_beaub //
19766		sp_beauc //
19767		sp_beaud //
19768		sp_beaue //
19769		sp_beauf //
19770		sp_beaug //
19771		sp_beauh //
	19766	sp_beaua //
	19767	sp_beaub //
	19768	sp_beauc //
	19769	sp_beaud //
	19770	sp_beaue //
	19771	sp_beauf //
	19772	sp_beaug //
	19773	sp_beauh //
19772	19774	sp_bigbd // Big Break Deluxe Club (Ace)
19773	19775	sp_bigbda //
19774	19776	sp_brkbk // Break The Bank (Ace)
r15704	r15705
19863	19865	sp_golda // Golden Arrow Club (Ace)
19864	19866	sp_goldaa //
19865	19867	sp_golds // Golden Streak (Ace)
19866		sp_goldsa //
19867		sp_goldsb //
19868		sp_goldsc //
19869		sp_goldsd //
19870		sp_goldse //
19871		sp_goldsf //
19872		sp_goldsg //
19873		sp_goldsh //
	19868	sp_goldsa //
	19869	sp_goldsb //
	19870	sp_goldsc //
	19871	sp_goldsd //
	19872	sp_goldse //
	19873	sp_goldsf //
	19874	sp_goldsg //
	19875	sp_goldsh //
19874	19876	sp_goldt // Golden Touch (Golden Streak) (Ace)
19875	19877	sp_here // Here We Go (Ace)
19876	19878	sp_herea //
r15704	r15705
19969	19971	sp_poundbwbf //
19970	19972	sp_road // Road To Hell (Ace)
19971	19973	sp_skylm // Sky's The Limit Club, The (Ace)
19972		sp_skylma //
	19974	sp_skylma //
19973	19975	sp_tkpik // Take Your Pick (Ace)
19974	19976	sp_tkpika //
19975	19977	sp_tkpikb //
r15704	r15705
19982	19984	sp_front // Final Frontier (Bwb)
19983	19985	sp_atw // Around the World (Crystal)
19984	19986	sp_five // Fiver Fever (Crystal)
19985		sp_fivea //
	19987	sp_fivea //
19986	19988	sp_crun // Cash Run (Crystal)
19987	19989	sp_cruna //
19988	19990	sp_crunb //

src/mame/machine/bfm_bd1.h
r15704	r15705
34	34	protected:
35	35	static const UINT8 AT_NORMAL = 0x00;
36	36	static const UINT8 AT_FLASH = 0x01;
37		static const UINT8 AT_BLANK = 0x02;
	37	static const UINT8 AT_BLANK = 0x02;
38	38	static const UINT8 AT_FLASHED = 0x80; // set when character should be blinked off
39	39
40	40	int m_cursor_pos;

src/mame/machine/bfm_bda.c
r15704	r15705
302	302	break;
303	303
304	304	case 0xB0: // 0xB0 - 0xBF Clear display area
305
	305
306	306	switch ( data & 0x03 )
307	307	{
308	308	case 0x00: // clr nothing

src/mame/machine/bfm_bda.h
r15704	r15705
34	34	protected:
35	35	static const UINT8 AT_NORMAL = 0x00;
36	36	static const UINT8 AT_FLASH = 0x01;
37		static const UINT8 AT_BLANK = 0x02;
	37	static const UINT8 AT_BLANK = 0x02;
38	38	static const UINT8 AT_FLASHED = 0x80; // set when character should be blinked off
39	39
40	40	int m_cursor_pos;

src/mame/machine/bfm_bd1.c
r15704	r15705
293	293	break;
294	294
295	295	case 0xB0: // 0xB0 - 0xBF Clear display area
296
	296
297	297	switch ( data & 0x03 )
298	298	{
299	299	case 0x00: // clr nothing

src/mame/includes/esd16.h
r15704	r15705
19	19	m_head_layersize(*this, "head_layersize"),
20	20	m_headpanic_platform_x(*this, "platform_x"),
21	21	m_headpanic_platform_y(*this, "platform_y")
22		{
	22	{
23	23	m_tilemap0_color = 0;
24	24	m_tilemap1_color = 0;
25	25	}
r15704	r15705
55	55	DECLARE_WRITE16_MEMBER(esd16_vram_0_w);
56	56	DECLARE_WRITE16_MEMBER(esd16_vram_1_w);
57	57	DECLARE_WRITE16_MEMBER(esd16_tilemap0_color_w);
58		DECLARE_WRITE16_MEMBER(esd16_tilemap0_color_jumppop_w);
	58	DECLARE_WRITE16_MEMBER(esd16_tilemap0_color_jumppop_w);
59	59	};
60	60
61	61

src/mame/mame.mak
r15704	r15705
1879	1879	$(DRIVERS)/umipoker.o \
1880	1880	$(DRIVERS)/unkfr.o \
1881	1881	$(DRIVERS)/unkhorse.o \
1882		$(DRIVERS)/usgames.o $(VIDEO)/usgames.o \
	1882	$(DRIVERS)/usgames.o $(VIDEO)/usgames.o \
1883	1883	$(DRIVERS)/vamphalf.o \
1884	1884	$(DRIVERS)/vcombat.o \
1885	1885	$(DRIVERS)/vectrex.o $(VIDEO)/vectrex.o $(MACHINE)/vectrex.o \

src/mame/video/taitojc.c
r15704	r15705
488	488
489	489	void taitojc_renderer::render_polygons(running_machine &machine, UINT16 *polygon_fifo, int length)
490	490	{
491		// taitojc_state *state = machine.driver_data<taitojc_state>();
	491	// taitojc_state *state = machine.driver_data<taitojc_state>();
492	492	const rectangle visarea = machine.primary_screen->visible_area();
493	493	vertex_t vert[4];
494	494	int i;

src/mame/drivers/bfm_sc1.c
r15704	r15705
1785	1785	ROM_REGION( 0x10000, "maincpu", 0 )
1786	1786	ROM_LOAD( "cop56cp2", 0x0000, 0x008000, CRC(c862ee34) SHA1(e807d1072953e67581ce0181bfd82a7efcee7bf0) )
1787	1787	ROM_LOAD( "cop56cp1", 0x8000, 0x008000, CRC(214edd7d) SHA1(007c17cc522c8f0d30bc1fd08bb18850344f62ad) )
1788
	1788
1789	1789	ROM_REGION( 0x80000, "upd", 0 )
1790	1790	ROM_LOAD( "copssnd.bin", 0x0000, 0x040000, CRC(4bebbc37) SHA1(10eb8542a9de35efc0f75b532c94e1b3e0d21e47) )
1791	1791
r15704	r15705
1795	1795	ROM_REGION( 0x10000, "maincpu", 0 )
1796	1796	ROM_LOAD( "cops & robbers 5p v1-3 b (27256)", 0x0000, 0x008000, CRC(6f5425d6) SHA1(7673841ccfe16eaa0a5cfca1596383f7711f2dbe) )
1797	1797	ROM_LOAD( "cops & robbers 5p v1-3 a (27256)", 0x8000, 0x008000, CRC(29513083) SHA1(f2ce0b573d6756e7d835488b8d8eed3266787255) )
1798
	1798
1799	1799	ROM_REGION( 0x80000, "upd", 0 )
1800	1800	ROM_LOAD( "copssnd.bin", 0x0000, 0x040000, CRC(4bebbc37) SHA1(10eb8542a9de35efc0f75b532c94e1b3e0d21e47) )
1801	1801

src/mame/drivers/segaxbd.c
r15704	r15705
546	546	*/
547	547	space->machine().sound().system_enable(data & 0x80);
548	548	break;
549
	549
550	550	default: break;
551	551	}
552	552
r15704	r15705
635	635	coin_counter_w(machine, 0, (data >> 4) & 0x01);
636	636
637	637	/*
638		aburner2:
639		d1: altitude warning lamp
640		d2: start lamp
641		d5: lock on lamp
642		d6: danger lamp
643		in clone aburner, lamps work only in testmode?
644
645		*/
	638	aburner2:
	639	d1: altitude warning lamp
	640	d2: start lamp
	641	d5: lock on lamp
	642	d6: danger lamp
	643	in clone aburner, lamps work only in testmode?
	644
	645	*/
646	646	output_set_lamp_value(0, (data >> 5) & 0x01);
647	647	output_set_lamp_value(1, (data >> 6) & 0x01);
648	648	output_set_lamp_value(2, (data >> 1) & 0x01);

src/mame/drivers/acesp.c
r15704	r15705
56	56	/* 0x3f */
57	57	//----- 0x0040 - 0x013f is internal RAM (256 bytes) -----
58	58	AM_RANGE(0x0040, 0x013f) AM_RAM
59
60	59
	60
61	61	/** regular map **/
62	62	AM_RANGE(0x0140, 0x1fff) AM_RAM
63	63	AM_RANGE(0x2000, 0xffff) AM_ROM
r15704	r15705
2310	2310	SP_CODER_SOUND
2311	2311	ROM_END
2312	2312
2313
	2313
2314	2314	ROM_START( sp_coderb )
2315	2315	ROM_REGION( 0x80000, "maincpu", 0 )
2316	2316	ROM_LOAD( "cr655d3d", 0x0000, 0x8000, CRC(a20fc66b) SHA1(df67d0fe655e218afc92342609411e76be4dd47b) )
r15704	r15705
3342	3342	ROM_LOAD( "0016rp40.bin", 0x0000, 0x010000, CRC(591e3e24) SHA1(b147bfc19aa46eb3237b270d771031caaf978850) ) // merged rom
3343	3343	SP_ONBOX_SOUND
3344	3344	ROM_END
3345
	3345
3346	3346	ROM_START( sp_onboxn )
3347	3347	ROM_REGION( 0x80000, "maincpu", 0 )
3348	3348	ROM_LOAD( "0016rp50.bin", 0x0000, 0x010000, CRC(73c5c449) SHA1(453969ec5c4fe1ce8f118110106e31126a358cda) ) // merged rom
3349	3349	SP_ONBOX_SOUND
3350	3350	ROM_END
3351
3352	3351
3353	3352
	3353
3354	3354	#define SP_PISTE_SOUND \
3355	3355	ROM_REGION( 0x100000, "oki", ROMREGION_ERASE00 ) \
3356	3356	/* not used, or missing? */ \

src/mame/drivers/cybertnk.c
r15704	r15705
11	11	How are unused sprites marked? None of the bits alone seem to be used for this purpose
12	12	and while in many cases the first value gets cleared to 0x0000 (palette 0, upper tile offset 0)
13	13	that doesn't really seem like a valid marker, and leaves us with some lingering sprites anyway.
14
	14
15	15	Attempting to clear the spriteram every frame doesn't help either, the list is copied, complete
16	16	with 'unwanted' sprites every frame, ruling out some kind of auto clear after drawing operation.
17	17
r15704	r15705
307	307	UINT16 param1 = state->m_roadram[i+2];
308	308	UINT16 param2 = state->m_roadram[i+1];
309	309	UINT16 param3 = state->m_roadram[i+0];
310
	310
311	311	int col = (param2 & 0x3f);
312	312
313	313	// seems to be priority related, cases seen are 0xc0 and 0x00 (once the palette bits are masked out)
r15704	r15705
335	335
336	336	/*
337	337
338		o = offset
339		y = ypos Y = ysize ^ = always 0xF? ? = set for no obvious reason..
340		x = xpos X = xsize f = flipx
	338	o = offset
	339	y = ypos Y = ysize ^ = always 0xF? ? = set for no obvious reason..
	340	x = xpos X = xsize f = flipx
341	341
342		Z = zoom * = alt zoom? (ok for roadside, but 00 for player tank etc?)
343		C = colour
	342	Z = zoom * = alt zoom? (ok for roadside, but 00 for player tank etc?)
	343	C = colour
344	344	+word offset
345		CCCC CCCC #### @ooo 0x0 # bits are often set too? @ is set at the very end of spriteram
346		oooo oooo oooo oooo 0x1
347		---- ---- ---y yyyy 0x2
348		---- ---- ---- ---- 0x3 (always has a value here, gets set to FFFF on some cleared sprites?)
349		???? ^^^^ YYYY YYYY 0x4
350		f--- --xx xxxx xxxx 0x5
351		ZZZZ ZZZZ ---- XXXX 0x6
352		---- ---- ** ** 0x7
	345	CCCC CCCC #### @ooo 0x0 # bits are often set too? @ is set at the very end of spriteram
	346	oooo oooo oooo oooo 0x1
	347	---- ---- ---y yyyy 0x2
	348	---- ---- ---- ---- 0x3 (always has a value here, gets set to FFFF on some cleared sprites?)
	349	???? ^^^^ YYYY YYYY 0x4
	350	f--- --xx xxxx xxxx 0x5
	351	ZZZZ ZZZZ ---- XXXX 0x6
	352	---- ---- ** ** 0x7
353	353
354		*/
	354	*/
355	355
356	356
357	357	for(int offs=0;offs<0x1000/2;offs+=8)
r15704	r15705
386	386	for(int yi = 0;yi < ysize;yi++)
387	387	{
388	388	xf = xz = 0;
389
390	389
	390
391	391	int yy = y+yz;
392	392
393	393	if ((yy>=miny) && (yy<=maxy))
394	394	{
395		dest = &bitmap.pix16(yy, 0);
	395	dest = &bitmap.pix16(yy, 0);
396	396
397	397	int start,end,inc;
398	398
r15704	r15705
412	412	for(int xi=start;xi != end;xi+=inc)
413	413	{ // start x loop
414	414	UINT32 color;
415
	415
416	416	color = sprrom[spr_offs+xi/8];
417
	417
418	418	UINT16 dot;
419	419	int x_dec; //helpers
420	420
r15704	r15705
471	471	if(yf >= 0x80) { yz++; yf-=0x80; }
472	472	}
473	473	}
474		}
	474	}
475	475
476		// if (state->m_spr_ram[0xff0/2] == 0x0008)
477		// memset(state->m_spr_ram, 0x00, 0xff0);
	476	// if (state->m_spr_ram[0xff0/2] == 0x0008)
	477	// memset(state->m_spr_ram, 0x00, 0xff0);
478	478
479	479	}
480	480
r15704	r15705
493	493	state->m_tilemap1_tilemap->set_scrollx(state->m_tilemap1scroll[0]);
494	494	state->m_tilemap2_tilemap->set_scrollx(state->m_tilemap2scroll[0]);
495	495
496
497	496
	497
498	498	bitmap.fill(get_black_pen(screen.machine()), cliprect);
499	499
500	500
r15704	r15705
541	541	{
542	542	if (offset == 0)
543	543	{
544		printf("cybertnk_sound_cmd_w offset 0 %02x\n", data);
	544	printf("cybertnk_sound_cmd_w offset 0 %02x\n", data);
545	545	}
546	546	else if (offset == 1)
547	547	{
r15704	r15705
555	555	{
556	556	if (offset == 0)
557	557	{
558		// printf("cybertnk_mux_w offset 0 %02x\n", data);
	558	// printf("cybertnk_mux_w offset 0 %02x\n", data);
559	559	}
560	560	else if (offset == 1)
561	561	{
562		// printf("cybertnk_mux_w offset 1 %02x\n", data);
	562	// printf("cybertnk_mux_w offset 1 %02x\n", data);
563	563	m_mux_data = data & 0x60;
564	564	/* Other bits are unknown */
565	565	}
r15704	r15705
583	583	if (offset == 0)
584	584	{
585	585	// unused?
586		logerror("cybertnk_irq_ack_w offset 0 %02x\n", data);
	586	logerror("cybertnk_irq_ack_w offset 0 %02x\n", data);
587	587	}
588	588	else if (offset == 1)
589	589	{
r15704	r15705
602	602	else if (offset == 1)
603	603	{
604	604	// unused?
605		logerror("cybertnk_cnt_w offset 1 %02x\n", data);
	605	logerror("cybertnk_cnt_w offset 1 %02x\n", data);
606	606	}
607	607	}
608	608

src/mame/drivers/mpu4.c
r15704	r15705
13740	13740	ROM_LOAD( "fds103p.bin", 0x0000, 0x010000, CRC(764bd0a8) SHA1(cea826c94ce28ab3e47071846756a7e1effa5d1b) )
13741	13741	ROM_LOAD( "twisterprog.bin", 0x0000, 0x010000, CRC(96209a3e) SHA1(434aa824a517929d9ace959b06f2d38464a54541) )
13742	13742
13743
	13743
13744	13744	ROM_REGION( 0x100000, "msm6376", ROMREGION_ERASE00 )
13745	13745	ROM_LOAD( "twistersound.bin", 0x000000, 0x100000, CRC(5aa2729b) SHA1(cf490ec6c75c038addcff24655cd6e498cad60c1) )
13746
	13746
13747	13747	ROM_END
13748	13748
13749	13749

src/mame/drivers/namcos21.c
r15704	r15705
1533	1533	MCFG_PALETTE_LENGTH(NAMCOS21_NUM_COLORS)
1534	1534
1535	1535	MCFG_VIDEO_START(namcos21)
1536
	1536
1537	1537	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1538	1538
1539	1539	MCFG_SOUND_ADD("c140", C140, 8000000/374)
r15704	r15705
2410	2410
2411	2411	static INPUT_PORTS_START( winrungp )
2412	2412	PORT_INCLUDE(winrun)
2413
	2413
2414	2414	PORT_MODIFY("DSW")
2415	2415	PORT_DIPNAME( 0x20, 0x00, "PCM ROM")
2416	2416	PORT_DIPSETTING( 0x20, "2M" )

src/mame/drivers/lastbank.c
r15704	r15705
2	2
3	3	Last Bank (c) 1994 Excellent Systems
4	4
5		driver by Angelo Salese
	5	driver by Angelo Salese
6	6
7	7	Uses a TC0091LVC, a variant of the one used on Taito L HW
8	8
r15704	r15705
429	429
430	430
431	431	static GFXDECODE_START( lastbank )
432		GFXDECODE_ENTRY( "gfx1", 0, bg2_layout, 0, 16 )
433		GFXDECODE_ENTRY( "gfx1", 0, sp2_layout, 0, 16 )
	432	GFXDECODE_ENTRY( "gfx1", 0, bg2_layout, 0, 16 )
	433	GFXDECODE_ENTRY( "gfx1", 0, sp2_layout, 0, 16 )
434	434	GFXDECODE_END
435	435
436	436	static TIMER_DEVICE_CALLBACK( lastbank_irq_scanline )
r15704	r15705
459	459	MCFG_CPU_ADD("audiocpu",Z80,MASTER_CLOCK/4)
460	460	MCFG_CPU_PROGRAM_MAP(lastbank_audio_map)
461	461	MCFG_CPU_IO_MAP(lastbank_audio_io)
462		// MCFG_CPU_PERIODIC_INT(nmi_line_pulse,60)
	462	// MCFG_CPU_PERIODIC_INT(nmi_line_pulse,60)
463	463
464	464	MCFG_QUANTUM_PERFECT_CPU("maincpu")
465	465
r15704	r15705
480	480	MCFG_GFXDECODE( lastbank )
481	481	MCFG_PALETTE_LENGTH(0x100)
482	482
483		// MCFG_VIDEO_START(lastbank)
	483	// MCFG_VIDEO_START(lastbank)
484	484
485	485	/* sound hardware */
486	486	MCFG_SPEAKER_STANDARD_MONO("mono")

src/mame/drivers/wardner.c
r15704	r15705
138	138	wardner_state(const machine_config &mconfig, device_type type, const char *tag)
139	139	: twincobr_state(mconfig, type,tag),
140	140	m_rambase_c000(*this, "rambase_c000")
141		{
	141	{
142	142	}
143	143
144	144	required_shared_ptr<UINT8> m_rambase_c000;
r15704	r15705
168	168	else if ((addr >= 0xc000) && (addr < 0xc800))
169	169	return m_rambase_c000[addr - 0xc000];
170	170	}
171
	171
172	172	// ROM bank mapped
173	173	return m_ROM[m_wardner_membank * 0x8000 + offset];
174	174	}

src/mame/drivers/pokechmp.c
r15704	r15705
11	11
12	12	Todo:
13	13
14		Verify frequencies etc.
	14	Verify frequencies etc.
15	15
16	16	*/
17	17
r15704	r15705
54	54	UINT8 *ROM = memregion("maincpu")->base();
55	55
56	56	int bank;
57
	57
58	58	bank = (data & 0x1) ? 0x04000 : 0x00000;
59	59	bank \|= (data & 0x2) ? 0x10000 : 0x00000;
60	60
r15704	r15705
175	175	RGN_FRAC(1,8),
176	176	8,
177	177	/* bizzare order, but it seems to be correct? */
178		{ RGN_FRAC(1,8), RGN_FRAC(3,8),RGN_FRAC(0,8),RGN_FRAC(5,8),RGN_FRAC(2,8),RGN_FRAC(7,8),RGN_FRAC(4,8),RGN_FRAC(6,8) },
	178	{ RGN_FRAC(1,8), RGN_FRAC(3,8),RGN_FRAC(0,8),RGN_FRAC(5,8),RGN_FRAC(2,8),RGN_FRAC(7,8),RGN_FRAC(4,8),RGN_FRAC(6,8) },
179	179	{ 0, 1, 2, 3, 4, 5, 6, 7 },
180	180	{ 08, 18, 28, 38, 48, 58, 68, 78 },
181	181	88 / every char takes 8 consecutive bytes */
r15704	r15705
244	244	{
245	245	// default sound rom bank
246	246	machine.root_device().membank("bank3")->configure_entries(0, 2, machine.root_device().memregion("audiocpu")->base() + 0x10000, 0x4000);
247
	247
248	248	// default fixed area for main CPU
249	249	machine.root_device().membank("fixed")->set_base( machine.root_device().memregion("maincpu")->base() + 0x18000 );
250
	250
251	251	// default OKI sample bank
252	252	machine.root_device().membank("okibank")->set_base( machine.root_device().memregion("oki")->base() + 0x40000 );
253	253	}

src/mame/drivers/taitotz.c
r15704	r15705
79	79	#include "video/polynew.h"
80	80
81	81	/*
82		Interesting mem areas
	82	Interesting mem areas
83	83
84		0x40080400...0x400807fc: PPC Interrupt handler table for TLCS900 interrupts (called from 0x4002ea80)
	84	0x40080400...0x400807fc: PPC Interrupt handler table for TLCS900 interrupts (called from 0x4002ea80)
85	85	0x40080440 (0x10): 0x4003b274 (0xfc06f7 on TLCS sets 0x1000)
86	86	0x400804c0 (0x30): 0x4003f1e4 (INT1 handler on TLCS sets 0x3010) (comms, could be IEEE1394)
87	87	0x40080500 (0x40): 0x4002ed94 (debug/trace)
88	88	0x40080504 (0x41): 0x4002ede4 (debug/break)
89		0x40080540 (0x50): 0x4003c21c 0x5001: sets 0x00000001 in 0x40049c58
90		0x40080740 (0xd0): 0x4002ecc0 (INT3 handler on TLCS sets 0xd000) (VBlank?)
	89	0x40080540 (0x50): 0x4003c21c 0x5001: sets 0x00000001 in 0x40049c58
	90	0x40080740 (0xd0): 0x4002ecc0 (INT3 handler on TLCS sets 0xd000) (VBlank?)
91	91	0x400807c0 (0xf0): 0x4002eae4 (0xfc0a44 on TLCS sets 0xf001)
92
	92
93	93	PPC -> TLCS Commands:
94		0x1000: 0x4003a9e0() HDD Reset
95		0x1001: 0x4003aa14() HDD Init. Writes HDD status and error to io_shared[0x1a00].
96		0x1010: 0x4003aaf4(), 0x4003ab8c() HDD Read Sector
97		0x1020: 0x4003ac1c() HDD Write Sector
98		0x4000: ? Related to sound loading?
99		0x4001: 0x400429b0() MBox related
100		0x4002: ? Loads a byte from MBox ram. Address in io_shared[0x1c04]
101		0x4003: ? Writes a byte into MBox ram. Address in io_shared[0x1c04], data in io_shared[0x1c06].
102		0x4004: 0x40042bc4(), 0x40042c50() Play music/sound? Params in io_shared[0x1c08...0x1c12]
103		0x5000: 0x4003bc68() Reset RTC?
104		0x5010: 0x4003bb68() Read RTC
105		0x5020: 0x4003bbec() Write RTC
106		0x6000: ? Backup RAM Read. Address in io_shared[0x1d00].
107		0x6010: ? Backup RAM Write. Address in io_shared[0x1d00].
108		0x7000: 0x4003d1c4()
109		0x7001: 0x4003d28c()
110		0x7002: 0x4003d4ac()
111		0x7003: 0x4003d508()
112		0x7004: 0x4003d554()
113		0x7005: 0x4003d168()
114		0x8000: ? Used by vibration (force feedback?) on pwrshovl
115		0xa000: ? Used by vibration (force feedback?) on pwrshovl
116		0xf000: 0x4002f328() TLCS_Init
117		0xf010: 0x4002f074() Enables TLCS watchdog timer
118		0xf011: 0x4002f0a8() Disables TLCS watchdog
119		0xf020: ?
120		0xf055: 0x4002f0dc() Enables TLCS watchdog and infloops the TLCS
121		0xf0ff: ? TLCS soft reset?
	94	0x1000: 0x4003a9e0() HDD Reset
	95	0x1001: 0x4003aa14() HDD Init. Writes HDD status and error to io_shared[0x1a00].
	96	0x1010: 0x4003aaf4(), 0x4003ab8c() HDD Read Sector
	97	0x1020: 0x4003ac1c() HDD Write Sector
	98	0x4000: ? Related to sound loading?
	99	0x4001: 0x400429b0() MBox related
	100	0x4002: ? Loads a byte from MBox ram. Address in io_shared[0x1c04]
	101	0x4003: ? Writes a byte into MBox ram. Address in io_shared[0x1c04], data in io_shared[0x1c06].
	102	0x4004: 0x40042bc4(), 0x40042c50() Play music/sound? Params in io_shared[0x1c08...0x1c12]
	103	0x5000: 0x4003bc68() Reset RTC?
	104	0x5010: 0x4003bb68() Read RTC
	105	0x5020: 0x4003bbec() Write RTC
	106	0x6000: ? Backup RAM Read. Address in io_shared[0x1d00].
	107	0x6010: ? Backup RAM Write. Address in io_shared[0x1d00].
	108	0x7000: 0x4003d1c4()
	109	0x7001: 0x4003d28c()
	110	0x7002: 0x4003d4ac()
	111	0x7003: 0x4003d508()
	112	0x7004: 0x4003d554()
	113	0x7005: 0x4003d168()
	114	0x8000: ? Used by vibration (force feedback?) on pwrshovl
	115	0xa000: ? Used by vibration (force feedback?) on pwrshovl
	116	0xf000: 0x4002f328() TLCS_Init
	117	0xf010: 0x4002f074() Enables TLCS watchdog timer
	118	0xf011: 0x4002f0a8() Disables TLCS watchdog
	119	0xf020: ?
	120	0xf055: 0x4002f0dc() Enables TLCS watchdog and infloops the TLCS
	121	0xf0ff: ? TLCS soft reset?
122	122
123		TLCS -> PPC Commands:
124		0x10xx: 0xfc06f7() HDD Command ack?
125		0x40094ec8:
126		0x00: IDLE
127		0x10: READ
128		0x11: READ SECTOR
129		0x12: READ ALL
130		0x20: WRITE
131		0x21: WRITE SECTOR
132		0x22: WRITE ALL
133		0x30: VENDER
134		0xff: ERROR
135		0x??: UNKNOWN
136		0x3010: 0xfc071c() int1 handler Comm IRQ, IEEE1394
137		0x40xx: ? Debug
138		0x41xx: ? Debug
139		0x5001: ? RTC?
140		0xd000: 0xfc06b4() int3 handler VBlank? Runs a counter on the PPC side
141		0xf001: 0xfc0a44() PPC sync?
	123	TLCS -> PPC Commands:
	124	0x10xx: 0xfc06f7() HDD Command ack?
	125	0x40094ec8:
	126	0x00: IDLE
	127	0x10: READ
	128	0x11: READ SECTOR
	129	0x12: READ ALL
	130	0x20: WRITE
	131	0x21: WRITE SECTOR
	132	0x22: WRITE ALL
	133	0x30: VENDER
	134	0xff: ERROR
	135	0x??: UNKNOWN
	136	0x3010: 0xfc071c() int1 handler Comm IRQ, IEEE1394
	137	0x40xx: ? Debug
	138	0x41xx: ? Debug
	139	0x5001: ? RTC?
	140	0xd000: 0xfc06b4() int3 handler VBlank? Runs a counter on the PPC side
	141	0xf001: 0xfc0a44() PPC sync?
142	142
143	143
144		BG2 intro packet writes:
	144	BG2 intro packet writes:
145	145
146		construction?
147		0x4012f390()
148		-> 0x401304f0() scene graph parser?
149		-> 0x40130d60()
150		-> 0x401aff48() R3 = dest, R4 = source, R5 = length
	146	construction?
	147	0x4012f390()
	148	-> 0x401304f0() scene graph parser?
	149	-> 0x40130d60()
	150	-> 0x401aff48() R3 = dest, R4 = source, R5 = length
151	151
152		0x40174674()
153		0x401ba294()
154		R3 = 0x000007d0, R4 = 0x40707bac, R5 = 0x00000398
	152	0x40174674()
	153	0x401ba294()
	154	R3 = 0x000007d0, R4 = 0x40707bac, R5 = 0x00000398
155	155
156		f1 00 00 63 0c 00 00 7f 0c 00 00 00 08 00 00 00
157		00 40 01 3e 00 00 81 00 00 00 7f 00 00 7f 00 00
158		00 40 3e 3e 00 00 7f 00 00 00 7f 00 00 7f 00 00
159		00 40 3e 00 00 00 7f 00 00 00 81 00 00 7f 00 00
160		00 40 01 00 00 00 81 00 00 00 81 00 00 7f 00 00
161		f1 00 00 69 00 00 7f 00 0c 7f 00 00 0d 00 00 7f
162		00 40 00 3f 00 00 e0 40 00 00 00 00 00 7f 7f 00
163		00 40 00 00 00 00 e0 40 00 00 00 00 00 7f 81 00
164		00 40 1f 00 00 00 1f c0 00 00 00 00 00 7f 81 00
165		00 40 1f 3f 00 00 1f c0 00 00 00 00 00 7f 7f 00
166		...
	156	f1 00 00 63 0c 00 00 7f 0c 00 00 00 08 00 00 00
	157	00 40 01 3e 00 00 81 00 00 00 7f 00 00 7f 00 00
	158	00 40 3e 3e 00 00 7f 00 00 00 7f 00 00 7f 00 00
	159	00 40 3e 00 00 00 7f 00 00 00 81 00 00 7f 00 00
	160	00 40 01 00 00 00 81 00 00 00 81 00 00 7f 00 00
	161	f1 00 00 69 00 00 7f 00 0c 7f 00 00 0d 00 00 7f
	162	00 40 00 3f 00 00 e0 40 00 00 00 00 00 7f 7f 00
	163	00 40 00 00 00 00 e0 40 00 00 00 00 00 7f 81 00
	164	00 40 1f 00 00 00 1f c0 00 00 00 00 00 7f 81 00
	165	00 40 1f 3f 00 00 1f c0 00 00 00 00 00 7f 7f 00
	166	...
167	167
168		R3 = 0x00000b68, R4 = 0x40707e58, R5 = 0x00001000
	168	R3 = 0x00000b68, R4 = 0x40707e58, R5 = 0x00001000
169	169
170		e1 00 00 73 00 81 00 00 04 00 00 00 0c 00 00 00
171		00 40 06 00 00 94 fd d1 00 d2 82 ce 00 2e 03 ef
172		00 40 06 00 00 99 fd d1 00 c0 82 ce 00 df 00 40
173		00 40 06 02 00 91 fd d1 00 ef 88 9e 00 c7 fc 40
174		00 40 06 1f 00 88 fd d1 00 00 b8 60 00 26 03 ef
175		e0 00 00 73 00 81 00 00 04 00 00 00 0c 00 00 00
176		00 40 06 1f 00 8b fd d1 00 00 b8 60 00 d0 fc 40
177		00 40 06 1f 00 88 fd d1 00 00 b8 60 00 26 03 ef
178		00 40 06 02 00 91 fd d1 00 ef 88 9e 00 c7 fc 40
179		...
	170	e1 00 00 73 00 81 00 00 04 00 00 00 0c 00 00 00
	171	00 40 06 00 00 94 fd d1 00 d2 82 ce 00 2e 03 ef
	172	00 40 06 00 00 99 fd d1 00 c0 82 ce 00 df 00 40
	173	00 40 06 02 00 91 fd d1 00 ef 88 9e 00 c7 fc 40
	174	00 40 06 1f 00 88 fd d1 00 00 b8 60 00 26 03 ef
	175	e0 00 00 73 00 81 00 00 04 00 00 00 0c 00 00 00
	176	00 40 06 1f 00 8b fd d1 00 00 b8 60 00 d0 fc 40
	177	00 40 06 1f 00 88 fd d1 00 00 b8 60 00 26 03 ef
	178	00 40 06 02 00 91 fd d1 00 ef 88 9e 00 c7 fc 40
	179	...
180	180
181		R3 = 0x00001b68, R4 = 0x40707e58, R5 = 0x00000d19
182		R3 = 0x00075770, R4 = 0x40443e2c, R5 = 0x00000014
183		R3 = 0x00075784, R4 = 0x40443e7c, R5 = 0x00000014
184		R3 = 0x00075798, R4 = 0x40443ecc, R5 = 0x00000014
185		R3 = 0x000757ac, R4 = 0x40443f1c, R5 = 0x00000014
186		R3 = 0x000757c0, R4 = 0x40443e6c, R5 = 0x00000014
	181	R3 = 0x00001b68, R4 = 0x40707e58, R5 = 0x00000d19
	182	R3 = 0x00075770, R4 = 0x40443e2c, R5 = 0x00000014
	183	R3 = 0x00075784, R4 = 0x40443e7c, R5 = 0x00000014
	184	R3 = 0x00075798, R4 = 0x40443ecc, R5 = 0x00000014
	185	R3 = 0x000757ac, R4 = 0x40443f1c, R5 = 0x00000014
	186	R3 = 0x000757c0, R4 = 0x40443e6c, R5 = 0x00000014
187	187
188		R3 = 0x00062ca0, R4 = 0x409cfa70, R5 = 0x000001e0
189		R3 = 0x00008ca0, R4 = 0x409f8f70, R5 = 0x000002c5
190		R3 = 0x00002ba4, R4 = 0x40fffaf0, R5 = 0x00000028
191		R3 = 0x0001f4a0, R4 = 0x40a06350, R5 = 0x00000340
192		R3 = 0x00002bcc, R4 = 0x40fffaf0, R5 = 0x00000028
	188	R3 = 0x00062ca0, R4 = 0x409cfa70, R5 = 0x000001e0
	189	R3 = 0x00008ca0, R4 = 0x409f8f70, R5 = 0x000002c5
	190	R3 = 0x00002ba4, R4 = 0x40fffaf0, R5 = 0x00000028
	191	R3 = 0x0001f4a0, R4 = 0x40a06350, R5 = 0x00000340
	192	R3 = 0x00002bcc, R4 = 0x40fffaf0, R5 = 0x00000028
193	193
194		R3 = 0x00000190, R4 = 0x40fff8f8, R5 = 0x00000014
	194	R3 = 0x00000190, R4 = 0x40fff8f8, R5 = 0x00000014
195	195
196		0x40188514()
197		R3 = 0x0000d818, R4 = 0x40ffcce0, R5 = 0x00000bc0
	196	0x40188514()
	197	R3 = 0x0000d818, R4 = 0x40ffcce0, R5 = 0x00000bc0
198	198
199		00 00 00 dd 00 00 00 00 00 00 00 00 00 00 00 00
200		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
201		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
202		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
203		...
	199	00 00 00 dd 00 00 00 00 00 00 00 00 00 00 00 00
	200	00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
	201	00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
	202	00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
	203	...
204	204
205		R3 = 0x0001494c, R4 = 0x40ffcce0, R5 = 0x00000bc0
	205	R3 = 0x0001494c, R4 = 0x40ffcce0, R5 = 0x00000bc0
206	206
207		0x40116c28(): Draws 2D images
208		R3 = 0x009e0c7a, R4 = 0x40a7c3bc, R5 = 0x0000007c
	207	0x40116c28(): Draws 2D images
	208	R3 = 0x009e0c7a, R4 = 0x40a7c3bc, R5 = 0x0000007c
209	209
210		0x40116a80(): Clears 2D images?
211		R3 = 0x009f6308, R4 = 0x40a9a784, R5 = 0x000000f0
	210	0x40116a80(): Clears 2D images?
	211	R3 = 0x009f6308, R4 = 0x40a9a784, R5 = 0x000000f0
212	212
213	213
214	214
215		-> 0x40116430(): R3 = dest (\|= 0x30800000), R4 = source, R5 = num words
216		-> 0x401162ac() WriteVideoMem: R3 = source, R4 = dest, R5 = num words
217		-> 0x401064b0() Write video data using FIFO: R3 = source, R4 = dest, R5 = num words (must be divisible by 8)
218		-> 0x40106668() Write video data using write port: R3 = source, R4 = dest, R5 = num words
	215	-> 0x40116430(): R3 = dest (\|= 0x30800000), R4 = source, R5 = num words
	216	-> 0x401162ac() WriteVideoMem: R3 = source, R4 = dest, R5 = num words
	217	-> 0x401064b0() Write video data using FIFO: R3 = source, R4 = dest, R5 = num words (must be divisible by 8)
	218	-> 0x40106668() Write video data using write port: R3 = source, R4 = dest, R5 = num words
219	219
220	220
221	221
222		0x40106788(): FIFO Packet write: R3 = source, R4 = select between cmd 0 and 1, R5 = num words (must be divisible by 8)
	222	0x40106788(): FIFO Packet write: R3 = source, R4 = select between cmd 0 and 1, R5 = num words (must be divisible by 8)
223	223
224	224
225	225
226		BG2: 4x4 Matrices at 0x40223218
227		word 0: ?? (0x62e6c, 0xf20a0, ...) anded by 0x1fffff on read, or'd by 0xff800000, or'd by 0x400000 if no matrix, store -> [0x00]
228		word 1: ?? (usually zero)
229		word 2: float (often 1.0) multiplied by 31.0f, converted to (int), anded by 0x1f, or by 0x80 if word 1 == 1, store -> [0x08]
230		word 3: float if (exponent < 1, mult by 0.5), store -> [0x04]
231		word 4: usually 0x00000001 if 0, matrix not stored
232		16x float: 4x4 matrix
233		matrix[0][0] -> store [0x10]
234		matrix[1][0] -> store [0x14]
235		matrix[2][0] -> store [0x18]
236		matrix[3][0] -> store [0x1c]
237		...
238		word 0: Pointer to another matrix
239		word 1: Pointer to another matrix
	226	BG2: 4x4 Matrices at 0x40223218
	227	word 0: ?? (0x62e6c, 0xf20a0, ...) anded by 0x1fffff on read, or'd by 0xff800000, or'd by 0x400000 if no matrix, store -> [0x00]
	228	word 1: ?? (usually zero)
	229	word 2: float (often 1.0) multiplied by 31.0f, converted to (int), anded by 0x1f, or by 0x80 if word 1 == 1, store -> [0x08]
	230	word 3: float if (exponent < 1, mult by 0.5), store -> [0x04]
	231	word 4: usually 0x00000001 if 0, matrix not stored
	232	16x float: 4x4 matrix
	233	matrix[0][0] -> store [0x10]
	234	matrix[1][0] -> store [0x14]
	235	matrix[2][0] -> store [0x18]
	236	matrix[3][0] -> store [0x1c]
	237	...
	238	word 0: Pointer to another matrix
	239	word 1: Pointer to another matrix
240	240
241		0x401afffc(): Write
	241	0x401afffc(): Write
242	242
243		0x40118af0():
244		-> 0x401195e0(): Read (Transposes matrix, only columns 0-2 stored + 4 extra command words)
	243	0x40118af0():
	244	-> 0x401195e0(): Read (Transposes matrix, only columns 0-2 stored + 4 extra command words)
245	245
246		-> 0x40118080: Read, store to [0x40362314+], never read
	246	-> 0x40118080: Read, store to [0x40362314+], never read
247	247
248	248
249		Display list top?: 0x403408c0 (pointer to at 0x4020b80c)
250		bottom?: 0x403608e4 (pointer to at 0x4020b81c)
	249	Display list top?: 0x403408c0 (pointer to at 0x4020b80c)
	250	bottom?: 0x403608e4 (pointer to at 0x4020b81c)
251	251
252		0x40123fcc():
253		-> 0x401186c8(): Display list parser?
	252	0x40123fcc():
	253	-> 0x401186c8(): Display list parser?
254	254
255		0x40117fb4(): Insert command to disp list. R3 = command word
	255	0x40117fb4(): Insert command to disp list. R3 = command word
256	256
257		Display list format
258		-------------------
259		0xffff0010: ?
	257	Display list format
	258	-------------------
	259	0xffff0010: ?
260	260
261		0xffff0011: Draw Polygon Object
262		0 = Polygon data address (21 bits) in screen RAM (in dwords). If 0x400000 set, no matrix.
263		1 = Object scale (float), if <1.0f multiply scale by 2.0f
264		2 = 0x80 = object alpha enable, 0x1f = object alpha (0x1f = opaque)
265		3 = ?
266		4...15 = 4x3 matrix
	261	0xffff0011: Draw Polygon Object
	262	0 = Polygon data address (21 bits) in screen RAM (in dwords). If 0x400000 set, no matrix.
	263	1 = Object scale (float), if <1.0f multiply scale by 2.0f
	264	2 = 0x80 = object alpha enable, 0x1f = object alpha (0x1f = opaque)
	265	3 = ?
	266	4...15 = 4x3 matrix
267	267
268		0xffff0020: ? (no parameters)
269
270		0xffff0021: Draw Pretransformed Polygon (used for drawing the background images)
271		0 = address? (if 0x400 set, 24 words)
272		1 = Texture number (* 0x4000 to address the texture)
273		2 = ?
274		3 = ? (usually 0)
275
276		Vertex data: 4x or 5x 4 words
277		0 = XY coordinates. X = high 16 bits, Y = low 16 bits
278		1 = Z value?
279		2 = UV coordinates. U = high 16 bits, V = low 16 bits (possibly shifted left by 4?)
280		3 = ? (usually 0)
281
282		0xffff0022: ? (1 word)
283		0 = ? (Set to 0x00000001 before drawing the background. Z-buffer read disable?)
284
285		0xffff0030: ? (2 + n words) FIFO write?
286		0 = ?
287		1 = num of words
288		n words = ?
289
290		0xffff0080: Display List Call?
291
292		0xffff00ff: End of List?
	268	0xffff0020: ? (no parameters)
293	269
294		Polygon data format
295		-------------------
	270	0xffff0021: Draw Pretransformed Polygon (used for drawing the background images)
	271	0 = address? (if 0x400 set, 24 words)
	272	1 = Texture number (* 0x4000 to address the texture)
	273	2 = ?
	274	3 = ? (usually 0)
296	275
297		Word 0:
298		---x---- -------- -------- -------- 1: this is the last polygon of the model
299		-------x -------- -------- -------- 0: triangle, 1: quad
300		-------- -------- -----xxx xxxxxxxx Texture number (* 0x4000 to address the texture)
	276	Vertex data: 4x or 5x 4 words
	277	0 = XY coordinates. X = high 16 bits, Y = low 16 bits
	278	1 = Z value?
	279	2 = UV coordinates. U = high 16 bits, V = low 16 bits (possibly shifted left by 4?)
	280	3 = ? (usually 0)
301	281
302		Word 1:
303		?
	282	0xffff0022: ? (1 word)
	283	0 = ? (Set to 0x00000001 before drawing the background. Z-buffer read disable?)
304	284
305		Word 2:
306		?
	285	0xffff0030: ? (2 + n words) FIFO write?
	286	0 = ?
	287	1 = num of words
	288	n words = ?
307	289
308		Word 3:
309		?
	290	0xffff0080: Display List Call?
310	291
311		Vertex data: 3x (triangle) or 4x (quad) 4 words
312		Word 0:
313		-------- -------- -------- xxxxxxxx Texture V coordinate (0..63 with max 4x repeat)
314		-------- -------- xxxxxxxx -------- Texture U coordinate (0..63 with max 4x repeat)
315		-------- xxxxxxxx -------- -------- Usually 0x40. HUD elements set 0xff. Self-illumination?
	292	0xffff00ff: End of List?
316	293
317		Word 1:
318		-------- -------- xxxxxxxx xxxxxxxx Vertex X coordinate (signed 8.8 fixed point)
319		-------- xxxxxxxx -------- -------- Normal X (signed 1.7 fixed point)
	294	Polygon data format
	295	-------------------
320	296
321		Word 2:
322		-------- -------- xxxxxxxx xxxxxxxx Vertex Y coordinate (signed 8.8 fixed point)
323		-------- xxxxxxxx -------- -------- Normal Y (signed 1.7 fixed point)
	297	Word 0:
	298	---x---- -------- -------- -------- 1: this is the last polygon of the model
	299	-------x -------- -------- -------- 0: triangle, 1: quad
	300	-------- -------- -----xxx xxxxxxxx Texture number (* 0x4000 to address the texture)
324	301
325		Word 3:
326		-------- -------- xxxxxxxx xxxxxxxx Vertex Z coordinate (signed 8.8 fixed point)
327		-------- xxxxxxxx -------- -------- Normal Z (signed 1.7 fixed point)
	302	Word 1:
	303	?
328	304
329		3D registers
330		------------
	305	Word 2:
	306	?
331	307
332		0x00000100: xxxxxxxx xxxxxxxx -------- -------- Viewport Y?
333		-------- -------- xxxxxxxx xxxxxxxx Viewport X?
	308	Word 3:
	309	?
334	310
335		0x00000101: xxxxxxxx xxxxxxxx -------- -------- Viewport center X? (usually 255 or 240)
336		-------- -------- xxxxxxxx xxxxxxxx Viewport center Y? (usually 200 or 191)
	311	Vertex data: 3x (triangle) or 4x (quad) 4 words
	312	Word 0:
	313	-------- -------- -------- xxxxxxxx Texture V coordinate (0..63 with max 4x repeat)
	314	-------- -------- xxxxxxxx -------- Texture U coordinate (0..63 with max 4x repeat)
	315	-------- xxxxxxxx -------- -------- Usually 0x40. HUD elements set 0xff. Self-illumination?
337	316
338		0x00000102: xxxxxxxx xxxxxxxx -------- -------- ? (usually 0x100)
339		-------- -------- xxxxxxxx xxxxxxxx ? (usually 0x100 or 0xc0)
	317	Word 1:
	318	-------- -------- xxxxxxxx xxxxxxxx Vertex X coordinate (signed 8.8 fixed point)
	319	-------- xxxxxxxx -------- -------- Normal X (signed 1.7 fixed point)
340	320
341		0x00000103:
	321	Word 2:
	322	-------- -------- xxxxxxxx xxxxxxxx Vertex Y coordinate (signed 8.8 fixed point)
	323	-------- xxxxxxxx -------- -------- Normal Y (signed 1.7 fixed point)
342	324
343		0x00000104:
	325	Word 3:
	326	-------- -------- xxxxxxxx xxxxxxxx Vertex Z coordinate (signed 8.8 fixed point)
	327	-------- xxxxxxxx -------- -------- Normal Z (signed 1.7 fixed point)
344	328
345		0x10000100:
	329	3D registers
	330	------------
346	331
347		0x10000101:
	332	0x00000100: xxxxxxxx xxxxxxxx -------- -------- Viewport Y?
	333	-------- -------- xxxxxxxx xxxxxxxx Viewport X?
348	334
349		0x10000102: xxxxxxxx xxxxxxxx -------- -------- Diffuse light color (ARGB1555)
350		-------- -------- xxxxxxxx xxxxxxxx Ambient light color (ARGB1555)
351
352		0x10000103:
	335	0x00000101: xxxxxxxx xxxxxxxx -------- -------- Viewport center X? (usually 255 or 240)
	336	-------- -------- xxxxxxxx xxxxxxxx Viewport center Y? (usually 200 or 191)
353	337
354		0x10000104:
355
356		0x10000105:
	338	0x00000102: xxxxxxxx xxxxxxxx -------- -------- ? (usually 0x100)
	339	-------- -------- xxxxxxxx xxxxxxxx ? (usually 0x100 or 0xc0)
	340
	341	0x00000103:
	342
	343	0x00000104:
	344
	345	0x10000100:
	346
	347	0x10000101:
	348
	349	0x10000102: xxxxxxxx xxxxxxxx -------- -------- Diffuse light color (ARGB1555)
	350	-------- -------- xxxxxxxx xxxxxxxx Ambient light color (ARGB1555)
	351
	352	0x10000103:
	353
	354	0x10000104:
	355
	356	0x10000105:
357	357	*/
358	358
359	359	#define LOG_PPC_TO_TLCS_COMMANDS 1
r15704	r15705
418	418	POLY_NY = 4,
419	419	POLY_NZ = 5,
420	420	};
421
	421
422	422	//static const float ZBUFFER_MAX = 10000000000.0f;
423	423
424	424	bitmap_rgb32 *m_fb;
r15704	r15705
443	443	int m_specular_r;
444	444	int m_specular_g;
445	445	int m_specular_b;
446
	446
447	447	float m_vp_center_x;
448	448	float m_vp_center_y;
449	449	float m_vp_focus;
r15704	r15705
509	509
510	510	UINT8 m_rtcdata[8];
511	511
512
513	512
	513
514	514	UINT32 m_reg105;
515	515	UINT32 m_displist_addr;
516	516	int m_count;
r15704	r15705
522	522	static void taitotz_exit(running_machine &machine)
523	523	{
524	524	/*
525		taitotz_state *state = machine.driver_data<taitotz_state>();
	525	taitotz_state *state = machine.driver_data<taitotz_state>();
526	526
527		FILE *file;
528		int i;
	527	FILE *file;
	528	int i;
529	529
530		file = fopen("screen_ram.bin","wb");
531		for (i=0; i < 0x200000; i++)
532		{
533		fputc((UINT8)(state->m_screen_ram[i] >> 24), file);
534		fputc((UINT8)(state->m_screen_ram[i] >> 16), file);
535		fputc((UINT8)(state->m_screen_ram[i] >> 8), file);
536		fputc((UINT8)(state->m_screen_ram[i] >> 0), file);
537		}
538		fclose(file);
	530	file = fopen("screen_ram.bin","wb");
	531	for (i=0; i < 0x200000; i++)
	532	{
	533	fputc((UINT8)(state->m_screen_ram[i] >> 24), file);
	534	fputc((UINT8)(state->m_screen_ram[i] >> 16), file);
	535	fputc((UINT8)(state->m_screen_ram[i] >> 8), file);
	536	fputc((UINT8)(state->m_screen_ram[i] >> 0), file);
	537	}
	538	fclose(file);
539	539
540		file = fopen("frame_ram.bin","wb");
541		for (i=0; i < 0x80000; i++)
542		{
543		fputc((UINT8)(state->m_frame_ram[i] >> 24), file);
544		fputc((UINT8)(state->m_frame_ram[i] >> 16), file);
545		fputc((UINT8)(state->m_frame_ram[i] >> 8), file);
546		fputc((UINT8)(state->m_frame_ram[i] >> 0), file);
547		}
548		fclose(file);
	540	file = fopen("frame_ram.bin","wb");
	541	for (i=0; i < 0x80000; i++)
	542	{
	543	fputc((UINT8)(state->m_frame_ram[i] >> 24), file);
	544	fputc((UINT8)(state->m_frame_ram[i] >> 16), file);
	545	fputc((UINT8)(state->m_frame_ram[i] >> 8), file);
	546	fputc((UINT8)(state->m_frame_ram[i] >> 0), file);
	547	}
	548	fclose(file);
549	549
550		file = fopen("texture_ram.bin","wb");
551		for (i=0; i < 0x800000; i++)
552		{
553		fputc((UINT8)(state->m_texture_ram[i] >> 24), file);
554		fputc((UINT8)(state->m_texture_ram[i] >> 16), file);
555		fputc((UINT8)(state->m_texture_ram[i] >> 8), file);
556		fputc((UINT8)(state->m_texture_ram[i] >> 0), file);
557		}
558		fclose(file);
559		*/
	550	file = fopen("texture_ram.bin","wb");
	551	for (i=0; i < 0x800000; i++)
	552	{
	553	fputc((UINT8)(state->m_texture_ram[i] >> 24), file);
	554	fputc((UINT8)(state->m_texture_ram[i] >> 16), file);
	555	fputc((UINT8)(state->m_texture_ram[i] >> 8), file);
	556	fputc((UINT8)(state->m_texture_ram[i] >> 0), file);
	557	}
	558	fclose(file);
	559	*/
560	560	}
561	561
562	562	static VIDEO_START( taitotz )
r15704	r15705
596	596	UINT32 i;
597	597	float x2, y;
598	598	const float threehalfs = 1.5f;
599
	599
600	600	x2 = number * 0.5f;
601	601	y = number;
602	602	i = (UINT32)&y;
603	603	i = 0x5f3759df - ( i >> 1 );
604	604	y = (float)&i;
605		y = y * ( threehalfs - ( x2 * y * y ) );
	605	y = y * ( threehalfs - ( x2 * y * y ) );
606	606	return y;
607	607	}
608	608
r15704	r15705
789	789	g = ((g * a) >> 5) + ((sg * (31 - a)) >> 5);
790	790	b = ((b * a) >> 5) + ((sb * (31 - a)) >> 5);
791	791	}
792
793	792
	793
794	794	// write to framebuffer
795	795	fb[x] = 0xff000000 \| (r << 16) \| (g << 8) \| b;
796	796	}
r15704	r15705
920	920	{
921	921	// texture coordinates
922	922	UINT8 tu = (src[index] >> 8) & 0xff;
923		UINT8 tv = (src[index] >> 0) & 0xff;
	923	UINT8 tv = (src[index] >> 0) & 0xff;
924	924	v[i].p[POLY_U] = (float)(tu);
925	925	v[i].p[POLY_V] = (float)(tv);
926	926
r15704	r15705
931	931	float px = ((float)(x) / 256.0f) * scale;
932	932	float py = ((float)(y) / 256.0f) * scale;
933	933	float pz = ((float)(z) / 256.0f) * scale;
934
	934
935	935	// normals
936	936	INT8 inx = (src[index + 1] >> 16) & 0xff;
937	937	INT8 iny = (src[index + 2] >> 16) & 0xff;
r15704	r15705
1100	1100	m_matrix[1][1]= (float)&w[9];
1101	1101	m_matrix[2][1]= (float)&w[10];
1102	1102	m_matrix[3][1]= (float)&w[11];
1103
	1103
1104	1104	m_matrix[0][2]= (float)&w[12];
1105	1105	m_matrix[1][2]= (float)&w[13];
1106	1106	m_matrix[2][2]= (float)&w[14];
r15704	r15705
1161	1161	UINT16 y = (w[4] >> 0) & 0xffff;
1162	1162	UINT16 tu = (w[6] >> 20) & 0xfff;
1163	1163	UINT16 tv = (w[6] >> 4) & 0xfff;
1164		// UINT16 z = (w[5] & 0xffff);
	1164	// UINT16 z = (w[5] & 0xffff);
1165	1165
1166	1166	v[j].x = x;
1167	1167	v[j].y = y; // batlgear needs -50 modifier here (why?)
r15704	r15705
1279	1279	bitmap.fill(0x000000, cliprect);
1280	1280	state->m_renderer->set_fb(&bitmap);
1281	1281	state->m_renderer->render_displaylist(screen.machine(), cliprect);
1282
1283	1282
	1283
1284	1284	UINT16 screen_src = (UINT16)&state->m_screen_ram[state->m_scr_base];
1285	1285
1286	1286	for (int j=0; j < 384; j++)
r15704	r15705
1329	1329	}
1330	1330
1331	1331	/*
1332		Video chip memory map
	1332	Video chip memory map
1333	1333
1334		0x800000...0x9fffff Screen RAM
1335		0x980000...7fff Char RAM
1336		0x9c0000...fffff Tile RAM?
	1334	0x800000...0x9fffff Screen RAM
	1335	0x980000...7fff Char RAM
	1336	0x9c0000...fffff Tile RAM?
1337	1337
1338		0x1000000...0x17fffff Texture RAM
	1338	0x1000000...0x17fffff Texture RAM
1339	1339
1340		0x1800000...0x187ffff Frame RAM
	1340	0x1800000...0x187ffff Frame RAM
1341	1341
1342	1342
1343		landhigh puts fullscreen images into 0x9c0000
1344		batlgr2 into 0x9e0000
	1343	landhigh puts fullscreen images into 0x9c0000
	1344	batlgr2 into 0x9e0000
1345	1345	*/
1346	1346
1347	1347	static UINT32 video_mem_r(taitotz_state *state, UINT32 address)
r15704	r15705
1407	1407
1408	1408	if (reg != 0x20000008)
1409	1409	logerror("video_reg_r: reg: %08X\n", reg);
1410
	1410
1411	1411	if (subreg < 0x10)
1412	1412	{
1413	1413	return state->m_video_unk_reg[subreg];
r15704	r15705
1500	1500	{
1501	1501	UINT64 r = 0;
1502	1502	UINT32 reg = offset * 8;
1503
	1503
1504	1504	if (ACCESSING_BITS_0_31)
1505	1505	{
1506	1506	reg += 4;
r15704	r15705
1600	1600	}
1601	1601	case 0x3:
1602	1602	{
1603		// video_chip_w: port 0x08: 30000001 gets spammed a lot
	1603	// video_chip_w: port 0x08: 30000001 gets spammed a lot
1604	1604	break;
1605	1605	}
1606	1606	default:
r15704	r15705
1666	1666	else if (command == 0x1)
1667	1667	{
1668	1668	// FIFO command/packet write
1669
	1669
1670	1670	if (ACCESSING_BITS_32_63)
1671	1671	{
1672	1672	if (m_video_fifo_ptr >= 8)
r15704	r15705
1734	1734	READ64_MEMBER(taitotz_state::ppc_common_r)
1735	1735	{
1736	1736	UINT64 res = 0;
1737
	1737
1738	1738	if (ACCESSING_BITS_0_15)
1739	1739	{
1740	1740	res \|= m_io_share_ram[(offset * 2) + 1];
r15704	r15705
1801	1801	m_io_share_ram[0x1c1a/2]
1802	1802	);
1803	1803	}
1804
	1804
1805	1805	/*
1806		if (m_io_share_ram[0xfff] == 0x1010)
1807		{
1808		printf(" %04X %04X %04X %04X\n", m_io_share_ram[0x1a02/2], m_io_share_ram[0x1a04/2], m_io_share_ram[0x1a06/2], m_io_share_ram[0x1a08/2]);
1809		}
1810		*/
1811
	1806	if (m_io_share_ram[0xfff] == 0x1010)
	1807	{
	1808	printf(" %04X %04X %04X %04X\n", m_io_share_ram[0x1a02/2], m_io_share_ram[0x1a04/2], m_io_share_ram[0x1a06/2], m_io_share_ram[0x1a08/2]);
	1809	}
	1810	*/
	1811
1812	1812	#endif
1813	1813
1814	1814
r15704	r15705
1935	1935	if (m_io_share_ram[0xfff] == 0 && m_io_share_ram[0xffe] == 0x1012)
1936	1936	{
1937	1937	//device_spin_until_trigger(machine().device("iocpu"), TLCS_PPC_COMM_TRIGGER);
1938		device_yield(machine().device("iocpu"));
	1938	device_yield(machine().device("iocpu"));
1939	1939	machine().scheduler().trigger(PPC_TLCS_COMM_TRIGGER);
1940	1940	}
1941	1941	}
r15704	r15705
2048	2048	{
2049	2049	//static UINT16 ide_reg_latch;
2050	2050	int reg = offset >> 1;
2051
	2051
2052	2052	if (reg != 6)
2053	2053	fatalerror("tlcs_ide1_r: %02X\n", offset);
2054	2054
r15704	r15705
2116	2116	{
2117	2117	case 0x7:
2118	2118	//if (data != 0xff && data != 0xfa && data != 0xfe)
2119		// printf("tlcs900_port_write %02X, %02X\n", offset, data);
	2119	// printf("tlcs900_port_write %02X, %02X\n", offset, data);
2120	2120	break;
2121	2121
2122	2122	case 0x8:
r15704	r15705
2128	2128
2129	2129	case 0x9:
2130	2130	//if (data != 0x00)
2131		// printf("tlcs900_port_write %02X, %02X\n", offset, data);
	2131	// printf("tlcs900_port_write %02X, %02X\n", offset, data);
2132	2132	break;
2133	2133
2134	2134	case 0xb:
r15704	r15705
2142	2142
2143	2143	// TLCS900 interrupt vectors
2144	2144	// 0xfc0150: Reset
2145		// 0xfc0120: SWI1-7 -
2146		// 0xfc0120: NMI -
2147		// 0xfc0120: INTWD -
2148		// 0xfc0122: INT0 PPC communication
2149		// 0xfc0137: INT1 IEEE1394?
2150		// 0xfc013c: INT2 IDE
2151		// 0xfc0141: INT3 VBlank? Drives a counter on PPC side
2152		// 0xfc0146: INT4 -
2153		// 0xfc0147: INT5 -
2154		// 0xfc0148: INT6 -
2155		// 0xfc0149: INT7 -
2156		// 0xfc014a: INT8 Sound chip interrupt?
2157		// 0xfc0120: INTAD -
2158		// 0xfc0120: INTTR8-A -
2159		// 0xfc0120: INTT0 -
2160		// 0xfc0467: INTT1 A/D Conversion
2161		// 0xfc0120: INTT2-7 -
2162		// 0xfc0120: INTTC0-3 -
2163		// 0xfc0d1d: INTRX0 Serial 0 receive
2164		// 0xfc0ca5: INTTX0 Serial 0 transmit
2165		// 0xfc0d55: INTRX1 Serial 1 receive
2166		// 0xfc0ce1: INTTX1 Serial 1 transmit
	2145	// 0xfc0120: SWI1-7 -
	2146	// 0xfc0120: NMI -
	2147	// 0xfc0120: INTWD -
	2148	// 0xfc0122: INT0 PPC communication
	2149	// 0xfc0137: INT1 IEEE1394?
	2150	// 0xfc013c: INT2 IDE
	2151	// 0xfc0141: INT3 VBlank? Drives a counter on PPC side
	2152	// 0xfc0146: INT4 -
	2153	// 0xfc0147: INT5 -
	2154	// 0xfc0148: INT6 -
	2155	// 0xfc0149: INT7 -
	2156	// 0xfc014a: INT8 Sound chip interrupt?
	2157	// 0xfc0120: INTAD -
	2158	// 0xfc0120: INTTR8-A -
	2159	// 0xfc0120: INTT0 -
	2160	// 0xfc0467: INTT1 A/D Conversion
	2161	// 0xfc0120: INTT2-7 -
	2162	// 0xfc0120: INTTC0-3 -
	2163	// 0xfc0d1d: INTRX0 Serial 0 receive
	2164	// 0xfc0ca5: INTTX0 Serial 0 transmit
	2165	// 0xfc0d55: INTRX1 Serial 1 receive
	2166	// 0xfc0ce1: INTTX1 Serial 1 transmit
2167	2167
2168	2168	static ADDRESS_MAP_START( tlcs900h_mem, AS_PROGRAM, 8, taitotz_state)
2169	2169	AM_RANGE(0x010000, 0x02ffff) AM_RAM // Work RAM
r15704	r15705
2233	2233	PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_BUTTON7 ) // View 5
2234	2234	PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_BUTTON8 ) // View 6
2235	2235	PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON3 ) // View 1
2236		PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON4 ) // View 2
	2236	PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON4 ) // View 2
2237	2237	PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_BUTTON1 ) // Select 1
2238	2238	PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_BUTTON2 ) // Select 2
2239	2239	INPUT_PORTS_END
r15704	r15705
2510	2510	{
2511	2511	UINT32 rom = (UINT32)machine.root_device().memregion("user1")->base();
2512	2512	rom[(0x2c87c^4)/4] = 0x38600000; // skip sound load timeout...
2513		// rom[(0x2c620^4)/4] = 0x48000014; // ID check skip (not needed with correct serial number)
	2513	// rom[(0x2c620^4)/4] = 0x48000014; // ID check skip (not needed with correct serial number)
2514	2514	}
2515	2515
2516	2516	// Init for BIOS 1.11a
r15704	r15705
2561	2561	taitotz_state *state = machine.driver_data<taitotz_state>();
2562	2562
2563	2563	init_taitotz_152(machine);
2564
	2564
2565	2565	state->m_hdd_serial_number = BATLGR2_HDD_SERIAL;
2566
	2566
2567	2567	state->m_scr_base = 0x1e0000;
2568	2568
2569	2569	state->m_displist_addr = 0x3608e4;
r15704	r15705
2574	2574	taitotz_state *state = machine.driver_data<taitotz_state>();
2575	2575
2576	2576	init_taitotz_152(machine);
2577
	2577
2578	2578	state->m_hdd_serial_number = BATLGR2A_HDD_SERIAL;
2579
	2579
2580	2580	state->m_scr_base = 0x1e0000;
2581	2581
2582	2582	state->m_displist_addr = 0x3608e4;
r15704	r15705
2587	2587	taitotz_state *state = machine.driver_data<taitotz_state>();
2588	2588
2589	2589	init_taitotz_111a(machine);
2590
	2590
2591	2591	// unknown, not used by BIOS 1.11a
2592	2592	state->m_hdd_serial_number = NULL;
2593
	2593
2594	2594	state->m_scr_base = 0x1c0000;
2595	2595
2596	2596	state->m_displist_addr = 0x4a989c;

src/mame/drivers/jpmsru.c
r15704	r15705
2	2
3	3	JPM S.R.U Hardware
4	4
5		The Stepper Reel Unit (SRU) was the first JPM hardware platform
6		to use CPU based technology as opposed to a purely mechanical
7		setup.
8
9		It really shows that this is the antecedent of System 80,
10		the sound hardware seems to be a basic discrete circuit (complete
11		with tone pot), and the hardware uses the older TMS9980A as a CPU.
12
13		TODO: Everything!
14
	5	The Stepper Reel Unit (SRU) was the first JPM hardware platform
	6	to use CPU based technology as opposed to a purely mechanical
	7	setup.
	8
	9	It really shows that this is the antecedent of System 80,
	10	the sound hardware seems to be a basic discrete circuit (complete
	11	with tone pot), and the hardware uses the older TMS9980A as a CPU.
	12
	13	TODO: Everything!
	14
15	15	**********************************************************************/
16	16
17	17	#include "emu.h"

src/mame/drivers/taito_l.c
r15704	r15705
2147	2147	ROM_LOAD( "b36-11-1.bin", 0x00000, 0x20000, CRC(f19fb0d5) SHA1(ba7187dfa5b4a08cebf236913a80066dafbbc59f) )
2148	2148	ROM_LOAD( "b36-09.bin", 0x20000, 0x20000, CRC(9c466e43) SHA1(2466a3f1f8124323008c9925f90e9a1d2edf1564) )
2149	2149
2150		ROM_REGION( 0x10000, "audiocpu", 0 )
	2150	ROM_REGION( 0x10000, "audiocpu", 0 )
2151	2151	ROM_LOAD( "b36-06.bin", 0x00000, 0x10000, CRC(29bbc4f8) SHA1(39a68729c6180c5f6cdf604e692018e7d6bf5591) )
2152	2152
2153	2153	ROM_REGION( 0x10000, "slave", 0 )
r15704	r15705
2166	2166	ROM_LOAD( "b36-08-1.bin", 0x00000, 0x20000, CRC(6cc8f79f) SHA1(17b4903f87e6d5447c8557c2baca1728f86245dc) )
2167	2167	ROM_LOAD( "b36-09.bin", 0x20000, 0x20000, CRC(9c466e43) SHA1(2466a3f1f8124323008c9925f90e9a1d2edf1564) )
2168	2168
2169		ROM_REGION( 0x10000, "audiocpu", 0 )
	2169	ROM_REGION( 0x10000, "audiocpu", 0 )
2170	2170	ROM_LOAD( "b36-06.bin", 0x00000, 0x10000, CRC(29bbc4f8) SHA1(39a68729c6180c5f6cdf604e692018e7d6bf5591) )
2171	2171
2172	2172	ROM_REGION( 0x10000, "slave", 0 )
r15704	r15705
2185	2185	ROM_LOAD( "b36-08.bin", 0x00000, 0x20000, CRC(f40b9178) SHA1(ccf5afcf08cac0d5b2d6ba74abd62d35412f0265) )
2186	2186	ROM_LOAD( "b36-09.bin", 0x20000, 0x20000, CRC(9c466e43) SHA1(2466a3f1f8124323008c9925f90e9a1d2edf1564) )
2187	2187
2188		ROM_REGION( 0x10000, "audiocpu", 0 )
	2188	ROM_REGION( 0x10000, "audiocpu", 0 )
2189	2189	ROM_LOAD( "b36-06.bin", 0x00000, 0x10000, CRC(29bbc4f8) SHA1(39a68729c6180c5f6cdf604e692018e7d6bf5591) )
2190	2190
2191	2191	ROM_REGION( 0x10000, "slave", 0 )
r15704	r15705
2204	2204	ROM_LOAD( "b70-11.bin", 0x00000, 0x20000, CRC(7d9f7583) SHA1(d8fa7c66a81fb356fa9c72f377bfc31b1837eafb) )
2205	2205	ROM_LOAD( "b70-03.bin", 0x20000, 0x80000, CRC(42d5a9b8) SHA1(10714fe95c372cec12376e615a9abe213aff12bc) )
2206	2206
2207		ROM_REGION( 0x10000, "audiocpu", 0 )
	2207	ROM_REGION( 0x10000, "audiocpu", 0 )
2208	2208	ROM_LOAD( "b70-09.bin", 0x00000, 0x10000, CRC(85cccaa2) SHA1(5459cd8df9d94e1938008cfc17d4ebac98004bfc) )
2209	2209
2210	2210	ROM_REGION( 0x20000, "slave", 0 )
r15704	r15705
2220	2220	ROM_LOAD( "b70-07.bin", 0x00000, 0x20000, CRC(939114af) SHA1(66218536dcb3b34ffa01d3c9c2fee365d91cfe00) )
2221	2221	ROM_LOAD( "b70-03.bin", 0x20000, 0x80000, CRC(42d5a9b8) SHA1(10714fe95c372cec12376e615a9abe213aff12bc) )
2222	2222
2223		ROM_REGION( 0x10000, "audiocpu", 0 )
	2223	ROM_REGION( 0x10000, "audiocpu", 0 )
2224	2224	ROM_LOAD( "b70-09.bin", 0x00000, 0x10000, CRC(85cccaa2) SHA1(5459cd8df9d94e1938008cfc17d4ebac98004bfc) )
2225	2225
2226	2226	ROM_REGION( 0x20000, "slave", 0 )
r15704	r15705
2236	2236	ROM_LOAD( "c01-13.rom", 0x00000, 0x20000, CRC(7ef47525) SHA1(79789fa3bcaeb6666c108d2e4b69a1f9341b2f4a) )
2237	2237	ROM_LOAD( "c01-04.rom", 0x20000, 0x20000, CRC(358bd076) SHA1(beb20a09370d05de719dde596eadca8fecb14ce5) )
2238	2238
2239		ROM_REGION( 0x10000, "audiocpu", 0 )
	2239	ROM_REGION( 0x10000, "audiocpu", 0 )
2240	2240	ROM_LOAD( "c01-08.rom", 0x00000, 0x10000, CRC(810efff8) SHA1(dd4fc046095e0e815e8e1fd96d258da0d6bba298) )
2241	2241
2242	2242	ROM_REGION( 0x20000, "slave", 0 )
r15704	r15705
2256	2256	ROM_LOAD( "c01-12.rom", 0x00000, 0x20000, CRC(09f345b3) SHA1(f3f9a7dab0b3f87b6919a7b37cb52245e112cb08) )
2257	2257	ROM_LOAD( "c01-04.rom", 0x20000, 0x20000, CRC(358bd076) SHA1(beb20a09370d05de719dde596eadca8fecb14ce5) )
2258	2258
2259		ROM_REGION( 0x10000, "audiocpu", 0 )
	2259	ROM_REGION( 0x10000, "audiocpu", 0 )
2260	2260	ROM_LOAD( "c01-08.rom", 0x00000, 0x10000, CRC(810efff8) SHA1(dd4fc046095e0e815e8e1fd96d258da0d6bba298) )
2261	2261
2262	2262	ROM_REGION( 0x20000, "slave", 0 )
r15704	r15705
2276	2276	ROM_LOAD( "c01-06.bin", 0x00000, 0x20000, CRC(90fa1409) SHA1(7904488d567ce5d8705b2d2c8a4b4aae310cc28b) )
2277	2277	ROM_LOAD( "c01-04.rom", 0x20000, 0x20000, CRC(358bd076) SHA1(beb20a09370d05de719dde596eadca8fecb14ce5) )
2278	2278
2279		ROM_REGION( 0x10000, "audiocpu", 0 )
	2279	ROM_REGION( 0x10000, "audiocpu", 0 )
2280	2280	ROM_LOAD( "c01-08.rom", 0x00000, 0x10000, CRC(810efff8) SHA1(dd4fc046095e0e815e8e1fd96d258da0d6bba298) )
2281	2281
2282	2282	ROM_REGION( 0x20000, "slave", 0 )

src/mame/drivers/globalvr.c
r15704	r15705
155	155	GAME( 2005, nfsug, 0, globalvr, globalvr, 0, ROT0, "Gloval VR", "Need For Speed: Underground Install (2 Discs) (v1.1)", GAME_IS_SKELETON )
156	156
157	157
158
	158

src/mame/drivers/cyclemb.c
r15704	r15705
1	1	/***************************************************************************************************
2	2
3	3	Cycle Mahbou (c) 1984 Taito Corporation / Seta
4		Sky Destroyer (c9 1985 Taito Corporation
	4	Sky Destroyer (c9 1985 Taito Corporation
5	5
6	6	appears to be in the exact middle between the gsword / josvolly HW and the ppking / gladiator HW
7	7
r15704	r15705
237	237	int x,y;
238	238	//UINT8 flip_screen = state->flip_screen();
239	239	/*
240		char tempstring[1024];
	240	char tempstring[1024];
241	241
242		for (x=0;x<64;x++)
243		{
244		if (x<32)
245		sprintf(tempstring, "%s %02x", tempstring, state->m_vram[x*64+0]);
246		else
247		sprintf(tempstring, "%s %02x", tempstring, state->m_vram[(x-32)*64+1]);
248		}
	242	for (x=0;x<64;x++)
	243	{
	244	if (x<32)
	245	sprintf(tempstring, "%s %02x", tempstring, state->m_vram[x*64+0]);
	246	else
	247	sprintf(tempstring, "%s %02x", tempstring, state->m_vram[(x-32)*64+1]);
	248	}
249	249
250		printf("%s", tempstring);
	250	printf("%s", tempstring);
251	251	*/
252	252
253	253	for (y=0;y<32;y++)
r15704	r15705
300	300	UINT16 spr_offs,i;
301	301	INT16 x,y;
302	302
303		// popmessage("%d %d",state->m_obj2_ram[0x0d], 0xf1 - state->m_obj2_ram[0x0c+1] + 68);
	303	// popmessage("%d %d",state->m_obj2_ram[0x0d], 0xf1 - state->m_obj2_ram[0x0c+1] + 68);
304	304
305	305	for(i=0;i<0x80;i+=2)
306	306	{
r15704	r15705
314	314	if(region == 2)
315	315	{
316	316	spr_offs >>= 2;
317		// spr_offs += ((state->m_obj3_ram[i+0] & 3) << 5);
	317	// spr_offs += ((state->m_obj3_ram[i+0] & 3) << 5);
318	318	x-=16;
319	319	}
320	320
r15704	r15705
459	459	printf("%02x\n",skydest_mcu.txd);
460	460	skydest_mcu.rxd = 0x00;
461	461	}
462		// skydest_mcu.rxd = space->machine().rand();
463		// break;
	462	// skydest_mcu.rxd = space->machine().rand();
	463	// break;
464	464	}
465	465	}
466	466
r15704	r15705
1005	1005	MCFG_SCREEN_VISIBLE_AREA(28, 348-1, 28, 308-1)
1006	1006	MCFG_SCREEN_UPDATE_STATIC(skydest)
1007	1007
1008		// MCFG_PALETTE_INIT(skydest)
	1008	// MCFG_PALETTE_INIT(skydest)
1009	1009	MACHINE_CONFIG_END
1010	1010
1011	1011	/***************************************************************************
r15704	r15705
1066	1066
1067	1067	ROM_REGION( 0x10000, "sprite_data_1", ROMREGION_ERASEFF )
1068	1068	ROM_LOAD( "pd0-7.1k", 0x000000, 0x002000, CRC(83137d42) SHA1(7e35f28577d6bfeee184a0ac3095b478999d6477) ) //ok
1069		ROM_LOAD( "pd1-8.1l", 0x002000, 0x002000, CRC(b810858b) SHA1(385e625fc989a1dfa18559a62c99363b62c66a67) ) //ok
	1069	ROM_LOAD( "pd1-8.1l", 0x002000, 0x002000, CRC(b810858b) SHA1(385e625fc989a1dfa18559a62c99363b62c66a67) ) //ok
1070	1070	ROM_LOAD( "pd0-9.1m", 0x004000, 0x002000, CRC(6f558bee) SHA1(0539feaa848d6cfb9f90a46a851f73fb74e82676) ) //ok
1071	1071	ROM_LOAD( "pd1-10.1n", 0x006000, 0x002000, CRC(5840b5b5) SHA1(1b5b188023c4d3198402c946b8c5a51d7f512a07) )
1072	1072	ROM_LOAD( "pd0-11.1r", 0x008000, 0x002000, CRC(29e5fce4) SHA1(59748e3a192a45dce7920e8d5a7a11d5145915b0) ) //ok
1073		ROM_LOAD( "pd0-12.1s", 0x00a000, 0x002000, CRC(06234942) SHA1(1cc40a8c8e24ab6db1dc7dc88979be23b7a9cab6) )
	1073	ROM_LOAD( "pd0-12.1s", 0x00a000, 0x002000, CRC(06234942) SHA1(1cc40a8c8e24ab6db1dc7dc88979be23b7a9cab6) )
1074	1074	ROM_LOAD( "pd1-13.1t", 0x00c000, 0x002000, CRC(3cca5b95) SHA1(74baec7c128254c394dd3162df7abacf5ed5a99b) ) //ok
1075	1075	ROM_LOAD( "pd0-14.1u", 0x00e000, 0x002000, CRC(7ef05b01) SHA1(f36ad1c0dac201729def78dc18feacda8fcf1a3f) )
1076	1076

src/mame/drivers/cobra.c
r15704	r15705
2	2	*/
3	3
4	4	/*
5		check_color_buffer(): 0, 0
6		gfxfifo_exec: ram write 00100: 00000800
7		gfxfifo_exec: ram write 00104: 00000000
8		gfxfifo_exec: ram write 00108: 00000080
9		gfxfifo_exec: ram write 0010C: 00000080
10		gfxfifo_exec: ram write 00110: 20200000
11		gfxfifo_exec: ram write 00120: 08800800
12		gfxfifo_exec: ram write 00124: 00081018
13		gfxfifo_exec: ram write 00128: 08080808
14		gfxfifo_exec: ram write 80100: 00800000
15		gfxfifo_exec: ram write 80104: 00800000
16		gfxfifo_exec: ram write 80110: 00800000
17		gfxfifo_exec: ram write 800A8: 00000000
18		gfxfifo_exec: ram write 80108: 00000000
	5	check_color_buffer(): 0, 0
	6	gfxfifo_exec: ram write 00100: 00000800
	7	gfxfifo_exec: ram write 00104: 00000000
	8	gfxfifo_exec: ram write 00108: 00000080
	9	gfxfifo_exec: ram write 0010C: 00000080
	10	gfxfifo_exec: ram write 00110: 20200000
	11	gfxfifo_exec: ram write 00120: 08800800
	12	gfxfifo_exec: ram write 00124: 00081018
	13	gfxfifo_exec: ram write 00128: 08080808
	14	gfxfifo_exec: ram write 80100: 00800000
	15	gfxfifo_exec: ram write 80104: 00800000
	16	gfxfifo_exec: ram write 80110: 00800000
	17	gfxfifo_exec: ram write 800A8: 00000000
	18	gfxfifo_exec: ram write 80108: 00000000
19	19
20		check_color_buffer(): 0, 1
21		gfxfifo_exec: ram write 00120: 08800800
22		gfxfifo_exec: ram write 00124: 00081018
23		gfxfifo_exec: ram write 00128: 08080808
24		gfxfifo_exec: ram write 80100: 00200000
25		gfxfifo_exec: ram write 80104: 00200000
26		gfxfifo_exec: ram write 80110: 00200000
27		gfxfifo_exec: ram write 800A8: 00000000
	20	check_color_buffer(): 0, 1
	21	gfxfifo_exec: ram write 00120: 08800800
	22	gfxfifo_exec: ram write 00124: 00081018
	23	gfxfifo_exec: ram write 00128: 08080808
	24	gfxfifo_exec: ram write 80100: 00200000
	25	gfxfifo_exec: ram write 80104: 00200000
	26	gfxfifo_exec: ram write 80110: 00200000
	27	gfxfifo_exec: ram write 800A8: 00000000
28	28
29		check_overlay_buffer():
30		gfxfifo_exec: ram write 00120: 08800800
31		gfxfifo_exec: ram write 00124: 00081018
32		gfxfifo_exec: ram write 00128: 08080808
33		gfxfifo_exec: ram write 80100: 000E0000
34		gfxfifo_exec: ram write 80104: 000E0000
35		gfxfifo_exec: ram write 80110: 000E0000
36		gfxfifo_exec: ram write 800A8: 00000000
	29	check_overlay_buffer():
	30	gfxfifo_exec: ram write 00120: 08800800
	31	gfxfifo_exec: ram write 00124: 00081018
	32	gfxfifo_exec: ram write 00128: 08080808
	33	gfxfifo_exec: ram write 80100: 000E0000
	34	gfxfifo_exec: ram write 80104: 000E0000
	35	gfxfifo_exec: ram write 80110: 000E0000
	36	gfxfifo_exec: ram write 800A8: 00000000
37	37
38		check_z_buffer():
39		gfxfifo_exec: ram write 00120: 08000800
40		gfxfifo_exec: ram write 00124: 00000010
41		gfxfifo_exec: ram write 00128: 00001010
42		gfxfifo_exec: ram write 80100: 00000000
43		gfxfifo_exec: ram write 80104: 00000800
44		gfxfifo_exec: ram write 80110: 00000800
45		gfxfifo_exec: ram write 800A8: 80000000
	38	check_z_buffer():
	39	gfxfifo_exec: ram write 00120: 08000800
	40	gfxfifo_exec: ram write 00124: 00000010
	41	gfxfifo_exec: ram write 00128: 00001010
	42	gfxfifo_exec: ram write 80100: 00000000
	43	gfxfifo_exec: ram write 80104: 00000800
	44	gfxfifo_exec: ram write 80110: 00000800
	45	gfxfifo_exec: ram write 800A8: 80000000
46	46
47		check_stencil_buffer():
48		gfxfifo_exec: ram write 00120: 08000800
49		gfxfifo_exec: ram write 00124: 00000010
50		gfxfifo_exec: ram write 00128: 00001010
51		gfxfifo_exec: ram write 80100: 00000000
52		gfxfifo_exec: ram write 80104: 00000200
53		gfxfifo_exec: ram write 80110: 00000200
54		gfxfifo_exec: ram write 800A8: 80000000
	47	check_stencil_buffer():
	48	gfxfifo_exec: ram write 00120: 08000800
	49	gfxfifo_exec: ram write 00124: 00000010
	50	gfxfifo_exec: ram write 00128: 00001010
	51	gfxfifo_exec: ram write 80100: 00000000
	52	gfxfifo_exec: ram write 80104: 00000200
	53	gfxfifo_exec: ram write 80110: 00000200
	54	gfxfifo_exec: ram write 800A8: 80000000
55	55	*/
56	56
57	57
r15704	r15705
203	203	int m_comram_page;
204	204
205	205	bitmap_rgb32 *m_framebuffer;
206
	206
207	207	int m_main_debug_state;
208	208	int m_main_debug_state_wc;
209	209	int m_sub_debug_state;
r15704	r15705
290	290	{
291	291	int x = x1;
292	292	for (int i=0; i < abs(dx); i++)
293		{
	293	{
294	294	int y = y1 + (dy * (float)(x - x1) / (float)(dx));
295	295
296	296	UINT32 *fb = &m_fb->pix32(y);
r15704	r15705
656	656
657	657
658	658	/*
659		if (fifo_is_empty(S2MFIFO))
660		{
661		device_spin_until_time(machine().device("subcpu"), attotime::from_usec(80));
662		}
663		*/
	659	if (fifo_is_empty(S2MFIFO))
	660	{
	661	device_spin_until_time(machine().device("subcpu"), attotime::from_usec(80));
	662	}
	663	*/
664	664	}
665	665	if (ACCESSING_BITS_32_39)
666	666	{
r15704	r15705
900	900
901	901	if (m_m2sfifo->is_empty())
902	902	{
903		// cputag_set_input_line(space.machine(), "subcpu", INPUT_LINE_IRQ0, CLEAR_LINE);
	903	// cputag_set_input_line(space.machine(), "subcpu", INPUT_LINE_IRQ0, CLEAR_LINE);
904	904
905	905	// this is a hack...
906	906	// MAME has a small interrupt latency, which prevents the IRQ bit from being cleared in
r15704	r15705
911	911	r \|= (value & 0xff) << 24;
912	912
913	913	/*
914		if (fifo_is_empty(M2SFIFO))
915		{
916		device_spin_until_time(machine().device("maincpu"), attotime::from_usec(80));
917		}
918		*/
	914	if (fifo_is_empty(M2SFIFO))
	915	{
	916	device_spin_until_time(machine().device("maincpu"), attotime::from_usec(80));
	917	}
	918	*/
919	919	}
920	920	if (ACCESSING_BITS_16_23)
921	921	{
r15704	r15705
986	986
987	987	if (!s2mfifo_unk_flag)
988	988	{
989		// cputag_set_input_line(space.machine(), "subcpu", INPUT_LINE_IRQ1, ASSERT_LINE);
	989	// cputag_set_input_line(space.machine(), "subcpu", INPUT_LINE_IRQ1, ASSERT_LINE);
990	990
991	991	// this is a hack...
992	992	// MAME has a small interrupt latency, which prevents the IRQ bit from being set in
r15704	r15705
995	995	}
996	996	else
997	997	{
998		// cputag_set_input_line(space.machine(), "subcpu", INPUT_LINE_IRQ1, CLEAR_LINE);
	998	// cputag_set_input_line(space.machine(), "subcpu", INPUT_LINE_IRQ1, CLEAR_LINE);
999	999
1000	1000	// this is a hack...
1001	1001	// MAME has a small interrupt latency, which prevents the IRQ bit from being cleared in
r15704	r15705
1195	1195	AM_RANGE(0x7e000000, 0x7e000003) AM_MIRROR(0x80000000) AM_WRITE(sub_debug_w)
1196	1196	AM_RANGE(0x7e180000, 0x7e180003) AM_MIRROR(0x80000000) AM_READWRITE(sub_unk1_r, sub_unk1_w)
1197	1197	AM_RANGE(0x7e200000, 0x7e200003) AM_MIRROR(0x80000000) AM_READWRITE(sub_config_r, sub_config_w)
1198		// AM_RANGE(0x7e240000, 0x7e27ffff) AM_MIRROR(0x80000000) AM_RAM // PSAC (ROZ) in Racing Jam.
1199		// AM_RANGE(0x7e280000, 0x7e28ffff) AM_MIRROR(0x80000000) AM_RAM // LANC
1200		// AM_RANGE(0x7e300000, 0x7e30ffff) AM_MIRROR(0x80000000) AM_RAM // LANC
	1198	// AM_RANGE(0x7e240000, 0x7e27ffff) AM_MIRROR(0x80000000) AM_RAM // PSAC (ROZ) in Racing Jam.
	1199	// AM_RANGE(0x7e280000, 0x7e28ffff) AM_MIRROR(0x80000000) AM_RAM // LANC
	1200	// AM_RANGE(0x7e300000, 0x7e30ffff) AM_MIRROR(0x80000000) AM_RAM // LANC
1201	1201	AM_RANGE(0x7e380000, 0x7e380003) AM_MIRROR(0x80000000) AM_READWRITE(sub_mainbd_r, sub_mainbd_w)
1202	1202	AM_RANGE(0x7ff80000, 0x7fffffff) AM_MIRROR(0x80000000) AM_ROM AM_REGION("user2", 0) /* Boot ROM */
1203	1203	ADDRESS_MAP_END
r15704	r15705
1391	1391	case 0xa8:
1392	1392	case 0xac:
1393	1393	{
1394		// 0xA80114CC prm_flashcolor()
	1394	// 0xA80114CC prm_flashcolor()
1395	1395	// 0xA80118CC
1396	1396	// 0xA80108FF
1397	1397
1398		// 0xA80108FF prm_flashmisc()
	1398	// 0xA80108FF prm_flashmisc()
1399	1399	// 0xA80110FF
1400	1400	// 0xA8011CE0
1401	1401
1402		// 0xA401BCC0 texenvmode()
	1402	// 0xA401BCC0 texenvmode()
1403	1403
1404		// 0xA4019CC0 mode_fog()
	1404	// 0xA4019CC0 mode_fog()
1405	1405
1406		// 0xA40018C0 mode_stipple()
	1406	// 0xA40018C0 mode_stipple()
1407	1407	// 0xA400D080
1408	1408
1409		// 0xA40138E0 mode_viewclip()
	1409	// 0xA40138E0 mode_viewclip()
1410	1410
1411		// 0xA4011410 mode_scissor()
	1411	// 0xA4011410 mode_scissor()
1412	1412
1413		// 0xA40198A0 mode_alphatest()
	1413	// 0xA40198A0 mode_alphatest()
1414	1414
1415		// 0xA8002010 mode_depthtest()
	1415	// 0xA8002010 mode_depthtest()
1416	1416
1417		// 0xA800507C mode_blend()
	1417	// 0xA800507C mode_blend()
1418	1418
1419		// 0xA8001CFE mode_stenciltest()
	1419	// 0xA8001CFE mode_stenciltest()
1420	1420
1421		// 0xA8002010 mode_stencilmod()
	1421	// 0xA8002010 mode_stencilmod()
1422	1422	// 0xA80054E0
1423	1423	// 0xA8001CFE
1424	1424
1425		// 0xA80118CC mode_colormask()
	1425	// 0xA80118CC mode_colormask()
1426	1426	// 0xA80114CC
1427	1427
1428	1428	// 0xAxxxxxxx is different form in mbuslib_regwrite()
r15704	r15705
1461	1461	{
1462	1462	// E0C00004 18C003C0 - 32 params
1463	1463	// E0C00004 18F803C1 - 48 params
1464		// E0C00003 18C003C0 - 24 params prm_triangle()
1465		// E0C00008 18C003C0 - 64 params prm_trianglestrip()
1466		// E0C00001 58C003C1 - 10 params prm_trianglefan() (start vertex?)
1467		// E0800004 18C003C0 - 32 params prm_trianglefan()
1468		// E3000002 58C003C1 - 20 params prm_line()
1469		// E3000008 58C003C1 - 80 params prm_lines()
1470		// E3000005 58C003C1 - 50 params prm_linestrip()
1471		// E2000001 18C003C0 - 8 params prm_point()
1472		// E2000008 18C003C0 - 64 params prm_points()
	1464	// E0C00003 18C003C0 - 24 params prm_triangle()
	1465	// E0C00008 18C003C0 - 64 params prm_trianglestrip()
	1466	// E0C00001 58C003C1 - 10 params prm_trianglefan() (start vertex?)
	1467	// E0800004 18C003C0 - 32 params prm_trianglefan()
	1468	// E3000002 58C003C1 - 20 params prm_line()
	1469	// E3000008 58C003C1 - 80 params prm_lines()
	1470	// E3000005 58C003C1 - 50 params prm_linestrip()
	1471	// E2000001 18C003C0 - 8 params prm_point()
	1472	// E2000008 18C003C0 - 64 params prm_points()
1473	1473	// E0C00003 38C003C1 - 30 params
1474	1474	// E0C00008 38C003C1 - 80 params
1475	1475	// E0C00001 78C003C0 - 10 params
1476	1476	// E0800004 38C003C1 - 40 params
1477		// E3000002 78C003C0 - 20 params prm_line()
	1477	// E3000002 78C003C0 - 20 params prm_line()
1478	1478	// E3400002 58C003C1 - 20 params
1479	1479	// E0C00003 18F803C1 - 36 params
1480	1480	// E0C00001 58F803C0 - 12 params
r15704	r15705
1536	1536	return;
1537	1537	}
1538	1538
1539
1540	1539
	1540
1541	1541	// make sure the FIFO has fresh data at top...
1542	1542	fifo_out->flush();
1543	1543
r15704	r15705
1598	1598	}
1599	1599	}
1600	1600	/*
1601		else if (w1 == 0xe0c00003 && w2 == 0x18c003c0)
1602		{
1603		// Triangle poly packet?
1604		vertex_t vert[3];
	1601	else if (w1 == 0xe0c00003 && w2 == 0x18c003c0)
	1602	{
	1603	// Triangle poly packet?
	1604	vertex_t vert[3];
1605	1605
1606		for (i=0; i < 3; i++)
1607		{
1608		UINT64 in = 0;
1609		fifo_in->pop(NULL, &in);
	1606	for (i=0; i < 3; i++)
	1607	{
	1608	UINT64 in = 0;
	1609	fifo_in->pop(NULL, &in);
1610	1610
1611		fifo_in->pop(NULL, &in);
	1611	fifo_in->pop(NULL, &in);
1612	1612
1613		vert[i].x = (u2f((UINT32)(in)) / 8.0f) + 256.0f;
	1613	vert[i].x = (u2f((UINT32)(in)) / 8.0f) + 256.0f;
1614	1614
1615		fifo_in->pop(NULL, &in);
	1615	fifo_in->pop(NULL, &in);
1616	1616
1617		vert[i].y = (u2f((UINT32)(in)) / 8.0f) + 192.0f;
	1617	vert[i].y = (u2f((UINT32)(in)) / 8.0f) + 192.0f;
1618	1618
1619		fifo_in->pop(NULL, &in);
	1619	fifo_in->pop(NULL, &in);
1620	1620
1621		fifo_in->pop(NULL, &in);
1622		fifo_in->pop(NULL, &in);
1623		fifo_in->pop(NULL, &in);
1624		fifo_in->pop(NULL, &in);
1625		}
	1621	fifo_in->pop(NULL, &in);
	1622	fifo_in->pop(NULL, &in);
	1623	fifo_in->pop(NULL, &in);
	1624	fifo_in->pop(NULL, &in);
	1625	}
1626	1626
1627		render_delegate rd = render_delegate(FUNC(cobra_renderer::render_texture_scan), this);
1628		render_triangle(visarea, rd, 6, vert[0], vert[1], vert[2]);
1629		}
1630		*/
	1627	render_delegate rd = render_delegate(FUNC(cobra_renderer::render_texture_scan), this);
	1628	render_triangle(visarea, rd, 6, vert[0], vert[1], vert[2]);
	1629	}
	1630	*/
1631	1631	else
1632	1632	{
1633	1633	printf("gfxfifo_exec: unhandled %08X %08X\n", w1, w2);
r15704	r15705
1673	1673	fifo_in->pop(NULL, &param);
1674	1674
1675	1675	/*
1676		if (c == 0)
	1676	if (c == 0)
1677	1677	printf(" ");
1678	1678	printf("%08X ", (UINT32)(param));
1679	1679
r15704	r15705
2058	2058	if (value == 0xc0)
2059	2059	{
2060	2060	m_gfxfifo_in->pop(&space.device(), &in1);
2061		m_gfxfifo_in->pop(&space.device(), &in2);
	2061	m_gfxfifo_in->pop(&space.device(), &in2);
2062	2062	m_gfx_unknown_v1 = (UINT32)(in1 >> 32); // FIFO number is read back from this same register
2063	2063
2064	2064	m_gfxfifo_out->push(&space.device(), in1 & 0xffffffff);
r15704	r15705
2379	2379	rom[0x62094 / 4] = 0x60000000; // skip hardcheck()...
2380	2380	rom[0x62ddc / 4] = 0x60000000; // skip lanc_hardcheck()
2381	2381
2382
	2382
2383	2383	// calculate the checksum of the patched rom...
2384	2384	UINT32 sum = 0;
2385	2385	for (int i=0; i < 0x20000/4; i++)

src/mame/drivers/sfbonus.c
r15704	r15705
6173	6173	GAME( 200?, getrich, 0, sfbonus, newer1_reels3, getrich, ROT0, "Amcoe", "Get Rich (Version 1.0.1)", 0) /* After Around The World */
6174	6174
6175	6175	// no graphic / sound roms dumped for these sets, but functional program roms & descramble are in place
6176		/* Version 4 is a multi-game that has New Fruit Bonus ‘96 Special Edition Ver. 4, New Cherry ‘96 Special Edition Ver. 4 or Skill Cherry ‘97 Ver. 4 */
	6176	/* Version 4 is a multi-game that has New Fruit Bonus ?96 Special Edition Ver. 4, New Cherry ?96 Special Edition Ver. 4 or Skill Cherry ?97 Ver. 4 */
6177	6177	GAME( 2006, version4, 0, sfbonus, amcoe1_reels3, version4, ROT0, "Amcoe", "Version 4 (Version 4.3R CGA)", GAME_NOT_WORKING)
6178	6178	GAME( 2006, version4v, version4, sfbonus, amcoe1_reels3, version4v, ROT0, "Amcoe", "Version 4 (Version 4.3R Dual)", GAME_NOT_WORKING)
6179	6179	GAME( 2006, version4d2, version4, sfbonus, amcoe1_reels3, version4d2, ROT0, "Amcoe", "Version 4 (Version 4.3E CGA)", GAME_NOT_WORKING)

src/mame/drivers/bfm_sc2.c
r15704	r15705
1461	1461	AM_RANGE(0x2C00, 0x2C00) AM_WRITE(unlock_w) /* custom chip unlock */
1462	1462	AM_RANGE(0x2D00, 0x2D01) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
1463	1463	AM_RANGE(0x2E00, 0x2E00) AM_WRITE(bankswitch_w) /* write bank (rom page select for 0x6000 - 0x7fff ) */
1464		//AM_RANGE(0x2F00, 0x2F00) AM_WRITE(vfd2_data_w) /* vfd2 data (not usually connected!)*/
	1464	//AM_RANGE(0x2F00, 0x2F00) AM_WRITE(vfd2_data_w) /* vfd2 data (not usually connected!)*/
1465	1465
1466	1466	AM_RANGE(0x3FFE, 0x3FFE) AM_READ(direct_input_r )
1467	1467	AM_RANGE(0x3FFF, 0x3FFF) AM_READ(coin_input_r)

src/mame/drivers/pong.c
r15704	r15705
397	397
398	398	/* net */
399	399	TTL_74107(ic_f3b, clk, 256H, 256HQ, high)
400		TTL_7400_NAND(ic_g3b, ic_f3b.QQ, 256H)
	400	TTL_7400_NAND(ic_g3b, ic_f3b.QQ, 256H)
401	401	TTL_7427_NOR(ic_g2b, ic_g3b.Q, vblank, 4V)
402	402	NET_ALIAS(net, ic_g2b.Q)
403	403
r15704	r15705
423	423
424	424	NETLIST_INCLUDE(pong_schematics)
425	425	/* the signal above is delayed on pong due to counter at gate delays.
426		* This is approximated by the following circuit ...
427		*/
	426	* This is approximated by the following circuit ...
	427	*/
428	428	NET_REMOVE_DEV(ic_h5b)
429	429	NETDEV_DELAY_RISE(ic_g5b_D, clk, ic_g5b.Q)
430	430	TTL_7400_NAND(ic_h5b, ic_h5c.Q, ic_g5b_D.Q)
r15704	r15705
441	441	pong_state(const machine_config &mconfig, device_type type, const char *tag)
442	442	: driver_device(mconfig, type, tag),
443	443	m_maincpu(*this, "maincpu"),
444		m_dac(this, "dac"), / just to have a sound device */
	444	m_dac(this, "dac"), / just to have a sound device */
445	445	m_srst(*this, "maincpu", "SRST"),
446	446	m_sw1a(*this, "maincpu", "sw1a.POS"),
447	447	m_sw1b(*this, "maincpu", "sw1b.POS"),

src/mame/drivers/mpu3.c
r15704	r15705
628	628	if ( data & 0x08 ) m_vfd->reset();
629	629
630	630	m_alpha_data_line = ((data & 0x20) >> 5);
631
	631
632	632	if (m_alpha_clock != ((data & 0x10) >>4))
633	633	{
634	634	if (!m_alpha_clock)//falling edge

src/mame/drivers/aces1.c
r15704	r15705
45	45	{
46	46	return 0x00;
47	47	}
48
	48
49	49	DECLARE_READ8_MEMBER( aces1_unk_port00_r )
50	50	{
51	51	return 0x00;
r15704	r15705
111	111
112	112	DECLARE_WRITE8_MEMBER(ppi8255_ic25_intf_write_a)
113	113	{
114		// printf("extender lamps %02x\n", data);
	114	// printf("extender lamps %02x\n", data);
115	115	}
116	116
117	117	DECLARE_WRITE8_MEMBER(ppi8255_ic25_intf_write_b)
118	118	{
119		// printf("meters, extender select %02x\n", data);
	119	// printf("meters, extender select %02x\n", data);
120	120	}
121	121
122	122	DECLARE_WRITE8_MEMBER(ppi8255_ic25_intf_write_c)
123	123	{
124		// printf("reels, extender strobe %02x\n", data);
	124	// printf("reels, extender strobe %02x\n", data);
125	125	}
126
	126
127	127	DECLARE_READ8_MEMBER( ppi8255_ic37_intf_read_a )
128	128	{
129	129	return 0xff;
r15704	r15705
154	154	static TIMER_CALLBACK( m_aces1_irq_timer_callback )
155	155	{
156	156	aces1_state *state = machine.driver_data<aces1_state>();
157		// printf("irq\n");
	157	// printf("irq\n");
158	158	device_set_input_line(state->m_maincpu, INPUT_LINE_IRQ0, HOLD_LINE);
159	159	state->aces1_reset_irq_timer();
160	160	}
r15704	r15705
162	162	static TIMER_CALLBACK( m_aces1_nmi_timer_callback )
163	163	{
164	164	aces1_state *state = machine.driver_data<aces1_state>();
165		// printf("nmi\n");
	165	// printf("nmi\n");
166	166	device_set_input_line(state->m_maincpu, INPUT_LINE_NMI, PULSE_LINE);
167	167	state->aces1_reset_nmi_timer();
168	168	}
r15704	r15705
315	315	MCFG_I8255A_ADD( "ppi8255_ic24", ppi8255_ic24_intf )
316	316	MCFG_I8255A_ADD( "ppi8255_ic25", ppi8255_ic25_intf )
317	317	MCFG_I8255A_ADD( "ppi8255_ic37", ppi8255_ic37_intf )
318
	318
319	319	MCFG_MACHINE_START( aces1 )
320	320	MCFG_MACHINE_RESET( aces1 )
321	321	MCFG_DEFAULT_LAYOUT(layout_aces1)
r15704	r15705
403	403
404	404	/*
405	405	ROM_START( ac1taklva ) // set 2, just a merged rom of the above, probably for another emulator
406		ROM_REGION( 0x8000, "maincpu", 0 )
407		ROM_LOAD( "430tl.bin", 0x0000, 0x8000, CRC(2fabb08f) SHA1(b737930e428f9258ab22394229c2b5039edf8f97) )
	406	ROM_REGION( 0x8000, "maincpu", 0 )
	407	ROM_LOAD( "430tl.bin", 0x0000, 0x8000, CRC(2fabb08f) SHA1(b737930e428f9258ab22394229c2b5039edf8f97) )
408	408	ROM_END
409	409
410	410	ROM_START( ac1cshtw ) // Cash Towers, same ROM as above, original machine apparently plays the same, reskinned machine?
411		ROM_REGION( 0x8000, "maincpu", 0 )
412		ROM_LOAD( "ctp1.bin", 0x0000, 0x8000, CRC(2fabb08f) SHA1(b737930e428f9258ab22394229c2b5039edf8f97) )
	411	ROM_REGION( 0x8000, "maincpu", 0 )
	412	ROM_LOAD( "ctp1.bin", 0x0000, 0x8000, CRC(2fabb08f) SHA1(b737930e428f9258ab22394229c2b5039edf8f97) )
413	413	ROM_END
414	414	*/
415	415
r15704	r15705
731	731	GAME( 199?, ac1primt ,0 ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Primetime (Ace) (ACESYS1) (set 1)",GAME_IS_SKELETON_MECHANICAL )
732	732	GAME( 199?, ac1primta ,ac1primt ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Primetime (Ace) (ACESYS1) (set 2)",GAME_IS_SKELETON_MECHANICAL ) // same but different rom size?
733	733	GAME( 199?, ac1taklv ,0 ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Take It Or Leave It (Ace) (ACESYS1) (set 1)",GAME_IS_SKELETON_MECHANICAL )
734		//GAME( 199?, ac1taklva ,ac1taklv ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Take It Or Leave It (Ace) (ACESYS1) (set 2)",GAME_IS_SKELETON_MECHANICAL ) // just a merged rom of the above, probably for another emulator
735		//GAME( 199?, ac1cshtw ,0 ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Cash Towers (Ace) (ACESYS1)",GAME_IS_SKELETON_MECHANICAL ) // same ROM as above, original machine apparently plays the same, reskinned machine?
	734	//GAME( 199?, ac1taklva ,ac1taklv ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Take It Or Leave It (Ace) (ACESYS1) (set 2)",GAME_IS_SKELETON_MECHANICAL ) // just a merged rom of the above, probably for another emulator
	735	//GAME( 199?, ac1cshtw ,0 ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Cash Towers (Ace) (ACESYS1)",GAME_IS_SKELETON_MECHANICAL ) // same ROM as above, original machine apparently plays the same, reskinned machine?
736	736	GAME( 199?, ac1bbclb ,0 ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Big Break Club (Ace) (ACESYS1) (set 1)",GAME_IS_SKELETON_MECHANICAL )
737	737	GAME( 199?, ac1bbclba ,ac1bbclb ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Big Break Club (Ace) (ACESYS1) (set 2)",GAME_IS_SKELETON_MECHANICAL )
738	738	GAME( 199?, ac1clbsv ,0 ,aces1 ,aces1 ,aces1 ,ROT0 ,"Ace", "Club Sovereign (Ace) (ACESYS1)",GAME_IS_SKELETON_MECHANICAL )

src/mame/drivers/mpu5.c
r15704	r15705
1057	1057	ROM_LOAD16_BYTE( "bbtr02.p2", 0x000001, 0x080000, CRC(1fc52d87) SHA1(12147409de0420323c998c58eec3c3c3d326063e) )
1058	1058	ROM_LOAD16_BYTE( "bbtr02.p3", 0x100000, 0x080000, CRC(6c2e9086) SHA1(856ed523b09356dd25249ad93d2433c7565fac7c) ) // == bbro10.p3
1059	1059	ROM_LOAD16_BYTE( "bbtr02.p4", 0x100001, 0x080000, CRC(a0f9ff38) SHA1(e9f38c546e6a194e9c72ab5089bdf9b9c6e0c5e8) ) // == bbro10.p4
1060
	1060
1061	1061	ROM_REGION( 0x100000, "altrevs", 0 ) /* Alternate revision Prg ROMs, to be sorted into clones */
1062	1062	ROM_LOAD16_BYTE( "bbtr02ad.p1", 0x000000, 0x080000, CRC(27a37ec6) SHA1(5122603bc3c9ce4cd2627bc5229dd8becefcaadf) )
1063	1063	ROM_LOAD16_BYTE( "bbtr02b.p1", 0x000000, 0x080000, CRC(6d173df4) SHA1(8fe471472b2fb01ec4d2ce7ea2984328a43d59fb) )
r15704	r15705
1442	1442	ROM_LOAD16_BYTE( "carn04.p2", 0x000001, 0x080000, CRC(99aa52e2) SHA1(3b41d928b519001497e1dae17bde5fdc71f971a7) )
1443	1443	ROM_LOAD16_BYTE( "carn04.p3", 0x100000, 0x080000, CRC(b4e632d4) SHA1(4bc3d04aa1884d50c5052b9e8b0069a243d3875b) ) // == 03
1444	1444	ROM_LOAD16_BYTE( "carn04.p4", 0x100001, 0x080000, CRC(691b53e5) SHA1(580f9ea8cc2ca5cb80da8aecd7d7a6b3ce5e158c) ) // == 03
1445
	1445
1446	1446	ROM_REGION( 0x100000, "altrevs", 0 ) /* Alternate revision Prg ROMs, to be sorted into clones */
1447	1447	ROM_LOAD16_BYTE( "carn04ad.p1", 0x000000, 0x080000, CRC(aa4a14e5) SHA1(250941c658dce7077a0b5a65be464ff6307aabdf) )
1448	1448	ROM_LOAD16_BYTE( "carn04b.p1", 0x000000, 0x080000, CRC(c9ced662) SHA1(2a0da3e37ad6d6d9c2401182c368256102c23800) )
r15704	r15705
1665	1665	ROM_LOAD16_BYTE( "cotr02.p2", 0x000001, 0x080000, CRC(69cdb5b3) SHA1(399f8c6049de30aded5766514a40cedea043df3a) )
1666	1666	ROM_LOAD16_BYTE( "cotr02.p3", 0x100000, 0x080000, CRC(2fc0ed76) SHA1(6548767bc1c0d6135de3a60a0f6ce48098f7d137) ) // == 06
1667	1667	ROM_LOAD16_BYTE( "cotr02.p4", 0x100001, 0x080000, CRC(fb5c5c16) SHA1(7c6346bb93933bd4b5a0cf73ba4eeb74d2b47812) ) // == 06
1668
	1668
1669	1669	ROM_REGION( 0x100000, "altrevs", 0 ) /* Alternate revision Prg ROMs, to be sorted into clones */
1670	1670	ROM_LOAD16_BYTE( "cotr02d.p1", 0x000000, 0x080000, CRC(0a08db68) SHA1(dc31265d659acb53e1ce2b823501387c7d629ffe) )
1671	1671	ROM_LOAD16_BYTE( "cotr02dy.p1", 0x000000, 0x080000, CRC(abcf7e6f) SHA1(cab844c757dd4ed4bed44fe371a3ffa9b54a42b3) )
r15704	r15705
1896	1896	ROM_LOAD16_BYTE( "drct07.p2", 0x000001, 0x080000, CRC(4ce428df) SHA1(1144bc21269af10e7094b1bd2271fc6ee63a8d25) )
1897	1897	ROM_LOAD16_BYTE( "drct07.p3", 0x100000, 0x080000, CRC(5054ec32) SHA1(2f4134456f502583ce93af4ccc55eb89dbfe48ca) ) // == 06
1898	1898	ROM_LOAD16_BYTE( "drct07.p4", 0x100001, 0x080000, CRC(0483d31f) SHA1(81a299f05cfd6d1446d44509da86c3a70fb00ba0) ) // == 06
1899
	1899
1900	1900	ROM_REGION( 0x100000, "altrevs", 0 ) /* Alternate revision Prg ROMs, to be sorted into clones */
1901	1901	ROM_LOAD16_BYTE( "drct07d.p1", 0x000000, 0x080000, CRC(c467ca89) SHA1(06f13448860ca7360dd48e29fc780554bc42ab8b) )
1902	1902	ROM_LOAD16_BYTE( "drct07dz.p1", 0x000000, 0x080000, CRC(907d9e63) SHA1(a1a8f74e79043cecb42cfd28c14cef98d54b4785) )
r15704	r15705
2434	2434	ROM_LOAD16_BYTE( "g1tr02.p2", 0x000001, 0x080000, CRC(7d3118e9) SHA1(a4ccf46d15125c67e6e17b117bc3a880b46b47e7) )
2435	2435	ROM_LOAD16_BYTE( "g1tr02.p3", 0x100000, 0x080000, CRC(befbf489) SHA1(d198c27bafaddfd9c2c522be84b2a7aae52f712a) ) // == 03
2436	2436	ROM_LOAD16_BYTE( "g1tr02.p4", 0x100001, 0x080000, CRC(50e63933) SHA1(501caf831c11d603079807f3fd0570f0991a5f9c) ) // == 03
2437
	2437
2438	2438	ROM_REGION( 0x100000, "altrevs", 0 ) /* Alternate revision Prg ROMs, to be sorted into clones */
2439	2439	ROM_LOAD16_BYTE( "g1tr02dy.p1", 0x000000, 0x080000, CRC(e9c967ea) SHA1(1a2806e5b95e11aa5a80d7e434ebb40eba057aac) )
2440	2440	ROM_LOAD16_BYTE( "g1tr02k.p1", 0x000000, 0x080000, CRC(d892e461) SHA1(72185d4c8e6670a0ec87f3807d4c465b1ea2ea89) )
r15704	r15705
2447	2447	ROM_LOAD16_BYTE( "gotr01.p2", 0x000001, 0x080000, CRC(000f6663) SHA1(f79f52c5d4af6cf576db9c529b868b34cd203026) )
2448	2448	ROM_LOAD16_BYTE( "gotr01.p3", 0x100000, 0x080000, CRC(befbf489) SHA1(d198c27bafaddfd9c2c522be84b2a7aae52f712a) ) // == 03
2449	2449	ROM_LOAD16_BYTE( "gotr01.p4", 0x100001, 0x080000, CRC(50e63933) SHA1(501caf831c11d603079807f3fd0570f0991a5f9c) ) // == 03
2450
2451		ROM_REGION( 0x100000, "altrevs", 0 ) /* Alternate revision Prg ROMs, to be sorted into clones */
	2450
	2451	ROM_REGION( 0x100000, "altrevs", 0 ) /* Alternate revision Prg ROMs, to be sorted into clones */
2452	2452	ROM_LOAD16_BYTE( "gotr01d.p1", 0x000000, 0x080000, CRC(171a5db8) SHA1(4b10705efafcc456c2a26f9a80bbb9f7c67cea9b) )
2453	2453	ROM_LOAD16_BYTE( "gotr01dy.p1", 0x000000, 0x080000, CRC(715102e2) SHA1(af067bb2a80793391cb350e15f7f364f9ed3ee22) )
2454	2454	ROM_LOAD16_BYTE( "gotr01k.p1", 0x000000, 0x080000, CRC(c57930cb) SHA1(3d24482169dc207b5d8ff9819fff8661df19bc79) )
r15704	r15705
5971	5971
5972	5972	ROM_REGION( 0x100000, "altrevs", 0 ) /* Alternate revision Prg ROMs, to be sorted into clones */
5973	5973	ROM_LOAD16_BYTE( "ms__sjs2.2_1", 0x000000, 0x080000, CRC(312c2501) SHA1(95e16c5013ea8e246c04b828af6f6b3ca82d18e0) )
5974		// ROM_LOAD16_BYTE( "ms__sjs2.2_2", 0x000000, 0x080000, CRC(31187bc2) SHA1(d352d67feddbf670dbbaff224b19701ce1231fd9) )
5975		// ROM_LOAD16_BYTE( "ms__sjs2.2_3", 0x000000, 0x080000, CRC(8c44ed26) SHA1(35b29f7e4d9c1c73dd9d4891decc131443fc21c5) )
5976		// ROM_LOAD16_BYTE( "ms__sjs2.2_4", 0x000000, 0x080000, CRC(eb3b0f16) SHA1(4664110800c2f5005ffe8d8c1cf5b588dd994347) )
	5974	// ROM_LOAD16_BYTE( "ms__sjs2.2_2", 0x000000, 0x080000, CRC(31187bc2) SHA1(d352d67feddbf670dbbaff224b19701ce1231fd9) )
	5975	// ROM_LOAD16_BYTE( "ms__sjs2.2_3", 0x000000, 0x080000, CRC(8c44ed26) SHA1(35b29f7e4d9c1c73dd9d4891decc131443fc21c5) )
	5976	// ROM_LOAD16_BYTE( "ms__sjs2.2_4", 0x000000, 0x080000, CRC(eb3b0f16) SHA1(4664110800c2f5005ffe8d8c1cf5b588dd994347) )
5977	5977	ROM_END
5978	5978
5979	5979

src/mame/drivers/tasman.c
r15704	r15705
11	11
12	12	Thanks to palindrome for PCB scans.
13	13
14		0x38606
	14	0x38606
15	15	*/
16	16
17	17	#include "emu.h"
r15704	r15705
141	141	/*
142	142	static READ32_HANDLER( rng_r )
143	143	{
144		return space->machine().rand();
	144	return space->machine().rand();
145	145	}
146	146	*/
147	147
r15704	r15705
196	196
197	197	AM_RANGE(0x500380, 0x500383) AM_READ_LEGACY(test_r)
198	198	AM_RANGE(0x500000, 0x5007ff) AM_RAM
199		// AM_RANGE(0x500400, 0x500403) AM_NOP //dual port?
200		// AM_RANGE(0x500420, 0x500423) AM_NOP //dual port?
201		// AM_RANGE(0x500500, 0x500503) AM_NOP // reads sound ROM in here, polled from m68k?
	199	// AM_RANGE(0x500400, 0x500403) AM_NOP //dual port?
	200	// AM_RANGE(0x500420, 0x500423) AM_NOP //dual port?
	201	// AM_RANGE(0x500500, 0x500503) AM_NOP // reads sound ROM in here, polled from m68k?
202	202	AM_RANGE(0x580000, 0x580007) AM_READ_LEGACY(test_r)
203	203
204	204	AM_RANGE(0x600000, 0x60000f) AM_READ_LEGACY(test_r)

src/mame/drivers/esd16.c
r15704	r15705
180	180
181	181	AM_RANGE(0x180008, 0x180009) AM_WRITE(esd16_tilemap0_color_jumppop_w) // todo
182	182
183		ESD16_PALETTE_AREA( 0x140000 )
	183	ESD16_PALETTE_AREA( 0x140000 )
184	184	ESD16_SPRITE_AREA( 0x160000 )
185	185	ESD16_IO_AREA_DSW( 0x180000 )
186	186	ESD16_VRAM_AREA( 0x300000 )

src/mame/drivers/globalfr.c
r15704	r15705
42	42	WRITE16_MEMBER(globalfr_state::vfd_w)
43	43	{
44	44
45		// if(!(data & 0x20)) need to find reset
	45	// if(!(data & 0x20)) need to find reset
46	46	{
47	47	int clock = (data & 0x40) != 0;
48	48	int datline = (data & 0x80);
r15704	r15705
55	55	}
56	56	m_alpha_clock = clock;
57	57	}
58		// else
59		// {
60		// m_vfd->reset();
61		// }
	58	// else
	59	// {
	60	// m_vfd->reset();
	61	// }
62	62	}
63	63
64	64	static ADDRESS_MAP_START( globalfr_map, AS_PROGRAM, 16, globalfr_state )

src/mame/drivers/proconn.c
r15704	r15705
263	263	proconn_state *state = device->machine().driver_data<proconn_state>();
264	264
265	265	//Don't like the look of this, should be a clock somewhere
266		// if (offset == 0)
267		// state->m_vfd->write_char( data );
	266	// if (offset == 0)
	267	// state->m_vfd->write_char( data );
268	268
269	269	for (int i=0; i<8;i++)
270	270	{
r15704	r15705
317	317	MCFG_CPU_PROGRAM_MAP(proconn_map)
318	318	MCFG_CPU_IO_MAP(proconn_portmap)
319	319	MCFG_ROC10937_ADD("vfd",0,LEFT_TO_RIGHT)
320
	320
321	321	MCFG_Z80PIO_ADD( "z80pio_1", 4000000, pio_interface_1 ) /* ?? Mhz */
322	322	MCFG_Z80PIO_ADD( "z80pio_2", 4000000, pio_interface_2 ) /* ?? Mhz */
323	323	MCFG_Z80PIO_ADD( "z80pio_3", 4000000, pio_interface_3 ) /* ?? Mhz */

src/mame/drivers/bfmsys85.c
r15704	r15705
75	75	: driver_device(mconfig, type, tag),
76	76	m_vfd(*this, "vfd")
77	77	{ }
78
	78
79	79	optional_device<roc10937_t> m_vfd;
80	80	int m_mmtr_latch;
81	81	int m_triac_latch;
r15704	r15705
260	260
261	261	WRITE8_MEMBER(bfmsys85_state::vfd_w)
262	262	{
263
	263
264	264	if (data & VFD_RESET)//inverted?
265	265	{
266	266	if (m_alpha_clock != (data & VFD_CLOCK1))

src/mame/drivers/dfruit.c
r15704	r15705
2	2
3	3	Fruit Dream (c) 1993 Nippon Data Kiki / Star Fish
4	4
5		driver by Angelo Salese
	5	driver by Angelo Salese
6	6
7	7	Uses a TC0091LVC, a variant of the one used on Taito L HW
8	8
9	9	TODO:
10		- title screen (PCG uploads at 0x1b400?)
11		- inputs are grossly mapped;
12		- lamps?
13		- service mode?
14		- nvram?
	10	- title screen (PCG uploads at 0x1b400?)
	11	- inputs are grossly mapped;
	12	- lamps?
	13	- service mode?
	14	- nvram?
15	15
16	16	***************************************************************************/
17	17

src/mame/drivers/jpmmps.c
r15704	r15705
56	56	static ADDRESS_MAP_START( jpmmps_io_map, AS_IO, 8, jpmmps_state )
57	57	ADDRESS_MAP_GLOBAL_MASK(0xff)
58	58	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE("tms9902_ic5", tms9902_device, cruread, cruwrite)
59
60		// AM_RANGE(0x0020, 0x0020) // power fail
61		// AM_RANGE(0x0021, 0x0021) // wd timeout
62		// AM_RANGE(0x0022, 0x0022) // invalid access
63		// AM_RANGE(0x0023, 0x0023) // clear down
64
65		// AM_RANGE(0x0026, 0x0026) // uart4 int
66		// AM_RANGE(0x0027, 0x0027) // uart2 int
67	59
	60	// AM_RANGE(0x0020, 0x0020) // power fail
	61	// AM_RANGE(0x0021, 0x0021) // wd timeout
	62	// AM_RANGE(0x0022, 0x0022) // invalid access
	63	// AM_RANGE(0x0023, 0x0023) // clear down
	64
	65	// AM_RANGE(0x0026, 0x0026) // uart4 int
	66	// AM_RANGE(0x0027, 0x0027) // uart2 int
	67
68	68	AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE("tms9902_ic10", tms9902_device, cruread, cruwrite)
69	69
70		// AM_RANGE(0x0060, 0x0060) // watchdog
71		// AM_RANGE(0x0061, 0x0061) // ram en
72		// AM_RANGE(0x0062, 0x0062) // alarm
73		// AM_RANGE(0x0063, 0x0063) // nmi en
74		// AM_RANGE(0x0064, 0x0064) // reel en
75		// AM_RANGE(0x0065, 0x0065) // io en
76		// AM_RANGE(0x0066, 0x0066) // bb
77		// AM_RANGE(0x0067, 0x0067) // diagnostic led
	70	// AM_RANGE(0x0060, 0x0060) // watchdog
	71	// AM_RANGE(0x0061, 0x0061) // ram en
	72	// AM_RANGE(0x0062, 0x0062) // alarm
	73	// AM_RANGE(0x0063, 0x0063) // nmi en
	74	// AM_RANGE(0x0064, 0x0064) // reel en
	75	// AM_RANGE(0x0065, 0x0065) // io en
	76	// AM_RANGE(0x0066, 0x0066) // bb
	77	// AM_RANGE(0x0067, 0x0067) // diagnostic led
78	78	ADDRESS_MAP_END
79	79
80	80

src/mame/drivers/jpms80.c
r15704	r15705
45	45
46	46	static ADDRESS_MAP_START( jpms80_io_map, AS_IO, 8, jpms80_state )
47	47	ADDRESS_MAP_GLOBAL_MASK(0x1ff)
48		// AM_RANGE(0x0000, 0x000f) // I/O & Optic (in) / Reels (out)
49		// AM_RANGE(0x0050, 0x0050) // INT1 enable (lv3)
50		// AM_RANGE(0x0051, 0x0051) // INT2 enable (lv4)
51		// AM_RANGE(0x0052, 0x0052) // Watchdog
52		// AM_RANGE(0x0053, 0x0053) // I/O Enable
53		// AM_RANGE(0x0140, 0x015f) // AY
	48	// AM_RANGE(0x0000, 0x000f) // I/O & Optic (in) / Reels (out)
	49	// AM_RANGE(0x0050, 0x0050) // INT1 enable (lv3)
	50	// AM_RANGE(0x0051, 0x0051) // INT2 enable (lv4)
	51	// AM_RANGE(0x0052, 0x0052) // Watchdog
	52	// AM_RANGE(0x0053, 0x0053) // I/O Enable
	53	// AM_RANGE(0x0140, 0x015f) // AY
54	54	AM_RANGE(0x01e0, 0x01ff) AM_DEVREADWRITE("tms9902duart", tms9902_device, cruread, cruwrite)
55		// Lamps, Meters etc. can move around
	55	// Lamps, Meters etc. can move around
56	56	ADDRESS_MAP_END
57	57
58	58

src/osd/sdl/sdl.mak
r15704	r15705
37	37
38	38	# NO_X11 = 1
39	39
40		# uncomment next line to disable XInput support for e.g. multiple lightguns
	40	# uncomment next line to disable XInput support for e.g. multiple lightguns
41	41	# using Wiimote driver (see http://spritesmods.com/?art=wiimote-mamegun for more info)
42	42	# enabling NO_X11 also implies no XInput support, of course.
43	43

src/osd/sdl/input.c
r15704	r15705
1045	1045	{
1046	1046	int index;
1047	1047	XExtensionVersion *version;
1048
	1048
1049	1049	lightgun_enabled = machine.options().lightgun();
1050		devmap_init(machine, &lightgun_map, SDLOPTION_LIGHTGUNINDEX, 8, "Lightgun mapping");
1051
	1050	devmap_init(machine, &lightgun_map, SDLOPTION_LIGHTGUNINDEX, 8, "Lightgun mapping");
	1051
1052	1052	XDisplay = XOpenDisplay(NULL);
1053	1053
1054	1054	if (XDisplay == NULL) {

src/emu/cpu/v30mz/v30mz.c
r15704	r15705
449	449
450	450	OP( 0x68, i_push_d16 ) { UINT32 tmp; FETCHWORD(tmp); PUSH(tmp); CLK(1); }
451	451	OP( 0x69, i_imul_d16 ) { UINT32 tmp; DEF_r16w; FETCHWORD(tmp); dst = (INT32)((INT16)src)*(INT32)((INT16)tmp); cpustate->CarryVal = cpustate->OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1); RegWord(ModRM)=(UINT16)dst; if (ModRM >= 0xc0) CLK(3) else CLK(4) }
452		OP( 0x6a, i_push_d8 ) { UINT32 tmp = (UINT16)((INT16)((INT8)FETCH)); PUSH(tmp); CLK(1); }
	452	OP( 0x6a, i_push_d8 ) { UINT32 tmp = (UINT16)((INT16)((INT8)FETCH)); PUSH(tmp); CLK(1); }
453	453	OP( 0x6b, i_imul_d8 ) { UINT32 src2; DEF_r16w; src2= (UINT16)((INT16)((INT8)FETCH)); dst = (INT32)((INT16)src)*(INT32)((INT16)src2); cpustate->CarryVal = cpustate->OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1); RegWord(ModRM)=(UINT16)dst; if (ModRM >= 0xc0) CLK(3) else CLK(4) }
454	454	OP( 0x6c, i_insb ) { PutMemB(ES,cpustate->regs.w[IY],read_port(cpustate->regs.w[DW])); cpustate->regs.w[IY]+= -2 * cpustate->DF + 1; CLK(6); }
455	455	OP( 0x6d, i_insw ) { PutMemB(ES,cpustate->regs.w[IY],read_port(cpustate->regs.w[DW])); PutMemB(ES,(cpustate->regs.w[IY]+1)&0xffff,read_port((cpustate->regs.w[DW]+1)&0xffff)); cpustate->regs.w[IY]+= -4 * cpustate->DF + 2; CLK(6); }

src/emu/cpu/tlcs900/tlcs900.c
r15704	r15705
1946	1946	cpustate->cycles += inst->cycles;
1947	1947	}
1948	1948
1949		// tmp95c063_handle_ad( cpustate ); // TODO
	1949	// tmp95c063_handle_ad( cpustate ); // TODO
1950	1950
1951	1951	tmp95c063_handle_timers( cpustate );
1952	1952
1953		// tmp95c063_check_hdma( cpustate ); // TODO
	1953	// tmp95c063_check_hdma( cpustate ); // TODO
1954	1954
1955	1955	cpustate->icount -= cpustate->cycles;
1956	1956	} while ( cpustate->icount > 0 );
r15704	r15705
2123	2123
2124	2124
2125	2125	DEFINE_LEGACY_CPU_DEVICE(TLCS900H, tlcs900h);
2126		DEFINE_LEGACY_CPU_DEVICE(TMP95C063, tmp95c063);
		No newline at end of file
	2126	DEFINE_LEGACY_CPU_DEVICE(TMP95C063, tmp95c063);

src/emu/cpu/powerpc/ppccom.c
r15704	r15705
455	455
456	456
457	457	/*-------------------------------------------------
458		ppccom_dcstore_callback - call the dcstore
459		callback if installed
	458	ppccom_dcstore_callback - call the dcstore
	459	callback if installed
460	460	-------------------------------------------------*/
461	461
462	462	void ppccom_dcstore_callback(powerpc_state *ppc)
r15704	r15705
1672	1672	}
1673	1673
1674	1674	/*-------------------------------------------------
1675		ppc_set_dcstore_callback - installs a callback
1676		for detecting datacache stores with dcbst
	1675	ppc_set_dcstore_callback - installs a callback
	1676	for detecting datacache stores with dcbst
1677	1677	-------------------------------------------------*/
1678	1678
1679	1679	void ppc_set_dcstore_callback(device_t *device, ppc_dcstore_handler handler)

src/emu/cpu/tms32051/32051ops.c
r15704	r15705
38	38	INLINE INT32 ADD(tms32051_state *cpustate, UINT32 a, UINT32 b)
39	39	{
40	40	UINT32 res = a + b;
41
	41
42	42	// C is set if carry was generated
43	43	cpustate->st1.c = (a > res) ? 1 : 0;
44	44

src/emu/cpu/f8/f8.c
r15704	r15705
1160	1160	static void f8_amd(f8_Regs *cpustate)
1161	1161	{
1162	1162
1163		/*SKR from F8 Guide To programming description of AMD
	1163	/*SKR from F8 Guide To programming description of AMD
1164	1164
1165	1165	binary add the addend to the binary sum of the augend and $66
1166	1166	NOTE the binary addition of the augend to $66 is done before AMD is called
r15704	r15705
1196	1196	tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f);
1197	1197	if(c==1&&ic==0)
1198	1198	tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f);
1199
	1199
1200	1200	cpustate->a = tmp;
1201	1201	}
1202	1202
r15704	r15705
1412	1412	tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f);
1413	1413	if(c==1&&ic==0)
1414	1414	tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f);
1415
	1415
1416	1416	cpustate->a = tmp;
1417	1417	}
1418	1418
r15704	r15705
1445	1445	tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f);
1446	1446	if(c==1&&ic==0)
1447	1447	tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f);
1448
	1448
1449	1449	cpustate->a = tmp;
1450	1450	}
1451	1451
r15704	r15705
1478	1478	tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f);
1479	1479	if(c==1&&ic==0)
1480	1480	tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f);
1481
	1481
1482	1482	cpustate->a = tmp;
1483	1483	cpustate->is = (cpustate->is & 0x38) \| ((cpustate->is + 1) & 0x07);
1484	1484	}
r15704	r15705
1512	1512	tmp=((tmp+0xa0)&0xf0)+(tmp&0x0f);
1513	1513	if(c==1&&ic==0)
1514	1514	tmp=(tmp&0xf0)+((tmp+0x0a)&0x0f);
1515
	1515
1516	1516	cpustate->a = tmp;
1517	1517	cpustate->is = (cpustate->is & 0x38) \| ((cpustate->is - 1) & 0x07);
1518	1518	}

src/emu/cpu/tms32025/tms32025.c
r15704	r15705
554	554
555	555
556	556	/****************************************************************************
557		* Emulate the Instructions
	557	* Emulate the Instructions
558	558	****************************************************************************/
559	559
560	560	/* The following functions are here to fill the void for the */
r15704	r15705
1997	1997
1998	1998	if (cpustate->init_load_addr == 2) { /* Repeat next instruction */
1999	1999	/****************************************************\
2000		***** These instructions are not repeatable ******
2001		ADLK, ANDK, LALK, LRLK, ORK, SBLK, XORK
2002		ADDK, ADRK, LACK, LARK, LDPK, MPYK, RPTK
2003		SBRK, SPM, SUBK, ZAC, IDLE, RPT, TRAP
2004		BACC, CALA, RET
2005		B, BANZ, BBNZ, BBZ, BC, BGEZ, BGZ, BIOZ
2006		BNC, BNV, BNZ, BV, BZ, CALL, BLEZ, BLZ
2007		\****************************************************/
	2000	***** These instructions are not repeatable ******
	2001	ADLK, ANDK, LALK, LRLK, ORK, SBLK, XORK
	2002	ADDK, ADRK, LACK, LARK, LDPK, MPYK, RPTK
	2003	SBRK, SPM, SUBK, ZAC, IDLE, RPT, TRAP
	2004	BACC, CALA, RET
	2005	B, BANZ, BBNZ, BBZ, BC, BGEZ, BGZ, BIOZ
	2006	BNC, BNV, BNZ, BV, BZ, CALL, BLEZ, BLZ
	2007	\****************************************************/
2008	2008	cpustate->PREVPC = cpustate->PC;
2009	2009
2010	2010	debugger_instruction_hook(device, cpustate->PC);

src/emu/cpu/m6800/m6800.c
r15704	r15705
2183	2183	DEFINE_LEGACY_CPU_DEVICE(HD63701, hd63701);
2184	2184	DEFINE_LEGACY_CPU_DEVICE(NSC8105, nsc8105);
2185	2185
2186		// DP-40 package: HD6303RP, HD63A03RP, HD63B03RP,
2187		// FP-54 package: HD6303RF, HD63A03RF, HD63B03RF,
2188		// CG-40 package: HD6303RCG, HD63A03RCG, HD63B03RCG,
	2186	// DP-40 package: HD6303RP, HD63A03RP, HD63B03RP,
	2187	// FP-54 package: HD6303RF, HD63A03RF, HD63B03RF,
	2188	// CG-40 package: HD6303RCG, HD63A03RCG, HD63B03RCG,
2189	2189	DEFINE_LEGACY_CPU_DEVICE(HD6303R, hd6303r);
2190	2190
2191	2191	// DP-64S package: HD6303YP, HD63A03YP, HD63B03YP, HD63C03YP

src/emu/machine/roc10937.c
r15704	r15705
159	159	save_item(NAME(m_count));
160	160	save_item(NAME(m_duty));
161	161	save_item(NAME(m_disp));
162
163	162
	163
164	164	device_reset();
165	165	}
166	166
r15704	r15705
183	183	///////////////////////////////////////////////////////////////////////////
184	184	UINT32 rocvfd_t::set_display(UINT32 segin)
185	185	{
186
187
	186
	187
188	188	return BITSWAP32(segin, 31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,11,9,15,13,12,8,10,14,7,6,5,4,3,2,1,0);
189	189
190	190	}
r15704	r15705
208	208	}
209	209	else
210	210	{
211		m_outputs[i] = set_display(m_chars[i]);
	211	m_outputs[i] = set_display(m_chars[i]);
212	212	}
213	213	output_set_indexed_value("vfd", (m_port_val*16) + i, m_outputs[i]);
214	214	}
r15704	r15705
272	272	}
273	273	else
274	274	{ // Display data
275		// data &= 0x3F;
	275	// data &= 0x3F;
276	276
277	277	switch ( data )
278	278	{

src/emu/machine/tc009xlvc.c
r15704	r15705
1	1	/***************************************************************************
2	2
3		TC009xLVC device emulation
	3	TC009xLVC device emulation
4	4
5		Written by Angelo Salese, based off Taito L implementation
	5	Written by Angelo Salese, based off Taito L implementation
6	6
7		TODO:
8		- non-video stuff needs to be ported there as well
	7	TODO:
	8	- non-video stuff needs to be ported there as well
9	9
10	10	***************************************************************************/
11	11
r15704	r15705
188	188	int code = vdp->m_vram0[2 * tile_index]
189	189	\| ((attr & 0x03) << 8)
190	190	\| ((vdp->m_vregs[(attr & 0xc) >> 2]) << 10);
191		// \| (state->m_horshoes_gfxbank << 12);
	191	// \| (state->m_horshoes_gfxbank << 12);
192	192
193	193	SET_TILE_INFO_DEVICE(
194	194	0,
r15704	r15705
204	204	int code = vdp->m_vram1[2 * tile_index]
205	205	\| ((attr & 0x03) << 8)
206	206	\| ((vdp->m_vregs[(attr & 0xc) >> 2]) << 10);
207		// \| (state->m_horshoes_gfxbank << 12);
	207	// \| (state->m_horshoes_gfxbank << 12);
208	208
209	209	SET_TILE_INFO_DEVICE(
210	210	0,

src/emu/machine/roc10937.h
r15704	r15705
22	22
23	23	#define MCFG_ROC10937_REVERSE(_reversed) \
24	24	roc10937_t::static_set_zero(*device, _reversed); \
25
	25
26	26	#define MCFG_ROC10937_REMOVE(_tag) \
27	27	MCFG_DEVICE_REMOVE(_tag)
28	28
r15704	r15705
50	50
51	51	#define MCFG_MSC1937_REVERSE(_reversed) \
52	52	roc10937_t::static_set_zero(*device, _reversed); \
53
	53
54	54	#define MCFG_MSC1937_REMOVE(_tag) \
55	55	MCFG_DEVICE_REMOVE(_tag)
56
57
	56
	57
58	58	class rocvfd_t : public device_t {
59	59	public:
60	60	typedef delegate<void (bool state)> line_cb;

src/emu/machine/tc009xlvc.h
r15704	r15705
1	1	/***************************************************************************
2	2
3		TC0091LVC device
	3	TC0091LVC device
4	4
5	5	***************************************************************************/
6	6
r15704	r15705
43	43	UINT8 *m_palette_ram;
44	44	UINT8 *m_vregs;
45	45	UINT8 *m_bitmap_ram;
46
	46
47	47	UINT8 *m_pcg_ram;
48	48	UINT8 *m_pcg1_ram;
49	49	UINT8 *m_pcg2_ram;

src/emu/machine/netlist.c
r15704	r15705
6	6
7	7	****************************************************************************
8	8
9		Couriersud reserves the right to license the code under a less restrictive
10		license going forward.
	9	Couriersud reserves the right to license the code under a less restrictive
	10	license going forward.
11	11
12		Copyright Nicola Salmoria and the MAME team
13		All rights reserved.
	12	Copyright Nicola Salmoria and the MAME team
	13	All rights reserved.
14	14
15		Redistribution and use of this code or any derivative works are permitted
16		provided that the following conditions are met:
	15	Redistribution and use of this code or any derivative works are permitted
	16	provided that the following conditions are met:
17	17
18		* Redistributions may not be sold, nor may they be used in a commercial
19		product or activity.
	18	* Redistributions may not be sold, nor may they be used in a commercial
	19	product or activity.
20	20
21		* Redistributions that are modified from the original source must include the
22		complete source code, including the source code for all components used by a
23		binary built from the modified sources. However, as a special exception, the
24		source code distributed need not include anything that is normally distributed
25		(in either source or binary form) with the major components (compiler, kernel,
26		and so on) of the operating system on which the executable runs, unless that
27		component itself accompanies the executable.
	21	* Redistributions that are modified from the original source must include the
	22	complete source code, including the source code for all components used by a
	23	binary built from the modified sources. However, as a special exception, the
	24	source code distributed need not include anything that is normally distributed
	25	(in either source or binary form) with the major components (compiler, kernel,
	26	and so on) of the operating system on which the executable runs, unless that
	27	component itself accompanies the executable.
28	28
29		* Redistributions must reproduce the above copyright notice, this list of
30		conditions and the following disclaimer in the documentation and/or other
31		materials provided with the distribution.
	29	* Redistributions must reproduce the above copyright notice, this list of
	30	conditions and the following disclaimer in the documentation and/or other
	31	materials provided with the distribution.
32	32
33		THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34		AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35		IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36		ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37		LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38		CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39		SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
40		INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
41		CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42		ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43		POSSIBILITY OF SUCH DAMAGE.
	33	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	34	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	35	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	36	ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
	37	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	38	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	39	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	40	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	41	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	42	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	43	POSSIBILITY OF SUCH DAMAGE.
44	44
45	45
46	46	****************************************************************************/
r15704	r15705
73	73	#if KEEP_STATISTICS
74	74	#define add_to_stat(v,x) do { atomic_add32((v), (x)); } while (0)
75	75	#define inc_stat(v) add_to_stat(v, 1)
76		#define begin_timing(v) do { (v) -= get_profile_ticks(); } while (0)
	76	#define begin_timing(v) do { (v) -= get_profile_ticks(); } while (0)
77	77	#define end_timing(v) do { (v) += get_profile_ticks(); } while (0)
78	78	#else
79	79	#define add_to_stat(v,x) do { } while (0)
r15704	r15705
778	778	do
779	779	{
780	780	// debugging
781		//m_ppc = m_pc; // copy PC to previous PC
	781	//m_ppc = m_pc; // copy PC to previous PC
782	782	//if (check_debugger)
783		// debugger_instruction_hook(this, 0); //m_pc);
	783	// debugger_instruction_hook(this, 0); //m_pc);
784	784	if (--m_ss == 0)
785	785	{
786	786	m_ss = ssdiv2;

src/emu/machine/netlist.h
r15704	r15705
6	6
7	7	****************************************************************************
8	8
9		Couriersud reserves the right to license the code under a less restrictive
10		license going forward.
	9	Couriersud reserves the right to license the code under a less restrictive
	10	license going forward.
11	11
12		Copyright Nicola Salmoria and the MAME team
13		All rights reserved.
	12	Copyright Nicola Salmoria and the MAME team
	13	All rights reserved.
14	14
15		Redistribution and use of this code or any derivative works are permitted
16		provided that the following conditions are met:
	15	Redistribution and use of this code or any derivative works are permitted
	16	provided that the following conditions are met:
17	17
18		* Redistributions may not be sold, nor may they be used in a commercial
19		product or activity.
	18	* Redistributions may not be sold, nor may they be used in a commercial
	19	product or activity.
20	20
21		* Redistributions that are modified from the original source must include the
22		complete source code, including the source code for all components used by a
23		binary built from the modified sources. However, as a special exception, the
24		source code distributed need not include anything that is normally distributed
25		(in either source or binary form) with the major components (compiler, kernel,
26		and so on) of the operating system on which the executable runs, unless that
27		component itself accompanies the executable.
	21	* Redistributions that are modified from the original source must include the
	22	complete source code, including the source code for all components used by a
	23	binary built from the modified sources. However, as a special exception, the
	24	source code distributed need not include anything that is normally distributed
	25	(in either source or binary form) with the major components (compiler, kernel,
	26	and so on) of the operating system on which the executable runs, unless that
	27	component itself accompanies the executable.
28	28
29		* Redistributions must reproduce the above copyright notice, this list of
30		conditions and the following disclaimer in the documentation and/or other
31		materials provided with the distribution.
	29	* Redistributions must reproduce the above copyright notice, this list of
	30	conditions and the following disclaimer in the documentation and/or other
	31	materials provided with the distribution.
32	32
33		THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34		AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35		IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36		ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37		LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38		CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39		SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
40		INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
41		CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42		ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43		POSSIBILITY OF SUCH DAMAGE.
	33	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	34	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	35	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	36	ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
	37	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	38	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	39	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	40	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	41	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	42	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	43	POSSIBILITY OF SUCH DAMAGE.
44	44
45	45
46	46	****************************************************************************/
r15704	r15705
93	93
94	94	#define NETLIST_END }
95	95
96		#define NETLIST_INCLUDE(_name) \
	96	#define NETLIST_INCLUDE(_name) \
97	97	NETLIST_NAME(_name)(netlist); \
98	98
99	99
100		#define NETLIST_MEMREGION(_name) \
	100	#define NETLIST_MEMREGION(_name) \
101	101	netlist.parse((char *)downcast<netlist_t &>(netlist.netlist()).machine().root_device().memregion(_name)->base()); \
102	102
103	103	#if defined(__GNUC__) && (__GNUC__ >= 3)
r15704	r15705
154	154	// MAME specific
155	155
156	156	#define MCFG_NETLIST_ADD(_tag, _clock, _setup, _subcycles) \
157		MCFG_DEVICE_ADD(_tag, NETLIST, _clock) \
	157	MCFG_DEVICE_ADD(_tag, NETLIST, _clock) \
158	158	MCFG_NETLIST_SUBCYCLES(_subcycles) \
159		MCFG_NETLIST_SETUP(_setup) \
	159	MCFG_NETLIST_SETUP(_setup) \
160	160
161	161	#define MCFG_NETLIST_REPLACE(_tag, _clock, _setup, _subcycles) \
162		MCFG_DEVICE_REPLACE(_tag, NETLIST, _clock) \
	162	MCFG_DEVICE_REPLACE(_tag, NETLIST, _clock) \
163	163	MCFG_NETLIST_SUBCYCLES(_subcycles) \
164		MCFG_NETLIST_SETUP(_setup) \
	164	MCFG_NETLIST_SETUP(_setup) \
165	165
166		#define MCFG_NETLIST_SUBCYCLES(_subcycles) \
	166	#define MCFG_NETLIST_SUBCYCLES(_subcycles) \
167	167	netlist_mame_device::static_set_subcycles(*device, _subcycles); \
168	168
169		#define MCFG_NETLIST_SETUP(_setup) \
	169	#define MCFG_NETLIST_SETUP(_setup) \
170	170	netlist_mame_device::static_set_constructor(*device, NETLIST_NAME(_setup)); \
171	171
172	172
r15704	r15705
267	267	public:
268	268	net_output_t();
269	269
270		ATTR_HOT inline void clear() { set_Q(nst_LOW); }
271		ATTR_HOT inline void set() { set_Q(nst_HIGH); }
	270	ATTR_HOT inline void clear() { set_Q(nst_LOW); }
	271	ATTR_HOT inline void set() { set_Q(nst_HIGH); }
272	272	ATTR_HOT inline void setTo(const net_sig_t val) { set_Q(val); }
273	273	ATTR_HOT inline void setTo(const net_sig_t val, const UINT8 delay_ns) { set_Q(val,delay_ns); }
274	274	ATTR_HOT inline void setToNoCheck(const net_sig_t val)
r15704	r15705
285	285
286	286	ATTR_COLD void initial(const net_sig_t val) { m_Q = val; m_new_Q = val; }
287	287
288		ATTR_HOT inline const net_sig_t Q() const { return m_Q; }
	288	ATTR_HOT inline const net_sig_t Q() const { return m_Q; }
289	289
290	290	inline net_sig_t *Q_ptr() { return &m_Q; }
291		inline net_sig_t *new_Q_ptr() { return &m_new_Q; }
	291	inline net_sig_t *new_Q_ptr() { return &m_new_Q; }
292	292
293	293	ATTR_COLD void register_con(net_dev_t *dev);
294	294
r15704	r15705
407	407	inline void initial(const double val) { m_param = val; }
408	408	inline void initial(const int val) { m_param = val; }
409	409
410		inline double Value() { return m_param; }
411		inline int ValueInt() { return m_param; }
	410	inline double Value() { return m_param; }
	411	inline int ValueInt() { return m_param; }
412	412
413	413	ATTR_HOT inline const net_dev_t *ttl_dev() { return m_ttldev; }
414	414	void set_ttl_dev(net_dev_t *dev) { m_ttldev = dev; }

src/emu/machine/net_lib.c
r15704	r15705
6	6
7	7	****************************************************************************
8	8
9		Couriersud reserves the right to license the code under a less restrictive
10		license going forward.
	9	Couriersud reserves the right to license the code under a less restrictive
	10	license going forward.
11	11
12		Copyright Nicola Salmoria and the MAME team
13		All rights reserved.
	12	Copyright Nicola Salmoria and the MAME team
	13	All rights reserved.
14	14
15		Redistribution and use of this code or any derivative works are permitted
16		provided that the following conditions are met:
	15	Redistribution and use of this code or any derivative works are permitted
	16	provided that the following conditions are met:
17	17
18		* Redistributions may not be sold, nor may they be used in a commercial
19		product or activity.
	18	* Redistributions may not be sold, nor may they be used in a commercial
	19	product or activity.
20	20
21		* Redistributions that are modified from the original source must include the
22		complete source code, including the source code for all components used by a
23		binary built from the modified sources. However, as a special exception, the
24		source code distributed need not include anything that is normally distributed
25		(in either source or binary form) with the major components (compiler, kernel,
26		and so on) of the operating system on which the executable runs, unless that
27		component itself accompanies the executable.
	21	* Redistributions that are modified from the original source must include the
	22	complete source code, including the source code for all components used by a
	23	binary built from the modified sources. However, as a special exception, the
	24	source code distributed need not include anything that is normally distributed
	25	(in either source or binary form) with the major components (compiler, kernel,
	26	and so on) of the operating system on which the executable runs, unless that
	27	component itself accompanies the executable.
28	28
29		* Redistributions must reproduce the above copyright notice, this list of
30		conditions and the following disclaimer in the documentation and/or other
31		materials provided with the distribution.
	29	* Redistributions must reproduce the above copyright notice, this list of
	30	conditions and the following disclaimer in the documentation and/or other
	31	materials provided with the distribution.
32	32
33		THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34		AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35		IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36		ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37		LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38		CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39		SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
40		INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
41		CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42		ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43		POSSIBILITY OF SUCH DAMAGE.
	33	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	34	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	35	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	36	ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
	37	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	38	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	39	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	40	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	41	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	42	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	43	POSSIBILITY OF SUCH DAMAGE.
44	44
45	45
46	46	****************************************************************************/
r15704	r15705
705	705	{
706	706	ENTRY(netdev_const, NETDEV_CONST)
707	707	ENTRY(netdev_input, NETDEV_INPUT)
708		ENTRY(netdev_callback, NETDEV_CALLBACK)
709		ENTRY(nicMultiSwitch, NETDEV_SWITCH2)
	708	ENTRY(netdev_callback, NETDEV_CALLBACK)
	709	ENTRY(nicMultiSwitch, NETDEV_SWITCH2)
710	710	ENTRY(netdev_delay_lh, NETDEV_DELAY_RAISE)
711	711	ENTRY(nicRSFF, NETDEV_RSFF)
712	712	ENTRY(nic7400, TTL_7400_NAND)

src/emu/machine/net_lib.h
r15704	r15705
6	6
7	7	****************************************************************************
8	8
9		Couriersud reserves the right to license the code under a less restrictive
10		license going forward.
	9	Couriersud reserves the right to license the code under a less restrictive
	10	license going forward.
11	11
12		Copyright Nicola Salmoria and the MAME team
13		All rights reserved.
	12	Copyright Nicola Salmoria and the MAME team
	13	All rights reserved.
14	14
15		Redistribution and use of this code or any derivative works are permitted
16		provided that the following conditions are met:
	15	Redistribution and use of this code or any derivative works are permitted
	16	provided that the following conditions are met:
17	17
18		* Redistributions may not be sold, nor may they be used in a commercial
19		product or activity.
	18	* Redistributions may not be sold, nor may they be used in a commercial
	19	product or activity.
20	20
21		* Redistributions that are modified from the original source must include the
22		complete source code, including the source code for all components used by a
23		binary built from the modified sources. However, as a special exception, the
24		source code distributed need not include anything that is normally distributed
25		(in either source or binary form) with the major components (compiler, kernel,
26		and so on) of the operating system on which the executable runs, unless that
27		component itself accompanies the executable.
	21	* Redistributions that are modified from the original source must include the
	22	complete source code, including the source code for all components used by a
	23	binary built from the modified sources. However, as a special exception, the
	24	source code distributed need not include anything that is normally distributed
	25	(in either source or binary form) with the major components (compiler, kernel,
	26	and so on) of the operating system on which the executable runs, unless that
	27	component itself accompanies the executable.
28	28
29		* Redistributions must reproduce the above copyright notice, this list of
30		conditions and the following disclaimer in the documentation and/or other
31		materials provided with the distribution.
	29	* Redistributions must reproduce the above copyright notice, this list of
	30	conditions and the following disclaimer in the documentation and/or other
	31	materials provided with the distribution.
32	32
33		THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34		AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35		IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36		ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37		LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38		CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39		SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
40		INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
41		CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42		ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43		POSSIBILITY OF SUCH DAMAGE.
	33	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	34	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	35	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	36	ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
	37	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	38	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	39	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	40	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	41	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	42	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	43	POSSIBILITY OF SUCH DAMAGE.
44	44
45	45
46	46	****************************************************************************/
r15704	r15705
92	92
93	93	#define TTL_7402_NOR(_name, _I1, _I2) \
94	94	NET_REGISTER_DEV(nic7402, _name) \
95		NET_CONNECT(_name, I1, _I1) \
	95	NET_CONNECT(_name, I1, _I1) \
96	96	NET_CONNECT(_name, I2, _I2) \
97	97
98	98	#define TTL_7404_INVERT(_name, _I1) \
r15704	r15705
145	145
146	146	#define TTL_7486_XOR(_name, _I1, _I2) \
147	147	NET_REGISTER_DEV(nic7486, _name) \
148		NET_CONNECT(_name, I1, _I1) \
	148	NET_CONNECT(_name, I1, _I1) \
149	149	NET_CONNECT(_name, I2, _I2) \
150	150
151	151	#define TTL_7448(_name, _A0, _A1, _A2, _A3, _LTQ, _BIQ, _RBIQ) \
r15704	r15705
347	347	{
348	348	public:
349	349	nic74107(netlist_setup_t parent, const char name)
350		: nic74107A(parent, name) {}
	350	: nic74107A(parent, name) {}
351	351
352	352	};
353	353

src/emu/machine/am9517a.c
r15704	r15705
143	143
144	144
145	145	//-------------------------------------------------
146		// set_hreq
	146	// set_hreq
147	147	//-------------------------------------------------
148	148
149	149	inline void am9517a_device::set_hreq(int state)

src/version.c
r15704	r15705
38	38	***************************************************************************/
39	39
40	40	extern const char build_version[];
41		const char build_version[] = "0.146u3 ("__DATE__")";
	41	const char build_version[] = "0.146u4 ("__DATE__")";

src/mess/machine/pc.c
r15704	r15705
84	84	* 'reconfiguration code' (inverted number of failing memory bank) to
85	85	* the register.
86	86
87		* bit 1-0 'reconfiguration code'
88		* bit 2 enable read access
89		* bit 3 enable write access
	87	* bit 1-0 'reconfiguration code'
	88	* bit 2 enable read access
	89	* bit 3 enable write access
90	90	*/
91	91
92	92	READ8_MEMBER(pc_state::ec1841_memboard_r)
r15704	r15705
940	940	DBG_LOG(1,"mc1502_k_s_c",("= %02X (%d) %s\n", key, mc1502_keyb.pulsing,
941	941	(key \|\| mc1502_keyb.pulsing) ? " will IRQ" : ""));
942	942
943		/*
944		If a key is pressed and we're not pulsing yet, start pulsing the IRQ1;
945		keep pulsing while any key is pressed, and pulse one time after all keys
946		are released.
947		*/
	943	/*
	944	If a key is pressed and we're not pulsing yet, start pulsing the IRQ1;
	945	keep pulsing while any key is pressed, and pulse one time after all keys
	946	are released.
	947	*/
948	948	if (key) {
949	949	if (mc1502_keyb.pulsing < 2) {
950	950	mc1502_keyb.pulsing += 2;
r15704	r15705
996	996	int data = 0xff;
997	997	double tap_val = (device->machine().device<cassette_image_device>(CASSETTE_TAG)->input());
998	998
999		// 0x80 -- serial RxD
1000		// 0x40 -- CASS IN, also loops back T2OUT (gated by CASWR)
	999	// 0x80 -- serial RxD
	1000	// 0x40 -- CASS IN, also loops back T2OUT (gated by CASWR)
1001	1001	data = ( data & ~0x40 ) \| ( tap_val < 0 ? 0x40 : 0x00 ) \| ( (BIT(st->m_ppi_portb, 7) && timer2_output) ? 0x40 : 0x00 );
1002		// 0x20 -- T2OUT
	1002	// 0x20 -- T2OUT
1003	1003	data = ( data & ~0x20 ) \| ( timer2_output ? 0x20 : 0x00 );
1004		// 0x10 -- SNDOUT
	1004	// 0x10 -- SNDOUT
1005	1005	data = ( data & ~0x10 ) \| ( (BIT(st->m_ppi_portb, 1) && timer2_output) ? 0x10 : 0x00 );
1006	1006
1007		DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
	1007	DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
1008	1008	data, tap_val, timer2_output, machine.describe_context()));
1009	1009	return data;
1010	1010	}
r15704	r15705
1480	1480	st->m_dma8237 = NULL;
1481	1481	st->m_pit8253 = machine.device("pit8253");
1482	1482
1483		/*
	1483	/*
1484	1484	Keyboard polling circuit holds IRQ1 high until a key is
1485	1485	pressed, then it starts a timer that pulses IRQ1 low each
1486	1486	40ms (check) for 20ms (check) until all keys are released.
1487	1487	Last pulse causes BIOS to write a 'break' scancode into port 60h.
1488		*/
	1488	*/
1489	1489	pic8259_ir1_w(st->m_pic8259, 1);
1490	1490	memset(&mc1502_keyb, 0, sizeof(mc1502_keyb));
1491	1491	mc1502_keyb.keyb_signal_timer = machine.scheduler().timer_alloc(FUNC(mc1502_keyb_signal_callback));

src/mess/machine/llc.c
r15704	r15705
81	81
82	82	// timer 0 irq does digit display, and timer 3 irq does scan of the
83	83	// monitor keyboard. Currently the keyboard is being scanned too fast.
84		// No idea how the CTC is connected, so guessed.
	84	// No idea how the CTC is connected, so guessed.
85	85	Z80CTC_INTERFACE( llc1_ctc_intf )
86	86	{
87	87	0,

src/mess/video/uv201.c
r15704	r15705
167	167	void uv201_device::device_reset()
168	168	{
169	169	m_out_ext_int_func(CLEAR_LINE);
170
	170
171	171	m_out_hblank_func(1);
172	172	m_timer_hblank_off->adjust(attotime::from_ticks( HBLANK_END, m_clock ));
173	173	}

src/mess/drivers/x1.c
r15704	r15705
13	13	- Implement APSS tape commands;
14	14	- Sort out / redump the BIOS gfx roms;
15	15	- X1Turbo: Implement SIO.
16		- Implement true 400 lines mode (i.e. Chatnoir no Mahjong v2.1, Casablanca)
	16	- Implement true 400 lines mode (i.e. Chatnoir no Mahjong v2.1, Casablanca)
17	17	- Implement SASI HDD interface;
18	18	- clean-ups!
19	19	- There are various unclear video things, these are:

src/mess/drivers/digel804.c
r15704	r15705
265	265	*/
266	266	// HACK to dump display contents to stderr
267	267	// FIXME : not sure what to do here with the new device! 201207
268		// fprintf(stderr,"%s\n",ROC10937_get_string(0));
	268	// fprintf(stderr,"%s\n",ROC10937_get_string(0));
269	269	#ifdef PORT43_R_VERBOSE
270	270	logerror("Digel804: returning %02X for port 43 status read\n", port43_rtn);
271	271	#endif

src/mess/drivers/vt100.c
r15704	r15705
131	131
132	132	WRITE8_MEMBER( vt100_state::vt100_keyboard_w )
133	133	{
134		beep_set_frequency( m_speaker, 786 ); // 7.945us per serial clock = ~125865.324hz, / 160 clocks per char = ~ 786 hz
	134	beep_set_frequency( m_speaker, 786 ); // 7.945us per serial clock = ~125865.324hz, / 160 clocks per char = ~ 786 hz
135	135	output_set_value("online_led",BIT(data, 5) ? 0 : 1);
136	136	output_set_value("local_led", BIT(data, 5));
137	137	output_set_value("locked_led",BIT(data, 4) ? 0 : 1);

src/mess/drivers/alesis.c
r15704	r15705
34	34
35	35	static ADDRESS_MAP_START(sr16_mem, AS_PROGRAM, 8, alesis_state)
36	36	ADDRESS_MAP_UNMAP_HIGH
37		// AM_RANGE(0x0006, 0x0007 ) // LCD interface?
	37	// AM_RANGE(0x0006, 0x0007 ) // LCD interface?
38	38	AM_RANGE(0x0000, 0xffff) AM_ROM
39	39	ADDRESS_MAP_END
40	40

src/mess/drivers/pc8801.c
r15704	r15705
29	29	- Balance of Power: uses the SIO port for mouse polling;
30	30	- Battle Entry: moans with a JP msg then dies if you try to press either numpad 1 or 2 (asks if the user wants to use the sound board (yes 1 / no 2)
31	31	- Bishoujo Baseball Gakuen: checks ym2608 after intro screen;
32		- The Black Onyx: writes a katakana msg: "rino kata ha koko ni orimasen" then doesn't show up anything.
	32	- The Black Onyx: writes a katakana msg: "rino kata ha koko ni orimasen" then doesn't show up anything.
33	33	- Blue Moon Story: moans with a kanji msg;.
34	34	- Bubblegum Crisis: crashes due of a spurious irq (works if you soft reset the emulation when it triggers the halt opcode);
35	35	- Can Can Bunny: bitmap artifacts on intro, could be either ALU or floppy issues;
36		- Carrot: gfxs are messed up
37		- Combat: mono gfx mode enabled, but I don't see any noticeable quirk?
	36	- Carrot: gfxs are messed up
	37	- Combat: mono gfx mode enabled, but I don't see any noticeable quirk?
38	38	- Fire Hawk: tries to r/w the opn ports (probably crashed due to floppy?)
39	39	- Grobda: palette is ugly (parent pc8801 only);
40	40	- Hang-On: typical busted attributes for a N-BASIC game
r15704	r15705
58	58	- Kuronekosou Souzoku Satsujin Jiken ("Illegal function call in 105")
59	59	- Jark (needs PC-8801MC)
60	60	- MakaiMura (attempts to r/w the sio ports, but it's clearly crashed)
61		- Mr. Pro Yakyuu
	61	- Mr. Pro Yakyuu
62	62	- Space Harrier
63	63	- The Return of Ishtar
64	64	- Tobira wo Akete (random crashes in parent pc8801 only)

src/mess/drivers/vk100.c
r15704	r15705
164	164	UINT8 m_VG_MODE;
165	165	UINT8 m_LASTVRAM;
166	166	UINT8 m_vgGO;
167
	167
168	168	DECLARE_WRITE8_MEMBER(vgLD_X);
169	169	DECLARE_WRITE8_MEMBER(vgLD_Y);
170	170	DECLARE_WRITE8_MEMBER(vgERR);
r15704	r15705
189	189	static TIMER_CALLBACK( execute_vg )
190	190	{
191	191	/* figure out ram address based on tech manual page 5-24:
192		* real address to 16-bit chunk a13 a12 \| a11 a10 a9 a8 \| a7 a6 a5 a4 \| a3 a2 a1 a0
193		* X+Y input Y8 Y7 \| Y6 Y5 Y4 Y3 \| Y2 Y1 X9' X8'\| X7' X6' X5' X4'
194		* X3' and X2' choose a 4-bit block, X1 and X0 choose a bit within that.
195		* Figure out the ram address in address space "vram" based on this:
196		* vram is 0x8000 long (0x4000 16-bit blocks in sequence)
197		* so:
198		* vram: a14 a13 a12 \| a11 a10 a9 a8 \| a7 a6 a5 a4 \| a3 a2 a1 a0
199		* vg: Y8 Y7 Y6 \| Y5 Y4 Y3 Y2 \| Y1 X9' X8' X7'\| X6' X5' X4'(x3') x2' x1 x0
200		* X3' is handled by the nybblenum statement, as is X2'
201		* X1 and X0 are handled by the pattern rom directly:
202		* x0 -> a0, x1 -> a1
203		* this handles bits like:
204		* x1 x0
205		* 0 0 -> bit 0
206		* 0 1 -> bit 1
207		* 1 0 -> bit 2
208		* 1 1 -> bit 3
209		*
210		*/
	192	* real address to 16-bit chunk a13 a12 \| a11 a10 a9 a8 \| a7 a6 a5 a4 \| a3 a2 a1 a0
	193	* X+Y input Y8 Y7 \| Y6 Y5 Y4 Y3 \| Y2 Y1 X9' X8'\| X7' X6' X5' X4'
	194	* X3' and X2' choose a 4-bit block, X1 and X0 choose a bit within that.
	195	* Figure out the ram address in address space "vram" based on this:
	196	* vram is 0x8000 long (0x4000 16-bit blocks in sequence)
	197	* so:
	198	* vram: a14 a13 a12 \| a11 a10 a9 a8 \| a7 a6 a5 a4 \| a3 a2 a1 a0
	199	* vg: Y8 Y7 Y6 \| Y5 Y4 Y3 Y2 \| Y1 X9' X8' X7'\| X6' X5' X4'(x3') x2' x1 x0
	200	* X3' is handled by the nybblenum statement, as is X2'
	201	* X1 and X0 are handled by the pattern rom directly:
	202	* x0 -> a0, x1 -> a1
	203	* this handles bits like:
	204	* x1 x0
	205	* 0 0 -> bit 0
	206	* 0 1 -> bit 1
	207	* 1 0 -> bit 2
	208	* 1 1 -> bit 3
	209	*
	210	*/
211	211	vk100_state *state = machine.driver_data<vk100_state>();
212	212	// XFinal is (X'&0x3FC)\|(X&0x3)
213	213	UINT16 XFinal = state->m_trans[(state->m_vgX&0x3FC)>>2]<<2\|(state->m_vgX&0x3); // appears correct
r15704	r15705
317	317	/*
318	318	void drawVector(UINT16 px, UINT16 py, UINT16 x, UINT16 y, int pattern)
319	319	{
320		UINT8 *gfx = machine.root_device().memregion("vram")->base();
	320	UINT8 *gfx = machine.root_device().memregion("vram")->base();
321	321	}*/
322	322
323	323	/* ports 0x40 and 0x41: load low and high bytes of vector gen X register */
r15704	r15705
349	349	#endif
350	350	}
351	351
352		/* port 0x45: "SOPS" screen options
	352	/* port 0x45: "SOPS" screen options
353	353	* Blink --Background color-- Blink Serial Select Reverse
354	354	* Enable Green Red Blue Control BG/FG
355	355	* d7 d6 d5 d4 d3 d2 d1 d0
356		* apparently, 00 = rs232/eia, 01 = 20ma, 10 = hardcopy, 11 = test/loopback
	356	* apparently, 00 = rs232/eia, 01 = 20ma, 10 = hardcopy, 11 = test/loopback
357	357	*/
358	358	WRITE8_MEMBER(vk100_state::vgSOPS)
359	359	{
r15704	r15705
369	369	{
370	370	m_vgPAT = data;
371	371	#ifdef PAT_DEBUG
372		for (int i = 7; i >= 0; i--)
	372	for (int i = 7; i >= 0; i--)
373	373	{
374	374	printf("%s", (data&(1<<i))?"X":".");
375	375	}
r15704	r15705
380	380	#endif
381	381	}
382	382
383		/* port 0x47: "PMUL" load vg Pattern Multiply Register
	383	/* port 0x47: "PMUL" load vg Pattern Multiply Register
384	384	The pattern multiply register loads a counter which counts reads from
385	385	the pattern register and increments on each one. if it overflows from
386	386	1111 to 0000 the pattern register is shifted right one bit and the
r15704	r15705
446	446	m_vgPAT_Mask = 0x100;
447	447	m_VG_MODE = 0;
448	448	m_vgGO = 1;
449		machine().scheduler().timer_set(attotime::zero, FUNC(execute_vg));
	449	machine().scheduler().timer_set(attotime::zero, FUNC(execute_vg));
450	450	}
451	451
452	452	/* port 0x65: "EX DOT" execute a dot (start the state machine) */
r15704	r15705
460	460	m_vgPAT_Mask = 0x100; // load vgPAT_Mask
461	461	m_VG_MODE = 1;
462	462	m_vgGO = 1;
463		machine().scheduler().timer_set(attotime::zero, FUNC(execute_vg));
	463	machine().scheduler().timer_set(attotime::zero, FUNC(execute_vg));
464	464	}
465	465
466	466	/* port 0x66: "EX VEC" execute a pattern (8 fixed direction) vector (start the state machine) */
r15704	r15705
473	473	m_vgPAT_Mask = 0x100; // load vgPAT_Mask
474	474	m_VG_MODE = 2;
475	475	m_vgGO = 1;
476		machine().scheduler().timer_set(attotime::zero, FUNC(execute_vg));
	476	machine().scheduler().timer_set(attotime::zero, FUNC(execute_vg));
477	477	}
478	478
479	479	/* port 0x67: "EX ER" execute an "erase"? */
r15704	r15705
487	487	m_vgPAT_Mask = 0x100; // load vgPAT_Mask
488	488	m_VG_MODE = 3;
489	489	m_vgGO = 1;
490		machine().scheduler().timer_set(attotime::zero, FUNC(execute_vg));
	490	machine().scheduler().timer_set(attotime::zero, FUNC(execute_vg));
491	491	}
492	492
493	493	/* port 0x68: "KBDW" d7 is beeper, d6 is keyclick, d5-d0 are keyboard LEDS */
r15704	r15705
521	521	/* port 0x40-0x47: "SYSTAT A"; various status bits, poorly documented in the tech manual
522	522	* /GO BIT3 BIT2 BIT1 BIT0 Dip ? ?
523	523	* Switch
524		* d7 d6 d5 d4 d3 d2 d1 d0
	524	* d7 d6 d5 d4 d3 d2 d1 d0
525	525	* bit3, 2, 1, 0 are the last 4 bits read by the vector generator from VRAM
526	526	* this appears to be the only way the vram can be READ by the cpu
527	527	d2 is where the dipswitch values are read from, based on the offset
528	528	d1 is unknown
529	529	d0 is unknown
530
	530
531	531	31D reads and checks d7 in a loop
532	532	205 reads, xors with 0x55 (from reg D), ANDS result with 0x78 and branches if it is not zero (checking for bit pattern 1010?)
533	533	299 reads, rotates result right 3 times and ANDs the result with 0x0F
r15704	r15705
544	544
545	545	/* port 0x48: "SYSTAT B"; NOT documented in the tech manual at all.
546	546	* ? ? ? ? ? ? ? ?
547		* d7 d6 d5 d4 d3 d2 d1 d0
	547	* d7 d6 d5 d4 d3 d2 d1 d0
548	548	* according to the code at 606, the systat b register has something
549	549	* to do with the uart 8251, though what exactly is unclear.
550	550	* the ACTS (inverse of DCTS) signal lives in one of these bits (see 5-62)
r15704	r15705
601	601	AM_RANGE (0x68, 0x68) AM_WRITE(KBDW) //KBDW (probably AM_MIRROR(0x03))
602	602	AM_RANGE (0x6C, 0x6C) AM_WRITE(BAUD) //LD BAUD (baud rate clock divider setting for i8251 tx and rx clocks) (probably AM_MIRROR(0x03))
603	603	AM_RANGE(0x70, 0x70) AM_DEVWRITE("i8251", i8251_device, data_w) //LD COMD (i8251 data reg)
604		AM_RANGE(0x71, 0x71) AM_DEVWRITE("i8251", i8251_device, control_w) //LD COM (i8251 control reg)
	604	AM_RANGE(0x71, 0x71) AM_DEVWRITE("i8251", i8251_device, control_w) //LD COM (i8251 control reg)
605	605	//AM_RANGE (0x74, 0x74) AM_WRITE(unknown_74)
606	606	//AM_RANGE (0x78, 0x78) AM_WRITE(kbdw) //KBDW ?(mirror?)
607	607	//AM_RANGE (0x7C, 0x7C) AM_WRITE(unknown_7C)
r15704	r15705
840	840
841	841	static MC6845_UPDATE_ROW( vk100_update_row )
842	842	{
843		static const UINT32 colorTable[16] = {
	843	static const UINT32 colorTable[16] = {
844	844	0x000000, 0x0000FF, 0xFF0000, 0xFF00FF, 0x00FF00, 0x00FFFF, 0xFFFF00, 0xFFFFFF,
845	845	0x000000, 0x0000FF, 0xFF0000, 0xFF00FF, 0x00FF00, 0x00FFFF, 0xFFFF00, 0xFFFFFF };
846		static const UINT32 colorTable2[16] = {
	846	static const UINT32 colorTable2[16] = {
847	847	0x000000, 0x0000FF, 0xFF0000, 0xFF00FF, 0x00FF00, 0x00FFFF, 0xFFFF00, 0xFFFFFF,
848		0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000 };
	848	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000 };
849	849	//printf("y=%d, ma=%04x, ra=%02x, x_count=%02x ", y, ma, ra, x_count);
850	850	/* figure out ram address based on tech manual page 5-23:
851		* real address to 16-bit chunk a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
852		* crtc input MA11 MA10 MA9 MA8 MA7 MA6 RA1 RA0 MA5 MA4 MA3 MA2 MA1 MA0
853		*/
	851	* real address to 16-bit chunk a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
	852	* crtc input MA11 MA10 MA9 MA8 MA7 MA6 RA1 RA0 MA5 MA4 MA3 MA2 MA1 MA0
	853	*/
854	854	vk100_state *state = device->machine().driver_data<vk100_state>();
855	855	UINT16 EA = ((ma&0xfc0)<<2)\|((ra&0x3)<<6)\|(ma&0x3F);
856	856	// display the 64 different 12-bit-wide chunks
r15704	r15705
967	967
968	968	ROM_REGION( 0x400, "proms", ROMREGION_ERASEFF )
969	969	/* some sort of "COUNTER ROM" involved with erasing VRAM dram to the background color? (256*4, 82s129)
970		* control bits:
971		* /CE1 ----- ?
972		* /CE2 ----- ?
973		* addr bits: 76543210
974		* \|\|\|\|\|\|\|\-- ?
975		* \|\|\|\|\|\|\--- ?
976		* \|\|\|\|\|\---- ?
977		* \|\|\|\|\----- ?
978		* \|\|\|\------ ?
979		* \|\|\------- ?
980		* \|\-------- ?
981		* \--------- comes from the gated ERASE L/d5 on the vector rom [verified from tracing]
982		* data bits: 3210
983		* \|\|\|\-- ?
984		* \|\|\--- ?
985		* \|\---- ?
986		* \----- ?
987		*/
	970	* control bits:
	971	* /CE1 ----- ?
	972	* /CE2 ----- ?
	973	* addr bits: 76543210
	974	* \|\|\|\|\|\|\|\-- ?
	975	* \|\|\|\|\|\|\--- ?
	976	* \|\|\|\|\|\---- ?
	977	* \|\|\|\|\----- ?
	978	* \|\|\|\------ ?
	979	* \|\|\------- ?
	980	* \|\-------- ?
	981	* \--------- comes from the gated ERASE L/d5 on the vector rom [verified from tracing]
	982	* data bits: 3210
	983	* \|\|\|\-- ?
	984	* \|\|\--- ?
	985	* \|\---- ?
	986	* \----- ?
	987	*/
988	988	ROM_LOAD( "wb8151_573a2.6301.pr3.ic44", 0x0000, 0x0100, CRC(75885a9f) SHA1(c721dad6a69c291dd86dad102ed3a8ddd620ecc4)) // label verified from nigwil's and andy's board
989	989	/* this is the "DIRECTION ROM" == mb6309 (256x8, 82s135)
990		* see figure 5-24 on page 5-39
991		* It tells the direction and enable for counting on the X and Y counters
992		* and also handles the non-math related parts of the bresenham line algorithm
993		* control bits:
994		* /CE1 ----- ?
995		* /CE2 ----- ?
996		* addr bits: 76543210
997		* \|\|\|\|\\\\-- DIR (vgDIR register low 4 bits)
998		* \|\|\|\------ ERROR CARRY (strobed in by STROBE L from the error counter's adder)
999		* \|\|\------- Y0 (the otherwise unused lsb of the Y register, used for bresenham)
1000		* \|\-------- feedback bit from d5 gated by V CLK
1001		* \--------- GND; the second half of the prom is blank (0x00)
1002		* data bits: 76543210
1003		* \|\|\|\|\|\|\|\-- ENA X (enables change on X counter)
1004		* \|\|\|\|\|\|\--- ENA Y (enables change on Y counter)
1005		* \|\|\|\|\|\---- Y DIRECTION (high is count down, low is count up)
1006		* \|\|\|\|\----- X DIRECTION (high is count down, low is count up)
1007		* \|\|\|\------ PIXEL WRT
1008		* \|\|\------- feedback bit to a6
1009		* \|\-------- UNUSED, always 0
1010		* \--------- UNUSED, always 0
1011		*/
	990	* see figure 5-24 on page 5-39
	991	* It tells the direction and enable for counting on the X and Y counters
	992	* and also handles the non-math related parts of the bresenham line algorithm
	993	* control bits:
	994	* /CE1 ----- ?
	995	* /CE2 ----- ?
	996	* addr bits: 76543210
	997	* \|\|\|\|\\\\-- DIR (vgDIR register low 4 bits)
	998	* \|\|\|\------ ERROR CARRY (strobed in by STROBE L from the error counter's adder)
	999	* \|\|\------- Y0 (the otherwise unused lsb of the Y register, used for bresenham)
	1000	* \|\-------- feedback bit from d5 gated by V CLK
	1001	* \--------- GND; the second half of the prom is blank (0x00)
	1002	* data bits: 76543210
	1003	* \|\|\|\|\|\|\|\-- ENA X (enables change on X counter)
	1004	* \|\|\|\|\|\|\--- ENA Y (enables change on Y counter)
	1005	* \|\|\|\|\|\---- Y DIRECTION (high is count down, low is count up)
	1006	* \|\|\|\|\----- X DIRECTION (high is count down, low is count up)
	1007	* \|\|\|\------ PIXEL WRT
	1008	* \|\|\------- feedback bit to a6
	1009	* \|\-------- UNUSED, always 0
	1010	* \--------- UNUSED, always 0
	1011	*/
1012	1012	ROM_LOAD( "wb8141_059b1.tbp18s22.pr5.ic108", 0x0100, 0x0100, CRC(4b63857a) SHA1(3217247d983521f0b0499b5c4ef6b5de9844c465)) // label verified from andy's board
1013	1013	/* this is the "VECTOR ROM" (256*8, 82s135) which runs the vector generator state machine
1014		* the vector rom bits are complex and are unfortunately poorly documented
1015		* in the tech manual. see figure 5-23.
1016		* control bits:
1017		* /CE1 ----- ?
1018		* /CE2 ----- ?
1019		* addr bits: 76543210
1020		* \|\|\|\|\\\\-- To sync counter, which counts 0xC 0x3 0x2 0x1 0x0 0x5 0x4 0xB 0xA 0x9 0x8 0xD in that order
1021		* \|\|\|\------ A0\__Address lsb bits of the execute write, i.e. VG_MODE; these are INVERTED FIRST.
1022		* \|\|\------- A1/
1023		* \|\-------- CARRY_IN (when set, only one /LD ERROR pulse occurs instead of two)
1024		* \--------- ? possibly tied or somehow pulsed by sync rom d7? /LD ERROR only goes active (low) when this is unset
1025		*
1026		* data bits: 76543210
1027		* \|\|\|\|\|\|\|\-- /WRITE aka WRITE L (fig 5-20, page 5-32, writes the post-pattern-converted value back to vram at X,Y)
1028		* \|\|\|\|\|\|\--- ? vector clk
1029		* \|\|\|\|\|\---- ? vector clk
1030		* \|\|\|\|\----- /LD ERROR aka STROBE ERROR L (strobes the adder result value into the vgERR register)
1031		* \|\|\|\------ ? d-load?
1032		* \|\|\------- ERASE L (latched, forces a4 on the sync rom low and also forces a7 on the counter rom; the counter rom may be involved in blanking all of vram) [verified from tracing]
1033		* \|\-------- C0 aka C IN (high during DVM read, low otherwise, likely a carry in to the adder so DVM is converted from 1s to 2s complement)
1034		* \--------- ? done l?
1035		*
1036		* According to the vt125 tech manual (vt100 tech manual rev 3, page 6-85) the 8 signals here are:
1037		* ERASE L - d5
1038		* SHIFT ENA
1039		* C IN - d6
1040		* D LOAD
1041		* WRITE L - d0
1042		* DONE L
1043		* VECTOR CLK
1044		* STROBE ERROR L - d3
1045		*/
	1014	* the vector rom bits are complex and are unfortunately poorly documented
	1015	* in the tech manual. see figure 5-23.
	1016	* control bits:
	1017	* /CE1 ----- ?
	1018	* /CE2 ----- ?
	1019	* addr bits: 76543210
	1020	* \|\|\|\|\\\\-- To sync counter, which counts 0xC 0x3 0x2 0x1 0x0 0x5 0x4 0xB 0xA 0x9 0x8 0xD in that order
	1021	* \|\|\|\------ A0\__Address lsb bits of the execute write, i.e. VG_MODE; these are INVERTED FIRST.
	1022	* \|\|\------- A1/
	1023	* \|\-------- CARRY_IN (when set, only one /LD ERROR pulse occurs instead of two)
	1024	* \--------- ? possibly tied or somehow pulsed by sync rom d7? /LD ERROR only goes active (low) when this is unset
	1025	*
	1026	* data bits: 76543210
	1027	* \|\|\|\|\|\|\|\-- /WRITE aka WRITE L (fig 5-20, page 5-32, writes the post-pattern-converted value back to vram at X,Y)
	1028	* \|\|\|\|\|\|\--- ? vector clk
	1029	* \|\|\|\|\|\---- ? vector clk
	1030	* \|\|\|\|\----- /LD ERROR aka STROBE ERROR L (strobes the adder result value into the vgERR register)
	1031	* \|\|\|\------ ? d-load?
	1032	* \|\|\------- ERASE L (latched, forces a4 on the sync rom low and also forces a7 on the counter rom; the counter rom may be involved in blanking all of vram) [verified from tracing]
	1033	* \|\-------- C0 aka C IN (high during DVM read, low otherwise, likely a carry in to the adder so DVM is converted from 1s to 2s complement)
	1034	* \--------- ? done l?
	1035	*
	1036	* According to the vt125 tech manual (vt100 tech manual rev 3, page 6-85) the 8 signals here are:
	1037	* ERASE L - d5
	1038	* SHIFT ENA
	1039	* C IN - d6
	1040	* D LOAD
	1041	* WRITE L - d0
	1042	* DONE L
	1043	* VECTOR CLK
	1044	* STROBE ERROR L - d3
	1045	*/
1046	1046	ROM_LOAD( "wb8146_058b1.6309.pr1.ic99", 0x0200, 0x0100, CRC(71b01864) SHA1(e552f5b0bc3f443299282b1da7e9dbfec60e12bf)) // label verified from nigwil's and andy's board
1047	1047	/* this is the "SYNC ROM" == mb6331 (32x8, 82s123)
1048		* It generates the ram RAS/CAS and a few other signals, see figure 5-20 on page 5-32
1049		* The exact pins for each signal are not documented.
1050		* control bits:
1051		* /CE1 -- GND(Unused)
1052		* addr bits: 43210
1053		* \|\\\\-- To sync counter, which counts 0xC 0x3 0x2 0x1 0x0 0x5 0x4 0xB 0xA 0x9 0x8 0xD in that order
1054		* \------ comes from the gated ERASE L/d5 from the vector rom, only low during VG_MODE == ER (ERase Screen) [verified from tracing]
1055		* when high: the sync rom matches figure 5-20 (page 5-32) and 5-23 (page 5-38)
1056		* when low: RA/RB is fixed on WOPS in the register file
1057		* LD SHFR does NOT output pulses (effectively blanking the screen)
1058		* WRT/RD is held at /RD so vg to vram do nothing,
1059		* however while the crtc is refreshing the screen it instead is writing zeroes to every location
1060		* data bits: 76543210
1061		* \|\|\|\|\|\|\|\-- WRT/RD (write high when x,y (vg) drives vram, read low when ma (crtc) drives vram)
1062		* \|\|\|\|\|\|\--- /RAS (for vram)
1063		* \|\|\|\|\|\---- STROBE aka STROBE L aka VG STROBE(latches the carry bit from the adder to the direction rom AND causes the data at the X,Y address of vram to be read into the holding register before pattern is applied)
1064		* \|\|\|\|\----- LD SHFR (loads the 12-bit shift register of data to be shifted to screen)
1065		* \|\|\|\------ /CAS (for vram)
1066		* \|\|\------- RA\__selects which slot of the 8x4 register file (du, dvm, dir, or wops) is selected
1067		* \|\-------- RB/
1068		* \--------- VG vector rom "enable"? (mentioned on page 5-31 last paragraph?) (this is off by one cycle though...) [active low, sync addr 011]
1069		* This may actually have to do with gating the DCNT DONE L signal to make the FINISH signal which unsets the /GO register
1070		* The VT125 proms E64/E66 and their respective latches E65 and E83 are roughly
1071		* but not completely equivalent to the sync rom
1072		*/
	1048	* It generates the ram RAS/CAS and a few other signals, see figure 5-20 on page 5-32
	1049	* The exact pins for each signal are not documented.
	1050	* control bits:
	1051	* /CE1 -- GND(Unused)
	1052	* addr bits: 43210
	1053	* \|\\\\-- To sync counter, which counts 0xC 0x3 0x2 0x1 0x0 0x5 0x4 0xB 0xA 0x9 0x8 0xD in that order
	1054	* \------ comes from the gated ERASE L/d5 from the vector rom, only low during VG_MODE == ER (ERase Screen) [verified from tracing]
	1055	* when high: the sync rom matches figure 5-20 (page 5-32) and 5-23 (page 5-38)
	1056	* when low: RA/RB is fixed on WOPS in the register file
	1057	* LD SHFR does NOT output pulses (effectively blanking the screen)
	1058	* WRT/RD is held at /RD so vg to vram do nothing,
	1059	* however while the crtc is refreshing the screen it instead is writing zeroes to every location
	1060	* data bits: 76543210
	1061	* \|\|\|\|\|\|\|\-- WRT/RD (write high when x,y (vg) drives vram, read low when ma (crtc) drives vram)
	1062	* \|\|\|\|\|\|\--- /RAS (for vram)
	1063	* \|\|\|\|\|\---- STROBE aka STROBE L aka VG STROBE(latches the carry bit from the adder to the direction rom AND causes the data at the X,Y address of vram to be read into the holding register before pattern is applied)
	1064	* \|\|\|\|\----- LD SHFR (loads the 12-bit shift register of data to be shifted to screen)
	1065	* \|\|\|\------ /CAS (for vram)
	1066	* \|\|\------- RA\__selects which slot of the 8x4 register file (du, dvm, dir, or wops) is selected
	1067	* \|\-------- RB/
	1068	* \--------- VG vector rom "enable"? (mentioned on page 5-31 last paragraph?) (this is off by one cycle though...) [active low, sync addr 011]
	1069	* This may actually have to do with gating the DCNT DONE L signal to make the FINISH signal which unsets the /GO register
	1070	* The VT125 proms E64/E66 and their respective latches E65 and E83 are roughly
	1071	* but not completely equivalent to the sync rom
	1072	*/
1073	1073	ROM_LOAD( "wb8-14_297a1.74s288.pr6.ic89", 0x0300, 0x0020, CRC(e2f7c566) SHA1(a4c3dc5d07667141ad799168a862cb3c489b4934)) // label verified from nigwil's and andy's board
1074	1074	ROM_END
1075	1075

src/mess/drivers/pc.c
r15704	r15705
246	246	AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r, pc_page_w, 0xffff)
247	247	AM_RANGE(0x00a0, 0x00a1) AM_WRITE8( pc_nmi_enable_w, 0x00ff )
248	248	AM_RANGE(0x0210, 0x0217) AM_NOP // expansion chassis interface
249		// AM_RANGE(0x0230, 0x021f) // mouse
	249	// AM_RANGE(0x0230, 0x021f) // mouse
250	250	AM_RANGE(0x0240, 0x0257) AM_READWRITE8(pc_rtc_r, pc_rtc_w, 0xffff)
251	251	AM_RANGE(0x02b0, 0x02b3) AM_READWRITE8(ec1841_memboard_r, ec1841_memboard_w, 0xffff);
252		// AM_RANGE(0x02f8, 0x02f8) AM_DEVREADWRITE8_LEGACY("upd8251_1", i8251_device, data_r, data_w, 0x00ff)
253		// AM_RANGE(0x02f9, 0x02f9) AM_DEVREADWRITE8_LEGACY("upd8251_1", i8251_device, status_r, control_w, 0xff00)
	252	// AM_RANGE(0x02f8, 0x02f8) AM_DEVREADWRITE8_LEGACY("upd8251_1", i8251_device, data_r, data_w, 0x00ff)
	253	// AM_RANGE(0x02f9, 0x02f9) AM_DEVREADWRITE8_LEGACY("upd8251_1", i8251_device, status_r, control_w, 0xff00)
254	254	AM_RANGE(0x0378, 0x037f) AM_DEVREADWRITE8_LEGACY("lpt_0", pc_lpt_r, pc_lpt_w, 0xffff)
255	255	AM_RANGE(0x03f0, 0x03f7) AM_READWRITE8_LEGACY(pc_fdc_r, pc_fdc_w, 0xffff)
256		// AM_RANGE(0x03f8, 0x03f9) AM_DEVREADWRITE8_LEGACY("upd8251_0", i8251_device, data_r, data_w, 0x00ff)
257		// AM_RANGE(0x03f8, 0x03f9) AM_DEVREADWRITE8_LEGACY("upd8251_0", i8251_device, status_r, control_w, 0xff00)
	256	// AM_RANGE(0x03f8, 0x03f9) AM_DEVREADWRITE8_LEGACY("upd8251_0", i8251_device, data_r, data_w, 0x00ff)
	257	// AM_RANGE(0x03f8, 0x03f9) AM_DEVREADWRITE8_LEGACY("upd8251_0", i8251_device, status_r, control_w, 0xff00)
258	258	ADDRESS_MAP_END
259	259
260	260
r15704	r15705
266	266	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("ppi8255", i8255_device, read, write, 0xffff)
267	267	AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r, pc_page_w, 0xffff)
268	268	AM_RANGE(0x00a0, 0x00a1) AM_WRITE8( pc_nmi_enable_w, 0x00ff )
269		// AM_RANGE(0x0200, 0x0207) AM_READWRITE8_LEGACY(pc_JOY_r, pc_JOY_w, 0xffff)
	269	// AM_RANGE(0x0200, 0x0207) AM_READWRITE8_LEGACY(pc_JOY_r, pc_JOY_w, 0xffff)
270	270	AM_RANGE(0x0240, 0x0257) AM_READWRITE8(pc_rtc_r, pc_rtc_w, 0xffff)
271		// AM_RANGE(0x02e8, 0x02ef) AM_DEVREADWRITE8("ins8250_3", ins8250_device, ins8250_r, ins8250_w, 0xffff)
	271	// AM_RANGE(0x02e8, 0x02ef) AM_DEVREADWRITE8("ins8250_3", ins8250_device, ins8250_r, ins8250_w, 0xffff)
272	272	AM_RANGE(0x02f8, 0x02ff) AM_DEVREADWRITE8("ins8250_1", ins8250_device, ins8250_r, ins8250_w, 0xffff)
273	273	AM_RANGE(0x0340, 0x0357) AM_NOP /* anonymous bios should not recogniced realtimeclock */
274	274	AM_RANGE(0x0378, 0x037f) AM_DEVREADWRITE8_LEGACY("lpt_0", pc_lpt_r, pc_lpt_w, 0xffff)
275		// AM_RANGE(0x03e8, 0x03ef) AM_DEVREADWRITE8("ins8250_2", ins8250_device, ins8250_r, ins8250_w, 0xffff)
	275	// AM_RANGE(0x03e8, 0x03ef) AM_DEVREADWRITE8("ins8250_2", ins8250_device, ins8250_r, ins8250_w, 0xffff)
276	276	AM_RANGE(0x03f0, 0x03f7) AM_READWRITE8_LEGACY(pc_fdc_r, pc_fdc_w, 0xffff)
277	277	AM_RANGE(0x03f8, 0x03ff) AM_DEVREADWRITE8("ins8250_0", ins8250_device, ins8250_r, ins8250_w, 0xffff)
278	278	ADDRESS_MAP_END
r15704	r15705
1316	1316
1317	1317	static MACHINE_CONFIG_START( mc1502, pc_state )
1318	1318	/* basic machine hardware */
1319		// MCFG_CPU_PC(mc1502, mc1502, I8088, XTAL_16MHz/3, pcjr_frame_interrupt) /* check frame_interrupt */
	1319	// MCFG_CPU_PC(mc1502, mc1502, I8088, XTAL_16MHz/3, pcjr_frame_interrupt) /* check frame_interrupt */
1320	1320	MCFG_CPU_ADD("maincpu", I8088, XTAL_16MHz/3)
1321	1321	MCFG_CPU_PROGRAM_MAP(mc1502_map)
1322	1322	MCFG_CPU_IO_MAP(mc1502_io)
r15704	r15705
1361	1361	static MACHINE_CONFIG_START( ec1841, pc_state )
1362	1362	/* basic machine hardware */
1363	1363	MCFG_CPU_PC(ec1841, ec1841, I8086, 4096000, pc_frame_interrupt) // correct but slow
1364		// MCFG_CPU_PC(ec1841, ec1841, I8086, 4772720, pc_frame_interrupt)
	1364	// MCFG_CPU_PC(ec1841, ec1841, I8086, 4772720, pc_frame_interrupt)
1365	1365
1366	1366	MCFG_QUANTUM_TIME(attotime::from_hz(60))
1367	1367
r15704	r15705
1377	1377
1378	1378	MCFG_I8255_ADD( "ppi8255", ibm5160_ppi8255_interface )
1379	1379
1380		// MCFG_I8251_ADD( "upd8251_0", default_i8251_interface ) // modeled after BSC adapter?
1381		// MCFG_I8251_ADD( "upd8251_1", default_i8251_interface )
	1380	// MCFG_I8251_ADD( "upd8251_0", default_i8251_interface ) // modeled after BSC adapter?
	1381	// MCFG_I8251_ADD( "upd8251_1", default_i8251_interface )
1382	1382
1383	1383	/* video hardware -- supports font uploads */
1384	1384	MCFG_FRAGMENT_ADD( pcvideo_cga )
r15704	r15705
1403	1403	/* internal ram -- up to 4 banks of 512K */
1404	1404	MCFG_RAM_ADD(RAM_TAG)
1405	1405	MCFG_RAM_DEFAULT_SIZE("512K")
1406		// MCFG_RAM_EXTRA_OPTIONS("640K,1024K,1576K,2048K")
	1406	// MCFG_RAM_EXTRA_OPTIONS("640K,1024K,1576K,2048K")
1407	1407	MACHINE_CONFIG_END
1408	1408
1409	1409

15994 Revisions