src/mess/drivers/p8k.c
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| 44 | 44 | DECLARE_WRITE8_MEMBER(p8k_port0_w); |
| 45 | 45 | DECLARE_READ8_MEMBER(p8k_port24_r); |
| 46 | 46 | DECLARE_WRITE8_MEMBER(p8k_port24_w); |
| 47 | DECLARE_READ16_MEMBER(portff82_r); |
| 48 | DECLARE_WRITE16_MEMBER(portff82_w); |
| 47 | 49 | DECLARE_WRITE8_MEMBER(kbd_put); |
| 48 | 50 | UINT8 m_term_data; |
| 49 | 51 | required_device<cpu_device> m_maincpu; |
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| 153 | 155 | }; |
| 154 | 156 | |
| 155 | 157 | |
| 156 | | #if 0 // we need a real Z8001 CPU core for the 16 bit IO map |
| 158 | //#if 0 // we need a real Z8001 CPU core for the 16 bit IO map |
| 157 | 159 | // TODO: could any of the following be implemented through a DEVREADWRITE8 + suitable mask? |
| 158 | 160 | |
| 159 | 161 | static READ16_DEVICE_HANDLER( p8k_16_sio_r ) |
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| 196 | 198 | |
| 197 | 199 | static READ16_DEVICE_HANDLER( p8k_16_pio_r ) |
| 198 | 200 | { |
| 199 | | return (UINT16)z80pio_r(device, (offset & 0x06) >> 1); |
| 201 | return 0; //(UINT16)z80pio_r(device, (offset & 0x06) >> 1); |
| 200 | 202 | } |
| 201 | 203 | |
| 202 | 204 | static WRITE16_DEVICE_HANDLER( p8k_16_pio_w ) |
| 203 | 205 | { |
| 204 | | z80pio_w(device, (offset & 0x06) >> 1, (UINT8)(data & 0xff)); |
| 206 | //z80pio_w(device, (offset & 0x06) >> 1, (UINT8)(data & 0xff)); |
| 205 | 207 | } |
| 206 | 208 | |
| 207 | 209 | static READ16_DEVICE_HANDLER( p8k_16_ctc_r ) |
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| 214 | 216 | z80ctc_w(device, (offset & 0x06) >> 1, (UINT8)(data & 0xff)); |
| 215 | 217 | } |
| 216 | 218 | |
| 219 | READ16_MEMBER( p8k_state::portff82_r ) |
| 220 | { |
| 221 | if (offset == 3) // FF87 |
| 222 | return 0xff; |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | WRITE16_MEMBER( p8k_state::portff82_w ) |
| 227 | { |
| 228 | if (offset == 1) // FF83 |
| 229 | m_terminal->write(space, 0, data); |
| 230 | } |
| 231 | |
| 232 | |
| 217 | 233 | static ADDRESS_MAP_START(p8k_16_iomap, AS_IO, 16, p8k_state) |
| 218 | 234 | // AM_RANGE(0x0fef0, 0x0feff) // clock |
| 219 | | AM_RANGE(0x0ff80, 0x0ff87) AM_DEVREADWRITE("z80sio_0", p8k_16_sio_r, p8k_16_sio_w) |
| 220 | | AM_RANGE(0x0ff88, 0x0ff8f) AM_DEVREADWRITE("z80sio_1", p8k_16_sio_r, p8k_16_sio_w) |
| 221 | | AM_RANGE(0x0ff90, 0x0ff97) AM_DEVREADWRITE("z80pio_0", p8k_16_pio_r, p8k_16_pio_w) |
| 222 | | AM_RANGE(0x0ff98, 0x0ff9f) AM_DEVREADWRITE("z80pio_1", p8k_16_pio_r, p8k_16_pio_w) |
| 223 | | AM_RANGE(0x0ffa0, 0x0ffa7) AM_DEVREADWRITE("z80pio_2", p8k_16_pio_r, p8k_16_pio_w) |
| 224 | | AM_RANGE(0x0ffa8, 0x0ffaf) AM_DEVREADWRITE("z80ctc_0", p8k_16_ctc_r, p8k_16_ctc_w) |
| 225 | | AM_RANGE(0x0ffb0, 0x0ffb7) AM_DEVREADWRITE("z80ctc_1", p8k_16_ctc_r, p8k_16_ctc_w) |
| 235 | //AM_RANGE(0x0ff80, 0x0ff87) AM_DEVREADWRITE_LEGACY("z80sio_0", p8k_16_sio_r, p8k_16_sio_w) |
| 236 | AM_RANGE(0x0ff80, 0x0ff87) AM_READWRITE(portff82_r,portff82_w) |
| 237 | AM_RANGE(0x0ff88, 0x0ff8f) AM_DEVREADWRITE_LEGACY("z80sio_1", p8k_16_sio_r, p8k_16_sio_w) |
| 238 | AM_RANGE(0x0ff90, 0x0ff97) AM_DEVREADWRITE_LEGACY("z80pio_0", p8k_16_pio_r, p8k_16_pio_w) |
| 239 | AM_RANGE(0x0ff98, 0x0ff9f) AM_DEVREADWRITE_LEGACY("z80pio_1", p8k_16_pio_r, p8k_16_pio_w) |
| 240 | AM_RANGE(0x0ffa0, 0x0ffa7) AM_DEVREADWRITE_LEGACY("z80pio_2", p8k_16_pio_r, p8k_16_pio_w) |
| 241 | AM_RANGE(0x0ffa8, 0x0ffaf) AM_DEVREADWRITE_LEGACY("z80ctc_0", p8k_16_ctc_r, p8k_16_ctc_w) |
| 242 | AM_RANGE(0x0ffb0, 0x0ffb7) AM_DEVREADWRITE_LEGACY("z80ctc_1", p8k_16_ctc_r, p8k_16_ctc_w) |
| 226 | 243 | // AM_RANGE(0x0ffc0, 0x0ffc1) // SCR |
| 227 | 244 | // AM_RANGE(0x0ffc8, 0x0ffc9) // SBR |
| 228 | 245 | // AM_RANGE(0x0ffd0, 0x0ffd1) // NBR |
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| 232 | 249 | // AM_RANGE(0x0fff8, 0x0fff9) // IF1L |
| 233 | 250 | ADDRESS_MAP_END |
| 234 | 251 | |
| 235 | | #endif |
| 252 | //#endif |
| 236 | 253 | |
| 237 | 254 | |
| 238 | 255 | /* Input ports */ |
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| 274 | 291 | //memcpy(state->m_p_ram, ROM, 0x2000); |
| 275 | 292 | } |
| 276 | 293 | |
| 277 | | static VIDEO_START( p8k ) |
| 278 | | { |
| 279 | | } |
| 280 | 294 | |
| 281 | | static SCREEN_UPDATE_IND16( p8k ) |
| 282 | | { |
| 283 | | return 0; |
| 284 | | } |
| 285 | 295 | |
| 286 | | |
| 287 | 296 | /*************************************************************************** |
| 288 | 297 | |
| 289 | 298 | P8000 8bit Peripherals |
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| 672 | 681 | MCFG_CPU_ADD("maincpu", Z8001, XTAL_4MHz ) // actually z8001, appropriate changes pending |
| 673 | 682 | MCFG_CPU_CONFIG(p8k_16_daisy_chain) |
| 674 | 683 | MCFG_CPU_PROGRAM_MAP(p8k_16_memmap) |
| 675 | | // MCFG_CPU_IO_MAP(p8k_16_iomap) |
| 676 | | |
| 677 | | // MCFG_MACHINE_START( p8000_16 ) |
| 684 | MCFG_CPU_IO_MAP(p8k_16_iomap) |
| 678 | 685 | MCFG_MACHINE_RESET(p8k_16) |
| 679 | 686 | |
| 680 | 687 | /* peripheral hardware */ |
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| 692 | 699 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.5) |
| 693 | 700 | |
| 694 | 701 | /* video hardware */ |
| 695 | | MCFG_SCREEN_ADD("screen", RASTER) |
| 696 | | MCFG_SCREEN_REFRESH_RATE(50) |
| 697 | | MCFG_SCREEN_SIZE(640,480) |
| 698 | | MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1) |
| 699 | | MCFG_VIDEO_START(p8k) |
| 700 | | MCFG_SCREEN_UPDATE_STATIC(p8k) |
| 701 | | MCFG_GFXDECODE(p8k) |
| 702 | | MCFG_PALETTE_LENGTH(2) |
| 703 | | MCFG_PALETTE_INIT(black_and_white) |
| 702 | MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, terminal_intf) |
| 704 | 703 | MACHINE_CONFIG_END |
| 705 | 704 | |
| 706 | 705 | /* ROM definition */ |