Previous

15994 Revisions

Next

r15201 Wednesday 16th May, 2012 at 15:37:28 UTC by Curt Coder
[E01] Added SCSI bus. (nw)

[src/mess/drivers]	e01.c
[src/mess/includes]	e01.h

src/mess/includes/e01.h

r15200	r15201
	1	/**********************************************************************
	2
	3	Acorn FileStore E01/E20 network hard disk emulation
	4
	5	Copyright MESS Team.
	6	Visit http://mamedev.org for licensing and usage restrictions.
	7
	8	**********************************************************************/
	9
1	10	#pragma once
2	11
3	12	#ifndef __E01__
r15200	r15201
7	16	#include "emu.h"
8	17	#include "cpu/m6502/m6502.h"
9	18	#include "imagedev/flopdrv.h"
10		#include "machine/ram.h"
	19	#include "imagedev/harddriv.h"
11	20	#include "machine/ctronics.h"
12	21	#include "machine/6522via.h"
13	22	#include "machine/mc146818.h"
14	23	#include "machine/mc6854.h"
	24	#include "machine/ram.h"
	25	#include "machine/scsibus.h"
15	26	#include "machine/wd17xx.h"
16	27
17	28	#define R65C102_TAG      "r65c102"
r15200	r15201
20	31	#define MC6854_TAG      "mc6854"
21	32	#define HD146818_TAG   "hd146818"
22	33	#define CENTRONICS_TAG   "centronics"
	34	#define SCSIBUS_TAG      "scsi"
23	35
24	36	class e01_state : public driver_device
25	37	{
r15200	r15201
29	41	m_maincpu(*this, R65C102_TAG),
30	42	m_fdc(*this, WD2793_TAG),
31	43	m_rtc(*this, HD146818_TAG),
32		m_ram(*this, RAM_TAG)
	44	m_ram(*this, RAM_TAG),
	45	m_scsibus(*this, SCSIBUS_TAG)
33	46	{ }
34	47
35	48	required_device<cpu_device> m_maincpu;
36	49	required_device<device_t> m_fdc;
37	50	required_device<mc146818_device> m_rtc;
38	51	required_device<ram_device> m_ram;
	52	required_device<device_t> m_scsibus;
39	53
40	54	virtual void machine_start();
41	55	virtual void machine_reset();
r15200	r15201
49	63	DECLARE_WRITE8_MEMBER( network_irq_disable_w );
50	64	DECLARE_READ8_MEMBER( network_irq_enable_r );
51	65	DECLARE_WRITE8_MEMBER( network_irq_enable_w );
	66	DECLARE_READ8_MEMBER( hdc_data_r );
	67	DECLARE_WRITE8_MEMBER( hdc_data_w );
	68	DECLARE_READ8_MEMBER( hdc_status_r );
	69	DECLARE_WRITE8_MEMBER( hdc_select_w );
52	70	DECLARE_WRITE8_MEMBER( hdc_irq_enable_w );
53	71	DECLARE_READ8_MEMBER( rtc_address_r );
54	72	DECLARE_WRITE8_MEMBER( rtc_address_w );
r15200	r15201
58	76	DECLARE_WRITE_LINE_MEMBER( adlc_irq_w );
59	77	DECLARE_WRITE_LINE_MEMBER( via_irq_w );
60	78	DECLARE_WRITE_LINE_MEMBER( fdc_drq_w );
	79	DECLARE_WRITE_LINE_MEMBER( scsi_bsy_w );
	80	DECLARE_WRITE_LINE_MEMBER( scsi_req_w );
61	81
62	82	/* interrupt state */
63	83	int m_adlc_ie;

src/mess/drivers/e01.c

r15200	r15201
1		/***************************************************************************
	1	/**********************************************************************
2	2
3		Acorn AEH26 FileStore E01
	3	Acorn FileStore E01/E20 network hard disk emulation
4	4
5		20/05/2010 Skeleton driver.
	5	Copyright MESS Team.
	6	Visit http://mamedev.org for licensing and usage restrictions.
6	7
7	8	http://acorn.chriswhy.co.uk/Network/Econet.html
8	9	http://acorn.chriswhy.co.uk/Network/Pics/Acorn_FileStoreE01.html
9	10	http://acorn.chriswhy.co.uk/8bit_Upgrades/Acorn_FileStoreE01S.html
10	11	http://www.heyrick.co.uk/econet/fs/emulator.html
	12	http://www.pdfio.com/k-1019481.html#
11	13
12		****************************************************************************/
	14	**********************************************************************/
13	15
14	16	/*
15	17
r15200	r15201
37	39
38	40	TODO:
39	41
40		- RTC interrupts (rewrite mc146818)
	42	- centronics strobe
	43	- VIA CB2 -> econet rx/tx clock terminator
41	44	- ADLC interrupts
42	45	- ECONET device
43		- printer
44	46	- artwork
45	47	- hard disk
46	48
	49	E20: Rodime RO652 (-chs 306,4,17,512)
	50	E40S:
	51	E60S:
	52
47	53	*/
48	54
49	55	#include "includes/e01.h"
50	56	#include "e01.lh"
51	57
52		/***************************************************************************
53		INTERRUPT HANDLING
54		***************************************************************************/
55	58
56		/*-------------------------------------------------
57		update_interrupts - update interrupt state
58		-------------------------------------------------*/
59	59
	60	//**************************************************************************
	61	//  INTERRUPT HANDLING
	62	//**************************************************************************
	63
	64	//-------------------------------------------------
	65	//  update_interrupts - update interrupt state
	66	//-------------------------------------------------
	67
60	68	void e01_state::update_interrupts()
61	69	{
62		m_maincpu->set_input_line(INPUT_LINE_IRQ0, (m_via_irq || (m_hdc_ie & m_hdc_irq) || m_rtc_irq) ? ASSERT_LINE : CLEAR_LINE);
63		m_maincpu->set_input_line(INPUT_LINE_NMI, (m_fdc_drq || (m_adlc_ie & m_adlc_irq)) ? ASSERT_LINE : CLEAR_LINE);
	70	int irq = (m_via_irq || (m_hdc_ie & m_hdc_irq) || m_rtc_irq) ? ASSERT_LINE : CLEAR_LINE;
	71	int nmi = (m_fdc_drq || (m_adlc_ie & m_adlc_irq)) ? ASSERT_LINE : CLEAR_LINE;
	72
	73	m_maincpu->set_input_line(INPUT_LINE_IRQ0, irq);
	74	m_maincpu->set_input_line(INPUT_LINE_NMI, nmi);
64	75	}
65	76
66		/*-------------------------------------------------
67		network_irq_enable - network interrupt enable
68		-------------------------------------------------*/
69	77
	78	//-------------------------------------------------
	79	//   network_irq_enable - network interrupt enable
	80	//-------------------------------------------------
	81
70	82	void e01_state::network_irq_enable(int enabled)
71	83	{
72	84	m_adlc_ie = enabled;
r15200	r15201
74	86	update_interrupts();
75	87	}
76	88
77		/*-------------------------------------------------
78		hdc_irq_enable - hard disk interrupt enable
79		-------------------------------------------------*/
80	89
	90	//-------------------------------------------------
	91	//   hdc_irq_enable - hard disk interrupt enable
	92	//-------------------------------------------------
	93
81	94	void e01_state::hdc_irq_enable(int enabled)
82	95	{
83	96	m_hdc_ie = enabled;
r15200	r15201
85	98	update_interrupts();
86	99	}
87	100
88		/***************************************************************************
89		READ/WRITE HANDLERS
90		***************************************************************************/
91	101
92		/*-------------------------------------------------
93		eprom_r - ROM/RAM select read
94		-------------------------------------------------*/
95	102
	103	//**************************************************************************
	104	//  READ/WRITE HANDLERS
	105	//**************************************************************************
	106
	107	//-------------------------------------------------
	108	//  eprom_r - ROM/RAM select read
	109	//-------------------------------------------------
	110
96	111	READ8_MEMBER( e01_state::ram_select_r )
97	112	{
98	113	membank("bank1")->set_entry(0);
r15200	r15201
101	116	return 0;
102	117	}
103	118
104		/*-------------------------------------------------
105		floppy_w - floppy control write
106		-------------------------------------------------*/
107	119
	120	//-------------------------------------------------
	121	//  floppy_w - floppy control write
	122	//-------------------------------------------------
	123
108	124	WRITE8_MEMBER( e01_state::floppy_w )
109	125	{
110	126	/*
r15200	r15201
119	135	5       floppy master reset
120	136	6       floppy test
121	137	7       mode LED
122
123		*/
124
125		/* floppy 1 select */
	138
	139	*/
	140
	141	// floppy 1 select
126	142	if (!BIT(data, 0)) wd17xx_set_drive(m_fdc, 0);
127	143
128		/* floppy 2 select */
	144	// floppy 2 select
129	145	if (!BIT(data, 1)) wd17xx_set_drive(m_fdc, 1);
130	146
131		/* floppy side select */
	147	// floppy side select
132	148	wd17xx_set_side(m_fdc, BIT(data, 2));
133	149
134		/* TODO NVRAM select */
	150	// TODO NVRAM select
135	151	//mc146818_stby_w(m_rtc, BIT(data, 3));
136	152
137		/* floppy density */
	153	// floppy density
138	154	wd17xx_dden_w(m_fdc, BIT(data, 4));
139	155
140		/* floppy master reset */
	156	// floppy master reset
141	157	wd17xx_mr_w(m_fdc, BIT(data, 5));
142	158
143		/* TODO floppy test */
	159	// TODO floppy test
144	160	//wd17xx_test_w(m_fdc, BIT(data, 6));
145	161
146		/* mode LED */
	162	// mode LED
147	163	output_set_value("led_0", BIT(data, 7));
148	164	}
149	165
	166
	167	//-------------------------------------------------
	168	//  network_irq_disable_r -
	169	//-------------------------------------------------
	170
150	171	READ8_MEMBER( e01_state::network_irq_disable_r )
151	172	{
152	173	network_irq_enable(0);
r15200	r15201
154	175	return 0;
155	176	}
156	177
	178
	179	//-------------------------------------------------
	180	//  network_irq_disable_w -
	181	//-------------------------------------------------
	182
157	183	WRITE8_MEMBER( e01_state::network_irq_disable_w )
158	184	{
159	185	network_irq_enable(0);
160	186	}
161	187
	188
	189	//-------------------------------------------------
	190	//  network_irq_enable_r -
	191	//-------------------------------------------------
	192
162	193	READ8_MEMBER( e01_state::network_irq_enable_r )
163	194	{
164	195	network_irq_enable(1);
r15200	r15201
166	197	return 0;
167	198	}
168	199
	200
	201	//-------------------------------------------------
	202	//  network_irq_enable_w -
	203	//-------------------------------------------------
	204
169	205	WRITE8_MEMBER( e01_state::network_irq_enable_w )
170	206	{
171	207	network_irq_enable(1);
172	208	}
173	209
	210
	211	//-------------------------------------------------
	212	//  hdc_data_r -
	213	//-------------------------------------------------
	214
	215	READ8_MEMBER( e01_state::hdc_data_r )
	216	{
	217	UINT8 data = scsi_data_r(m_scsibus, 0);
	218
	219	scsi_ack_w(m_scsibus, 0);
	220
	221	return data;
	222	}
	223
	224
	225	//-------------------------------------------------
	226	//  hdc_data_w -
	227	//-------------------------------------------------
	228
	229	WRITE8_MEMBER( e01_state::hdc_data_w )
	230	{
	231	scsi_data_w(m_scsibus, 0, data);
	232
	233	scsi_ack_w(m_scsibus, 0);
	234	}
	235
	236
	237	//-------------------------------------------------
	238	//  hdc_status_r -
	239	//-------------------------------------------------
	240
	241	READ8_MEMBER( e01_state::hdc_status_r )
	242	{
	243	/*
	244
	245	bit     description
	246
	247	0       MSG
	248	1       BSY
	249	2       0
	250	3       0
	251	4       NIRQ
	252	5       REQ
	253	6       I/O
	254	7       C/D
	255
	256	*/
	257
	258	UINT8 data = 0;
	259
	260	data |= !scsi_msg_r(m_scsibus);
	261	data |= !scsi_bsy_r(m_scsibus) << 1;
	262	data |= !scsi_req_r(m_scsibus) << 5;
	263	data |= !scsi_io_r(m_scsibus) << 6;
	264	data |= !scsi_cd_r(m_scsibus) << 7;
	265
	266	return data;
	267	}
	268
	269
	270	//-------------------------------------------------
	271	//  hdc_select_w -
	272	//-------------------------------------------------
	273
	274	WRITE8_MEMBER( e01_state::hdc_select_w )
	275	{
	276	scsi_sel_w(m_scsibus, 0);
	277	}
	278
	279
	280	//-------------------------------------------------
	281	//  hdc_irq_enable_w -
	282	//-------------------------------------------------
	283
174	284	WRITE8_MEMBER( e01_state::hdc_irq_enable_w )
175	285	{
176	286	hdc_irq_enable(BIT(data, 0));
177	287	}
178	288
	289
	290	//-------------------------------------------------
	291	//  rtc_address_r -
	292	//-------------------------------------------------
	293
179	294	READ8_MEMBER( e01_state::rtc_address_r )
180	295	{
181	296	return m_rtc->read(space, 0);
182	297	}
183	298
	299
	300	//-------------------------------------------------
	301	//  rtc_address_w -
	302	//-------------------------------------------------
	303
184	304	WRITE8_MEMBER( e01_state::rtc_address_w )
185	305	{
186	306	m_rtc->write(space, 0, data);
187	307	}
188	308
	309
	310	//-------------------------------------------------
	311	//  rtc_data_r -
	312	//-------------------------------------------------
	313
189	314	READ8_MEMBER( e01_state::rtc_data_r )
190	315	{
191	316	return m_rtc->read(space, 1);
192	317	}
193	318
	319
	320	//-------------------------------------------------
	321	//  rtc_data_w -
	322	//-------------------------------------------------
	323
194	324	WRITE8_MEMBER( e01_state::rtc_data_w )
195	325	{
196	326	m_rtc->write(space, 1, data);
197	327	}
198	328
199		/***************************************************************************
200		MEMORY MAPS
201		***************************************************************************/
202	329
203		/*-------------------------------------------------
204		ADDRESS_MAP( e01_mem )
205		-------------------------------------------------*/
	330	//**************************************************************************
	331	//  MEMORY MAPS
	332	//**************************************************************************
206	333
	334	//-------------------------------------------------
	335	//  ADDRESS_MAP( e01_mem )
	336	//-------------------------------------------------
	337
207	338	static ADDRESS_MAP_START( e01_mem, AS_PROGRAM, 8, e01_state )
208	339	AM_RANGE(0x0000, 0xfbff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank2")
209	340	AM_RANGE(0xfc00, 0xfc00) AM_MIRROR(0x00c3) AM_READWRITE(rtc_address_r, rtc_address_w)
r15200	r15201
215	346	AM_RANGE(0xfc24, 0xfc24) AM_MIRROR(0x00c3) AM_READWRITE(network_irq_disable_r, network_irq_disable_w)
216	347	AM_RANGE(0xfc28, 0xfc28) AM_MIRROR(0x00c3) AM_READWRITE(network_irq_enable_r, network_irq_enable_w)
217	348	AM_RANGE(0xfc2c, 0xfc2c) AM_MIRROR(0x00c3) AM_READ_PORT("FLAP")
218		//  AM_RANGE(0xfc30, 0xfc30) AM_MIRROR(0x00c0) HD data
219		//  AM_RANGE(0xfc31, 0xfc31) AM_MIRROR(0x00c0) HD status
220		//  AM_RANGE(0xfc32, 0xfc32) AM_MIRROR(0x00c0) HD select
	349	AM_RANGE(0xfc30, 0xfc30) AM_MIRROR(0x00c0) AM_READWRITE(hdc_data_r, hdc_data_w)
	350	AM_RANGE(0xfc31, 0xfc31) AM_MIRROR(0x00c0) AM_READ(hdc_status_r)
	351	AM_RANGE(0xfc32, 0xfc32) AM_MIRROR(0x00c0) AM_WRITE(hdc_select_w)
221	352	AM_RANGE(0xfc33, 0xfc33) AM_MIRROR(0x00c0) AM_WRITE(hdc_irq_enable_w)
222	353	AM_RANGE(0xfd00, 0xffff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank4")
223	354	ADDRESS_MAP_END
224	355
225		/***************************************************************************
226		INPUT PORTS
227		***************************************************************************/
228	356
229		/*-------------------------------------------------
230		INPUT_PORTS( e01 )
231		-------------------------------------------------*/
232	357
	358	//**************************************************************************
	359	//  INPUT PORTS
	360	//**************************************************************************
	361
	362	//-------------------------------------------------
	363	//  INPUT_PORTS( e01 )
	364	//-------------------------------------------------
	365
233	366	static INPUT_PORTS_START( e01 )
234	367	PORT_START("FLAP")
235	368	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNUSED )
r15200	r15201
241	374	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
242	375	INPUT_PORTS_END
243	376
244		/***************************************************************************
245		DEVICE CONFIGURATION
246		***************************************************************************/
247	377
248		/*-------------------------------------------------
249		MC146818_INTERFACE( rtc_intf )
250		-------------------------------------------------*/
251	378
	379	//**************************************************************************
	380	//  DEVICE CONFIGURATION
	381	//**************************************************************************
	382
	383	//-------------------------------------------------
	384	//  MC146818_INTERFACE( rtc_intf )
	385	//-------------------------------------------------
	386
252	387	WRITE_LINE_MEMBER( e01_state::rtc_irq_w )
253	388	{
254	389	m_rtc_irq = state;
r15200	r15201
256	391	update_interrupts();
257	392	}
258	393
259		static TIMER_DEVICE_CALLBACK( rtc_irq_hack )
	394	static mc146818_interface rtc_intf =
260	395	{
261		e01_state *state = timer.machine().driver_data<e01_state>();
	396	DEVCB_DRIVER_LINE_MEMBER(e01_state, rtc_irq_w)
	397	};
262	398
263		state->m_rtc_irq = !state->m_rtc_irq;
264	399
265		state->update_interrupts();
266		}
	400	//-------------------------------------------------
	401	//  mc6854_interface adlc_intf
	402	//-------------------------------------------------
267	403
268		/*-------------------------------------------------
269		mc6854_interface adlc_intf
270		-------------------------------------------------*/
271
272	404	WRITE_LINE_MEMBER( e01_state::adlc_irq_w )
273	405	{
274	406	m_adlc_irq = state;
r15200	r15201
284	416	NULL
285	417	};
286	418
287		/*-------------------------------------------------
288		via6522_interface via_intf
289		-------------------------------------------------*/
290	419
	420	//-------------------------------------------------
	421	//  via6522_interface via_intf
	422	//-------------------------------------------------
	423
291	424	WRITE_LINE_MEMBER( e01_state::via_irq_w )
292	425	{
293	426	m_via_irq = state;
r15200	r15201
303	436	DEVCB_NULL,
304	437	DEVCB_NULL,
305	438	DEVCB_NULL,
	439
	440	DEVCB_DEVICE_MEMBER(CENTRONICS_TAG, centronics_device, write),
306	441	DEVCB_NULL,
307	442	DEVCB_NULL,
308	443	DEVCB_NULL,
309	444	DEVCB_NULL,
310	445	DEVCB_NULL,
311		DEVCB_NULL,
	446
312	447	DEVCB_DRIVER_LINE_MEMBER(e01_state, via_irq_w)
313	448	};
314	449
315		/*-------------------------------------------------
316		floppy_interface e01_floppy_interface
317		-------------------------------------------------*/
318	450
	451	//-------------------------------------------------
	452	//  floppy_interface e01_floppy_interface
	453	//-------------------------------------------------
	454
319	455	static const floppy_interface e01_floppy_interface =
320	456	{
321	457	DEVCB_NULL,
r15200	r15201
329	465	NULL
330	466	};
331	467
332		/*-------------------------------------------------
333		wd17xx_interface fdc_intf
334		-------------------------------------------------*/
335	468
	469	//-------------------------------------------------
	470	//  wd17xx_interface fdc_intf
	471	//-------------------------------------------------
	472
336	473	WRITE_LINE_MEMBER( e01_state::fdc_drq_w )
337	474	{
338	475	m_fdc_drq = state;
r15200	r15201
348	485	{ FLOPPY_0, FLOPPY_1, NULL, NULL }
349	486	};
350	487
351		/***************************************************************************
352		MACHINE INITIALIZATION
353		***************************************************************************/
354	488
355		/*-------------------------------------------------
356		MACHINE_START( e01 )
357		-------------------------------------------------*/
	489	//-------------------------------------------------
	490	//  SCSIBus_interface scsi_intf
	491	//-------------------------------------------------
358	492
	493	static const SCSIConfigTable scsi_dev_table =
	494	{
	495	1,
	496	{
	497	{ SCSI_ID_0, "harddisk0", SCSI_DEVICE_HARDDISK }
	498	}
	499	};
	500
	501	WRITE_LINE_MEMBER( e01_state::scsi_bsy_w )
	502	{
	503	if (!state)
	504	{
	505	scsi_sel_w(m_scsibus, 1);
	506	}
	507	}
	508
	509	WRITE_LINE_MEMBER( e01_state::scsi_req_w )
	510	{
	511	if (state)
	512	{
	513	scsi_ack_w(m_scsibus, 1);
	514	}
	515
	516	m_hdc_irq = !state;
	517	update_interrupts();
	518	}
	519
	520	static const SCSIBus_interface scsi_intf =
	521	{
	522	&scsi_dev_table,
	523	NULL,
	524	DEVCB_DRIVER_LINE_MEMBER(e01_state, scsi_bsy_w),
	525	DEVCB_NULL,
	526	DEVCB_NULL,
	527	DEVCB_NULL,
	528	DEVCB_NULL,
	529	DEVCB_DRIVER_LINE_MEMBER(e01_state, scsi_req_w),
	530	DEVCB_NULL
	531	};
	532
	533
	534	//-------------------------------------------------
	535	//  centronics_interface e01_centronics_intf
	536	//-------------------------------------------------
	537
	538	static centronics_interface e01_centronics_intf =
	539	{
	540	DEVCB_DEVICE_LINE_MEMBER(R6522_TAG, via6522_device, write_ca1),
	541	DEVCB_NULL,
	542	DEVCB_NULL
	543	};
	544
	545
	546
	547	//**************************************************************************
	548	//  MACHINE INITIALIZATION
	549	//**************************************************************************
	550
	551	//-------------------------------------------------
	552	//  MACHINE_START( e01 )
	553	//-------------------------------------------------
	554
359	555	void e01_state::machine_start()
360	556	{
361	557	UINT8 *ram = m_ram->pointer();
362	558	UINT8 *rom = memregion(R65C102_TAG)->base();
363	559
364		/* setup memory banking */
	560	// setup memory banking
365	561	membank("bank1")->configure_entry(0, ram);
366	562	membank("bank1")->configure_entry(1, rom);
367	563	membank("bank1")->set_entry(1);
r15200	r15201
376	572	membank("bank4")->configure_entry(0, ram + 0xfd00);
377	573	membank("bank4")->set_entry(0);
378	574
379		/* register for state saving */
	575	// register for state saving
380	576	save_item(NAME(m_adlc_ie));
381	577	save_item(NAME(m_hdc_ie));
382	578	save_item(NAME(m_rtc_irq));
r15200	r15201
386	582	save_item(NAME(m_adlc_irq));
387	583	}
388	584
389		/*-------------------------------------------------
390		MACHINE_RESET( e01 )
391		-------------------------------------------------*/
392	585
	586	//-------------------------------------------------
	587	//  MACHINE_RESET( e01 )
	588	//-------------------------------------------------
	589
393	590	void e01_state::machine_reset()
394	591	{
	592	init_scsibus(m_scsibus, 512);
	593
395	594	membank("bank1")->set_entry(1);
396	595	membank("bank3")->set_entry(1);
397	596	}
398	597
399		/***************************************************************************
400		MACHINE DRIVERS
401		***************************************************************************/
402	598
403		/*-------------------------------------------------
404		MACHINE_DRIVER( e01 )
405		-------------------------------------------------*/
406	599
	600	//**************************************************************************
	601	//  MACHINE DRIVERS
	602	//**************************************************************************
	603
	604	//-------------------------------------------------
	605	//  MACHINE_DRIVER( e01 )
	606	//-------------------------------------------------
	607
407	608	static MACHINE_CONFIG_START( e01, e01_state )
408		/* basic machine hardware */
409		MCFG_CPU_ADD(R65C102_TAG, M65C02, 1000000) // Rockwell R65C102P3
	609	// basic machine hardware
	610	MCFG_CPU_ADD(R65C102_TAG, M65C02, XTAL_8MHz/4) // Rockwell R65C102P3
410	611	MCFG_CPU_PROGRAM_MAP(e01_mem)
411	612
412		MCFG_MC146818_ADD(HD146818_TAG, MC146818_STANDARD)
	613	MCFG_MC146818_IRQ_ADD(HD146818_TAG, MC146818_STANDARD, rtc_intf)
413	614
414		MCFG_TIMER_ADD_PERIODIC("rtc_hack", rtc_irq_hack, attotime::from_hz(2)) // HACK!
415
416		/* video hardware */
	615	// video hardware
417	616	MCFG_DEFAULT_LAYOUT( layout_e01 )
418	617
419		/* devices */
420		MCFG_VIA6522_ADD(R6522_TAG, 100000, via_intf)
	618	// devices
	619	MCFG_VIA6522_ADD(R6522_TAG, XTAL_8MHz/4, via_intf)
421	620	MCFG_MC6854_ADD(MC6854_TAG, adlc_intf)
422	621	MCFG_WD2793_ADD(WD2793_TAG, fdc_intf)
423	622	MCFG_LEGACY_FLOPPY_2_DRIVES_ADD(e01_floppy_interface)
424		//  MCFG_CENTRONICS_PRINTER_ADD(CENTRONICS_TAG, e01_centronics_config)
	623	MCFG_CENTRONICS_PRINTER_ADD(CENTRONICS_TAG, e01_centronics_intf)
425	624
426		/* internal ram */
	625	MCFG_SCSIBUS_ADD(SCSIBUS_TAG, scsi_intf)
	626	MCFG_HARDDISK_ADD("harddisk0")
	627
	628	// internal ram
427	629	MCFG_RAM_ADD(RAM_TAG)
428	630	MCFG_RAM_DEFAULT_SIZE("64K")
429	631	MACHINE_CONFIG_END
430	632
431		/***************************************************************************
432		ROMS
433		***************************************************************************/
434	633
435		/*-------------------------------------------------
436		ROM( e01 )
437		-------------------------------------------------*/
438	634
	635	//**************************************************************************
	636	//  ROMS
	637	//**************************************************************************
	638
	639	//-------------------------------------------------
	640	//  ROM( e01 )
	641	//-------------------------------------------------
	642
439	643	ROM_START( e01 )
440	644	ROM_REGION( 0x10000, R65C102_TAG, 0 )
441	645	ROM_DEFAULT_BIOS("v131")
r15200	r15201
444	648	ROMX_LOAD( "0254,205-03 e01 mos", 0x8000, 0x8000, CRC(a13e8014) SHA1(6f44a1a48108c60a64a1774cb30c1a59c4a6a199), ROM_BIOS(1) )
445	649	ROM_END
446	650
447		/*-------------------------------------------------
448		ROM( e01s )
449		-------------------------------------------------*/
450	651
	652	//-------------------------------------------------
	653	//  ROM( e01s )
	654	//-------------------------------------------------
	655
451	656	ROM_START( e01s )
452	657	ROM_REGION( 0x10000, R65C102_TAG, 0 )
453	658	ROM_DEFAULT_BIOS("v140")
r15200	r15201
457	662	ROMX_LOAD( "e01sv140.rom",  0x0000, 0x10000, CRC(5068fe86) SHA1(9b8740face15b5541e2375b3054988af00757931), ROM_BIOS(2) ) // which label?
458	663	ROM_END
459	664
460		/***************************************************************************
461		SYSTEM DRIVERS
462		***************************************************************************/
463	665
464		/*    YEAR  NAME      PARENT    COMPAT  MACHINE   INPUT     INIT      COMPANY   FULLNAME */
	666
	667	//**************************************************************************
	668	//  SYSTEM DRIVERS
	669	//**************************************************************************
	670
	671	//    YEAR  NAME      PARENT    COMPAT  MACHINE   INPUT     INIT      COMPANY   FULLNAME
465	672	COMP( 1988, e01,  0,       0,   e01,   e01,    0,  "Acorn",   "FileStore E01",      GAME_NOT_WORKING | GAME_NO_SOUND)
466	673	COMP( 1988, e01s, e01,       0,   e01,   e01,    0,  "Acorn",   "FileStore E01S",      GAME_NOT_WORKING | GAME_NO_SOUND)

Previous

15994 Revisions

Next

---

© 1998-2018 The MESS Team