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r15186 Wednesday 16th May, 2012 at 01:20:06 UTC by R. Belmont
Made Z8001 I/O 16 bits wide, proper 8259 PIC hookup on M20 (no EC tests fail now) [R. Belmont, Christian Gr?\195?\182ssler]
[src/emu/cpu/z8000]z8000.c
[src/mess/drivers]m20.c

src/emu/cpu/z8000/z8000.c
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246246{
247247   if(mode == 0)
248248   {
249      return cpustate->io->read_byte((UINT16)(addr)) +
250           (cpustate->io->read_byte((UINT16)(addr+1)) << 8);
249        if (cpustate->device->type() == Z8001)
250        {
251            return cpustate->io->read_word((UINT16)addr);
252        }
253        else
254        {
255            return cpustate->io->read_byte((UINT16)(addr)) +
256                  (cpustate->io->read_byte((UINT16)(addr+1)) << 8);
257        }
251258   }
252259   else
253260   {
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272279{
273280   if(mode == 0)
274281   {
275      cpustate->io->write_byte((UINT16)(addr),value & 0xff);
276      cpustate->io->write_byte((UINT16)(addr+1),(value >> 8) & 0xff);
282        if (cpustate->device->type() == Z8001)
283        {
284            cpustate->io->write_word((UINT16)addr, value);
285        }
286        else
287        {
288            cpustate->io->write_byte((UINT16)(addr),value & 0xff);
289            cpustate->io->write_byte((UINT16)(addr+1),(value >> 8) & 0xff);
290        }
277291   }
278292   else
279293   {
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795809   {
796810      case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 16;               break;
797811      case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 20;               break;
798      case DEVINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 8;               break;
812      case DEVINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 16;               break;
799813      case DEVINFO_INT_ADDRBUS_WIDTH + AS_IO:      info->i = 16;               break;
800814
801815      /* --- the following bits of info are returned as pointers to data or functions --- */
src/mess/drivers/m20.c
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4242#include "machine/i8251.h"
4343#include "machine/i8255.h"
4444#include "machine/pit8253.h"
45#include "machine/pic8259.h"
4546#include "imagedev/flopdrv.h"
4647#include "formats/basicdsk.h"
4748
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5455        m_kbdi8251(*this, "i8251_1"),
5556        m_ttyi8251(*this, "i8251_2"),
5657        m_i8255(*this, "ppi8255"),
58        m_i8259(*this, "i8259"),
5759      m_p_videoram(*this, "p_videoram"){ }
5860
5961    required_device<device_t> m_maincpu;
6062    required_device<i8251_device> m_kbdi8251;
6163    required_device<i8251_device> m_ttyi8251;
6264    required_device<i8255_device> m_i8255;
65    required_device<device_t> m_i8259;
6366   required_shared_ptr<UINT16> m_p_videoram;
6467
6568    virtual void machine_reset();
6669
67   DECLARE_READ8_MEMBER(ppi_r);
68   DECLARE_WRITE8_MEMBER(ppi_w);
70    DECLARE_READ16_MEMBER(m20_i8259_r);
71    DECLARE_WRITE16_MEMBER(m20_i8259_w);
72    DECLARE_WRITE_LINE_MEMBER(pic_irq_line_w);
6973};
7074
7175
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106110   return 0;
107111}
108112
109// translate addresses 81/83/85/87 to PPI offsets 0/1/2/3
110READ8_MEMBER(m20_state::ppi_r)
113READ16_MEMBER(m20_state::m20_i8259_r)
111114{
112    return m_i8255->read(space, offset/2);
115    return pic8259_r(m_i8259, offset)<<1;
113116}
114117
115WRITE8_MEMBER(m20_state::ppi_w)
118WRITE16_MEMBER(m20_state::m20_i8259_w)
116119{
117    m_i8255->write(space, offset/2, data);
120    pic8259_w(m_i8259, offset, (data>>1));
118121}
119122
120// same for pit8253
121READ8_DEVICE_HANDLER(m20_pit8253_r)
123WRITE_LINE_MEMBER( m20_state::pic_irq_line_w )
122124{
123    return pit8253_r(device, offset / 2);
125    if (state)
126    {
127        // PIC raised IRQ line
128    }
129    else
130    {
131        // PIC lowered IRQ line
132    }
124133}
125134
126WRITE8_DEVICE_HANDLER(m20_pit8253_w)
127{
128    pit8253_w(device, offset / 2, data);
129}
130
131135/* from the M20 hardware reference manual:
132136   M20 memory is configured according to the following scheme:
133137   Segment   Contents
r15185r15186
157161//  AM_RANGE( 0x20000, 0x2???? ) //work RAM?
158162ADDRESS_MAP_END
159163
160static ADDRESS_MAP_START(m20_io, AS_IO, 8, m20_state)
164static ADDRESS_MAP_START(m20_io, AS_IO, 16, m20_state)
161165   ADDRESS_MAP_UNMAP_HIGH
162166
163   AM_RANGE(0x01, 0x01) AM_DEVWRITE_LEGACY("wd177x", wd17xx_command_w)
164   AM_RANGE(0x03, 0x03) AM_DEVREADWRITE_LEGACY("wd177x", wd17xx_track_r, wd17xx_track_w)
165   AM_RANGE(0x05, 0x05) AM_DEVREADWRITE_LEGACY("wd177x", wd17xx_sector_r, wd17xx_sector_w)
166   AM_RANGE(0x07, 0x07) AM_DEVREADWRITE_LEGACY("wd177x", wd17xx_data_r, wd17xx_data_w)
167   AM_RANGE(0x00, 0x01) AM_DEVWRITE8_LEGACY("wd177x", wd17xx_command_w, 0x00ff)
168   AM_RANGE(0x02, 0x03) AM_DEVREADWRITE8_LEGACY("wd177x", wd17xx_track_r, wd17xx_track_w, 0x00ff)
169   AM_RANGE(0x04, 0x05) AM_DEVREADWRITE8_LEGACY("wd177x", wd17xx_sector_r, wd17xx_sector_w, 0x00ff)
170   AM_RANGE(0x06, 0x07) AM_DEVREADWRITE8_LEGACY("wd177x", wd17xx_data_r, wd17xx_data_w, 0x00ff)
167171
168   AM_RANGE(0x61, 0x61) AM_DEVWRITE("crtc", mc6845_device, address_w)
169   AM_RANGE(0x63, 0x63) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
170    AM_RANGE(0x81, 0x87) AM_READWRITE(ppi_r, ppi_w)
171    AM_RANGE(0xa1, 0xa1) AM_DEVREADWRITE("i8251_1", i8251_device, data_r, data_w)
172    AM_RANGE(0xa3, 0xa3) AM_DEVREADWRITE("i8251_1", i8251_device, status_r, control_w)
173    AM_RANGE(0xc1, 0xc1) AM_DEVREADWRITE("i8251_2", i8251_device, data_r, data_w)
174    AM_RANGE(0xc3, 0xc3) AM_DEVREADWRITE("i8251_2", i8251_device, status_r, control_w)
172   AM_RANGE(0x60, 0x61) AM_DEVWRITE8("crtc", mc6845_device, address_w, 0x00ff)
173   AM_RANGE(0x62, 0x63) AM_DEVREADWRITE8("crtc", mc6845_device, register_r, register_w, 0x00ff)
175174
176   AM_RANGE(0x121, 0x127) AM_DEVREADWRITE_LEGACY("pit8253", m20_pit8253_r, m20_pit8253_w)
175   AM_RANGE(0x80, 0x87) AM_DEVREADWRITE8("ppi8255", i8255_device, read, write, 0x00ff)
177176
177    AM_RANGE(0xa0, 0xa1) AM_DEVREADWRITE8("i8251_1", i8251_device, data_r, data_w, 0x00ff)
178    AM_RANGE(0xa2, 0xa3) AM_DEVREADWRITE8("i8251_1", i8251_device, status_r, control_w, 0x00ff)
179    AM_RANGE(0xc0, 0xc1) AM_DEVREADWRITE8("i8251_2", i8251_device, data_r, data_w, 0x00ff)
180    AM_RANGE(0xc2, 0xc3) AM_DEVREADWRITE8("i8251_2", i8251_device, status_r, control_w, 0x00ff)
181
182   AM_RANGE(0x120, 0x127) AM_DEVREADWRITE8_LEGACY("pit8253", pit8253_r, pit8253_w, 0x00ff)
183
184   AM_RANGE(0x140, 0x143) AM_READWRITE(m20_i8259_r, m20_i8259_w)
185//   AM_RANGE(0x140, 0x143) AM_DEVREADWRITE8_LEGACY("i8259", pic8259_r, pic8259_w, 0xffff)
186
178187   // 0x21?? / 0x21? - fdc ... seems to control the screen colors???
179188ADDRESS_MAP_END
180189
r15185r15186
313322   }
314323};
315324
325const struct pic8259_interface pic_intf =
326{
327   DEVCB_DRIVER_LINE_MEMBER(m20_state, pic_irq_line_w),
328    DEVCB_LINE_VCC, // we're the only 8259, so we're the master
329   DEVCB_NULL
330};
331
316332static MACHINE_CONFIG_START( m20, m20_state )
317333   /* basic machine hardware */
318334   MCFG_CPU_ADD("maincpu", Z8001, MAIN_CLOCK)
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343359   MCFG_I8251_ADD("i8251_1", kbd_i8251_intf)
344360   MCFG_I8251_ADD("i8251_2", tty_i8251_intf)
345361   MCFG_PIT8253_ADD("pit8253", pit8253_intf)
362   MCFG_PIC8259_ADD("i8259", pic_intf)
346363   MCFG_LEGACY_FLOPPY_2_DRIVES_ADD(m20_floppy_interface)
347364MACHINE_CONFIG_END
348365

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