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r15149 Saturday 12th May, 2012 at 13:53:49 UTC by Miodrag Milanović
Added PPC405GP to PPC cpu core [Lukasz Markowski]

Added custom DCR read/write handlers to PPC cpu core [Miodrag Milanovic]

dm7000 work in progress by Lukasz (no whatsnew)
[src/emu/cpu/powerpc]ppc.c ppc.h ppccom.c ppccom.h ppcdrc.c
[src/mess/drivers]dm7000.c

src/emu/cpu/powerpc/ppcdrc.c
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441441   assert(device != NULL);
442442   assert(device->type() == PPC403GA ||
443443         device->type() == PPC403GCX ||
444         device->type() == PPC405GP ||
444445         device->type() == PPC601 ||
445446         device->type() == PPC602 ||
446447         device->type() == PPC603 ||
r15148r15149
44284429
44294430
44304431
4432/*-------------------------------------------------
4433    ppc403gcx_init - PowerPC 403GCX-specific
4434    initialization
4435-------------------------------------------------*/
4436
4437static CPU_INIT( ppc405gp )
4438{
4439   ppcdrc_init(PPC_MODEL_405GP, PPCCAP_4XX | PPCCAP_VEA, 1, device, irqcallback);
4440}
4441
4442
4443/*-------------------------------------------------
4444    ppc403gcx_get_info - PowerPC 403GCX-specific
4445    information getter
4446-------------------------------------------------*/
4447
4448CPU_GET_INFO( ppc405gp )
4449{
4450   switch (state)
4451   {
4452      /* --- the following bits of info are returned as 64-bit signed integers --- */
4453
4454      /* --- the following bits of info are returned as pointers to data or functions --- */
4455      case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(ppc405gp);         break;
4456      case CPUINFO_FCT_SET_INFO:                  info->setinfo = CPU_SET_INFO_NAME(ppcdrc4xx);      break;
4457
4458      /* --- the following bits of info are returned as NULL-terminated strings --- */
4459      case DEVINFO_STR_NAME:                     strcpy(info->s, "PowerPC 405GP");      break;
4460
4461      /* --- everything else is handled generically --- */
4462      default:                              CPU_GET_INFO_CALL(ppcdrc4xx);      break;
4463   }
4464}
4465
4466
44314467/***************************************************************************
44324468    PPC 6XX VARIANTS
44334469***************************************************************************/
r15148r15149
46774713DEFINE_LEGACY_CPU_DEVICE(PPC403GA, ppc403ga);
46784714DEFINE_LEGACY_CPU_DEVICE(PPC403GCX, ppc403gcx);
46794715
4716DEFINE_LEGACY_CPU_DEVICE(PPC405GP, ppc405gp);
4717
46804718DEFINE_LEGACY_CPU_DEVICE(PPC601, ppc601);
46814719DEFINE_LEGACY_CPU_DEVICE(PPC602, ppc602);
46824720DEFINE_LEGACY_CPU_DEVICE(PPC603, ppc603);
src/emu/cpu/powerpc/ppccom.c
r15148r15149
318318   ppc->program = device->space(AS_PROGRAM);
319319   ppc->direct = &ppc->program->direct();
320320   ppc->system_clock = (config != NULL) ? config->bus_frequency : device->clock();
321   ppc->dcr_read_func = (config != NULL) ? config->dcr_read_func : NULL;
322   ppc->dcr_write_func = (config != NULL) ? config->dcr_write_func : NULL;
323
321324   ppc->tb_divisor = (ppc->tb_divisor * device->clock() + ppc->system_clock / 2 - 1) / ppc->system_clock;
322325   ppc->codexor = 0;
323326   if (!(cap & PPCCAP_4XX) && device->space_config()->m_endianness != ENDIANNESS_NATIVE)
r15148r15149
10851088
10861089   /* default handling */
10871090   mame_printf_debug("DCR %03X read\n", ppc->param0);
1088   if (ppc->param0 < ARRAY_LENGTH(ppc->dcr))
1089      ppc->param1 = ppc->dcr[ppc->param0];
1090   else
1091      ppc->param1 = 0;
1091   if (!ppc->dcr_read_func) {
1092      if (ppc->param0 < ARRAY_LENGTH(ppc->dcr))
1093         ppc->param1 = ppc->dcr[ppc->param0];
1094      else
1095         ppc->param1 = 0;
1096   } else {
1097      ppc->param1 = ppc->dcr_read_func(ppc->device,ppc->param0,0xffffffff);
1098   }
10921099}
10931100
10941101
r15148r15149
11731180
11741181   /* default handling */
11751182   mame_printf_debug("DCR %03X write = %08X\n", ppc->param0, ppc->param1);
1176   if (ppc->param0 < ARRAY_LENGTH(ppc->dcr))
1177      ppc->dcr[ppc->param0] = ppc->param1;
1183   if (!ppc->dcr_write_func) {
1184      if (ppc->param0 < ARRAY_LENGTH(ppc->dcr))
1185         ppc->dcr[ppc->param0] = ppc->param1;
1186   } else {
1187      ppc->dcr_write_func(ppc->device,ppc->param0,ppc->param1,0xffffffff);
1188   }
11781189}
11791190
11801191
src/emu/cpu/powerpc/ppc.c
r15148r15149
973973
974974}
975975
976static CPU_INIT( ppc405 )
977{
978   const ppc_config *configdata = device->static_config();
979
980   ppc_init();
981
982   /* PPC403 specific opcodes */
983   ppc.optable31[454] = ppc_dccci;
984   ppc.optable31[486] = ppc_dcread;
985   ppc.optable31[262] = ppc_icbt;
986   ppc.optable31[966] = ppc_iccci;
987   ppc.optable31[998] = ppc_icread;
988   ppc.optable31[323] = ppc_mfdcr;
989   ppc.optable31[451] = ppc_mtdcr;
990   ppc.optable31[131] = ppc_wrtee;
991   ppc.optable31[163] = ppc_wrteei;
992
993   // !!! why is rfci here !!!
994   ppc.optable19[51] = ppc_rfci;
995
996   ppc.spu.rx_timer = device->machine().scheduler().timer_alloc(FUNC(ppc403_spu_rx_callback));
997   ppc.spu.tx_timer = device->machine().scheduler().timer_alloc(FUNC(ppc403_spu_tx_callback));
998
999   ppc.read8 = ppc403_read8;
1000   ppc.read16 = ppc403_read16;
1001   ppc.read32 = ppc403_read32;
1002   ppc.write8 = ppc403_write8;
1003   ppc.write16 = ppc403_write16;
1004   ppc.write32 = ppc403_write32;
1005   ppc.read16_unaligned = ppc403_read16_unaligned;
1006   ppc.read32_unaligned = ppc403_read32_unaligned;
1007   ppc.write16_unaligned = ppc403_write16_unaligned;
1008   ppc.write32_unaligned = ppc403_write32_unaligned;
1009
1010   ppc.irq_callback = irqcallback;
1011   ppc.device = device;
1012   ppc.program = device->space(AS_PROGRAM);
1013
1014   ppc.pvr = configdata->pvr;
1015}
1016
1017static CPU_EXIT( ppc405 )
1018{
1019
1020}
1021
9761022static CPU_INIT( ppc603 )
9771023{
9781024   const ppc_config *configdata = device->static_config();
r15148r15149
18931939   }
18941940}
18951941
1942CPU_GET_INFO( ppc405 )
1943{
1944   switch(state)
1945   {
1946      /* --- the following bits of info are returned as 64-bit signed integers --- */
1947      case CPUINFO_INT_INPUT_LINES:               info->i = 8;                     break;
1948      case DEVINFO_INT_ENDIANNESS:               info->i = ENDIANNESS_BIG;               break;
1949      case CPUINFO_INT_REGISTER + PPC_EXIER:         info->i = EXIER;                  break;
1950      case CPUINFO_INT_REGISTER + PPC_EXISR:         info->i = EXISR;                  break;
1951
1952      /* --- the following bits of info are returned as pointers to data or functions --- */
1953      case CPUINFO_FCT_SET_INFO:                  info->setinfo = CPU_SET_INFO_NAME(ppc403);      break;
1954      case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(ppc403);            break;
1955      case CPUINFO_FCT_RESET:                     info->reset = CPU_RESET_NAME(ppc403);            break;
1956      case CPUINFO_FCT_EXIT:                     info->exit = CPU_EXIT_NAME(ppc403);            break;
1957      case CPUINFO_FCT_EXECUTE:                  info->execute = CPU_EXECUTE_NAME(ppc403);         break;
1958
1959      /* --- the following bits of info are returned as NULL-terminated strings --- */
1960      case DEVINFO_STR_NAME:                     strcpy(info->s, "PPC403");            break;
1961      case CPUINFO_STR_REGISTER + PPC_EXIER:         sprintf(info->s, "EXIER: %08X", EXIER); break;
1962      case CPUINFO_STR_REGISTER + PPC_EXISR:         sprintf(info->s, "EXISR: %08X", EXISR); break;
1963
1964      default:                              CPU_GET_INFO_CALL(ppc);            break;
1965   }
1966}
1967
18961968CPU_GET_INFO( ppc603 )
18971969{
18981970   switch(state)
r15148r15149
20982170DEFINE_LEGACY_CPU_DEVICE(PPC403GA, ppc403ga);
20992171DEFINE_LEGACY_CPU_DEVICE(PPC403GCX, ppc403gcx);
21002172
2173DEFINE_LEGACY_CPU_DEVICE(PPC405GP, ppc405gp);
2174
21012175DEFINE_LEGACY_CPU_DEVICE(PPC601, ppc601);
21022176DEFINE_LEGACY_CPU_DEVICE(PPC602, ppc602);
21032177DEFINE_LEGACY_CPU_DEVICE(PPC603, ppc603);
src/emu/cpu/powerpc/ppccom.h
r15148r15149
565565
566566   /* for use by specific implementations */
567567   ppcimp_state *   impstate;
568
569   read32_device_func   dcr_read_func;
570   write32_device_func   dcr_write_func;   
568571};
569572
570573
src/emu/cpu/powerpc/ppc.h
r15148r15149
151151struct _powerpc_config
152152{
153153   UINT32      bus_frequency;
154   read32_device_func   dcr_read_func;
155   write32_device_func   dcr_write_func;   
154156};
155157
156158
r15148r15149
170172DECLARE_LEGACY_CPU_DEVICE(PPC403GA, ppc403ga);
171173DECLARE_LEGACY_CPU_DEVICE(PPC403GCX, ppc403gcx);
172174
175DECLARE_LEGACY_CPU_DEVICE(PPC405GP, ppc405gp);
176
173177DECLARE_LEGACY_CPU_DEVICE(PPC601, ppc601);
174178DECLARE_LEGACY_CPU_DEVICE(PPC602, ppc602);
175179DECLARE_LEGACY_CPU_DEVICE(PPC603, ppc603);
src/mess/drivers/dm7000.c
r15148r15149
3939#include "emu.h"
4040#include "cpu/powerpc/ppc.h"
4141
42#define VERBOSE_LEVEL ( 0 )
4243
44INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ...)
45{
46   if (VERBOSE_LEVEL >= n_level)
47   {
48      va_list v;
49      char buf[32768];
50      va_start( v, s_fmt);
51      vsprintf( buf, s_fmt, v);
52      va_end( v);
53      logerror( "%s: %s", machine.describe_context( ), buf);
54   }
55}
56
4357class dm7000_state : public driver_device
4458{
4559public:
4660   dm7000_state(const machine_config &mconfig, device_type type, const char *tag)
47      : driver_device(mconfig, type, tag) { }
61      : driver_device(mconfig, type, tag),
62      m_maincpu(*this, "maincpu")   { }
4863
64   required_device<cpu_device> m_maincpu;
65   
66   DECLARE_WRITE8_MEMBER ( dm7000_iic0_w );
67   DECLARE_READ8_MEMBER ( dm7000_iic0_r );
68   DECLARE_WRITE8_MEMBER ( dm7000_iic1_w );
69   DECLARE_READ8_MEMBER ( dm7000_iic1_r );
70   
71   DECLARE_WRITE8_MEMBER ( dm7000_scc0_w );
72   DECLARE_READ8_MEMBER ( dm7000_scc0_r );
73   UINT8 m_scc0_lcr;
74   UINT8 m_scc0_lsr;
75   
76   DECLARE_WRITE8_MEMBER ( dm7000_gpio0_w );
77   DECLARE_READ8_MEMBER ( dm7000_gpio0_r );
78   
79   DECLARE_WRITE8_MEMBER ( dm7000_scp0_w );
80   DECLARE_READ8_MEMBER ( dm7000_scp0_r );
81   
82   UINT32         dcr[512];   
4983};
5084
85READ8_MEMBER( dm7000_state::dm7000_iic0_r )
86{
87   UINT32 data = 0; // dummy
88   verboselog( machine(), 9, "(IIC0) %08X -> %08X (PC %08X)\n", 0x40030000 + offset, data, cpu_get_pc(m_maincpu));
89   return data;
90}
5191
92WRITE8_MEMBER( dm7000_state::dm7000_iic0_w )
93{
94   verboselog( machine(), 9, "(IIC0) %08X <- %08X (PC %08X)\n", 0x40030000 + offset, data, cpu_get_pc(m_maincpu));
95}
96
97READ8_MEMBER( dm7000_state::dm7000_iic1_r )
98{
99   UINT32 data = 0; // dummy
100   verboselog( machine(), 9, "(IIC1) %08X -> %08X (PC %08X)\n", 0x400b0000 + offset, data, cpu_get_pc(m_maincpu));
101   return data;
102}
103
104WRITE8_MEMBER( dm7000_state::dm7000_iic1_w )
105{
106   verboselog( machine(), 9, "(IIC1) %08X <- %08X (PC %08X)\n", 0x400b0000 + offset, data, cpu_get_pc(m_maincpu));
107}
108
109#define UART_DLL   0
110#define UART_RBR   0
111#define UART_THR   0
112#define UART_DLH   1
113#define UART_IER   1
114#define UART_IIR   2
115#define UART_FCR   2
116#define UART_LCR   3
117#define    UART_LCR_DLAB   0x80
118#define UART_MCR   4
119#define UART_LSR   5
120#define      UART_LSR_TEMT   0x20
121#define      UART_LSR_THRE   0x40
122#define UART_MSR   6
123#define UART_SCR   7
124
125READ8_MEMBER( dm7000_state::dm7000_scc0_r )
126{
127   UINT32 data = 0; // dummy
128   switch(offset) {
129      case UART_LSR:
130         data = UART_LSR_THRE | UART_LSR_TEMT;
131         break;
132   }
133   verboselog( machine(), 9, "(SCC0) %08X -> %08X (PC %08X)\n", 0x40040000 + offset, data, cpu_get_pc(m_maincpu));
134   return data;
135}
136
137WRITE8_MEMBER( dm7000_state::dm7000_scc0_w )
138{
139   switch(offset) {
140      case UART_THR:
141         if(!(m_scc0_lcr & UART_LCR_DLAB)) {
142            printf("%c", data);
143         }
144         break;
145      case UART_LCR:
146         m_scc0_lcr = data;
147         break;
148   }
149   verboselog( machine(), 9, "(SCC0) %08X <- %08X (PC %08X)\n", 0x40040000 + offset, data, cpu_get_pc(m_maincpu));
150}
151
152READ8_MEMBER( dm7000_state::dm7000_gpio0_r )
153{
154   UINT32 data = 0; // dummy
155   verboselog( machine(), 9, "(GPIO0) %08X -> %08X (PC %08X)\n", 0x40060000 + offset, data, cpu_get_pc(m_maincpu));
156   return data;
157}
158
159WRITE8_MEMBER( dm7000_state::dm7000_gpio0_w )
160{
161   verboselog( machine(), 9, "(GPIO0) %08X <- %08X (PC %08X)\n", 0x40060000 + offset, data, cpu_get_pc(m_maincpu));
162}
163
164#define SCP_SPMODE 0
165#define SCP_RXDATA 1
166#define SCP_TXDATA 2
167#define SCP_SPCOM 3
168#define SCP_STATUS 4
169#define    SCP_STATUS_RXRDY 1
170#define SCP_CDM 6
171
172READ8_MEMBER( dm7000_state::dm7000_scp0_r )
173{
174   UINT32 data = 0; // dummy
175   switch(offset) {
176      case SCP_STATUS:
177         data = SCP_STATUS_RXRDY;
178         break;
179   }
180   verboselog( machine(), 9, "(SCP0) %08X -> %08X (PC %08X)\n", 0x400c0000 + offset, data, cpu_get_pc(m_maincpu));
181   return data;
182}
183
184WRITE8_MEMBER( dm7000_state::dm7000_scp0_w )
185{
186   verboselog( machine(), 9, "(SCP0) %08X <- %08X (PC %08X)\n", 0x400c0000 + offset, data, cpu_get_pc(m_maincpu));
187   switch(offset) {
188      case SCP_TXDATA:
189         //printf("%02X ", data);
190         break;
191   }
192}
193
52194/*
53195 Memory map for the IBM "Redwood-4" STB03xxx evaluation board.
54196
55197 The  STB03xxx internal i/o addresses don't work for us 1:1,
56198 so we need to map them at a well know virtual address.
57199
58 4000 000x   uart1           -> 0xe000 000x
200 4000 000x   uart1
59201 4001 00xx   ppu
60202 4002 00xx   smart card
61203 4003 000x   iic
r15148r15149
66208 400b 000x   iic
67209 400c 000x   scp
68210 400d 000x   modem
211 
212 STB04xxx
213 
214 4000 00xx   Serial1/Infrared Controller
215 4001 00xx   Universal Serial Bus
216 4002 00xx   Smart Card Interface 0
217 4003 000x   IIC Interface 0
218 4004 000x   Serial0/Uart750 Controller
219 4005 0xxx   General Purpose Timers
220 4006 00xx   General Purpose Input / Output
221 4007 00xx   Smart Card Interface 1
222 400b 000x   IIC Interface 1
223 400c 000x   Serial Controller Port
224 400d 00xx   Synchronous Serial Port
225 400e 000x   Serial2/UART750 Controller
226 400f 0xxx   IDE Controller
227 
69228*/
70229static ADDRESS_MAP_START( dm7000_mem, AS_PROGRAM, 32, dm7000_state )
71230   ADDRESS_MAP_UNMAP_HIGH
72   AM_RANGE(0x00000000, 0x01ffffff) AM_RAM   // RAM page 0 - 32MB
73   AM_RANGE(0x20000000, 0x21ffffff) AM_RAM // RAM page 1 - 32MB
231   AM_RANGE(0x00000000, 0x01ffffff) AM_RAM                              // RAM page 0 - 32MB
232   AM_RANGE(0x20000000, 0x21ffffff) AM_RAM                              // RAM page 1 - 32MB
233   
234   AM_RANGE(0x40030000, 0x4003000f) AM_READWRITE8(dm7000_iic0_r, dm7000_iic0_w, 0xffffffff)
235   AM_RANGE(0x40040000, 0x40040007) AM_READWRITE8(dm7000_scc0_r, dm7000_scc0_w, 0xffffffff)
236   AM_RANGE(0x40060000, 0x40060047) AM_READWRITE8(dm7000_gpio0_r, dm7000_gpio0_w, 0xffffffff)
237   AM_RANGE(0x400b0000, 0x400b000f) AM_READWRITE8(dm7000_iic1_r, dm7000_iic1_w, 0xffffffff)
238   AM_RANGE(0x400c0000, 0x400c0007) AM_READWRITE8(dm7000_scp0_r, dm7000_scp0_w, 0xffffffff)
239   
74240   AM_RANGE(0xfffe0000, 0xffffffff) AM_ROM AM_REGION("user1",0)
75241ADDRESS_MAP_END
76242
r15148r15149
81247
82248static MACHINE_RESET(dm7000)
83249{
250   dm7000_state *state = machine.driver_data<dm7000_state>();
251   
252   state->m_scc0_lsr = UART_LSR_THRE | UART_LSR_TEMT;
84253}
85254
86255static VIDEO_START( dm7000 )
r15148r15149
91260{
92261   return 0;
93262}
263#define DCRSTB045_CMD_STAT    0x14a      /* Command status */
94264
265static READ32_DEVICE_HANDLER( dcr_r )
266{
267   dm7000_state *state = device->machine().driver_data<dm7000_state>();
268   switch(offset) {
269      case DCRSTB045_CMD_STAT:
270         return 0; // assume that video dev is always ready
271      default:
272         return state->dcr[offset];
273   }
274
275}
276
277static WRITE32_DEVICE_HANDLER( dcr_w )
278{
279   dm7000_state *state = device->machine().driver_data<dm7000_state>();
280   state->dcr[offset] = data;
281}
282
283static const powerpc_config ppc405_config =
284{
285   252000000,
286   dcr_r,
287   dcr_w
288};
289
95290static MACHINE_CONFIG_START( dm7000, dm7000_state )
96291   /* basic machine hardware */
97   MCFG_CPU_ADD("maincpu",PPC403GA, 252000000) // Should be PPC405
292   MCFG_CPU_ADD("maincpu",PPC405GP, 252000000) // Should be PPC405
98293   MCFG_CPU_PROGRAM_MAP(dm7000_mem)
99294
100295   MCFG_MACHINE_RESET(dm7000)

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