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r14964 Thursday 19th April, 2012 at 11:44:11 UTC by Miodrag Milanović
Sync with MAME r16029 and more driver modernization (no whatsnew)

[src/emu]	device.c device.h diexec.c diexec.h disound.c disound.h memory.c memory.h
[src/emu/sound]	2151intf.c 2151intf.h i5000.c i5000.h okim6295.c okim6295.h
[src/mame]	mame.lst mame.mak
[src/mame/audio]	atarijsa.c mcr.c mcr.h midway.c* midway.h* seibu.c t5182.c williams.c williams.h
[src/mame/drivers]	aliens.c amspdwy.c aquarium.c asuka.c atarig42.c atarisy1.c atarisy2.c bfm_sc4.c bfm_sc4h.c blockout.c bmcbowl.c boogwing.c byvid.c cabal.c cave.c cbuster.c chinagat.c chqflag.c cninja.c cps1.c cps3.c crimfght.c cyberbal.c darkseal.c dassault.c dblewing.c dbz.c ddragon.c ddragon3.c deco32.c dietgo.c dlair.c dooyong.c exzisus.c fantland.c fitfight.c funkyjet.c galaga.c gotcha.c hng64.c hornet.c hyprduel.c igs017.c lemmings.c m107.c m72.c m90.c m92.c madmotor.c mcr.c mcr3.c mcr68.c megasys1.c merit.c metro.c midtunit.c midyunit.c missile.c mjkjidai.c mlanding.c mpu4.c mugsmash.c namcos1.c namcos10.c nemesis.c ninjaw.c nmk16.c nova2001.c opwolf.c photon2.c plygonet.c rabbit.c rainbow.c rastan.c renegade.c rohga.c rpunch.c segahang.c segas16a.c segas24.c segaxbd.c segaybd.c seta.c sf.c shadfrce.c shisen.c sidearms.c sigmab98.c silvmil.c snowbros.c srmp6.c starwars.c subsino.c subsino2.c supbtime.c surpratk.c taito_x.c tatsumi.c tecmo16.c tickee.c tmmjprd.c tmnt.c topspeed.c tourtabl.c tumbleb.c tumblep.c vaportra.c vball.c vcombat.c vigilant.c williams.c wwfsstar.c wwfwfest.c
[src/mame/includes]	aerofgt.h alpha68k.h argus.h astrocde.h atarig42.h atarigt.h atarisy2.h bfm_sc45.h bloodbro.h cclimber.h centiped.h cischeat.h cninja.h cps3.h dooyong.h fantland.h fastfred.h fitfight.h flstory.h galpani2.h galpanic.h gberet.h gottlieb.h hng64.h itech32.h kaneko16.h liberate.h m72.h m90.h mcr.h mcr68.h meadows.h midtunit.h midvunit.h midwunit.h midyunit.h model2.h moo.h mystwarr.h n8080.h ninjakd2.h nmk16.h nova2001.h offtwall.h ojankohs.h pktgaldx.h plygonet.h qix.h rainbow.h realbrk.h scramble.h segas32.h seta2.h snes.h starwars.h suna8.h system16.h tatsumi.h tmnt.h toaplan1.h tubep.h unico.h wecleman.h williams.h
[src/mame/layout]	bfm_sc4.lay
[src/mame/machine]	atarigen.c atarigen.h bfm_bd1.c mcr.c mcr68.c midtunit.c midyunit.c opwolf.c snes.c williams.c
[src/mame/video]	decospr.c fastfred.c galpanic.c gotcha.c mcr68.c suna8.c tia.c tia.h zaxxon.c
[src/mess/drivers]	a2600.c a7800.c ami1200.c amstr_pc.c amstrad.c apollo.c apple1.c apple3.c aquarius.c atm.c b2m.c bbc.c bk.c busicom.c cbmb.c comquest.c concept.c craft.c dai.c einstein.c electron.c elwro800.c enterp.c fm7.c galaxy.c galeb.c gb.c gba.c glasgow.c gmaster.c gp32.c hec2hrp.c interact.c ip22.c irisha.c lisa.c llc.c lviv.c lynx.c mbc55x.c microtan.c mikro80.c mikrosha.c msx.c mtx.c mz700.c nascom1.c nc.c nes.c ng_aes.c odyssey2.c ondra.c orao.c oric.c orion.c partner.c pc.c pce.c pcw.c pcw16.c pecom.c pentagon.c pmd85.c poly88.c pp01.c primo.c psx.c radio86.c rmnimbus.c samcoupe.c sapi1.c scorpion.c sms.c spec128.c specpls3.c spectrum.c svi318.c svision.c ti85.c ti99_2.c timex.c vtech2.c x68k.c z80ne.c
[src/mess/formats]	m65_snqk.c
[src/mess/includes]	a7800.h amstrad.h apollo.h apple1.h apple3.h aquarius.h at.h b2m.h bbc.h bk.h busicom.h cbmb.h comquest.h concept.h dai.h einstein.h electron.h enterp.h fm7.h galaxy.h galeb.h gb.h gba.h gmaster.h gp32.h hec2hrp.h irisha.h lisa.h llc.h lviv.h lynx.h mbc55x.h microtan.h mikro80.h msx.h mtx.h mz700.h nascom1.h nc.h nes.h odyssey2.h ondra.h orao.h oric.h orion.h partner.h pc.h pce.h pcw.h pcw16.h pecom.h pk8020.h pmd85.h poly88.h pp01.h primo.h radio86.h rmnimbus.h samcoupe.h sapi1.h sms.h spectrum.h svi318.h svision.h ti85.h vtech2.h z80ne.h zx.h
[src/mess/machine]	a7800.c amstrad.c apollo.c apple1.c apple3.c at.c b2m.c bbc.c bk.c cbmb.c concept.c dai.c ecb_grip.c electron.c galaxy.c gb.c hec2hrp.c irisha.c isa_ibm_mfc.c isa_ibm_mfc.h lisa.c llc.c lviv.c lynx.c mbc55x.c microtan.c mikro80.c msx.c mtx.c mz700.c nascom1.c nes.c odyssey2.c ondra.c orao.c oric.c orion.c partner.c pc.c pce.c pecom.c pk8020.c pmd85.c poly88.c pp01.c primo.c radio86.c rmnimbus.c samcoupe.c sapi1.c sms.c svi318.c ti85.c vtech2.c z80ne.c zx.c
[src/mess/video]	a7800.c aquarius.c bbc.c fm7.c gb.c microtan.c mz700.c odyssey2.c pecom.c rmnimbus.c vtech2.c
[src/osd/windows]	windows.mak

src/mame/mame.lst

r14963	r14964
10079	10079	fitfight      // bootleg of Art of Fighting
10080	10080	histryma      // bootleg of Fighter's History
10081	10081	bbprot         // unfinished prototype
	10082	hotmindff      // (c) Playmark
10082	10083	beaminv         // (c) 1979 Tekunon Kougyou (Arcade TV Game List - P.95, Left, 9 from top)
10083	10084	pacominv      // (c) 1979 Pacom Corporation
10084	10085	mcatadv         // (c) 1993 Wintechno
r14963	r14964
13914	13915	sc4mclbe   //
13915	13916	sc4mdlx      // Monopoly Deluxe (Mazooma)
13916	13917	sc4mondxg   //
13917		sc4mowowd   //
13918	13918	sc4mont      // Montego Pay (Qps)
13919	13919	sc4monta   //
13920	13920	sc4montb   //
r14963	r14964
13956	13956	sc4pacmn   // Pac Man (Mazooma)
13957	13957	sc4pacmna   //
13958	13958	sc4pacmnb   //
13959		sc4pacmnc   //
13960		sc4pacmnd   //
13961		sc4pacmne   //
	13959	sc4pacqp   //
	13960	sc4pacqpa   //
	13961	sc4pacqpb   //
13962	13962	sc4paccs   // Pac Man Casino (Mazooma)
13963	13963	sc4paccsa   //
13964	13964	sc4paccsb   //
r14963	r14964
15094	15094	sc4gballa   //
15095	15095	sc4gballb   //
15096	15096	sc4gballc   //
15097		sc4ggame   // Golden Game (Mazooma)
	15097	sc4ggtb       // Golden Game (Mazooma) Top Box
	15098	sc4ggtba   //
	15099	sc4ggtbb   //
	15100	sc4ggame   // Golden Game
15098	15101	sc4ggamea   //
15099	15102	sc4ggameb   //
15100	15103	sc4ggamec   //
15101	15104	sc4ggamed   //
15102		sc4ggamee   //
15103	15105	sc4ggamef   //
15104	15106	sc4ggameg   //
15105		sc4ggameh   //
15106	15107	sc4ggamei   //
15107	15108	sc4ggamej   //
15108	15109	sc4ggamek   //
15109	15110	sc4ggamel   //
15110	15111	sc4ggamem   //
15111	15112	sc4ggamen   //
15112		sc4ggameo   //
15113	15113	sc4ggamep   //
15114	15114	sc4ggameq   //
15115	15115	sc4ggamer   //
r14963	r14964
15144	15144	sc4ggdlxe   //
15145	15145	sc4ggdlxf   //
15146	15146	sc4ggdlxg   //
15147		sc4ggg      // Grand Golden Game (Mazooma)
15148		sc4ggga      //
	15147	sc4gggtb   // Grand Golden Game (Mazooma)
	15148	sc4gggtba   //
	15149	sc4ggg      //
15149	15150	sc4gggb      //
15150	15151	sc4gggc      //
15151	15152	sc4gggd      //
r14963	r14964
15154	15155	sc4gggg      //
15155	15156	sc4gggh      //
15156	15157	sc4gggi      //
15157		sc4gggj      //
15158	15158	sc4gggk      //
15159	15159	sc4gggl      //
15160	15160	sc4gggm      //
r14963	r14964
15653	15653	sc4dndben   //
15654	15654	sc4dndbc   // Deal Or No Deal Box Clever (Bellfruit)
15655	15655	sc4dndbca   //
	15656	sc4bwow     // Wheel of Wealth (Bellfruit)
	15657	sc4bwowa   //
15656	15658	sc4mowow   // Monopoly Wheel Of Wealth (Mazooma)
15657	15659	sc4mowowa   //
15658	15660	sc4mowowb   //
15659	15661	sc4mowowc   //
15660		sc4mowowe   //
15661		sc4mowowf   //
15662		sc4mowowg   //
15663		sc4mowowh   //
15664		sc4mowowi   //
15665		sc4mowowj   //
	15662	sc4mwwtb   //
	15663	sc4mwwtba   //
	15664	sc4mwwtbb   //
	15665	sc4mwwtbc   //
	15666	sc4mwwtbd   //
15666	15667	sc4nunsm   // Nuns 'n' Roses (Mazooma)
15667	15668	sc4nunsmb   //
15668	15669	sc4nunsmc   //

src/mame/audio/mcr.c

r14963	r14964
1		/***************************************************************************
2
3		audio/mcr.c
4
5		Functions to emulate general the various MCR sound cards.
6
7		***************************************************************************/
8
9		#include "emu.h"
10		#include "cpu/z80/z80.h"
11		#include "cpu/m68000/m68000.h"
12		#include "cpu/m6800/m6800.h"
13		#include "cpu/m6809/m6809.h"
14		#include "sound/tms5220.h"
15		#include "sound/ay8910.h"
16		#include "sound/dac.h"
17		#include "audio/williams.h"
18		#include "includes/mcr.h"
19		#include "audio/mcr.h"
20
21
22
23		/*************************************
24		*
25		*  Constants
26		*
27		*************************************/
28
29		#define SSIO_CLOCK         XTAL_16MHz
30		#define CSDELUXE_CLOCK      XTAL_16MHz
31		#define SOUNDSGOOD_CLOCK   XTAL_16MHz
32		#define TURBOCS_CLOCK      XTAL_8MHz
33		#define SQUAWKTALK_CLOCK   XTAL_3_579545MHz
34
35
36
37		/*************************************
38		*
39		*  Global variables
40		*
41		*************************************/
42
43		static UINT8 mcr_sound_config;
44
45
46
47		/*************************************
48		*
49		*  Statics
50		*
51		*************************************/
52
53		static UINT16 dacval;
54
55		/* SSIO-specific globals */
56		static device_t *ssio_sound_cpu;
57		static UINT8 ssio_data[4];
58		static UINT8 ssio_status;
59		static UINT8 ssio_14024_count;
60		static UINT8 ssio_mute;
61		static UINT8 ssio_overall[2];
62		static UINT8 ssio_duty_cycle[2][3];
63		static UINT8 ssio_ayvolume_lookup[16];
64		static UINT8 ssio_custom_input_mask[5];
65		static UINT8 ssio_custom_output_mask[2];
66		static read8_delegate ssio_custom_input[5];
67		static write8_delegate ssio_custom_output[2];
68
69		/* Chip Squeak Deluxe-specific globals */
70		static device_t *csdeluxe_sound_cpu;
71		static UINT8 csdeluxe_status;
72
73		/* Turbo Chip Squeak-specific globals */
74		static device_t *turbocs_sound_cpu;
75		static UINT8 turbocs_status;
76
77		/* Sounds Good-specific globals */
78		static device_t *soundsgood_sound_cpu;
79		static UINT8 soundsgood_status;
80
81		/* Squawk n' Talk-specific globals */
82		static device_t *squawkntalk_sound_cpu;
83		static UINT8 squawkntalk_tms_command;
84		static UINT8 squawkntalk_tms_strobes;
85
86
87
88		/*************************************
89		*
90		*  Prototypes
91		*
92		*************************************/
93
94		static void ssio_compute_ay8910_modulation(running_machine &machine);
95
96
97
98		/*************************************
99		*
100		*  Generic MCR sound initialization
101		*
102		*************************************/
103
104		void mcr_sound_init(running_machine &machine, UINT8 config)
105		{
106		mcr_sound_config = config;
107
108		/* SSIO */
109		if (mcr_sound_config & MCR_SSIO)
110		{
111		ssio_sound_cpu = machine.device("ssiocpu");
112		ssio_compute_ay8910_modulation(machine);
113		state_save_register_global_array(machine, ssio_data);
114		state_save_register_global(machine, ssio_status);
115		state_save_register_global(machine, ssio_14024_count);
116		state_save_register_global(machine, ssio_mute);
117		state_save_register_global_array(machine, ssio_overall);
118		state_save_register_global_2d_array(machine, ssio_duty_cycle);
119		}
120
121		/* Turbo Chip Squeak */
122		if (mcr_sound_config & MCR_TURBO_CHIP_SQUEAK)
123		{
124		turbocs_sound_cpu = machine.device("tcscpu");
125		state_save_register_global(machine, turbocs_status);
126		}
127
128		/* Chip Squeak Deluxe */
129		if (mcr_sound_config & MCR_CHIP_SQUEAK_DELUXE)
130		{
131		csdeluxe_sound_cpu = machine.device("csdcpu");
132		state_save_register_global(machine, csdeluxe_status);
133		}
134
135		/* Sounds Good */
136		if (mcr_sound_config & MCR_SOUNDS_GOOD)
137		{
138		soundsgood_sound_cpu = machine.device("sgcpu");
139		state_save_register_global(machine, soundsgood_status);
140		}
141
142		/* Squawk n Talk */
143		if (mcr_sound_config & MCR_SQUAWK_N_TALK)
144		{
145		squawkntalk_sound_cpu = machine.device("sntcpu");
146		state_save_register_global(machine, squawkntalk_tms_command);
147		state_save_register_global(machine, squawkntalk_tms_strobes);
148		}
149
150		/* Advanced Audio */
151		if (mcr_sound_config & MCR_WILLIAMS_SOUND)
152		williams_cvsd_init(machine);
153		}
154
155
156		void mcr_sound_reset(running_machine &machine)
157		{
158		/* SSIO */
159		if (mcr_sound_config & MCR_SSIO)
160		{
161		ssio_reset_w(machine, 1);
162		ssio_reset_w(machine, 0);
163		}
164
165		/* Turbo Chip Squeak */
166		if (mcr_sound_config & MCR_TURBO_CHIP_SQUEAK)
167		{
168		turbocs_reset_w(machine, 1);
169		turbocs_reset_w(machine, 0);
170		}
171
172		/* Chip Squeak Deluxe */
173		if (mcr_sound_config & MCR_CHIP_SQUEAK_DELUXE)
174		{
175		csdeluxe_reset_w(machine, 1);
176		csdeluxe_reset_w(machine, 0);
177		}
178
179		/* Sounds Good */
180		if (mcr_sound_config & MCR_SOUNDS_GOOD)
181		{
182		soundsgood_reset_w(machine, 1);
183		soundsgood_reset_w(machine, 0);
184		}
185
186		/* Squawk n Talk */
187		if (mcr_sound_config & MCR_SQUAWK_N_TALK)
188		{
189		squawkntalk_reset_w(machine, 1);
190		squawkntalk_reset_w(machine, 0);
191		}
192
193		/* Advanced Audio */
194		if (mcr_sound_config & MCR_WILLIAMS_SOUND)
195		{
196		williams_cvsd_reset_w(machine, 1);
197		williams_cvsd_reset_w(machine, 0);
198		}
199		}
200
201
202
203		/*************************************
204		*
205		*  MCR SSIO communications
206		*
207		*  Z80, 2 AY-8910
208		*
209		*************************************/
210
211		/*
212		AY-8910 modulation:
213
214		Starts with a 16MHz oscillator
215		/2 via 7474 flip-flip @ F11
216
217		This signal clocks the binary counter @ E11 which
218		cascades into the decade counter @ D11. This combo
219		effectively counts from 0-159 and then wraps. The
220		value from these counters is input to an 82S123 PROM,
221		which appears to be standard on all games.
222
223		One bit at a time from this PROM is clocked at a time
224		and the resulting inverted signal becomes a clock for
225		the down counters at F3, F4, F5, F8, F9, and F10. The
226		value in these down counters are reloaded after the 160
227		counts from the binary/decade counter combination.
228
229		When these down counters are loaded, the TC signal is
230		clear, which mutes the voice. When the down counters
231		cross through 0, the TC signal goes high and the 4016
232		multiplexers allow the AY-8910 voice to go through.
233		Thus, writing a 0 to the counters will enable the
234		voice for the longest period of time, while writing
235		a 15 enables it for the shortest period of time.
236		This creates an effective duty cycle for the voice.
237
238		Given that the down counters are reset 50000 times per
239		second (SSIO_CLOCK/2/160), which is above the typical
240		frequency of sound output. So we simply apply a volume
241		adjustment to each voice according to the duty cycle.
242		*/
243		static void ssio_compute_ay8910_modulation(running_machine &machine)
244		{
245		UINT8 *prom = machine.region("proms")->base();
246		int volval;
247
248		/* loop over all possible values of the duty cycle */
249		for (volval = 0; volval < 16; volval++)
250		{
251		int remaining_clocks = volval;
252		int clock, cur = 0, prev = 1;
253
254		/* loop over all the clocks until we run out; look up in the PROM */
255		/* to find out when the next clock should fire */
256		for (clock = 0; clock < 160 && remaining_clocks; clock++)
257		{
258		cur = prom[clock / 8] & (0x80 >> (clock % 8));
259
260		/* check for a high -> low transition */
261		if (cur == 0 && prev != 0)
262		remaining_clocks--;
263
264		prev = cur;
265		}
266
267		/* treat the duty cycle as a volume */
268		ssio_ayvolume_lookup[15-volval] = clock * 100 / 160;
269		}
270		}
271
272		/********* internal interfaces ***********/
273		static INTERRUPT_GEN( ssio_14024_clock )
274		{
275		/*
276		/SINT is generated as follows:
277
278		Starts with a 16MHz oscillator
279		/2 via 7474 flip-flop @ F11
280		/16 via 74161 binary counter @ E11
281		/10 via 74190 decade counter @ D11
282
283		Bit 3 of the decade counter clocks a 14024 7-bit async counter @ C12.
284		This routine is called to clock this 7-bit counter.
285		Bit 6 of the output is inverted and connected to /SINT.
286		*/
287		ssio_14024_count = (ssio_14024_count + 1) & 0x7f;
288
289		/* if the low 5 bits clocked to 0, bit 6 has changed state */
290		if ((ssio_14024_count & 0x3f) == 0)
291		device_set_input_line(device, 0, (ssio_14024_count & 0x40) ? ASSERT_LINE : CLEAR_LINE);
292		}
293
294		READ8_MEMBER(mcr_state::ssio_irq_clear)
295		{
296		/* a read here asynchronously resets the 14024 count, clearing /SINT */
297		ssio_14024_count = 0;
298		device_set_input_line(ssio_sound_cpu, 0, CLEAR_LINE);
299		return 0xff;
300		}
301
302		WRITE8_MEMBER(mcr_state::ssio_status_w)
303		{
304		ssio_status = data;
305		}
306
307		READ8_MEMBER(mcr_state::ssio_data_r)
308		{
309		return ssio_data[offset];
310		}
311
312		static TIMER_CALLBACK( ssio_delayed_data_w )
313		{
314		ssio_data[param >> 8] = param & 0xff;
315		}
316
317		static void ssio_update_volumes(running_machine &machine)
318		{
319		device_t *ay0 = machine.device("ssio.1");
320		device_t *ay1 = machine.device("ssio.2");
321		ay8910_set_volume(ay0, 0, ssio_mute ? 0 : ssio_ayvolume_lookup[ssio_duty_cycle[0][0]]);
322		ay8910_set_volume(ay0, 1, ssio_mute ? 0 : ssio_ayvolume_lookup[ssio_duty_cycle[0][1]]);
323		ay8910_set_volume(ay0, 2, ssio_mute ? 0 : ssio_ayvolume_lookup[ssio_duty_cycle[0][2]]);
324		ay8910_set_volume(ay1, 0, ssio_mute ? 0 : ssio_ayvolume_lookup[ssio_duty_cycle[1][0]]);
325		ay8910_set_volume(ay1, 1, ssio_mute ? 0 : ssio_ayvolume_lookup[ssio_duty_cycle[1][1]]);
326		ay8910_set_volume(ay1, 2, ssio_mute ? 0 : ssio_ayvolume_lookup[ssio_duty_cycle[1][2]]);
327		}
328
329		static WRITE8_DEVICE_HANDLER( ssio_porta0_w )
330		{
331		ssio_duty_cycle[0][0] = data & 15;
332		ssio_duty_cycle[0][1] = data >> 4;
333		ssio_update_volumes(device->machine());
334		}
335
336		static WRITE8_DEVICE_HANDLER( ssio_portb0_w )
337		{
338		ssio_duty_cycle[0][2] = data & 15;
339		ssio_overall[0] = (data >> 4) & 7;
340		ssio_update_volumes(device->machine());
341		}
342
343		static WRITE8_DEVICE_HANDLER( ssio_porta1_w )
344		{
345		ssio_duty_cycle[1][0] = data & 15;
346		ssio_duty_cycle[1][1] = data >> 4;
347		ssio_update_volumes(device->machine());
348		}
349
350		static WRITE8_DEVICE_HANDLER( ssio_portb1_w )
351		{
352		ssio_duty_cycle[1][2] = data & 15;
353		ssio_overall[1] = (data >> 4) & 7;
354		ssio_mute = data & 0x80;
355		ssio_update_volumes(device->machine());
356		}
357
358		/********* external interfaces ***********/
359		WRITE8_MEMBER(mcr_state::ssio_data_w)
360		{
361		machine().scheduler().synchronize(FUNC(ssio_delayed_data_w), (offset << 8) | (data & 0xff));
362		}
363
364		READ8_MEMBER(mcr_state::ssio_status_r)
365		{
366		return ssio_status;
367		}
368
369		void ssio_reset_w(running_machine &machine, int state)
370		{
371		/* going high halts the CPU */
372		if (state)
373		{
374		int i;
375
376		device_set_input_line(ssio_sound_cpu, INPUT_LINE_RESET, ASSERT_LINE);
377
378		/* latches also get reset */
379		for (i = 0; i < 4; i++)
380		ssio_data[i] = 0;
381		ssio_status = 0;
382		ssio_14024_count = 0;
383		}
384		/* going low resets and reactivates the CPU */
385		else
386		device_set_input_line(ssio_sound_cpu, INPUT_LINE_RESET, CLEAR_LINE);
387		}
388
389		READ8_MEMBER(mcr_state::ssio_input_port_r)
390		{
391		static const char *const port[] = { "SSIO.IP0", "SSIO.IP1", "SSIO.IP2", "SSIO.IP3", "SSIO.IP4" };
392		UINT8 result = input_port_read_safe(machine(), port[offset], 0xff);
393		if (!ssio_custom_input[offset].isnull())
394		result = (result & ~ssio_custom_input_mask[offset]) |
395		(ssio_custom_input[offset](*&space, offset, 0xff) & ssio_custom_input_mask[offset]);
396		return result;
397		}
398
399		WRITE8_MEMBER(mcr_state::ssio_output_port_w)
400		{
401		int which = offset >> 2;
402		if (which == 0)
403		mcr_control_port_w(*&space, offset, data);
404		if (!ssio_custom_output[which].isnull())
405		ssio_custom_output[which](*&space, offset, data & ssio_custom_output_mask[which],0xff);
406		}
407
408		void ssio_set_custom_input(int which, int mask, read8_delegate handler)
409		{
410		ssio_custom_input[which] = handler;
411		ssio_custom_input_mask[which] = mask;
412		}
413
414		void ssio_set_custom_output(int which, int mask, write8_delegate handler)
415		{
416		ssio_custom_output[which/4] = handler;
417		ssio_custom_output_mask[which/4] = mask;
418		}
419
420
421		/********* sound interfaces ***********/
422		static const ay8910_interface ssio_ay8910_interface_1 =
423		{
424		AY8910_LEGACY_OUTPUT,
425		AY8910_DEFAULT_LOADS,
426		DEVCB_NULL,
427		DEVCB_NULL,
428		DEVCB_HANDLER(ssio_porta0_w),
429		DEVCB_HANDLER(ssio_portb0_w)
430		};
431
432		static const ay8910_interface ssio_ay8910_interface_2 =
433		{
434		AY8910_LEGACY_OUTPUT,
435		AY8910_DEFAULT_LOADS,
436		DEVCB_NULL,
437		DEVCB_NULL,
438		DEVCB_HANDLER(ssio_porta1_w),
439		DEVCB_HANDLER(ssio_portb1_w)
440		};
441
442
443		/********* memory interfaces ***********/
444
445		/* address map verified from schematics */
446		static ADDRESS_MAP_START( ssio_map, AS_PROGRAM, 8, mcr_state )
447		ADDRESS_MAP_UNMAP_HIGH
448		AM_RANGE(0x0000, 0x3fff) AM_ROM
449		AM_RANGE(0x8000, 0x83ff) AM_MIRROR(0x0c00) AM_RAM
450		AM_RANGE(0x9000, 0x9003) AM_MIRROR(0x0ffc) AM_READ(ssio_data_r)
451		AM_RANGE(0xa000, 0xa000) AM_MIRROR(0x0ffc) AM_DEVWRITE_LEGACY("ssio.1", ay8910_address_w)
452		AM_RANGE(0xa001, 0xa001) AM_MIRROR(0x0ffc) AM_DEVREAD_LEGACY("ssio.1", ay8910_r)
453		AM_RANGE(0xa002, 0xa002) AM_MIRROR(0x0ffc) AM_DEVWRITE_LEGACY("ssio.1", ay8910_data_w)
454		AM_RANGE(0xb000, 0xb000) AM_MIRROR(0x0ffc) AM_DEVWRITE_LEGACY("ssio.2", ay8910_address_w)
455		AM_RANGE(0xb001, 0xb001) AM_MIRROR(0x0ffc) AM_DEVREAD_LEGACY("ssio.2", ay8910_r)
456		AM_RANGE(0xb002, 0xb002) AM_MIRROR(0x0ffc) AM_DEVWRITE_LEGACY("ssio.2", ay8910_data_w)
457		AM_RANGE(0xc000, 0xcfff) AM_READNOP AM_WRITE(ssio_status_w)
458		AM_RANGE(0xd000, 0xdfff) AM_WRITENOP   /* low bit controls yellow LED */
459		AM_RANGE(0xe000, 0xefff) AM_READ(ssio_irq_clear)
460		AM_RANGE(0xf000, 0xffff) AM_READ_PORT("SSIO.DIP")   /* 6 DIP switches */
461		ADDRESS_MAP_END
462
463
464		/********* machine driver ***********/
465		MACHINE_CONFIG_FRAGMENT(mcr_ssio)
466		MCFG_CPU_ADD("ssiocpu", Z80, SSIO_CLOCK/2/4)
467		MCFG_CPU_PROGRAM_MAP(ssio_map)
468		MCFG_CPU_PERIODIC_INT(ssio_14024_clock, SSIO_CLOCK/2/16/10)
469
470		MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
471		MCFG_SOUND_ADD("ssio.1", AY8910, SSIO_CLOCK/2/4)
472		MCFG_SOUND_CONFIG(ssio_ay8910_interface_1)
473		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.33)
474
475		MCFG_SOUND_ADD("ssio.2", AY8910, SSIO_CLOCK/2/4)
476		MCFG_SOUND_CONFIG(ssio_ay8910_interface_2)
477		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.33)
478		MACHINE_CONFIG_END
479
480
481
482		/*************************************
483		*
484		*  Chip Squeak Deluxe communications
485		*
486		*  MC68000, 1 PIA, 10-bit DAC
487		*
488		*************************************/
489
490		/********* internal interfaces ***********/
491		static WRITE8_DEVICE_HANDLER( csdeluxe_porta_w )
492		{
493		dacval = (dacval & ~0x3fc) | (data << 2);
494		dac_signed_data_16_w(device->machine().device("csddac"), dacval << 6);
495		}
496
497		static WRITE8_DEVICE_HANDLER( csdeluxe_portb_w )
498		{
499		UINT8 z_mask = downcast<pia6821_device *>(device)->port_b_z_mask();
500
501		dacval = (dacval & ~0x003) | (data >> 6);
502		dac_signed_data_16_w(device->machine().device("csddac"), dacval << 6);
503
504		if (~z_mask & 0x10)  csdeluxe_status = (csdeluxe_status & ~1) | ((data >> 4) & 1);
505		if (~z_mask & 0x20)  csdeluxe_status = (csdeluxe_status & ~2) | ((data >> 4) & 2);
506		}
507
508		static WRITE_LINE_DEVICE_HANDLER( csdeluxe_irq )
509		{
510		pia6821_device *pia = downcast<pia6821_device *>(device);
511		int combined_state = pia->irq_a_state() | pia->irq_b_state();
512
513		device_set_input_line(csdeluxe_sound_cpu, 4, combined_state ? ASSERT_LINE : CLEAR_LINE);
514		}
515
516		static TIMER_CALLBACK( csdeluxe_delayed_data_w )
517		{
518		pia6821_device *pia = machine.device<pia6821_device>("csdpia");
519
520		pia->portb_w(param & 0x0f);
521		pia->ca1_w(~param & 0x10);
522
523		/* oftentimes games will write one nibble at a time; the sync on this is very */
524		/* important, so we boost the interleave briefly while this happens */
525		machine.scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
526		}
527
528		static READ16_DEVICE_HANDLER( csdeluxe_pia_r )
529		{
530		/* Spy Hunter accesses the MSB; Turbo Tag access via the LSB */
531		/* My guess is that Turbo Tag works through a fluke, whereby the 68000 */
532		/* using the MOVEP instruction outputs the same value on the high and */
533		/* low bytes. */
534		pia6821_device *pia = downcast<pia6821_device *>(device);
535		if (ACCESSING_BITS_8_15)
536		return pia->read_alt(*device->machine().memory().first_space(), offset) << 8;
537		else
538		return pia->read_alt(*device->machine().memory().first_space(), offset);
539		}
540
541		static WRITE16_DEVICE_HANDLER( csdeluxe_pia_w )
542		{
543		pia6821_device *pia = downcast<pia6821_device *>(device);
544		if (ACCESSING_BITS_8_15)
545		pia->write_alt(*device->machine().memory().first_space(), offset, data >> 8);
546		else
547		pia->write_alt(*device->machine().memory().first_space(), offset, data);
548		}
549
550
551		/********* external interfaces ***********/
552		WRITE8_MEMBER(mcr_state::csdeluxe_data_w)
553		{
554		machine().scheduler().synchronize(FUNC(csdeluxe_delayed_data_w), data);
555		}
556
557		READ8_MEMBER(mcr_state::csdeluxe_status_r)
558		{
559		return csdeluxe_status;
560		}
561
562		void csdeluxe_reset_w(running_machine &machine, int state)
563		{
564		device_set_input_line(csdeluxe_sound_cpu, INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
565		}
566
567
568		/********* memory interfaces ***********/
569
570		/* address map determined by PAL; not verified */
571		static ADDRESS_MAP_START( csdeluxe_map, AS_PROGRAM, 16, mcr_state )
572		ADDRESS_MAP_UNMAP_HIGH
573		ADDRESS_MAP_GLOBAL_MASK(0x1ffff)
574		AM_RANGE(0x000000, 0x007fff) AM_ROM
575		AM_RANGE(0x018000, 0x018007) AM_DEVREADWRITE_LEGACY("csdpia", csdeluxe_pia_r, csdeluxe_pia_w)
576		AM_RANGE(0x01c000, 0x01cfff) AM_RAM
577		ADDRESS_MAP_END
578
579
580		/********* PIA interfaces ***********/
581		static const pia6821_interface csdeluxe_pia_intf =
582		{
583		DEVCB_NULL,      /* port A in */
584		DEVCB_NULL,      /* port B in */
585		DEVCB_NULL,      /* line CA1 in */
586		DEVCB_NULL,      /* line CB1 in */
587		DEVCB_NULL,      /* line CA2 in */
588		DEVCB_NULL,      /* line CB2 in */
589		DEVCB_HANDLER(csdeluxe_porta_w),      /* port A out */
590		DEVCB_HANDLER(csdeluxe_portb_w),      /* port B out */
591		DEVCB_NULL,      /* line CA2 out */
592		DEVCB_NULL,      /* port CB2 out */
593		DEVCB_LINE(csdeluxe_irq),      /* IRQA */
594		DEVCB_LINE(csdeluxe_irq)      /* IRQB */
595		};
596
597
598		/********* machine driver ***********/
599		MACHINE_CONFIG_FRAGMENT(chip_squeak_deluxe)
600		MCFG_CPU_ADD("csdcpu", M68000, CSDELUXE_CLOCK/2)
601		MCFG_CPU_PROGRAM_MAP(csdeluxe_map)
602
603		MCFG_PIA6821_ADD("csdpia", csdeluxe_pia_intf)
604
605		MCFG_SPEAKER_STANDARD_MONO("mono")
606		MCFG_SOUND_ADD("csddac", DAC, 0)
607		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
608		MACHINE_CONFIG_END
609
610		MACHINE_CONFIG_FRAGMENT(chip_squeak_deluxe_stereo)
611		MCFG_CPU_ADD("csdcpu", M68000, CSDELUXE_CLOCK/2)
612		MCFG_CPU_PROGRAM_MAP(csdeluxe_map)
613
614		MCFG_PIA6821_ADD("csdpia", csdeluxe_pia_intf)
615
616		MCFG_SOUND_ADD("csddac", DAC, 0)
617		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
618		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
619		MACHINE_CONFIG_END
620
621
622
623		/*************************************
624		*
625		*  MCR Sounds Good communications
626		*
627		*  MC68000, 1 PIA, 10-bit DAC
628		*
629		*************************************/
630
631		/********* internal interfaces ***********/
632		static WRITE8_DEVICE_HANDLER( soundsgood_porta_w )
633		{
634		dacval = (dacval & ~0x3fc) | (data << 2);
635		dac_signed_data_16_w(device->machine().device("sgdac"), dacval << 6);
636		}
637
638		static WRITE8_DEVICE_HANDLER( soundsgood_portb_w )
639		{
640		UINT8 z_mask = downcast<pia6821_device *>(device)->port_b_z_mask();
641
642		dacval = (dacval & ~0x003) | (data >> 6);
643		dac_signed_data_16_w(device->machine().device("sgdac"), dacval << 6);
644
645		if (~z_mask & 0x10)  soundsgood_status = (soundsgood_status & ~1) | ((data >> 4) & 1);
646		if (~z_mask & 0x20)  soundsgood_status = (soundsgood_status & ~2) | ((data >> 4) & 2);
647		}
648
649		static WRITE_LINE_DEVICE_HANDLER( soundsgood_irq )
650		{
651		pia6821_device *pia = downcast<pia6821_device *>(device);
652		int combined_state = pia->irq_a_state() | pia->irq_b_state();
653
654		device_set_input_line(soundsgood_sound_cpu, 4, combined_state ? ASSERT_LINE : CLEAR_LINE);
655		}
656
657		static TIMER_CALLBACK( soundsgood_delayed_data_w )
658		{
659		pia6821_device *pia = machine.device<pia6821_device>("sgpia");
660
661		pia->portb_w((param >> 1) & 0x0f);
662		pia->ca1_w(~param & 0x01);
663
664		/* oftentimes games will write one nibble at a time; the sync on this is very */
665		/* important, so we boost the interleave briefly while this happens */
666		machine.scheduler().boost_interleave(attotime::zero, attotime::from_usec(250));
667		}
668
669
670		/********* external interfaces ***********/
671		WRITE8_MEMBER(mcr_state::soundsgood_data_w)
672		{
673		machine().scheduler().synchronize(FUNC(soundsgood_delayed_data_w), data);
674		}
675
676		READ8_MEMBER(mcr_state::soundsgood_status_r)
677		{
678		return soundsgood_status;
679		}
680
681		void soundsgood_reset_w(running_machine &machine, int state)
682		{
683		//if (state) mame_printf_debug("SG Reset\n");
684		device_set_input_line(soundsgood_sound_cpu, INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
685		}
686
687
688		/********* memory interfaces ***********/
689
690		/* address map determined by PAL; not verified */
691		static ADDRESS_MAP_START( soundsgood_map, AS_PROGRAM, 16, mcr_state )
692		ADDRESS_MAP_UNMAP_HIGH
693		ADDRESS_MAP_GLOBAL_MASK(0x7ffff)
694		AM_RANGE(0x000000, 0x03ffff) AM_ROM
695		AM_RANGE(0x060000, 0x060007) AM_DEVREADWRITE8("sgpia", pia6821_device, read_alt, write_alt, 0xff00)
696		AM_RANGE(0x070000, 0x070fff) AM_RAM
697		ADDRESS_MAP_END
698
699
700		/********* PIA interfaces ***********/
701		static const pia6821_interface soundsgood_pia_intf =
702		{
703		DEVCB_NULL,      /* port A in */
704		DEVCB_NULL,      /* port B in */
705		DEVCB_NULL,      /* line CA1 in */
706		DEVCB_NULL,      /* line CB1 in */
707		DEVCB_NULL,      /* line CA2 in */
708		DEVCB_NULL,      /* line CB2 in */
709		DEVCB_HANDLER(soundsgood_porta_w),      /* port A out */
710		DEVCB_HANDLER(soundsgood_portb_w),      /* port B out */
711		DEVCB_NULL,      /* line CA2 out */
712		DEVCB_NULL,      /* port CB2 out */
713		DEVCB_LINE(soundsgood_irq),      /* IRQA */
714		DEVCB_LINE(soundsgood_irq)      /* IRQB */
715		};
716
717
718		/********* machine driver ***********/
719		MACHINE_CONFIG_FRAGMENT(sounds_good)
720		MCFG_CPU_ADD("sgcpu", M68000, SOUNDSGOOD_CLOCK/2)
721		MCFG_CPU_PROGRAM_MAP(soundsgood_map)
722
723		MCFG_PIA6821_ADD("sgpia", soundsgood_pia_intf)
724
725		MCFG_SPEAKER_STANDARD_MONO("mono")
726		MCFG_SOUND_ADD("sgdac", DAC, 0)
727		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
728		MACHINE_CONFIG_END
729
730
731
732		/*************************************
733		*
734		*  MCR Turbo Chip Squeak communications
735		*
736		*  MC6809, 1 PIA, 10-bit DAC
737		*
738		*************************************/
739
740		/********* internal interfaces ***********/
741		static WRITE8_DEVICE_HANDLER( turbocs_porta_w )
742		{
743		dacval = (dacval & ~0x3fc) | (data << 2);
744		dac_signed_data_16_w(device->machine().device("tcsdac"), dacval << 6);
745		}
746
747		static WRITE8_DEVICE_HANDLER( turbocs_portb_w )
748		{
749		dacval = (dacval & ~0x003) | (data >> 6);
750		dac_signed_data_16_w(device->machine().device("tcsdac"), dacval << 6);
751		turbocs_status = (data >> 4) & 3;
752		}
753
754		static WRITE_LINE_DEVICE_HANDLER( turbocs_irq )
755		{
756		pia6821_device *pia = downcast<pia6821_device *>(device);
757		int combined_state = pia->irq_a_state() | pia->irq_b_state();
758
759		device_set_input_line(turbocs_sound_cpu, M6809_IRQ_LINE, combined_state ? ASSERT_LINE : CLEAR_LINE);
760		}
761
762		static TIMER_CALLBACK( turbocs_delayed_data_w )
763		{
764		pia6821_device *pia = machine.device<pia6821_device>("tcspia");
765
766		pia->portb_w((param >> 1) & 0x0f);
767		pia->ca1_w(~param & 0x01);
768
769		/* oftentimes games will write one nibble at a time; the sync on this is very */
770		/* important, so we boost the interleave briefly while this happens */
771		machine.scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
772		}
773
774
775		/********* external interfaces ***********/
776		WRITE8_MEMBER(mcr_state::turbocs_data_w)
777		{
778		machine().scheduler().synchronize(FUNC(turbocs_delayed_data_w), data);
779		}
780
781		READ8_MEMBER(mcr_state::turbocs_status_r)
782		{
783		return turbocs_status;
784		}
785
786		void turbocs_reset_w(running_machine &machine, int state)
787		{
788		device_set_input_line(turbocs_sound_cpu, INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
789		}
790
791
792		/********* memory interfaces ***********/
793
794		/* address map verified from schematics */
795		static ADDRESS_MAP_START( turbocs_map, AS_PROGRAM, 8, mcr_state )
796		ADDRESS_MAP_UNMAP_HIGH
797		AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0x3800) AM_RAM
798		AM_RANGE(0x4000, 0x4003) AM_MIRROR(0x3ffc) AM_DEVREADWRITE("tcspia", pia6821_device, read_alt, write_alt)
799		AM_RANGE(0x8000, 0xffff) AM_ROM
800		ADDRESS_MAP_END
801
802
803		/********* PIA interfaces ***********/
804		static const pia6821_interface turbocs_pia_intf =
805		{
806		DEVCB_NULL,      /* port A in */
807		DEVCB_NULL,      /* port B in */
808		DEVCB_NULL,      /* line CA1 in */
809		DEVCB_NULL,      /* line CB1 in */
810		DEVCB_NULL,      /* line CA2 in */
811		DEVCB_NULL,      /* line CB2 in */
812		DEVCB_HANDLER(turbocs_porta_w),      /* port A out */
813		DEVCB_HANDLER(turbocs_portb_w),      /* port B out */
814		DEVCB_NULL,      /* line CA2 out */
815		DEVCB_NULL,      /* port CB2 out */
816		DEVCB_LINE(turbocs_irq),      /* IRQA */
817		DEVCB_LINE(turbocs_irq)      /* IRQB */
818		};
819
820
821		/********* machine driver ***********/
822		MACHINE_CONFIG_FRAGMENT(turbo_chip_squeak)
823		MCFG_CPU_ADD("tcscpu", M6809E, TURBOCS_CLOCK)
824		MCFG_CPU_PROGRAM_MAP(turbocs_map)
825
826		MCFG_PIA6821_ADD("tcspia", turbocs_pia_intf)
827
828		MCFG_SPEAKER_STANDARD_MONO("mono")
829		MCFG_SOUND_ADD("tcsdac", DAC, 0)
830		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
831		MACHINE_CONFIG_END
832
833
834
835		/*************************************
836		*
837		*  MCR Squawk n Talk communications
838		*
839		*  MC6802, 2 PIAs, TMS5200, AY8912 (not used), 8-bit DAC (not used)
840		*
841		*************************************/
842
843		/********* internal interfaces ***********/
844		static WRITE8_DEVICE_HANDLER( squawkntalk_porta1_w )
845		{
846		logerror("Write to AY-8912 = %02X\n", data);
847		}
848
849		WRITE8_MEMBER(mcr_state::squawkntalk_dac_w)
850		{
851		logerror("Write to DAC = %02X\n", data);
852		}
853
854		static WRITE8_DEVICE_HANDLER( squawkntalk_porta2_w )
855		{
856		squawkntalk_tms_command = data;
857		}
858
859		static WRITE8_DEVICE_HANDLER( squawkntalk_portb2_w )
860		{
861		device_t *tms = device->machine().device("sntspeech");
862		pia6821_device *pia = downcast<pia6821_device *>(device);
863
864		/* bits 0-1 select read/write strobes on the TMS5200 */
865		data &= 0x03;
866
867		/* write strobe -- pass the current command to the TMS5200 */
868		if (((data ^ squawkntalk_tms_strobes) & 0x02) && !(data & 0x02))
869		{
870		tms5220_data_w(tms, offset, squawkntalk_tms_command);
871
872		/* DoT expects the ready line to transition on a command/write here, so we oblige */
873		pia->ca2_w(1);
874		pia->ca2_w(0);
875		}
876
877		/* read strobe -- read the current status from the TMS5200 */
878		else if (((data ^ squawkntalk_tms_strobes) & 0x01) && !(data & 0x01))
879		{
880		pia->porta_w(tms5220_status_r(tms, offset));
881
882		/* DoT expects the ready line to transition on a command/write here, so we oblige */
883		pia->ca2_w(1);
884		pia->ca2_w(0);
885		}
886
887		/* remember the state */
888		squawkntalk_tms_strobes = data;
889		}
890
891		static WRITE_LINE_DEVICE_HANDLER( squawkntalk_irq )
892		{
893		pia6821_device *pia0 = device->machine().device<pia6821_device>("sntpia0");
894		pia6821_device *pia1 = device->machine().device<pia6821_device>("sntpia1");
895		int combined_state = pia0->irq_a_state() | pia0->irq_b_state() | pia1->irq_a_state() | pia1->irq_b_state();
896
897		device_set_input_line(squawkntalk_sound_cpu, M6800_IRQ_LINE, combined_state ? ASSERT_LINE : CLEAR_LINE);
898		}
899
900		static TIMER_CALLBACK( squawkntalk_delayed_data_w )
901		{
902		pia6821_device *pia0 = machine.device<pia6821_device>("sntpia0");
903
904		pia0->porta_w(~param & 0x0f);
905		pia0->cb1_w(~param & 0x10);
906		}
907
908
909		/********* external interfaces ***********/
910		WRITE8_MEMBER(mcr_state::squawkntalk_data_w)
911		{
912		machine().scheduler().synchronize(FUNC(squawkntalk_delayed_data_w), data);
913		}
914
915		void squawkntalk_reset_w(running_machine &machine, int state)
916		{
917		device_set_input_line(squawkntalk_sound_cpu, INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
918		}
919
920
921		/********* memory interfaces ***********/
922
923		/* address map verified from schematics */
924		/* note that jumpers control the ROM sizes; if these are changed, use the alternate */
925		/* address map below */
926		static ADDRESS_MAP_START( squawkntalk_map, AS_PROGRAM, 8, mcr_state )
927		ADDRESS_MAP_UNMAP_HIGH
928		AM_RANGE(0x0000, 0x007f) AM_RAM      /* internal RAM */
929		AM_RANGE(0x0080, 0x0083) AM_MIRROR(0x4f6c) AM_DEVREADWRITE("sntpia0", pia6821_device, read, write)
930		AM_RANGE(0x0090, 0x0093) AM_MIRROR(0x4f6c) AM_DEVREADWRITE("sntpia1", pia6821_device, read, write)
931		AM_RANGE(0x1000, 0x1fff) AM_MIRROR(0x4000) AM_WRITE(squawkntalk_dac_w)
932		AM_RANGE(0x8000, 0xbfff) AM_MIRROR(0x4000) AM_ROM
933		ADDRESS_MAP_END
934
935		/* alternate address map if the ROM jumpers are changed to support a smaller */
936		/* ROM size of 2k */
937		#ifdef UNUSED_FUNCTION
938		ADDRESS_MAP_START( squawkntalk_alt_map, AS_PROGRAM, 8, mcr_state )
939		ADDRESS_MAP_UNMAP_HIGH
940		AM_RANGE(0x0000, 0x007f) AM_RAM      /* internal RAM */
941		AM_RANGE(0x0080, 0x0083) AM_MIRROR(0x676c) AM_DEVREADWRITE("sntpia0", pia6821_device, read, write)
942		AM_RANGE(0x0090, 0x0093) AM_MIRROR(0x676c) AM_DEVREADWRITE("sntpia1", pia6821_device, read, write)
943		AM_RANGE(0x0800, 0x0fff) AM_MIRROR(0x6000) AM_WRITE(squawkntalk_dac_w)
944		AM_RANGE(0x8000, 0x9fff) AM_MIRROR(0x6000) AM_ROM
945		ADDRESS_MAP_END
946		#endif
947
948
949		/********* PIA interfaces ***********/
950		static const pia6821_interface squawkntalk_pia0_intf =
951		{
952		DEVCB_NULL,      /* port A in */
953		DEVCB_NULL,      /* port B in */
954		DEVCB_NULL,      /* line CA1 in */
955		DEVCB_NULL,      /* line CB1 in */
956		DEVCB_NULL,      /* line CA2 in */
957		DEVCB_NULL,      /* line CB2 in */
958		DEVCB_HANDLER(squawkntalk_porta1_w),      /* port A out */
959		DEVCB_NULL,      /* port B out */
960		DEVCB_NULL,      /* line CA2 out */
961		DEVCB_NULL,      /* port CB2 out */
962		DEVCB_LINE(squawkntalk_irq),   /* IRQA */
963		DEVCB_LINE(squawkntalk_irq)      /* IRQB */
964		};
965
966		static const pia6821_interface squawkntalk_pia1_intf =
967		{
968		DEVCB_NULL,      /* port A in */
969		DEVCB_NULL,      /* port B in */
970		DEVCB_NULL,      /* line CA1 in */
971		DEVCB_NULL,      /* line CB1 in */
972		DEVCB_NULL,      /* line CA2 in */
973		DEVCB_NULL,      /* line CB2 in */
974		DEVCB_HANDLER(squawkntalk_porta2_w),      /* port A out */
975		DEVCB_HANDLER(squawkntalk_portb2_w),      /* port B out */
976		DEVCB_NULL,      /* line CA2 out */
977		DEVCB_NULL,      /* port CB2 out */
978		DEVCB_LINE(squawkntalk_irq),   /* IRQA */
979		DEVCB_LINE(squawkntalk_irq)      /* IRQB */
980		};
981
982
983		/********* machine driver ***********/
984		MACHINE_CONFIG_FRAGMENT(squawk_n_talk)
985		MCFG_CPU_ADD("sntcpu", M6802, SQUAWKTALK_CLOCK)
986		MCFG_CPU_PROGRAM_MAP(squawkntalk_map)
987
988		MCFG_PIA6821_ADD("sntpia0", squawkntalk_pia0_intf)
989		MCFG_PIA6821_ADD("sntpia1", squawkntalk_pia1_intf)
990
991		/* only used on Discs of Tron, which is stereo */
992		MCFG_SOUND_ADD("sntspeech", TMS5200, 640000)
993		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.60)
994		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.60)
995
996		/* the board also supports an AY-8912 and/or an 8-bit DAC, neither of */
997		/* which are populated on the Discs of Tron board */
998		MACHINE_CONFIG_END

src/mame/audio/mcr.h

r14963	r14964
1		/***************************************************************************
2
3		audio/mcr.h
4
5		Functions to emulate general the various MCR sound cards.
6
7		***************************************************************************/
8
9		#include "machine/6821pia.h"
10
11
12
13		/************ Generic MCR routines ***************/
14
15		void mcr_sound_init(running_machine &machine, UINT8 config);
16		void mcr_sound_reset(running_machine &machine);
17
18		void ssio_reset_w(running_machine &machine, int state);
19		void ssio_set_custom_input(int which, int mask, read8_delegate handler);
20		void ssio_set_custom_output(int which, int mask, write8_delegate handler);
21
22		void csdeluxe_reset_w(running_machine &machine, int state);
23
24		void turbocs_reset_w(running_machine &machine, int state);
25
26		void soundsgood_reset_w(running_machine &machine, int state);
27
28		void squawkntalk_reset_w(running_machine &machine, int state);
29
30
31
32		/************ Sound Configuration ***************/
33
34		#define MCR_SSIO            0x01
35		#define MCR_CHIP_SQUEAK_DELUXE   0x02
36		#define MCR_SOUNDS_GOOD         0x04
37		#define MCR_TURBO_CHIP_SQUEAK   0x08
38		#define MCR_SQUAWK_N_TALK      0x10
39		#define MCR_WILLIAMS_SOUND      0x20
40
41
42
43		/************ SSIO input ports ***************/
44
45		#define SSIO_INPUT_PORTS \
46		AM_RANGE(0x00, 0x04) AM_MIRROR(0x18) AM_READ(ssio_input_port_r) \
47		AM_RANGE(0x07, 0x07) AM_MIRROR(0x18) AM_READ(ssio_status_r) \
48		AM_RANGE(0x00, 0x07) AM_MIRROR(0x03) AM_WRITE(ssio_output_port_w) \
49		AM_RANGE(0x1c, 0x1f) AM_WRITE(ssio_data_w)
50
51
52
53		/************ External definitions ***************/
54
55		MACHINE_CONFIG_EXTERN( mcr_ssio );
56		MACHINE_CONFIG_EXTERN( chip_squeak_deluxe );
57		MACHINE_CONFIG_EXTERN( chip_squeak_deluxe_stereo );
58		MACHINE_CONFIG_EXTERN( sounds_good );
59		MACHINE_CONFIG_EXTERN( turbo_chip_squeak );
60		MACHINE_CONFIG_EXTERN( squawk_n_talk );

src/mame/audio/atarijsa.c

r14963	r14964
548	548
549	549	/* update the OKI bank */
550	550	if (oki6295 != NULL)
551		memory_set_bank(space->machine(), "bank12", (space->machine().memory().bank("bank12") & 2) | ((data >> 1) & 1));
	551	memory_set_bank(space->machine(), "bank12", (space->machine().memory().bank("bank12")->entry() & 2) | ((data >> 1) & 1));
552	552
553	553	/* update the bank */
554	554	memcpy(bank_base, &bank_source_data[0x1000 * ((data >> 6) & 3)], 0x1000);
r14963	r14964
572	572
573	573	/* update the OKI bank */
574	574	if (oki6295 != NULL)
575		memory_set_bank(space->machine(), "bank12", (space->machine().memory().bank("bank12") & 1) | ((data >> 3) & 2));
	575	memory_set_bank(space->machine(), "bank12", (space->machine().memory().bank("bank12")->entry() & 1) | ((data >> 3) & 2));
576	576
577	577	/* update the volumes */
578	578	ym2151_volume = ((data >> 1) & 7) * 100 / 7;
r14963	r14964
681	681	if ((data&1) == 0) devtag_reset(space->machine(), "ymsnd");
682	682
683	683	/* update the OKI bank */
684		memory_set_bank(space->machine(), "bank12", (space->machine().memory().bank("bank12") & 2) | ((data >> 1) & 1));
	684	memory_set_bank(space->machine(), "bank12", (space->machine().memory().bank("bank12")->entry() & 2) | ((data >> 1) & 1));
685	685
686	686	/* update the bank */
687	687	memcpy(bank_base, &bank_source_data[0x1000 * ((data >> 6) & 3)], 0x1000);
r14963	r14964
705	705	*/
706	706
707	707	/* update the OKI bank */
708		memory_set_bank(space->machine(), "bank12", (space->machine().memory().bank("bank12") & 1) | ((data >> 3) & 2));
	708	memory_set_bank(space->machine(), "bank12", (space->machine().memory().bank("bank12")->entry() & 1) | ((data >> 3) & 2));
709	709	memory_set_bank(space->machine(), "bank14", data >> 6);
710	710
711	711	/* update the volumes */
r14963	r14964
790	790
791	791	static const ym2151_interface ym2151_config =
792	792	{
793		atarigen_ym2151_irq_gen,
794		ym2151_ctl_w
	793	DEVCB_LINE(atarigen_ym2151_irq_gen),
	794	DEVCB_HANDLER(ym2151_ctl_w)
795	795	};
796	796
797	797

src/mame/audio/seibu.c

r14963	r14964
37	37	#include "sound/3812intf.h"
38	38	#include "sound/2151intf.h"
39	39	#include "sound/2203intf.h"
	40	#include "sound/okiadpcm.h"
40	41	#include "sound/okim6295.h"
41	42
42	43
r14963	r14964
142	143	typedef struct _seibu_adpcm_state seibu_adpcm_state;
143	144	struct _seibu_adpcm_state
144	145	{
145		adpcm_state m_adpcm;
	146	oki_adpcm_state m_adpcm;
146	147	sound_stream *m_stream;
147	148	UINT32 m_current;
148	149	UINT32 m_end;
r14963	r14964
190	191	state->m_playing = 0;
191	192	state->m_stream = device->machine().sound().stream_alloc(*device, 0, 1, device->clock(), state, seibu_adpcm_callback);
192	193	state->m_base = machine.region(intf->rom_region)->base();
193
194		// because legacy device tokens are just allocated as a blob, the constructor for adpcm_state
195		// is not called, so use placement new to force it to set up; when this is converted to a
196		// modern device, we can remove this grossness
197		new(&state->m_adpcm) adpcm_state;
198	194	state->m_adpcm.reset();
199	195	}
200	196
r14963	r14964
474	470
475	471	const ym2151_interface seibu_ym2151_interface =
476	472	{
477		seibu_ym2151_irqhandler
	473	DEVCB_LINE(seibu_ym2151_irqhandler)
478	474	};
479	475
480	476	const ym2203_interface seibu_ym2203_interface =

src/mame/audio/midway.c

r0	r14964
	1	/***************************************************************************
	2
	3	audio/mcr.c
	4
	5	Functions to emulate general the various Midway sound cards.
	6
	7	****************************************************************************
	8
	9	Copyright Aaron Giles
	10	All rights reserved.
	11
	12	Redistribution and use in source and binary forms, with or without
	13	modification, are permitted provided that the following conditions are
	14	met:
	15
	16	* Redistributions of source code must retain the above copyright
	17	notice, this list of conditions and the following disclaimer.
	18	* Redistributions in binary form must reproduce the above copyright
	19	notice, this list of conditions and the following disclaimer in
	20	the documentation and/or other materials provided with the
	21	distribution.
	22	* Neither the name 'MAME' nor the names of its contributors may be
	23	used to endorse or promote products derived from this software
	24	without specific prior written permission.
	25
	26	THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
	27	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	28	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	29	DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
	30	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	31	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	32	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	33	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	34	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	35	IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	36	POSSIBILITY OF SUCH DAMAGE.
	37
	38	***************************************************************************/
	39
	40	#include "emu.h"
	41	#include "audio/williams.h"
	42	#include "includes/mcr.h"
	43	#include "audio/midway.h"
	44
	45
	46
	47	//**************************************************************************
	48	//  CONSTANTS
	49	//**************************************************************************
	50
	51	#define SSIO_CLOCK         XTAL_16MHz
	52	#define CSDELUXE_CLOCK      XTAL_16MHz
	53	#define SOUNDSGOOD_CLOCK   XTAL_16MHz
	54	#define TURBOCS_CLOCK      XTAL_8MHz
	55	#define SQUAWKTALK_CLOCK   XTAL_3_579545MHz
	56
	57
	58
	59	//**************************************************************************
	60	//  GLOBAL VARIABLES
	61	//**************************************************************************
	62
	63	extern const device_type MIDWAY_SSIO = &device_creator<midway_ssio_device>;
	64	extern const device_type MIDWAY_CHIP_SQUEAK_DELUXE = &device_creator<midway_chip_squeak_deluxe_device>;
	65	extern const device_type MIDWAY_SOUNDS_GOOD = &device_creator<midway_sounds_good_device>;
	66	extern const device_type MIDWAY_TURBO_CHIP_SQUEAK = &device_creator<midway_turbo_chip_squeak_device>;
	67	extern const device_type MIDWAY_SQUAWK_N_TALK = &device_creator<midway_squawk_n_talk_device>;
	68
	69
	70
	71	//**************************************************************************
	72	//  SUPER SOUND I/O BOARD (SSIO)
	73	//**************************************************************************
	74
	75	//-------------------------------------------------
	76	//  midway_ssio_device - constructor
	77	//-------------------------------------------------
	78
	79	midway_ssio_device::midway_ssio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	80	: device_t(mconfig, MIDWAY_SSIO, "Midway SSIO Sound Board", "midssio", tag, owner, clock),
	81	device_mixer_interface(mconfig, *this, 2),
	82	m_cpu(*this, "cpu"),
	83	m_ay0(*this, "ay0"),
	84	m_ay1(*this, "ay1"),
	85	m_status(0),
	86	m_14024_count(0),
	87	m_mute(0)
	88	{
	89	memset(m_data, 0, sizeof(m_data));
	90	memset(m_overall, 0, sizeof(m_overall));
	91	memset(m_duty_cycle, 0, sizeof(m_duty_cycle));
	92	memset(m_ayvolume_lookup, 0, sizeof(m_ayvolume_lookup));
	93	memset(m_custom_input_mask, 0, sizeof(m_custom_input_mask));
	94	memset(m_custom_output_mask, 0, sizeof(m_custom_output_mask));
	95	}
	96
	97
	98	//-------------------------------------------------
	99	//  read - return the status value
	100	//-------------------------------------------------
	101
	102	READ8_MEMBER(midway_ssio_device::read)
	103	{
	104	return m_status;
	105	}
	106
	107
	108	//-------------------------------------------------
	109	//  write - handle an external write to one of the
	110	//   input latches
	111	//-------------------------------------------------
	112
	113	WRITE8_MEMBER(midway_ssio_device::write)
	114	{
	115	synchronize(0, (offset << 8) | (data & 0xff));
	116	}
	117
	118
	119	//-------------------------------------------------
	120	//  reset_write - write to the reset line
	121	//-------------------------------------------------
	122
	123	WRITE_LINE_MEMBER(midway_ssio_device::reset_write)
	124	{
	125	// going high halts the CPU
	126	if (state)
	127	{
	128	device_reset();
	129	m_cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
	130	}
	131
	132	// going low resets and reactivates the CPU
	133	else
	134	m_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
	135	}
	136
	137
	138	//-------------------------------------------------
	139	//  ioport_read - read from one of the I/O ports
	140	//  on the device
	141	//-------------------------------------------------
	142
	143	READ8_MEMBER(midway_ssio_device::ioport_read)
	144	{
	145	static const char *const port[] = { "IP0", "IP1", "IP2", "IP3", "IP4" };
	146	astring tempstr;
	147	UINT8 result = input_port_read_safe(machine(), subtag(tempstr, port[offset]), 0xff);
	148	if (!m_custom_input[offset].isnull())
	149	result = (result & ~m_custom_input_mask[offset]) |
	150	(m_custom_input[offset](space, offset, 0xff) & m_custom_input_mask[offset]);
	151	return result;
	152	}
	153
	154
	155	//-------------------------------------------------
	156	//  ioport_write - write to one of the I/O ports
	157	//  on the device
	158	//-------------------------------------------------
	159
	160	WRITE8_MEMBER(midway_ssio_device::ioport_write)
	161	{
	162	int which = offset >> 2;
	163	if (!m_custom_output[which].isnull())
	164	m_custom_output[which](space, offset, data & m_custom_output_mask[which], 0xff);
	165	}
	166
	167
	168	//-------------------------------------------------
	169	//  set_custom_input - configure a custom port
	170	//   reader
	171	//-------------------------------------------------
	172
	173	void midway_ssio_device::set_custom_input(int which, UINT8 mask, read8_delegate handler)
	174	{
	175	m_custom_input[which] = handler;
	176	m_custom_input_mask[which] = mask;
	177	}
	178
	179
	180	//-------------------------------------------------
	181	//  set_custom_output - configure a custom port
	182	//   writer
	183	//-------------------------------------------------
	184
	185	void midway_ssio_device::set_custom_output(int which, UINT8 mask, write8_delegate handler)
	186	{
	187	m_custom_output[which/4] = handler;
	188	m_custom_output_mask[which/4] = mask;
	189	}
	190
	191
	192	//-------------------------------------------------
	193	//  compute_ay8910_modulation - precompute
	194	//   volume modulation tables based on the duty
	195	//   cycle described by the PROMs
	196	//-------------------------------------------------
	197
	198	void midway_ssio_device::compute_ay8910_modulation()
	199	{
	200	//
	201	// AY-8910 modulation:
	202	//
	203	// Starts with a 16MHz oscillator
	204	//   /2 via 7474 flip-flip @ F11
	205	//
	206	// This signal clocks the binary counter @ E11 which
	207	// cascades into the decade counter @ D11. This combo
	208	// effectively counts from 0-159 and then wraps. The
	209	// value from these counters is input to an 82S123 PROM,
	210	// which appears to be standard on all games.
	211	//
	212	// One bit at a time from this PROM is clocked at a time
	213	// and the resulting inverted signal becomes a clock for
	214	// the down counters at F3, F4, F5, F8, F9, and F10. The
	215	// value in these down counters are reloaded after the 160
	216	// counts from the binary/decade counter combination.
	217	//
	218	// When these down counters are loaded, the TC signal is
	219	// clear, which mutes the voice. When the down counters
	220	// cross through 0, the TC signal goes high and the 4016
	221	// multiplexers allow the AY-8910 voice to go through.
	222	// Thus, writing a 0 to the counters will enable the
	223	// voice for the longest period of time, while writing
	224	// a 15 enables it for the shortest period of time.
	225	// This creates an effective duty cycle for the voice.
	226	//
	227	// Given that the down counters are reset 50000 times per
	228	// second (SSIO_CLOCK/2/160), which is above the typical
	229	// frequency of sound output. So we simply apply a volume
	230	// adjustment to each voice according to the duty cycle.
	231	//
	232
	233	// loop over all possible values of the duty cycle
	234	UINT8 *prom = machine().region("proms")->base();
	235	for (int volval = 0; volval < 16; volval++)
	236	{
	237	// loop over all the clocks until we run out; look up in the PROM
	238	// to find out when the next clock should fire
	239	int remaining_clocks = volval;
	240	int cur = 0, prev = 1;
	241	int curclock;
	242	for (curclock = 0; curclock < 160 && remaining_clocks; curclock++)
	243	{
	244	cur = prom[curclock / 8] & (0x80 >> (curclock % 8));
	245
	246	// check for a high -> low transition
	247	if (cur == 0 && prev != 0)
	248	remaining_clocks--;
	249
	250	prev = cur;
	251	}
	252
	253	// treat the duty cycle as a volume
	254	m_ayvolume_lookup[15 - volval] = curclock * 100 / 160;
	255	}
	256	}
	257
	258
	259	//-------------------------------------------------
	260	//  clock_14024 - periodic timer to clock the
	261	//   7-bit async counter at C12
	262	//-------------------------------------------------
	263
	264	INTERRUPT_GEN_MEMBER(midway_ssio_device::clock_14024)
	265	{
	266	//
	267	//  /SINT is generated as follows:
	268	//
	269	//  Starts with a 16MHz oscillator
	270	//      /2 via 7474 flip-flop @ F11
	271	//      /16 via 74161 binary counter @ E11
	272	//      /10 via 74190 decade counter @ D11
	273	//
	274	//  Bit 3 of the decade counter clocks a 14024 7-bit async counter @ C12.
	275	//  This routine is called to clock this 7-bit counter.
	276	//  Bit 6 of the output is inverted and connected to /SINT.
	277	//
	278	m_14024_count = (m_14024_count + 1) & 0x7f;
	279
	280	// if the low 5 bits clocked to 0, bit 6 has changed state
	281	if ((m_14024_count & 0x3f) == 0)
	282	m_cpu->set_input_line(0, (m_14024_count & 0x40) ? ASSERT_LINE : CLEAR_LINE);
	283	}
	284
	285
	286	//-------------------------------------------------
	287	//  irq_clear - reset the IRQ state and 14024 count
	288	//-------------------------------------------------
	289
	290	READ8_MEMBER(midway_ssio_device::irq_clear)
	291	{
	292	// a read here asynchronously resets the 14024 count, clearing /SINT
	293	m_14024_count = 0;
	294	m_cpu->set_input_line(0, CLEAR_LINE);
	295	return 0xff;
	296	}
	297
	298
	299	//-------------------------------------------------
	300	//  status_w - set the outgoing status value
	301	//-------------------------------------------------
	302
	303	WRITE8_MEMBER(midway_ssio_device::status_w)
	304	{
	305	m_status = data;
	306	}
	307
	308
	309	//-------------------------------------------------
	310	//  data_r - read incoming data latches
	311	//-------------------------------------------------
	312
	313	READ8_MEMBER(midway_ssio_device::data_r)
	314	{
	315	return m_data[offset];
	316	}
	317
	318
	319	//-------------------------------------------------
	320	//  porta0_w - handle writes to AY-8910 #0 port A
	321	//-------------------------------------------------
	322
	323	WRITE8_MEMBER(midway_ssio_device::porta0_w)
	324	{
	325	m_duty_cycle[0][0] = data & 15;
	326	m_duty_cycle[0][1] = data >> 4;
	327	update_volumes();
	328	}
	329
	330
	331	//-------------------------------------------------
	332	//  portb0_w - handle writes to AY-8910 #0 port B
	333	//-------------------------------------------------
	334
	335	WRITE8_MEMBER(midway_ssio_device::portb0_w)
	336	{
	337	m_duty_cycle[0][2] = data & 15;
	338	m_overall[0] = (data >> 4) & 7;
	339	update_volumes();
	340	}
	341
	342
	343	//-------------------------------------------------
	344	//  porta1_w - handle writes to AY-8910 #1 port A
	345	//-------------------------------------------------
	346
	347	WRITE8_MEMBER(midway_ssio_device::porta1_w)
	348	{
	349	m_duty_cycle[1][0] = data & 15;
	350	m_duty_cycle[1][1] = data >> 4;
	351	update_volumes();
	352	}
	353
	354
	355	//-------------------------------------------------
	356	//  portb1_w - handle writes to AY-8910 #1 port B
	357	//-------------------------------------------------
	358
	359	WRITE8_MEMBER(midway_ssio_device::portb1_w)
	360	{
	361	m_duty_cycle[1][2] = data & 15;
	362	m_overall[1] = (data >> 4) & 7;
	363	m_mute = data & 0x80;
	364	update_volumes();
	365	}
	366
	367
	368	//-------------------------------------------------
	369	//  update_volumes - update the volumes of each
	370	//   AY-8910 channel based on modulation and mute
	371	//-------------------------------------------------
	372
	373	void midway_ssio_device::update_volumes()
	374	{
	375	ay8910_set_volume(m_ay0, 0, m_mute ? 0 : m_ayvolume_lookup[m_duty_cycle[0][0]]);
	376	ay8910_set_volume(m_ay0, 1, m_mute ? 0 : m_ayvolume_lookup[m_duty_cycle[0][1]]);
	377	ay8910_set_volume(m_ay0, 2, m_mute ? 0 : m_ayvolume_lookup[m_duty_cycle[0][2]]);
	378	ay8910_set_volume(m_ay1, 0, m_mute ? 0 : m_ayvolume_lookup[m_duty_cycle[1][0]]);
	379	ay8910_set_volume(m_ay1, 1, m_mute ? 0 : m_ayvolume_lookup[m_duty_cycle[1][1]]);
	380	ay8910_set_volume(m_ay1, 2, m_mute ? 0 : m_ayvolume_lookup[m_duty_cycle[1][2]]);
	381	}
	382
	383
	384	//-------------------------------------------------
	385	//  AY-8910 interfaces
	386	//-------------------------------------------------
	387
	388	static const ay8910_interface ssio_ay8910_interface_1 =
	389	{
	390	AY8910_LEGACY_OUTPUT,
	391	AY8910_DEFAULT_LOADS,
	392	DEVCB_NULL,
	393	DEVCB_NULL,
	394	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_ssio_device, porta0_w),
	395	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_ssio_device, portb0_w)
	396	};
	397
	398	static const ay8910_interface ssio_ay8910_interface_2 =
	399	{
	400	AY8910_LEGACY_OUTPUT,
	401	AY8910_DEFAULT_LOADS,
	402	DEVCB_NULL,
	403	DEVCB_NULL,
	404	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_ssio_device, porta1_w),
	405	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_ssio_device, portb1_w)
	406	};
	407
	408
	409	//-------------------------------------------------
	410	//  audio CPU map
	411	//-------------------------------------------------
	412
	413	// address map verified from schematics
	414	static ADDRESS_MAP_START( ssio_map, AS_PROGRAM, 8, midway_ssio_device )
	415	ADDRESS_MAP_UNMAP_HIGH
	416	AM_RANGE(0x0000, 0x3fff) AM_ROM
	417	AM_RANGE(0x8000, 0x83ff) AM_MIRROR(0x0c00) AM_RAM
	418	AM_RANGE(0x9000, 0x9003) AM_MIRROR(0x0ffc) AM_READ(data_r)
	419	AM_RANGE(0xa000, 0xa000) AM_MIRROR(0x0ffc) AM_DEVWRITE_LEGACY("ay0", ay8910_address_w)
	420	AM_RANGE(0xa001, 0xa001) AM_MIRROR(0x0ffc) AM_DEVREAD_LEGACY("ay0", ay8910_r)
	421	AM_RANGE(0xa002, 0xa002) AM_MIRROR(0x0ffc) AM_DEVWRITE_LEGACY("ay0", ay8910_data_w)
	422	AM_RANGE(0xb000, 0xb000) AM_MIRROR(0x0ffc) AM_DEVWRITE_LEGACY("ay1", ay8910_address_w)
	423	AM_RANGE(0xb001, 0xb001) AM_MIRROR(0x0ffc) AM_DEVREAD_LEGACY("ay1", ay8910_r)
	424	AM_RANGE(0xb002, 0xb002) AM_MIRROR(0x0ffc) AM_DEVWRITE_LEGACY("ay1", ay8910_data_w)
	425	AM_RANGE(0xc000, 0xcfff) AM_READNOP AM_WRITE(status_w)
	426	AM_RANGE(0xd000, 0xdfff) AM_WRITENOP   // low bit controls yellow LED
	427	AM_RANGE(0xe000, 0xefff) AM_READ(irq_clear)
	428	AM_RANGE(0xf000, 0xffff) AM_READ_PORT("DIP")   // 6 DIP switches
	429	ADDRESS_MAP_END
	430
	431
	432	//-------------------------------------------------
	433	//  machine configuration
	434	//-------------------------------------------------
	435
	436	static MACHINE_CONFIG_FRAGMENT( midway_ssio )
	437	MCFG_CPU_ADD("cpu", Z80, SSIO_CLOCK/2/4)
	438	MCFG_CPU_PROGRAM_MAP(ssio_map)
	439	MCFG_DEVICE_PERIODIC_INT_DEVICE(DEVICE_SELF_OWNER, midway_ssio_device, clock_14024, SSIO_CLOCK/2/16/10)
	440
	441	MCFG_SOUND_ADD("ay0", AY8910, SSIO_CLOCK/2/4)
	442	MCFG_SOUND_CONFIG(ssio_ay8910_interface_1)
	443	MCFG_MIXER_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.33, 0)
	444
	445	MCFG_SOUND_ADD("ay1", AY8910, SSIO_CLOCK/2/4)
	446	MCFG_SOUND_CONFIG(ssio_ay8910_interface_2)
	447	MCFG_MIXER_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.33, 1)
	448	MACHINE_CONFIG_END
	449
	450
	451	//-------------------------------------------------
	452	//  device_mconfig_additions - return a pointer to
	453	//  the device's machine fragment
	454	//-------------------------------------------------
	455
	456	machine_config_constructor midway_ssio_device::device_mconfig_additions() const
	457	{
	458	return MACHINE_CONFIG_NAME( midway_ssio );
	459	}
	460
	461
	462	//-------------------------------------------------
	463	//  device_input_ports - return a pointer to
	464	//  the device's I/O ports
	465	//-------------------------------------------------
	466
	467	ioport_constructor midway_ssio_device::device_input_ports() const
	468	{
	469	return NULL;
	470	//   return INPUT_PORTS_NAME( midway_ssio );
	471	}
	472
	473
	474	//-------------------------------------------------
	475	//  device_start - device-specific startup
	476	//-------------------------------------------------
	477
	478	void midway_ssio_device::device_start()
	479	{
	480	compute_ay8910_modulation();
	481	save_item(NAME(m_data));
	482	save_item(NAME(m_status));
	483	save_item(NAME(m_14024_count));
	484	save_item(NAME(m_mute));
	485	save_item(NAME(m_overall));
	486	save_item(NAME(m_duty_cycle));
	487	}
	488
	489
	490	//-------------------------------------------------
	491	//  device_reset - device-specific reset
	492	//-------------------------------------------------
	493
	494	void midway_ssio_device::device_reset()
	495	{
	496	// latches also get reset
	497	memset(m_data, 0, sizeof(m_data));
	498	m_status = 0;
	499	m_14024_count = 0;
	500	}
	501
	502
	503	//-------------------------------------------------
	504	//  device_timer - timer callbacks
	505	//-------------------------------------------------
	506
	507	void midway_ssio_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	508	{
	509	m_data[param >> 8] = param & 0xff;
	510	}
	511
	512
	513
	514	//**************************************************************************
	515	//  CHIP SQUEAK DELUXE BOARD
	516	//**************************************************************************
	517
	518	//-------------------------------------------------
	519	//  midway_chip_squeak_deluxe_device - constructor
	520	//-------------------------------------------------
	521
	522	midway_chip_squeak_deluxe_device::midway_chip_squeak_deluxe_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	523	: device_t(mconfig, MIDWAY_CHIP_SQUEAK_DELUXE, "Midway Chip Squeak Deluxe Sound Board", "midcsd", tag, owner, clock),
	524	device_mixer_interface(mconfig, *this),
	525	m_cpu(*this, "cpu"),
	526	m_pia(*this, "pia"),
	527	m_dac(*this, "dac"),
	528	m_status(0),
	529	m_dacval(0)
	530	{
	531	}
	532
	533
	534	//-------------------------------------------------
	535	//  read - return the status value
	536	//-------------------------------------------------
	537
	538	READ8_MEMBER(midway_chip_squeak_deluxe_device::read)
	539	{
	540	return m_status;
	541	}
	542
	543
	544	//-------------------------------------------------
	545	//  write - handle an external write to the input
	546	//   latch
	547	//-------------------------------------------------
	548
	549	WRITE8_MEMBER(midway_chip_squeak_deluxe_device::write)
	550	{
	551	synchronize(0, data);
	552	}
	553
	554
	555	//-------------------------------------------------
	556	//  reset_write - write to the reset line
	557	//-------------------------------------------------
	558
	559	WRITE_LINE_MEMBER(midway_chip_squeak_deluxe_device::reset_write)
	560	{
	561	m_cpu->set_input_line(INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
	562	}
	563
	564
	565	//-------------------------------------------------
	566	//  porta_w - PIA port A writes
	567	//-------------------------------------------------
	568
	569	WRITE8_MEMBER(midway_chip_squeak_deluxe_device::porta_w)
	570	{
	571	m_dacval = (m_dacval & ~0x3fc) | (data << 2);
	572	dac_signed_data_16_w(m_dac, m_dacval << 6);
	573	}
	574
	575
	576	//-------------------------------------------------
	577	//  portb_w - PIA port B writes
	578	//-------------------------------------------------
	579
	580	WRITE8_MEMBER(midway_chip_squeak_deluxe_device::portb_w)
	581	{
	582	m_dacval = (m_dacval & ~0x003) | (data >> 6);
	583	dac_signed_data_16_w(m_dac, m_dacval << 6);
	584
	585	UINT8 z_mask = m_pia->port_b_z_mask();
	586	if (~z_mask & 0x10)  m_status = (m_status & ~1) | ((data >> 4) & 1);
	587	if (~z_mask & 0x20)  m_status = (m_status & ~2) | ((data >> 4) & 2);
	588	}
	589
	590
	591	//-------------------------------------------------
	592	//  irq_w - IRQ line state changes
	593	//-------------------------------------------------
	594
	595	WRITE_LINE_MEMBER(midway_chip_squeak_deluxe_device::irq_w)
	596	{
	597	int combined_state = m_pia->irq_a_state() | m_pia->irq_b_state();
	598	m_cpu->set_input_line(4, combined_state ? ASSERT_LINE : CLEAR_LINE);
	599	}
	600
	601
	602	//-------------------------------------------------
	603	//  pia_r - PIA read access
	604	//-------------------------------------------------
	605
	606	READ16_MEMBER(midway_chip_squeak_deluxe_device::pia_r)
	607	{
	608	// Spy Hunter accesses the MSB; Turbo Tag access via the LSB
	609	// My guess is that Turbo Tag works through a fluke, whereby the 68000
	610	// using the MOVEP instruction outputs the same value on the high and
	611	// low bytes.
	612	if (ACCESSING_BITS_8_15)
	613	return m_pia->read_alt(space, offset) << 8;
	614	else
	615	return m_pia->read_alt(space, offset);
	616	}
	617
	618
	619	//-------------------------------------------------
	620	//  pia_w - PIA write access
	621	//-------------------------------------------------
	622
	623	WRITE16_MEMBER(midway_chip_squeak_deluxe_device::pia_w)
	624	{
	625	if (ACCESSING_BITS_8_15)
	626	m_pia->write_alt(space, offset, data >> 8);
	627	else
	628	m_pia->write_alt(space, offset, data);
	629	}
	630
	631
	632	//-------------------------------------------------
	633	//  audio CPU map
	634	//-------------------------------------------------
	635
	636	// address map determined by PAL; not verified
	637	static ADDRESS_MAP_START( csdeluxe_map, AS_PROGRAM, 16, midway_chip_squeak_deluxe_device )
	638	ADDRESS_MAP_UNMAP_HIGH
	639	ADDRESS_MAP_GLOBAL_MASK(0x1ffff)
	640	AM_RANGE(0x000000, 0x007fff) AM_ROM
	641	AM_RANGE(0x018000, 0x018007) AM_READWRITE(pia_r, pia_w)
	642	AM_RANGE(0x01c000, 0x01cfff) AM_RAM
	643	ADDRESS_MAP_END
	644
	645
	646	//-------------------------------------------------
	647	//  6821 PIA interface
	648	//-------------------------------------------------
	649
	650	static const pia6821_interface csdeluxe_pia_intf =
	651	{
	652	DEVCB_NULL,      // port A in
	653	DEVCB_NULL,      // port B in
	654	DEVCB_NULL,      // line CA1 in
	655	DEVCB_NULL,      // line CB1 in
	656	DEVCB_NULL,      // line CA2 in
	657	DEVCB_NULL,      // line CB2 in
	658	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_chip_squeak_deluxe_device, porta_w),   // port A out
	659	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_chip_squeak_deluxe_device, portb_w),   // port B out
	660	DEVCB_NULL,      // line CA2 out
	661	DEVCB_NULL,      // port CB2 out
	662	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_chip_squeak_deluxe_device, irq_w),   // IRQA
	663	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_chip_squeak_deluxe_device, irq_w)   // IRQB
	664	};
	665
	666
	667	//-------------------------------------------------
	668	//  machine configuration
	669	//-------------------------------------------------
	670
	671	static MACHINE_CONFIG_FRAGMENT(midway_chip_squeak_deluxe)
	672	MCFG_CPU_ADD("cpu", M68000, CSDELUXE_CLOCK/2)
	673	MCFG_CPU_PROGRAM_MAP(csdeluxe_map)
	674
	675	MCFG_PIA6821_ADD("pia", csdeluxe_pia_intf)
	676
	677	MCFG_SOUND_ADD("dac", DAC, 0)
	678	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 1.0)
	679	MACHINE_CONFIG_END
	680
	681
	682	//-------------------------------------------------
	683	//  device_mconfig_additions - return a pointer to
	684	//  the device's machine fragment
	685	//-------------------------------------------------
	686
	687	machine_config_constructor midway_chip_squeak_deluxe_device::device_mconfig_additions() const
	688	{
	689	return MACHINE_CONFIG_NAME( midway_chip_squeak_deluxe );
	690	}
	691
	692
	693	//-------------------------------------------------
	694	//  device_start - device-specific startup
	695	//-------------------------------------------------
	696
	697	void midway_chip_squeak_deluxe_device::device_start()
	698	{
	699	save_item(NAME(m_status));
	700	save_item(NAME(m_dacval));
	701	}
	702
	703
	704	//-------------------------------------------------
	705	//  device_reset - device-specific reset
	706	//-------------------------------------------------
	707
	708	void midway_chip_squeak_deluxe_device::device_reset()
	709	{
	710	}
	711
	712
	713	//-------------------------------------------------
	714	//  device_timer - timer callbacks
	715	//-------------------------------------------------
	716
	717	void midway_chip_squeak_deluxe_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	718	{
	719	m_pia->portb_w(param & 0x0f);
	720	m_pia->ca1_w(~param & 0x10);
	721
	722	// oftentimes games will write one nibble at a time; the sync on this is very
	723	// important, so we boost the interleave briefly while this happens
	724	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
	725	}
	726
	727
	728
	729	//**************************************************************************
	730	//  SOUNDS GOOD BOARD
	731	//**************************************************************************
	732
	733	//-------------------------------------------------
	734	//  midway_sounds_good_device - constructor
	735	//-------------------------------------------------
	736
	737	midway_sounds_good_device::midway_sounds_good_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	738	: device_t(mconfig, MIDWAY_SOUNDS_GOOD, "Midway Sounds Good Sound Board", "midsg", tag, owner, clock),
	739	device_mixer_interface(mconfig, *this),
	740	m_cpu(*this, "cpu"),
	741	m_pia(*this, "pia"),
	742	m_dac(*this, "dac"),
	743	m_status(0),
	744	m_dacval(0)
	745	{
	746	}
	747
	748
	749	//-------------------------------------------------
	750	//  read - return the status value
	751	//-------------------------------------------------
	752
	753	READ8_MEMBER(midway_sounds_good_device::read)
	754	{
	755	return m_status;
	756	}
	757
	758
	759	//-------------------------------------------------
	760	//  write - handle an external write to the input
	761	//   latch
	762	//-------------------------------------------------
	763
	764	WRITE8_MEMBER(midway_sounds_good_device::write)
	765	{
	766	synchronize(0, data);
	767	}
	768
	769
	770	//-------------------------------------------------
	771	//  reset_write - write to the reset line
	772	//-------------------------------------------------
	773
	774	WRITE_LINE_MEMBER(midway_sounds_good_device::reset_write)
	775	{
	776	//if (state) mame_printf_debug("SG Reset\n");
	777	m_cpu->set_input_line(INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
	778	}
	779
	780
	781	//-------------------------------------------------
	782	//  porta_w - PIA port A writes
	783	//-------------------------------------------------
	784
	785	WRITE8_MEMBER(midway_sounds_good_device::porta_w)
	786	{
	787	m_dacval = (m_dacval & ~0x3fc) | (data << 2);
	788	dac_signed_data_16_w(m_dac, m_dacval << 6);
	789	}
	790
	791
	792	//-------------------------------------------------
	793	//  portb_w - PIA port B writes
	794	//-------------------------------------------------
	795
	796	WRITE8_MEMBER(midway_sounds_good_device::portb_w)
	797	{
	798	UINT8 z_mask = m_pia->port_b_z_mask();
	799
	800	m_dacval = (m_dacval & ~0x003) | (data >> 6);
	801	dac_signed_data_16_w(m_dac, m_dacval << 6);
	802
	803	if (~z_mask & 0x10)  m_status = (m_status & ~1) | ((data >> 4) & 1);
	804	if (~z_mask & 0x20)  m_status = (m_status & ~2) | ((data >> 4) & 2);
	805	}
	806
	807
	808	//-------------------------------------------------
	809	//  irq_w - IRQ line state changes
	810	//-------------------------------------------------
	811
	812	WRITE_LINE_MEMBER(midway_sounds_good_device::irq_w)
	813	{
	814	int combined_state = m_pia->irq_a_state() | m_pia->irq_b_state();
	815	m_cpu->set_input_line(4, combined_state ? ASSERT_LINE : CLEAR_LINE);
	816	}
	817
	818
	819	//-------------------------------------------------
	820	//  audio CPU map
	821	//-------------------------------------------------
	822
	823	// address map determined by PAL; not verified
	824	static ADDRESS_MAP_START( soundsgood_map, AS_PROGRAM, 16, midway_sounds_good_device )
	825	ADDRESS_MAP_UNMAP_HIGH
	826	ADDRESS_MAP_GLOBAL_MASK(0x7ffff)
	827	AM_RANGE(0x000000, 0x03ffff) AM_ROM
	828	AM_RANGE(0x060000, 0x060007) AM_DEVREADWRITE8("pia", pia6821_device, read_alt, write_alt, 0xff00)
	829	AM_RANGE(0x070000, 0x070fff) AM_RAM
	830	ADDRESS_MAP_END
	831
	832
	833	//-------------------------------------------------
	834	//  6821 PIA interface
	835	//-------------------------------------------------
	836
	837	static const pia6821_interface soundsgood_pia_intf =
	838	{
	839	DEVCB_NULL,      // port A in
	840	DEVCB_NULL,      // port B in
	841	DEVCB_NULL,      // line CA1 in
	842	DEVCB_NULL,      // line CB1 in
	843	DEVCB_NULL,      // line CA2 in
	844	DEVCB_NULL,      // line CB2 in
	845	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_sounds_good_device, porta_w),   // port A out
	846	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_sounds_good_device, portb_w),   // port B out
	847	DEVCB_NULL,      // line CA2 out
	848	DEVCB_NULL,      // port CB2 out
	849	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_sounds_good_device, irq_w),   // IRQA
	850	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_sounds_good_device, irq_w)   // IRQB
	851	};
	852
	853
	854	//-------------------------------------------------
	855	//  machine configuration
	856	//-------------------------------------------------
	857
	858	static MACHINE_CONFIG_FRAGMENT(midway_sounds_good)
	859	MCFG_CPU_ADD("cpu", M68000, SOUNDSGOOD_CLOCK/2)
	860	MCFG_CPU_PROGRAM_MAP(soundsgood_map)
	861
	862	MCFG_PIA6821_ADD("pia", soundsgood_pia_intf)
	863
	864	MCFG_SOUND_ADD("dac", DAC, 0)
	865	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 1.0)
	866	MACHINE_CONFIG_END
	867
	868
	869	//-------------------------------------------------
	870	//  device_mconfig_additions - return a pointer to
	871	//  the device's machine fragment
	872	//-------------------------------------------------
	873
	874	machine_config_constructor midway_sounds_good_device::device_mconfig_additions() const
	875	{
	876	return MACHINE_CONFIG_NAME( midway_sounds_good );
	877	}
	878
	879
	880	//-------------------------------------------------
	881	//  device_start - device-specific startup
	882	//-------------------------------------------------
	883
	884	void midway_sounds_good_device::device_start()
	885	{
	886	save_item(NAME(m_status));
	887	save_item(NAME(m_dacval));
	888	}
	889
	890
	891	//-------------------------------------------------
	892	//  device_reset - device-specific reset
	893	//-------------------------------------------------
	894
	895	void midway_sounds_good_device::device_reset()
	896	{
	897	}
	898
	899
	900	//-------------------------------------------------
	901	//  device_timer - timer callbacks
	902	//-------------------------------------------------
	903
	904	void midway_sounds_good_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	905	{
	906	m_pia->portb_w((param >> 1) & 0x0f);
	907	m_pia->ca1_w(~param & 0x01);
	908
	909	// oftentimes games will write one nibble at a time; the sync on this is very
	910	// important, so we boost the interleave briefly while this happens
	911	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(250));
	912	}
	913
	914
	915
	916	//**************************************************************************
	917	//  TURBO CHIP SQUEAK BOARD
	918	//**************************************************************************
	919
	920	//-------------------------------------------------
	921	//  midway_turbo_chip_squeak_device - constructor
	922	//-------------------------------------------------
	923
	924	midway_turbo_chip_squeak_device::midway_turbo_chip_squeak_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	925	: device_t(mconfig, MIDWAY_TURBO_CHIP_SQUEAK, "Midway Turbo Chip Squeak Sound Board", "midtcs", tag, owner, clock),
	926	device_mixer_interface(mconfig, *this),
	927	m_cpu(*this, "cpu"),
	928	m_pia(*this, "pia"),
	929	m_dac(*this, "dac"),
	930	m_status(0),
	931	m_dacval(0)
	932	{
	933	}
	934
	935
	936	//-------------------------------------------------
	937	//  read - return the status value
	938	//-------------------------------------------------
	939
	940	READ8_MEMBER(midway_turbo_chip_squeak_device::read)
	941	{
	942	return m_status;
	943	}
	944
	945
	946	//-------------------------------------------------
	947	//  write - handle an external write to the input
	948	//   latch
	949	//-------------------------------------------------
	950
	951	WRITE8_MEMBER(midway_turbo_chip_squeak_device::write)
	952	{
	953	synchronize(0, data);
	954	}
	955
	956
	957	//-------------------------------------------------
	958	//  reset_write - write to the reset line
	959	//-------------------------------------------------
	960
	961	WRITE_LINE_MEMBER(midway_turbo_chip_squeak_device::reset_write)
	962	{
	963	m_cpu->set_input_line(INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
	964	}
	965
	966
	967	//-------------------------------------------------
	968	//  porta_w - PIA port A writes
	969	//-------------------------------------------------
	970
	971	WRITE8_MEMBER(midway_turbo_chip_squeak_device::porta_w)
	972	{
	973	m_dacval = (m_dacval & ~0x3fc) | (data << 2);
	974	dac_signed_data_16_w(m_dac, m_dacval << 6);
	975	}
	976
	977
	978	//-------------------------------------------------
	979	//  portb_w - PIA port B writes
	980	//-------------------------------------------------
	981
	982	WRITE8_MEMBER(midway_turbo_chip_squeak_device::portb_w)
	983	{
	984	m_dacval = (m_dacval & ~0x003) | (data >> 6);
	985	dac_signed_data_16_w(m_dac, m_dacval << 6);
	986	m_status = (data >> 4) & 3;
	987	}
	988
	989
	990	//-------------------------------------------------
	991	//  irq_w - IRQ line state changes
	992	//-------------------------------------------------
	993
	994	WRITE_LINE_MEMBER(midway_turbo_chip_squeak_device::irq_w)
	995	{
	996	int combined_state = m_pia->irq_a_state() | m_pia->irq_b_state();
	997	m_cpu->set_input_line(M6809_IRQ_LINE, combined_state ? ASSERT_LINE : CLEAR_LINE);
	998	}
	999
	1000
	1001	//-------------------------------------------------
	1002	//  audio CPU map
	1003	//-------------------------------------------------
	1004
	1005	// address map verified from schematics
	1006	static ADDRESS_MAP_START( turbocs_map, AS_PROGRAM, 8, midway_turbo_chip_squeak_device )
	1007	ADDRESS_MAP_UNMAP_HIGH
	1008	AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0x3800) AM_RAM
	1009	AM_RANGE(0x4000, 0x4003) AM_MIRROR(0x3ffc) AM_DEVREADWRITE("pia", pia6821_device, read_alt, write_alt)
	1010	AM_RANGE(0x8000, 0xffff) AM_ROM
	1011	ADDRESS_MAP_END
	1012
	1013
	1014	//-------------------------------------------------
	1015	//  6821 PIA interface
	1016	//-------------------------------------------------
	1017
	1018	static const pia6821_interface turbocs_pia_intf =
	1019	{
	1020	DEVCB_NULL,      // port A in
	1021	DEVCB_NULL,      // port B in
	1022	DEVCB_NULL,      // line CA1 in
	1023	DEVCB_NULL,      // line CB1 in
	1024	DEVCB_NULL,      // line CA2 in
	1025	DEVCB_NULL,      // line CB2 in
	1026	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_turbo_chip_squeak_device, porta_w),      // port A out
	1027	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_turbo_chip_squeak_device, portb_w),      // port B out
	1028	DEVCB_NULL,      // line CA2 out
	1029	DEVCB_NULL,      // port CB2 out
	1030	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_turbo_chip_squeak_device, irq_w),   // IRQA
	1031	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_turbo_chip_squeak_device, irq_w)      // IRQB
	1032	};
	1033
	1034
	1035	//-------------------------------------------------
	1036	//  machine configuration
	1037	//-------------------------------------------------
	1038
	1039	static MACHINE_CONFIG_FRAGMENT(midway_turbo_chip_squeak)
	1040	MCFG_CPU_ADD("cpu", M6809E, TURBOCS_CLOCK)
	1041	MCFG_CPU_PROGRAM_MAP(turbocs_map)
	1042
	1043	MCFG_PIA6821_ADD("pia", turbocs_pia_intf)
	1044
	1045	MCFG_SOUND_ADD("dac", DAC, 0)
	1046	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 1.0)
	1047	MACHINE_CONFIG_END
	1048
	1049
	1050	//-------------------------------------------------
	1051	//  device_mconfig_additions - return a pointer to
	1052	//  the device's machine fragment
	1053	//-------------------------------------------------
	1054
	1055	machine_config_constructor midway_turbo_chip_squeak_device::device_mconfig_additions() const
	1056	{
	1057	return MACHINE_CONFIG_NAME( midway_turbo_chip_squeak );
	1058	}
	1059
	1060
	1061	//-------------------------------------------------
	1062	//  device_start - device-specific startup
	1063	//-------------------------------------------------
	1064
	1065	void midway_turbo_chip_squeak_device::device_start()
	1066	{
	1067	save_item(NAME(m_status));
	1068	save_item(NAME(m_dacval));
	1069	}
	1070
	1071
	1072	//-------------------------------------------------
	1073	//  device_reset - device-specific reset
	1074	//-------------------------------------------------
	1075
	1076	void midway_turbo_chip_squeak_device::device_reset()
	1077	{
	1078	}
	1079
	1080
	1081	//-------------------------------------------------
	1082	//  device_timer - timer callbacks
	1083	//-------------------------------------------------
	1084
	1085	void midway_turbo_chip_squeak_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	1086	{
	1087	m_pia->portb_w((param >> 1) & 0x0f);
	1088	m_pia->ca1_w(~param & 0x01);
	1089
	1090	// oftentimes games will write one nibble at a time; the sync on this is very
	1091	// important, so we boost the interleave briefly while this happens
	1092	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
	1093	}
	1094
	1095
	1096	//**************************************************************************
	1097	//  SQUAWK 'N' TALK BOARD
	1098	//**************************************************************************
	1099
	1100	//-------------------------------------------------
	1101	//  midway_squawk_n_talk_device - constructor
	1102	//-------------------------------------------------
	1103
	1104	midway_squawk_n_talk_device::midway_squawk_n_talk_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	1105	: device_t(mconfig, MIDWAY_SQUAWK_N_TALK, "Midway Squawk 'n' Talk Sound Board", "midsnt", tag, owner, clock),
	1106	device_mixer_interface(mconfig, *this),
	1107	m_cpu(*this, "cpu"),
	1108	m_pia0(*this, "pia0"),
	1109	m_pia1(*this, "pia1"),
	1110	m_tms5200(*this, "tms5200"),
	1111	m_tms_command(0),
	1112	m_tms_strobes(0)
	1113	{
	1114	}
	1115
	1116
	1117	//-------------------------------------------------
	1118	//  write - handle an external write to the input
	1119	//   latch
	1120	//-------------------------------------------------
	1121
	1122	WRITE8_MEMBER(midway_squawk_n_talk_device::write)
	1123	{
	1124	synchronize(0, data);
	1125	}
	1126
	1127
	1128	//-------------------------------------------------
	1129	//  reset_write - write to the reset line
	1130	//-------------------------------------------------
	1131
	1132	WRITE_LINE_MEMBER(midway_squawk_n_talk_device::reset_write)
	1133	{
	1134	m_cpu->set_input_line(INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
	1135	}
	1136
	1137
	1138	//-------------------------------------------------
	1139	//  porta1_w - PIA #1 port A writes
	1140	//-------------------------------------------------
	1141
	1142	WRITE8_MEMBER(midway_squawk_n_talk_device::porta1_w )
	1143	{
	1144	logerror("Write to AY-8912 = %02X\n", data);
	1145	}
	1146
	1147
	1148	//-------------------------------------------------
	1149	//  dac_w - DAC data writes
	1150	//-------------------------------------------------
	1151
	1152	WRITE8_MEMBER(midway_squawk_n_talk_device::dac_w)
	1153	{
	1154	logerror("Write to DAC = %02X\n", data);
	1155	}
	1156
	1157
	1158	//-------------------------------------------------
	1159	//  porta2_w - PIA #2 port A writes
	1160	//-------------------------------------------------
	1161
	1162	WRITE8_MEMBER(midway_squawk_n_talk_device::porta2_w)
	1163	{
	1164	m_tms_command = data;
	1165	}
	1166
	1167
	1168	//-------------------------------------------------
	1169	//  portb2_w - PIA #2 port B writes
	1170	//-------------------------------------------------
	1171
	1172	WRITE8_MEMBER(midway_squawk_n_talk_device::portb2_w)
	1173	{
	1174	// bits 0-1 select read/write strobes on the TMS5200
	1175	data &= 0x03;
	1176
	1177	// write strobe -- pass the current command to the TMS5200
	1178	if (((data ^ m_tms_strobes) & 0x02) && !(data & 0x02))
	1179	{
	1180	tms5220_data_w(m_tms5200, offset, m_tms_command);
	1181
	1182	// DoT expects the ready line to transition on a command/write here, so we oblige
	1183	m_pia1->ca2_w(1);
	1184	m_pia1->ca2_w(0);
	1185	}
	1186
	1187	// read strobe -- read the current status from the TMS5200
	1188	else if (((data ^ m_tms_strobes) & 0x01) && !(data & 0x01))
	1189	{
	1190	m_pia1->porta_w(tms5220_status_r(m_tms5200, offset));
	1191
	1192	// DoT expects the ready line to transition on a command/write here, so we oblige
	1193	m_pia1->ca2_w(1);
	1194	m_pia1->ca2_w(0);
	1195	}
	1196
	1197	// remember the state
	1198	m_tms_strobes = data;
	1199	}
	1200
	1201
	1202	//-------------------------------------------------
	1203	//  irq_w - IRQ line state changes
	1204	//-------------------------------------------------
	1205
	1206	WRITE_LINE_MEMBER(midway_squawk_n_talk_device::irq_w)
	1207	{
	1208	int combined_state = m_pia0->irq_a_state() | m_pia0->irq_b_state() | m_pia1->irq_a_state() | m_pia1->irq_b_state();
	1209	m_cpu->set_input_line(M6800_IRQ_LINE, combined_state ? ASSERT_LINE : CLEAR_LINE);
	1210	}
	1211
	1212
	1213	//-------------------------------------------------
	1214	//  audio CPU map
	1215	//-------------------------------------------------
	1216
	1217	// address map verified from schematics
	1218	// note that jumpers control the ROM sizes; if these are changed, use the alternate
	1219	// address map below
	1220	static ADDRESS_MAP_START( squawkntalk_map, AS_PROGRAM, 8, midway_squawk_n_talk_device )
	1221	ADDRESS_MAP_UNMAP_HIGH
	1222	AM_RANGE(0x0000, 0x007f) AM_RAM      // internal RAM
	1223	AM_RANGE(0x0080, 0x0083) AM_MIRROR(0x4f6c) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
	1224	AM_RANGE(0x0090, 0x0093) AM_MIRROR(0x4f6c) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
	1225	AM_RANGE(0x1000, 0x1fff) AM_MIRROR(0x4000) AM_WRITE(dac_w)
	1226	AM_RANGE(0x8000, 0xbfff) AM_MIRROR(0x4000) AM_ROM
	1227	ADDRESS_MAP_END
	1228
	1229	// alternate address map if the ROM jumpers are changed to support a smaller
	1230	// ROM size of 2k
	1231	#ifdef UNUSED_FUNCTION
	1232	static ADDRESS_MAP_START( squawkntalk_alt_map, AS_PROGRAM, 8, midway_squawk_n_talk_device )
	1233	ADDRESS_MAP_UNMAP_HIGH
	1234	AM_RANGE(0x0000, 0x007f) AM_RAM      // internal RAM
	1235	AM_RANGE(0x0080, 0x0083) AM_MIRROR(0x676c) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
	1236	AM_RANGE(0x0090, 0x0093) AM_MIRROR(0x676c) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
	1237	AM_RANGE(0x0800, 0x0fff) AM_MIRROR(0x6000) AM_WRITE(dac_w)
	1238	AM_RANGE(0x8000, 0x9fff) AM_MIRROR(0x6000) AM_ROM
	1239	ADDRESS_MAP_END
	1240	#endif
	1241
	1242
	1243	//-------------------------------------------------
	1244	//  6821 PIA interfaces
	1245	//-------------------------------------------------
	1246
	1247	static const pia6821_interface squawkntalk_pia0_intf =
	1248	{
	1249	DEVCB_NULL,      // port A in
	1250	DEVCB_NULL,      // port B in
	1251	DEVCB_NULL,      // line CA1 in
	1252	DEVCB_NULL,      // line CB1 in
	1253	DEVCB_NULL,      // line CA2 in
	1254	DEVCB_NULL,      // line CB2 in
	1255	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_squawk_n_talk_device, porta1_w),   // port A out
	1256	DEVCB_NULL,      // port B out
	1257	DEVCB_NULL,      // line CA2 out
	1258	DEVCB_NULL,      // port CB2 out
	1259	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_squawk_n_talk_device, irq_w),   // IRQA
	1260	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_squawk_n_talk_device, irq_w)      // IRQB
	1261	};
	1262
	1263	static const pia6821_interface squawkntalk_pia1_intf =
	1264	{
	1265	DEVCB_NULL,      // port A in
	1266	DEVCB_NULL,      // port B in
	1267	DEVCB_NULL,      // line CA1 in
	1268	DEVCB_NULL,      // line CB1 in
	1269	DEVCB_NULL,      // line CA2 in
	1270	DEVCB_NULL,      // line CB2 in
	1271	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_squawk_n_talk_device, porta2_w),      // port A out
	1272	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, midway_squawk_n_talk_device, portb2_w),      // port B out
	1273	DEVCB_NULL,      // line CA2 out
	1274	DEVCB_NULL,      // port CB2 out
	1275	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_squawk_n_talk_device, irq_w),   // IRQA
	1276	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, midway_squawk_n_talk_device, irq_w)      // IRQB
	1277	};
	1278
	1279
	1280	//-------------------------------------------------
	1281	//  machine configuration
	1282	//-------------------------------------------------
	1283
	1284	static MACHINE_CONFIG_FRAGMENT(midway_squawk_n_talk)
	1285	MCFG_CPU_ADD("cpu", M6802, SQUAWKTALK_CLOCK)
	1286	MCFG_CPU_PROGRAM_MAP(squawkntalk_map)
	1287
	1288	MCFG_PIA6821_ADD("pia0", squawkntalk_pia0_intf)
	1289	MCFG_PIA6821_ADD("pia1", squawkntalk_pia1_intf)
	1290
	1291	// only used on Discs of Tron, which is stereo
	1292	MCFG_SOUND_ADD("tms5200", TMS5200, 640000)
	1293	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.60)
	1294
	1295	// the board also supports an AY-8912 and/or an 8-bit DAC, neither of
	1296	// which are populated on the Discs of Tron board
	1297	MACHINE_CONFIG_END
	1298
	1299
	1300	//-------------------------------------------------
	1301	//  device_mconfig_additions - return a pointer to
	1302	//  the device's machine fragment
	1303	//-------------------------------------------------
	1304
	1305	machine_config_constructor midway_squawk_n_talk_device::device_mconfig_additions() const
	1306	{
	1307	return MACHINE_CONFIG_NAME( midway_squawk_n_talk );
	1308	}
	1309
	1310
	1311	//-------------------------------------------------
	1312	//  device_start - device-specific startup
	1313	//-------------------------------------------------
	1314
	1315	void midway_squawk_n_talk_device::device_start()
	1316	{
	1317	save_item(NAME(m_tms_command));
	1318	save_item(NAME(m_tms_strobes));
	1319	}
	1320
	1321
	1322	//-------------------------------------------------
	1323	//  device_reset - device-specific reset
	1324	//-------------------------------------------------
	1325
	1326	void midway_squawk_n_talk_device::device_reset()
	1327	{
	1328	}
	1329
	1330
	1331	//-------------------------------------------------
	1332	//  device_timer - timer callbacks
	1333	//-------------------------------------------------
	1334
	1335	void midway_squawk_n_talk_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	1336	{
	1337	m_pia0->porta_w(~param & 0x0f);
	1338	m_pia0->cb1_w(~param & 0x10);
	1339	}

src/mame/audio/midway.h

r0	r14964
	1	/***************************************************************************
	2
	3	audio/midway.h
	4
	5	Functions to emulate general the various Midway sound cards.
	6
	7	****************************************************************************
	8
	9	Copyright Aaron Giles
	10	All rights reserved.
	11
	12	Redistribution and use in source and binary forms, with or without
	13	modification, are permitted provided that the following conditions are
	14	met:
	15
	16	* Redistributions of source code must retain the above copyright
	17	notice, this list of conditions and the following disclaimer.
	18	* Redistributions in binary form must reproduce the above copyright
	19	notice, this list of conditions and the following disclaimer in
	20	the documentation and/or other materials provided with the
	21	distribution.
	22	* Neither the name 'MAME' nor the names of its contributors may be
	23	used to endorse or promote products derived from this software
	24	without specific prior written permission.
	25
	26	THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
	27	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	28	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	29	DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
	30	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	31	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	32	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	33	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	34	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	35	IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	36	POSSIBILITY OF SUCH DAMAGE.
	37
	38	***************************************************************************/
	39
	40	#pragma once
	41
	42	#ifndef __MIDWAY_AUDIO__
	43	#define __MIDWAY_AUDIO__
	44
	45	#include "cpu/z80/z80.h"
	46	#include "cpu/m68000/m68000.h"
	47	#include "cpu/m6800/m6800.h"
	48	#include "cpu/m6809/m6809.h"
	49	#include "machine/6821pia.h"
	50	#include "sound/tms5220.h"
	51	#include "sound/ay8910.h"
	52	#include "sound/dac.h"
	53
	54
	55	//**************************************************************************
	56	//  GLOBAL VARIABLES
	57	//**************************************************************************
	58
	59	extern const device_type MIDWAY_SSIO;
	60	extern const device_type MIDWAY_CHIP_SQUEAK_DELUXE;
	61	extern const device_type MIDWAY_SOUNDS_GOOD;
	62	extern const device_type MIDWAY_TURBO_CHIP_SQUEAK;
	63	extern const device_type MIDWAY_SQUAWK_N_TALK;
	64
	65
	66
	67	//**************************************************************************
	68	//  DEVICE CONFIGURATION MACROS
	69	//**************************************************************************
	70
	71	#define MCFG_MIDWAY_SSIO_ADD(_tag) \
	72	MCFG_DEVICE_ADD(_tag, MIDWAY_SSIO, 0) \
	73
	74	#define MCFG_MIDWAY_CHIP_SQUEAK_DELUXE_ADD(_tag) \
	75	MCFG_DEVICE_ADD(_tag, MIDWAY_CHIP_SQUEAK_DELUXE, 0) \
	76
	77	#define MCFG_MIDWAY_SOUNDS_GOOD_ADD(_tag) \
	78	MCFG_DEVICE_ADD(_tag, MIDWAY_SOUNDS_GOOD, 0) \
	79
	80	#define MCFG_MIDWAY_TURBO_CHIP_SQUEAK_ADD(_tag) \
	81	MCFG_DEVICE_ADD(_tag, MIDWAY_TURBO_CHIP_SQUEAK, 0) \
	82
	83	#define MCFG_MIDWAY_SQUAWK_N_TALK_ADD(_tag) \
	84	MCFG_DEVICE_ADD(_tag, MIDWAY_SQUAWK_N_TALK, 0) \
	85
	86
	87
	88	//**************************************************************************
	89	//  TYPE DEFINITIONS
	90	//**************************************************************************
	91
	92	// ======================> midway_ssio_device
	93
	94	class midway_ssio_device :   public device_t,
	95	public device_mixer_interface
	96	{
	97	public:
	98	// construction/destruction
	99	midway_ssio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	100
	101	// read/write
	102	DECLARE_READ8_MEMBER(read);
	103	DECLARE_WRITE8_MEMBER(write);
	104	DECLARE_WRITE_LINE_MEMBER(reset_write);
	105	DECLARE_READ8_MEMBER(ioport_read);
	106	DECLARE_WRITE8_MEMBER(ioport_write);
	107
	108	// configuration
	109	void set_custom_input(int which, UINT8 mask, read8_delegate handler);
	110	void set_custom_output(int which, UINT8 mask, write8_delegate handler);
	111
	112	// internal communications
	113	INTERRUPT_GEN_MEMBER(clock_14024);
	114	READ8_MEMBER(irq_clear);
	115	DECLARE_WRITE8_MEMBER(status_w);
	116	DECLARE_READ8_MEMBER(data_r);
	117	DECLARE_WRITE8_MEMBER(porta0_w);
	118	DECLARE_WRITE8_MEMBER(portb0_w);
	119	DECLARE_WRITE8_MEMBER(porta1_w);
	120	DECLARE_WRITE8_MEMBER(portb1_w);
	121
	122	protected:
	123	// device-level overrides
	124	virtual machine_config_constructor device_mconfig_additions() const;
	125	virtual ioport_constructor device_input_ports() const;
	126	virtual void device_start();
	127	virtual void device_reset();
	128	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	129
	130	private:
	131	// internal helpers
	132	void compute_ay8910_modulation();
	133	void update_volumes();
	134
	135	// devices
	136	required_device<z80_device> m_cpu;
	137	required_device<ay8910_device> m_ay0;
	138	required_device<ay8910_device> m_ay1;
	139
	140	// internal state
	141	UINT8 m_data[4];
	142	UINT8 m_status;
	143	UINT8 m_14024_count;
	144	UINT8 m_mute;
	145	UINT8 m_overall[2];
	146	UINT8 m_duty_cycle[2][3];
	147	UINT8 m_ayvolume_lookup[16];
	148
	149	// I/O port overrides
	150	UINT8 m_custom_input_mask[5];
	151	read8_delegate m_custom_input[5];
	152	UINT8 m_custom_output_mask[2];
	153	write8_delegate m_custom_output[2];
	154	};
	155
	156
	157	// ======================> midway_chip_squeak_deluxe_device
	158
	159	class midway_chip_squeak_deluxe_device :   public device_t,
	160	public device_mixer_interface
	161	{
	162	public:
	163	// construction/destruction
	164	midway_chip_squeak_deluxe_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	165
	166	// read/write
	167	DECLARE_READ8_MEMBER(read);
	168	DECLARE_WRITE8_MEMBER(write);
	169	DECLARE_WRITE_LINE_MEMBER(reset_write);
	170
	171	// internal communications
	172	DECLARE_WRITE8_MEMBER(porta_w);
	173	DECLARE_WRITE8_MEMBER(portb_w);
	174	DECLARE_WRITE_LINE_MEMBER(irq_w);
	175	DECLARE_READ16_MEMBER(pia_r);
	176	DECLARE_WRITE16_MEMBER(pia_w);
	177
	178	protected:
	179	// device-level overrides
	180	virtual machine_config_constructor device_mconfig_additions() const;
	181	virtual void device_start();
	182	virtual void device_reset();
	183	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	184
	185	private:
	186	// devices
	187	required_device<m68000_device> m_cpu;
	188	required_device<pia6821_device> m_pia;
	189	required_device<dac_device> m_dac;
	190
	191	// internal state
	192	UINT8 m_status;
	193	UINT16 m_dacval;
	194	};
	195
	196
	197	// ======================> midway_sounds_good_device
	198
	199	class midway_sounds_good_device :   public device_t,
	200	public device_mixer_interface
	201	{
	202	public:
	203	// construction/destruction
	204	midway_sounds_good_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	205
	206	// read/write
	207	DECLARE_READ8_MEMBER(read);
	208	DECLARE_WRITE8_MEMBER(write);
	209	DECLARE_WRITE_LINE_MEMBER(reset_write);
	210
	211	// internal communications
	212	DECLARE_WRITE8_MEMBER(porta_w);
	213	DECLARE_WRITE8_MEMBER(portb_w);
	214	DECLARE_WRITE_LINE_MEMBER(irq_w);
	215
	216	protected:
	217	// device-level overrides
	218	virtual machine_config_constructor device_mconfig_additions() const;
	219	virtual void device_start();
	220	virtual void device_reset();
	221	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	222
	223	private:
	224	// devices
	225	required_device<m68000_device> m_cpu;
	226	required_device<pia6821_device> m_pia;
	227	required_device<dac_device> m_dac;
	228
	229	// internal state
	230	UINT8 m_status;
	231	UINT16 m_dacval;
	232	};
	233
	234
	235	// ======================> midway_turbo_chip_squeak_device
	236
	237	class midway_turbo_chip_squeak_device :   public device_t,
	238	public device_mixer_interface
	239	{
	240	public:
	241	// construction/destruction
	242	midway_turbo_chip_squeak_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	243
	244	// read/write
	245	DECLARE_READ8_MEMBER(read);
	246	DECLARE_WRITE8_MEMBER(write);
	247	DECLARE_WRITE_LINE_MEMBER(reset_write);
	248
	249	// internal communications
	250	DECLARE_WRITE8_MEMBER(porta_w);
	251	DECLARE_WRITE8_MEMBER(portb_w);
	252	DECLARE_WRITE_LINE_MEMBER(irq_w);
	253
	254	protected:
	255	// device-level overrides
	256	virtual machine_config_constructor device_mconfig_additions() const;
	257	virtual void device_start();
	258	virtual void device_reset();
	259	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	260
	261	private:
	262	// devices
	263	required_device<m6809e_device> m_cpu;
	264	required_device<pia6821_device> m_pia;
	265	required_device<dac_device> m_dac;
	266
	267	// internal state
	268	UINT8 m_status;
	269	UINT16 m_dacval;
	270	};
	271
	272
	273	// ======================> midway_squawk_n_talk_device
	274
	275	class midway_squawk_n_talk_device :   public device_t,
	276	public device_mixer_interface
	277	{
	278	public:
	279	// construction/destruction
	280	midway_squawk_n_talk_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	281
	282	// read/write
	283	DECLARE_WRITE8_MEMBER(write);
	284	DECLARE_WRITE_LINE_MEMBER(reset_write);
	285
	286	// internal communications
	287	DECLARE_WRITE8_MEMBER(porta1_w);
	288	DECLARE_WRITE8_MEMBER(dac_w);
	289	DECLARE_WRITE8_MEMBER(porta2_w);
	290	DECLARE_WRITE8_MEMBER(portb2_w);
	291	DECLARE_WRITE_LINE_MEMBER(irq_w);
	292
	293	protected:
	294	// device-level overrides
	295	virtual machine_config_constructor device_mconfig_additions() const;
	296	virtual void device_start();
	297	virtual void device_reset();
	298	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	299
	300	private:
	301	// devices
	302	required_device<m6802_device> m_cpu;
	303	required_device<pia6821_device> m_pia0;
	304	required_device<pia6821_device> m_pia1;
	305	optional_device<tms5200_device> m_tms5200;
	306
	307	// internal state
	308	UINT8 m_tms_command;
	309	UINT8 m_tms_strobes;
	310	};
	311
	312
	313	/************ SSIO input ports ***************/
	314
	315	#define SSIO_INPUT_PORTS(ssio) \
	316	AM_RANGE(0x00, 0x04) AM_MIRROR(0x18) AM_DEVREAD(ssio, midway_ssio_device, ioport_read) \
	317	AM_RANGE(0x07, 0x07) AM_MIRROR(0x18) AM_DEVREAD(ssio, midway_ssio_device, read) \
	318	AM_RANGE(0x00, 0x07) AM_MIRROR(0x03) AM_DEVWRITE(ssio, midway_ssio_device, ioport_write) \
	319	AM_RANGE(0x1c, 0x1f) AM_DEVWRITE(ssio, midway_ssio_device, write)
	320
	321
	322	#endif /* __MIDWAY_AUDIO__ */

src/mame/audio/t5182.c

r14963	r14964
272	272
273	273	const ym2151_interface t5182_ym2151_interface =
274	274	{
275		t5182_ym2151_irq_handler
	275	DEVCB_LINE(t5182_ym2151_irq_handler)
276	276	};
277	277
278	278

src/mame/audio/williams.c

r14963	r14964
1	1	/***************************************************************************
2	2
	3	audio/williams.h
	4
	5	Functions to emulate general the various Williams/Midway sound cards.
	6
	7	****************************************************************************
	8
	9	Copyright Aaron Giles
	10	All rights reserved.
	11
	12	Redistribution and use in source and binary forms, with or without
	13	modification, are permitted provided that the following conditions are
	14	met:
	15
	16	* Redistributions of source code must retain the above copyright
	17	notice, this list of conditions and the following disclaimer.
	18	* Redistributions in binary form must reproduce the above copyright
	19	notice, this list of conditions and the following disclaimer in
	20	the documentation and/or other materials provided with the
	21	distribution.
	22	* Neither the name 'MAME' nor the names of its contributors may be
	23	used to endorse or promote products derived from this software
	24	without specific prior written permission.
	25
	26	THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
	27	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	28	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	29	DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
	30	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	31	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	32	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	33	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	34	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	35	IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	36	POSSIBILITY OF SUCH DAMAGE.
	37
	38	****************************************************************************
	39
3	40	Midway/Williams Audio Boards
4	41	----------------------------
5	42
r14963	r14964
43	80
44	81
45	82
46		/***************************************************************************
47		STATIC GLOBALS
48		****************************************************************************/
	83	//**************************************************************************
	84	//  GLOBAL VARIABLES
	85	//**************************************************************************
49	86
50		typedef struct _williams_audio_state williams_audio_state;
51		struct _williams_audio_state
52		{
53		UINT8 sound_int_state;
	87	extern const device_type WILLIAMS_NARC_SOUND = &device_creator<williams_narc_sound_device>;
	88	extern const device_type WILLIAMS_CVSD_SOUND = &device_creator<williams_cvsd_sound_device>;
	89	extern const device_type WILLIAMS_ADPCM_SOUND = &device_creator<williams_adpcm_sound_device>;
54	90
55		UINT8 audio_talkback;
56		UINT8 audio_sync;
57	91
58		device_t *sound_cpu;
59		device_t *soundalt_cpu;
60		};
61	92
62		static williams_audio_state audio;
	93	//**************************************************************************
	94	//  CVSD SOUND BOARD
	95	//**************************************************************************
63	96
64		/***************************************************************************
65		FUNCTION PROTOTYPES
66		****************************************************************************/
	97	//-------------------------------------------------
	98	//  williams_cvsd_sound_device - constructor
	99	//-------------------------------------------------
67	100
68		static void init_audio_state(running_machine &machine);
	101	williams_cvsd_sound_device::williams_cvsd_sound_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	102	: device_t(mconfig, WILLIAMS_CVSD_SOUND, "Williams CVSD Sound Board", "wmscvsd", tag, owner, clock),
	103	device_mixer_interface(mconfig, *this),
	104	m_cpu(*this, "cpu"),
	105	m_pia(*this, "pia"),
	106	m_hc55516(*this, "cvsd"),
	107	m_talkback(0)
	108	{
	109	}
69	110
70		static void cvsd_ym2151_irq(device_t *device, int state);
71		static void adpcm_ym2151_irq(device_t *device, int state);
72		static WRITE_LINE_DEVICE_HANDLER( cvsd_irqa );
73		static WRITE_LINE_DEVICE_HANDLER( cvsd_irqb );
74	111
75		static WRITE8_HANDLER( cvsd_bank_select_w );
76		static WRITE8_DEVICE_HANDLER( cvsd_talkback_w );
77		static WRITE8_DEVICE_HANDLER( cvsd_digit_clock_clear_w );
78		static WRITE8_DEVICE_HANDLER( cvsd_clock_set_w );
	112	//-------------------------------------------------
	113	//  write - handle an external write to the input
	114	//   latch
	115	//-------------------------------------------------
79	116
80		static READ8_HANDLER( adpcm_command_r );
81		static WRITE8_HANDLER( adpcm_bank_select_w );
82		static WRITE8_DEVICE_HANDLER( adpcm_6295_bank_select_w );
83		static WRITE8_HANDLER( adpcm_talkback_w );
	117	WRITE16_MEMBER(williams_cvsd_sound_device::write)
	118	{
	119	synchronize(0, data);
	120	}
84	121
85		static READ8_HANDLER( narc_command_r );
86		static READ8_HANDLER( narc_command2_r );
87		static WRITE8_HANDLER( narc_command2_w );
88		static WRITE8_HANDLER( narc_master_bank_select_w );
89		static WRITE8_HANDLER( narc_slave_bank_select_w );
90		static WRITE8_HANDLER( narc_master_talkback_w );
91		static WRITE8_HANDLER( narc_master_sync_w );
92		static WRITE8_HANDLER( narc_slave_talkback_w );
93		static WRITE8_HANDLER( narc_slave_sync_w );
94	122
	123	//-------------------------------------------------
	124	//  reset_write - write to the reset line
	125	//-------------------------------------------------
95	126
	127	WRITE_LINE_MEMBER(williams_cvsd_sound_device::reset_write)
	128	{
	129	// going high halts the CPU
	130	if (state)
	131	{
	132	bank_select_w(*m_cpu->space(), 0, 0);
	133	device_reset();
	134	m_cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
	135	}
96	136
97		/***************************************************************************
98		PROCESSOR STRUCTURES
99		****************************************************************************/
	137	// going low resets and reactivates the CPU
	138	else
	139	m_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
	140	}
100	141
101		/* CVSD readmem/writemem structures */
102		static ADDRESS_MAP_START( williams_cvsd_map, AS_PROGRAM, 8, driver_device )
103		AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0x1800) AM_RAM
104		AM_RANGE(0x2000, 0x2001) AM_MIRROR(0x1ffe) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r, ym2151_w)
105		AM_RANGE(0x4000, 0x4003) AM_MIRROR(0x1ffc) AM_DEVREADWRITE("cvsdpia", pia6821_device, read, write)
106		AM_RANGE(0x6000, 0x6000) AM_MIRROR(0x07ff) AM_DEVWRITE_LEGACY("cvsd", cvsd_digit_clock_clear_w)
107		AM_RANGE(0x6800, 0x6800) AM_MIRROR(0x07ff) AM_DEVWRITE_LEGACY("cvsd", cvsd_clock_set_w)
108		AM_RANGE(0x7800, 0x7800) AM_MIRROR(0x07ff) AM_WRITE_LEGACY(cvsd_bank_select_w)
109		AM_RANGE(0x8000, 0xffff) AM_ROMBANK("bank5")
110		ADDRESS_MAP_END
111	142
	143	//-------------------------------------------------
	144	//  bank_select_w - change memory banks
	145	//-------------------------------------------------
112	146
113		/* NARC master readmem/writemem structures */
114		static ADDRESS_MAP_START( williams_narc_master_map, AS_PROGRAM, 8, driver_device )
115		AM_RANGE(0x0000, 0x1fff) AM_RAM
116		AM_RANGE(0x2000, 0x2001) AM_MIRROR(0x03fe) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r, ym2151_w)
117		AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(narc_master_talkback_w)
118		AM_RANGE(0x2c00, 0x2c00) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(narc_command2_w)
119		AM_RANGE(0x3000, 0x3000) AM_MIRROR(0x03ff) AM_DEVWRITE_LEGACY("dac1", dac_w)
120		AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_READ_LEGACY(narc_command_r)
121		AM_RANGE(0x3800, 0x3800) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(narc_master_bank_select_w)
122		AM_RANGE(0x3c00, 0x3c00) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(narc_master_sync_w)
123		AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("bank5")
124		AM_RANGE(0xc000, 0xffff) AM_ROMBANK("bank6")
125		ADDRESS_MAP_END
	147	WRITE8_MEMBER(williams_cvsd_sound_device::bank_select_w)
	148	{
	149	subbank("rombank")->set_entry(data & 0x0f);
	150	}
126	151
127		/* NARC slave readmem/writemem structures */
128		static ADDRESS_MAP_START( williams_narc_slave_map, AS_PROGRAM, 8, driver_device )
129		AM_RANGE(0x0000, 0x1fff) AM_RAM
130		AM_RANGE(0x2000, 0x2000) AM_MIRROR(0x03ff) AM_DEVWRITE_LEGACY("cvsd", cvsd_clock_set_w)
131		AM_RANGE(0x2400, 0x2400) AM_MIRROR(0x03ff) AM_DEVWRITE_LEGACY("cvsd", cvsd_digit_clock_clear_w)
132		AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(narc_slave_talkback_w)
133		AM_RANGE(0x3000, 0x3000) AM_MIRROR(0x03ff) AM_DEVWRITE_LEGACY("dac2", dac_w)
134		AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_READ_LEGACY(narc_command2_r)
135		AM_RANGE(0x3800, 0x3800) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(narc_slave_bank_select_w)
136		AM_RANGE(0x3c00, 0x3c00) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(narc_slave_sync_w)
137		AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("bank7")
138		AM_RANGE(0xc000, 0xffff) AM_ROMBANK("bank8")
139		ADDRESS_MAP_END
140	152
	153	//-------------------------------------------------
	154	//  talkback_w - write to the talkback latch
	155	//-------------------------------------------------
141	156
142		/* ADPCM readmem/writemem structures */
143		static ADDRESS_MAP_START( williams_adpcm_map, AS_PROGRAM, 8, driver_device )
144		AM_RANGE(0x0000, 0x1fff) AM_RAM
145		AM_RANGE(0x2000, 0x2000) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(adpcm_bank_select_w)
146		AM_RANGE(0x2400, 0x2401) AM_MIRROR(0x03fe) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r, ym2151_w)
147		AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_DEVWRITE_LEGACY("dac", dac_w)
148		AM_RANGE(0x2c00, 0x2c00) AM_MIRROR(0x03ff) AM_DEVREADWRITE("oki", okim6295_device, read, write)
149		AM_RANGE(0x3000, 0x3000) AM_MIRROR(0x03ff) AM_READ_LEGACY(adpcm_command_r)
150		AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_DEVWRITE_LEGACY("oki", adpcm_6295_bank_select_w)
151		AM_RANGE(0x3c00, 0x3c00) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(adpcm_talkback_w)
152		AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("bank5")
153		AM_RANGE(0xc000, 0xffff) AM_ROMBANK("bank6")
154		ADDRESS_MAP_END
	157	WRITE8_MEMBER(williams_cvsd_sound_device::talkback_w)
	158	{
	159	m_talkback = data;
	160	logerror("CVSD Talkback = %02X\n", data);
	161	}
155	162
156	163
	164	//-------------------------------------------------
	165	//  cvsd_digit_clock_clear_w - clear the clock on
	166	//  the HC55516 and clock the data
	167	//-------------------------------------------------
157	168
158		/* PIA structure */
159		static const pia6821_interface cvsd_pia_intf =
	169	WRITE8_MEMBER(williams_cvsd_sound_device::cvsd_digit_clock_clear_w)
160	170	{
161		DEVCB_NULL,      /* port A in */
162		DEVCB_NULL,      /* port B in */
163		DEVCB_NULL,      /* line CA1 in */
164		DEVCB_NULL,      /* line CB1 in */
165		DEVCB_NULL,      /* line CA2 in */
166		DEVCB_NULL,      /* line CB2 in */
167		DEVCB_DEVICE_HANDLER("dac", dac_w),      /* port A out */
168		DEVCB_HANDLER(cvsd_talkback_w),      /* port B out */
169		DEVCB_NULL,      /* line CA2 out */
170		DEVCB_NULL,      /* port CB2 out */
171		DEVCB_LINE(cvsd_irqa),      /* IRQA */
172		DEVCB_LINE(cvsd_irqb)      /* IRQB */
173		};
	171	hc55516_digit_w(m_hc55516, data);
	172	hc55516_clock_w(m_hc55516, 0);
	173	}
174	174
175	175
	176	//-------------------------------------------------
	177	//  cvsd_clock_set_w - set the clock on the HC55516
	178	//-------------------------------------------------
176	179
177		/***************************************************************************
178		AUDIO STRUCTURES
179		****************************************************************************/
180
181		/* YM2151 structure (CVSD variant) */
182		static const ym2151_interface cvsd_ym2151_interface =
	180	WRITE8_MEMBER(williams_cvsd_sound_device::cvsd_clock_set_w)
183	181	{
184		cvsd_ym2151_irq
185		};
	182	hc55516_clock_w(m_hc55516, 1);
	183	}
186	184
187	185
188		/* YM2151 structure (ADPCM variant) */
189		static const ym2151_interface adpcm_ym2151_interface =
	186	//-------------------------------------------------
	187	//  ym2151_irq_w - process IRQ signal changes from
	188	//   the YM2151
	189	//-------------------------------------------------
	190
	191	WRITE_LINE_MEMBER(williams_cvsd_sound_device::ym2151_irq_w)
190	192	{
191		adpcm_ym2151_irq
192		};
	193	m_pia->ca1_w(!state);
	194	}
193	195
194	196
	197	//-------------------------------------------------
	198	//  pia_irqa - process IRQ A signal changes from
	199	//   the 6821
	200	//-------------------------------------------------
195	201
196		/***************************************************************************
197		MACHINE DRIVERS
198		****************************************************************************/
	202	WRITE_LINE_MEMBER(williams_cvsd_sound_device::pia_irqa)
	203	{
	204	m_cpu->set_input_line(M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
	205	}
199	206
200		MACHINE_CONFIG_FRAGMENT( williams_cvsd_sound )
201		MCFG_CPU_ADD("cvsdcpu", M6809E, CVSD_MASTER_CLOCK)
202		MCFG_CPU_PROGRAM_MAP(williams_cvsd_map)
203	207
204		MCFG_PIA6821_ADD("cvsdpia", cvsd_pia_intf)
	208	//-------------------------------------------------
	209	//  pia_irqb - process IRQ B signal changes from
	210	//   the 6821
	211	//-------------------------------------------------
205	212
206		MCFG_SPEAKER_STANDARD_MONO("mono")
	213	WRITE_LINE_MEMBER(williams_cvsd_sound_device::pia_irqb)
	214	{
	215	m_cpu->set_input_line(INPUT_LINE_NMI, state ? ASSERT_LINE : CLEAR_LINE);
	216	}
207	217
208		MCFG_SOUND_ADD("ymsnd", YM2151, CVSD_FM_CLOCK)
209		MCFG_SOUND_CONFIG(cvsd_ym2151_interface)
210		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.10)
211	218
212		MCFG_SOUND_ADD("dac", DAC, 0)
213		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
	219	//-------------------------------------------------
	220	//  audio CPU map
	221	//-------------------------------------------------
214	222
215		MCFG_SOUND_ADD("cvsd", HC55516, 0)
216		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.60)
217		MACHINE_CONFIG_END
	223	static ADDRESS_MAP_START( williams_cvsd_map, AS_PROGRAM, 8, williams_cvsd_sound_device )
	224	AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0x1800) AM_RAM
	225	AM_RANGE(0x2000, 0x2001) AM_MIRROR(0x1ffe) AM_DEVREADWRITE_LEGACY("ym2151", ym2151_r, ym2151_w)
	226	AM_RANGE(0x4000, 0x4003) AM_MIRROR(0x1ffc) AM_DEVREADWRITE("pia", pia6821_device, read, write)
	227	AM_RANGE(0x6000, 0x6000) AM_MIRROR(0x07ff) AM_WRITE(cvsd_digit_clock_clear_w)
	228	AM_RANGE(0x6800, 0x6800) AM_MIRROR(0x07ff) AM_WRITE(cvsd_clock_set_w)
	229	AM_RANGE(0x7800, 0x7800) AM_MIRROR(0x07ff) AM_WRITE(bank_select_w)
	230	AM_RANGE(0x8000, 0xffff) AM_ROMBANK("rombank")
	231	ADDRESS_MAP_END
218	232
219	233
220		MACHINE_CONFIG_FRAGMENT( williams_narc_sound )
221		MCFG_CPU_ADD("narc1cpu", M6809E, NARC_MASTER_CLOCK)
222		MCFG_CPU_PROGRAM_MAP(williams_narc_master_map)
	234	//-------------------------------------------------
	235	//  6821 PIA interface
	236	//-------------------------------------------------
223	237
224		MCFG_CPU_ADD("narc2cpu", M6809E, NARC_MASTER_CLOCK)
225		MCFG_CPU_PROGRAM_MAP(williams_narc_slave_map)
	238	static const pia6821_interface cvsd_pia_intf =
	239	{
	240	DEVCB_NULL,      // port A in
	241	DEVCB_NULL,      // port B in
	242	DEVCB_NULL,      // line CA1 in
	243	DEVCB_NULL,      // line CB1 in
	244	DEVCB_NULL,      // line CA2 in
	245	DEVCB_NULL,      // line CB2 in
	246	DEVCB_DEVICE_HANDLER("dac", dac_w),      // port A out
	247	DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, williams_cvsd_sound_device, talkback_w),      // port B out
	248	DEVCB_NULL,      // line CA2 out
	249	DEVCB_NULL,      // port CB2 out
	250	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, williams_cvsd_sound_device, pia_irqa),   // IRQA
	251	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, williams_cvsd_sound_device, pia_irqb)   // IRQB
	252	};
226	253
227		MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
228	254
229		MCFG_SOUND_ADD("ymsnd", YM2151, NARC_FM_CLOCK)
230		MCFG_SOUND_CONFIG(adpcm_ym2151_interface)
231		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.10)
232		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.10)
	255	//-------------------------------------------------
	256	//  YM2151 configuration
	257	//-------------------------------------------------
233	258
234		MCFG_SOUND_ADD("dac1", DAC, 0)
235		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
236		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
	259	static const ym2151_interface cvsd_ym2151_interface =
	260	{
	261	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, williams_cvsd_sound_device, ym2151_irq_w)
	262	};
237	263
238		MCFG_SOUND_ADD("dac2", DAC, 0)
239		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
240		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
241	264
242		MCFG_SOUND_ADD("cvsd", HC55516, 0)
243		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.60)
244		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.60)
245		MACHINE_CONFIG_END
	265	//-------------------------------------------------
	266	//  machine configuration
	267	//-------------------------------------------------
246	268
	269	static MACHINE_CONFIG_FRAGMENT( williams_cvsd_sound )
	270	MCFG_CPU_ADD("cpu", M6809E, CVSD_MASTER_CLOCK)
	271	MCFG_CPU_PROGRAM_MAP(williams_cvsd_map)
247	272
248		MACHINE_CONFIG_FRAGMENT( williams_adpcm_sound )
249		MCFG_CPU_ADD("adpcm", M6809E, ADPCM_MASTER_CLOCK)
250		MCFG_CPU_PROGRAM_MAP(williams_adpcm_map)
	273	MCFG_PIA6821_ADD("pia", cvsd_pia_intf)
251	274
252		MCFG_SPEAKER_STANDARD_MONO("mono")
	275	MCFG_SOUND_ADD("ym2151", YM2151, CVSD_FM_CLOCK)
	276	MCFG_SOUND_CONFIG(cvsd_ym2151_interface)
	277	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.10)
253	278
254		MCFG_SOUND_ADD("ymsnd", YM2151, ADPCM_FM_CLOCK)
255		MCFG_SOUND_CONFIG(adpcm_ym2151_interface)
256		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.10)
257
258	279	MCFG_SOUND_ADD("dac", DAC, 0)
259		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
	280	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.50)
260	281
261		MCFG_OKIM6295_ADD("oki", ADPCM_MASTER_CLOCK/8, OKIM6295_PIN7_HIGH) // clock frequency & pin 7 not verified
262		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
	282	MCFG_SOUND_ADD("cvsd", HC55516, 0)
	283	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.60)
263	284	MACHINE_CONFIG_END
264	285
265	286
	287	//-------------------------------------------------
	288	//  device_mconfig_additions - return a pointer to
	289	//  the device's machine fragment
	290	//-------------------------------------------------
266	291
267		/***************************************************************************
268		INITIALIZATION
269		****************************************************************************/
270
271		void williams_cvsd_init(running_machine &machine)
	292	machine_config_constructor williams_cvsd_sound_device::device_mconfig_additions() const
272	293	{
273		williams_audio_state *state = &audio;
274		UINT8 *ROM;
275		int bank;
	294	return MACHINE_CONFIG_NAME( williams_cvsd_sound );
	295	}
276	296
277		/* configure the CPU */
278		state->sound_cpu = machine.device("cvsdcpu");
279		state->soundalt_cpu = NULL;
280	297
281		/* configure master CPU banks */
282		ROM = machine.region("cvsdcpu")->base();
283		for (bank = 0; bank < 16; bank++)
	298	//-------------------------------------------------
	299	//  device_start - device-specific startup
	300	//-------------------------------------------------
	301
	302	void williams_cvsd_sound_device::device_start()
	303	{
	304	// configure master CPU banks
	305	UINT8 *rom = subregion("cpu")->base();
	306	for (int bank = 0; bank < 16; bank++)
284	307	{
285		/*
286		D0/D1 -> selects: 0=U4 1=U19 2=U20 3=n/c
287		D2 -> A15
288		D3 -> A16
289		*/
	308	//
	309	//  D0/D1 -> selects: 0=U4 1=U19 2=U20 3=n/c
	310	//  D2 -> A15
	311	//  D3 -> A16
	312	//
290	313	offs_t offset = 0x8000 * ((bank >> 2) & 3) + 0x20000 * (bank & 3);
291		memory_configure_bank(machine, "bank5", bank, 1, &ROM[0x10000 + offset], 0);
	314	subbank("rombank")->configure_entry(bank, &rom[0x10000 + offset]);
292	315	}
293		memory_set_bank(machine, "bank5", 0);
	316	subbank("rombank")->set_entry(0);
294	317
295		/* reset the IRQ state */
296		machine.device<pia6821_device>("cvsdpia")->ca1_w(1);
	318	// reset the IRQ state
	319	m_pia->ca1_w(1);
297	320
298		/* register for save states */
299		state_save_register_global(machine, state->sound_int_state);
300		state_save_register_global(machine, state->audio_talkback);
	321	// register for save states
	322	save_item(NAME(m_talkback));
301	323	}
302	324
303	325
304		void williams_narc_init(running_machine &machine)
	326	//-------------------------------------------------
	327	//  device_reset - device-specific reset
	328	//-------------------------------------------------
	329
	330	void williams_cvsd_sound_device::device_reset()
305	331	{
306		williams_audio_state *state = &audio;
307		UINT8 *ROM;
308		int bank;
	332	// reset interrupt states
	333	m_cpu->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
	334	m_cpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
	335	m_cpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
	336	}
309	337
310		/* configure the CPU */
311		state->sound_cpu = machine.device("narc1cpu");
312		state->soundalt_cpu = machine.device("narc2cpu");
313	338
314		/* configure master CPU banks */
315		ROM = machine.region("narc1cpu")->base();
316		for (bank = 0; bank < 16; bank++)
317		{
318		/*
319		D0 -> A15
320		D1/D2 -> selects: 0=n/c 1=U3 2=U4 3=U5
321		D3 -> A16
322		*/
323		offs_t offset = 0x8000 * (bank & 1) + 0x10000 * ((bank >> 3) & 1) + 0x20000 * ((bank >> 1) & 3);
324		memory_configure_bank(machine, "bank5", bank, 1, &ROM[0x10000 + offset], 0);
325		}
326		memory_set_bankptr(machine, "bank6", &ROM[0x10000 + 0x4000 + 0x8000 + 0x10000 + 0x20000 * 3]);
	339	//-------------------------------------------------
	340	//  device_timer - timer callbacks
	341	//-------------------------------------------------
327	342
328		/* configure slave CPU banks */
329		ROM = machine.region("narc2cpu")->base();
330		for (bank = 0; bank < 16; bank++)
331		{
332		/*
333		D0 -> A15
334		D1/D2 -> selects: 0=U35 1=U36 2=U37 3=U38
335		D3 -> A16
336		*/
337		offs_t offset = 0x8000 * (bank & 1) + 0x10000 * ((bank >> 3) & 1) + 0x20000 * ((bank >> 1) & 3);
338		memory_configure_bank(machine, "bank7", bank, 1, &ROM[0x10000 + offset], 0);
339		}
340		memory_set_bankptr(machine, "bank8", &ROM[0x10000 + 0x4000 + 0x8000 + 0x10000 + 0x20000 * 3]);
341
342		/* register for save states */
343		state_save_register_global(machine, state->sound_int_state);
344		state_save_register_global(machine, state->audio_talkback);
345		state_save_register_global(machine, state->audio_sync);
	343	void williams_cvsd_sound_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	344	{
	345	// process incoming data write
	346	m_pia->portb_w(param & 0xff);
	347	m_pia->cb1_w((param >> 8) & 1);
	348	m_pia->cb2_w((param >> 9) & 1);
346	349	}
347	350
348	351
349		void williams_adpcm_init(running_machine &machine)
350		{
351		williams_audio_state *state = &audio;
352		UINT8 *ROM;
353	352
354		/* configure the CPU */
355		state->sound_cpu = machine.device("adpcm");
356		state->soundalt_cpu = NULL;
	353	//**************************************************************************
	354	//  NARC SOUND BOARD
	355	//**************************************************************************
357	356
358		/* configure banks */
359		ROM = machine.region("adpcm")->base();
360		memory_configure_bank(machine, "bank5", 0, 8, &ROM[0x10000], 0x8000);
361		memory_set_bankptr(machine, "bank6", &ROM[0x10000 + 0x4000 + 7 * 0x8000]);
	357	//-------------------------------------------------
	358	//  williams_narc_sound_device - constructor
	359	//-------------------------------------------------
362	360
363		/* expand ADPCM data */
364		/* it is assumed that U12 is loaded @ 0x00000 and U13 is loaded @ 0x40000 */
365		ROM = machine.region("oki")->base();
366		memcpy(ROM + 0x1c0000, ROM + 0x080000, 0x20000);   /* expand individual banks */
367		memcpy(ROM + 0x180000, ROM + 0x0a0000, 0x20000);
368		memcpy(ROM + 0x140000, ROM + 0x0c0000, 0x20000);
369		memcpy(ROM + 0x100000, ROM + 0x0e0000, 0x20000);
370		memcpy(ROM + 0x0c0000, ROM + 0x000000, 0x20000);
371		memcpy(ROM + 0x000000, ROM + 0x040000, 0x20000);
372		memcpy(ROM + 0x080000, ROM + 0x020000, 0x20000);
	361	williams_narc_sound_device::williams_narc_sound_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	362	: device_t(mconfig, WILLIAMS_NARC_SOUND, "Williams NARC Sound Board", "wmsnarc", tag, owner, clock),
	363	device_mixer_interface(mconfig, *this),
	364	m_cpu0(*this, "cpu0"),
	365	m_cpu1(*this, "cpu1"),
	366	m_hc55516(*this, "cvsd"),
	367	m_latch(0),
	368	m_latch2(0),
	369	m_talkback(0),
	370	m_audio_sync(0),
	371	m_sound_int_state(0)
	372	{
	373	}
373	374
374		memcpy(ROM + 0x1e0000, ROM + 0x060000, 0x20000);   /* copy common bank */
375		memcpy(ROM + 0x1a0000, ROM + 0x060000, 0x20000);
376		memcpy(ROM + 0x160000, ROM + 0x060000, 0x20000);
377		memcpy(ROM + 0x120000, ROM + 0x060000, 0x20000);
378		memcpy(ROM + 0x0e0000, ROM + 0x060000, 0x20000);
379		memcpy(ROM + 0x0a0000, ROM + 0x060000, 0x20000);
380		memcpy(ROM + 0x020000, ROM + 0x060000, 0x20000);
381	375
382		/* register for save states */
383		state_save_register_global(machine, state->sound_int_state);
384		state_save_register_global(machine, state->audio_talkback);
	376	//-------------------------------------------------
	377	//  read - return the talkback register with the
	378	//   SYNC bits in bits 8 and 9
	379	//-------------------------------------------------
	380
	381	READ16_MEMBER(williams_narc_sound_device::read)
	382	{
	383	return m_talkback | (m_audio_sync << 8);
385	384	}
386	385
387	386
388		static void init_audio_state(running_machine &machine)
	387	//-------------------------------------------------
	388	//  write - handle an external write to the input
	389	//   latch
	390	//-------------------------------------------------
	391
	392	WRITE16_MEMBER(williams_narc_sound_device::write)
389	393	{
390		williams_audio_state *state = &audio;
391		device_t *sound_cpu = state->sound_cpu;
392		device_t *soundalt_cpu = state->soundalt_cpu;
	394	synchronize(TID_MASTER_COMMAND, data);
	395	}
393	396
394		/* reset the YM2151 state */
395		devtag_reset(machine, "ymsnd");
396	397
397		/* clear all the interrupts */
398		state->sound_int_state = 0;
399		if (sound_cpu != NULL)
	398	//-------------------------------------------------
	399	//  reset_write - write to the reset line
	400	//-------------------------------------------------
	401
	402	WRITE_LINE_MEMBER(williams_narc_sound_device::reset_write)
	403	{
	404	// going high halts the CPU
	405	if (state)
400	406	{
401		device_set_input_line(sound_cpu, M6809_FIRQ_LINE, CLEAR_LINE);
402		device_set_input_line(sound_cpu, M6809_IRQ_LINE, CLEAR_LINE);
403		device_set_input_line(sound_cpu, INPUT_LINE_NMI, CLEAR_LINE);
	407	master_bank_select_w(*m_cpu0->space(), 0, 0);
	408	slave_bank_select_w(*m_cpu1->space(), 0, 0);
	409	device_reset();
	410	m_cpu0->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
	411	m_cpu1->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
404	412	}
405		if (soundalt_cpu != NULL)
	413
	414	// going low resets and reactivates the CPU
	415	else
406	416	{
407		device_set_input_line(soundalt_cpu, M6809_FIRQ_LINE, CLEAR_LINE);
408		device_set_input_line(soundalt_cpu, M6809_IRQ_LINE, CLEAR_LINE);
409		device_set_input_line(soundalt_cpu, INPUT_LINE_NMI, CLEAR_LINE);
	417	m_cpu0->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
	418	m_cpu1->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
410	419	}
411	420	}
412	421
413	422
	423	//-------------------------------------------------
	424	//  master_bank_select_w - select the bank for the
	425	//  master CPU
	426	//-------------------------------------------------
414	427
415		/***************************************************************************
416		CVSD IRQ GENERATION CALLBACKS
417		****************************************************************************/
418
419		static void cvsd_ym2151_irq(device_t *device, int state)
	428	WRITE8_MEMBER(williams_narc_sound_device::master_bank_select_w)
420	429	{
421		device->machine().device<pia6821_device>("cvsdpia")->ca1_w(!state);
	430	subbank("masterbank")->set_entry(data & 0x0f);
422	431	}
423	432
424	433
425		static WRITE_LINE_DEVICE_HANDLER( cvsd_irqa )
	434	//-------------------------------------------------
	435	//  slave_bank_select_w - select the bank for the
	436	//  slave CPU
	437	//-------------------------------------------------
	438
	439	WRITE8_MEMBER(williams_narc_sound_device::slave_bank_select_w)
426	440	{
427		williams_audio_state *sndstate = &audio;
428
429		device_set_input_line(sndstate->sound_cpu, M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
	441	subbank("slavebank")->set_entry(data & 0x0f);
430	442	}
431	443
432	444
433		static WRITE_LINE_DEVICE_HANDLER( cvsd_irqb )
	445	//-------------------------------------------------
	446	//  command_r - read command written by external
	447	//   agent
	448	//-------------------------------------------------
	449
	450	READ8_MEMBER(williams_narc_sound_device::command_r)
434	451	{
435		williams_audio_state *sndstate = &audio;
436
437		device_set_input_line(sndstate->sound_cpu, INPUT_LINE_NMI, state ? ASSERT_LINE : CLEAR_LINE);
	452	m_cpu0->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
	453	m_sound_int_state = 0;
	454	return m_latch;
438	455	}
439	456
440	457
	458	//-------------------------------------------------
	459	//  command2_w - write command from master CPU to
	460	//   slave CPU
	461	//-------------------------------------------------
441	462
442		/***************************************************************************
443		ADPCM IRQ GENERATION CALLBACKS
444		****************************************************************************/
445
446		static void adpcm_ym2151_irq(device_t *device, int state)
	463	WRITE8_MEMBER(williams_narc_sound_device::command2_w)
447	464	{
448		williams_audio_state *sndstate = &audio;
449
450		device_set_input_line(sndstate->sound_cpu, M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
	465	synchronize(TID_SLAVE_COMMAND, data);
451	466	}
452	467
453	468
	469	//-------------------------------------------------
	470	//  command2_r - read command written by master
	471	//   CPU
	472	//-------------------------------------------------
454	473
455		/***************************************************************************
456		CVSD READ/WRITE HANDLERS
457		****************************************************************************/
458
459		static WRITE8_HANDLER( cvsd_bank_select_w )
	474	READ8_MEMBER(williams_narc_sound_device::command2_r)
460	475	{
461		memory_set_bank(space->machine(), "bank5", data & 0x0f);
	476	m_cpu1->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
	477	return m_latch2;
462	478	}
463	479
464	480
465		static WRITE8_DEVICE_HANDLER( cvsd_talkback_w )
	481	//-------------------------------------------------
	482	//  master_talkback_w - handle writes to the
	483	//   talkback latch from the master CPU
	484	//-------------------------------------------------
	485
	486	WRITE8_MEMBER(williams_narc_sound_device::master_talkback_w)
466	487	{
467		williams_audio_state *state = &audio;
468
469		state->audio_talkback = data;
470		logerror("CVSD Talkback = %02X\n", data);
	488	m_talkback = data;
	489	logerror("Master Talkback = %02X\n", data);
471	490	}
472	491
473	492
474		static WRITE8_DEVICE_HANDLER( cvsd_digit_clock_clear_w )
	493	//-------------------------------------------------
	494	//  master_sync_w - handle writes to the master
	495	//   SYNC register
	496	//-------------------------------------------------
	497
	498	WRITE8_MEMBER(williams_narc_sound_device::master_sync_w)
475	499	{
476		hc55516_digit_w(device, data);
477		hc55516_clock_w(device, 0);
	500	timer_set(attotime::from_double(TIME_OF_74LS123(180000, 0.000001)), TID_SYNC_CLEAR, 0x01);
	501	m_audio_sync |= 0x01;
	502	logerror("Master sync = %02X\n", data);
478	503	}
479	504
480	505
481		static WRITE8_DEVICE_HANDLER( cvsd_clock_set_w )
	506	//-------------------------------------------------
	507	//  slave_talkback_w - handle writes to the
	508	//   talkback latch from the slave CPU
	509	//-------------------------------------------------
	510
	511	WRITE8_MEMBER(williams_narc_sound_device::slave_talkback_w)
482	512	{
483		hc55516_clock_w(device, 1);
	513	logerror("Slave Talkback = %02X\n", data);
484	514	}
485	515
486	516
487		/***************************************************************************
488		CVSD COMMUNICATIONS
489		****************************************************************************/
	517	//-------------------------------------------------
	518	//  slave_sync_w - handle writes to the slave
	519	//   SYNC register
	520	//-------------------------------------------------
490	521
491		static TIMER_CALLBACK( williams_cvsd_delayed_data_w )
	522	WRITE8_MEMBER(williams_narc_sound_device::slave_sync_w)
492	523	{
493		pia6821_device *pia = machine.device<pia6821_device>("cvsdpia");
494		pia->portb_w(param & 0xff);
495		pia->cb1_w((param >> 8) & 1);
496		pia->cb2_w((param >> 9) & 1);
	524	timer_set(attotime::from_double(TIME_OF_74LS123(180000, 0.000001)), TID_SYNC_CLEAR, 0x02);
	525	m_audio_sync |= 0x02;
	526	logerror("Slave sync = %02X\n", data);
497	527	}
498	528
499	529
500		void williams_cvsd_data_w(running_machine &machine, int data)
	530	//-------------------------------------------------
	531	//  cvsd_digit_clock_clear_w - clear the clock on
	532	//  the HC55516 and clock the data
	533	//-------------------------------------------------
	534
	535	WRITE8_MEMBER(williams_narc_sound_device::cvsd_digit_clock_clear_w)
501	536	{
502		machine.scheduler().synchronize(FUNC(williams_cvsd_delayed_data_w), data);
	537	hc55516_digit_w(m_hc55516, data);
	538	hc55516_clock_w(m_hc55516, 0);
503	539	}
504	540
505	541
506		void williams_cvsd_reset_w(running_machine &machine, int state)
	542	//-------------------------------------------------
	543	//  cvsd_clock_set_w - set the clock on the HC55516
	544	//-------------------------------------------------
	545
	546	WRITE8_MEMBER(williams_narc_sound_device::cvsd_clock_set_w)
507	547	{
508		williams_audio_state *sndstate = &audio;
509		address_space *space = sndstate->sound_cpu->memory().space(AS_PROGRAM);
510
511		/* going high halts the CPU */
512		if (state)
513		{
514		cvsd_bank_select_w(space, 0, 0);
515		init_audio_state(space->machine());
516		device_set_input_line(&space->device(), INPUT_LINE_RESET, ASSERT_LINE);
517		}
518		/* going low resets and reactivates the CPU */
519		else
520		device_set_input_line(&space->device(), INPUT_LINE_RESET, CLEAR_LINE);
	548	hc55516_clock_w(m_hc55516, 1);
521	549	}
522	550
523	551
	552	//-------------------------------------------------
	553	//  ym2151_irq_w - handle line changes on the
	554	//   YM2151 IRQ line
	555	//-------------------------------------------------
524	556
525		/***************************************************************************
526		NARC READ/WRITE HANDLERS
527		****************************************************************************/
528
529		static WRITE8_HANDLER( narc_master_bank_select_w )
	557	WRITE_LINE_MEMBER(williams_narc_sound_device::ym2151_irq_w)
530	558	{
531		memory_set_bank(space->machine(), "bank5", data & 0x0f);
	559	m_cpu0->set_input_line(M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
532	560	}
533	561
534	562
535		static WRITE8_HANDLER( narc_slave_bank_select_w )
536		{
537		memory_set_bank(space->machine(), "bank7", data & 0x0f);
538		}
	563	//-------------------------------------------------
	564	//  master CPU map
	565	//-------------------------------------------------
539	566
	567	static ADDRESS_MAP_START( williams_narc_master_map, AS_PROGRAM, 8, williams_narc_sound_device )
	568	AM_RANGE(0x0000, 0x1fff) AM_RAM
	569	AM_RANGE(0x2000, 0x2001) AM_MIRROR(0x03fe) AM_DEVREADWRITE_LEGACY("ym2151", ym2151_r, ym2151_w)
	570	AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_WRITE(master_talkback_w)
	571	AM_RANGE(0x2c00, 0x2c00) AM_MIRROR(0x03ff) AM_WRITE(command2_w)
	572	AM_RANGE(0x3000, 0x3000) AM_MIRROR(0x03ff) AM_DEVWRITE_LEGACY("dac1", dac_w)
	573	AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_READ(command_r)
	574	AM_RANGE(0x3800, 0x3800) AM_MIRROR(0x03ff) AM_WRITE(master_bank_select_w)
	575	AM_RANGE(0x3c00, 0x3c00) AM_MIRROR(0x03ff) AM_WRITE(master_sync_w)
	576	AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("masterbank")
	577	AM_RANGE(0xc000, 0xffff) AM_ROMBANK("masterupper")
	578	ADDRESS_MAP_END
540	579
541		static READ8_HANDLER( narc_command_r )
542		{
543		williams_audio_state *state = &audio;
544		driver_device *drvstate = space->machine().driver_data<driver_device>();
545		device_set_input_line(state->sound_cpu, M6809_IRQ_LINE, CLEAR_LINE);
546		state->sound_int_state = 0;
547		return drvstate->soundlatch_byte_r(*space, 0);
548		}
549	580
	581	//-------------------------------------------------
	582	//  slave CPU map
	583	//-------------------------------------------------
550	584
551		static WRITE8_HANDLER( narc_command2_w )
552		{
553		williams_audio_state *state = &audio;
554		driver_device *drvstate = space->machine().driver_data<driver_device>();
555		drvstate->soundlatch2_byte_w(*space, 0, data & 0xff);
556		device_set_input_line(state->soundalt_cpu, M6809_FIRQ_LINE, ASSERT_LINE);
557		}
	585	static ADDRESS_MAP_START( williams_narc_slave_map, AS_PROGRAM, 8, williams_narc_sound_device )
	586	AM_RANGE(0x0000, 0x1fff) AM_RAM
	587	AM_RANGE(0x2000, 0x2000) AM_MIRROR(0x03ff) AM_WRITE(cvsd_clock_set_w)
	588	AM_RANGE(0x2400, 0x2400) AM_MIRROR(0x03ff) AM_WRITE(cvsd_digit_clock_clear_w)
	589	AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_WRITE(slave_talkback_w)
	590	AM_RANGE(0x3000, 0x3000) AM_MIRROR(0x03ff) AM_DEVWRITE_LEGACY("dac2", dac_w)
	591	AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_READ(command2_r)
	592	AM_RANGE(0x3800, 0x3800) AM_MIRROR(0x03ff) AM_WRITE(slave_bank_select_w)
	593	AM_RANGE(0x3c00, 0x3c00) AM_MIRROR(0x03ff) AM_WRITE(slave_sync_w)
	594	AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("slavebank")
	595	AM_RANGE(0xc000, 0xffff) AM_ROMBANK("slaveupper")
	596	ADDRESS_MAP_END
558	597
559	598
560		static READ8_HANDLER( narc_command2_r )
	599	//-------------------------------------------------
	600	//  YM2151 configuration
	601	//-------------------------------------------------
	602
	603	static const ym2151_interface narc_ym2151_interface =
561	604	{
562		williams_audio_state *state = &audio;
563		driver_device *drvstate = space->machine().driver_data<driver_device>();
564		device_set_input_line(state->soundalt_cpu, M6809_FIRQ_LINE, CLEAR_LINE);
565		return drvstate->soundlatch2_byte_r(*space, 0);
566		}
	605	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, williams_narc_sound_device, ym2151_irq_w)
	606	};
567	607
568	608
569		static WRITE8_HANDLER( narc_master_talkback_w )
570		{
571		williams_audio_state *state = &audio;
	609	//-------------------------------------------------
	610	//  machine configuration
	611	//-------------------------------------------------
572	612
573		state->audio_talkback = data;
574		logerror("Master Talkback = %02X\n", data);
575		}
	613	static MACHINE_CONFIG_FRAGMENT( williams_narc_sound )
	614	MCFG_CPU_ADD("cpu0", M6809E, NARC_MASTER_CLOCK)
	615	MCFG_CPU_PROGRAM_MAP(williams_narc_master_map)
576	616
	617	MCFG_CPU_ADD("cpu1", M6809E, NARC_MASTER_CLOCK)
	618	MCFG_CPU_PROGRAM_MAP(williams_narc_slave_map)
577	619
578		static TIMER_CALLBACK( narc_sync_clear )
579		{
580		williams_audio_state *state = &audio;
	620	MCFG_SOUND_ADD("ym2151", YM2151, NARC_FM_CLOCK)
	621	MCFG_SOUND_CONFIG(narc_ym2151_interface)
	622	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.10)
581	623
582		state->audio_sync &= ~param;
583		}
	624	MCFG_SOUND_ADD("dac1", DAC, 0)
	625	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.50)
584	626
585		static WRITE8_HANDLER( narc_master_sync_w )
586		{
587		williams_audio_state *state = &audio;
	627	MCFG_SOUND_ADD("dac2", DAC, 0)
	628	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.50)
588	629
589		space->machine().scheduler().timer_set(attotime::from_double(TIME_OF_74LS123(180000, 0.000001)), FUNC(narc_sync_clear), 0x01);
590		state->audio_sync |= 0x01;
591		logerror("Master sync = %02X\n", data);
592		}
	630	MCFG_SOUND_ADD("cvsd", HC55516, 0)
	631	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.60)
	632	MACHINE_CONFIG_END
593	633
594	634
595		static WRITE8_HANDLER( narc_slave_talkback_w )
	635	//-------------------------------------------------
	636	//  device_mconfig_additions - return a pointer to
	637	//  the device's machine fragment
	638	//-------------------------------------------------
	639
	640	machine_config_constructor williams_narc_sound_device::device_mconfig_additions() const
596	641	{
597		logerror("Slave Talkback = %02X\n", data);
	642	return MACHINE_CONFIG_NAME( williams_narc_sound );
598	643	}
599	644
600	645
601		static WRITE8_HANDLER( narc_slave_sync_w )
	646	//-------------------------------------------------
	647	//  device_start - device-specific startup
	648	//-------------------------------------------------
	649
	650	void williams_narc_sound_device::device_start()
602	651	{
603		williams_audio_state *state = &audio;
	652	// configure master CPU banks
	653	UINT8 *rom = subregion("cpu0")->base();
	654	for (int bank = 0; bank < 16; bank++)
	655	{
	656	//
	657	//  D0 -> A15
	658	//  D1/D2 -> selects: 0=n/c 1=U3 2=U4 3=U5
	659	//  D3 -> A16
	660	//
	661	offs_t offset = 0x8000 * (bank & 1) + 0x10000 * ((bank >> 3) & 1) + 0x20000 * ((bank >> 1) & 3);
	662	subbank("masterbank")->configure_entry(bank, &rom[0x10000 + offset]);
	663	}
	664	subbank("masterupper")->set_base(&rom[0x10000 + 0x4000 + 0x8000 + 0x10000 + 0x20000 * 3]);
604	665
605		space->machine().scheduler().timer_set(attotime::from_double(TIME_OF_74LS123(180000, 0.000001)), FUNC(narc_sync_clear), 0x02);
606		state->audio_sync |= 0x02;
607		logerror("Slave sync = %02X\n", data);
	666	// configure slave CPU banks
	667	rom = subregion("cpu1")->base();
	668	for (int bank = 0; bank < 16; bank++)
	669	{
	670	//
	671	//  D0 -> A15
	672	//  D1/D2 -> selects: 0=U35 1=U36 2=U37 3=U38
	673	//  D3 -> A16
	674	//
	675	offs_t offset = 0x8000 * (bank & 1) + 0x10000 * ((bank >> 3) & 1) + 0x20000 * ((bank >> 1) & 3);
	676	subbank("slavebank")->configure_entry(bank, &rom[0x10000 + offset]);
	677	}
	678	subbank("slaveupper")->set_base(&rom[0x10000 + 0x4000 + 0x8000 + 0x10000 + 0x20000 * 3]);
	679
	680	// register for save states
	681	save_item(NAME(m_latch));
	682	save_item(NAME(m_latch2));
	683	save_item(NAME(m_talkback));
	684	save_item(NAME(m_audio_sync));
	685	save_item(NAME(m_sound_int_state));
608	686	}
609	687
610	688
	689	//-------------------------------------------------
	690	//  device_reset - device-specific reset
	691	//-------------------------------------------------
611	692
612		/***************************************************************************
613		NARC COMMUNICATIONS
614		****************************************************************************/
	693	void williams_narc_sound_device::device_reset()
	694	{
	695	// reset interrupt states
	696	m_sound_int_state = 0;
	697	m_cpu0->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
	698	m_cpu0->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
	699	m_cpu0->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
	700	m_cpu1->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
	701	m_cpu1->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
	702	m_cpu1->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
	703	}
615	704
616		void williams_narc_data_w(running_machine &machine, int data)
	705
	706	//-------------------------------------------------
	707	//  device_timer - timer callbacks
	708	//-------------------------------------------------
	709
	710	void williams_narc_sound_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
617	711	{
618		williams_audio_state *state = &audio;
619		device_t *sound_cpu = state->sound_cpu;
620		address_space *space = sound_cpu->memory().space(AS_PROGRAM);
621		driver_device *drvstate = space->machine().driver_data<driver_device>();
622		drvstate->soundlatch_byte_w(*space, 0, data & 0xff);
623		device_set_input_line(sound_cpu, INPUT_LINE_NMI, (data & 0x100) ? CLEAR_LINE : ASSERT_LINE);
624		if (!(data & 0x200))
	712	switch (id)
625	713	{
626		device_set_input_line(sound_cpu, M6809_IRQ_LINE, ASSERT_LINE);
627		state->sound_int_state = 1;
	714	case TID_MASTER_COMMAND:
	715	m_latch = param & 0xff;
	716	m_cpu0->set_input_line(INPUT_LINE_NMI, (param & 0x100) ? CLEAR_LINE : ASSERT_LINE);
	717	if ((param & 0x200) == 0)
	718	{
	719	m_cpu0->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
	720	m_sound_int_state = 1;
	721	}
	722	break;
	723
	724	case TID_SLAVE_COMMAND:
	725	m_latch2 = param & 0xff;
	726	m_cpu1->set_input_line(M6809_FIRQ_LINE, ASSERT_LINE);
	727	break;
	728
	729	case TID_SYNC_CLEAR:
	730	m_audio_sync &= ~param;
	731	break;
628	732	}
629	733	}
630	734
631	735
632		void williams_narc_reset_w(running_machine &machine, int state)
	736	//**************************************************************************
	737	//  ADPCM SOUND BOARD
	738	//**************************************************************************
	739
	740	//-------------------------------------------------
	741	//  williams_adpcm_sound_device - constructor
	742	//-------------------------------------------------
	743
	744	williams_adpcm_sound_device::williams_adpcm_sound_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	745	: device_t(mconfig, WILLIAMS_ADPCM_SOUND, "Williams ADPCM Sound Board", "wmsadpcm", tag, owner, clock),
	746	device_mixer_interface(mconfig, *this),
	747	m_cpu(*this, "cpu"),
	748	m_latch(0),
	749	m_talkback(0),
	750	m_sound_int_state(0)
633	751	{
634		williams_audio_state *sndstate = &audio;
635		device_t *sound_cpu = sndstate->sound_cpu;
636		device_t *soundalt_cpu = sndstate->soundalt_cpu;
	752	}
637	753
638		/* going high halts the CPU */
	754
	755	//-------------------------------------------------
	756	//  write - handle an external write to the input
	757	//   latch
	758	//-------------------------------------------------
	759
	760	WRITE16_MEMBER(williams_adpcm_sound_device::write)
	761	{
	762	synchronize(TID_COMMAND, data);
	763	}
	764
	765
	766	//-------------------------------------------------
	767	//  reset_write - write to the reset line
	768	//-------------------------------------------------
	769
	770	WRITE_LINE_MEMBER(williams_adpcm_sound_device::reset_write)
	771	{
	772	// going high halts the CPU
639	773	if (state)
640	774	{
641		address_space *space = sound_cpu->memory().space(AS_PROGRAM);
642		narc_master_bank_select_w(space, 0, 0);
643		narc_slave_bank_select_w(space, 0, 0);
644		init_audio_state(space->machine());
645		device_set_input_line(sound_cpu, INPUT_LINE_RESET, ASSERT_LINE);
646		device_set_input_line(soundalt_cpu, INPUT_LINE_RESET, ASSERT_LINE);
	775	bank_select_w(*m_cpu->space(), 0, 0);
	776	device_reset();
	777	m_cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
647	778	}
648		/* going low resets and reactivates the CPU */
	779
	780	// going low resets and reactivates the CPU
649	781	else
650		{
651		device_set_input_line(sound_cpu, INPUT_LINE_RESET, CLEAR_LINE);
652		device_set_input_line(soundalt_cpu, INPUT_LINE_RESET, CLEAR_LINE);
653		}
	782	m_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
654	783	}
655	784
656	785
657		int williams_narc_talkback_r(running_machine &machine)
	786	//-------------------------------------------------
	787	//  irq_read - read the sound IRQ state
	788	//-------------------------------------------------
	789
	790	READ_LINE_MEMBER(williams_adpcm_sound_device::irq_read)
658	791	{
659		williams_audio_state *state = &audio;
660
661		return state->audio_talkback | (state->audio_sync << 8);
	792	return m_sound_int_state;
662	793	}
663	794
664	795
	796	//-------------------------------------------------
	797	//  bank_select_w - select the sound CPU memory
	798	//   bank
	799	//-------------------------------------------------
665	800
666		/***************************************************************************
667		ADPCM READ/WRITE HANDLERS
668		****************************************************************************/
669
670		static WRITE8_HANDLER( adpcm_bank_select_w )
	801	WRITE8_MEMBER(williams_adpcm_sound_device::bank_select_w)
671	802	{
672		memory_set_bank(space->machine(), "bank5", data & 0x07);
	803	subbank("rombank")->set_entry(data & 0x07);
673	804	}
674	805
675	806
676		static WRITE8_DEVICE_HANDLER( adpcm_6295_bank_select_w )
	807	//-------------------------------------------------
	808	//  bank_select_w - select the OKI6295 memory
	809	//   bank
	810	//-------------------------------------------------
	811
	812	WRITE8_MEMBER(williams_adpcm_sound_device::oki6295_bank_select_w)
677	813	{
678		downcast<okim6295_device *>(device)->set_bank_base((data & 7) * 0x40000);
	814	subbank("okibank")->set_entry(data & 7);
679	815	}
680	816
681	817
682		static TIMER_CALLBACK( clear_irq_state )
	818	//-------------------------------------------------
	819	//  command_r - read the command from the external
	820	//   latch
	821	//-------------------------------------------------
	822
	823	READ8_MEMBER(williams_adpcm_sound_device::command_r)
683	824	{
684		williams_audio_state *state = &audio;
	825	m_cpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
685	826
686		state->sound_int_state = 0;
	827	// don't clear the external IRQ state for a short while; this allows the
	828	// self-tests to pass
	829	timer_set(attotime::from_usec(10), TID_IRQ_CLEAR);
	830	return m_latch;
687	831	}
688	832
689	833
690		static READ8_HANDLER( adpcm_command_r )
	834	//-------------------------------------------------
	835	//  talkback_w - write to the talkback latch
	836	//-------------------------------------------------
	837
	838	WRITE8_MEMBER(williams_adpcm_sound_device::talkback_w)
691	839	{
692		williams_audio_state *state = &audio;
693		device_t *sound_cpu = state->sound_cpu;
694		device_set_input_line(sound_cpu, M6809_IRQ_LINE, CLEAR_LINE);
695
696		/* don't clear the external IRQ state for a short while; this allows the
697		self-tests to pass */
698		space->machine().scheduler().timer_set(attotime::from_usec(10), FUNC(clear_irq_state));
699		driver_device *drvstate = space->machine().driver_data<driver_device>();
700		return drvstate->soundlatch_byte_r(*space, 0);
	840	m_talkback = data;
	841	logerror("ADPCM Talkback = %02X\n", data);
701	842	}
702	843
703	844
704		static WRITE8_HANDLER( adpcm_talkback_w )
	845	//-------------------------------------------------
	846	//  talkback_w - write to the talkback latch
	847	//-------------------------------------------------
	848
	849	WRITE_LINE_MEMBER(williams_adpcm_sound_device::ym2151_irq_w)
705	850	{
706		williams_audio_state *state = &audio;
707		state->audio_talkback = data;
708		logerror("ADPCM Talkback = %02X\n", data);
	851	m_cpu->set_input_line(M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
709	852	}
710	853
711	854
	855	//-------------------------------------------------
	856	//  audio CPU map
	857	//-------------------------------------------------
712	858
713		/***************************************************************************
714		ADPCM COMMUNICATIONS
715		****************************************************************************/
	859	static ADDRESS_MAP_START( williams_adpcm_map, AS_PROGRAM, 8, williams_adpcm_sound_device )
	860	AM_RANGE(0x0000, 0x1fff) AM_RAM
	861	AM_RANGE(0x2000, 0x2000) AM_MIRROR(0x03ff) AM_WRITE(bank_select_w)
	862	AM_RANGE(0x2400, 0x2401) AM_MIRROR(0x03fe) AM_DEVREADWRITE_LEGACY("ym2151", ym2151_r, ym2151_w)
	863	AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_DEVWRITE_LEGACY("dac", dac_w)
	864	AM_RANGE(0x2c00, 0x2c00) AM_MIRROR(0x03ff) AM_DEVREADWRITE("oki", okim6295_device, read, write)
	865	AM_RANGE(0x3000, 0x3000) AM_MIRROR(0x03ff) AM_READ(command_r)
	866	AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_WRITE(oki6295_bank_select_w)
	867	AM_RANGE(0x3c00, 0x3c00) AM_MIRROR(0x03ff) AM_WRITE(talkback_w)
	868	AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("rombank")
	869	AM_RANGE(0xc000, 0xffff) AM_ROMBANK("romupper")
	870	ADDRESS_MAP_END
716	871
717		void williams_adpcm_data_w(running_machine &machine, int data)
	872
	873	//-------------------------------------------------
	874	//  OKI6295 map
	875	//-------------------------------------------------
	876
	877	static ADDRESS_MAP_START( williams_adpcm_oki_map, AS_0, 8, williams_adpcm_sound_device )
	878	AM_RANGE(0x00000, 0x1ffff) AM_ROMBANK("okibank")
	879	AM_RANGE(0x20000, 0x3ffff) AM_ROM AM_REGION("oki", 0x60000)
	880	ADDRESS_MAP_END
	881
	882
	883	//-------------------------------------------------
	884	//  YM2151 configuration
	885	//-------------------------------------------------
	886
	887	static const ym2151_interface adpcm_ym2151_interface =
718	888	{
719		williams_audio_state *state = &audio;
720		device_t *sound_cpu = state->sound_cpu;
721		address_space *space = sound_cpu->memory().space(AS_PROGRAM);
722		driver_device *drvstate = space->machine().driver_data<driver_device>();
723		drvstate->soundlatch_byte_w(*space, 0, data & 0xff);
724		if (!(data & 0x200))
725		{
726		device_set_input_line(sound_cpu, M6809_IRQ_LINE, ASSERT_LINE);
727		state->sound_int_state = 1;
728		space->machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
729		}
	889	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, williams_adpcm_sound_device, ym2151_irq_w)
	890	};
	891
	892
	893	//-------------------------------------------------
	894	//  machine configuration
	895	//-------------------------------------------------
	896
	897	static MACHINE_CONFIG_FRAGMENT( williams_adpcm_sound )
	898	MCFG_CPU_ADD("cpu", M6809E, ADPCM_MASTER_CLOCK)
	899	MCFG_CPU_PROGRAM_MAP(williams_adpcm_map)
	900
	901	MCFG_SOUND_ADD("ym2151", YM2151, ADPCM_FM_CLOCK)
	902	MCFG_SOUND_CONFIG(adpcm_ym2151_interface)
	903	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.10)
	904
	905	MCFG_SOUND_ADD("dac", DAC, 0)
	906	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.50)
	907
	908	MCFG_OKIM6295_ADD("oki", ADPCM_MASTER_CLOCK/8, OKIM6295_PIN7_HIGH) // clock frequency & pin 7 not verified
	909	MCFG_DEVICE_ADDRESS_MAP(AS_0, williams_adpcm_oki_map)
	910	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.50)
	911	MACHINE_CONFIG_END
	912
	913
	914	//-------------------------------------------------
	915	//  device_mconfig_additions - return a pointer to
	916	//  the device's machine fragment
	917	//-------------------------------------------------
	918
	919	machine_config_constructor williams_adpcm_sound_device::device_mconfig_additions() const
	920	{
	921	return MACHINE_CONFIG_NAME( williams_adpcm_sound );
730	922	}
731	923
732	924
733		void williams_adpcm_reset_w(running_machine &machine, int state)
	925	//-------------------------------------------------
	926	//  device_start - device-specific startup
	927	//-------------------------------------------------
	928
	929	void williams_adpcm_sound_device::device_start()
734	930	{
735		williams_audio_state *sndstate = &audio;
736		device_t *sound_cpu = sndstate->sound_cpu;
	931	// configure banks
	932	UINT8 *rom = subregion("cpu")->base();
	933	subbank("rombank")->configure_entries(0, 8, &rom[0x10000], 0x8000);
	934	subbank("romupper")->set_base(&rom[0x10000 + 0x4000 + 7 * 0x8000]);
737	935
738		/* going high halts the CPU */
739		if (state)
740		{
741		address_space *space = sound_cpu->memory().space(AS_PROGRAM);
742		adpcm_bank_select_w(space, 0, 0);
743		init_audio_state(space->machine());
744		device_set_input_line(sound_cpu, INPUT_LINE_RESET, ASSERT_LINE);
745		}
746		/* going low resets and reactivates the CPU */
747		else
748		device_set_input_line(sound_cpu, INPUT_LINE_RESET, CLEAR_LINE);
	936	// expand ADPCM data
	937	rom = subregion("oki")->base();
	938	// it is assumed that U12 is loaded @ 0x00000 and U13 is loaded @ 0x40000
	939	subbank("okibank")->configure_entry(0, &rom[0x40000]);
	940	subbank("okibank")->configure_entry(1, &rom[0x40000]);
	941	subbank("okibank")->configure_entry(2, &rom[0x20000]);
	942	subbank("okibank")->configure_entry(3, &rom[0x00000]);
	943	subbank("okibank")->configure_entry(4, &rom[0xe0000]);
	944	subbank("okibank")->configure_entry(5, &rom[0xc0000]);
	945	subbank("okibank")->configure_entry(6, &rom[0xa0000]);
	946	subbank("okibank")->configure_entry(7, &rom[0x80000]);
	947
	948	// register for save states
	949	save_item(NAME(m_latch));
	950	save_item(NAME(m_talkback));
	951	save_item(NAME(m_sound_int_state));
749	952	}
750	953
751	954
752		int williams_adpcm_sound_irq_r(running_machine &machine)
	955	//-------------------------------------------------
	956	//  device_reset - device-specific reset
	957	//-------------------------------------------------
	958
	959	void williams_adpcm_sound_device::device_reset()
753	960	{
754		williams_audio_state *state = &audio;
755		return state->sound_int_state;
	961	// reset interrupt states
	962	m_sound_int_state = 0;
	963	m_cpu->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
	964	m_cpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
	965	m_cpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
756	966	}
	967
	968
	969	//-------------------------------------------------
	970	//  device_timer - timer callbacks
	971	//-------------------------------------------------
	972
	973	void williams_adpcm_sound_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	974	{
	975	switch (id)
	976	{
	977	case TID_COMMAND:
	978	m_latch = param & 0xff;
	979	if (!(param & 0x200))
	980	{
	981	m_cpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
	982	m_sound_int_state = 1;
	983	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
	984	}
	985	break;
	986
	987	case TID_IRQ_CLEAR:
	988	m_sound_int_state = 0;
	989	break;
	990	}
	991	}

src/mame/audio/williams.h

r14963	r14964
1	1	/***************************************************************************
2	2
3		Midway/Williams Audio Boards
	3	audio/williams.h
4	4
	5	Functions to emulate general the various Williams/Midway sound cards.
	6
	7	****************************************************************************
	8
	9	Copyright Aaron Giles
	10	All rights reserved.
	11
	12	Redistribution and use in source and binary forms, with or without
	13	modification, are permitted provided that the following conditions are
	14	met:
	15
	16	* Redistributions of source code must retain the above copyright
	17	notice, this list of conditions and the following disclaimer.
	18	* Redistributions in binary form must reproduce the above copyright
	19	notice, this list of conditions and the following disclaimer in
	20	the documentation and/or other materials provided with the
	21	distribution.
	22	* Neither the name 'MAME' nor the names of its contributors may be
	23	used to endorse or promote products derived from this software
	24	without specific prior written permission.
	25
	26	THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
	27	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	28	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	29	DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
	30	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	31	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	32	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	33	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	34	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	35	IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	36	POSSIBILITY OF SUCH DAMAGE.
	37
5	38	****************************************************************************/
6	39
7		MACHINE_CONFIG_EXTERN( williams_cvsd_sound );
8		MACHINE_CONFIG_EXTERN( williams_adpcm_sound );
9		MACHINE_CONFIG_EXTERN( williams_narc_sound );
	40	#include "emu.h"
	41	#include "machine/6821pia.h"
	42	#include "cpu/m6809/m6809.h"
	43	#include "sound/2151intf.h"
	44	#include "sound/okim6295.h"
	45	#include "sound/hc55516.h"
	46	#include "sound/dac.h"
10	47
11		void williams_cvsd_init(running_machine &machine);
12		void williams_cvsd_data_w(running_machine &machine, int data);
13		void williams_cvsd_reset_w(running_machine &machine, int state);
14	48
15		void williams_adpcm_init(running_machine &machine);
16		void williams_adpcm_data_w(running_machine &machine, int data);
17		void williams_adpcm_reset_w(running_machine &machine, int state);
18		int williams_adpcm_sound_irq_r(running_machine &machine);
19	49
20		void williams_narc_init(running_machine &machine);
21		void williams_narc_data_w(running_machine &machine, int data);
22		void williams_narc_reset_w(running_machine &machine, int state);
23		int williams_narc_talkback_r(running_machine &machine);
	50	//**************************************************************************
	51	//  GLOBAL VARIABLES
	52	//**************************************************************************
	53
	54	extern const device_type WILLIAMS_NARC_SOUND;
	55	extern const device_type WILLIAMS_CVSD_SOUND;
	56	extern const device_type WILLIAMS_ADPCM_SOUND;
	57
	58
	59
	60	//**************************************************************************
	61	//  DEVICE CONFIGURATION MACROS
	62	//**************************************************************************
	63
	64	#define MCFG_WILLIAMS_NARC_SOUND_ADD(_tag) \
	65	MCFG_DEVICE_ADD(_tag, WILLIAMS_NARC_SOUND, 0) \
	66
	67	#define MCFG_WILLIAMS_CVSD_SOUND_ADD(_tag) \
	68	MCFG_DEVICE_ADD(_tag, WILLIAMS_CVSD_SOUND, 0) \
	69
	70	#define MCFG_WILLIAMS_ADPCM_SOUND_ADD(_tag) \
	71	MCFG_DEVICE_ADD(_tag, WILLIAMS_ADPCM_SOUND, 0) \
	72
	73
	74
	75	//**************************************************************************
	76	//  TYPE DEFINITIONS
	77	//**************************************************************************
	78
	79	// ======================> williams_cvsd_sound_device
	80
	81	class williams_cvsd_sound_device :   public device_t,
	82	public device_mixer_interface
	83	{
	84	public:
	85	// construction/destruction
	86	williams_cvsd_sound_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	87
	88	// read/write
	89	DECLARE_WRITE16_MEMBER(write);
	90	DECLARE_WRITE_LINE_MEMBER(reset_write);
	91
	92	// internal communications
	93	DECLARE_WRITE8_MEMBER(bank_select_w);
	94	DECLARE_WRITE8_MEMBER(talkback_w);
	95	DECLARE_WRITE8_MEMBER(cvsd_digit_clock_clear_w);
	96	DECLARE_WRITE8_MEMBER(cvsd_clock_set_w);
	97	DECLARE_WRITE_LINE_MEMBER(ym2151_irq_w);
	98	DECLARE_WRITE_LINE_MEMBER(pia_irqa);
	99	DECLARE_WRITE_LINE_MEMBER(pia_irqb);
	100
	101	protected:
	102	// device-level overrides
	103	virtual machine_config_constructor device_mconfig_additions() const;
	104	virtual void device_start();
	105	virtual void device_reset();
	106	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	107
	108	private:
	109	// devices
	110	required_device<m6809e_device> m_cpu;
	111	required_device<pia6821_device> m_pia;
	112	required_device<hc55516_device> m_hc55516;
	113
	114	// internal state
	115	UINT8 m_talkback;
	116	};
	117
	118
	119	// ======================> williams_narc_sound_device
	120
	121	class williams_narc_sound_device :   public device_t,
	122	public device_mixer_interface
	123	{
	124	public:
	125	// construction/destruction
	126	williams_narc_sound_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	127
	128	// read/write
	129	DECLARE_READ16_MEMBER(read);
	130	DECLARE_WRITE16_MEMBER(write);
	131	DECLARE_WRITE_LINE_MEMBER(reset_write);
	132
	133	// internal communications
	134	DECLARE_WRITE8_MEMBER(master_bank_select_w);
	135	DECLARE_WRITE8_MEMBER(slave_bank_select_w);
	136	DECLARE_READ8_MEMBER(command_r);
	137	DECLARE_WRITE8_MEMBER(command2_w);
	138	DECLARE_READ8_MEMBER(command2_r);
	139	DECLARE_WRITE8_MEMBER(master_talkback_w);
	140	DECLARE_WRITE8_MEMBER(master_sync_w);
	141	DECLARE_WRITE8_MEMBER(slave_talkback_w);
	142	DECLARE_WRITE8_MEMBER(slave_sync_w);
	143	DECLARE_WRITE8_MEMBER(cvsd_digit_clock_clear_w);
	144	DECLARE_WRITE8_MEMBER(cvsd_clock_set_w);
	145	DECLARE_WRITE_LINE_MEMBER(ym2151_irq_w);
	146
	147	protected:
	148	// device-level overrides
	149	virtual machine_config_constructor device_mconfig_additions() const;
	150	virtual void device_start();
	151	virtual void device_reset();
	152	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	153
	154	private:
	155	// timer IDs
	156	enum
	157	{
	158	TID_MASTER_COMMAND,
	159	TID_SLAVE_COMMAND,
	160	TID_SYNC_CLEAR
	161	};
	162
	163	// devices
	164	required_device<m6809e_device> m_cpu0;
	165	required_device<m6809e_device> m_cpu1;
	166	required_device<hc55516_device> m_hc55516;
	167
	168	// internal state
	169	UINT8 m_latch;
	170	UINT8 m_latch2;
	171	UINT8 m_talkback;
	172	UINT8 m_audio_sync;
	173	UINT8 m_sound_int_state;
	174	};
	175
	176
	177	// ======================> williams_adpcm_sound_device
	178
	179	class williams_adpcm_sound_device :   public device_t,
	180	public device_mixer_interface
	181	{
	182	public:
	183	// construction/destruction
	184	williams_adpcm_sound_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	185
	186	// read/write
	187	DECLARE_WRITE16_MEMBER(write);
	188	DECLARE_WRITE_LINE_MEMBER(reset_write);
	189	DECLARE_READ_LINE_MEMBER(irq_read);
	190
	191	// internal communications
	192	DECLARE_WRITE8_MEMBER(bank_select_w);
	193	DECLARE_WRITE8_MEMBER(oki6295_bank_select_w);
	194	DECLARE_READ8_MEMBER(command_r);
	195	DECLARE_WRITE8_MEMBER(talkback_w);
	196	DECLARE_WRITE_LINE_MEMBER(ym2151_irq_w);
	197
	198	protected:
	199	// timer IDs
	200	enum
	201	{
	202	TID_COMMAND,
	203	TID_IRQ_CLEAR
	204	};
	205
	206	// device-level overrides
	207	virtual machine_config_constructor device_mconfig_additions() const;
	208	virtual void device_start();
	209	virtual void device_reset();
	210	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	211
	212	private:
	213	// devices
	214	required_device<m6809e_device> m_cpu;
	215
	216	// internal state
	217	UINT8 m_latch;
	218	UINT8 m_talkback;
	219	UINT8 m_sound_int_state;
	220	};
	221
	222

src/mame/machine/midyunit.c

r14963	r14964
7	7	#include "emu.h"
8	8	#include "cpu/tms34010/tms34010.h"
9	9	#include "cpu/m6809/m6809.h"
10		#include "audio/williams.h"
11	10	#include "includes/midyunit.h"
12	11
13	12
r14963	r14964
172	171	if (offset == 0)
173	172	m_term2_analog_select = (data >> 12) & 3;
174	173
175		williams_adpcm_reset_w(machine(), (~data & 0x100) >> 1);
176		williams_adpcm_data_w(machine(), data);
	174	m_adpcm_sound->reset_write((~data & 0x100) >> 1);
	175	m_adpcm_sound->write(space, offset, data);
177	176	}
178	177
179	178
r14963	r14964
298	297	switch (sound)
299	298	{
300	299	case SOUND_CVSD_SMALL:
301		williams_cvsd_init(machine);
302		machine.device("cvsdcpu")->memory().space(AS_PROGRAM)->install_write_handler(prot_start, prot_end, write8_delegate(FUNC(midyunit_state::cvsd_protection_w),state));
	300	machine.device("cvsd:cpu")->memory().space(AS_PROGRAM)->install_write_handler(prot_start, prot_end, write8_delegate(FUNC(midyunit_state::cvsd_protection_w),state));
303	301	state->m_cvsd_protection_base = machine.region("cvsdcpu")->base() + 0x10000 + (prot_start - 0x8000);
304	302	break;
305	303
306	304	case SOUND_CVSD:
307		williams_cvsd_init(machine);
308		machine.device("cvsdcpu")->memory().space(AS_PROGRAM)->install_ram(prot_start, prot_end);
	305	machine.device("cvsd:cpu")->memory().space(AS_PROGRAM)->install_ram(prot_start, prot_end);
309	306	break;
310	307
311	308	case SOUND_ADPCM:
312		williams_adpcm_init(machine);
313		machine.device("adpcm")->memory().space(AS_PROGRAM)->install_ram(prot_start, prot_end);
	309	machine.device("adpcm:cpu")->memory().space(AS_PROGRAM)->install_ram(prot_start, prot_end);
314	310	break;
315	311
316	312	case SOUND_NARC:
317		williams_narc_init(machine);
318		machine.device("narc1cpu")->memory().space(AS_PROGRAM)->install_ram(prot_start, prot_end);
	313	machine.device("narcsnd:cpu0")->memory().space(AS_PROGRAM)->install_ram(prot_start, prot_end);
319	314	break;
320	315
321	316	case SOUND_YAWDIM:
r14963	r14964
559	554	switch (state->m_chip_type)
560	555	{
561	556	case SOUND_NARC:
562		williams_narc_reset_w(machine, 1);
563		williams_narc_reset_w(machine, 0);
	557	state->m_narc_sound->reset_write(1);
	558	state->m_narc_sound->reset_write(0);
564	559	break;
565	560
566	561	case SOUND_CVSD:
567	562	case SOUND_CVSD_SMALL:
568		williams_cvsd_reset_w(machine, 1);
569		williams_cvsd_reset_w(machine, 0);
	563	state->m_cvsd_sound->reset_write(1);
	564	state->m_cvsd_sound->reset_write(0);
570	565	break;
571	566
572	567	case SOUND_ADPCM:
573		williams_adpcm_reset_w(machine, 1);
574		williams_adpcm_reset_w(machine, 0);
	568	state->m_adpcm_sound->reset_write(1);
	569	state->m_adpcm_sound->reset_write(0);
575	570	break;
576	571
577	572	case SOUND_YAWDIM:
r14963	r14964
601	596	switch (m_chip_type)
602	597	{
603	598	case SOUND_NARC:
604		williams_narc_data_w(machine(), data);
	599	m_narc_sound->write(space, offset, data);
605	600	break;
606	601
607	602	case SOUND_CVSD_SMALL:
608	603	case SOUND_CVSD:
609		williams_cvsd_reset_w(machine(), (~data & 0x100) >> 8);
610		williams_cvsd_data_w(machine(), (data & 0xff) | ((data & 0x200) >> 1));
	604	m_cvsd_sound->reset_write((~data & 0x100) >> 8);
	605	m_cvsd_sound->write(space, offset, (data & 0xff) | ((data & 0x200) >> 1));
611	606	break;
612	607
613	608	case SOUND_ADPCM:
614		williams_adpcm_reset_w(machine(), (~data & 0x100) >> 8);
615		williams_adpcm_data_w(machine(), data);
	609	m_adpcm_sound->reset_write((~data & 0x100) >> 8);
	610	m_adpcm_sound->write(space, offset, data);
616	611	break;
617	612
618	613	case SOUND_YAWDIM:

src/mame/machine/midtunit.c

r14963	r14964
7	7	#include "emu.h"
8	8	#include "cpu/tms34010/tms34010.h"
9	9	#include "cpu/m6809/m6809.h"
10		#include "audio/williams.h"
11		#include "audio/dcs.h"
12	10	#include "includes/midtunit.h"
13	11
14	12
r14963	r14964
434	432	{
435	433	case SOUND_ADPCM:
436	434	case SOUND_ADPCM_LARGE:
437		williams_adpcm_init(machine);
438	435	break;
439	436
440	437	case SOUND_DCS:
r14963	r14964
466	463	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x1b00000, 0x1b6ffff, read16_delegate(FUNC(midtunit_state::mk_prot_r),state), write16_delegate(FUNC(midtunit_state::mk_prot_w),state));
467	464
468	465	/* sound chip protection (hidden RAM) */
469		machine.device("adpcm")->memory().space(AS_PROGRAM)->install_ram(0xfb9c, 0xfbc6);
	466	machine.device("adpcm:cpu")->memory().space(AS_PROGRAM)->install_ram(0xfb9c, 0xfbc6);
470	467	}
471	468
472	469	DRIVER_INIT( mkturbo )
r14963	r14964
499	496
500	497	/* sound chip protection (hidden RAM) */
501	498	if (!te_protection)
502		machine.device("adpcm")->memory().space(AS_PROGRAM)->install_ram(0xfbaa, 0xfbd4);
	499	machine.device("adpcm:cpu")->memory().space(AS_PROGRAM)->install_ram(0xfbaa, 0xfbd4);
503	500	else
504		machine.device("adpcm")->memory().space(AS_PROGRAM)->install_ram(0xfbec, 0xfc16);
	501	machine.device("adpcm:cpu")->memory().space(AS_PROGRAM)->install_ram(0xfbec, 0xfc16);
505	502	}
506	503
507	504	DRIVER_INIT( nbajam )
r14963	r14964
527	524	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x1b00000, 0x1bfffff, read16_delegate(FUNC(midtunit_state::jdredd_prot_r),state), write16_delegate(FUNC(midtunit_state::jdredd_prot_w),state));
528	525
529	526	/* sound chip protection (hidden RAM) */
530		machine.device("adpcm")->memory().space(AS_PROGRAM)->install_read_bank(0xfbcf, 0xfbf9, "bank7");
531		machine.device("adpcm")->memory().space(AS_PROGRAM)->install_write_bank(0xfbcf, 0xfbf9, "bank9");
	527	machine.device("adpcm:cpu")->memory().space(AS_PROGRAM)->install_read_bank(0xfbcf, 0xfbf9, "bank7");
	528	machine.device("adpcm:cpu")->memory().space(AS_PROGRAM)->install_write_bank(0xfbcf, 0xfbf9, "bank9");
532	529	memory_set_bankptr(machine, "bank9", auto_alloc_array(machine, UINT8, 0x80));
533	530
534	531	#if ENABLE_ALL_JDREDD_LEVELS
r14963	r14964
574	571
575	572	MACHINE_RESET( midtunit )
576	573	{
	574	midtunit_state *state = machine.driver_data<midtunit_state>();
577	575	/* reset sound */
578	576	switch (chip_type)
579	577	{
580	578	case SOUND_ADPCM:
581	579	case SOUND_ADPCM_LARGE:
582		williams_adpcm_reset_w(machine, 1);
583		williams_adpcm_reset_w(machine, 0);
	580	state->m_adpcm_sound->reset_write(1);
	581	state->m_adpcm_sound->reset_write(0);
584	582	break;
585	583
586	584	case SOUND_DCS:
r14963	r14964
633	631	}
634	632
635	633	/* call through based on the sound type */
	634	midtunit_state *state = space.machine().driver_data<midtunit_state>();
636	635	if (ACCESSING_BITS_0_7 && ACCESSING_BITS_8_15)
637	636	switch (chip_type)
638	637	{
639	638	case SOUND_ADPCM:
640	639	case SOUND_ADPCM_LARGE:
641		williams_adpcm_reset_w(machine(), ~data & 0x100);
642		williams_adpcm_data_w(machine(), data & 0xff);
	640	state->m_adpcm_sound->reset_write(~data & 0x100);
	641	state->m_adpcm_sound->write(space, offset, data & 0xff);
643	642
644	643	/* the games seem to check for $82 loops, so this should be just barely enough */
645	644	fake_sound_state = 128;

src/mame/machine/mcr68.c

r14963	r14964
5	5	***************************************************************************/
6	6
7	7	#include "emu.h"
8		#include "audio/mcr.h"
	8	#include "audio/midway.h"
9	9	#include "includes/mcr.h"
10	10	#include "includes/mcr68.h"
11	11
r14963	r14964
171	171
172	172	/* initialize the clock */
173	173	state->m_m6840_internal_counter_period = attotime::from_hz(machine.device("maincpu")->unscaled_clock() / 10);
174
175		/* initialize the sound */
176		mcr_sound_reset(machine);
177	174	}
178	175
179	176
r14963	r14964
296	293	{
297	294	mcr68_state *drvstate = device->machine().driver_data<mcr68_state>();
298	295	address_space *space = device->machine().device("maincpu")->memory().space(AS_PROGRAM);
299		drvstate->csdeluxe_data_w(*space, 0, (state << 4) | drvstate->m_zwackery_sound_data);
	296	drvstate->m_chip_squeak_deluxe->write(*space, 0, (state << 4) | drvstate->m_zwackery_sound_data);
300	297	}
301	298
302	299

src/mame/machine/snes.c

r14963	r14964
1838	1838	}
1839	1839
1840	1840
1841		DIRECT_UPDATE_HANDLER( snes_spc_direct )
	1841	DIRECT_UPDATE_MEMBER(snes_state::snes_spc_direct)
1842	1842	{
1843		direct.explicit_configure(0x0000, 0xffff, 0xffff, spc_get_ram(machine.device("spc700")));
	1843	direct.explicit_configure(0x0000, 0xffff, 0xffff, spc_get_ram(machine().device("spc700")));
1844	1844	return ~0;
1845	1845	}
1846	1846
1847		DIRECT_UPDATE_HANDLER( snes_direct )
	1847	DIRECT_UPDATE_MEMBER(snes_state::snes_direct)
1848	1848	{
1849	1849	direct.explicit_configure(0x0000, 0xffff, 0xffff, snes_ram);
1850	1850	return ~0;
r14963	r14964
1860	1860	state->m_spc700 = machine.device<snes_sound_device>("spc700");
1861	1861	state->m_superfx = machine.device<cpu_device>("superfx");
1862	1862
1863		state->m_maincpu->space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(snes_direct), &machine));
1864		state->m_soundcpu->space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(snes_spc_direct), &machine));
	1863	state->m_maincpu->space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(snes_state::snes_direct), state));
	1864	state->m_soundcpu->space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(snes_state::snes_spc_direct), state));
1865	1865
1866	1866	// power-on sets these registers like this
1867	1867	snes_ram[WRIO] = 0xff;

src/mame/machine/atarigen.c

r14963	r14964
455	455	}
456	456
457	457
458		DIRECT_UPDATE_HANDLER( atarigen_slapstic_setdirect )
	458	DIRECT_UPDATE_MEMBER(atarigen_state::atarigen_slapstic_setdirect)
459	459	{
460		atarigen_state *state = machine.driver_data<atarigen_state>();
461
462	460	/* if we jump to an address in the slapstic region, tweak the slapstic
463	461	at that address and return ~0; this will cause us to be called on
464	462	subsequent fetches as well */
465		address &= ~state->m_slapstic_mirror;
466		if (address >= state->m_slapstic_base && address < state->m_slapstic_base + 0x8000)
	463	address &= ~m_slapstic_mirror;
	464	if (address >= m_slapstic_base && address < m_slapstic_base + 0x8000)
467	465	{
468	466	offs_t pc = cpu_get_previouspc(&direct.space().device());
469		if (pc != state->m_slapstic_last_pc || address != state->m_slapstic_last_address)
	467	if (pc != m_slapstic_last_pc || address != m_slapstic_last_address)
470	468	{
471		state->m_slapstic_last_pc = pc;
472		state->m_slapstic_last_address = address;
	469	m_slapstic_last_pc = pc;
	470	m_slapstic_last_address = address;
473	471	atarigen_slapstic_r(&direct.space(), (address >> 1) & 0x3fff, 0xffff);
474	472	}
475	473	return ~0;
r14963	r14964
514	512	state->m_slapstic_mirror = mirror;
515	513
516	514	address_space *space = downcast<cpu_device *>(device)->space(AS_PROGRAM);
517		space->set_direct_update_handler(direct_update_delegate(FUNC(atarigen_slapstic_setdirect), &device->machine()));
	515	space->set_direct_update_handler(direct_update_delegate(FUNC(atarigen_state::atarigen_slapstic_setdirect), state));
518	516	}
519	517	}
520	518

src/mame/machine/atarigen.h

r14963	r14964
188	188	UINT32               m_playfield2_latch;
189	189
190	190	atarigen_screen_timer   m_screen_timer[2];
	191
	192	DECLARE_DIRECT_UPDATE_MEMBER(atarigen_slapstic_setdirect);
191	193	};
192	194
193	195

src/mame/machine/mcr.c

r14963	r14964
5	5	***************************************************************************/
6	6
7	7	#include "emu.h"
8		#include "audio/mcr.h"
	8	#include "audio/midway.h"
9	9	#include "includes/mcr.h"
10	10
11	11	#define VERBOSE 0
r14963	r14964
174	174	{
175	175	/* reset cocktail flip */
176	176	mcr_cocktail_flip = 0;
177
178		/* initialize the sound */
179		mcr_sound_reset(machine);
180	177	}
181	178
182	179
r14963	r14964
228	225
229	226	/*************************************
230	227	*
231		*  Generic MCR port write handlers
232		*
233		*************************************/
234
235		WRITE8_MEMBER(mcr_state::mcr_control_port_w)
236		{
237		/*
238		Bit layout is as follows:
239		D7 = n/c
240		D6 = cocktail flip
241		D5 = red LED
242		D4 = green LED
243		D3 = n/c
244		D2 = coin meter 3
245		D1 = coin meter 2
246		D0 = coin meter 1
247		*/
248
249		coin_counter_w(machine(), 0, (data >> 0) & 1);
250		coin_counter_w(machine(), 1, (data >> 1) & 1);
251		coin_counter_w(machine(), 2, (data >> 2) & 1);
252		mcr_cocktail_flip = (data >> 6) & 1;
253		}
254
255
256		/*************************************
257		*
258	228	*  NFL Football IPU board
259	229	*
260	230	*************************************/

src/mame/machine/williams.c

r14963	r14964
5	5	***************************************************************************/
6	6
7	7	#include "emu.h"
8		#include "audio/williams.h"
9	8	#include "cpu/m6800/m6800.h"
10	9	#include "cpu/m6809/m6809.h"
11	10	#include "machine/6821pia.h"
r14963	r14964
988	987	{
989	988	williams_state *state = machine.driver_data<williams_state>();
990	989	MACHINE_START_CALL(williams2);
991		williams_cvsd_init(machine);
992	990	state_save_register_global(machine, state->m_joust2_current_sound_data);
993	991	}
994	992
995	993
996	994	MACHINE_RESET( joust2 )
997	995	{
998		pia6821_device *pia_3 = machine.device<pia6821_device>("cvsdpia");
999
1000		/* standard init */
1001	996	MACHINE_RESET_CALL(williams2);
1002		pia_3->ca1_w(1);
1003	997	}
1004	998
1005	999
r14963	r14964
1013	1007	static WRITE8_DEVICE_HANDLER( joust2_pia_3_cb1_w )
1014	1008	{
1015	1009	williams_state *state = device->machine().driver_data<williams_state>();
1016		pia6821_device *pia_3 = device->machine().device<pia6821_device>("cvsdpia");
1017
1018	1010	state->m_joust2_current_sound_data = (state->m_joust2_current_sound_data & ~0x100) | ((data << 8) & 0x100);
1019		pia_3->cb1_w(data);
	1011	state->m_cvsd_sound->write(*device->machine().memory().first_space(), 0, state->m_joust2_current_sound_data);
1020	1012	}
1021	1013
1022	1014
r14963	r14964
1024	1016	{
1025	1017	williams_state *state = device->machine().driver_data<williams_state>();
1026	1018	state->m_joust2_current_sound_data = (state->m_joust2_current_sound_data & ~0xff) | (data & 0xff);
1027		williams_cvsd_data_w(device->machine(), state->m_joust2_current_sound_data);
	1019	state->m_cvsd_sound->write(*device->machine().memory().first_space(), 0, state->m_joust2_current_sound_data);
1028	1020	device->machine().scheduler().synchronize(FUNC(joust2_deferred_snd_cmd_w), state->m_joust2_current_sound_data);
1029	1021	}

src/mame/machine/opwolf.c

r14963	r14964
718	718	{
719	719	opwolf_state *state = machine.driver_data<opwolf_state>();
720	720
721		//TODO:FIX
722		//state->m_cchip_ram = auto_alloc_array_clear(machine, UINT8, 0x400 * 8);
	721	state->m_cchip_ram.allocate(0x400 * 8);
723	722
724	723	state->save_item(NAME(state->m_current_bank));
725	724	state->save_item(NAME(state->m_current_cmd));
r14963	r14964
732	731	state->save_item(NAME(state->m_cchip_coins));
733	732	state->save_item(NAME(state->m_cchip_coins_for_credit));
734	733	state->save_item(NAME(state->m_cchip_credits_for_coin));
735		//state->save_pointer(NAME(state->m_cchip_ram), 0x400 * 8);
736	734
737	735	state->m_current_bank = 0;
738	736	state->m_current_cmd = 0;

src/mame/machine/bfm_bd1.c

r14963	r14964
26	26	UINT8   scroll_active,      // flag <>0, scrolling active
27	27	display_mode,      // display scroll   mode, 0/1/2/3
28	28	display_blanking,   // display blanking mode, 0/1/2/3
	29	blank_flag,
29	30	flash_rate,         // flash rate 0-F
30		flash_control;      // flash control 0/1/2/3
	31	flash_control,      // flash control 0/1/2/3
	32	flash_flag;
31	33
32	34	UINT8   string[18];         // text buffer
33	35	UINT32  segments[16],      // segments
r14963	r14964
278	280	{
279	281	case 0x80:   // 0x80 - 0x8F Set display blanking
280	282
281		bd1[id].display_blanking = data & 0x0F;
282		change = 1;
	283	//TODO: Implement this, MAME artwork not mature enough
	284	switch ( data & 0x04 )
	285	{
	286	case 0x00:   // blank all
	287	break;
	288	case 0x01:   // blank inside window
	289	break;
	290
	291	case 0x02:   // blank outside window
	292	break;
	293
	294	case 0x03:   // blank entire display
	295	break;
	296
	297	case 0x04:   // futaba setup
	298
	299	bd1[id].blank_flag = 1;
	300	break;
	301	}
283	302	break;
284	303
285	304	case 0x90:   // 0x90 - 0x9F Set cursor pos
r14963	r14964
382	401
383	402	default:
384	403
385		change = BD1_setdata(id, BD1charset[data & 0x3F], data);
	404	if (bd1[id].blank_flag || bd1[id].flash_flag)
	405	{
	406	if (bd1[id].blank_flag)
	407	{
	408	bd1[id].display_blanking = data & 0x0F;
	409	change = 1;
	410	bd1[id].blank_flag = 0;
	411	}
	412	if (bd1[id].flash_flag)
	413	{
	414	//not setting yet
	415	bd1[id].blank_flag = 0;
	416	}
	417	}
	418	else
	419	{
	420
	421	if (data > 0x3F)
	422	{
	423	//   logerror("Undefined character %x \n", data);
	424	}
	425	change = BD1_setdata(id, BD1charset[data & 0x3F], data);
	426	}
386	427	break;
387	428	}
388	429	return change;
r14963	r14964
409	450
410	451	static int BD1_setdata(int id, int segdata, int data)
411	452	{
	453
412	454	int change = 0, move = 0;
413	455
414	456	switch ( data )

src/mame/includes/nmk16.h

r14963	r14964
18	18
19	19	int mask[4*2];
20	20	required_shared_ptr<UINT16> m_nmk_bgvideoram0;
21		required_shared_ptr<UINT16> m_nmk_txvideoram;
	21	optional_shared_ptr<UINT16> m_nmk_txvideoram;
22	22	required_shared_ptr<UINT16> m_mainram;
23	23	optional_shared_ptr<UINT16> m_gunnail_scrollram;
24	24	optional_shared_ptr<UINT8> m_spriteram;

src/mame/includes/rainbow.h

r14963	r14964
12	12	m_spriteram(*this, "spriteram"){ }
13	13
14	14	/* memory pointers */
15		required_shared_ptr<UINT16> m_spriteram;
	15	optional_shared_ptr<UINT16> m_spriteram;
16	16	//  UINT16 *    paletteram;    // currently this uses generic palette handling
17	17
18	18	/* video-related */

src/mame/includes/aerofgt.h

r14963	r14964
15	15
16	16	/* memory pointers */
17	17	required_shared_ptr<UINT16> m_bg1videoram;
18		required_shared_ptr<UINT16> m_bg2videoram;
19		required_shared_ptr<UINT16> m_rasterram;
	18	optional_shared_ptr<UINT16> m_bg2videoram;
	19	optional_shared_ptr<UINT16> m_rasterram;
20	20	optional_shared_ptr<UINT16> m_bitmapram;
21		required_shared_ptr<UINT16> m_spriteram1;
22		required_shared_ptr<UINT16> m_spriteram2;
	21	optional_shared_ptr<UINT16> m_spriteram1;
	22	optional_shared_ptr<UINT16> m_spriteram2;
23	23	required_shared_ptr<UINT16> m_spriteram3;
24	24	optional_shared_ptr<UINT16> m_tx_tilemap_ram;
25	25	//  UINT16 *  m_paletteram;   // currently this uses generic palette handling

src/mame/includes/midyunit.h

r14963	r14964
5	5	**************************************************************************/
6	6
7	7	#include "cpu/tms34010/tms34010.h"
	8	#include "audio/williams.h"
8	9	#include "machine/nvram.h"
9	10
10	11	/* protection data types */
r14963	r14964
32	33	public:
33	34	midyunit_state(const machine_config &mconfig, device_type type, const char *tag)
34	35	: driver_device(mconfig, type, tag),
	36	m_narc_sound(*this, "narcsnd"),
	37	m_cvsd_sound(*this, "cvsd"),
	38	m_adpcm_sound(*this, "adpcm"),
35	39	m_gfx_rom(*this, "gfx_rom", 16) { }
36	40
	41	optional_device<williams_narc_sound_device> m_narc_sound;
	42	optional_device<williams_cvsd_sound_device> m_cvsd_sound;
	43	optional_device<williams_adpcm_sound_device> m_adpcm_sound;
	44
37	45	UINT16 *m_cmos_ram;
38	46	UINT32 m_cmos_page;
39	47	optional_shared_ptr<UINT8> m_gfx_rom;

src/mame/includes/galpani2.h

r14963	r14964
5	5	public:
6	6	galpani2_state(const machine_config &mconfig, device_type type, const char *tag)
7	7	: kaneko16_state(mconfig, type, tag),
	8	m_bg8(*this, "bg8"),
	9	m_palette(*this, "palette"),
	10	m_bg8_scrollx(*this, "bg8_scrollx"),
	11	m_bg8_scrolly(*this, "bg8_scrolly"),
	12	m_bg15(*this, "bg15"),
	13	m_ram(*this, "ram"),
	14	m_ram2(*this, "ram2"),
	15	m_rombank(*this, "rombank"),
8	16	m_maincpu(*this,"maincpu"),
9	17	m_subcpu(*this,"sub")
10	18	{ }
11	19
12		UINT16 *m_bg8[2];
13		UINT16 *m_palette[2];
14		UINT16 *m_bg8_scrollx[2];
15		UINT16 *m_bg8_scrolly[2];
16		UINT16 *m_bg15;
	20	required_shared_ptr_array<UINT16, 2> m_bg8;
	21	optional_shared_ptr_array<UINT16, 2> m_palette;
	22	required_shared_ptr_array<UINT16, 2> m_bg8_scrollx;
	23	required_shared_ptr_array<UINT16, 2> m_bg8_scrolly;
	24	required_shared_ptr<UINT16> m_bg15;
17	25	UINT16 m_eeprom_word;
18		UINT16 *m_ram;
19		UINT16 *m_ram2;
	26	required_shared_ptr<UINT16> m_ram;
	27	required_shared_ptr<UINT16> m_ram2;
20	28	UINT16 m_old_mcu_nmi1;
21	29	UINT16 m_old_mcu_nmi2;
22		UINT16 *m_rombank;
	30	required_shared_ptr<UINT16> m_rombank;
23	31	bitmap_ind16 *m_bg8_bitmap[2];
24	32	bitmap_ind16 *m_bg15_bitmap;
25	33

src/mame/includes/midtunit.h

r14963	r14964
4	4
5	5	**************************************************************************/
6	6
	7	#include "audio/williams.h"
	8	#include "audio/dcs.h"
	9
7	10	class midtunit_state : public driver_device
8	11	{
9	12	public:
10	13	midtunit_state(const machine_config &mconfig, device_type type, const char *tag)
11	14	: driver_device(mconfig, type, tag),
12		m_nvram(*this, "nvram") { }
	15	m_nvram(*this, "nvram"),
	16	m_cvsd_sound(*this, "cvsd"),
	17	m_adpcm_sound(*this, "adpcm") { }
13	18
14	19	required_shared_ptr<UINT16>   m_nvram;
	20	optional_device<williams_cvsd_sound_device> m_cvsd_sound;
	21	optional_device<williams_adpcm_sound_device> m_adpcm_sound;
	22
15	23	DECLARE_WRITE16_MEMBER(midtunit_cmos_enable_w);
16	24	DECLARE_WRITE16_MEMBER(midtunit_cmos_w);
17	25	DECLARE_READ16_MEMBER(midtunit_cmos_r);

src/mame/includes/seta2.h

r14963	r14964
5	5	: driver_device(mconfig, type, tag),
6	6	m_maincpu(*this,"maincpu"),
7	7	m_nvram(*this, "nvram") ,
8		m_spriteram(*this, "spriteram"),
9		m_vregs(*this, "vregs"),
	8	m_spriteram(*this, "spriteram", 0),
	9	m_vregs(*this, "vregs", 0),
10	10	m_coldfire_regs(*this, "coldfire_regs"),
11	11	m_funcube_outputs(*this, "funcube_outputs"),
12	12	m_funcube_leds(*this, "funcube_leds"){ }

src/mame/includes/itech32.h

r14963	r14964
19	19	public:
20	20	itech32_state(const machine_config &mconfig, device_type type, const char *tag)
21	21	: driver_device(mconfig, type, tag) ,
22		m_main_ram(*this, "main_ram"),
23		m_nvram(*this, "nvram"),
24		m_video(*this, "video"),
25		m_main_rom(*this, "main_rom"),
	22	m_main_ram(*this, "main_ram", 0),
	23	m_nvram(*this, "nvram", 0),
	24	m_video(*this, "video", 0),
	25	m_main_rom(*this, "main_rom", 0),
26	26	m_drivedge_zbuf_control(*this, "drivedge_zctl"),
27	27	m_tms1_boot(*this, "tms1_boot"),
28	28	m_tms1_ram(*this, "tms1_ram"),

src/mame/includes/fitfight.h

r14963	r14964
49	49	DECLARE_WRITE16_MEMBER(fof_bak_tileram_w);
50	50	DECLARE_WRITE16_MEMBER(fof_mid_tileram_w);
51	51	DECLARE_WRITE16_MEMBER(fof_txt_tileram_w);
	52
	53	DECLARE_READ16_MEMBER( hotmindff_unk_r );
52	54	};
53	55
54	56

src/mame/includes/argus.h

r14963	r14964
13	13	m_spriteram(*this, "spriteram"),
14	14	m_butasan_bg1ram(*this, "butasan_bg1ram"){ }
15	15
16		required_shared_ptr<UINT8> m_bg0_scrollx;
17		required_shared_ptr<UINT8> m_bg0_scrolly;
	16	optional_shared_ptr<UINT8> m_bg0_scrollx;
	17	optional_shared_ptr<UINT8> m_bg0_scrolly;
18	18	required_shared_ptr<UINT8> m_bg1_scrollx;
19	19	required_shared_ptr<UINT8> m_bg1_scrolly;
20	20	required_shared_ptr<UINT8> m_paletteram;

src/mame/includes/fastfred.h

r14963	r14964
11	11	{
12	12	public:
13	13	fastfred_state(const machine_config &mconfig, device_type type, const char *tag)
14		: galaxold_state(mconfig, type, tag) { }
	14	: galaxold_state(mconfig, type, tag),
	15	m_videoram(*this, "videoram"),
	16	m_spriteram(*this, "spriteram"),
	17	m_attributesram(*this, "attributesram"),
	18	m_background_color(*this, "bgcolor"),
	19	m_imago_fg_videoram(*this, "imago_fg_vram") { }
15	20
16	21	UINT8 m_imago_sprites[0x800*3];
17	22	UINT16 m_imago_sprites_address;
18	23	UINT8 m_imago_sprites_bank;
19	24	int m_hardware_type;
20		UINT8 *m_videoram;
21		UINT8 *m_spriteram;
22		size_t m_spriteram_size;
23		UINT8 *m_attributesram;
24		UINT8 *m_background_color;
25		UINT8 *m_imago_fg_videoram;
	25	required_shared_ptr<UINT8> m_videoram;
	26	required_shared_ptr<UINT8> m_spriteram;
	27	required_shared_ptr<UINT8> m_attributesram;
	28	optional_shared_ptr<UINT8> m_background_color;
	29	optional_shared_ptr<UINT8> m_imago_fg_videoram;
26	30	UINT16 m_charbank;
27	31	UINT8 m_colorbank;
28	32	tilemap_t *m_bg_tilemap;

src/mame/includes/galpanic.h

r14963	r14964
4	4	{
5	5	public:
6	6	galpanic_state(const machine_config &mconfig, device_type type, const char *tag)
7		: kaneko16_state(mconfig, type, tag) { }
	7	: kaneko16_state(mconfig, type, tag),
	8	m_bgvideoram(*this, "bgvideoram"),
	9	m_fgvideoram(*this, "fgvideoram"),
	10	m_spriteram(*this, "spriteram") { }
8	11
9		UINT16 *m_bgvideoram;
10		UINT16 *m_fgvideoram;
11		size_t m_fgvideoram_size;
	12	required_shared_ptr<UINT16> m_bgvideoram;
	13	required_shared_ptr<UINT16> m_fgvideoram;
12	14	bitmap_ind16 m_bitmap;
13	15	bitmap_ind16 m_sprites_bitmap;
14		UINT16 *m_spriteram;
15		size_t m_spriteram_size;
	16	required_shared_ptr<UINT16> m_spriteram;
16	17	DECLARE_WRITE16_MEMBER(galpanic_6295_bankswitch_w);
17	18	DECLARE_WRITE16_MEMBER(galpanica_6295_bankswitch_w);
18	19	DECLARE_WRITE16_MEMBER(galpanica_misc_w);

src/mame/includes/cclimber.h

r14963	r14964
18	18
19	19	required_shared_ptr<UINT8> m_bigsprite_videoram;
20	20	required_shared_ptr<UINT8> m_videoram;
21		required_shared_ptr<UINT8> m_column_scroll;
	21	optional_shared_ptr<UINT8> m_column_scroll;
22	22	required_shared_ptr<UINT8> m_spriteram;
23	23	required_shared_ptr<UINT8> m_bigsprite_control;
24	24	required_shared_ptr<UINT8> m_colorram;

src/mame/includes/kaneko16.h

r14963	r14964
92	92	optional_shared_ptr<UINT16> m_spriteram;
93	93	optional_shared_ptr<UINT16> m_bg15_reg;
94	94	optional_shared_ptr<UINT16> m_bg15_select;
95		required_shared_ptr<UINT16> m_sprites_regs;
	95	optional_shared_ptr<UINT16> m_sprites_regs;
96	96	optional_shared_ptr_array<UINT16,4> m_vram;
97	97	optional_shared_ptr_array<UINT16,4> m_vscroll;
98		required_shared_ptr<UINT16> m_layers_0_regs;
	98	optional_shared_ptr<UINT16> m_layers_0_regs;
99	99	optional_shared_ptr<UINT16> m_layers_1_regs;
100		required_shared_ptr<UINT16> m_mcu_ram;
101		required_shared_ptr<UINT16> m_mainram;
	100	optional_shared_ptr<UINT16> m_mcu_ram;
	101	optional_shared_ptr<UINT16> m_mainram;
102	102
103	103	UINT8 m_nvram_save[128];
104	104	int m_sprite_type;

src/mame/includes/system16.h

r14963	r14964
16	16	required_shared_ptr<UINT16> m_textram;
17	17	optional_shared_ptr<UINT16> m_bg0_tileram;
18	18	optional_shared_ptr<UINT16> m_bg1_tileram;
19		required_shared_ptr<UINT16> m_tileram;
	19	optional_shared_ptr<UINT16> m_tileram;
20	20	optional_shared_ptr<UINT16> m_goldnaxeb2_bgpage;
21	21	optional_shared_ptr<UINT16> m_goldnaxeb2_fgpage;
22	22

src/mame/includes/suna8.h

r14963	r14964
13	13	m_wram(*this, "wram"){ }
14	14
15	15	required_device<cpu_device> m_maincpu;
16		required_shared_ptr<UINT8> m_hardhead_ip;
17		required_shared_ptr<UINT8> m_spriteram;
18		required_shared_ptr<UINT8> m_wram;
	16	optional_shared_ptr<UINT8> m_hardhead_ip;
	17	optional_shared_ptr<UINT8> m_spriteram;
	18	optional_shared_ptr<UINT8> m_wram;
19	19
20	20	UINT8 m_rombank;
21	21	UINT8 m_spritebank;

src/mame/includes/nova2001.h

r14963	r14964
8	8	m_spriteram(*this, "spriteram"){ }
9	9
10	10	UINT8 m_ninjakun_io_a002_ctrl;
11		required_shared_ptr<UINT8> m_fg_videoram;
	11	optional_shared_ptr<UINT8> m_fg_videoram;
12	12	required_shared_ptr<UINT8> m_bg_videoram;
13	13	tilemap_t *m_bg_tilemap;
14	14	tilemap_t *m_fg_tilemap;
15		required_shared_ptr<UINT8> m_spriteram;
	15	optional_shared_ptr<UINT8> m_spriteram;
16	16	DECLARE_WRITE8_MEMBER(ninjakun_cpu1_io_A002_w);
17	17	DECLARE_WRITE8_MEMBER(ninjakun_cpu2_io_A002_w);
18	18	DECLARE_WRITE8_MEMBER(ninjakun_paletteram_w);

src/mame/includes/flstory.h

r14963	r14964
13	13	required_shared_ptr<UINT8> m_videoram;
14	14	required_shared_ptr<UINT8> m_spriteram;
15	15	required_shared_ptr<UINT8> m_scrlram;
16		required_shared_ptr<UINT8> m_workram;
	16	optional_shared_ptr<UINT8> m_workram;
17	17	//  UINT8 *  m_paletteram;    // currently this uses generic palette handling
18	18	//  UINT8 *  m_paletteram_2;  // currently this uses generic palette handling
19	19

src/mame/includes/model2.h

r14963	r14964
29	29	required_shared_ptr<UINT32> m_textureram0;
30	30	required_shared_ptr<UINT32> m_textureram1;
31	31	required_shared_ptr<UINT32> m_lumaram;
32		required_shared_ptr<UINT16> m_soundram;
	32	optional_shared_ptr<UINT16> m_soundram;
33	33	optional_shared_ptr<UINT32> m_tgp_program;
34	34
35	35	UINT32 m_intreq;

src/mame/includes/toaplan1.h

r14963	r14964
18	18	required_shared_ptr<UINT16> m_colorram1;
19	19	required_shared_ptr<UINT16> m_colorram2;
20	20
21		required_shared_ptr<UINT8> m_sharedram;
	21	optional_shared_ptr<UINT8> m_sharedram;
22	22
23	23	int m_coin_count; /* coin count increments on startup ? , so dont count it */
24	24	int m_intenable;

src/mame/includes/tmnt.h

r14963	r14964
11	11	m_tmnt2_1c0800(*this, "tmnt2_1c0800"){ }
12	12
13	13	/* memory pointers */
14		required_shared_ptr<UINT16> m_spriteram;
	14	optional_shared_ptr<UINT16> m_spriteram;
15	15	optional_shared_ptr<UINT16> m_tmnt2_rom;
16	16	optional_shared_ptr<UINT16> m_sunset_104000;
17	17	optional_shared_ptr<UINT16> m_tmnt2_1c0800;

src/mame/includes/scramble.h

r14963	r14964
5	5	{
6	6	public:
7	7	scramble_state(const machine_config &mconfig, device_type type, const char *tag)
8		: galaxold_state(mconfig, type, tag) { }
	8	: galaxold_state(mconfig, type, tag),
	9	m_soundram(*this, "soundram") { }
9	10
10		UINT8 *m_soundram;
	11	required_shared_ptr<UINT8> m_soundram;
11	12	UINT8 m_cavelon_bank;
12	13	UINT8 m_security_2B_counter;
13	14	UINT8 m_xb;

src/mame/includes/qix.h

r14963	r14964
33	33	m_scanline_latch(*this, "scanline_latch") { }
34	34
35	35	/* machine state */
36		required_shared_ptr<UINT8> m_68705_port_out;
37		required_shared_ptr<UINT8> m_68705_ddr;
	36	optional_shared_ptr<UINT8> m_68705_port_out;
	37	optional_shared_ptr<UINT8> m_68705_ddr;
38	38	UINT8  m_68705_port_in[3];
39	39	UINT8  m_coinctrl;
40	40
41	41	/* video state */
42		required_shared_ptr<UINT8> m_videoram;
	42	optional_shared_ptr<UINT8> m_videoram;
43	43	required_shared_ptr<UINT8> m_videoram_address;
44	44	optional_shared_ptr<UINT8> m_videoram_mask;
45	45	required_shared_ptr<UINT8> m_paletteram;

src/mame/includes/snes.h

r14963	r14964
487	487	cpu_device *m_superfx;
488	488	upd7725_device *m_upd7725;
489	489	upd96050_device *m_upd96050;
	490
	491	DECLARE_DIRECT_UPDATE_MEMBER(snes_spc_direct);
	492	DECLARE_DIRECT_UPDATE_MEMBER(snes_direct);
490	493	};
491	494
492	495	/* Special chips, checked at init and used in memory handlers */

src/mame/includes/cps3.h

r14963	r14964
98	98	DECLARE_WRITE32_MEMBER(cps3_unk_vidregs_w);
99	99	DECLARE_READ32_MEMBER(cps3_colourram_r);
100	100	DECLARE_WRITE32_MEMBER(cps3_colourram_w);
	101	DECLARE_DIRECT_UPDATE_MEMBER(cps3_direct_handler);
101	102	};
102	103
103	104

src/mame/includes/wecleman.h

r14963	r14964
11	11	m_spriteram(*this, "spriteram"),
12	12	m_roadram(*this, "roadram"){ }
13	13
14		required_shared_ptr<UINT16> m_videostatus;
15		required_shared_ptr<UINT16> m_protection_ram;
	14	optional_shared_ptr<UINT16> m_videostatus;
	15	optional_shared_ptr<UINT16> m_protection_ram;
16	16	required_shared_ptr<UINT16> m_blitter_regs;
17		required_shared_ptr<UINT16> m_pageram;
	17	optional_shared_ptr<UINT16> m_pageram;
18	18	optional_shared_ptr<UINT16> m_txtram;
19	19	required_shared_ptr<UINT16> m_spriteram;
20	20	required_shared_ptr<UINT16> m_roadram;

src/mame/includes/alpha68k.h

r14963	r14964
18	18	required_shared_ptr<UINT16> m_shared_ram;
19	19	required_shared_ptr<UINT16> m_spriteram;
20	20	required_shared_ptr<UINT16> m_videoram;
21		required_shared_ptr<UINT16> m_paletteram;
	21	optional_shared_ptr<UINT16> m_paletteram;
22	22
23	23	/* video-related */
24	24	tilemap_t     *m_fix_tilemap;

src/mame/includes/cischeat.h

r14963	r14964
12	12	m_f1gpstr2_ioready(*this, "ioready"){ }
13	13
14	14	required_shared_ptr<UINT16> m_vregs;
15		required_shared_ptr_array<UINT16,3> m_scrollram;
	15	optional_shared_ptr_array<UINT16,3> m_scrollram;
16	16	required_shared_ptr<UINT16> m_ram;
17		required_shared_ptr_array<UINT16,2> m_roadram;
	17	optional_shared_ptr_array<UINT16,2> m_roadram;
18	18	optional_shared_ptr<UINT16> m_f1gpstr2_ioready;
19	19
20	20	UINT16 *m_objectram;

src/mame/includes/centiped.h

r14963	r14964
14	14	m_spriteram(*this, "spriteram"),
15	15	m_bullsdrt_tiles_bankram(*this, "bullsdrt_bank"){ }
16	16
17		required_shared_ptr<UINT8> m_rambase;
	17	optional_shared_ptr<UINT8> m_rambase;
18	18	required_shared_ptr<UINT8> m_videoram;
19	19	required_shared_ptr<UINT8> m_spriteram;
20	20	optional_shared_ptr<UINT8> m_bullsdrt_tiles_bankram;

src/mame/includes/atarig42.h

r14963	r14964
43	43	DECLARE_WRITE16_MEMBER(guardians_sloop_data_w);
44	44	void roadriot_sloop_tweak(int offset);
45	45	void guardians_sloop_tweak(int offset);
	46	DECLARE_DIRECT_UPDATE_MEMBER(atarig42_sloop_direct_handler);
46	47	};
47	48
48	49

src/mame/includes/midvunit.h

r14963	r14964
42	42	m_nvram(*this, "nvram"),
43	43	m_ram_base(*this, "ram_base"),
44	44	m_fastram_base(*this, "fastram_base"),
45		m_tms32031_control(*this, "tms32031_control"),
	45	m_tms32031_control(*this, "32031_control"),
46	46	m_midvplus_misc(*this, "midvplus_misc"),
47		m_videoram(*this, "videoram"),
	47	m_videoram(*this, "videoram", 32),
48	48	m_textureram(*this, "textureram") { }
49	49
50	50	optional_shared_ptr<UINT32>   m_nvram;
51	51	required_shared_ptr<UINT32> m_ram_base;
52		required_shared_ptr<UINT32> m_fastram_base;
	52	optional_shared_ptr<UINT32> m_fastram_base;
53	53	required_shared_ptr<UINT32> m_tms32031_control;
54		required_shared_ptr<UINT32> m_midvplus_misc;
	54	optional_shared_ptr<UINT32> m_midvplus_misc;
55	55	required_shared_ptr<UINT16> m_videoram;
56	56	required_shared_ptr<UINT32> m_textureram;
57	57

src/mame/includes/atarisy2.h

r14963	r14964
67	67	DECLARE_WRITE8_MEMBER(tms5220_w);
68	68	DECLARE_WRITE8_MEMBER(tms5220_strobe_w);
69	69	DECLARE_WRITE8_MEMBER(coincount_w);
	70	DECLARE_DIRECT_UPDATE_MEMBER(atarisy2_direct_handler);
70	71	};
71	72
72	73

src/mame/includes/ninjakd2.h

r14963	r14964
11	11	UINT8 m_omegaf_io_protection[3];
12	12	UINT8 m_omegaf_io_protection_input;
13	13	int m_omegaf_io_protection_tic;
14		required_shared_ptr<UINT8> m_bg_videoram;
	14	optional_shared_ptr<UINT8> m_bg_videoram;
15	15	required_shared_ptr<UINT8> m_fg_videoram;
16	16	int m_next_sprite_overdraw_enabled;
17	17	int (*m_stencil_compare_function) (UINT16 pal);

src/mame/includes/ojankohs.h

r14963	r14964
14	14	m_paletteram(*this, "paletteram"){ }
15	15
16	16	/* memory pointers */
17		required_shared_ptr<UINT8> m_videoram;
18		required_shared_ptr<UINT8> m_colorram;
	17	optional_shared_ptr<UINT8> m_videoram;
	18	optional_shared_ptr<UINT8> m_colorram;
19	19	optional_shared_ptr<UINT8> m_paletteram;
20	20
21	21	/* video-related */

src/mame/includes/n8080.h

r14963	r14964
9	9
10	10	/* memory pointers */
11	11	required_shared_ptr<UINT8> m_videoram;
12		required_shared_ptr<UINT8> m_colorram;     // for helifire
	12	optional_shared_ptr<UINT8> m_colorram;     // for helifire
13	13
14	14	/* video-related */
15	15	emu_timer* m_cannon_timer;

src/mame/includes/liberate.h

r14963	r14964
10	10	m_spriteram(*this, "spriteram"),
11	11	m_scratchram(*this, "scratchram"){ }
12	12
13		required_shared_ptr<UINT8> m_paletteram;
	13	optional_shared_ptr<UINT8> m_paletteram;
14	14	optional_shared_ptr<UINT8> m_bg_vram; /* prosport */
15	15	required_shared_ptr<UINT8> m_colorram;
16	16	required_shared_ptr<UINT8> m_videoram;

src/mame/includes/plygonet.h

r14963	r14964
63	63	DECLARE_WRITE32_MEMBER(polygonet_ttl_ram_w);
64	64	DECLARE_READ32_MEMBER(polygonet_roz_ram_r);
65	65	DECLARE_WRITE32_MEMBER(polygonet_roz_ram_w);
	66	DIRECT_UPDATE_MEMBER(plygonet_dsp56k_direct_handler);
66	67	};
67	68
68	69	/*----------- defined in video/plygonet.c -----------*/

src/mame/includes/bfm_sc45.h

r14963	r14964
46	46	bool m_dochk41;
47	47
48	48
	49	DECLARE_WRITE8_MEMBER(mux_output_w);
	50	DECLARE_WRITE8_MEMBER(mux_output2_w);
49	51
50	52	DECLARE_READ16_MEMBER(sc4_mem_r);
51	53	DECLARE_WRITE16_MEMBER(sc4_mem_w);
r14963	r14964
78	80	PORT_DIPSETTING(    0x06, "6" ) \
79	81	PORT_DIPSETTING(    0x07, "500GBP (club)" ) \
80	82	PORT_DIPSETTING(    0x08, "5GBP" ) \
81		PORT_DIPSETTING(    0x09, "9" ) \
82		PORT_DIPSETTING(    0x0a, "4GBP / 25GBP" ) \
	83	PORT_DIPSETTING(    0x09, "15GBP" ) \
	84	PORT_DIPSETTING(    0x0a, "25GBP (4GBP, Maz)" ) \
83	85	PORT_DIPSETTING(    0x0b, "11" ) \
84	86	PORT_DIPSETTING(    0x0c, "35GBP" ) \
85	87	PORT_DIPSETTING(    0x0d, "70GBP" ) \
r14963	r14964
141	143	ROM_LOAD( "95008527.bin", 0x0000, 0x0ff5c3, CRC(6fac2014) SHA1(5b364406f7b5d8f4c54561e3977571e4a47273a0) ) \
142	144
143	145	#define sc_adwta_others \
144		ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
	146	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) /* PR1940 ADSNT SHOWTIME SOUNDS11 */ \
	147	ROM_LOAD( "95008656.bin", 0x000000, 0x100000, CRC(632a4cbb) SHA1(455e6242f5c5c1a0d84aadfdda33873e8e7b2418) ) \
	148	ROM_LOAD( "95008657.bin", 0x100000, 0x100000, CRC(aa68db50) SHA1(52ee314549fac989dd9ee494144ee3bbb99ee283) ) \
145	149
146	150	#define sc_aztec_others \
147	151	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
r14963	r14964
234	238
235	239	#define sc_bonbx_others \
236	240	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
237		ROM_LOAD( "95008992.bin", 0x0000, 0x0aa536, CRC(aad10089) SHA1(d8a32f66432ee901be05435e8930d3897f4b4e33) ) /* BARX - right header, wrong sounds */ \
	241	ROM_LOAD( "95008992.bin", 0x0000, 0x0aa536, CRC(aad10089) SHA1(d8a32f66432ee901be05435e8930d3897f4b4e33) ) /* BARX - right header, wrong sounds? */ \
	242	ROM_LOAD( "95009015.bin", 0x0000, 0x0b7821, CRC(8b6ca362) SHA1(4c50935b6d1038738ce631fbdc359416197b8c03) ) /* BARX - right header, wrong sounds? */ \
238	243
239	244	#define sc_brksp_others \
240	245	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
r14963	r14964
1178	1183
1179	1184	#define sc_gd_others \
1180	1185	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1181		/* PR1016 GOLD DIG SOUNDS11 */ \
	1186	/* PR1016 GOLD DIG SOUNDS11 (game header actually lists PR1016 GOLD DIGGER SOUNDS11 but it accepts these) */ \
1182	1187	ROM_LOAD( "95008187.bin", 0x000000, 0x100000, CRC(1fbbc7cc) SHA1(6e19b582a3654bbbcf65b8f42bd556029f43e8cb) ) \
1183	1188	ROM_LOAD( "95008188.bin", 0x100000, 0x100000, CRC(a74b23a7) SHA1(f7948edfb5524eaf80039c07ca7a9f76883f5a6f) ) \
	1189	ROM_REGION( 0x400000, "others", ROMREGION_ERASE00 ) \
1184	1190	/* PR3509 GOLD DIGGER SOUNDS11 */ \
1185	1191	ROM_LOAD( "95009061.bin", 0x000000, 0x100000, CRC(c4cad720) SHA1(ce67af8d9e0b2f4f79d38b7a01dfc5ff7323e162) ) \
1186	1192	ROM_LOAD( "95009062.bin", 0x100000, 0x100000, CRC(509761d3) SHA1(6a133cc33bac6a1696de98a4961572a86cefc1c8) ) \
1187	1193
	1194
1188	1195	#define sc_gdmz_others \
1189	1196	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1190	1197	ROM_LOAD( "95008980.bin", 0x0000, 0x0fe431, CRC(c09277a0) SHA1(227609194f7d7e8b00cbd5cb94f8679f8fff71c6) ) \
r14963	r14964
1228	1235	ROM_LOAD( "95008367.bin", 0x000000, 0x100000, CRC(37eea219) SHA1(e612b2c0bca83d742b35fbaf487b6805cfac024d) ) \
1229	1236	ROM_LOAD( "95008368.bin", 0x100000, 0x100000, CRC(06549054) SHA1(923a320f9689361802dc82db467b294f7bc85147) ) \
1230	1237
	1238	#define PR1327_CAS_HAPPY_NOTES_SOUNDS11 \
	1239	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
	1240	ROM_LOAD( "95008312.bin", 0x000000, 0x100000, CRC(cf33e14d) SHA1(33382be257a145784d9de7050b5c90f725241de4) ) \
	1241
1231	1242	#define sc_hapnt_others \
1232	1243	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1233	1244	/* PR1306 HAPPY NOTES SOUNDS11 */ \
1234	1245	ROM_LOAD( "95008290.bin", 0x000000, 0x100000, CRC(427fc43d) SHA1(c63154c7f2bb3e7ec78e31268a8040d0eb131f2f) ) \
1235		/* PR1327 CAS_HAPPY_NOTES SOUNDS11 */ \
1236		ROM_LOAD( "95008312.bin", 0x100000, 0x100000, CRC(cf33e14d) SHA1(33382be257a145784d9de7050b5c90f725241de4) ) \
1237	1246
1238	1247	#define sc_hfcl_others \
1239	1248	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
r14963	r14964
1494	1503	ROM_LOAD( "95890728.bin", 0x0000, 0x5000, CRC(0c3acfbc) SHA1(ff39c8236d5bd44c7d238edd1827af5aebc46e5c) ) \
1495	1504	ROM_LOAD( "95890729.bin", 0x0000, 0x5000, CRC(cf60ed2c) SHA1(df015b71567d6762b4c8ea6ad6d719cefdfdc60f) ) \
1496	1505
	1506	#define PR1706_WHEEL_OF_WEALTH_SOUNDS11 \
	1507	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
	1508	ROM_LOAD( "95008550.bin", 0x000000, 0x100000, CRC(db6343bf) SHA1(e4d702020af67aa5be0560027706c1cbf34296fa) ) \
	1509
	1510	#define WHEEL_OF_WEALTH_WOWT_SOUNDS \
	1511	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
	1512	ROM_LOAD( "95008869.bin", 0x000000, 0x0b9d9d, CRC(f3ef3bbb) SHA1(92f9835e96c4fc444a451e97b2b8a7b66e5794b7) ) \
	1513
	1514
1497	1515	#define sc_mowow_others \
1498	1516	ROM_REGION( 0x5000, "pics", 0 ) \
1499	1517	ROM_LOAD( "95890712.bin", 0x0000, 0x5000, CRC(ec6db00b) SHA1(d16a1527caa3c115e3326c897ce0fa66e3a0420d) ) \
1500	1518	ROM_LOAD( "95890713.bin", 0x0000, 0x5000, CRC(f0bb40b7) SHA1(33c19dab3086cdeae4f503fbf3f3cc5f0dad98c4) ) \
1501	1519	ROM_LOAD( "95890714.bin", 0x0000, 0x5000, CRC(33e16227) SHA1(87efc1a046ef6af0b72cc76a6ee393a4d1ddbce3) ) \
1502	1520	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1503		/* PR1706 WHEEL OF WEALTH SOUNDS11 */ \
1504		ROM_LOAD( "95008550.bin", 0x000000, 0x100000, CRC(db6343bf) SHA1(e4d702020af67aa5be0560027706c1cbf34296fa) ) \
1505		/* 95008551 STEPITS5 PR1666 */ \
	1521	/* WOW SOUNDS - wrong for this game, wants "WOTW SOUNDS" */ \
	1522	ROM_LOAD( "95008850.bin", 0x000000, 0x0af41f, CRC(8ca16e09) SHA1(9b494ad6946c2c7bbfad6591e62fa699fd53b6dc) ) \
	1523	ROM_REGION( 0x400000, "others", ROMREGION_ERASE00 ) \
	1524	/* 95008551 STEPITS5 PR1666  - wrong game?? */ \
1506	1525	ROM_LOAD( "95008551.bin", 0x100000, 0x100000, CRC(2d89a52a) SHA1(244101df7f6beae545f9b823750f908f532ac1e4) ) \
1507		/* WOW SOUNDS */ \
1508		ROM_LOAD( "95008850.bin", 0x000000, 0x0af41f, CRC(8ca16e09) SHA1(9b494ad6946c2c7bbfad6591e62fa699fd53b6dc) ) \
1509		/* WOWT SOUNDS */ \
1510		ROM_LOAD( "95008869.bin", 0x000000, 0x0b9d9d, CRC(f3ef3bbb) SHA1(92f9835e96c4fc444a451e97b2b8a7b66e5794b7) ) \
1511	1526
	1527
1512	1528	#define sc_nmare_others \
1513	1529	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1514	1530	/* PR3002 ELM STREET SOUNDS11 */ \
r14963	r14964
1775	1791	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) /* PR3013 SHOWTIME SOUNDS11 */ \
1776	1792	ROM_LOAD( "95008734.bin", 0x000000, 0x100000, CRC(8b469657) SHA1(514b3f4cbbafb3cee618b9ce0bae572f1a4fcf7b) ) \
1777	1793	ROM_LOAD( "95008735.bin", 0x100000, 0x100000, CRC(fa614cc1) SHA1(e5ecce4936a8db267b08b938ab5bc7500cf98f99) ) \
1778		ROM_REGION( 0x400000, "others1", ROMREGION_ERASE00 ) /* PR1940 ADSNT SHOWTIME SOUNDS11 */ \
1779		ROM_LOAD( "95008656.bin", 0x000000, 0x100000, CRC(632a4cbb) SHA1(455e6242f5c5c1a0d84aadfdda33873e8e7b2418) ) \
1780		ROM_LOAD( "95008657.bin", 0x100000, 0x100000, CRC(aa68db50) SHA1(52ee314549fac989dd9ee494144ee3bbb99ee283) ) \
1781	1794	ROM_REGION( 0x400000, "others2", ROMREGION_ERASE00 ) /* PR3243 SHOWTIME SOUNDS11 */ \
1782	1795	ROM_LOAD( "95008777.bin", 0x000000, 0x100000, CRC(1ff19229) SHA1(6db08982ee923ef4568caf76e05088574f99fc36) ) \
1783	1796	ROM_LOAD( "95008778.bin", 0x100000, 0x100000, CRC(2f2f3ee1) SHA1(cade826fec6c07a1fffa548c96404da83db14dd7) ) \
r14963	r14964
1942	1955	#define sc_mrrcl_others \
1943	1956	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1944	1957
1945		#define sc_gball_pthers \
	1958	#define PR1034_GOLDEN_BALLS_SOUNDS11 \
1946	1959	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1947		/* PR1034 GOLDEN BALLS SOUNDS11 */ \
1948	1960	ROM_LOAD( "95008161.bin", 0x000000, 0x080000, CRC(ecd13fd9) SHA1(51d11b9133d4e840ce9afd7cf716520ea0fc0343) ) \
1949	1961	ROM_LOAD( "95008162.bin", 0x080000, 0x080000, CRC(b4b4a5c5) SHA1(d0748decfaee7da52d2f6a4bc0877be4243ed6fb) ) \
	1962
	1963	#define sc_gball_pthers \
	1964	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1950	1965	/* PR1604 GOLDEN BALLS SOUNDS12 */ \
1951	1966	ROM_LOAD( "95008465.bin", 0x000000, 0x100000, CRC(5d1fa2c9) SHA1(c12de2b89f0bcb8f1b35630fffd205fd9d5b9777) ) \
1952	1967	ROM_LOAD( "95008466.bin", 0x100000, 0x100000, CRC(418068ab) SHA1(342939e9bcc1d213bc2f52666cc3765442e18635) ) \
r14963	r14964
1957	1972
1958	1973	#define sc_ggame_others \
1959	1974	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
	1975	ROM_LOAD( "95008992.bin", 0x0000, 0x0aa536, CRC(aad10089) SHA1(d8a32f66432ee901be05435e8930d3897f4b4e33) ) /* BARX */ \
	1976	ROM_REGION( 0x400000, "others", ROMREGION_ERASE00 ) \
1960	1977	ROM_LOAD( "95008515.bin", 0x0000, 0x0ab5c3, CRC(70cd8480) SHA1(2da34a0c1d9d84471005f5d6491499e707c0b0d4) ) /* KGXDX */  \
1961	1978	ROM_LOAD( "95008958.bin", 0x0000, 0x0435d3, CRC(31ffdb64) SHA1(e48cfa2e5b158555b4ba204fc1175810b81cbbed) ) /* MULTIGG */ \
1962		ROM_LOAD( "95008992.bin", 0x0000, 0x0aa536, CRC(aad10089) SHA1(d8a32f66432ee901be05435e8930d3897f4b4e33) ) /* BARX */ \
1963	1979	ROM_REGION( 0x5000, "pics", 0 ) \
1964	1980	ROM_LOAD( "95890410.bin", 0x0000, 0x5000, CRC(9588ae1d) SHA1(ae45d9e0272b2b048b99e337def1acfb2524597e) ) \
1965	1981	ROM_LOAD( "95890411.bin", 0x0000, 0x5000, CRC(895e5ea1) SHA1(070df49baca709f69fa1e522b21e42b716af0ba5) ) \
r14963	r14964
1967	1983
1968	1984	#define sc_ggg_others \
1969	1985	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1970		ROM_LOAD( "95008992.bin", 0x0000, 0x0aa536, CRC(aad10089) SHA1(d8a32f66432ee901be05435e8930d3897f4b4e33) ) \
1971		ROM_LOAD( "95009015.bin", 0x0000, 0x0b7821, CRC(8b6ca362) SHA1(4c50935b6d1038738ce631fbdc359416197b8c03) ) \
	1986	ROM_LOAD( "95009015.bin", 0x0000, 0x0b7821, CRC(8b6ca362) SHA1(4c50935b6d1038738ce631fbdc359416197b8c03) ) /* BARX SOUNDS */ \
	1987	ROM_REGION( 0x400000, "others", ROMREGION_ERASE00 ) \
	1988	ROM_LOAD( "95008992.bin", 0x0000, 0x0aa536, CRC(aad10089) SHA1(d8a32f66432ee901be05435e8930d3897f4b4e33) ) /* BARX SOUNDS */ \
1972	1989	ROM_REGION( 0x400000, "pivs", ROMREGION_ERASE00 ) \
1973	1990	ROM_LOAD( "95890730.bin", 0x0000, 0x5000, CRC(9673d1ce) SHA1(fee90139fc8de5e7b6dfe741b4852a363c17eb93) ) \
1974	1991	ROM_LOAD( "95890731.bin", 0x0000, 0x5000, CRC(8aa52172) SHA1(441a649e3da00556a8ea966a88ee9b58b4943d3b) ) \
r14963	r14964
1980	1997	#define sc_gnc_others \
1981	1998	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1982	1999
1983		#define sc_hellb_others \
	2000	#define SC4_95004211_HELLS_BELLS_PR6945 \
1984	2001	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
1985		/* 95004211 HELLS BELLS PR6945 */ \
1986	2002	ROM_LOAD( "95004211.bin", 0x0000, 0x080000, CRC(2e729642) SHA1(c8dcdce52f930b3fa894c46907691a28a5499a16) ) \
1987		/* PR1402 HELLS BELLS SOUNDS11 */ \
	2003
	2004	#define sc_hellb_others \
	2005	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) /* PR1402 HELLS BELLS SOUNDS11 */ \
1988	2006	ROM_LOAD( "95008341.bin", 0x0000, 0x100000, CRC(486e5395) SHA1(0ad68f271f4839d50a790b7f4427e1f1f1933bd4) ) \
1989	2007
1990	2008	#define sc_leg_others \
r14963	r14964
2019	2037	ROM_LOAD( "95008684.bin", 0x000000, 0x100000, CRC(52b7d26e) SHA1(ba6629dbad8d00c132c0ddf6a8a41ddc99231c75) ) \
2020	2038	ROM_LOAD( "95008685.bin", 0x100000, 0x100000, CRC(dc9717c0) SHA1(27234bb7c7e7bd1f395972ce2958d55e84005313) ) \
2021	2039
2022		#define sc_pacmn_others \
	2040	#define QPS_PACP_SOUNDS \
2023	2041	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
2024		ROM_LOAD( "95004183", 0x000000, 0x080000, CRC(4b28f610) SHA1(fff01c890a8c109bb4b522ee2391c15abdc2758c) ) \
2025		ROM_LOAD( "95004184", 0x080000, 0x080000, CRC(bee11fdd) SHA1(b5ce97108812e296c92a000444c1fb7a11286de4) ) \
2026		ROM_LOAD( "95004199.lo", 0x000000, 0x080000, CRC(3a9605c8) SHA1(ce1c94fe26eac9e145e94539f62f2bde740e5b9a) ) \
2027		ROM_LOAD( "95004199.hi", 0x080000, 0x080000, CRC(0ecfc531) SHA1(15e20eedf4b7d9102c40834612d111559b4dcbca) ) \
	2042	/* PACP SOUNDS */ \
2028	2043	ROM_LOAD( "97000000.evn", 0x000000, 0x080000, CRC(5b13fe7b) SHA1(1bd32e577914ab4e3bc3282261f8c3cdf015b85d) ) /* pacp */ \
2029	2044	ROM_LOAD( "97000000.odd", 0x080000, 0x080000, CRC(8bab1c78) SHA1(ddc915a8c56473ba4d67d8c62c66105dd622b593) ) \
2030	2045
	2046	#define PACMAN_SOUNDS \
	2047	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
	2048	/* PACMAN SOUNDS */   \
	2049	ROM_LOAD( "95004183", 0x000000, 0x080000, CRC(4b28f610) SHA1(fff01c890a8c109bb4b522ee2391c15abdc2758c) ) \
	2050	ROM_LOAD( "95004184", 0x080000, 0x080000, CRC(bee11fdd) SHA1(b5ce97108812e296c92a000444c1fb7a11286de4) ) \
	2051
	2052
2031	2053	#define sc_paccs_others \
2032	2054	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
	2055	ROM_LOAD( "95004199.lo", 0x000000, 0x080000, CRC(3a9605c8) SHA1(ce1c94fe26eac9e145e94539f62f2bde740e5b9a) ) \
	2056	ROM_LOAD( "95004199.hi", 0x080000, 0x080000, CRC(0ecfc531) SHA1(15e20eedf4b7d9102c40834612d111559b4dcbca) ) \
2033	2057
2034	2058	#define sc_paccl_others \
2035	2059	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
2036	2060	ROM_LOAD( "95008145.bin", 0x0000, 0x100000, CRC(e2ec54f8) SHA1(bb1c40b13151ed1e3c7ba603506701457392bb8b) ) \
2037		ROM_LOAD( "pacmancsnd.bin", 0x0000, 0x0bbb33, CRC(c505aa18) SHA1(a99bd1c4101269e2eb2b6becf210d9991fee1da1) ) \
	2061	ROM_LOAD( "pacmancsnd.bin", 0x0000, 0x0bbb33, CRC(c505aa18) SHA1(a99bd1c4101269e2eb2b6becf210d9991fee1da1) ) /* identical but cut at 0xff bytes */ \
2038	2062
2039	2063	#define sc_pacpl_others \
2040	2064	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
r14963	r14964
2670	2694	ROM_LOAD( "95004224.sn1", 0x000000, 0x080000, CRC(74382d29) SHA1(bd0323b7208e9b03e2d8468f7d4603fb4a3fe394) ) \
2671	2695	ROM_LOAD( "95004225.sn2", 0x080000, 0x080000, CRC(23efa88d) SHA1(af52ec3dcb45a2ea26eaa273c783134402105168) ) \
2672	2696
	2697	#define SC4_95004316_CAS_PHAR_GOLD_PR1261 \
	2698	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
	2699	ROM_LOAD( "95004316.snd", 0x000000, 0x080000, CRC(94a9ec9c) SHA1(bab1a431e2857b9db9fa3f3ef28f150e19c4ae50) ) /* casino */ \
	2700
2673	2701	#define sc_pgold_others \
2674	2702	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
2675		ROM_LOAD( "95004316.snd", 0x000000, 0x080000, CRC(94a9ec9c) SHA1(bab1a431e2857b9db9fa3f3ef28f150e19c4ae50) ) /* casino */ \
2676	2703	ROM_LOAD( "95008141.bin", 0x000000, 0x100000, CRC(e1b214dc) SHA1(811f6ec42961496f8cd9fb3434ab6a07457ca61a) ) \
2677	2704	ROM_LOAD( "95008142.bin", 0x100000, 0x100000, CRC(faa84d52) SHA1(f5139df5e9ff95fab3c01ac2b1aa44b1d939bf7a) ) \
2678	2705
r14963	r14964
3017	3044	ROM_REGION( 0x400000, "ymz", ROMREGION_ERASE00 ) \
3018	3045
3019	3046	#define sc_clbtm_others \
3020		ROM_REGION( 0x800000, "ymz", ROMREGION_ERASE00 ) \
3021		/* very large sound roms! */ \
3022		ROM_LOAD( "95008055.p1", 0x0000, 0x800000, CRC(ef474fd3) SHA1(e7427184683603b57a3a8b37452fa6ec7a41e34c) ) \
3023		ROM_LOAD( "95008056.p2", 0x0000, 0x800000, CRC(39b1b566) SHA1(937ec27964124b92b75d4b37d09a35585baa68c6) ) \
	3047	ROM_REGION( 0x1000000, "ymz", ROMREGION_ERASE00 ) \
	3048	/* very large sound roms! - overdumps.. mostly garbage (cut them) */ \
	3049	ROM_LOAD( "95008055.p1", 0x00000, 0x80000, CRC(ef474fd3) SHA1(e7427184683603b57a3a8b37452fa6ec7a41e34c) ) \
	3050	ROM_IGNORE(0x780000) \
	3051	ROM_LOAD( "95008056.p2", 0x80000, 0x80000, CRC(39b1b566) SHA1(937ec27964124b92b75d4b37d09a35585baa68c6) ) \
	3052	ROM_IGNORE(0x780000) \
3024	3053	\
	3054	ROM_REGION( 0x1000000, "others2", ROMREGION_ERASE00 ) \
3025	3055	ROM_LOAD( "95008055.bin", 0x0000, 0x100000, CRC(df9ae6e3) SHA1(5766cb1749aa92c34a76270a641f7a9302cc44d7) ) \
3026	3056	\
3027	3057	ROM_REGION( 0x400000, "others", ROMREGION_ERASE00 ) \
3028		/* dot matrix roms? */ \
	3058	/* dot matrix roms? - for the SC1 version? */ \
3029	3059	ROM_LOAD( "club-temptation_mtx_(ihex)ss.hex", 0x0000, 0x01d0da, CRC(08ebee96) SHA1(2e87d734c966abab1d4a59c9481ebea161f77286) ) \
3030	3060	ROM_LOAD( "clubtempdot.bin", 0x0000, 0x010000, CRC(283d2d9c) SHA1(5b76a13ad674f8a40c270e5dbc61dac04d411d02) ) /* DM01 */ \
3031	3061	ROM_LOAD( "95717692a.bin", 0x0000, 0x008000, CRC(f9fe7b9a) SHA1(0e3fe5da9fc837726d08f02a2c6ed782f016c982) ) /* is this something else? sc1/2? */ \

src/mame/includes/bloodbro.h

r14963	r14964
13	13	required_shared_ptr<UINT16> m_bgvideoram;
14	14	required_shared_ptr<UINT16> m_fgvideoram;
15	15	required_shared_ptr<UINT16> m_txvideoram;
16		required_shared_ptr<UINT16> m_scroll;
	16	optional_shared_ptr<UINT16> m_scroll;
17	17
18	18	tilemap_t *m_bg_tilemap;
19	19	tilemap_t *m_fg_tilemap;

src/mame/includes/unico.h

r14963	r14964
7	7	m_scroll(*this, "scroll"),
8	8	m_vram32(*this, "vram32"),
9	9	m_scroll32(*this, "scroll32"),
10		m_spriteram(*this, "spriteram"){ }
	10	m_spriteram(*this, "spriteram", 0){ }
11	11
12		required_shared_ptr<UINT16> m_vram;
13		required_shared_ptr<UINT16> m_scroll;
	12	optional_shared_ptr<UINT16> m_vram;
	13	optional_shared_ptr<UINT16> m_scroll;
14	14	optional_shared_ptr<UINT32> m_vram32;
15	15	optional_shared_ptr<UINT32> m_scroll32;
16	16	tilemap_t *m_tilemap[3];
17	17	int m_sprites_scrolldx;
18	18	int m_sprites_scrolldy;
19		required_shared_ptr<UINT16> m_spriteram;
	19	optional_shared_ptr<UINT16> m_spriteram;
20	20	DECLARE_WRITE16_MEMBER(zeropnt_sound_bank_w);
21	21	DECLARE_READ16_MEMBER(unico_gunx_0_msb_r);
22	22	DECLARE_READ16_MEMBER(unico_guny_0_msb_r);

src/mame/includes/realbrk.h

r14963	r14964
18	18	required_shared_ptr<UINT16> m_vram_1;
19	19	required_shared_ptr<UINT16> m_vram_2;
20	20	required_shared_ptr<UINT16> m_vregs;
21		required_shared_ptr<UINT16> m_dsw_select;
	21	optional_shared_ptr<UINT16> m_dsw_select;
22	22	optional_shared_ptr<UINT16> m_backup_ram;
23	23	optional_shared_ptr<UINT16> m_vram_0ras;
24	24	optional_shared_ptr<UINT16> m_vram_1ras;

src/mame/includes/astrocde.h

r14963	r14964
22	22	m_videoram(*this, "videoram"),
23	23	m_protected_ram(*this, "protected_ram"){ }
24	24
25		required_shared_ptr<UINT8> m_videoram;
	25	optional_shared_ptr<UINT8> m_videoram;
26	26	UINT8 m_video_config;
27	27	UINT8 m_sparkle[4];
28	28	char m_totalword[256];

src/mame/includes/cninja.h

r14963	r14964
44	44	required_shared_ptr<UINT16> m_pf2_rowscroll;
45	45	required_shared_ptr<UINT16> m_pf3_rowscroll;
46	46	required_shared_ptr<UINT16> m_pf4_rowscroll;
47		required_shared_ptr<UINT16> m_ram;
	47	optional_shared_ptr<UINT16> m_ram;
48	48
49	49	/* misc */
50	50	int        m_scanline;

src/mame/includes/midwunit.h

r14963	r14964
9	9	public:
10	10	midwunit_state(const machine_config &mconfig, device_type type, const char *tag)
11	11	: midtunit_state(mconfig, type, tag),
12		m_nvram(*this, "nvram") { }
	12	m_nvram(*this, "nvram"),
	13	m_decode_memory(*this, "decode_memory", 16) { }
13	14
14	15	required_shared_ptr<UINT16>   m_nvram;
15		UINT8 *m_decode_memory;
	16	required_shared_ptr<UINT8> m_decode_memory;
16	17	UINT8 m_cmos_write_enable;
17	18	UINT16 m_iodata[8];
18	19	UINT8 m_ioshuffle[16];

src/mame/includes/tatsumi.h

r14963	r14964
22	22	m_roundup_l_ram(*this, "roundup_l_ram"),
23	23	m_spriteram(*this, "spriteram") { }
24	24
25		required_shared_ptr<UINT16> m_videoram;
26		required_shared_ptr<UINT16> m_cyclwarr_cpua_ram;
27		required_shared_ptr<UINT16> m_cyclwarr_cpub_ram;
	25	optional_shared_ptr<UINT16> m_videoram;
	26	optional_shared_ptr<UINT16> m_cyclwarr_cpua_ram;
	27	optional_shared_ptr<UINT16> m_cyclwarr_cpub_ram;
28	28	UINT16 m_bigfight_a20000[8];
29	29	UINT16 m_bigfight_a60000[2];
30		required_shared_ptr<UINT16> m_apache3_g_ram;
	30	optional_shared_ptr<UINT16> m_apache3_g_ram;
31	31	UINT16 m_bigfight_a40000[2];
32	32	UINT8 *m_rom_sprite_lookup1;
33	33	UINT8 *m_rom_sprite_lookup2;
r14963	r14964
38	38	optional_shared_ptr<UINT16> m_roundup5_unknown0;
39	39	optional_shared_ptr<UINT16> m_roundup5_unknown1;
40	40	optional_shared_ptr<UINT16> m_roundup5_unknown2;
41		required_shared_ptr<UINT16> m_68k_ram;
42		required_shared_ptr<UINT8> m_apache3_z80_ram;
	41	optional_shared_ptr<UINT16> m_68k_ram;
	42	optional_shared_ptr<UINT8> m_apache3_z80_ram;
43	43	UINT16 m_control_word;
44	44	UINT16 m_apache3_rotate_ctrl[12];
45	45	required_shared_ptr<UINT16> m_sprite_control_ram;

src/mame/includes/meadows.h

r14963	r14964
14	14	m_spriteram(*this, "spriteram"),
15	15	m_videoram(*this, "videoram"){ }
16	16
17		required_shared_ptr<UINT8> m_spriteram;
	17	optional_shared_ptr<UINT8> m_spriteram;
18	18	required_shared_ptr<UINT8> m_videoram;
19	19	UINT8 m_dac;
20	20	int m_dac_enable;

src/mame/includes/m72.h

r14963	r14964
21	21	required_shared_ptr<UINT16> m_videoram2;
22	22	optional_shared_ptr<UINT16> m_majtitle_rowscrollram;
23	23	optional_shared_ptr<UINT16> m_spriteram2;
24		required_shared_ptr<UINT8> m_soundram;
	24	optional_shared_ptr<UINT8> m_soundram;
25	25
26	26	UINT16 *m_protection_ram;
27	27	emu_timer *m_scanline_timer;

src/mame/includes/fantland.h

r14963	r14964
5	5	public:
6	6	fantland_state(const machine_config &mconfig, device_type type, const char *tag)
7	7	: driver_device(mconfig, type, tag) ,
8		m_spriteram(*this, "spriteram", 16),
9		m_spriteram2(*this, "spriteram2", 16){ }
	8	m_spriteram(*this, "spriteram", 0),
	9	m_spriteram2(*this, "spriteram2", 0){ }
10	10
11	11	/* memory pointers */
12	12	//  UINT8 *    m_spriteram;   // currently directly used in a 16bit map...
r14963	r14964
29	29	device_t *m_msm2;
30	30	device_t *m_msm3;
31	31	device_t *m_msm4;
32		required_shared_ptr<UINT8> m_spriteram;
33		required_shared_ptr<UINT8> m_spriteram2;
	32	optional_shared_ptr<UINT8> m_spriteram;
	33	optional_shared_ptr<UINT8> m_spriteram2;
34	34	DECLARE_WRITE8_MEMBER(fantland_nmi_enable_w);
35	35	DECLARE_WRITE16_MEMBER(fantland_nmi_enable_16_w);
36	36	DECLARE_WRITE8_MEMBER(fantland_soundlatch_w);

src/mame/includes/mcr68.h

r14963	r14964
1	1	#include "machine/6821pia.h"
	2	#include "audio/midway.h"
	3	#include "audio/williams.h"
2	4
3	5	struct counter_state
4	6	{
r14963	r14964
10	12	attotime      period;
11	13	};
12	14
13		class mcr68_state : public mcr_state
	15	class mcr68_state : public driver_device
14	16	{
15	17	public:
16	18	mcr68_state(const machine_config &mconfig, device_type type, const char *tag)
17		: mcr_state(mconfig, type, tag),
18		m_videoram16(*this, "videoram16"),
19		m_spriteram16(*this, "spriteram16") { }
	19	: driver_device(mconfig, type, tag),
	20	m_chip_squeak_deluxe(*this, "csd"),
	21	m_sounds_good(*this, "sg"),
	22	m_turbo_chip_squeak(*this, "tcs"),
	23	m_cvsd_sound(*this, "cvsd"),
	24	m_videoram(*this, "videoram"),
	25	m_spriteram(*this, "spriteram") { }
20	26
21		required_shared_ptr<UINT16> m_videoram16;
	27	optional_device<midway_chip_squeak_deluxe_device> m_chip_squeak_deluxe;
	28	optional_device<midway_sounds_good_device> m_sounds_good;
	29	optional_device<midway_turbo_chip_squeak_device> m_turbo_chip_squeak;
	30	optional_device<williams_cvsd_sound_device> m_cvsd_sound;
	31
	32	required_shared_ptr<UINT16> m_videoram;
	33	required_shared_ptr<UINT16> m_spriteram;
22	34	UINT16 m_control_word;
23	35	UINT8 m_protection_data[5];
24	36	attotime m_timing_factor;
r14963	r14964
40	52	attotime m_m6840_internal_counter_period;
41	53	tilemap_t *m_bg_tilemap;
42	54	tilemap_t *m_fg_tilemap;
43		required_shared_ptr<UINT16> m_spriteram16;
44	55	DECLARE_READ16_MEMBER(zwackery_6840_r);
45	56	DECLARE_WRITE16_MEMBER(xenophobe_control_w);
46	57	DECLARE_WRITE16_MEMBER(blasted_control_w);

src/mame/includes/m90.h

r14963	r14964
7	7	m_spriteram(*this, "spriteram"){ }
8	8
9	9	required_shared_ptr<UINT16> m_video_data;
10		required_shared_ptr<UINT16> m_spriteram;
	10	optional_shared_ptr<UINT16> m_spriteram;
11	11	UINT16 m_video_control_data[8];
12	12	tilemap_t *m_pf1_layer;
13	13	tilemap_t *m_pf2_layer;

src/mame/includes/segas32.h

r14963	r14964
21	21	m_z80_shared_ram(*this,"z80_shared_ram"),
22	22	m_ga2_dpram(*this,"ga2_dpram"),
23	23	m_system32_workram(*this,"workram"),
24		m_system32_videoram(*this,"videoram"),
25		m_system32_spriteram(*this,"spriteram"),
26		m_system32_paletteram(*this,"paletteram") { }
	24	m_system32_videoram(*this,"videoram", 0),
	25	m_system32_spriteram(*this,"spriteram", 0),
	26	m_system32_paletteram(*this,"paletteram", 0) { }
27	27
28	28	required_shared_ptr<UINT8> m_z80_shared_ram;
29	29	optional_shared_ptr<UINT8> m_ga2_dpram;
30		required_shared_ptr<UINT16> m_system32_workram;
	30	optional_shared_ptr<UINT16> m_system32_workram;
31	31	required_shared_ptr<UINT16> m_system32_videoram;
32	32	required_shared_ptr<UINT16> m_system32_spriteram;
33	33

src/mame/includes/offtwall.h

r14963	r14964
10	10	{
11	11	public:
12	12	offtwall_state(const machine_config &mconfig, device_type type, const char *tag)
13		: atarigen_state(mconfig, type, tag) { }
	13	: atarigen_state(mconfig, type, tag),
	14	m_bankrom_base(*this, "bankrom_base") { }
14	15
15	16	UINT16 *m_bankswitch_base;
16		UINT16 *m_bankrom_base;
	17	required_shared_ptr<UINT16> m_bankrom_base;
17	18	UINT32 m_bank_offset;
18	19
19	20	UINT16 *m_spritecache_count;

src/mame/includes/mystwarr.h

r14963	r14964
22	22	int m_roz_rombank;
23	23	tilemap_t *m_ult_936_tilemap;
24	24	UINT16 m_clip;
25		required_shared_ptr<UINT16> m_spriteram;
	25	optional_shared_ptr<UINT16> m_spriteram;
26	26
27	27	required_device<cpu_device> m_maincpu;
28	28	DECLARE_READ16_MEMBER(eeprom_r);

src/mame/includes/gberet.h

r14963	r14964
19	19	/* memory pointers */
20	20	required_shared_ptr<UINT8> m_colorram;
21	21	required_shared_ptr<UINT8> m_videoram;
22		required_shared_ptr<UINT8> m_spriteram2;
	22	optional_shared_ptr<UINT8> m_spriteram2;
23	23	required_shared_ptr<UINT8> m_spriteram;
24		required_shared_ptr<UINT8> m_scrollram;
25		required_shared_ptr<UINT8> m_soundlatch;
	24	optional_shared_ptr<UINT8> m_scrollram;
	25	optional_shared_ptr<UINT8> m_soundlatch;
26	26
27	27	/* video-related */
28	28	tilemap_t * m_bg_tilemap;

src/mame/includes/gottlieb.h

r14963	r14964
2	2
3	3	Gottlieb hardware
4	4
	5	****************************************************************************
	6
	7	Copyright Aaron Giles
	8	All rights reserved.
	9
	10	Redistribution and use in source and binary forms, with or without
	11	modification, are permitted provided that the following conditions are
	12	met:
	13
	14	* Redistributions of source code must retain the above copyright
	15	notice, this list of conditions and the following disclaimer.
	16	* Redistributions in binary form must reproduce the above copyright
	17	notice, this list of conditions and the following disclaimer in
	18	the documentation and/or other materials provided with the
	19	distribution.
	20	* Neither the name 'MAME' nor the names of its contributors may be
	21	used to endorse or promote products derived from this software
	22	without specific prior written permission.
	23
	24	THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
	25	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	26	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	27	DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
	28	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	29	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	30	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	31	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	32	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	33	IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	34	POSSIBILITY OF SUCH DAMAGE.
	35
5	36	***************************************************************************/
6	37
7	38	#include "cpu/i86/i86.h"

src/mame/includes/tubep.h

r14963	r14964
14	14	emu_timer *m_interrupt_timer;
15	15	int m_curr_scanline;
16	16	required_shared_ptr<UINT8> m_textram;
17		required_shared_ptr<UINT8> m_backgroundram;
	17	optional_shared_ptr<UINT8> m_backgroundram;
18	18	required_shared_ptr<UINT8> m_sprite_colorsharedram;
19	19	optional_shared_ptr<UINT8> m_rjammer_backgroundram;
20	20	UINT8 *m_spritemap;

src/mame/includes/hng64.h

r14963	r14964
151	151	DECLARE_READ8_MEMBER(hng64_comm_shared_r);
152	152	DECLARE_WRITE8_MEMBER(hng64_comm_shared_w);
153	153	DECLARE_WRITE32_MEMBER(hng64_videoram_w);
	154	DECLARE_DIRECT_UPDATE_MEMBER(KL5C80_direct_handler);
154	155	};
155	156
156	157

src/mame/includes/moo.h

r14963	r14964
13	13	m_spriteram(*this, "spriteram"){ }
14	14
15	15	/* memory pointers */
16		required_shared_ptr<UINT16> m_workram;
	16	optional_shared_ptr<UINT16> m_workram;
17	17	required_shared_ptr<UINT16> m_spriteram;
18	18	//  UINT16 *    m_paletteram;    // currently this uses generic palette handling
19	19

src/mame/includes/pktgaldx.h

r14963	r14964
16	16	m_pktgaldb_sprites(*this, "pktgaldb_spr"){ }
17	17
18	18	/* memory pointers */
19		required_shared_ptr<UINT16> m_pf1_rowscroll;
20		required_shared_ptr<UINT16> m_pf2_rowscroll;
21		required_shared_ptr<UINT16> m_spriteram;
	19	optional_shared_ptr<UINT16> m_pf1_rowscroll;
	20	optional_shared_ptr<UINT16> m_pf2_rowscroll;
	21	optional_shared_ptr<UINT16> m_spriteram;
22	22	//  UINT16 *  paletteram;    // currently this uses generic palette handling (in decocomn.c)
23	23
24	24	optional_shared_ptr<UINT16> m_pktgaldb_fgram;

src/mame/includes/mcr.h

r14963	r14964
9	9	#include "machine/z80ctc.h"
10	10	#include "machine/z80pio.h"
11	11	#include "machine/z80sio.h"
	12	#include "audio/midway.h"
12	13
13	14	/* constants */
14	15	#define MAIN_OSC_MCR_I      XTAL_19_968MHz
r14963	r14964
21	22	: driver_device(mconfig, type, tag),
22	23	m_maincpu(*this, "maincpu"),
23	24	m_spriteram(*this, "spriteram") ,
24		m_videoram(*this, "videoram"){ }
	25	m_videoram(*this, "videoram"),
	26	m_ssio(*this, "ssio"),
	27	m_chip_squeak_deluxe(*this, "csd"),
	28	m_sounds_good(*this, "sg"),
	29	m_turbo_chip_squeak(*this, "tcs"),
	30	m_squawk_n_talk(*this, "snt") { }
25	31
26	32	// these should be required but can't because mcr68 shares with us
27	33	// once the sound boards are properly device-ified, fix this
r14963	r14964
29	35	optional_shared_ptr<UINT8> m_spriteram;
30	36	optional_shared_ptr<UINT8> m_videoram;
31	37
	38	optional_device<midway_ssio_device> m_ssio;
	39	optional_device<midway_chip_squeak_deluxe_device> m_chip_squeak_deluxe;
	40	optional_device<midway_sounds_good_device> m_sounds_good;
	41	optional_device<midway_turbo_chip_squeak_device> m_turbo_chip_squeak;
	42	optional_device<midway_squawk_n_talk_device> m_squawk_n_talk;
	43
32	44	DECLARE_WRITE8_MEMBER(mcr_control_port_w);
33	45	DECLARE_WRITE8_MEMBER(mcr_ipu_laserdisk_w);
34	46	DECLARE_READ8_MEMBER(mcr_ipu_watchdog_r);
r14963	r14964
55	67	DECLARE_READ8_MEMBER(demoderb_ip1_r);
56	68	DECLARE_READ8_MEMBER(demoderb_ip2_r);
57	69	DECLARE_WRITE8_MEMBER(demoderb_op4_w);
58		DECLARE_READ8_MEMBER(ssio_irq_clear);
59		DECLARE_WRITE8_MEMBER(ssio_status_w);
60		DECLARE_READ8_MEMBER(ssio_data_r);
61		DECLARE_WRITE8_MEMBER(ssio_data_w);
62		DECLARE_READ8_MEMBER(ssio_status_r);
63		DECLARE_READ8_MEMBER(ssio_input_port_r);
64		DECLARE_WRITE8_MEMBER(ssio_output_port_w);
65		DECLARE_WRITE8_MEMBER(csdeluxe_data_w);
66		DECLARE_READ8_MEMBER(csdeluxe_status_r);
67		DECLARE_WRITE8_MEMBER(soundsgood_data_w);
68		DECLARE_READ8_MEMBER(soundsgood_status_r);
69		DECLARE_WRITE8_MEMBER(turbocs_data_w);
70		DECLARE_READ8_MEMBER(turbocs_status_r);
71		DECLARE_WRITE8_MEMBER(squawkntalk_dac_w);
72		DECLARE_WRITE8_MEMBER(squawkntalk_data_w);
73	70	};
74	71
75	72

src/mame/includes/dooyong.h

r14963	r14964
12	12
13	13	optional_device<buffered_spriteram8_device> m_spriteram;
14	14	optional_device<buffered_spriteram16_device> m_spriteram16;
15		required_shared_ptr<UINT8> m_txvideoram;
	15	optional_shared_ptr<UINT8> m_txvideoram;
16	16	optional_shared_ptr<UINT8> m_paletteram_flytiger;
17	17	UINT8 m_sprites_disabled;
18	18	UINT8 m_flytiger_palette_bank;

src/mame/includes/williams.h

r14963	r14964
6	6
7	7
8	8	#include "machine/6821pia.h"
	9	#include "audio/williams.h"
9	10
10	11	class williams_state : public driver_device
11	12	{
12	13	public:
13	14	williams_state(const machine_config &mconfig, device_type type, const char *tag)
14	15	: driver_device(mconfig, type, tag),
	16	m_cvsd_sound(*this, "cvsd"),
15	17	m_nvram(*this, "nvram") ,
16	18	m_videoram(*this, "videoram"),
17	19	m_blaster_palette_0(*this, "blaster_pal0"),
18	20	m_blaster_scanline_control(*this, "blaster_scan"),
19	21	m_williams2_tileram(*this, "williams2_tile"){ }
20	22
	23	optional_device<williams_cvsd_sound_device> m_cvsd_sound;
	24
21	25	required_shared_ptr<UINT8>   m_nvram;
22	26	UINT8 *m_mayday_protection;
23	27	required_shared_ptr<UINT8> m_videoram;

src/mame/includes/atarigt.h

r14963	r14964
17	17	{
18	18	public:
19	19	atarigt_state(const machine_config &mconfig, device_type type, const char *tag)
20		: atarigen_state(mconfig, type, tag) { }
	20	: atarigen_state(mconfig, type, tag),
	21	m_colorram(*this, "colorram", 32),
	22	m_mo_command(*this, "mo_command") { }
21	23
22	24	UINT8         m_is_primrage;
23		UINT16 *      m_colorram;
	25	required_shared_ptr<UINT16> m_colorram;
24	26
25	27	bitmap_ind16 *      m_pf_bitmap;
26	28	bitmap_ind16 *      m_an_bitmap;
r14963	r14964
34	36
35	37	UINT32         m_expanded_mram[MRAM_ENTRIES * 3];
36	38
37		UINT32 *      m_mo_command;
	39	required_shared_ptr<UINT32> m_mo_command;
38	40
39	41	void         (*m_protection_w)(address_space *space, offs_t offset, UINT16 data);
40	42	void         (*m_protection_r)(address_space *space, offs_t offset, UINT16 *data);

src/mame/includes/starwars.h

r14963	r14964
58	58	DECLARE_READ8_MEMBER(starwars_main_ready_flag_r);
59	59	DECLARE_WRITE8_MEMBER(starwars_main_wr_w);
60	60	DECLARE_WRITE8_MEMBER(starwars_soundrst_w);
	61	DECLARE_DIRECT_UPDATE_MEMBER(esb_setdirect);
61	62	};
62	63
63	64

src/mame/mame.mak

r14963	r14964
976	976	$(DRIVERS)/astrocde.o $(VIDEO)/astrocde.o \
977	977	$(DRIVERS)/balsente.o $(MACHINE)/balsente.o $(VIDEO)/balsente.o \
978	978	$(DRIVERS)/gridlee.o $(AUDIO)/gridlee.o $(VIDEO)/gridlee.o \
979		$(DRIVERS)/mcr.o $(MACHINE)/mcr.o $(AUDIO)/mcr.o $(VIDEO)/mcr.o \
	979	$(DRIVERS)/mcr.o $(MACHINE)/mcr.o $(VIDEO)/mcr.o \
980	980	$(DRIVERS)/mcr3.o $(VIDEO)/mcr3.o \
981	981	$(DRIVERS)/mcr68.o $(MACHINE)/mcr68.o $(VIDEO)/mcr68.o \
982	982	$(DRIVERS)/midqslvr.o \
r14963	r14964
994	994	$(MACHINE)/midwayic.o \
995	995	$(AUDIO)/dcs.o \
996	996	$(AUDIO)/gorf.o \
	997	$(AUDIO)/midway.o \
997	998	$(AUDIO)/wow.o \
998	999
999	1000	$(MAMEOBJ)/namco.a: \

src/mame/video/zaxxon.c

r14963	r14964
165	165	zaxxon_state *state = machine.driver_data<zaxxon_state>();
166	166
167	167	/* allocate our own spriteram since it is not accessible by the main CPU */
168		//TODO:TIX
169		//state->m_spriteram = auto_alloc_array(machine, UINT8, 0x100);
	168	state->m_spriteram.allocate(0x100);
170	169
171	170	/* register for save states */
172	171	state->save_item(NAME(state->m_congo_fg_bank));
173	172	state->save_item(NAME(state->m_congo_color_bank));
174	173	state->save_item(NAME(state->m_congo_custom));
175		//state->save_pointer(NAME(state->m_spriteram), 0x100);
176	174
177	175	video_start_common(machine, congo_get_fg_tile_info);
178	176	}

src/mame/video/fastfred.c

r14963	r14964
239	239	fastfred_state *state = machine.driver_data<fastfred_state>();
240	240	int offs;
241	241
242		for (offs = state->m_spriteram_size - 4; offs >= 0; offs -= 4)
	242	for (offs = state->m_spriteram.bytes() - 4; offs >= 0; offs -= 4)
243	243	{
244	244	UINT8 code,sx,sy;
245	245	int flipx,flipy;

src/mame/video/galpanic.c

r14963	r14964
53	53	int offs;
54	54	int sx=0, sy=0;
55	55
56		for (offs = 0;offs < state->m_spriteram_size/2;offs += 4)
	56	for (offs = 0;offs < state->m_spriteram.bytes()/2;offs += 4)
57	57	{
58	58	int code,color,flipx,flipy;
59	59
r14963	r14964
89	89	galpanic_state *state = machine.driver_data<galpanic_state>();
90	90	int offs;
91	91
92		for (offs = 0;offs < state->m_fgvideoram_size/2;offs++)
	92	for (offs = 0;offs < state->m_fgvideoram.bytes()/2;offs++)
93	93	{
94	94	int sx,sy,color;
95	95

src/mame/video/suna8.c

r14963	r14964
170	170	if (!(state->m_text_dim > 0))
171	171	{
172	172	state->m_generic_paletteram_8.allocate(0x200 * 2);
173		//TODO:FIX
174		//state->m_spriteram = auto_alloc_array(machine, UINT8, 0x2000 * 2);
	173	state->m_spriteram.allocate(0x2000 * 2);
175	174	state->m_spritebank  = 0;
176	175	state->m_palettebank = 0;
177	176	}

src/mame/video/tia.c

r14963	r14964
8	8	#include "tia.h"
9	9	#include "sound/tiaintf.h"
10	10
11		#define HMOVE_INACTIVE      -200
12		#define PLAYER_GFX_SLOTS   4
13
14		// Per player graphic
15		// - pixel number to start drawing from (0-7, from GRPx) / number of pixels drawn from GRPx
16		// - display position to start drawing
17		// - size to use
18		struct player_gfx {
19		int   start_pixel[PLAYER_GFX_SLOTS];
20		int start_drawing[PLAYER_GFX_SLOTS];
21		int size[PLAYER_GFX_SLOTS];
22		int skipclip[PLAYER_GFX_SLOTS];
23		};
24
25		static struct player_gfx p0gfx;
26		static struct player_gfx p1gfx;
27
28		static UINT64 frame_cycles;
29		static UINT64 paddle_cycles;
30
31		static int horzP0;
32		static int horzP1;
33		static int horzM0;
34		static int horzM1;
35		static int horzBL;
36		static int motclkP0;
37		static int motclkP1;
38		static int motclkM0;
39		static int motclkM1;
40		static int motclkBL;
41		static int startP0;
42		static int startP1;
43		static int startM0;
44		static int startM1;
45		static int skipclipP0;
46		static int skipclipP1;
47		static int skipM0delay;
48		static int skipM1delay;
49
50		static int current_bitmap;
51
52		static int prev_x;
53		static int prev_y;
54
55		static UINT8 VSYNC;
56		static UINT8 VBLANK;
57		static UINT8 COLUP0;
58		static UINT8 COLUP1;
59		static UINT8 COLUBK;
60		static UINT8 COLUPF;
61		static UINT8 CTRLPF;
62		static UINT8 GRP0;
63		static UINT8 GRP1;
64		static UINT8 REFP0;
65		static UINT8 REFP1;
66		static UINT8 HMP0;
67		static UINT8 HMP1;
68		static UINT8 HMM0;
69		static UINT8 HMM1;
70		static UINT8 HMBL;
71		static UINT8 VDELP0;
72		static UINT8 VDELP1;
73		static UINT8 VDELBL;
74		static UINT8 NUSIZ0;
75		static UINT8 NUSIZ1;
76		static UINT8 ENAM0;
77		static UINT8 ENAM1;
78		static UINT8 ENABL;
79		static UINT8 CXM0P;
80		static UINT8 CXM1P;
81		static UINT8 CXP0FB;
82		static UINT8 CXP1FB;
83		static UINT8 CXM0FB;
84		static UINT8 CXM1FB;
85		static UINT8 CXBLPF;
86		static UINT8 CXPPMM;
87		static UINT8 RESMP0;
88		static UINT8 RESMP1;
89		static UINT8 PF0;
90		static UINT8 PF1;
91		static UINT8 PF2;
92		static UINT8 INPT4;
93		static UINT8 INPT5;
94
95		static UINT8 prevGRP0;
96		static UINT8 prevGRP1;
97		static UINT8 prevENABL;
98
99		static int HMOVE_started;
100		static int HMOVE_started_previous;
101		static UINT8 HMP0_latch;
102		static UINT8 HMP1_latch;
103		static UINT8 HMM0_latch;
104		static UINT8 HMM1_latch;
105		static UINT8 HMBL_latch;
106		static UINT8 REFLECT;      /* Should playfield be reflected or not */
107		static UINT8 NUSIZx_changed;
108
109		static bitmap_ind16 *helper[3];
110
111		static UINT16 screen_height;
112
113	11	static const int nusiz[8][3] =
114	12	{
115	13	{ 1, 1, 0 },
r14963	r14964
122	20	{ 1, 4, 0 }
123	21	};
124	22
125		static read16_space_func   tia_read_input_port;
126		static read8_space_func   tia_get_databus;
127		static write16_space_func   tia_vsync_callback;
128
129	23	static void extend_palette(running_machine &machine) {
130	24	int   i,j;
131	25
r14963	r14964
268	162	extend_palette( machine );
269	163	}
270	164
	165	// device type definition
	166	const device_type TIA_VIDEO = &device_creator<tia_video_device>;
271	167
272		VIDEO_START( tia )
	168	//-------------------------------------------------
	169	//  tia_video_device - constructor
	170	//-------------------------------------------------
	171
	172	tia_video_device::tia_video_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	173	: device_t(mconfig, TIA_VIDEO, "TIA Video", tag, owner, clock)
273	174	{
274		int cx = machine.primary_screen->width();
	175	}
275	176
276		screen_height = machine.primary_screen->height();
277		helper[0] = auto_bitmap_ind16_alloc(machine, cx, TIA_MAX_SCREEN_HEIGHT);
278		helper[1] = auto_bitmap_ind16_alloc(machine, cx, TIA_MAX_SCREEN_HEIGHT);
279		helper[2] = auto_bitmap_ind16_alloc(machine, cx, TIA_MAX_SCREEN_HEIGHT);
	177
	178	//-------------------------------------------------
	179	//  device_config_complete - perform any
	180	//  operations now that the configuration is
	181	//  complete
	182	//-------------------------------------------------
	183
	184	void tia_video_device::device_config_complete()
	185	{
	186	// inherit a copy of the static data
	187	const tia_interface *intf = reinterpret_cast<const tia_interface *>(static_config());
	188	if (intf != NULL)
	189	*static_cast<tia_interface *>(this) = *intf;
	190
	191	// or initialize to defaults if none provided
	192	else
	193	{
	194	memset(&m_read_input_port_cb, 0, sizeof(m_read_input_port_cb));
	195	memset(&m_databus_contents_cb, 0, sizeof(m_databus_contents_cb));
	196	memset(&m_vsync_callback_cb, 0, sizeof(m_vsync_callback_cb));
	197	}
280	198	}
	199	//-------------------------------------------------
	200	//  device_start - device-specific startup
	201	//-------------------------------------------------
281	202
	203	void tia_video_device::device_start()
	204	{
	205	// resolve callbacks
	206	m_read_input_port_func.resolve(m_read_input_port_cb, *this);
	207	m_databus_contents_func.resolve(m_databus_contents_cb, *this);
	208	m_vsync_callback_func.resolve(m_vsync_callback_cb, *this);
282	209
283		SCREEN_UPDATE_IND16( tia )
	210
	211	int cx = machine().primary_screen->width();
	212
	213	screen_height = machine().primary_screen->height();
	214	helper[0] = auto_bitmap_ind16_alloc(machine(), cx, TIA_MAX_SCREEN_HEIGHT);
	215	helper[1] = auto_bitmap_ind16_alloc(machine(), cx, TIA_MAX_SCREEN_HEIGHT);
	216	helper[2] = auto_bitmap_ind16_alloc(machine(), cx, TIA_MAX_SCREEN_HEIGHT);
	217	}
	218
	219
	220	//-------------------------------------------------
	221	//  screen_update -
	222	//-------------------------------------------------
	223
	224	UINT32 tia_video_device::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
284	225	{
285	226	screen_height = screen.height();
286	227	copybitmap(bitmap, *helper[2], 0, 0, 0, 0, cliprect);
r14963	r14964
288	229	}
289	230
290	231
291		static void draw_sprite_helper(UINT8* p, UINT8 *col, struct player_gfx *gfx,
	232	void tia_video_device::draw_sprite_helper(UINT8* p, UINT8 *col, struct player_gfx *gfx,
292	233	UINT8 GRP, UINT8 COLUP, UINT8 REFP)
293	234	{
294	235	int i;
r14963	r14964
321	262	}
322	263
323	264
324		static void draw_missile_helper(UINT8* p, UINT8* col, int horz, int skipdelay, int latch, int start,
	265	void tia_video_device::draw_missile_helper(UINT8* p, UINT8* col, int horz, int skipdelay, int latch, int start,
325	266	UINT8 RESMP, UINT8 ENAM, UINT8 NUSIZ, UINT8 COLUM)
326	267	{
327	268	int num = nusiz[NUSIZ & 7][0];
r14963	r14964
385	326	}
386	327
387	328
388		static void draw_playfield_helper(UINT8* p, UINT8* col, int horz,
	329	void tia_video_device::draw_playfield_helper(UINT8* p, UINT8* col, int horz,
389	330	UINT8 COLU, UINT8 REFPF)
390	331	{
391	332	UINT32 PF =
r14963	r14964
431	372	}
432	373
433	374
434		static void draw_ball_helper(UINT8* p, UINT8* col, int horz, UINT8 ENAB)
	375	void tia_video_device::draw_ball_helper(UINT8* p, UINT8* col, int horz, UINT8 ENAB)
435	376	{
436	377	int width = 1 << ((CTRLPF >> 4) & 3);
437	378
r14963	r14964
450	391	}
451	392
452	393
453		static void drawS0(UINT8* p, UINT8* col)
	394	void tia_video_device::drawS0(UINT8* p, UINT8* col)
454	395	{
455	396	draw_sprite_helper(p, col, &p0gfx, (VDELP0 & 1) ? prevGRP0 : GRP0, COLUP0, REFP0);
456	397	}
457	398
458	399
459		static void drawS1(UINT8* p, UINT8* col)
	400	void tia_video_device::drawS1(UINT8* p, UINT8* col)
460	401	{
461	402	draw_sprite_helper(p, col, &p1gfx, (VDELP1 & 1) ? prevGRP1 : GRP1, COLUP1, REFP1);
462	403	}
463	404
464	405
465		static void drawM0(UINT8* p, UINT8* col)
	406	void tia_video_device::drawM0(UINT8* p, UINT8* col)
466	407	{
467	408	draw_missile_helper(p, col, horzM0, skipM0delay, HMM0_latch, startM0, RESMP0, ENAM0, NUSIZ0, COLUP0);
468	409	}
469	410
470	411
471		static void drawM1(UINT8* p, UINT8* col)
	412	void tia_video_device::drawM1(UINT8* p, UINT8* col)
472	413	{
473	414	draw_missile_helper(p, col, horzM1, skipM1delay, HMM1_latch, startM1, RESMP1, ENAM1, NUSIZ1, COLUP1);
474	415	}
475	416
476	417
477		static void drawBL(UINT8* p, UINT8* col)
	418	void tia_video_device::drawBL(UINT8* p, UINT8* col)
478	419	{
479	420	draw_ball_helper(p, col, horzBL, (VDELBL & 1) ? prevENABL : ENABL);
480	421	}
481	422
482	423
483		static void drawPF(UINT8* p, UINT8 *col)
	424	void tia_video_device::drawPF(UINT8* p, UINT8 *col)
484	425	{
485	426	draw_playfield_helper(p, col, 0,
486	427	((CTRLPF & 6) == 2) ? COLUP0 : COLUPF, 0);
r14963	r14964
490	431	}
491	432
492	433
493		static int collision_check(UINT8* p1, UINT8* p2, int x1, int x2)
	434	int tia_video_device::collision_check(UINT8* p1, UINT8* p2, int x1, int x2)
494	435	{
495	436	int i;
496	437
r14963	r14964
506	447	}
507	448
508	449
509		INLINE int current_x(address_space *space)
	450	int tia_video_device::current_x()
510	451	{
511		return 3 * ((space->machine().firstcpu->total_cycles() - frame_cycles) % 76) - 68;
	452	return 3 * ((machine().firstcpu->total_cycles() - frame_cycles) % 76) - 68;
512	453	}
513	454
514	455
515		INLINE int current_y(address_space *space)
	456	int tia_video_device::current_y()
516	457	{
517		return (space->machine().firstcpu->total_cycles() - frame_cycles) / 76;
	458	return (machine().firstcpu->total_cycles() - frame_cycles) / 76;
518	459	}
519	460
520	461
521		static void setup_pXgfx(void)
	462	void tia_video_device::setup_pXgfx(void)
522	463	{
523	464	int i;
524	465	for ( i = 0; i < PLAYER_GFX_SLOTS; i++ )
r14963	r14964
566	507	}
567	508	}
568	509
569		static void update_bitmap(int next_x, int next_y)
	510	void tia_video_device::update_bitmap(int next_x, int next_y)
570	511	{
571	512	int x;
572	513	int y;
r14963	r14964
851	792	}
852	793
853	794
854		static WRITE8_HANDLER( WSYNC_w )
	795	WRITE8_MEMBER( tia_video_device::WSYNC_w )
855	796	{
856		int cycles = space->machine().firstcpu->total_cycles() - frame_cycles;
	797	int cycles = machine().firstcpu->total_cycles() - frame_cycles;
857	798
858	799	if (cycles % 76)
859	800	{
860		device_adjust_icount(&space->device(), cycles % 76 - 76);
	801	device_adjust_icount(&space.device(), cycles % 76 - 76);
861	802	}
862	803	}
863	804
864	805
865		static WRITE8_HANDLER( VSYNC_w )
	806	WRITE8_MEMBER( tia_video_device::VSYNC_w )
866	807	{
867	808	if (data & 2)
868	809	{
869	810	if (!(VSYNC & 2))
870	811	{
871		int curr_y = current_y(space);
	812	int curr_y = current_y();
872	813
873	814	if ( curr_y > 5 )
874	815	update_bitmap(
875		space->machine().primary_screen->width(),
876		space->machine().primary_screen->height());
	816	machine().primary_screen->width(),
	817	machine().primary_screen->height());
877	818
878		if ( tia_vsync_callback ) {
879		tia_vsync_callback( space, 0, curr_y, 0xFFFF );
	819	if ( !m_vsync_callback_func.isnull() ) {
	820	m_vsync_callback_func(0, curr_y, 0xFFFF );
880	821	}
881	822
882	823	prev_y = 0;
883	824	prev_x = 0;
884	825
885		frame_cycles += 76 * current_y(space);
	826	frame_cycles += 76 * current_y();
886	827	}
887	828	}
888	829
r14963	r14964
890	831	}
891	832
892	833
893		static WRITE8_HANDLER( VBLANK_w )
	834	WRITE8_MEMBER( tia_video_device::VBLANK_w )
894	835	{
895	836	if (data & 0x80)
896	837	{
897		paddle_cycles = space->machine().firstcpu->total_cycles();
	838	paddle_cycles = machine().firstcpu->total_cycles();
898	839	}
899	840	if ( ! ( VBLANK & 0x40 ) ) {
900	841	INPT4 = 0x80;
r14963	r14964
904	845	}
905	846
906	847
907		static WRITE8_HANDLER( CTRLPF_w )
	848	WRITE8_MEMBER( tia_video_device::CTRLPF_w )
908	849	{
909		int curr_x = current_x(space);
	850	int curr_x = current_x();
910	851
911	852	CTRLPF = data;
912	853	if ( curr_x < 80 ) {
r14963	r14964
914	855	}
915	856	}
916	857
917		static WRITE8_HANDLER( HMP0_w )
	858	WRITE8_MEMBER( tia_video_device::HMP0_w )
918	859	{
919		int curr_x = current_x(space);
	860	int curr_x = current_x();
920	861
921	862	data &= 0xF0;
922	863
r14963	r14964
946	887	HMP0 = data;
947	888	}
948	889
949		static WRITE8_HANDLER( HMP1_w )
	890	WRITE8_MEMBER( tia_video_device::HMP1_w )
950	891	{
951		int curr_x = current_x(space);
	892	int curr_x = current_x();
952	893
953	894	data &= 0xF0;
954	895
r14963	r14964
978	919	HMP1 = data;
979	920	}
980	921
981		static WRITE8_HANDLER( HMM0_w )
	922	WRITE8_MEMBER( tia_video_device::HMM0_w )
982	923	{
983		int curr_x = current_x(space);
	924	int curr_x = current_x();
984	925
985	926	data &= 0xF0;
986	927
r14963	r14964
1009	950	HMM0 = data;
1010	951	}
1011	952
1012		static WRITE8_HANDLER( HMM1_w )
	953	WRITE8_MEMBER( tia_video_device::HMM1_w )
1013	954	{
1014		int curr_x = current_x(space);
	955	int curr_x = current_x();
1015	956
1016	957	data &= 0xF0;
1017	958
r14963	r14964
1040	981	HMM1 = data;
1041	982	}
1042	983
1043		static WRITE8_HANDLER( HMBL_w )
	984	WRITE8_MEMBER( tia_video_device::HMBL_w )
1044	985	{
1045		int curr_x = current_x(space);
	986	int curr_x = current_x();
1046	987
1047	988	data &= 0xF0;
1048	989
r14963	r14964
1071	1012	HMBL = data;
1072	1013	}
1073	1014
1074		static WRITE8_HANDLER( HMOVE_w )
	1015	WRITE8_MEMBER( tia_video_device::HMOVE_w )
1075	1016	{
1076		int curr_x = current_x(space);
1077		int curr_y = current_y(space);
	1017	int curr_x = current_x();
	1018	int curr_y = current_y();
1078	1019
1079	1020	HMOVE_started = curr_x;
1080	1021
r14963	r14964
1196	1137	}
1197	1138
1198	1139
1199		static WRITE8_HANDLER( RSYNC_w )
	1140	WRITE8_MEMBER( tia_video_device::RSYNC_w )
1200	1141	{
1201	1142	/* this address is used in chip testing */
1202	1143	}
1203	1144
1204	1145
1205		static WRITE8_HANDLER( NUSIZ0_w )
	1146	WRITE8_MEMBER( tia_video_device::NUSIZ0_w )
1206	1147	{
1207		int curr_x = current_x(space);
	1148	int curr_x = current_x();
1208	1149
1209	1150	/* Check if relevant bits have changed */
1210	1151	if ( ( data & 7 ) != ( NUSIZ0 & 7 ) ) {
r14963	r14964
1219	1160	/* This copy has started drawing */
1220	1161	if ( p0gfx.size[i] == 1 && nusiz[data & 7][1] > 1 ) {
1221	1162	int delay = 1 + ( ( p0gfx.start_pixel[i] + ( curr_x - p0gfx.start_drawing[i] ) ) & 1 );
1222		update_bitmap( curr_x + delay, current_y(space) );
	1163	update_bitmap( curr_x + delay, current_y() );
1223	1164	p0gfx.start_pixel[i] += ( curr_x + delay - p0gfx.start_drawing[i] );
1224	1165	if ( p0gfx.start_pixel[i] > 8 )
1225	1166	p0gfx.start_pixel[i] = 8;
r14963	r14964
1229	1170	if ( delay ) {
1230	1171	delay = p0gfx.size[i] - delay;
1231	1172	}
1232		update_bitmap( curr_x + delay, current_y(space) );
	1173	update_bitmap( curr_x + delay, current_y() );
1233	1174	p0gfx.start_pixel[i] += ( curr_x - p0gfx.start_drawing[i] ) / p0gfx.size[i];
1234	1175	p0gfx.start_drawing[i] = curr_x + delay;
1235	1176	} else {
r14963	r14964
1280	1221	}
1281	1222
1282	1223
1283		static WRITE8_HANDLER( NUSIZ1_w )
	1224	WRITE8_MEMBER( tia_video_device::NUSIZ1_w )
1284	1225	{
1285		int curr_x = current_x(space);
	1226	int curr_x = current_x();
1286	1227
1287	1228	/* Check if relevant bits have changed */
1288	1229	if ( ( data & 7 ) != ( NUSIZ1 & 7 ) ) {
r14963	r14964
1297	1238	/* This copy has started drawing */
1298	1239	if ( p1gfx.size[i] == 1 && nusiz[data & 7][1] > 1 ) {
1299	1240	int delay = 1 + ( ( p0gfx.start_pixel[i] + ( curr_x - p0gfx.start_drawing[i] ) ) & 1 );
1300		update_bitmap( curr_x + delay, current_y(space) );
	1241	update_bitmap( curr_x + delay, current_y() );
1301	1242	p1gfx.start_pixel[i] += ( curr_x + delay - p1gfx.start_drawing[i] );
1302	1243	if ( p1gfx.start_pixel[i] > 8 )
1303	1244	p1gfx.start_pixel[i] = 8;
r14963	r14964
1307	1248	if ( delay ) {
1308	1249	delay = p1gfx.size[i] - delay;
1309	1250	}
1310		update_bitmap( curr_x + delay, current_y(space) );
	1251	update_bitmap( curr_x + delay, current_y() );
1311	1252	p1gfx.start_pixel[i] += ( curr_x - p1gfx.start_drawing[i] ) / p1gfx.size[i];
1312	1253	p1gfx.start_drawing[i] = curr_x + delay;
1313	1254	} else {
r14963	r14964
1358	1299	}
1359	1300
1360	1301
1361		static WRITE8_HANDLER( HMCLR_w )
	1302	WRITE8_MEMBER( tia_video_device::HMCLR_w )
1362	1303	{
1363	1304	HMP0_w( space, offset, 0 );
1364	1305	HMP1_w( space, offset, 0 );
r14963	r14964
1368	1309	}
1369	1310
1370	1311
1371		static WRITE8_HANDLER( CXCLR_w )
	1312	WRITE8_MEMBER( tia_video_device::CXCLR_w )
1372	1313	{
1373	1314	CXM0P = 0;
1374	1315	CXM1P = 0;
r14963	r14964
1403	1344	}                                                               \
1404	1345	}
1405	1346
1406		static WRITE8_HANDLER( RESP0_w )
	1347	WRITE8_MEMBER( tia_video_device::RESP0_w )
1407	1348	{
1408		int curr_x = current_x(space);
	1349	int curr_x = current_x();
1409	1350	int new_horzP0;
1410	1351
1411	1352	/* Check if HMOVE is activated during this line */
r14963	r14964
1463	1404	}
1464	1405
1465	1406
1466		static WRITE8_HANDLER( RESP1_w )
	1407	WRITE8_MEMBER( tia_video_device::RESP1_w )
1467	1408	{
1468		int curr_x = current_x(space);
	1409	int curr_x = current_x();
1469	1410	int new_horzP1;
1470	1411
1471	1412	/* Check if HMOVE is activated during this line */
r14963	r14964
1523	1464	}
1524	1465
1525	1466
1526		static WRITE8_HANDLER( RESM0_w )
	1467	WRITE8_MEMBER( tia_video_device::RESM0_w )
1527	1468	{
1528		int curr_x = current_x(space);
	1469	int curr_x = current_x();
1529	1470	int new_horzM0;
1530	1471
1531	1472	/* Check if HMOVE is activated during this line */
r14963	r14964
1545	1486	}
1546	1487
1547	1488
1548		static WRITE8_HANDLER( RESM1_w )
	1489	WRITE8_MEMBER( tia_video_device::RESM1_w )
1549	1490	{
1550		int curr_x = current_x(space);
	1491	int curr_x = current_x();
1551	1492	int new_horzM1;
1552	1493
1553	1494	/* Check if HMOVE is activated during this line */
r14963	r14964
1567	1508	}
1568	1509
1569	1510
1570		static WRITE8_HANDLER( RESBL_w )
	1511	WRITE8_MEMBER( tia_video_device::RESBL_w )
1571	1512	{
1572		int curr_x = current_x(space);
	1513	int curr_x = current_x();
1573	1514
1574	1515	/* Check if HMOVE is activated during this line */
1575	1516	if ( HMOVE_started != HMOVE_INACTIVE ) {
r14963	r14964
1583	1524	}
1584	1525
1585	1526
1586		static WRITE8_HANDLER( RESMP0_w )
	1527	WRITE8_MEMBER( tia_video_device::RESMP0_w )
1587	1528	{
1588	1529	if (RESMP0 & 2)
1589	1530	{
r14963	r14964
1605	1546	}
1606	1547
1607	1548
1608		static WRITE8_HANDLER( RESMP1_w )
	1549	WRITE8_MEMBER( tia_video_device::RESMP1_w )
1609	1550	{
1610	1551	if (RESMP1 & 2)
1611	1552	{
r14963	r14964
1627	1568	}
1628	1569
1629	1570
1630		static WRITE8_HANDLER( GRP0_w )
	1571	WRITE8_MEMBER( tia_video_device::GRP0_w )
1631	1572	{
1632	1573	prevGRP1 = GRP1;
1633	1574
r14963	r14964
1635	1576	}
1636	1577
1637	1578
1638		static WRITE8_HANDLER( GRP1_w )
	1579	WRITE8_MEMBER( tia_video_device::GRP1_w )
1639	1580	{
1640	1581	prevGRP0 = GRP0;
1641	1582
r14963	r14964
1645	1586	}
1646	1587
1647	1588
1648		static READ8_HANDLER( INPT_r )
	1589	READ8_MEMBER( tia_video_device::INPT_r )
1649	1590	{
1650		UINT64 elapsed = space->machine().firstcpu->total_cycles() - paddle_cycles;
	1591	UINT64 elapsed = machine().firstcpu->total_cycles() - paddle_cycles;
1651	1592	int input = TIA_INPUT_PORT_ALWAYS_ON;
1652		if ( tia_read_input_port )
	1593	if ( !m_read_input_port_func.isnull() )
1653	1594	{
1654		input = tia_read_input_port(space, offset & 3, 0xFFFF);
	1595	input = m_read_input_port_func(offset & 3, 0xFFFF);
1655	1596	}
1656	1597
1657	1598	if ( input == TIA_INPUT_PORT_ALWAYS_ON )
r14963	r14964
1663	1604	}
1664	1605
1665	1606
1666		READ8_HANDLER( tia_r )
	1607	READ8_MEMBER( tia_video_device::read )
1667	1608	{
1668	1609	/* lower bits 0 - 5 seem to depend on the last byte on the
1669	1610	data bus. If the driver supplied a routine to retrieve
r14963	r14964
1672	1613	*/
1673	1614	UINT8 data = offset & 0x3f;
1674	1615
1675		if ( tia_get_databus )
	1616	if ( !m_databus_contents_func.isnull() )
1676	1617	{
1677		data = tia_get_databus(space, offset) & 0x3f;
	1618	data = m_databus_contents_func(offset) & 0x3f;
1678	1619	}
1679	1620
1680	1621	if (!(offset & 0x8))
1681	1622	{
1682		update_bitmap(current_x(space), current_y(space));
	1623	update_bitmap(current_x(), current_y());
1683	1624	}
1684	1625
1685	1626	switch (offset & 0xF)
r14963	r14964
1710	1651	return data | INPT_r(space,3);
1711	1652	case 0xC:
1712	1653	{
1713		int   button = tia_read_input_port ? ( tia_read_input_port(space,4,0xFFFF) & 0x80 ) : 0x80;
	1654	int   button = !m_read_input_port_func.isnull() ? ( m_read_input_port_func(4,0xFFFF) & 0x80 ) : 0x80;
1714	1655	INPT4 = ( VBLANK & 0x40) ? ( INPT4 & button ) : button;
1715	1656	}
1716	1657	return data | INPT4;
1717	1658	case 0xD:
1718	1659	{
1719		int button = tia_read_input_port ? ( tia_read_input_port(space,5,0xFFFF) & 0x80 ) : 0x80;
	1660	int button = !m_read_input_port_func.isnull() ? ( m_read_input_port_func(5,0xFFFF) & 0x80 ) : 0x80;
1720	1661	INPT5 = ( VBLANK & 0x40) ? ( INPT5 & button ) : button;
1721	1662	}
1722	1663	return data | INPT5;
r14963	r14964
1726	1667	}
1727	1668
1728	1669
1729		WRITE8_HANDLER( tia_w )
	1670	WRITE8_MEMBER( tia_video_device::write )
1730	1671	{
1731	1672	static const int delay[0x40] =
1732	1673	{
r14963	r14964
1776	1717	0,   // HMCLR
1777	1718	0,   // CXCLR
1778	1719	};
1779		int curr_x = current_x(space);
1780		int curr_y = current_y(space);
	1720	int curr_x = current_x();
	1721	int curr_y = current_y();
1781	1722
1782	1723	offset &= 0x3F;
1783	1724
r14963	r14964
1863	1804	case 0x18: /* AUDF1 */
1864	1805	case 0x19: /* AUDV0 */
1865	1806	case 0x1A: /* AUDV1 */
1866		tia_sound_w(space->machine().device("tia"), offset, data);
	1807	tia_sound_w(machine().device("tia"), offset, data);
1867	1808	break;
1868	1809
1869	1810	case 0x1B:
r14963	r14964
1924	1865	}
1925	1866
1926	1867
1927		static void tia_reset(running_machine &machine)
	1868	//-------------------------------------------------
	1869	//  device_reset - device-specific reset
	1870	//-------------------------------------------------
	1871
	1872	void tia_video_device::device_reset()
1928	1873	{
1929	1874	int i;
1930	1875
r14963	r14964
1976	1921
1977	1922	NUSIZx_changed = 0;
1978	1923	}
1979
1980
1981
1982		void tia_init(running_machine &machine, const struct tia_interface* ti)
1983		{
1984		assert_always(machine.phase() == MACHINE_PHASE_INIT, "Can only call tia_init at init time!");
1985
1986		if ( ti ) {
1987		tia_read_input_port = ti->read_input_port;
1988		tia_get_databus = ti->databus_contents;
1989		tia_vsync_callback = ti->vsync_callback;
1990		} else {
1991		tia_read_input_port = NULL;
1992		tia_get_databus = NULL;
1993		tia_vsync_callback = NULL;
1994		}
1995
1996		tia_reset( machine );
1997
1998		machine.add_notifier(MACHINE_NOTIFY_RESET, machine_notify_delegate(FUNC(tia_reset), &machine));
1999		}
2000

src/mame/video/tia.h

r14963	r14964
1	1	#ifndef _VIDEO_TIA_H_
2	2	#define _VIDEO_TIA_H_
3	3
	4	//**************************************************************************
	5	//  MACROS / CONSTANTS
	6	//**************************************************************************
	7
	8
4	9	#define TIA_PALETTE_LENGTH            128 + 128 * 128
5	10	#define TIA_INPUT_PORT_ALWAYS_ON      0
6	11	#define TIA_INPUT_PORT_ALWAYS_OFF      0xffff
7	12	#define TIA_MAX_SCREEN_HEIGHT         342
8	13
	14	#define HMOVE_INACTIVE      -200
	15	#define PLAYER_GFX_SLOTS   4
	16	// Per player graphic
	17	// - pixel number to start drawing from (0-7, from GRPx) / number of pixels drawn from GRPx
	18	// - display position to start drawing
	19	// - size to use
	20	struct player_gfx {
	21	int   start_pixel[PLAYER_GFX_SLOTS];
	22	int start_drawing[PLAYER_GFX_SLOTS];
	23	int size[PLAYER_GFX_SLOTS];
	24	int skipclip[PLAYER_GFX_SLOTS];
	25	};
	26
	27	//**************************************************************************
	28	//  INTERFACE CONFIGURATION MACROS
	29	//**************************************************************************
	30
	31	#define MCFG_TIA_VIDEO_ADD(_tag, _config) \
	32	MCFG_DEVICE_ADD(_tag, TIA_VIDEO, 0) \
	33	MCFG_DEVICE_CONFIG(_config)
	34
	35	//**************************************************************************
	36	//  TYPE DEFINITIONS
	37	//**************************************************************************
	38
	39
	40	// ======================> tia_interface
	41
	42
9	43	struct tia_interface {
10		read16_space_func   read_input_port;
11		read8_space_func   databus_contents;
12		write16_space_func   vsync_callback;
	44	devcb_read16   m_read_input_port_cb;
	45	devcb_read8      m_databus_contents_cb;
	46	devcb_write16   m_vsync_callback_cb;
13	47	};
14	48
15		PALETTE_INIT( tia_NTSC );
16		PALETTE_INIT( tia_PAL );
	49	// ======================> tia_video_device
17	50
18		VIDEO_START( tia );
19		SCREEN_UPDATE_IND16( tia );
	51	class tia_video_device :   public device_t,
	52	public tia_interface
	53	{
	54	public:
	55	// construction/destruction
	56	tia_video_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
20	57
21		READ8_HANDLER( tia_r );
22		WRITE8_HANDLER( tia_w );
	58	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
23	59
24		void tia_init(running_machine &machine, const struct tia_interface* ti);
	60	DECLARE_READ8_MEMBER( read );
	61	DECLARE_WRITE8_MEMBER( write );
25	62
	63	protected:
	64	// device-level overrides
	65	virtual void device_config_complete();
	66	virtual void device_start();
	67	virtual void device_reset();
	68
	69	void draw_sprite_helper(UINT8* p, UINT8 *col, struct player_gfx *gfx, UINT8 GRP, UINT8 COLUP, UINT8 REFP);
	70	void draw_missile_helper(UINT8* p, UINT8* col, int horz, int skipdelay, int latch, int start, UINT8 RESMP, UINT8 ENAM, UINT8 NUSIZ, UINT8 COLUM);
	71	void draw_playfield_helper(UINT8* p, UINT8* col, int horz, UINT8 COLU, UINT8 REFPF);
	72	void draw_ball_helper(UINT8* p, UINT8* col, int horz, UINT8 ENAB);
	73	void drawS0(UINT8* p, UINT8* col);
	74	void drawS1(UINT8* p, UINT8* col);
	75	void drawM0(UINT8* p, UINT8* col);
	76	void drawM1(UINT8* p, UINT8* col);
	77	void drawBL(UINT8* p, UINT8* col);
	78	void drawPF(UINT8* p, UINT8 *col);
	79	int collision_check(UINT8* p1, UINT8* p2, int x1, int x2);
	80	int current_x();
	81	int current_y();
	82	void setup_pXgfx(void);
	83	void update_bitmap(int next_x, int next_y);
	84	DECLARE_WRITE8_MEMBER( WSYNC_w );
	85	DECLARE_WRITE8_MEMBER( VSYNC_w );
	86	DECLARE_WRITE8_MEMBER( VBLANK_w );
	87	DECLARE_WRITE8_MEMBER( CTRLPF_w );
	88	DECLARE_WRITE8_MEMBER( HMP0_w );
	89	DECLARE_WRITE8_MEMBER( HMP1_w );
	90	DECLARE_WRITE8_MEMBER( HMM0_w );
	91	DECLARE_WRITE8_MEMBER( HMM1_w );
	92	DECLARE_WRITE8_MEMBER( HMBL_w );
	93	DECLARE_WRITE8_MEMBER( HMOVE_w );
	94	DECLARE_WRITE8_MEMBER( RSYNC_w );
	95	DECLARE_WRITE8_MEMBER( NUSIZ0_w );
	96	DECLARE_WRITE8_MEMBER( NUSIZ1_w );
	97	DECLARE_WRITE8_MEMBER( HMCLR_w );
	98	DECLARE_WRITE8_MEMBER( CXCLR_w );
	99	DECLARE_WRITE8_MEMBER( RESP0_w );
	100	DECLARE_WRITE8_MEMBER( RESP1_w );
	101	DECLARE_WRITE8_MEMBER( RESM0_w );
	102	DECLARE_WRITE8_MEMBER( RESM1_w );
	103	DECLARE_WRITE8_MEMBER( RESBL_w );
	104	DECLARE_WRITE8_MEMBER( RESMP0_w );
	105	DECLARE_WRITE8_MEMBER( RESMP1_w );
	106	DECLARE_WRITE8_MEMBER( GRP0_w );
	107	DECLARE_WRITE8_MEMBER( GRP1_w );
	108	DECLARE_READ8_MEMBER( INPT_r );
	109
	110
	111	private:
	112	devcb_resolved_read16   m_read_input_port_func;
	113	devcb_resolved_read8   m_databus_contents_func;
	114	devcb_resolved_write16   m_vsync_callback_func;
	115
	116	struct player_gfx p0gfx;
	117	struct player_gfx p1gfx;
	118
	119	UINT64 frame_cycles;
	120	UINT64 paddle_cycles;
	121
	122	int horzP0;
	123	int horzP1;
	124	int horzM0;
	125	int horzM1;
	126	int horzBL;
	127	int motclkP0;
	128	int motclkP1;
	129	int motclkM0;
	130	int motclkM1;
	131	int motclkBL;
	132	int startP0;
	133	int startP1;
	134	int startM0;
	135	int startM1;
	136	int skipclipP0;
	137	int skipclipP1;
	138	int skipM0delay;
	139	int skipM1delay;
	140
	141	int current_bitmap;
	142
	143	int prev_x;
	144	int prev_y;
	145
	146	UINT8 VSYNC;
	147	UINT8 VBLANK;
	148	UINT8 COLUP0;
	149	UINT8 COLUP1;
	150	UINT8 COLUBK;
	151	UINT8 COLUPF;
	152	UINT8 CTRLPF;
	153	UINT8 GRP0;
	154	UINT8 GRP1;
	155	UINT8 REFP0;
	156	UINT8 REFP1;
	157	UINT8 HMP0;
	158	UINT8 HMP1;
	159	UINT8 HMM0;
	160	UINT8 HMM1;
	161	UINT8 HMBL;
	162	UINT8 VDELP0;
	163	UINT8 VDELP1;
	164	UINT8 VDELBL;
	165	UINT8 NUSIZ0;
	166	UINT8 NUSIZ1;
	167	UINT8 ENAM0;
	168	UINT8 ENAM1;
	169	UINT8 ENABL;
	170	UINT8 CXM0P;
	171	UINT8 CXM1P;
	172	UINT8 CXP0FB;
	173	UINT8 CXP1FB;
	174	UINT8 CXM0FB;
	175	UINT8 CXM1FB;
	176	UINT8 CXBLPF;
	177	UINT8 CXPPMM;
	178	UINT8 RESMP0;
	179	UINT8 RESMP1;
	180	UINT8 PF0;
	181	UINT8 PF1;
	182	UINT8 PF2;
	183	UINT8 INPT4;
	184	UINT8 INPT5;
	185
	186	UINT8 prevGRP0;
	187	UINT8 prevGRP1;
	188	UINT8 prevENABL;
	189
	190	int HMOVE_started;
	191	int HMOVE_started_previous;
	192	UINT8 HMP0_latch;
	193	UINT8 HMP1_latch;
	194	UINT8 HMM0_latch;
	195	UINT8 HMM1_latch;
	196	UINT8 HMBL_latch;
	197	UINT8 REFLECT;      /* Should playfield be reflected or not */
	198	UINT8 NUSIZx_changed;
	199
	200	bitmap_ind16 *helper[3];
	201
	202	UINT16 screen_height;
	203
	204	};
	205
	206
	207	// device type definition
	208	extern const device_type TIA_VIDEO;
	209
	210	PALETTE_INIT( tia_NTSC );
	211	PALETTE_INIT( tia_PAL );
	212
26	213	#endif /* _VIDEO_TIA_H_ */

src/mame/video/decospr.c

r14963	r14964
40	40	(bootleg) nmg5.c
41	41	(bootleg) tumbleb.c
42	42	(bootleg) crospang.c
	43	(bootleg) silvmil.c
	44	(bootleg) gotcha.c
43	45
44	46	to convert:
45	47

src/mame/video/mcr68.c

r14963	r14964
21	21	static TILE_GET_INFO( get_bg_tile_info )
22	22	{
23	23	mcr68_state *state = machine.driver_data<mcr68_state>();
24		UINT16 *videoram = state->m_videoram16;
	24	UINT16 *videoram = state->m_videoram;
25	25	int data = LOW_BYTE(videoram[tile_index * 2]) | (LOW_BYTE(videoram[tile_index * 2 + 1]) << 8);
26	26	int code = (data & 0x3ff) | ((data >> 4) & 0xc00);
27	27	int color = (~data >> 12) & 3;
r14963	r14964
34	34	static TILE_GET_INFO( zwackery_get_bg_tile_info )
35	35	{
36	36	mcr68_state *state = machine.driver_data<mcr68_state>();
37		UINT16 *videoram = state->m_videoram16;
	37	UINT16 *videoram = state->m_videoram;
38	38	int data = videoram[tile_index];
39	39	int color = (data >> 13) & 7;
40	40	SET_TILE_INFO(0, data & 0x3ff, color, TILE_FLIPYX((data >> 11) & 3));
r14963	r14964
44	44	static TILE_GET_INFO( zwackery_get_fg_tile_info )
45	45	{
46	46	mcr68_state *state = machine.driver_data<mcr68_state>();
47		UINT16 *videoram = state->m_videoram16;
	47	UINT16 *videoram = state->m_videoram;
48	48	int data = videoram[tile_index];
49	49	int color = (data >> 13) & 7;
50	50	SET_TILE_INFO(2, data & 0x3ff, color, TILE_FLIPYX((data >> 11) & 3));
r14963	r14964
179	179
180	180	WRITE16_MEMBER(mcr68_state::mcr68_videoram_w)
181	181	{
182		UINT16 *videoram = m_videoram16;
	182	UINT16 *videoram = m_videoram;
183	183	COMBINE_DATA(&videoram[offset]);
184	184	m_bg_tilemap->mark_tile_dirty(offset / 2);
185	185	}
r14963	r14964
187	187
188	188	WRITE16_MEMBER(mcr68_state::zwackery_videoram_w)
189	189	{
190		UINT16 *videoram = m_videoram16;
	190	UINT16 *videoram = m_videoram;
191	191	COMBINE_DATA(&videoram[offset]);
192	192	m_bg_tilemap->mark_tile_dirty(offset);
193	193	m_fg_tilemap->mark_tile_dirty(offset);
r14963	r14964
198	198	{
199	199	/* yech -- Zwackery relies on the upper 8 bits of a spriteram read being $ff! */
200	200	/* to make this happen we always write $ff in the upper 8 bits */
201		COMBINE_DATA(&m_spriteram16[offset]);
202		m_spriteram16[offset] |= 0xff00;
	201	COMBINE_DATA(&m_spriteram[offset]);
	202	m_spriteram[offset] |= 0xff00;
203	203	}
204	204
205	205
r14963	r14964
214	214	{
215	215	mcr68_state *state = machine.driver_data<mcr68_state>();
216	216	rectangle sprite_clip = machine.primary_screen->visible_area();
217		UINT16 *spriteram16 = state->m_spriteram16;
	217	UINT16 *spriteram = state->m_spriteram;
218	218	int offs;
219	219
220	220	/* adjust for clipping */
r14963	r14964
225	225	machine.priority_bitmap.fill(1, sprite_clip);
226	226
227	227	/* loop over sprite RAM */
228		for (offs = state->m_spriteram16.bytes() / 2 - 4;offs >= 0;offs -= 4)
	228	for (offs = state->m_spriteram.bytes() / 2 - 4;offs >= 0;offs -= 4)
229	229	{
230	230	int code, color, flipx, flipy, x, y, flags;
231	231
232		flags = LOW_BYTE(spriteram16[offs + 1]);
233		code = LOW_BYTE(spriteram16[offs + 2]) + 256 * ((flags >> 3) & 0x01) + 512 * ((flags >> 6) & 0x03);
	232	flags = LOW_BYTE(spriteram[offs + 1]);
	233	code = LOW_BYTE(spriteram[offs + 2]) + 256 * ((flags >> 3) & 0x01) + 512 * ((flags >> 6) & 0x03);
234	234
235	235	/* skip if zero */
236	236	if (code == 0)
r14963	r14964
244	244	color = ~flags & 0x03;
245	245	flipx = flags & 0x10;
246	246	flipy = flags & 0x20;
247		x = LOW_BYTE(spriteram16[offs + 3]) * 2 + state->m_sprite_xoffset;
248		y = (241 - LOW_BYTE(spriteram16[offs])) * 2;
	247	x = LOW_BYTE(spriteram[offs + 3]) * 2 + state->m_sprite_xoffset;
	248	y = (241 - LOW_BYTE(spriteram[offs])) * 2;
249	249
250	250	/* allow sprites to clip off the left side */
251	251	if (x > 0x1f0) x -= 0x200;
r14963	r14964
267	267	static void zwackery_update_sprites(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, int priority)
268	268	{
269	269	mcr68_state *state = machine.driver_data<mcr68_state>();
270		UINT16 *spriteram16 = state->m_spriteram16;
	270	UINT16 *spriteram = state->m_spriteram;
271	271	int offs;
272	272
273	273	machine.priority_bitmap.fill(1, cliprect);
274	274
275	275	/* loop over sprite RAM */
276		for (offs = state->m_spriteram16.bytes() / 2 - 4;offs >= 0;offs -= 4)
	276	for (offs = state->m_spriteram.bytes() / 2 - 4;offs >= 0;offs -= 4)
277	277	{
278	278	int code, color, flipx, flipy, x, y, flags;
279	279
280	280	/* get the code and skip if zero */
281		code = LOW_BYTE(spriteram16[offs + 2]);
	281	code = LOW_BYTE(spriteram[offs + 2]);
282	282	if (code == 0)
283	283	continue;
284	284
285	285	/* extract the flag bits and determine the color */
286		flags = LOW_BYTE(spriteram16[offs + 1]);
	286	flags = LOW_BYTE(spriteram[offs + 1]);
287	287	color = ((~flags >> 2) & 0x0f) | ((flags & 0x02) << 3);
288	288
289	289	/* for low priority, draw everything but color 7 */
r14963	r14964
303	303	/* determine flipping and coordinates */
304	304	flipx = ~flags & 0x40;
305	305	flipy = flags & 0x80;
306		x = (231 - LOW_BYTE(spriteram16[offs + 3])) * 2;
307		y = (241 - LOW_BYTE(spriteram16[offs])) * 2;
	306	x = (231 - LOW_BYTE(spriteram[offs + 3])) * 2;
	307	y = (241 - LOW_BYTE(spriteram[offs])) * 2;
308	308
309	309	if (x <= -32) x += 512;
310	310

src/mame/video/gotcha.c

r14963	r14964
1	1	#include "emu.h"
2	2	#include "includes/gotcha.h"
	3	#include "video/decospr.h"
3	4
4	5	/***************************************************************************
5	6
r14963	r14964
100	101
101	102
102	103
103		static void draw_sprites( running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect )
104		{
105		gotcha_state *state = machine.driver_data<gotcha_state>();
106		UINT16 *spriteram = state->m_spriteram;
107		int offs;
108	104
109		for (offs = 0; offs < state->m_spriteram.bytes() / 2; offs += 4)
110		{
111		int sx, sy, code, color, flipx, flipy, height, y;
112
113		sx = spriteram[offs + 2];
114		sy = spriteram[offs + 0];
115		code = spriteram[offs + 1];
116		color = spriteram[offs + 2] >> 9;
117		height = 1 << ((spriteram[offs + 0] & 0x0600) >> 9);
118		flipx = spriteram[offs + 0] & 0x2000;
119		flipy = spriteram[offs + 0] & 0x4000;
120
121		for (y = 0; y < height; y++)
122		{
123		drawgfx_transpen(bitmap,cliprect,machine.gfx[1],
124		code + (flipy ? height-1 - y : y),
125		color,
126		flipx,flipy,
127		0x140-5 - ((sx + 0x10) & 0x1ff),0x100+1 - ((sy + 0x10 * (height - y)) & 0x1ff),0);
128		}
129		}
130		}
131
132
133	105	SCREEN_UPDATE_IND16( gotcha )
134	106	{
135	107	gotcha_state *state = screen.machine().driver_data<gotcha_state>();
136	108	state->m_bg_tilemap->draw(bitmap, cliprect, 0, 0);
137	109	state->m_fg_tilemap->draw(bitmap, cliprect, 0, 0);
138		draw_sprites(screen.machine(), bitmap, cliprect);
	110	screen.machine().device<decospr_device>("spritegen")->draw_sprites(bitmap, cliprect, state->m_spriteram, 0x400);
139	111	return 0;
140	112	}

src/mame/layout/bfm_sc4.lay

r14963	r14964
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	1630	</backdrop>
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	1636	</backdrop>
	1637	<backdrop name="matrix124" element="matrixlamp" state="0">
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	1639	</backdrop>
	1640	<backdrop name="matrix125" element="matrixlamp" state="0">
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	1642	</backdrop>
	1643	<backdrop name="matrix126" element="matrixlamp" state="0">
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	1645	</backdrop>
	1646	<backdrop name="matrix127" element="matrixlamp" state="0">
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	1648	</backdrop>
	1649	<backdrop name="matrix128" element="matrixlamp" state="0">
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	1651	</backdrop>
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	1654	</backdrop>
	1655	<backdrop name="matrix130" element="matrixlamp" state="0">
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	1657	</backdrop>
	1658	<backdrop name="matrix131" element="matrixlamp" state="0">
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	1660	</backdrop>
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	1663	</backdrop>
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	1669	</backdrop>
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	1672	</backdrop>
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	1675	</backdrop>
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	1681	</backdrop>
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	1684	</backdrop>
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	1687	</backdrop>
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	1693	</backdrop>
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	1696	</backdrop>
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	1699	</backdrop>
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	1714	</backdrop>
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	1744	</backdrop>
	1745
	1746	<!-- the rest of the elements tend to be used for 7-segs
	1747	so render them as both -->
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	1750	</backdrop>
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	1756	</backdrop>
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	1759	</backdrop>
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	1765	</backdrop>
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	1768	</backdrop>
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	1771	</backdrop>
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	1774	</backdrop>
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	1777	</backdrop>
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	1780	</backdrop>
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	1783	</backdrop>
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	1792	</backdrop>
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	1795	</backdrop>
	1796	<backdrop name="matrix176" element="matrixlamp" state="0">
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	1798	</backdrop>
	1799	<backdrop name="matrix177" element="matrixlamp" state="0">
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	1804	</backdrop>
	1805	<backdrop name="matrix179" element="matrixlamp" state="0">
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	1807	</backdrop>
	1808	<backdrop name="matrix180" element="matrixlamp" state="0">
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	1810	</backdrop>
	1811	<backdrop name="matrix181" element="matrixlamp" state="0">
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	1813	</backdrop>
	1814	<backdrop name="matrix182" element="matrixlamp" state="0">
	1815	<bounds y="24" x="288" width="3" height="3"/>
	1816	</backdrop>
	1817	<backdrop name="matrix183" element="matrixlamp" state="0">
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	1819	</backdrop>
	1820	<backdrop name="matrix184" element="matrixlamp" state="0">
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	1822	</backdrop>
	1823	<backdrop name="matrix185" element="matrixlamp" state="0">
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	1825	</backdrop>
	1826	<backdrop name="matrix186" element="matrixlamp" state="0">
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	1828	</backdrop>
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	1831	</backdrop>
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	1834	</backdrop>
	1835	<backdrop name="matrix189" element="matrixlamp" state="0">
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	1837	</backdrop>
	1838	<backdrop name="matrix190" element="matrixlamp" state="0">
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	1840	</backdrop>
	1841	<backdrop name="matrix191" element="matrixlamp" state="0">
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	1843	</backdrop>
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	1846	</backdrop>
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	1849	</backdrop>
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	1852	</backdrop>
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	1855	</backdrop>
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	1858	</backdrop>
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	1894	</backdrop>
	1895	<backdrop name="matrix209" element="matrixlamp" state="0">
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	1897	</backdrop>
	1898	<backdrop name="matrix210" element="matrixlamp" state="0">
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	1903	</backdrop>
	1904	<backdrop name="matrix212" element="matrixlamp" state="0">
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	1906	</backdrop>
	1907	<backdrop name="matrix213" element="matrixlamp" state="0">
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	1909	</backdrop>
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	1912	</backdrop>
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	1915	</backdrop>
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	1921	</backdrop>
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	1932	<bounds y="20" x="308" width="3" height="3"/>
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	1936	</backdrop>
	1937	<backdrop name="matrix223" element="matrixlamp" state="0">
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	1939	</backdrop>
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	1942	</backdrop>
	1943	<backdrop name="matrix225" element="matrixlamp" state="0">
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	1945	</backdrop>
	1946	<backdrop name="matrix226" element="matrixlamp" state="0">
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	1948	</backdrop>
	1949	<backdrop name="matrix227" element="matrixlamp" state="0">
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	1951	</backdrop>
	1952	<backdrop name="matrix228" element="matrixlamp" state="0">
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	1954	</backdrop>
	1955	<backdrop name="matrix229" element="matrixlamp" state="0">
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	1957	</backdrop>
	1958	<backdrop name="matrix230" element="matrixlamp" state="0">
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	1960	</backdrop>
	1961	<backdrop name="matrix231" element="matrixlamp" state="0">
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	1963	</backdrop>
	1964	<backdrop name="matrix232" element="matrixlamp" state="0">
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	1966	</backdrop>
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	1976	<backdrop name="matrix236" element="matrixlamp" state="0">
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	1979	<backdrop name="matrix237" element="matrixlamp" state="0">
	1980	<bounds y="20" x="316" width="3" height="3"/>
	1981	</backdrop>
	1982	<backdrop name="matrix238" element="matrixlamp" state="0">
	1983	<bounds y="24" x="316" width="3" height="3"/>
	1984	</backdrop>
	1985	<backdrop name="matrix239" element="matrixlamp" state="0">
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	1991	<backdrop name="matrix241" element="matrixlamp" state="0">
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	1993	</backdrop>
	1994	<backdrop name="matrix242" element="matrixlamp" state="0">
	1995	<bounds y="8" x="320" width="3" height="3"/>
	1996	</backdrop>
	1997	<backdrop name="matrix243" element="matrixlamp" state="0">
	1998	<bounds y="12" x="320" width="3" height="3"/>
	1999	</backdrop>
	2000	<backdrop name="matrix244" element="matrixlamp" state="0">
	2001	<bounds y="16" x="320" width="3" height="3"/>
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	2003	<backdrop name="matrix245" element="matrixlamp" state="0">
	2004	<bounds y="20" x="320" width="3" height="3"/>
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	2006	<backdrop name="matrix246" element="matrixlamp" state="0">
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	2009	<backdrop name="matrix247" element="matrixlamp" state="0">
	2010	<bounds y="28" x="320" width="3" height="3"/>
	2011	</backdrop>
	2012	<backdrop name="matrix248" element="matrixlamp" state="0">
	2013	<bounds y="0" x="324" width="3" height="3"/>
	2014	</backdrop>
	2015	<backdrop name="matrix249" element="matrixlamp" state="0">
	2016	<bounds y="4" x="324" width="3" height="3"/>
	2017	</backdrop>
	2018	<backdrop name="matrix250" element="matrixlamp" state="0">
	2019	<bounds y="8" x="324" width="3" height="3"/>
	2020	</backdrop>
	2021	<backdrop name="matrix251" element="matrixlamp" state="0">
	2022	<bounds y="12" x="324" width="3" height="3"/>
	2023	</backdrop>
	2024	<backdrop name="matrix252" element="matrixlamp" state="0">
	2025	<bounds y="16" x="324" width="3" height="3"/>
	2026	</backdrop>
	2027	<backdrop name="matrix253" element="matrixlamp" state="0">
	2028	<bounds y="20" x="324" width="3" height="3"/>
	2029	</backdrop>
	2030	<backdrop name="matrix254" element="matrixlamp" state="0">
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	2032	</backdrop>
	2033	<backdrop name="matrix255" element="matrixlamp" state="0">
	2034	<bounds y="28" x="324" width="3" height="3"/>
	2035	</backdrop>
	2036
	2037	<backdrop name="digit0" element="digit" state="0">
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	2039	</backdrop>
	2040	<backdrop name="digit1" element="digit" state="0">
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	2042	</backdrop>
	2043	<backdrop name="digit2" element="digit" state="0">
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	2045	</backdrop>
	2046	<backdrop name="digit3" element="digit" state="0">
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	2048	</backdrop>
	2049	<backdrop name="digit4" element="digit" state="0">
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	2054	</backdrop>
	2055	<backdrop name="digit6" element="digit" state="0">
	2056	<bounds x="300" y="64" width="18" height="34"/>
	2057	</backdrop>
	2058	<backdrop name="digit7" element="digit" state="0">
	2059	<bounds x="320" y="64" width="18" height="34"/>
	2060	</backdrop>
	2061	<backdrop name="digit8" element="digit" state="0">
	2062	<bounds x="340" y="64" width="18" height="34"/>
	2063	</backdrop>
	2064	<backdrop name="digit9" element="digit" state="0">
	2065	<bounds x="360" y="64" width="18" height="34"/>
	2066	</backdrop>
	2067	<backdrop name="digit10" element="digit" state="0">
	2068	<bounds x="380" y="64" width="18" height="34"/>
	2069	</backdrop>
	2070	<backdrop name="digit11" element="digit" state="0">
	2071	<bounds x="400" y="64" width="18" height="34"/>
	2072	</backdrop>
	2073
	2074
	2075
	2076	</view>
	2077	<view name="VFD Display Output Only">
10	2078	<backdrop name="vfd0" element="vfd0" state="0">
11		<bounds x="0" y="280" width="9" height="14"/>
	2079	<bounds x="10" y="200" width="9" height="17"/>
12	2080	</backdrop>
13	2081	<backdrop name="vfd1" element="vfd0" state="0">
14		<bounds x="9" y="280" width="9" height="14"/>
	2082	<bounds x="19" y="200" width="9" height="17"/>
15	2083	</backdrop>
16	2084	<backdrop name="vfd2" element="vfd0" state="0">
17		<bounds x="18" y="280" width="9" height="14"/>
	2085	<bounds x="28" y="200" width="9" height="17"/>
18	2086	</backdrop>
19	2087	<backdrop name="vfd3" element="vfd0" state="0">
20		<bounds x="27" y="280" width="9" height="14"/>
	2088	<bounds x="37" y="200" width="9" height="17"/>
21	2089	</backdrop>
22	2090	<backdrop name="vfd4" element="vfd0" state="0">
23		<bounds x="36" y="280" width="9" height="14"/>
	2091	<bounds x="46" y="200" width="9" height="17"/>
24	2092	</backdrop>
25	2093	<backdrop name="vfd5" element="vfd0" state="0">
26		<bounds x="45" y="280" width="9" height="14"/>
	2094	<bounds x="55" y="200" width="9" height="17"/>
27	2095	</backdrop>
28	2096	<backdrop name="vfd6" element="vfd0" state="0">
29		<bounds x="54" y="280" width="9" height="14"/>
	2097	<bounds x="64" y="200" width="9" height="17"/>
30	2098	</backdrop>
31	2099	<backdrop name="vfd7" element="vfd0" state="0">
32		<bounds x="63" y="280" width="9" height="14"/>
	2100	<bounds x="73" y="200" width="9" height="17"/>
33	2101	</backdrop>
34	2102	<backdrop name="vfd8" element="vfd0" state="0">
35		<bounds x="72" y="280" width="9" height="14"/>
	2103	<bounds x="82" y="200" width="9" height="17"/>
36	2104	</backdrop>
37	2105	<backdrop name="vfd9" element="vfd0" state="0">
38		<bounds x="81" y="280" width="9" height="14"/>
	2106	<bounds x="91" y="200" width="9" height="17"/>
39	2107	</backdrop>
40	2108	<backdrop name="vfd10" element="vfd0" state="0">
41		<bounds x="90" y="280" width="9" height="14"/>
	2109	<bounds x="100" y="200" width="9" height="17"/>
42	2110	</backdrop>
43	2111	<backdrop name="vfd11" element="vfd0" state="0">
44		<bounds x="99" y="280" width="9" height="14"/>
	2112	<bounds x="109" y="200" width="9" height="17"/>
45	2113	</backdrop>
46	2114	<backdrop name="vfd12" element="vfd0" state="0">
47		<bounds x="108" y="280" width="9" height="14"/>
	2115	<bounds x="118" y="200" width="9" height="17"/>
48	2116	</backdrop>
49	2117	<backdrop name="vfd13" element="vfd0" state="0">
50		<bounds x="117" y="280" width="9" height="14"/>
	2118	<bounds x="127" y="200" width="9" height="17"/>
51	2119	</backdrop>
52	2120	<backdrop name="vfd14" element="vfd0" state="0">
53		<bounds x="126" y="280" width="9" height="14"/>
	2121	<bounds x="136" y="200" width="9" height="17"/>
54	2122	</backdrop>
55	2123	<backdrop name="vfd15" element="vfd0" state="0">
56		<bounds x="135" y="280" width="9" height="14"/>
	2124	<bounds x="145" y="200" width="9" height="17"/>
57	2125	</backdrop>
58	2126	</view>
	2127	</mamelayout>
59	2128
60		</mamelayout>

src/mame/drivers/snowbros.c

r14963	r14964
1509	1509
1510	1510	static const ym2151_interface ym2151_config =
1511	1511	{
1512		irqhandler
	1512	DEVCB_LINE(irqhandler)
1513	1513	};
1514	1514
1515	1515

src/mame/drivers/segaxbd.c

r14963	r14964
1236	1236
1237	1237	static const ym2151_interface ym2151_config =
1238	1238	{
1239		sound_cpu_irq
	1239	DEVCB_LINE(sound_cpu_irq)
1240	1240	};
1241	1241
1242	1242

src/mame/drivers/dblewing.c

r14963	r14964
540	540
541	541	static const ym2151_interface ym2151_config =
542	542	{
543		sound_irq
	543	DEVCB_LINE(sound_irq)
544	544	};
545	545
546	546	static int dblewing_bank_callback( const int bank )

src/mame/drivers/hornet.c

r14963	r14964
336	336	UINT8 m_led_reg1;
337	337	required_shared_ptr<UINT32> m_workram;
338	338	required_shared_ptr<UINT32> m_sharc_dataram0;
339		required_shared_ptr<UINT32> m_sharc_dataram1;
	339	optional_shared_ptr<UINT32> m_sharc_dataram1;
340	340	UINT8 *m_jvs_sdata;
341	341	UINT32 m_jvs_sdata_ptr;
342	342	emu_timer *m_sound_irq_timer;

src/mame/drivers/ddragon3.c

r14963	r14964
521	521
522	522	static const ym2151_interface ym2151_config =
523	523	{
524		dd3_ymirq_handler
	524	DEVCB_LINE(dd3_ymirq_handler)
525	525	};
526	526
527	527	/*************************************

src/mame/drivers/fitfight.c

r14963	r14964
87	87	#include "sound/okim6295.h"
88	88	#include "includes/fitfight.h"
89	89
	90	READ16_MEMBER( fitfight_state::hotmindff_unk_r )
	91	{
	92	// won't boot unless things in here change, this is p1/p2 inputs in fitfight
	93	return space.machine().rand();
	94	}
90	95
91	96	READ16_MEMBER(fitfight_state::fitfight_700000_r)
92	97	{
r14963	r14964
169	174	AM_RANGE(0xd00000, 0xd007ff) AM_RAM AM_SHARE("spriteram")
170	175
171	176	AM_RANGE(0xe00000, 0xe0ffff) AM_RAM
	177	AM_RANGE(0xff0000, 0xffffff) AM_RAM // hot mind uses RAM here (mirror?)
172	178	ADDRESS_MAP_END
173	179
174	180	static ADDRESS_MAP_START( bbprot_main_map, AS_PROGRAM, 16, fitfight_state )
r14963	r14964
965	971	ROM_LOAD( "s16_h_mc.bin",  0x080000, 0x080000, CRC(3b9091de) SHA1(b426dab6361f5d48519dc9de146e1b2270af6c8b) )
966	972	ROM_END
967	973
	974	ROM_START( hotmindff )
	975	ROM_REGION( 0x100000, "maincpu", 0 ) /* 68000 Code */
	976	ROM_LOAD16_BYTE( "21.u138", 0x000001, 0x020000, CRC(00d9ba73) SHA1(5f33f7e9b9446cdc380e6236381d86c46f55ede7) )
	977	ROM_LOAD16_BYTE( "20.u125", 0x000000, 0x020000, CRC(8a7b2cc2) SHA1(031255cff4764dd61f5418be8090310193aa2e59) )
	978
	979	ROM_REGION( 0x01c000, "audiocpu", 0 ) /* Sound Program */
	980	ROM_LOAD( "22.u23",  0x000000, 0x004000, CRC(ca0327a2) SHA1(b725f625860dae4723e0ed4a6c7c29a2b1a3d15f) )
	981	ROM_CONTINUE(          0x010000, 0x00c000 )
	982
	983	ROM_REGION( 0x100000, "oki", 0 ) /* OKI Samples? */
	984	ROM_LOAD( "19.u18",  0x000000, 0x040000, CRC(296d71da) SHA1(49735012691a9e65c4da6132428f7a9149504fd3) )
	985
	986	ROM_REGION( 0x100000, "gfx1", 0 ) /* GFX */
	987	ROM_LOAD( "29.bin",  0x000000, 0x020000, CRC(cd4cab01) SHA1(90165f57adbfd7d85eaccfe794d347ed795dfba1) )
	988	ROM_LOAD( "30.bin",  0x040000, 0x020000, CRC(33f991b5) SHA1(8fddb5a3c78e73eb2a741aa970ff2c650a847317) )
	989	ROM_LOAD( "25.bin",  0x080000, 0x020000, CRC(21e7c729) SHA1(bf2a89ab54ef362bfee9fdcb7623d0f092559793) )
	990	ROM_LOAD( "26.bin",  0x0c0000, 0x020000, CRC(5802e7d0) SHA1(6a6661c753b31492295813952fc559e5189aae9f) )
	991
	992	ROM_REGION( 0x400000, "gfx2", 0 ) /* Sprites */
	993	ROM_LOAD( "23.bin",  0x000000, 0x020000, CRC(4d2c79ed) SHA1(df7004b11f5bcd51f7629fa1cc907976d9b8c8dc) )
	994	ROM_LOAD( "24.bin",  0x100000, 0x020000, CRC(f43618d0) SHA1(7c383582ebcab713f2d8e6b4c73fc0415465d62d) )
	995	ROM_LOAD( "27.bin",  0x200000, 0x020000, CRC(9cee7e50) SHA1(3e131b4acf35b58d511f7313425d002e939a7ff9) )
	996	ROM_LOAD( "28.bin",  0x300000, 0x020000, CRC(059c7bcf) SHA1(b9d8b1e1482baeede750a54749834c68c2d0cfef) )
	997	ROM_END
	998
	999
	1000
968	1001	/* INIT */
969	1002
970	1003	static DRIVER_INIT( fitfight )
r14963	r14964
991	1024	state->m_bbprot_kludge = 1;
992	1025	}
993	1026
	1027	DRIVER_INIT( hotmindff )
	1028	{
	1029	fitfight_state *state = machine.driver_data<fitfight_state>();
	1030	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x200000, 0x200001, 0, 0, read16_delegate(FUNC(fitfight_state::hotmindff_unk_r),state));
	1031	DRIVER_INIT_CALL(fitfight);
	1032	}
	1033
	1034
994	1035	/* GAME */
995	1036
996	1037	GAME( 199?, fitfight, 0, fitfight, fitfight, fitfight, ROT0, "bootleg", "Fit of Fighting", GAME_IMPERFECT_GRAPHICS | GAME_NO_SOUND | GAME_SUPPORTS_SAVE )
997	1038	GAME( 199?, histryma, 0, fitfight, histryma, histryma, ROT0, "bootleg", "The History of Martial Arts", GAME_IMPERFECT_GRAPHICS | GAME_NO_SOUND | GAME_SUPPORTS_SAVE )
998	1039	GAME( 199?, bbprot,   0, bbprot,   bbprot,   bbprot,   ROT0, "<unknown>", "unknown fighting game 'BB' (prototype)", GAME_IMPERFECT_GRAPHICS | GAME_NO_SOUND | GAME_SUPPORTS_SAVE )
	1040	GAME( 199?, hotmindff,  hotmind, fitfight,   fitfight,   hotmindff,   ROT0, "Playmark", "Hot Mind (Fit of Fighting hardware)", GAME_NOT_WORKING | GAME_NO_SOUND ) // need to fix scroll offsets + inputs

src/mame/drivers/deco32.c

r14963	r14964
1636	1636
1637	1637	static const ym2151_interface ym2151_config =
1638	1638	{
1639		sound_irq,
1640		sound_bankswitch_w
	1639	DEVCB_LINE(sound_irq),
	1640	DEVCB_HANDLER(sound_bankswitch_w)
1641	1641	};
1642	1642
1643	1643	static const ym2151_interface ym2151_interface_nslasher =
1644	1644	{
1645		sound_irq_nslasher,
1646		sound_bankswitch_w
	1645	DEVCB_LINE(sound_irq_nslasher),
	1646	DEVCB_HANDLER(sound_bankswitch_w)
1647	1647	};
1648	1648
1649	1649	static const eeprom_interface eeprom_interface_tattass =

src/mame/drivers/segaybd.c

r14963	r14964
917	917
918	918	static const ym2151_interface ym2151_config =
919	919	{
920		sound_cpu_irq
	920	DEVCB_LINE(sound_cpu_irq)
921	921	};
922	922
923	923

src/mame/drivers/aliens.c

r14963	r14964
206	206
207	207	static const ym2151_interface ym2151_config =
208	208	{
209		0,
210		aliens_snd_bankswitch_w
	209	DEVCB_NULL,
	210	DEVCB_HANDLER(aliens_snd_bankswitch_w)
211	211	};
212	212
213	213

src/mame/drivers/chinagat.c

r14963	r14964
500	500
501	501	static const ym2151_interface ym2151_config =
502	502	{
503		chinagat_irq_handler
	503	DEVCB_LINE(chinagat_irq_handler)
504	504	};
505	505
506	506	/* This on the bootleg board, instead of the m6295 */

src/mame/drivers/namcos10.c

r14963	r14964
500	500	psx_driver_init(machine);
501	501	}
502	502
503		static void decrypt_bios( running_machine &machine, int start, int end, int b15, int b14, int b13, int b12, int b11, int b10, int b9, int b8,
	503	static void decrypt_bios( running_machine &machine, const char *regionName, int start, int b15, int b14, int b13, int b12, int b11, int b10, int b9, int b8,
504	504	int b7, int b6, int b5, int b4, int b3, int b2, int b1, int b0 )
505	505	{
506		UINT16 *BIOS = (UINT16 *)(machine.region( "user1" )->base() + start);
507		int len = (end - start)/2;
	506	const memory_region *region = machine.region( regionName );
	507	UINT16 *BIOS = (UINT16 *)( region->base() + start );
	508	int len = (region->bytes()-start)/2;
508	509
509	510	for( int i = 0; i < len; i++ )
510	511	{
r14963	r14964
515	516
516	517	static DRIVER_INIT( mrdrilr2 )
517	518	{
	519	decrypt_bios( machine, "user1", 0, 0xc, 0xd, 0xf, 0xe, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x4, 0x1, 0x2, 0x5, 0x0, 0x3 );
518	520	memm_driver_init(machine);
519		decrypt_bios( machine, 0x000000, 0x041000, 0xc, 0xd, 0xf, 0xe, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x4, 0x1, 0x2, 0x5, 0x0, 0x3 );
520		decrypt_bios( machine, 0x060000, 0x062000, 0xc, 0xd, 0xf, 0xe, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x4, 0x1, 0x2, 0x5, 0x0, 0x3 );
521	521	}
522	522
523	523	static DRIVER_INIT( gjspace )
524	524	{
	525	decrypt_bios( machine, "user2", 0x8400, 0x0, 0x2, 0xe, 0xd, 0xf, 0x6, 0xc, 0x7, 0x5, 0x1, 0x9, 0x8, 0xa, 0x3, 0x4, 0xb );
525	526	memn_driver_init(machine);
526		decrypt_bios( machine, 0x000000, 0x400000, 0x0, 0x2, 0xe, 0xd, 0xf, 0x6, 0xc, 0x7, 0x5, 0x1, 0x9, 0x8, 0xa, 0x3, 0x4, 0xb );
527	527	}
528	528
529	529	static DRIVER_INIT( mrdrilrg )
530	530	{
	531	decrypt_bios( machine, "user2", 0x8400, 0x6, 0x4, 0x7, 0x5, 0x2, 0x1, 0x0, 0x3, 0xc, 0xd, 0xe, 0xf, 0x8, 0x9, 0xb, 0xa );
531	532	memn_driver_init(machine);
532		decrypt_bios( machine, 0x000000, 0x400000, 0x6, 0x4, 0x7, 0x5, 0x2, 0x1, 0x0, 0x3, 0xc, 0xd, 0xe, 0xf, 0x8, 0x9, 0xb, 0xa );
533	533	}
534	534
535	535	static DRIVER_INIT( knpuzzle )
536	536	{
	537	decrypt_bios( machine, "user2", 0x8400, 0x6, 0x7, 0x4, 0x5, 0x2, 0x0, 0x3, 0x1, 0xc, 0xd, 0xe, 0xf, 0x9, 0xb, 0x8, 0xa );
537	538	memn_driver_init(machine);
538		decrypt_bios( machine, 0x000000, 0x400000, 0x6, 0x7, 0x4, 0x5, 0x2, 0x0, 0x3, 0x1, 0xc, 0xd, 0xe, 0xf, 0x9, 0xb, 0x8, 0xa );
539	539	}
540	540
541	541	static DRIVER_INIT( startrgn )
542	542	{
	543	decrypt_bios( machine, "user2", 0x8400, 0x6, 0x5, 0x4, 0x7, 0x1, 0x3, 0x0, 0x2, 0xc, 0xd, 0xe, 0xf, 0x8, 0xb, 0xa, 0x9 );
543	544	memn_driver_init(machine);
544		decrypt_bios( machine, 0x000000, 0x400000, 0x6, 0x5, 0x4, 0x7, 0x1, 0x3, 0x0, 0x2, 0xc, 0xd, 0xe, 0xf, 0x8, 0xb, 0xa, 0x9 );
545	545	}
546	546
547	547	static DRIVER_INIT( gamshara )
548	548	{
	549	decrypt_bios( machine, "user2", 0x8400, 0x5, 0x4, 0x7, 0x6, 0x0, 0x1, 0x3, 0x2, 0xd, 0xf, 0xc, 0xe, 0x8, 0x9, 0xa, 0xb );
549	550	memn_driver_init(machine);
550		decrypt_bios( machine, 0x000000, 0x400000, 0x5, 0x4, 0x7, 0x6, 0x0, 0x1, 0x3, 0x2, 0xd, 0xf, 0xc, 0xe, 0x8, 0x9, 0xa, 0xb );
551	551	}
552	552
553	553	static DRIVER_INIT( gunbalna )
554	554	{
	555	decrypt_bios( machine, "user2", 0x8400, 0x5, 0x4, 0x7, 0x6, 0x0, 0x1, 0x3, 0x2, 0xd, 0xf, 0xc, 0xe, 0x9, 0x8, 0xa, 0xb );
555	556	memn_driver_init(machine);
556		decrypt_bios( machine, 0x000000, 0x400000, 0x5, 0x4, 0x7, 0x6, 0x0, 0x1, 0x3, 0x2, 0xd, 0xf, 0xc, 0xe, 0x9, 0x8, 0xa, 0xb );
557	557	}
558	558
559	559	static DRIVER_INIT( chocovdr )
560	560	{
561		memn_driver_init(machine);
562	561	//  NOTE: none of the possible permutations show the Sony Computer Entertainment string at BIOS[0x84], very likely a bad dump
563	562	//                                             BAD? 0 or 9                             1 or 8         0 or 9
564	563	//                         ok!  ok!  ok!  ok!            ok!  ok!  ok!  ok!  ok!  ok!       ok!  ok!
565		decrypt_bios( machine, 0x000000, 0x400000, 0x5, 0x4, 0x6, 0x7, 0x1, 0x0, 0x2, 0x3, 0xc, 0xf, 0xe, 0xd, 0x8, 0xb, 0xa, 0x9 );
	564	decrypt_bios( machine, "user2", 0x8400, 0x5, 0x4, 0x6, 0x7, 0x1, 0x0, 0x2, 0x3, 0xc, 0xf, 0xe, 0xd, 0x8, 0xb, 0xa, 0x9 );
	565	memn_driver_init(machine);
566	566	}
567	567
568	568	static DRIVER_INIT( panikuru )
569	569	{
	570	decrypt_bios( machine, "user2", 0x8400, 0x6, 0x4, 0x7, 0x5, 0x0, 0x1, 0x2, 0x3, 0xc, 0xf, 0xe, 0xd, 0x9, 0x8, 0xb, 0xa );
570	571	memn_driver_init(machine);
571		decrypt_bios( machine, 0x000000, 0x400000, 0x6, 0x4, 0x7, 0x5, 0x0, 0x1, 0x2, 0x3, 0xc, 0xf, 0xe, 0xd, 0x9, 0x8, 0xb, 0xa );
572	572	}
573	573
574	574	static DRIVER_INIT( nflclsfb )
575	575	{
	576	decrypt_bios( machine, "user2", 0x8400, 0x6, 0x5, 0x4, 0x7, 0x1, 0x3, 0x0, 0x2, 0xc, 0xd, 0xe, 0xf, 0x8, 0xb, 0xa, 0x9 );
576	577	memn_driver_init(machine);
577		decrypt_bios( machine, 0x000000, 0x400000, 0x6, 0x5, 0x4, 0x7, 0x1, 0x3, 0x0, 0x2, 0xc, 0xd, 0xe, 0xf, 0x8, 0xb, 0xa, 0x9 );
578	578	}
579	579
580	580

src/mame/drivers/mpu4.c

r14963	r14964
528	528
529	529	READ8_MEMBER(mpu4_state::bankswitch_r)
530	530	{
531		return machine().memory().bank("bank1");
	531	return machine().memory().bank("bank1")->entry();
532	532	}
533	533
534	534

src/mame/drivers/darkseal.c

r14963	r14964
229	229
230	230	static const ym2151_interface ym2151_config =
231	231	{
232		sound_irq
	232	DEVCB_LINE(sound_irq)
233	233	};
234	234
235	235	static const deco16ic_interface darkseal_deco16ic_tilegen1_intf =

src/mame/drivers/mcr3.c

r14963	r14964
104	104	#include "emu.h"
105	105	#include "cpu/z80/z80.h"
106	106	#include "machine/z80ctc.h"
107		#include "audio/mcr.h"
	107	#include "audio/midway.h"
108	108	#include "machine/nvram.h"
109	109	#include "includes/mcr.h"
110	110	#include "includes/mcr3.h"
r14963	r14964
162	162	if (data & 0x40) m_input_mux = 1;
163	163
164	164	/* low 5 bits control the turbo CS */
165		turbocs_data_w(space, offset, data);
	165	m_turbo_chip_squeak->write(space, offset, data);
166	166	}
167	167
168	168
r14963	r14964
265	265	m_maxrpm_adc_select = (m_maxrpm_adc_control >> 1) & 3;
266	266
267	267	/* low 5 bits control the turbo CS */
268		turbocs_data_w(space, offset, data);
	268	m_turbo_chip_squeak->write(space, offset, data);
269	269	}
270	270
271	271
r14963	r14964
278	278
279	279	READ8_MEMBER(mcr3_state::rampage_ip4_r)
280	280	{
281		return input_port_read(machine(), "MONO.IP4") | (soundsgood_status_r(space,0) << 7);
	281	return input_port_read(machine(), "MONO.IP4") | (m_sounds_good->read(space,0) << 7);
282	282	}
283	283
284	284
285	285	WRITE8_MEMBER(mcr3_state::rampage_op6_w)
286	286	{
287	287	/* bit 5 controls reset of the Sounds Good board */
288		soundsgood_reset_w(machine(), (~data >> 5) & 1);
	288	m_sounds_good->reset_write((~data >> 5) & 1);
289	289
290	290	/* low 5 bits go directly to the Sounds Good board */
291		soundsgood_data_w(space, offset, data);
	291	m_sounds_good->write(space, offset, data);
292	292	}
293	293
294	294
r14963	r14964
301	301
302	302	READ8_MEMBER(mcr3_state::powerdrv_ip2_r)
303	303	{
304		return input_port_read(machine(), "MONO.IP2") | (soundsgood_status_r(space, 0) << 7);
	304	return input_port_read(machine(), "MONO.IP2") | (m_sounds_good->read(space, 0) << 7);
305	305	}
306	306
307	307
r14963	r14964
329	329	WRITE8_MEMBER(mcr3_state::powerdrv_op6_w)
330	330	{
331	331	/* bit 5 controls reset of the Sounds Good board */
332		soundsgood_reset_w(machine(), (~data >> 5) & 1);
	332	m_sounds_good->reset_write((~data >> 5) & 1);
333	333
334	334	/* low 5 bits go directly to the Sounds Good board */
335		soundsgood_data_w(space, offset, data);
	335	m_sounds_good->write(space, offset, data);
336	336	}
337	337
338	338
r14963	r14964
348	348	UINT8 result = input_port_read(machine(), "MONO.IP0");
349	349	if (m_input_mux)
350	350	result = (result & ~0x0a) | (input_port_read(machine(), "MONO.IP0.ALT") & 0x0a);
351		return (result & ~0x10) | ((soundsgood_status_r(space, 0) << 4) & 0x10);
	351	return (result & ~0x10) | ((m_sounds_good->read(space, 0) << 4) & 0x10);
352	352	}
353	353
354	354
r14963	r14964
372	372	WRITE8_MEMBER(mcr3_state::stargrds_op6_w)
373	373	{
374	374	/* bit 6 controls reset of the Sounds Good board */
375		soundsgood_reset_w(machine(), (~data >> 6) & 1);
	375	m_sounds_good->reset_write((~data >> 6) & 1);
376	376
377	377	/* unline the other games, the STROBE is in the high bit instead of the low bit */
378		soundsgood_data_w(space, offset, (data << 1) | (data >> 7));
	378	m_sounds_good->write(space, offset, (data << 1) | (data >> 7));
379	379	}
380	380
381	381
r14963	r14964
388	388
389	389	READ8_MEMBER(mcr3_state::spyhunt_ip1_r)
390	390	{
391		return input_port_read(machine(), "SSIO.IP1") | (csdeluxe_status_r(space, 0) << 5);
	391	return input_port_read(machine(), "ssio:IP1") | (m_chip_squeak_deluxe->read(space, 0) << 5);
392	392	}
393	393
394	394
395	395	READ8_MEMBER(mcr3_state::spyhunt_ip2_r)
396	396	{
397	397	/* multiplexed steering wheel/gas pedal */
398		return input_port_read(machine(), m_input_mux ? "SSIO.IP2.ALT" : "SSIO.IP2");
	398	return input_port_read(machine(), m_input_mux ? "ssio:IP2.ALT" : "ssio:IP2");
399	399	}
400	400
401	401
r14963	r14964
432	432	m_last_op4 = data;
433	433
434	434	/* low 5 bits go to control the Chip Squeak Deluxe */
435		csdeluxe_data_w(space, offset, data);
	435	m_chip_squeak_deluxe->write(space, offset, data);
436	436	}
437	437
438	438
r14963	r14964
447	447	{
448	448	/* multiplexed steering wheel/gas pedal */
449	449	if (m_input_mux)
450		return input_port_read(machine(), "SSIO.IP2.ALT");
	450	return input_port_read(machine(), "ssio:IP2.ALT");
451	451
452		return input_port_read(machine(), "SSIO.IP2") + 5 * (machine().primary_screen->frame_number() & 1);
	452	return input_port_read(machine(), "ssio:IP2") + 5 * (machine().primary_screen->frame_number() & 1);
453	453	}
454	454
455	455
r14963	r14964
523	523	static ADDRESS_MAP_START( spyhunt_portmap, AS_IO, 8, mcr3_state )
524	524	ADDRESS_MAP_UNMAP_HIGH
525	525	ADDRESS_MAP_GLOBAL_MASK(0xff)
526		SSIO_INPUT_PORTS
	526	SSIO_INPUT_PORTS("ssio")
527	527	AM_RANGE(0x84, 0x86) AM_WRITE(spyhunt_scroll_value_w)
528	528	AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
529	529	AM_RANGE(0xe8, 0xe8) AM_WRITENOP
r14963	r14964
886	886
887	887	/* verified from wiring diagram, plus DIP switches from manual */
888	888	static INPUT_PORTS_START( spyhunt )
889		PORT_START("SSIO.IP0")   /* J4 1-8 */
	889	PORT_START("ssio:IP0")   /* J4 1-8 */
890	890	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
891	891	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
892	892	PORT_BIT( 0x0c, IP_ACTIVE_LOW, IPT_UNUSED )
r14963	r14964
895	895	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
896	896	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
897	897
898		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	898	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
899	899	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Oil Slick")
900	900	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("Missiles")
901	901	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Weapon Truck")
r14963	r14964
904	904	PORT_BIT( 0x60, IP_ACTIVE_HIGH, IPT_SPECIAL )   /* status from CS deluxe, never read */
905	905	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
906	906
907		PORT_START("SSIO.IP2")   /* J5 1-8 */
	907	PORT_START("ssio:IP2")   /* J5 1-8 */
908	908	PORT_BIT( 0xff, 0x30, IPT_PEDAL ) PORT_MINMAX(0x30,0xff) PORT_SENSITIVITY(100) PORT_KEYDELTA(10)
909	909
910		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	910	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
911	911	PORT_DIPNAME( 0x01, 0x01, "Game Timer" )
912	912	PORT_DIPSETTING(    0x00, "1:00" )
913	913	PORT_DIPSETTING(    0x01, "1:30" )
r14963	r14964
918	918	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
919	919	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
920	920
921		PORT_START("SSIO.IP4")   /* J6 1-8 */
	921	PORT_START("ssio:IP4")   /* J6 1-8 */
922	922	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
923	923
924		PORT_START("SSIO.DIP")
	924	PORT_START("ssio:DIP")
925	925	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
926	926
927		PORT_START("SSIO.IP2.ALT")
	927	PORT_START("ssio:IP2.ALT")
928	928	PORT_BIT( 0xff, 0x74, IPT_PADDLE ) PORT_MINMAX(0x34,0xb4) PORT_SENSITIVITY(40) PORT_KEYDELTA(10)
929	929	INPUT_PORTS_END
930	930
931	931
932	932	/* not verified, no manual found */
933	933	static INPUT_PORTS_START( crater )
934		PORT_START("SSIO.IP0")   /* J4 1-8 */
	934	PORT_START("ssio:IP0")   /* J4 1-8 */
935	935	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
936	936	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
937	937	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
941	941	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
942	942	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
943	943
944		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	944	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
945	945	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(25) PORT_KEYDELTA(10) PORT_CODE_DEC(KEYCODE_Z) PORT_CODE_INC(KEYCODE_X) PORT_REVERSE
946	946
947		PORT_START("SSIO.IP2")   /* J5 1-8 */
	947	PORT_START("ssio:IP2")   /* J5 1-8 */
948	948	PORT_BIT( 0x03, IP_ACTIVE_LOW, IPT_UNUSED )
949	949	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_2WAY
950	950	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_2WAY
r14963	r14964
953	953	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 )
954	954	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
955	955
956		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	956	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
957	957	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
958	958
959		PORT_START("SSIO.IP4")   /* J6 1-8 */
	959	PORT_START("ssio:IP4")   /* J6 1-8 */
960	960	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
961	961
962		PORT_START("SSIO.DIP")
	962	PORT_START("ssio:DIP")
963	963	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
964	964	INPUT_PORTS_END
965	965
966	966
967	967	/* not verified, no manual found */
968	968	static INPUT_PORTS_START( turbotag )
969		PORT_START("SSIO.IP0")   /* J4 1-8 */
	969	PORT_START("ssio:IP0")   /* J4 1-8 */
970	970	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
971	971	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
972	972	PORT_BIT( 0x0c, IP_ACTIVE_LOW, IPT_UNUSED )
r14963	r14964
975	975	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
976	976	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
977	977
978		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	978	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
979	979	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Left Button")
980	980	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("Left Trigger")
981	981	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Center Button")
r14963	r14964
984	984	PORT_BIT( 0x60, IP_ACTIVE_HIGH, IPT_SPECIAL )   /* status from CS deluxe, never read */
985	985	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
986	986
987		PORT_START("SSIO.IP2")   /* J5 1-8 */
	987	PORT_START("ssio:IP2")   /* J5 1-8 */
988	988	PORT_BIT( 0xff, 0x3c, IPT_PEDAL ) PORT_MINMAX(60,180) PORT_SENSITIVITY(100) PORT_KEYDELTA(10)
989	989
990		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	990	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
991	991	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
992	992	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Demo_Sounds ) )
993	993	PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
r14963	r14964
996	996	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
997	997	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
998	998
999		PORT_START("SSIO.IP4")   /* J6 1-8 */
	999	PORT_START("ssio:IP4")   /* J6 1-8 */
1000	1000	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1001	1001
1002		PORT_START("SSIO.DIP")
	1002	PORT_START("ssio:DIP")
1003	1003	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1004	1004
1005		PORT_START("SSIO.IP2.ALT")
	1005	PORT_START("ssio:IP2.ALT")
1006	1006	PORT_BIT( 0xff, 0x60, IPT_PADDLE ) PORT_SENSITIVITY(40) PORT_KEYDELTA(10)
1007	1007	INPUT_PORTS_END
1008	1008
r14963	r14964
1089	1089	MCFG_MACHINE_START(mcr)
1090	1090	MCFG_MACHINE_RESET(mcr)
1091	1091	MCFG_NVRAM_ADD_0FILL("nvram")
	1092
	1093	// sound hardware
	1094	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1092	1095
1093	1096	/* video hardware */
1094	1097	MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
r14963	r14964
1114	1117	static MACHINE_CONFIG_DERIVED( mono_tcs, mcrmono )
1115	1118
1116	1119	/* basic machine hardware */
1117		MCFG_FRAGMENT_ADD(turbo_chip_squeak)
	1120	MCFG_MIDWAY_TURBO_CHIP_SQUEAK_ADD("tcs")
	1121	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
	1122	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
1118	1123	MACHINE_CONFIG_END
1119	1124
1120	1125
r14963	r14964
1122	1127	static MACHINE_CONFIG_DERIVED( mono_sg, mcrmono )
1123	1128
1124	1129	/* basic machine hardware */
1125		MCFG_FRAGMENT_ADD(sounds_good)
	1130	MCFG_MIDWAY_SOUNDS_GOOD_ADD("sg")
	1131	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
	1132	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
1126	1133	MACHINE_CONFIG_END
1127	1134
1128	1135
r14963	r14964
1133	1140	static MACHINE_CONFIG_DERIVED( mcrscroll, mcrmono )
1134	1141
1135	1142	/* basic machine hardware */
1136		MCFG_FRAGMENT_ADD(mcr_ssio)
	1143	MCFG_MIDWAY_SSIO_ADD("ssio")
	1144	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
	1145	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
1137	1146
1138	1147	MCFG_CPU_MODIFY("maincpu")
1139	1148	MCFG_CPU_PROGRAM_MAP(spyhunt_map)
r14963	r14964
1156	1165	static MACHINE_CONFIG_DERIVED( mcrsc_csd, mcrscroll )
1157	1166
1158	1167	/* basic machine hardware */
1159		MCFG_FRAGMENT_ADD(chip_squeak_deluxe_stereo)
	1168	MCFG_MIDWAY_CHIP_SQUEAK_DELUXE_ADD("csd")
	1169	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
	1170	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
1160	1171	MACHINE_CONFIG_END
1161	1172
1162	1173
r14963	r14964
1173	1184	ROM_LOAD( "pro1.5b",      0x08000, 0x8000, CRC(034c00fc) SHA1(0f0e8f123a34c330021bce76ed7f38bcb2e9af4e) )
1174	1185	ROM_FILL(                 0x0e000, 0x2000, 0xff )   /* upper 8k is not mapped on monoboard */
1175	1186
1176		ROM_REGION( 0x10000, "tcscpu", 0 )   /* 64k for the Turbo Cheap Squeak */
	1187	ROM_REGION( 0x10000, "tcs:cpu", 0 )   /* 64k for the Turbo Cheap Squeak */
1177	1188	ROM_LOAD( "tcs_u5.bin",   0x0c000, 0x2000, CRC(eca33b2c) SHA1(938b021ea3b0f23aed7a98a930a58af371a02303) )
1178	1189	ROM_LOAD( "tcs_u4.bin",   0x0e000, 0x2000, CRC(3490289a) SHA1(a9d56ea60bb901267da41ab408f8e1ed3742b0ac) )
1179	1190
r14963	r14964
1199	1210	ROM_LOAD( "cpu_5b.bin",   0x08000, 0x8000, CRC(6800e746) SHA1(018c2b622b3654530ebc2c299b3f745777163d4b) )
1200	1211	ROM_FILL(                 0x0e000, 0x2000, 0xff )   /* upper 8k is not mapped on monoboard */
1201	1212
1202		ROM_REGION( 0x10000, "tcscpu", 0 )  /* 64k for the Turbo Cheap Squeak */
	1213	ROM_REGION( 0x10000, "tcs:cpu", 0 )  /* 64k for the Turbo Cheap Squeak */
1203	1214	ROM_LOAD( "tcs_u5.bin",   0xc000, 0x2000, CRC(a894ef8a) SHA1(7f53927fc185fff8ba1b1747f0d565e089d879e6) )
1204	1215	ROM_LOAD( "tcs_u4.bin",   0xe000, 0x2000, CRC(6ca6faf3) SHA1(4647e633dd11f55a65c3acf81adeb3af93624991) )
1205	1216
r14963	r14964
1230	1241	ROM_LOAD( "pro.1",        0x08000, 0x8000, CRC(f628bb30) SHA1(0514906b9764a7f02a730a610affea4d42a4510d) )
1231	1242	ROM_FILL(                 0x0e000, 0x2000, 0xff )   /* upper 8k is not mapped on monoboard */
1232	1243
1233		ROM_REGION( 0x10000, "tcscpu", 0 )  /* 64k for the Turbo Cheap Squeak */
	1244	ROM_REGION( 0x10000, "tcs:cpu", 0 )  /* 64k for the Turbo Cheap Squeak */
1234	1245	ROM_LOAD( "turbskwk.u5",   0x8000, 0x4000, CRC(55c3b759) SHA1(89d690a007a996e9c7df7b365942e4da755d15d7) )
1235	1246	ROM_LOAD( "turbskwk.u4",   0xc000, 0x4000, CRC(31a2da2e) SHA1(582434b5d6bc8e84f39191976d8aa0ef9245f253) )
1236	1247
r14963	r14964
1252	1263	ROM_LOAD( "pro1rev3.5b",  0x08000, 0x8000, CRC(d89bd9a4) SHA1(3531464ffe49dfaf2755d9e2dc1aea23819b3a5d) )
1253	1264	ROM_FILL(                 0x0e000, 0x2000, 0xff )   /* upper 8k is not mapped on monoboard */
1254	1265
1255		ROM_REGION( 0x40000, "sgcpu", 0 )  /* 256k for the Sounds Good board */
	1266	ROM_REGION( 0x40000, "sg:cpu", 0 )  /* 256k for the Sounds Good board */
1256	1267	ROM_LOAD16_BYTE( "ramp_u7.snd",  0x00000, 0x8000, CRC(cffd7fa5) SHA1(7c5cecce1d428f847fea37d53eb09c6f62055c6f) )   /* these are Revision 2 sound ROMs */
1257	1268	ROM_LOAD16_BYTE( "ramp_u17.snd", 0x00001, 0x8000, CRC(e92c596b) SHA1(4e2d87398f2e7b637cbad6cb16d832dfa8f8288c) )
1258	1269	ROM_LOAD16_BYTE( "ramp_u8.snd",  0x10000, 0x8000, CRC(11f787e4) SHA1(1fa195bf9169608099d17be5801738a4e17bec3d) )
r14963	r14964
1276	1287	ROM_LOAD( "pro1rev2.5b",  0x08000, 0x8000, CRC(58523d75) SHA1(5cd512864568ec7793bda0164f21e7d72a7ea817) )
1277	1288	ROM_FILL(                 0x0e000, 0x2000, 0xff )   /* upper 8k is not mapped on monoboard */
1278	1289
1279		ROM_REGION( 0x40000, "sgcpu", 0 )  /* 256k for the Sounds Good board */
	1290	ROM_REGION( 0x40000, "sg:cpu", 0 )  /* 256k for the Sounds Good board */
1280	1291	ROM_LOAD16_BYTE( "ramp_u7.snd",  0x00000, 0x8000, CRC(cffd7fa5) SHA1(7c5cecce1d428f847fea37d53eb09c6f62055c6f) )    /* these are Revision 2 sound ROMs */
1281	1292	ROM_LOAD16_BYTE( "ramp_u17.snd", 0x00001, 0x8000, CRC(e92c596b) SHA1(4e2d87398f2e7b637cbad6cb16d832dfa8f8288c) )
1282	1293	ROM_LOAD16_BYTE( "ramp_u8.snd",  0x10000, 0x8000, CRC(11f787e4) SHA1(1fa195bf9169608099d17be5801738a4e17bec3d) )
r14963	r14964
1300	1311	ROM_LOAD( "pdrv5b.bin",   0x08000, 0x8000, CRC(fa0544ad) SHA1(55a9cf8c8648761443e4a5a3b214f4d6236cbaff) )
1301	1312	ROM_FILL(                 0x0e000, 0x2000, 0xff )   /* upper 8k is not mapped on monoboard */
1302	1313
1303		ROM_REGION( 0x40000, "sgcpu", 0 )  /* 256k for the Sounds Good board */
	1314	ROM_REGION( 0x40000, "sg:cpu", 0 )  /* 256k for the Sounds Good board */
1304	1315	ROM_LOAD16_BYTE( "pdsndu7.bin",  0x00000, 0x8000, CRC(78713e78) SHA1(11382c024536f743e051ba208ae02d0f5e07cf5e) )
1305	1316	ROM_LOAD16_BYTE( "pdsndu17.bin", 0x00001, 0x8000, CRC(c41de6e4) SHA1(0391afd96ee80dd1d4a34e661e5df1e01fbbd57a) )
1306	1317	ROM_LOAD16_BYTE( "pdsndu8.bin",  0x10000, 0x8000, CRC(15714036) SHA1(77ca5f703eb7f146e13d9c01f4427f6aaa31df39) )
r14963	r14964
1324	1335	ROM_LOAD( "pro-1.5b",  0x08000, 0x8000, CRC(dba428b0) SHA1(72efa2f02e95f05a5503ced136fbdf3fcdf57554) )
1325	1336	ROM_FILL(              0x0e000, 0x2000, 0xff )   /* upper 8k is not mapped on monoboard */
1326	1337
1327		ROM_REGION( 0x40000, "sgcpu", 0 )  /* 256k for the Sounds Good board */
	1338	ROM_REGION( 0x40000, "sg:cpu", 0 )  /* 256k for the Sounds Good board */
1328	1339	ROM_LOAD16_BYTE( "snd0.u7",      0x00000, 0x8000, CRC(7755a493) SHA1(a888fba45a2a31de5b3082bfc5ccef94dafc4d16) )
1329	1340	ROM_LOAD16_BYTE( "snd1.u17",     0x00001, 0x8000, CRC(d98d14ae) SHA1(51dbb97655ab8a389ca67f0e796ab57894f5bb32) )
1330	1341
r14963	r14964
1349	1360	ROM_LOAD( "cpu_pg4.10d",  0x8000, 0x2000, CRC(a3033c15) SHA1(e9811450a7c952561912777d679fe45a6b5a794a) )
1350	1361	ROM_LOAD( "cpu_pg5.11d",  0xa000, 0x4000, CRC(53a4f7cd) SHA1(051b07ae993e14b329507710c0f7cadaa952f9ae) )
1351	1362
1352		ROM_REGION( 0x10000, "ssiocpu", 0 )
	1363	ROM_REGION( 0x10000, "ssio:cpu", 0 )
1353	1364	ROM_LOAD( "snd_0sd.a8",   0x0000, 0x1000, CRC(c95cf31e) SHA1(d1b0e299a27e306ddbc0654fd3a9d981c92afe8c) )
1354	1365	ROM_LOAD( "snd_1sd.a7",   0x1000, 0x1000, CRC(12aaa48e) SHA1(c6b835fc45e4484a4d52b682ce015caa242c8b4f) )
1355	1366
1356		ROM_REGION( 0x8000, "csdcpu", 0 )  /* 32k for the Chip Squeak Deluxe */
	1367	ROM_REGION( 0x8000, "csd:cpu", 0 )  /* 32k for the Chip Squeak Deluxe */
1357	1368	ROM_LOAD16_BYTE( "csd_u7a.u7",   0x00000, 0x2000, CRC(6e689fe7) SHA1(38ad2e9f12b9d389fb2568ebcb32c8bd1ac6879e) )
1358	1369	ROM_LOAD16_BYTE( "csd_u17b.u17", 0x00001, 0x2000, CRC(0d9ddce6) SHA1(d955c0e67fc78b517cc229601ab4023cc5a644c2) )
1359	1370	ROM_LOAD16_BYTE( "csd_u8c.u8",   0x04000, 0x2000, CRC(35563cd0) SHA1(5708d374dd56758194c95118f096ea51bf12bf64) )
r14963	r14964
1392	1403	ROM_LOAD( "sh_mb_6.bin",  0x8000, 0x2000, CRC(8cbf04d8) SHA1(e45cb36935367e46ea41de0177b3453cd8bdce85) )
1393	1404	ROM_LOAD( "cpu_pg5.11d",  0xa000, 0x4000, CRC(53a4f7cd) SHA1(051b07ae993e14b329507710c0f7cadaa952f9ae) )
1394	1405
1395		ROM_REGION( 0x10000, "ssiocpu", 0 )
	1406	ROM_REGION( 0x10000, "ssio:cpu", 0 )
1396	1407	ROM_LOAD( "snd_0sd.a8",   0x0000, 0x1000, CRC(c95cf31e) SHA1(d1b0e299a27e306ddbc0654fd3a9d981c92afe8c) )
1397	1408	ROM_LOAD( "snd_1sd.a7",   0x1000, 0x1000, CRC(12aaa48e) SHA1(c6b835fc45e4484a4d52b682ce015caa242c8b4f) )
1398	1409
1399		ROM_REGION( 0x8000, "csdcpu", 0 )  /* 32k for the Chip Squeak Deluxe */
	1410	ROM_REGION( 0x8000, "csd:cpu", 0 )  /* 32k for the Chip Squeak Deluxe */
1400	1411	ROM_LOAD16_BYTE( "csd_u7a.u7",   0x00000, 0x2000, CRC(6e689fe7) SHA1(38ad2e9f12b9d389fb2568ebcb32c8bd1ac6879e) )
1401	1412	ROM_LOAD16_BYTE( "csd_u17b.u17", 0x00001, 0x2000, CRC(0d9ddce6) SHA1(d955c0e67fc78b517cc229601ab4023cc5a644c2) )
1402	1413	ROM_LOAD16_BYTE( "csd_u8c.u8",   0x04000, 0x2000, CRC(35563cd0) SHA1(5708d374dd56758194c95118f096ea51bf12bf64) )
r14963	r14964
1434	1445	ROM_LOAD( "crcpu.9d",     0x6000, 0x2000, CRC(a03c4b11) SHA1(6a442a0828942dc51dbe0d3f19be855a52c12f39) )
1435	1446	ROM_LOAD( "crcpu.10d",    0x8000, 0x2000, CRC(44ae4cbd) SHA1(2188bf697f1b3fcbb2ad6cbd4d9098e3b8d56a95) )
1436	1447
1437		ROM_REGION( 0x10000, "ssiocpu", 0 )
	1448	ROM_REGION( 0x10000, "ssio:cpu", 0 )
1438	1449	ROM_LOAD( "crsnd4.a7",    0x0000, 0x1000, CRC(fd666cb5) SHA1(257174266e264db8ac9af5f2296fd0a22847f85f) )
1439	1450	ROM_LOAD( "crsnd1.a8",    0x1000, 0x1000, CRC(90bf2c4c) SHA1(7adfbf2251b5d46043d614554320e2fe544cc570) )
1440	1451	ROM_LOAD( "crsnd2.a9",    0x2000, 0x1000, CRC(3b8deef1) SHA1(a14186a33a7b5ca07086ce44fb1c8c64900654d0) )
r14963	r14964
1474	1485	ROM_LOAD( "ttprog5.bin",  0xa000, 0x2000, CRC(11e62fe4) SHA1(72897702c61486b654e4b4a3f6560c144c862e1f) )
1475	1486	ROM_RELOAD(               0xc000, 0x2000 )
1476	1487
1477		ROM_REGION( 0x10000, "ssiocpu", ROMREGION_ERASE00 )
	1488	ROM_REGION( 0x10000, "ssio:cpu", ROMREGION_ERASE00 )
1478	1489
1479		ROM_REGION( 0x8000, "csdcpu", 0 )  /* 32k for the Chip Squeak Deluxe */
	1490	ROM_REGION( 0x8000, "csd:cpu", 0 )  /* 32k for the Chip Squeak Deluxe */
1480	1491	ROM_LOAD16_BYTE( "ttu7.bin",  0x00000, 0x2000, CRC(8ebb3302) SHA1(c516abdae6eea524a6d2a039ed9bd7dff72ab986) )
1481	1492	ROM_LOAD16_BYTE( "ttu17.bin", 0x00001, 0x2000, CRC(605d6c74) SHA1(a6c2bc95cca372fa823ab256c9dd1f92b6ba45fd) )
1482	1493	ROM_LOAD16_BYTE( "ttu8.bin",  0x04000, 0x2000, CRC(6bfcb22a) SHA1(7b895e3ae1e99f195bb32b052f801b58c63a401c) )
r14963	r14964
1513	1524	*
1514	1525	*************************************/
1515	1526
1516		static void mcr_common_init(running_machine &machine, int sound_board)
	1527	static void mcr_common_init(running_machine &machine)
1517	1528	{
1518	1529	mcr3_state *state = machine.driver_data<mcr3_state>();
1519		mcr_sound_init(machine, sound_board);
1520	1530
1521	1531	state_save_register_global(machine, state->m_input_mux);
1522	1532	state_save_register_global(machine, state->m_latched_input);
r14963	r14964
1526	1536
1527	1537	static DRIVER_INIT( demoderm )
1528	1538	{
1529		mcr_common_init(machine, MCR_TURBO_CHIP_SQUEAK);
	1539	mcr_common_init(machine);
1530	1540	mcr3_state *state = machine.driver_data<mcr3_state>();
1531	1541	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x01, 0x01, read8_delegate(FUNC(mcr3_state::demoderm_ip1_r),state));
1532	1542	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x02, 0x02, read8_delegate(FUNC(mcr3_state::demoderm_ip2_r),state));
r14963	r14964
1537	1547	static DRIVER_INIT( sarge )
1538	1548	{
1539	1549	mcr3_state *state = machine.driver_data<mcr3_state>();
1540		mcr_common_init(machine, MCR_TURBO_CHIP_SQUEAK);
1541		machine.device("maincpu")->memory().space(AS_IO)->install_write_handler(0x06, 0x06, write8_delegate(FUNC(mcr3_state::turbocs_data_w),state));
	1550	mcr_common_init(machine);
	1551	machine.device("maincpu")->memory().space(AS_IO)->install_write_handler(0x06, 0x06, write8_delegate(FUNC(midway_turbo_chip_squeak_device::write),state->m_turbo_chip_squeak.target()));
1542	1552	}
1543	1553
1544	1554
1545	1555	static DRIVER_INIT( maxrpm )
1546	1556	{
1547	1557	mcr3_state *state = machine.driver_data<mcr3_state>();
1548		mcr_common_init(machine, MCR_TURBO_CHIP_SQUEAK);
	1558	mcr_common_init(machine);
1549	1559	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x01, 0x01, read8_delegate(FUNC(mcr3_state::maxrpm_ip1_r),state));
1550	1560	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x02, 0x02, read8_delegate(FUNC(mcr3_state::maxrpm_ip2_r),state));
1551	1561	machine.device("maincpu")->memory().space(AS_IO)->install_write_handler(0x05, 0x05, write8_delegate(FUNC(mcr3_state::maxrpm_op5_w),state));
r14963	r14964
1562	1572	static DRIVER_INIT( rampage )
1563	1573	{
1564	1574	mcr3_state *state = machine.driver_data<mcr3_state>();
1565		mcr_common_init(machine, MCR_SOUNDS_GOOD);
	1575	mcr_common_init(machine);
1566	1576	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x04, 0x04, read8_delegate(FUNC(mcr3_state::rampage_ip4_r),state));
1567	1577	machine.device("maincpu")->memory().space(AS_IO)->install_write_handler(0x06, 0x06, write8_delegate(FUNC(mcr3_state::rampage_op6_w),state));
1568	1578	}
r14963	r14964
1571	1581	static DRIVER_INIT( powerdrv )
1572	1582	{
1573	1583	mcr3_state *state = machine.driver_data<mcr3_state>();
1574		mcr_common_init(machine, MCR_SOUNDS_GOOD);
	1584	mcr_common_init(machine);
1575	1585	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x02, 0x02, read8_delegate(FUNC(mcr3_state::powerdrv_ip2_r),state));
1576	1586	machine.device("maincpu")->memory().space(AS_IO)->install_write_handler(0x05, 0x05, write8_delegate(FUNC(mcr3_state::powerdrv_op5_w),state));
1577	1587	machine.device("maincpu")->memory().space(AS_IO)->install_write_handler(0x06, 0x06, write8_delegate(FUNC(mcr3_state::powerdrv_op6_w),state));
r14963	r14964
1581	1591	static DRIVER_INIT( stargrds )
1582	1592	{
1583	1593	mcr3_state *state = machine.driver_data<mcr3_state>();
1584		mcr_common_init(machine, MCR_SOUNDS_GOOD);
	1594	mcr_common_init(machine);
1585	1595	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x00, 0x00, read8_delegate(FUNC(mcr3_state::stargrds_ip0_r),state));
1586	1596	machine.device("maincpu")->memory().space(AS_IO)->install_write_handler(0x05, 0x05, write8_delegate(FUNC(mcr3_state::stargrds_op5_w),state));
1587	1597	machine.device("maincpu")->memory().space(AS_IO)->install_write_handler(0x06, 0x06, write8_delegate(FUNC(mcr3_state::stargrds_op6_w),state));
r14963	r14964
1591	1601	static DRIVER_INIT( spyhunt )
1592	1602	{
1593	1603	mcr3_state *state = machine.driver_data<mcr3_state>();
1594		mcr_common_init(machine, MCR_SSIO | MCR_CHIP_SQUEAK_DELUXE);
1595		ssio_set_custom_input(1, 0x60, read8_delegate(FUNC(mcr3_state::spyhunt_ip1_r),state));
1596		ssio_set_custom_input(2, 0xff, read8_delegate(FUNC(mcr3_state::spyhunt_ip2_r),state));
1597		ssio_set_custom_output(4, 0xff, write8_delegate(FUNC(mcr3_state::spyhunt_op4_w),state));
	1604	mcr_common_init(machine);
	1605	machine.device<midway_ssio_device>("ssio")->set_custom_input(1, 0x60, read8_delegate(FUNC(mcr3_state::spyhunt_ip1_r),state));
	1606	machine.device<midway_ssio_device>("ssio")->set_custom_input(2, 0xff, read8_delegate(FUNC(mcr3_state::spyhunt_ip2_r),state));
	1607	machine.device<midway_ssio_device>("ssio")->set_custom_output(4, 0xff, write8_delegate(FUNC(mcr3_state::spyhunt_op4_w),state));
1598	1608
1599	1609	state->m_spyhunt_sprite_color_mask = 0x00;
1600	1610	state->m_spyhunt_scroll_offset = 16;
r14963	r14964
1604	1614	static DRIVER_INIT( crater )
1605	1615	{
1606	1616	mcr3_state *state = machine.driver_data<mcr3_state>();
1607		mcr_common_init(machine, MCR_SSIO);
	1617	mcr_common_init(machine);
1608	1618
1609	1619	state->m_spyhunt_sprite_color_mask = 0x03;
1610	1620	state->m_spyhunt_scroll_offset = 96;
r14963	r14964
1614	1624	static DRIVER_INIT( turbotag )
1615	1625	{
1616	1626	mcr3_state *state = machine.driver_data<mcr3_state>();
1617		mcr_common_init(machine, MCR_SSIO | MCR_CHIP_SQUEAK_DELUXE);
1618		ssio_set_custom_input(1, 0x60, read8_delegate(FUNC(mcr3_state::spyhunt_ip1_r),state));
1619		ssio_set_custom_input(2, 0xff, read8_delegate(FUNC(mcr3_state::turbotag_ip2_r),state));
1620		ssio_set_custom_output(4, 0xff, write8_delegate(FUNC(mcr3_state::spyhunt_op4_w),state));
	1627	mcr_common_init(machine);
	1628	machine.device<midway_ssio_device>("ssio")->set_custom_input(1, 0x60, read8_delegate(FUNC(mcr3_state::spyhunt_ip1_r),state));
	1629	machine.device<midway_ssio_device>("ssio")->set_custom_input(2, 0xff, read8_delegate(FUNC(mcr3_state::turbotag_ip2_r),state));
	1630	machine.device<midway_ssio_device>("ssio")->set_custom_output(4, 0xff, write8_delegate(FUNC(mcr3_state::spyhunt_op4_w),state));
1621	1631
1622	1632	state->m_spyhunt_sprite_color_mask = 0x00;
1623	1633	state->m_spyhunt_scroll_offset = 88;
1624	1634
1625	1635	/* the SSIO Z80 doesn't have any program to execute */
1626		machine.device<cpu_device>("csdcpu")->suspend(SUSPEND_REASON_DISABLE, 1);
	1636	machine.device<cpu_device>("csd:cpu")->suspend(SUSPEND_REASON_DISABLE, 1);
1627	1637
1628	1638	/* kludge for bad ROM read */
1629	1639	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x0b53, 0x0b53, read8_delegate(FUNC(mcr3_state::turbotag_kludge_r),state));

src/mame/drivers/wwfsstar.c

r14963	r14964
414	414
415	415	static const ym2151_interface ym2151_config =
416	416	{
417		wwfsstar_ymirq_handler
	417	DEVCB_LINE(wwfsstar_ymirq_handler)
418	418	};
419	419
420	420	/*******************************************************************************

src/mame/drivers/vaportra.c

r14963	r14964
207	207
208	208	static const ym2151_interface ym2151_config =
209	209	{
210		sound_irq
	210	DEVCB_LINE(sound_irq)
211	211	};
212	212
213	213

src/mame/drivers/nova2001.c

r14963	r14964
203	203	AM_RANGE(0xa003, 0xa003) AM_WRITE(pkunwar_flipscreen_w)
204	204	AM_RANGE(0xc000, 0xc7ff) AM_RAM_WRITE(nova2001_fg_videoram_w) AM_SHARE("fg_videoram")
205	205	AM_RANGE(0xc800, 0xcfff) AM_READWRITE(ninjakun_bg_videoram_r, ninjakun_bg_videoram_w) AM_SHARE("bg_videoram")
206		AM_RANGE(0xd000, 0xd7ff) AM_RAM AM_SHARE("spriteram") AM_SHARE("share3")
	206	AM_RANGE(0xd000, 0xd7ff) AM_RAM AM_SHARE("spriteram")
207	207	AM_RANGE(0xd800, 0xd9ff) AM_RAM_WRITE(ninjakun_paletteram_w) AM_SHARE("paletteram")
208	208	AM_RANGE(0xe000, 0xe3ff) AM_RAM AM_SHARE("share5")
209	209	AM_RANGE(0xe400, 0xe7ff) AM_RAM AM_SHARE("share6")

src/mame/drivers/photon2.c

r14963	r14964
19	19	photon2_state(const machine_config &mconfig, device_type type, const char *tag)
20	20	: driver_device(mconfig, type, tag),
21	21	m_maincpu(*this,"maincpu"),
22		m_spectrum_video_ram(*this, "spectruvideo_ram"){ }
	22	m_spectrum_video_ram(*this, "spectrum_vram"){ }
23	23
24	24	required_device<cpu_device> m_maincpu;
25		optional_shared_ptr<UINT8> m_spectrum_video_ram;
	25	required_shared_ptr<UINT8> m_spectrum_video_ram;
26	26	int m_spectrum_frame_number;
27	27	int m_spectrum_flash_invert;
28	28	UINT8 m_spectrum_port_fe;

src/mame/drivers/igs017.c

r14963	r14964
56	56	: driver_device(mconfig, type, tag),
57	57	m_input_addr(-1),
58	58	m_maincpu(*this, "maincpu"),
59		m_spriteram(*this, "spriteram"),
60		m_fg_videoram(*this, "fg_videoram"),
61		m_bg_videoram(*this, "bg_videoram"){ }
	59	m_spriteram(*this, "spriteram", 0),
	60	m_fg_videoram(*this, "fg_videoram", 0),
	61	m_bg_videoram(*this, "bg_videoram", 0){ }
62	62
63	63	int m_input_addr;
64	64	required_device<cpu_device> m_maincpu;

src/mame/drivers/mjkjidai.c

r14963	r14964
24	24	#include "emu.h"
25	25	#include "cpu/z80/z80.h"
26	26	#include "sound/sn76496.h"
27		#include "sound/okim6295.h"
	27	#include "sound/okiadpcm.h"
28	28	#include "includes/mjkjidai.h"
29	29
30	30	/* Start of ADPCM custom chip code */
31	31	typedef struct _mjkjidai_adpcm_state mjkjidai_adpcm_state;
32	32	struct _mjkjidai_adpcm_state
33	33	{
34		adpcm_state m_adpcm;
	34	oki_adpcm_state m_adpcm;
35	35	sound_stream *m_stream;
36	36	UINT32 m_current;
37	37	UINT32 m_end;

src/mame/drivers/aquarium.c

r14963	r14964
296	296
297	297	static const ym2151_interface ym2151_config =
298	298	{
299		irq_handler
	299	DEVCB_LINE(irq_handler)
300	300	};
301	301
302	302

src/mame/drivers/metro.c

r14963	r14964
532	532
533	533	static const ym2151_interface ym2151_config =
534	534	{
535		metro_sound_irq_handler   /* irq handler */
	535	DEVCB_LINE(metro_sound_irq_handler)   /* irq handler */
536	536	};
537	537
538	538

src/mame/drivers/surpratk.c

r14963	r14964
166	166
167	167	static const ym2151_interface ym2151_config =
168	168	{
169		irqhandler
	169	DEVCB_LINE(irqhandler)
170	170	};
171	171
172	172

src/mame/drivers/atarisy2.c

r14963	r14964
208	208	*
209	209	*************************************/
210	210
211		DIRECT_UPDATE_HANDLER( atarisy2_direct_handler )
	211	DIRECT_UPDATE_MEMBER( atarisy2_state::atarisy2_direct_handler )
212	212	{
213	213	/* make sure slapstic area looks like ROM */
214	214	if (address >= 0x8000 && address < 0x8200)
215	215	{
216		atarisy2_state *state = machine.driver_data<atarisy2_state>();
217		direct.explicit_configure(0x8000, 0x81ff, 0x1ff, reinterpret_cast<UINT8 *>(state->m_slapstic_base.target()));
	216	direct.explicit_configure(0x8000, 0x81ff, 0x1ff, reinterpret_cast<UINT8 *>(m_slapstic_base.target()));
218	217	return ~0;
219	218	}
220	219	return address;
r14963	r14964
246	245	atarigen_scanline_timer_reset(*machine.primary_screen, scanline_update, 64);
247	246
248	247	address_space *main = machine.device<t11_device>("maincpu")->space(AS_PROGRAM);
249		main->set_direct_update_handler(direct_update_delegate(FUNC(atarisy2_direct_handler), &machine));
	248	main->set_direct_update_handler(direct_update_delegate(FUNC(atarisy2_state::atarisy2_direct_handler), state));
250	249
251	250	state->m_p2portwr_state = 0;
252	251	state->m_p2portrd_state = 0;

src/mame/drivers/seta.c

r14963	r14964
10653	10653	RAM[0x1078/2] = 0x4e71;
10654	10654
10655	10655	// fixed priorities?
10656		//TODO:FIX
10657		//state->m_vregs = auto_alloc_array_clear(machine, UINT16, 3);
	10656	seta_state *state = machine.driver_data<seta_state>();
	10657	state->m_vregs.allocate(3);
10658	10658
10659	10659	DRIVER_INIT_CALL(blandia);
10660	10660	}
r14963	r14964
10669	10669	UINT16 *ROM = (UINT16 *)machine.region( "maincpu" )->base();
10670	10670
10671	10671	// missing / unused video regs
10672		//TODO:FIX
10673		//state->m_vregs = auto_alloc_array_clear(machine, UINT16, 3);
	10672	seta_state *state = machine.driver_data<seta_state>();
	10673	state->m_vregs.allocate(3);
10674	10674
10675	10675	// code patches (to be removed...)
10676	10676	ROM[0x4de0/2] = 0x4e71;   // hardware test errors
r14963	r14964
10685	10685	//UINT16 *ROM = (UINT16 *)machine.region( "maincpu" )->base();
10686	10686
10687	10687	// missing / unused video regs
10688		//TODO:FIX
10689		//state->m_vregs = auto_alloc_array_clear(machine, UINT16, 3);
	10688	seta_state *state = machine.driver_data<seta_state>();
	10689	state->m_vregs.allocate(3);
10690	10690
10691	10691	// code patches (to be removed...)
10692	10692	//ROM[0x4de0/2] = 0x4e71;   // hardware test errors

src/mame/drivers/vball.c

r14963	r14964
401	401
402	402	static const ym2151_interface ym2151_config =
403	403	{
404		vball_irq_handler
	404	DEVCB_LINE(vball_irq_handler)
405	405	};
406	406
407	407

src/mame/drivers/namcos1.c

r14963	r14964
1063	1063
1064	1064	static const ym2151_interface ym2151_config =
1065	1065	{
1066		namcos1_sound_interrupt
	1066	DEVCB_LINE(namcos1_sound_interrupt)
1067	1067	};
1068	1068
1069	1069	static const namco_interface namco_config =

src/mame/drivers/renegade.c

r14963	r14964
105	105	#include "cpu/m6809/m6809.h"
106	106	#include "cpu/m6805/m6805.h"
107	107	#include "sound/3526intf.h"
108		#include "sound/okim6295.h"
	108	#include "sound/okiadpcm.h"
109	109	#include "includes/renegade.h"
110	110
111	111
r14963	r14964
114	114	typedef struct _renegade_adpcm_state renegade_adpcm_state;
115	115	struct _renegade_adpcm_state
116	116	{
117		adpcm_state m_adpcm;
	117	oki_adpcm_state m_adpcm;
118	118	sound_stream *m_stream;
119	119	UINT32 m_current;
120	120	UINT32 m_end;

src/mame/drivers/cninja.c

r14963	r14964
731	731
732	732	static const ym2151_interface ym2151_config =
733	733	{
734		sound_irq,
735		sound_bankswitch_w
	734	DEVCB_LINE(sound_irq),
	735	DEVCB_HANDLER(sound_bankswitch_w)
736	736	};
737	737
738	738	static const ym2151_interface ym2151_interface2 =
739	739	{
740		sound_irq2
	740	DEVCB_LINE(sound_irq2)
741	741	};
742	742
743	743	/**********************************************************************************/

src/mame/drivers/missile.c

r14963	r14964
371	371	DECLARE_WRITE8_MEMBER(missile_w);
372	372	DECLARE_READ8_MEMBER(missile_r);
373	373	DECLARE_CUSTOM_INPUT_MEMBER(get_vblank);
	374	DECLARE_DIRECT_UPDATE_MEMBER(missile_direct_handler);
374	375	};
375	376
376	377
r14963	r14964
484	485	}
485	486
486	487
487		DIRECT_UPDATE_HANDLER( missile_direct_handler )
	488	DIRECT_UPDATE_MEMBER(missile_state::missile_direct_handler)
488	489	{
489	490	/* offset accounts for lack of A15 decoding */
490	491	int offset = address & 0x8000;
r14963	r14964
493	494	/* RAM? */
494	495	if (address < 0x4000)
495	496	{
496		missile_state *state = direct.space().machine().driver_data<missile_state>();
497		direct.explicit_configure(0x0000 | offset, 0x3fff | offset, 0x3fff, state->m_videoram);
	497	direct.explicit_configure(0x0000 | offset, 0x3fff | offset, 0x3fff, m_videoram);
498	498	return ~0;
499	499	}
500	500
r14963	r14964
519	519
520	520	/* set up an opcode base handler since we use mapped handlers for RAM */
521	521	address_space *space = machine.device<m6502_device>("maincpu")->space(AS_PROGRAM);
522		space->set_direct_update_handler(direct_update_delegate(FUNC(missile_direct_handler), &machine));
	522	space->set_direct_update_handler(direct_update_delegate(FUNC(missile_state::missile_direct_handler), state));
523	523
524	524	/* create a timer to speed/slow the CPU */
525	525	state->m_cpu_timer = machine.scheduler().timer_alloc(FUNC(adjust_cpu_speed));

src/mame/drivers/vigilant.c

r14963	r14964
463	463
464	464	static const ym2151_interface ym2151_config =
465	465	{
466		m72_ym2151_irq_handler
	466	DEVCB_LINE(m72_ym2151_irq_handler)
467	467	};
468	468
469	469	static const ym2203_interface ym2203_config =

src/mame/drivers/subsino2.c

r14963	r14964
81	81	: driver_device(mconfig, type, tag) ,
82	82	m_outputs16(*this, "outputs16"),
83	83	m_outputs(*this, "outputs"),
84		m_am188em_regs(*this, "am188eregs"){ }
	84	m_am188em_regs(*this, "am188em_regs"){ }
85	85
86	86	UINT8 *m_hm86171_colorram;
87	87	layer_t m_layers[2];
r14963	r14964
94	94	UINT8 m_ss9601_disable;
95	95	int m_hm86171_offs;
96	96	UINT8 m_dsw_mask;
97		required_shared_ptr<UINT16> m_outputs16;
	97	optional_shared_ptr<UINT16> m_outputs16;
98	98	optional_shared_ptr<UINT8> m_outputs;
99		optional_shared_ptr<UINT8> m_am188em_regs;
	99	required_shared_ptr<UINT8> m_am188em_regs;
100	100	UINT16 m_bishjan_sel;
101	101	UINT16 m_bishjan_input;
102	102	DECLARE_WRITE8_MEMBER(ss9601_byte_lo_w);

src/mame/drivers/dassault.c

r14963	r14964
518	518
519	519	static const ym2151_interface ym2151_config =
520	520	{
521		sound_irq,
522		sound_bankswitch_w
	521	DEVCB_LINE(sound_irq),
	522	DEVCB_HANDLER(sound_bankswitch_w)
523	523	};
524	524
525	525	/**********************************************************************************/

src/mame/drivers/tatsumi.c

r14963	r14964
846	846
847	847	static const ym2151_interface ym2151_config =
848	848	{
849		sound_irq
	849	DEVCB_LINE(sound_irq)
850	850	};
851	851
852	852	static INTERRUPT_GEN( roundup5_interrupt )

src/mame/drivers/supbtime.c

r14963	r14964
316	316
317	317	static const ym2151_interface ym2151_config =
318	318	{
319		sound_irq
	319	DEVCB_LINE(sound_irq)
320	320	};
321	321
322	322	static const deco16ic_interface supbtime_deco16ic_tilegen1_intf =

src/mame/drivers/m72.c

r14963	r14964
1825	1825
1826	1826	static const ym2151_interface ym2151_config =
1827	1827	{
1828		m72_ym2151_irq_handler
	1828	DEVCB_LINE(m72_ym2151_irq_handler)
1829	1829	};
1830	1830
1831	1831

src/mame/drivers/topspeed.c

r14963	r14964
621	621
622	622	static const ym2151_interface ym2151_config =
623	623	{
624		irq_handler,
625		sound_bankswitch_w
	624	DEVCB_LINE(irq_handler),
	625	DEVCB_HANDLER(sound_bankswitch_w)
626	626	};
627	627
628	628	static const msm5205_interface msm5205_config =

src/mame/drivers/amspdwy.c

r14963	r14964
246	246
247	247	static const ym2151_interface amspdwy_ym2151_interface =
248	248	{
249		irq_handler
	249	DEVCB_LINE(irq_handler)
250	250	};
251	251
252	252	static MACHINE_START( amspdwy )

src/mame/drivers/fantland.c

r14963	r14964
893	893
894	894	static const ym2151_interface galaxygn_ym2151_interface =
895	895	{
896		galaxygn_sound_irq
	896	DEVCB_LINE(galaxygn_sound_irq)
897	897	};
898	898
899	899	static MACHINE_CONFIG_START( galaxygn, fantland_state )

src/mame/drivers/tumbleb.c

r14963	r14964
2219	2219
2220	2220	static const ym2151_interface semicom_ym2151_interface =
2221	2221	{
2222		semicom_irqhandler
	2222	DEVCB_LINE(semicom_irqhandler)
2223	2223	};
2224	2224
2225	2225	static MACHINE_RESET (htchctch)

src/mame/drivers/m90.c

r14963	r14964
669	669
670	670	static const ym2151_interface ym2151_config =
671	671	{
672		m72_ym2151_irq_handler
	672	DEVCB_LINE(m72_ym2151_irq_handler)
673	673	};
674	674
675	675	/* this bootleg polls the YM2151 instead of taking interrupts from it */
676	676	static const ym2151_interface dynablsb_ym2151_config =
677	677	{
678		NULL
	678	DEVCB_NULL
679	679	};
680	680
681	681	static INTERRUPT_GEN( fake_nmi )

src/mame/drivers/cyberbal.c

r14963	r14964
416	416
417	417	static const ym2151_interface ym2151_config =
418	418	{
419		atarigen_ym2151_irq_gen
	419	DEVCB_LINE(atarigen_ym2151_irq_gen)
420	420	};
421	421
422	422

src/mame/drivers/bfm_sc4h.c

r14963	r14964
229	229
230	230	static WRITE8_HANDLER( bfm_sc4_reel4_w );
231	231
	232	WRITE8_MEMBER(sc4_state::mux_output_w)
	233	{
	234	int i;
	235	int off = offset<<3;
232	236
	237	for (i=0; i<8; i++)
	238	output_set_lamp_value(off+i, ((data & (1 << i)) != 0));
	239
	240
	241	output_set_indexed_value("matrix", off+i, ((data & (1 << i)) != 0));
	242	}
	243
	244	WRITE8_MEMBER(sc4_state::mux_output2_w)
	245	{
	246	int i;
	247	int off = offset<<3;
	248
	249	for (i=0; i<8; i++)
	250	{
	251	output_set_indexed_value("matrix", off+i, ((data & (1 << i)) != 0));
	252	}
	253
	254
	255	if (offset>=20)
	256	{
	257	offset-=20;
	258	// todo, reorder to what our 7segs expect
	259	UINT8 bf7segdata = BITSWAP8(data,7,6,5,4,3,2,1,0);
	260	output_set_digit_value(offset, bf7segdata);
	261
	262	}
	263
	264	}
	265
233	266	WRITE16_MEMBER(sc4_state::sc4_mem_w)
234	267	{
235	268	int pc = cpu_get_pc(&space.device());
r14963	r14964
260	293	else if ((offset>=base2) && (offset<end2))
261	294	{
262	295	offset-=base2;
	296	int addr = (offset<<1);
263	297
264		switch (offset << 1)
	298	if (addr < 0x0200)
265	299	{
266		case 0x0330:
267		logerror("%08x meter write %04x\n",pc, data);
268		//m_meterstatus = (m_meterstatus&0xc0) | (data & 0x3f);
269		sec.write_clock_line(~data&0x20);
270		break;
	300
	301	if (mem_mask&0xff00)
	302	{
	303	logerror("lamp write mem_mask&0xff00 unhandled\n");
	304	}
271	305
272		case 0x1248:
273		ymz280b_w(m_ymz,0, data & 0xff);
274		break;
	306	if (mem_mask&0x00ff)
	307	{   // lamps
	308	mux_output_w(space, (addr & 0x01f0)>>4, data);
	309	}
	310
	311	}
	312	else if ((addr >= 0x1000) && (addr < 0x1200))
	313	{
	314	if (mem_mask&0xff00)
	315	{
	316	logerror("lamp write mem_mask&0xff00 unhandled\n");
	317	}
275	318
276		case 0x124a:
277		ymz280b_w(m_ymz,1, data & 0xff);
278		break;
	319	if (mem_mask&0x00ff)
	320	{   // lamps
	321	mux_output2_w(space, (addr & 0x01f0)>>4, data);
	322	}
	323	}
	324	else
	325	{
	326	switch (addr)
	327	{
	328	case 0x0330:
	329	logerror("%08x meter write %04x\n",pc, data);
	330	//m_meterstatus = (m_meterstatus&0xc0) | (data & 0x3f);
	331	sec.write_clock_line(~data&0x20);
	332	break;
279	333
280		case 0x1330:
281		bfm_sc4_reel4_w(&space,0,data&0xf);
282		//m_meterstatus = (m_meterstatus&0x3f) | ((data & 0x30) << 2);
283		sec.write_data_line(~data&0x10);
284		break;
	334	case 0x1248:
	335	ymz280b_w(m_ymz,0, data & 0xff);
	336	break;
285	337
286		default:
287		logerror("%08x maincpu write access offset %08x data %04x mem_mask %04x cs %d (LAMPS etc.)\n", pc, offset*2, data, mem_mask, cs);
	338	case 0x124a:
	339	ymz280b_w(m_ymz,1, data & 0xff);
	340	break;
	341
	342	case 0x1330:
	343	bfm_sc4_reel4_w(&space,0,data&0xf);
	344	//m_meterstatus = (m_meterstatus&0x3f) | ((data & 0x30) << 2);
	345	sec.write_data_line(~data&0x10);
	346	break;
	347
	348	default:
	349	logerror("%08x maincpu write access offset %08x data %04x mem_mask %04x cs %d (LAMPS etc.)\n", pc, offset*2, data, mem_mask, cs);
	350	}
288	351	}
289	352	}
290	353	else
r14963	r14964
655	718	MCFG_DUART68681_ADD("duart68681", 16000000/4, bfm_sc4_duart68681_config) // ?? Mhz
656	719
657	720
658		MCFG_DEFAULT_LAYOUT(layout_awpvid14)
	721	MCFG_DEFAULT_LAYOUT(layout_bfm_sc4)
659	722
660	723	MCFG_SOUND_ADD("ymz", YMZ280B, 16000000) // ?? Mhz
661	724	MCFG_SOUND_CONFIG(ymz280b_config)

src/mame/drivers/boogwing.c

r14963	r14964
290	290
291	291	static const ym2151_interface ym2151_config =
292	292	{
293		sound_irq,
294		sound_bankswitch_w
	293	DEVCB_LINE(sound_irq),
	294	DEVCB_HANDLER(sound_bankswitch_w)
295	295	};
296	296
297	297

src/mame/drivers/segas16a.c

r14963	r14964
1936	1936
1937	1937	static const ym2151_interface ym2151_config =
1938	1938	{
1939		NULL,
1940		n7751_control_w
	1939	DEVCB_NULL,
	1940	DEVCB_HANDLER(n7751_control_w)
1941	1941	};
1942	1942
1943	1943

src/mame/drivers/segahang.c

r14963	r14964
778	778
779	779	static const ym2151_interface ym2151_config =
780	780	{
781		sound_irq
	781	DEVCB_LINE(sound_irq)
782	782	};
783	783
784	784

src/mame/drivers/gotcha.c

r14963	r14964
13	13	- Unknown sound writes at C00F; also, there's an NMI handler that would
14	14	read from C00F.
15	15	- Sound samples were getting chopped; I fixed this by changing sound/adpcm.c to
16		disregard requests to play new samples until the previous one is finished.
	16	disregard requests to play new samples until the previous one is finished*.
17	17
18	18	Gotcha pcb: 97,7,29 PARA VER 3.0 but it is the same as ppchamp
19	19
r14963	r14964
63	63	#include "sound/2151intf.h"
64	64	#include "sound/okim6295.h"
65	65	#include "includes/gotcha.h"
	66	#include "video/decospr.h"
66	67
67	68
68	69	WRITE16_MEMBER(gotcha_state::gotcha_lamps_w)
r14963	r14964
118	119	static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, gotcha_state )
119	120	AM_RANGE(0x0000, 0x7fff) AM_ROM
120	121	AM_RANGE(0xc000, 0xc001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r, ym2151_w)
121		AM_RANGE(0xc002, 0xc003) AM_DEVWRITE("oki", okim6295_device, write)   // TWO addresses!
	122	AM_RANGE(0xc002, 0xc002) AM_DEVREADWRITE("oki", okim6295_device, read, write) AM_MIRROR(1)
122	123	AM_RANGE(0xc006, 0xc006) AM_READ(soundlatch_byte_r)
123	124	AM_RANGE(0xd000, 0xd7ff) AM_RAM
124	125	ADDRESS_MAP_END
r14963	r14964
244	245
245	246	static const ym2151_interface ym2151_config =
246	247	{
247		irqhandler
	248	DEVCB_LINE(irqhandler)
248	249	};
249	250
250	251
r14963	r14964
300	301
301	302	MCFG_VIDEO_START(gotcha)
302	303
	304	MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
	305	decospr_device::set_gfx_region(*device, 1);
	306	decospr_device::set_is_bootleg(*device, true);
	307	decospr_device::set_offsets(*device, 5,-1); // aligned to 2nd instruction screen in attract
	308
	309
303	310	/* sound hardware */
304	311	MCFG_SPEAKER_STANDARD_MONO("mono")
305	312
r14963	r14964
392	399	ROM_LOAD( "uz11", 0x00000, 0x80000, CRC(3d96274c) SHA1(c7a670af86194c370bf8fb30afbe027ab78a0227) )
393	400	ROM_END
394	401
395		GAME( 1997, gotcha,  0,      gotcha, gotcha, 0, ROT0, "Dongsung", "Got-cha Mini Game Festival", GAME_SUPPORTS_SAVE )
396		GAME( 1997, ppchamp, gotcha, gotcha, gotcha, 0, ROT0, "Dongsung", "Pasha Pasha Champ Mini Game Festival (Korea)", GAME_SUPPORTS_SAVE )
	402	GAME( 1997, gotcha,  0,      gotcha, gotcha, 0, ROT0, "Dongsung / Para", "Got-cha Mini Game Festival", GAME_SUPPORTS_SAVE )
	403	GAME( 1997, ppchamp, gotcha, gotcha, gotcha, 0, ROT0, "Dongsung / Para", "Pasha Pasha Champ Mini Game Festival (Korea)", GAME_SUPPORTS_SAVE )

src/mame/drivers/ddragon.c

r14963	r14964
263	263
264	264	WRITE8_MEMBER(ddragon_state::darktowr_bankswitch_w)
265	265	{
266		int oldbank = machine().memory().bank("bank1");
	266	int oldbank = machine().memory().bank("bank1")->entry();
267	267	int newbank = (data & 0xe0) >> 5;
268	268
269	269	m_scrollx_hi = (data & 0x01);
r14963	r14964
946	946
947	947	static const ym2151_interface ym2151_config =
948	948	{
949		irq_handler
	949	DEVCB_LINE(irq_handler)
950	950	};
951	951
952	952	static const msm5205_interface msm5205_config =

src/mame/drivers/tickee.c

r14963	r14964
38	38	m_control(*this, "control"){ }
39	39
40	40	required_shared_ptr<UINT16> m_vram;
41		required_shared_ptr<UINT16> m_control;
	41	optional_shared_ptr<UINT16> m_control;
42	42	emu_timer *m_setup_gun_timer;
43	43	int m_beamxadd;
44	44	int m_beamyadd;

src/mame/drivers/m92.c

r14963	r14964
881	881
882	882	static const ym2151_interface ym2151_config =
883	883	{
884		sound_irq
	884	DEVCB_LINE(sound_irq)
885	885	};
886	886
887	887	/***************************************************************************/

src/mame/drivers/wwfwfest.c

r14963	r14964
374	374
375	375	static const ym2151_interface ym2151_config =
376	376	{
377		dd3_ymirq_handler
	377	DEVCB_LINE(dd3_ymirq_handler)
378	378	};
379	379
380	380	/*******************************************************************************

src/mame/drivers/vcombat.c

r14963	r14964
116	116	DECLARE_WRITE64_MEMBER(v0_fb_w);
117	117	DECLARE_WRITE64_MEMBER(v1_fb_w);
118	118	DECLARE_WRITE16_MEMBER(crtc_w);
	119	DECLARE_DIRECT_UPDATE_MEMBER(vcombat_vid_0_direct_handler);
	120	DECLARE_DIRECT_UPDATE_MEMBER(vcombat_vid_1_direct_handler);
119	121	};
120	122
121	123	static UINT32 update_screen(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect, int index)
r14963	r14964
413	415	}
414	416
415	417
416		DIRECT_UPDATE_HANDLER( vcombat_vid_0_direct_handler )
	418	DIRECT_UPDATE_MEMBER(vcombat_state::vcombat_vid_0_direct_handler)
417	419	{
418		vcombat_state *state = machine.driver_data<vcombat_state>();
419	420	if (address >= 0xfffc0000 && address <= 0xffffffff)
420	421	{
421		direct.explicit_configure(0xfffc0000, 0xffffffff, 0x3ffff, state->m_vid_0_shared_ram);
	422	direct.explicit_configure(0xfffc0000, 0xffffffff, 0x3ffff, m_vid_0_shared_ram);
422	423	return ~0;
423	424	}
424	425	return address;
425	426	}
426	427
427		DIRECT_UPDATE_HANDLER( vcombat_vid_1_direct_handler )
	428	DIRECT_UPDATE_MEMBER(vcombat_state::vcombat_vid_1_direct_handler)
428	429	{
429		vcombat_state *state = machine.driver_data<vcombat_state>();
430	430	if (address >= 0xfffc0000 && address <= 0xffffffff)
431	431	{
432		direct.explicit_configure(0xfffc0000, 0xffffffff, 0x3ffff, state->m_vid_1_shared_ram);
	432	direct.explicit_configure(0xfffc0000, 0xffffffff, 0x3ffff, m_vid_1_shared_ram);
433	433	return ~0;
434	434	}
435	435	return address;
r14963	r14964
443	443
444	444	/* The two i860s execute out of RAM */
445	445	address_space *space = machine.device<i860_device>("vid_0")->space(AS_PROGRAM);
446		space->set_direct_update_handler(direct_update_delegate(FUNC(vcombat_vid_0_direct_handler), &machine));
	446	space->set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_0_direct_handler), state));
447	447
448	448	space = machine.device<i860_device>("vid_1")->space(AS_PROGRAM);
449		space->set_direct_update_handler(direct_update_delegate(FUNC(vcombat_vid_1_direct_handler), &machine));
	449	space->set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_1_direct_handler), state));
450	450
451	451	/* Allocate the 68000 framebuffers */
452	452	state->m_m68k_framebuffer[0] = auto_alloc_array(machine, UINT16, 0x8000);
r14963	r14964
491	491
492	492	/* The i860 executes out of RAM */
493	493	address_space *space = machine.device<i860_device>("vid_0")->space(AS_PROGRAM);
494		space->set_direct_update_handler(direct_update_delegate(FUNC(vcombat_vid_0_direct_handler), &machine));
	494	space->set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_0_direct_handler), state));
495	495	}
496	496
497	497

src/mame/drivers/mcr.c

r14963	r14964
283	283
284	284
285	285	#include "emu.h"
286		#include "audio/mcr.h"
	286	#include "audio/midway.h"
287	287	#include "sound/samples.h"
288	288	#include "machine/nvram.h"
289	289	#include "includes/mcr.h"
r14963	r14964
302	302
303	303
304	304
	305	WRITE8_MEMBER(mcr_state::mcr_control_port_w)
	306	{
	307	/*
	308	Bit layout is as follows:
	309	D7 = n/c
	310	D6 = cocktail flip
	311	D5 = red LED
	312	D4 = green LED
	313	D3 = n/c
	314	D2 = coin meter 3
	315	D1 = coin meter 2
	316	D0 = coin meter 1
	317	*/
	318
	319	coin_counter_w(machine(), 0, (data >> 0) & 1);
	320	coin_counter_w(machine(), 1, (data >> 1) & 1);
	321	coin_counter_w(machine(), 2, (data >> 2) & 1);
	322	mcr_cocktail_flip = (data >> 6) & 1;
	323	}
	324
	325
305	326	/*************************************
306	327	*
307	328	*  Solar Fox input ports
r14963	r14964
316	337	/* game in cocktail mode, they don't work at all. So we fake-mux   */
317	338	/* the controls through player 1's ports */
318	339	if (mcr_cocktail_flip)
319		return input_port_read(machine(), "SSIO.IP0") | 0x08;
	340	return input_port_read(machine(), "ssio:IP0") | 0x08;
320	341	else
321		return ((input_port_read(machine(), "SSIO.IP0") & ~0x14) | 0x08) | ((input_port_read(machine(), "SSIO.IP0") & 0x08) >> 1) | ((input_port_read(machine(), "SSIO.IP2") & 0x01) << 4);
	342	return ((input_port_read(machine(), "ssio:IP0") & ~0x14) | 0x08) | ((input_port_read(machine(), "ssio:IP0") & 0x08) >> 1) | ((input_port_read(machine(), "ssio:IP2") & 0x01) << 4);
322	343	}
323	344
324	345
r14963	r14964
326	347	{
327	348	/*  same deal as above */
328	349	if (mcr_cocktail_flip)
329		return input_port_read(machine(), "SSIO.IP1") | 0xf0;
	350	return input_port_read(machine(), "ssio:IP1") | 0xf0;
330	351	else
331		return (input_port_read(machine(), "SSIO.IP1") >> 4) | 0xf0;
	352	return (input_port_read(machine(), "ssio:IP1") >> 4) | 0xf0;
332	353	}
333	354
334	355
r14963	r14964
361	382	READ8_MEMBER(mcr_state::wacko_ip1_r)
362	383	{
363	384	if (!input_mux)
364		return input_port_read(machine(), "SSIO.IP1");
	385	return input_port_read(machine(), "ssio:IP1");
365	386	else
366		return input_port_read(machine(), "SSIO.IP1.ALT");
	387	return input_port_read(machine(), "ssio:IP1.ALT");
367	388	}
368	389
369	390
370	391	READ8_MEMBER(mcr_state::wacko_ip2_r)
371	392	{
372	393	if (!input_mux)
373		return input_port_read(machine(), "SSIO.IP2");
	394	return input_port_read(machine(), "ssio:IP2");
374	395	else
375		return input_port_read(machine(), "SSIO.IP2.ALT");
	396	return input_port_read(machine(), "ssio:IP2.ALT");
376	397	}
377	398
378	399
r14963	r14964
512	533
513	534	/* bit 4 = SEL0 (J1-8) on squawk n talk board */
514	535	/* bits 3-0 = MD3-0 connected to squawk n talk (J1-4,3,2,1) */
515		squawkntalk_data_w(space, offset, data);
	536	m_squawk_n_talk->write(space, offset, data);
516	537	}
517	538
518	539
r14963	r14964
595	616
596	617	/* bit 4 = SEL0 (J1-8) on squawk n talk board */
597	618	/* bits 3-0 = MD3-0 connected to squawk n talk (J1-4,3,2,1) */
598		squawkntalk_data_w(space, offset, data);
	619	m_squawk_n_talk->write(space, offset, data);
599	620	}
600	621
601	622
r14963	r14964
608	629
609	630	READ8_MEMBER(mcr_state::demoderb_ip1_r)
610	631	{
611		return input_port_read(machine(), "SSIO.IP1") |
612		(input_port_read(machine(), input_mux ? "SSIO.IP1.ALT2" : "SSIO.IP1.ALT1") << 2);
	632	return input_port_read(machine(), "ssio:IP1") |
	633	(input_port_read(machine(), input_mux ? "ssio:IP1.ALT2" : "ssio:IP1.ALT1") << 2);
613	634	}
614	635
615	636
616	637	READ8_MEMBER(mcr_state::demoderb_ip2_r)
617	638	{
618		return input_port_read(machine(), "SSIO.IP2") |
619		(input_port_read(machine(), input_mux ? "SSIO.IP2.ALT2" : "SSIO.IP2.ALT1") << 2);
	639	return input_port_read(machine(), "ssio:IP2") |
	640	(input_port_read(machine(), input_mux ? "ssio:IP2.ALT2" : "ssio:IP2.ALT1") << 2);
620	641	}
621	642
622	643
r14963	r14964
624	645	{
625	646	if (data & 0x40) input_mux = 1;
626	647	if (data & 0x80) input_mux = 0;
627		turbocs_data_w(space, offset, data);
	648	m_turbo_chip_squeak->write(space, offset, data);
628	649	}
629	650
630	651
r14963	r14964
650	671	static ADDRESS_MAP_START( cpu_90009_portmap, AS_IO, 8, mcr_state )
651	672	ADDRESS_MAP_UNMAP_HIGH
652	673	ADDRESS_MAP_GLOBAL_MASK(0xff)
653		SSIO_INPUT_PORTS
	674	SSIO_INPUT_PORTS("ssio")
654	675	AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
655	676	AM_RANGE(0xe8, 0xe8) AM_WRITENOP
656	677	AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
r14963	r14964
677	698	static ADDRESS_MAP_START( cpu_90010_portmap, AS_IO, 8, mcr_state )
678	699	ADDRESS_MAP_UNMAP_HIGH
679	700	ADDRESS_MAP_GLOBAL_MASK(0xff)
680		SSIO_INPUT_PORTS
	701	SSIO_INPUT_PORTS("ssio")
681	702	AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
682	703	AM_RANGE(0xe8, 0xe8) AM_WRITENOP
683	704	AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
r14963	r14964
705	726	static ADDRESS_MAP_START( cpu_91490_portmap, AS_IO, 8, mcr_state )
706	727	ADDRESS_MAP_UNMAP_HIGH
707	728	ADDRESS_MAP_GLOBAL_MASK(0xff)
708		SSIO_INPUT_PORTS
	729	SSIO_INPUT_PORTS("ssio")
709	730	AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
710	731	AM_RANGE(0xe8, 0xe8) AM_WRITENOP
711	732	AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
r14963	r14964
748	769
749	770	/* verified from wiring diagram, plus DIP switches from manual */
750	771	static INPUT_PORTS_START( solarfox )
751		PORT_START("SSIO.IP0")   /* J4 1-8 */
	772	PORT_START("ssio:IP0")   /* J4 1-8 */
752	773	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
753	774	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
754	775	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 )
r14963	r14964
758	779	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
759	780	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
760	781
761		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	782	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
762	783	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
763	784	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
764	785	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
r14963	r14964
768	789	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_COCKTAIL
769	790	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_COCKTAIL
770	791
771		PORT_START("SSIO.IP2")   /* J5 1-8 */
	792	PORT_START("ssio:IP2")   /* J5 1-8 */
772	793	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
773	794	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNUSED )
774	795
775		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	796	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
776	797	PORT_DIPNAME( 0x03, 0x03, "Bonus" )
777	798	PORT_DIPSETTING(    0x02, DEF_STR( None ) )
778	799	PORT_DIPSETTING(    0x03, "After 10 racks" )
r14963	r14964
789	810	PORT_DIPSETTING(    0x80, DEF_STR( Upright ))
790	811	PORT_DIPSETTING(    0x00, DEF_STR( Cocktail ))
791	812
792		PORT_START("SSIO.IP4")   /* J6 1-8 */
	813	PORT_START("ssio:IP4")   /* J6 1-8 */
793	814	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
794	815
795		PORT_START("SSIO.DIP")
	816	PORT_START("ssio:DIP")
796	817	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
797	818	INPUT_PORTS_END
798	819
799	820
800	821	/* verified from wiring diagram, plus DIP switches from manual */
801	822	static INPUT_PORTS_START( kick )
802		PORT_START("SSIO.IP0")   /* J4 1-8 */
	823	PORT_START("ssio:IP0")   /* J4 1-8 */
803	824	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
804	825	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
805	826	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
809	830	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
810	831	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
811	832
812		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	833	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
813	834	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(3) PORT_KEYDELTA(50) PORT_REVERSE
814	835
815		PORT_START("SSIO.IP2")   /* J5 1-8 */
	836	PORT_START("ssio:IP2")   /* J5 1-8 */
816	837	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
817	838
818		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	839	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
819	840	PORT_DIPNAME( 0x01, 0x00, "Music" )
820	841	PORT_DIPSETTING(    0x01, DEF_STR( Off ))
821	842	PORT_DIPSETTING(    0x00, DEF_STR( On ))
822	843	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN )
823	844
824		PORT_START("SSIO.IP4")   /* J6 1-8 */
	845	PORT_START("ssio:IP4")   /* J6 1-8 */
825	846	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
826	847
827		PORT_START("SSIO.DIP")
	848	PORT_START("ssio:DIP")
828	849	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
829	850
830	851	PORT_START("DIAL2")
r14963	r14964
834	855
835	856	/* verified from wiring diagram, plus DIP switches from manual */
836	857	static INPUT_PORTS_START( kickc )
837		PORT_START("SSIO.IP0")   /* J4 1-8 */
	858	PORT_START("ssio:IP0")   /* J4 1-8 */
838	859	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
839	860	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
840	861	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
844	865	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
845	866	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
846	867
847		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	868	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
848	869	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(3) PORT_KEYDELTA(50) PORT_REVERSE
849	870
850		PORT_START("SSIO.IP2")   /* J5 1-8 */
	871	PORT_START("ssio:IP2")   /* J5 1-8 */
851	872	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
852	873	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNUSED )
853	874
854		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	875	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
855	876	PORT_DIPNAME( 0x01, 0x00, "Music" )
856	877	PORT_DIPSETTING(    0x01, DEF_STR( Off ))
857	878	PORT_DIPSETTING(    0x00, DEF_STR( On ))
r14963	r14964
861	882	PORT_DIPSETTING(    0x40, DEF_STR( Cocktail ))
862	883	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
863	884
864		PORT_START("SSIO.IP4")   /* J6 1-8 */
	885	PORT_START("ssio:IP4")   /* J6 1-8 */
865	886	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
866	887
867		PORT_START("SSIO.DIP")
	888	PORT_START("ssio:DIP")
868	889	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
869	890
870	891	PORT_START("DIAL2")
r14963	r14964
874	895
875	896	/* verified from wiring diagram, plus DIP switches from manual */
876	897	static INPUT_PORTS_START( shollow )
877		PORT_START("SSIO.IP0")   /* J4 1-8 */
	898	PORT_START("ssio:IP0")   /* J4 1-8 */
878	899	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
879	900	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
880	901	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
884	905	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
885	906	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
886	907
887		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	908	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
888	909	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_2WAY
889	910	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_2WAY
890	911	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 )
r14963	r14964
894	915	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
895	916	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
896	917
897		PORT_START("SSIO.IP2")   /* J5 1-8 */
	918	PORT_START("ssio:IP2")   /* J5 1-8 */
898	919	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
899	920
900		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	921	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
901	922	PORT_DIPNAME( 0x01, 0x01, "Coin Meters" )
902	923	PORT_DIPSETTING(    0x01, "1" )
903	924	PORT_DIPSETTING(    0x00, "2" )
r14963	r14964
906	927	PORT_DIPSETTING(    0x02, DEF_STR( Cocktail ) )
907	928	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNKNOWN )
908	929
909		PORT_START("SSIO.IP4")   /* J6 1-8 */
	930	PORT_START("ssio:IP4")   /* J6 1-8 */
910	931	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
911	932
912		PORT_START("SSIO.DIP")
	933	PORT_START("ssio:DIP")
913	934	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
914	935	INPUT_PORTS_END
915	936
916	937
917	938	/* verified from wiring diagram, plus DIP switches from manual */
918	939	static INPUT_PORTS_START( tron )
919		PORT_START("SSIO.IP0")   /* J4 1-8 */
	940	PORT_START("ssio:IP0")   /* J4 1-8 */
920	941	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
921	942	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
922	943	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
926	947	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
927	948	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
928	949
929		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	950	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
930	951	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_CODE_DEC(KEYCODE_Z) PORT_CODE_INC(KEYCODE_X) PORT_REVERSE
931	952
932		PORT_START("SSIO.IP2")   /* J5 1-8 */
	953	PORT_START("ssio:IP2")   /* J5 1-8 */
933	954	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
934	955	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
935	956	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
r14963	r14964
939	960	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
940	961	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
941	962
942		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	963	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
943	964	PORT_DIPNAME( 0x01, 0x00, "Coin Meters" )  PORT_DIPLOCATION("SW1:1")
944	965	PORT_DIPSETTING(    0x01, "1" )
945	966	PORT_DIPSETTING(    0x00, "2" )
r14963	r14964
958	979	// According to the manual, SW1 is a bank of *10* switches (9 is unused and 10 is freeze)
959	980	// Where are the values for the other two bits read?
960	981
961		PORT_START("SSIO.IP4")   /* J6 1-8 */
	982	PORT_START("ssio:IP4")   /* J6 1-8 */
962	983	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_COCKTAIL
963	984
964		PORT_START("SSIO.DIP")
	985	PORT_START("ssio:DIP")
965	986	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
966	987
967	988	INPUT_PORTS_END
968	989
969	990	static INPUT_PORTS_START( tron3 )
970		PORT_START("SSIO.IP0")   /* J4 1-8 */
	991	PORT_START("ssio:IP0")   /* J4 1-8 */
971	992	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
972	993	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
973	994	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
977	998	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
978	999	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
979	1000
980		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1001	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
981	1002	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_CODE_DEC(KEYCODE_Z) PORT_CODE_INC(KEYCODE_X) PORT_REVERSE
982	1003
983		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1004	PORT_START("ssio:IP2")   /* J5 1-8 */
984	1005	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
985	1006	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
986	1007	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
r14963	r14964
990	1011	//  PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
991	1012	//  PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
992	1013
993		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1014	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
994	1015	PORT_DIPNAME( 0x01, 0x00, "Coin Meters" )  PORT_DIPLOCATION("SW1:1")
995	1016	PORT_DIPSETTING(    0x01, "1" )
996	1017	PORT_DIPSETTING(    0x00, "2" )
r14963	r14964
1009	1030	// According to the manual, SW1 is a bank of *10* switches (9 is unused and 10 is freeze)
1010	1031	// Where are the values for the other two bits read?
1011	1032
1012		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1033	PORT_START("ssio:IP4")   /* J6 1-8 */
1013	1034	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1014	1035	//  PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_COCKTAIL
1015	1036
1016		PORT_START("SSIO.DIP")
	1037	PORT_START("ssio:DIP")
1017	1038	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1018	1039
1019	1040	INPUT_PORTS_END
r14963	r14964
1022	1043
1023	1044	/* verified from wiring diagram, plus DIP switches from manual */
1024	1045	static INPUT_PORTS_START( kroozr )
1025		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1046	PORT_START("ssio:IP0")   /* J4 1-8 */
1026	1047	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1027	1048	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1028	1049	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
1032	1053	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1033	1054	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1034	1055
1035		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1056	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1036	1057	PORT_BIT( 0x07, IP_ACTIVE_HIGH, IPT_SPECIAL )   /* low 3 bits of spinner */
1037	1058	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL )   /* sensor J1-10 */
1038	1059	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL )   /* sensor J1-9 */
r14963	r14964
1040	1061	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL )   /* upper 1 bit of spinner */
1041	1062	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 )
1042	1063
1043		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1064	PORT_START("ssio:IP2")   /* J5 1-8 */
1044	1065	PORT_BIT( 0xff, 0x64, IPT_AD_STICK_X ) PORT_MINMAX(48,152) PORT_SENSITIVITY(100) PORT_KEYDELTA(52)
1045	1066
1046		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1067	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1047	1068	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
1048	1069	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Cabinet ) )
1049	1070	PORT_DIPSETTING(    0x00, DEF_STR( Upright ) )
1050	1071	PORT_DIPSETTING(    0x40, DEF_STR( Cocktail ) )
1051	1072	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1052	1073
1053		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1074	PORT_START("ssio:IP4")   /* J6 1-8 */
1054	1075	PORT_BIT( 0xff, 0x64, IPT_AD_STICK_Y ) PORT_MINMAX(48,152) PORT_SENSITIVITY(100) PORT_KEYDELTA(52)
1055	1076
1056		PORT_START("SSIO.DIP")
	1077	PORT_START("ssio:DIP")
1057	1078	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1058	1079
1059	1080	PORT_START("DIAL")
r14963	r14964
1063	1084
1064	1085	/* verified from wiring diagram, plus DIP switches from manual */
1065	1086	static INPUT_PORTS_START( domino )
1066		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1087	PORT_START("ssio:IP0")   /* J4 1-8 */
1067	1088	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1068	1089	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1069	1090	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
1073	1094	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1074	1095	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1075	1096
1076		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1097	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1077	1098	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
1078	1099	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
1079	1100	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY
1080	1101	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
1081	1102	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
1082	1103
1083		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1104	PORT_START("ssio:IP2")   /* J5 1-8 */
1084	1105	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_COCKTAIL
1085	1106	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_COCKTAIL
1086	1107	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_COCKTAIL
r14963	r14964
1088	1109	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1089	1110	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
1090	1111
1091		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1112	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1092	1113	PORT_DIPNAME( 0x01, 0x00, "Music" )
1093	1114	PORT_DIPSETTING(    0x01, DEF_STR( Off ))
1094	1115	PORT_DIPSETTING(    0x00, DEF_STR( On ))
r14963	r14964
1103	1124	PORT_DIPSETTING(    0x80, "1" )
1104	1125	PORT_DIPSETTING(    0x00, "2" )
1105	1126
1106		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1127	PORT_START("ssio:IP4")   /* J6 1-8 */
1107	1128	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1108	1129
1109		PORT_START("SSIO.DIP")
	1130	PORT_START("ssio:DIP")
1110	1131	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1111	1132	INPUT_PORTS_END
1112	1133
1113	1134
1114	1135	/* verified from wiring diagram, plus DIP switches from manual */
1115	1136	static INPUT_PORTS_START( journey )
1116		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1137	PORT_START("ssio:IP0")   /* J4 1-8 */
1117	1138	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1118	1139	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1119	1140	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
1123	1144	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1124	1145	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1125	1146
1126		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1147	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1127	1148	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
1128	1149	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
1129	1150	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY
1130	1151	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
1131	1152	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
1132	1153
1133		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1154	PORT_START("ssio:IP2")   /* J5 1-8 */
1134	1155	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_COCKTAIL
1135	1156	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_COCKTAIL
1136	1157	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_COCKTAIL
r14963	r14964
1138	1159	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1139	1160	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
1140	1161
1141		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1162	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1142	1163	PORT_DIPNAME( 0x01, 0x01, "Coin Meters" )
1143	1164	PORT_DIPSETTING(    0x01, "1" )
1144	1165	PORT_DIPSETTING(    0x00, "2" )
r14963	r14964
1147	1168	PORT_DIPSETTING(    0x02, DEF_STR( Cocktail ) )
1148	1169	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
1149	1170
1150		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1171	PORT_START("ssio:IP4")   /* J6 1-8 */
1151	1172	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1152	1173
1153		PORT_START("SSIO.DIP")
	1174	PORT_START("ssio:DIP")
1154	1175	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1155	1176	INPUT_PORTS_END
1156	1177
1157	1178
1158	1179	/* verified from wiring diagram, plus DIP switches from manual */
1159	1180	static INPUT_PORTS_START( wacko )
1160		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1181	PORT_START("ssio:IP0")   /* J4 1-8 */
1161	1182	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1162	1183	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1163	1184	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
1167	1188	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1168	1189	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1169	1190
1170		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1191	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1171	1192	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10)
1172	1193
1173		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1194	PORT_START("ssio:IP2")   /* J5 1-8 */
1174	1195	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE
1175	1196
1176		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1197	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1177	1198	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNUSED )
1178	1199	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Cabinet ) )
1179	1200	PORT_DIPSETTING(    0x00, DEF_STR( Upright ) )
r14963	r14964
1182	1203	PORT_DIPSETTING(    0x80, "1" )
1183	1204	PORT_DIPSETTING(    0x00, "2" )
1184	1205
1185		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1206	PORT_START("ssio:IP4")   /* J6 1-8 */
1186	1207	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_RIGHT ) PORT_4WAY
1187	1208	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_LEFT ) PORT_4WAY
1188	1209	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) PORT_4WAY
r14963	r14964
1192	1213	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN ) PORT_4WAY PORT_COCKTAIL
1193	1214	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_UP ) PORT_4WAY PORT_COCKTAIL
1194	1215
1195		PORT_START("SSIO.DIP")
	1216	PORT_START("ssio:DIP")
1196	1217	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1197	1218
1198		PORT_START("SSIO.IP1.ALT")
	1219	PORT_START("ssio:IP1.ALT")
1199	1220	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_COCKTAIL
1200	1221
1201		PORT_START("SSIO.IP2.ALT")
	1222	PORT_START("ssio:IP2.ALT")
1202	1223	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_COCKTAIL
1203	1224	INPUT_PORTS_END
1204	1225
1205	1226
1206	1227	/* not verified, no manual found */
1207	1228	static INPUT_PORTS_START( twotiger )
1208		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1229	PORT_START("ssio:IP0")   /* J4 1-8 */
1209	1230	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1210	1231	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1211	1232	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
r14963	r14964
1215	1236	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1216	1237	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1217	1238
1218		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1239	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1219	1240	PORT_BIT( 0xff, 0x67, IPT_AD_STICK_X ) PORT_MINMAX(0, 206) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
1220	1241
1221		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1242	PORT_START("ssio:IP2")   /* J5 1-8 */
1222	1243	PORT_BIT( 0xff, 0x67, IPT_AD_STICK_X ) PORT_MINMAX(0, 206) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
1223	1244
1224		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1245	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1225	1246	PORT_DIPNAME( 0x01, 0x00, "Shot Speed" )
1226	1247	PORT_DIPSETTING(    0x01, "Fast" )
1227	1248	PORT_DIPSETTING(    0x00, "Slow" )
r14963	r14964
1230	1251	PORT_DIPSETTING(    0x02, "2 Credits" )
1231	1252	PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
1232	1253
1233		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1254	PORT_START("ssio:IP4")   /* J6 1-8 */
1234	1255	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 )
1235	1256	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
1236	1257	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 )
r14963	r14964
1239	1260	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
1240	1261	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
1241	1262
1242		PORT_START("SSIO.DIP")
	1263	PORT_START("ssio:DIP")
1243	1264	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1244	1265	INPUT_PORTS_END
1245	1266
1246	1267
1247	1268	/* not verified, no manual found */
1248	1269	static INPUT_PORTS_START( twotigrc )
1249		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1270	PORT_START("ssio:IP0")   /* J4 1-8 */
1250	1271	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1251	1272	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1252	1273	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
1256	1277	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1257	1278	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1258	1279
1259		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1280	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1260	1281	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(10) PORT_KEYDELTA(10) PORT_REVERSE
1261	1282
1262		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1283	PORT_START("ssio:IP2")   /* J5 1-8 */
1263	1284	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
1264	1285	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
1265	1286	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
1266	1287	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
1267	1288	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
1268	1289
1269		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1290	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1270	1291	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1271	1292
1272		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1293	PORT_START("ssio:IP4")   /* J6 1-8 */
1273	1294	PORT_BIT( 0xff, 0x00, IPT_DIAL ) PORT_SENSITIVITY(10) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(2)
1274	1295
1275		PORT_START("SSIO.DIP")
	1296	PORT_START("ssio:DIP")
1276	1297	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1277	1298	INPUT_PORTS_END
1278	1299
1279	1300
1280	1301	/* verified from wiring diagram, plus DIP switches from manual */
1281	1302	static INPUT_PORTS_START( tapper )
1282		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1303	PORT_START("ssio:IP0")   /* J4 1-8 */
1283	1304	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1284	1305	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1285	1306	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
1289	1310	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1290	1311	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1291	1312
1292		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1313	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1293	1314	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
1294	1315	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
1295	1316	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
r14963	r14964
1297	1318	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
1298	1319	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
1299	1320
1300		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1321	PORT_START("ssio:IP2")   /* J5 1-8 */
1301	1322	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_COCKTAIL
1302	1323	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_COCKTAIL
1303	1324	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_COCKTAIL
r14963	r14964
1305	1326	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1306	1327	PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
1307	1328
1308		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1329	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1309	1330	PORT_BIT( 0x03, IP_ACTIVE_LOW, IPT_UNUSED )
1310	1331	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Demo_Sounds ) )
1311	1332	PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
r14963	r14964
1318	1339	PORT_DIPSETTING(    0x80, "1" )
1319	1340	PORT_DIPSETTING(    0x00, "2" )
1320	1341
1321		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1342	PORT_START("ssio:IP4")   /* J6 1-8 */
1322	1343	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1323	1344
1324		PORT_START("SSIO.DIP")
	1345	PORT_START("ssio:DIP")
1325	1346	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1326	1347	INPUT_PORTS_END
1327	1348
1328	1349
1329	1350	/* not verified, no manual found */
1330	1351	static INPUT_PORTS_START( timber )
1331		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1352	PORT_START("ssio:IP0")   /* J4 1-8 */
1332	1353	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1333	1354	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1334	1355	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
1338	1359	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1339	1360	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1340	1361
1341		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1362	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1342	1363	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(1)
1343	1364	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(1)
1344	1365	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(1)
r14963	r14964
1347	1368	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
1348	1369	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
1349	1370
1350		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1371	PORT_START("ssio:IP2")   /* J5 1-8 */
1351	1372	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(2)
1352	1373	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(2)
1353	1374	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(2)
r14963	r14964
1356	1377	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
1357	1378	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
1358	1379
1359		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1380	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1360	1381	PORT_BIT( 0x03, IP_ACTIVE_LOW, IPT_UNUSED )
1361	1382	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Demo_Sounds ) )
1362	1383	PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
r14963	r14964
1369	1390	PORT_DIPSETTING(    0x80, "1" )
1370	1391	PORT_DIPSETTING(    0x00, "2" )
1371	1392
1372		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1393	PORT_START("ssio:IP4")   /* J6 1-8 */
1373	1394	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1374	1395
1375		PORT_START("SSIO.DIP")
	1396	PORT_START("ssio:DIP")
1376	1397	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1377	1398	INPUT_PORTS_END
1378	1399
1379	1400
1380	1401	/* verified from wiring diagram, plus DIP switches from manual */
1381	1402	static INPUT_PORTS_START( dotron )
1382		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1403	PORT_START("ssio:IP0")   /* J4 1-8 */
1383	1404	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1384	1405	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1385	1406	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
1389	1410	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1390	1411	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1391	1412
1392		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1413	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1393	1414	PORT_BIT( 0x7f, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_CODE_DEC(KEYCODE_Z) PORT_CODE_INC(KEYCODE_X) PORT_REVERSE
1394	1415	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
1395	1416
1396		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1417	PORT_START("ssio:IP2")   /* J5 1-8 */
1397	1418	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
1398	1419	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
1399	1420	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
r14963	r14964
1405	1426	PORT_DIPSETTING(    0x00, "Environmental" )
1406	1427	PORT_DIPSETTING(    0x80, DEF_STR( Upright ) )
1407	1428
1408		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1429	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1409	1430	PORT_DIPNAME( 0x01, 0x01, "Coin Meters" )
1410	1431	PORT_DIPSETTING(    0x01, "1" )
1411	1432	PORT_DIPSETTING(    0x00, "2" )
1412	1433	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNUSED )
1413	1434
1414		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1435	PORT_START("ssio:IP4")   /* J6 1-8 */
1415	1436	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1416	1437
1417		PORT_START("SSIO.DIP")
	1438	PORT_START("ssio:DIP")
1418	1439	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1419	1440
1420	1441	PORT_START("FAKE")   /* fake port to make aiming up & down easier */
r14963	r14964
1424	1445	static INPUT_PORTS_START( dotrone )
1425	1446	PORT_INCLUDE(dotron)
1426	1447
1427		PORT_MODIFY("SSIO.IP2")
	1448	PORT_MODIFY("ssio:IP2")
1428	1449	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Cabinet ) )
1429	1450	PORT_DIPSETTING(    0x00, "Environmental" )
1430	1451	PORT_DIPSETTING(    0x80, DEF_STR( Upright ) )
r14963	r14964
1433	1454
1434	1455	/* verified from wiring diagram, plus DIP switches from manual */
1435	1456	static INPUT_PORTS_START( nflfoot )
1436		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1457	PORT_START("ssio:IP0")   /* J4 1-8 */
1437	1458	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1438	1459	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BILL1 )
1439	1460	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )      /* continue game */
r14963	r14964
1443	1464	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1444	1465	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1445	1466
1446		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */
	1467	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */
1447	1468	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)    /* left engage */
1448	1469	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)    /* left select #1 play */
1449	1470	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)    /* left select #2 play */
r14963	r14964
1453	1474	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON7 ) PORT_PLAYER(1)      /* select one player */
1454	1475	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1455	1476
1456		PORT_START("SSIO.IP2")   /* J5 1-8 */
	1477	PORT_START("ssio:IP2")   /* J5 1-8 */
1457	1478	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)    /* right engage */
1458	1479	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)    /* right select #1 play */
1459	1480	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)    /* right select #2 play */
r14963	r14964
1463	1484	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON7 ) PORT_PLAYER(2)      /* select two player */
1464	1485	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL )               /* connects to IPU board */
1465	1486
1466		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1487	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1467	1488	PORT_DIPNAME( 0x01, 0x01, "Coin Meters" )
1468	1489	PORT_DIPSETTING(    0x01, "1" )
1469	1490	PORT_DIPSETTING(    0x00, "2" )
1470	1491	PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNUSED )
1471	1492
1472		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1493	PORT_START("ssio:IP4")   /* J6 1-8 */
1473	1494	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
1474	1495
1475		PORT_START("SSIO.DIP")
	1496	PORT_START("ssio:DIP")
1476	1497	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1477	1498	INPUT_PORTS_END
1478	1499
r14963	r14964
1480	1501	/* "wiring diagram was not available at time of publication" according to the manual */
1481	1502	/* DIPs verified from the manual */
1482	1503	static INPUT_PORTS_START( demoderb )
1483		PORT_START("SSIO.IP0")   /* J4 1-8 */
	1504	PORT_START("ssio:IP0")   /* J4 1-8 */
1484	1505	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
1485	1506	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1486	1507	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r14963	r14964
1490	1511	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_TILT )
1491	1512	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
1492	1513
1493		PORT_START("SSIO.IP1")   /* J4 10-13,15-18 */   /* The high 6 bits contain the steering wheel value */
	1514	PORT_START("ssio:IP1")   /* J4 10-13,15-18 */   /* The high 6 bits contain the steering wheel value */
1494	1515	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
1495	1516	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
1496	1517
1497		PORT_START("SSIO.IP1.ALT1")   /* J4 10-13,15-18 */   /* The high 6 bits contain the steering wheel value */
	1518	PORT_START("ssio:IP1.ALT1")   /* J4 10-13,15-18 */   /* The high 6 bits contain the steering wheel value */
1498	1519	PORT_BIT( 0x3f, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(1)
1499	1520
1500		PORT_START("SSIO.IP1.ALT2")   /* IN1 (muxed) -- the high 6 bits contain the steering wheel value */
	1521	PORT_START("ssio:IP1.ALT2")   /* IN1 (muxed) -- the high 6 bits contain the steering wheel value */
1501	1522	PORT_BIT( 0x3f, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(3)
1502	1523
1503		PORT_START("SSIO.IP2")   /* J5 1-8 */   /* The high 6 bits contain the steering wheel value */
	1524	PORT_START("ssio:IP2")   /* J5 1-8 */   /* The high 6 bits contain the steering wheel value */
1504	1525	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
1505	1526	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
1506	1527
1507		PORT_START("SSIO.IP2.ALT1")   /* J5 1-8 */   /* The high 6 bits contain the steering wheel value */
	1528	PORT_START("ssio:IP2.ALT1")   /* J5 1-8 */   /* The high 6 bits contain the steering wheel value */
1508	1529	PORT_BIT( 0x3f, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(2)
1509	1530
1510		PORT_START("SSIO.IP2.ALT2")   /* IN2 (muxed) -- the high 6 bits contain the steering wheel value */
	1531	PORT_START("ssio:IP2.ALT2")   /* IN2 (muxed) -- the high 6 bits contain the steering wheel value */
1511	1532	PORT_BIT( 0x3f, 0x00, IPT_DIAL ) PORT_SENSITIVITY(50) PORT_KEYDELTA(10) PORT_REVERSE PORT_PLAYER(4)
1512	1533
1513		PORT_START("SSIO.IP3")   /* DIPSW @ B3 */
	1534	PORT_START("ssio:IP3")   /* DIPSW @ B3 */
1514	1535	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Cabinet ) )
1515	1536	PORT_DIPSETTING(    0x01, "2P Upright" )
1516	1537	PORT_DIPSETTING(    0x00, "4P Cocktail" )
r14963	r14964
1530	1551	PORT_DIPSETTING(    0x10, DEF_STR( 1C_2C ) )
1531	1552	PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNKNOWN )
1532	1553
1533		PORT_START("SSIO.IP4")   /* J6 1-8 */
	1554	PORT_START("ssio:IP4")   /* J6 1-8 */
1534	1555	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
1535	1556	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN4 )
1536	1557	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 )
r14963	r14964
1540	1561	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
1541	1562	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
1542	1563
1543		PORT_START("SSIO.DIP")
	1564	PORT_START("ssio:DIP")
1544	1565	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1545	1566
1546	1567	INPUT_PORTS_END
r14963	r14964
1635	1656	MCFG_VIDEO_START(mcr)
1636	1657
1637	1658	/* sound hardware */
1638		MCFG_FRAGMENT_ADD(mcr_ssio)
	1659	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
	1660	MCFG_MIDWAY_SSIO_ADD("ssio")
	1661	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
	1662	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
1639	1663	MACHINE_CONFIG_END
1640	1664
1641	1665
r14963	r14964
1693	1717	static MACHINE_CONFIG_DERIVED( mcr_91490_snt, mcr_91490 )
1694	1718
1695	1719	/* basic machine hardware */
1696		MCFG_FRAGMENT_ADD(squawk_n_talk)
	1720	MCFG_MIDWAY_SQUAWK_N_TALK_ADD("snt")
	1721	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
	1722	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
1697	1723	MACHINE_CONFIG_END
1698	1724
1699	1725
r14963	r14964
1721	1747	static MACHINE_CONFIG_DERIVED( mcr_91490_tcs, mcr_91490 )
1722	1748
1723	1749	/* basic machine hardware */
1724		MCFG_FRAGMENT_ADD(turbo_chip_squeak)
	1750	MCFG_MIDWAY_TURBO_CHIP_SQUEAK_ADD("tcs")
	1751	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
	1752	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
1725	1753	MACHINE_CONFIG_END
1726	1754
1727	1755
r14963	r14964
1742	1770	ROM_LOAD( "sfcpu.6d",     0x5000, 0x1000, CRC(bd993cd9) SHA1(c074a6a40d0b9c0f4bf3fc5982263c89549fb338) )
1743	1771	ROM_LOAD( "sfcpu.7d",     0x6000, 0x1000, CRC(8ad8731d) SHA1(ffd19c3fbad3c5a240ab27963812cc300f3d7b89) )
1744	1772
1745		ROM_REGION( 0x10000, "ssiocpu", 0 )
	1773	ROM_REGION( 0x10000, "ssio:cpu", 0 )
1746	1774	ROM_LOAD( "sfsnd.7a",     0x0000, 0x1000, CRC(cdecf83a) SHA1(5acd2709e214408d756b39916bb98cd4ecda7988) )
1747	1775	ROM_LOAD( "sfsnd.8a",     0x1000, 0x1000, CRC(cb7788cb) SHA1(9e86f9131a6f0fc96dd436e21baf45e215ee65f4) )
1748	1776	ROM_LOAD( "sfsnd.9a",     0x2000, 0x1000, CRC(304896ce) SHA1(00ff640eab50022da980cdc5ce8cedebaaebc9cf) )
r14963	r14964
1771	1799	ROM_LOAD( "1600e-v2.d5",  0x4000, 0x1000, CRC(1d2834c0) SHA1(176fad90ab14c922a575c3d12a2c8a339d1518d4) )
1772	1800	ROM_LOAD( "1700f-v2.d6",  0x5000, 0x1000, CRC(ddf84ce1) SHA1(6f80b9a5cbd75b6e4af569ca4bcfcde7daaad64f) )
1773	1801
1774		ROM_REGION( 0x10000, "ssiocpu", 0 )
	1802	ROM_REGION( 0x10000, "ssio:cpu", 0 )
1775	1803	ROM_LOAD( "4200-a.a7",    0x0000, 0x1000, CRC(9e35c02e) SHA1(92afd0126dcfb2d4401927b2cf261090e186b6fa) )
1776	1804	ROM_LOAD( "4300-b.a8",    0x1000, 0x1000, CRC(ca2b7c28) SHA1(fdcca3b755822c045c3c321cccc3f58112e2ad11) )
1777	1805	ROM_LOAD( "4400-c.a9",    0x2000, 0x1000, CRC(d1901551) SHA1(fd7d6059f8ac59f95ae6f8ef12fbfce7ed16ec12) )
r14963	r14964
1800	1828	ROM_LOAD( "1600-e-ur.d5",  0x4000, 0x1000, CRC(f24bc0d7) SHA1(31dc996898c01f3427403e396a47444732904674) )
1801	1829	ROM_LOAD( "1700-f-ur.d6",  0x5000, 0x1000, CRC(672361fc) SHA1(010029460c25935f2156eb64c9109c26ce40b752) )
1802	1830
1803		ROM_REGION( 0x10000, "ssiocpu", 0 )
	1831	ROM_REGION( 0x10000, "ssio:cpu", 0 )
1804	1832	ROM_LOAD( "4200-a.a7",    0x0000, 0x1000, CRC(9e35c02e) SHA1(92afd0126dcfb2d4401927b2cf261090e186b6fa) )
1805	1833	ROM_LOAD( "4300-b.a8",    0x1000, 0x1000, CRC(ca2b7c28) SHA1(fdcca3b755822c045c3c321cccc3f58112e2ad11) )
1806	1834	ROM_LOAD( "4400-c.a9",    0x2000, 0x1000, CRC(d1901551) SHA1(fd7d6059f8ac59f95ae6f8ef12fbfce7ed16ec12) )
r14963	r14964
1829	1857	ROM_LOAD( "1600-e.d5",    0x4000, 0x1000, CRC(eaaa78a7) SHA1(3c057d486f3938561fb9947e0463b1255ae04ef9) )
1830	1858	ROM_LOAD( "1700-f.d6",    0x5000, 0x1000, CRC(c06c880f) SHA1(d5ac5682de316b9cb09d433e2c02746efadd2a81) )
1831	1859
1832		ROM_REGION( 0x10000, "ssiocpu", 0 )
	1860	ROM_REGION( 0x10000, "ssio:cpu", 0 )
1833	1861	ROM_LOAD( "4200-a.a7",    0x0000, 0x1000, CRC(9e35c02e) SHA1(92afd0126dcfb2d4401927b2cf261090e186b6fa) )
1834	1862	ROM_LOAD( "4300-b.a8",    0x1000, 0x1000, CRC(ca2b7c28) SHA1(fdcca3b755822c045c3c321cccc3f58112e2ad11) )
1835	1863	ROM_LOAD( "4400-c.a9",    0x2000, 0x1000, CRC(d1901551) SHA1(fd7d6059f8ac59f95ae6f8ef12fbfce7ed16ec12) )
r14963	r14964
1859	1887	ROM_LOAD( "sh-pro.04",    0x8000, 0x2000, CRC(22fa9175) SHA1(fd8ea76b3a7ffaf48fc11dd3b7c58e548e3e57c5) )
1860	1888	ROM_LOAD( "sh-pro.05",    0xa000, 0x2000, CRC(1716e2bb) SHA1(771e4c20d63e4e1d99723e6355db67064a278ae5) )
1861	1889
1862		ROM_REGION( 0x10000, "ssiocpu", 0 )
	1890	ROM_REGION( 0x10000, "ssio:cpu", 0 )
1863	1891	ROM_LOAD( "sh-snd.01",    0x0000, 0x1000, CRC(55a297cc) SHA1(b34f37fca61cdba26b5671feee991d133b8697a4) )
1864	1892	ROM_LOAD( "sh-snd.02",    0x1000, 0x1000, CRC(46fc31f6) SHA1(9b1a56962b2d210b1013bc35de780c6d5b3eb4bc) )
1865	1893	ROM_LOAD( "sh-snd.03",    0x2000, 0x1000, CRC(b1f4a6a8) SHA1(ba724f9cc0cc35dd31d4ad8b36a51da9d6cbfbcf) )
r14963	r14964
1887	1915	ROM_LOAD( "sh-pro.04",    0x8000, 0x2000, CRC(22fa9175) SHA1(fd8ea76b3a7ffaf48fc11dd3b7c58e548e3e57c5) )
1888	1916	ROM_LOAD( "sh-pro.05",    0xa000, 0x2000, CRC(1716e2bb) SHA1(771e4c20d63e4e1d99723e6355db67064a278ae5) )
1889	1917
1890		ROM_REGION( 0x10000, "ssiocpu", 0 )
	1918	ROM_REGION( 0x10000, "ssio:cpu", 0 )
1891	1919	ROM_LOAD( "snd-0.a7",     0x0000, 0x1000, CRC(9d815bb3) SHA1(51af797e08dbe3921e11ce70c3d0da50979336a4) )
1892	1920	ROM_LOAD( "snd-1.a8",     0x1000, 0x1000, CRC(9f253412) SHA1(a526e864073a2f9e67e2cbe53ab17fe726336241) )
1893	1921	ROM_LOAD( "snd-2.a9",     0x2000, 0x1000, CRC(7783d6c6) SHA1(1fb2117532e7da28afdb9837bcb6848165cf8173) )
r14963	r14964
1919	1947	ROM_LOAD( "scpu_pge.d6", 0x8000, 0x2000, CRC(24c185d8) SHA1(45ac7c53f6f4eba5c7bf3fc6559cddd3821eddad) )
1920	1948	ROM_LOAD( "scpu_pgf.d7", 0xA000, 0x2000, CRC(38c4bbaf) SHA1(a7cd496ce75199b8279ea963520cf70d5f562bb2) )
1921	1949
1922		ROM_REGION( 0x10000, "ssiocpu", 0 ) /* ROM's located on the Super Sound I/O Board (90913) */
	1950	ROM_REGION( 0x10000, "ssio:cpu", 0 ) /* ROM's located on the Super Sound I/O Board (90913) */
1923	1951	ROM_LOAD( "ssi_0a.a7",   0x0000, 0x1000, CRC(765e6eba) SHA1(42efeefc8571dfc237c0be3368248f1e56add92e) )
1924	1952	ROM_LOAD( "ssi_0b.a8",   0x1000, 0x1000, CRC(1b90ccdd) SHA1(0876e5eeaa63bb8cc97f3634a6ddd8a29a9b012f) )
1925	1953	ROM_LOAD( "ssi_0c.a9",   0x2000, 0x1000, CRC(3a4bc629) SHA1(ce8452a99a313ae7429de471bbea39de08c9fd4b) )
r14963	r14964
1958	1986	ROM_LOAD( "scpu_pge.d6", 0x8000, 0x2000, CRC(24c185d8) SHA1(45ac7c53f6f4eba5c7bf3fc6559cddd3821eddad) )
1959	1987	ROM_LOAD( "scpu_pgf.d7", 0xa000, 0x2000, CRC(38c4bbaf) SHA1(a7cd496ce75199b8279ea963520cf70d5f562bb2) )
1960	1988
1961		ROM_REGION( 0x10000, "ssiocpu", 0 ) /* ROM's located on the Super Sound I/O Board (90913) */
	1989	ROM_REGION( 0x10000, "ssio:cpu", 0 ) /* ROM's located on the Super Sound I/O Board (90913) */
1962	1990	ROM_LOAD( "ssi_0a.a7",   0x0000, 0x1000, CRC(765e6eba) SHA1(42efeefc8571dfc237c0be3368248f1e56add92e) )
1963	1991	ROM_LOAD( "ssi_0b.a8",   0x1000, 0x1000, CRC(1b90ccdd) SHA1(0876e5eeaa63bb8cc97f3634a6ddd8a29a9b012f) )
1964	1992	ROM_LOAD( "ssi_0c.a9",   0x2000, 0x1000, CRC(3a4bc629) SHA1(ce8452a99a313ae7429de471bbea39de08c9fd4b) )
r14963	r14964
1997	2025	ROM_LOAD( "scpu_pge(__0617).d6", 0x8000, 0x2000, CRC(ea198fa8) SHA1(d8c97ea87d504e77edc38c87c2953c8c4f1a405b) )
1998	2026	ROM_LOAD( "scpu_pgf(__0617).d7", 0xa000, 0x2000, CRC(4325fb08) SHA1(70727aa37354425315d8a8b3ca07bbe91f7e8f08) )
1999	2027
2000		ROM_REGION( 0x10000, "ssiocpu", 0 ) /* ROM's located on the Super Sound I/O Board (90913) */
	2028	ROM_REGION( 0x10000, "ssio:cpu", 0 ) /* ROM's located on the Super Sound I/O Board (90913) */
2001	2029	ROM_LOAD( "ssi_0a.a7",   0x0000, 0x1000, CRC(765e6eba) SHA1(42efeefc8571dfc237c0be3368248f1e56add92e) )
2002	2030	ROM_LOAD( "ssi_0b.a8",   0x1000, 0x1000, CRC(1b90ccdd) SHA1(0876e5eeaa63bb8cc97f3634a6ddd8a29a9b012f) )
2003	2031	ROM_LOAD( "ssi_0c.a9",   0x2000, 0x1000, CRC(3a4bc629) SHA1(ce8452a99a313ae7429de471bbea39de08c9fd4b) )
r14963	r14964
2036	2064	ROM_LOAD( "pge-615.d6",   0x8000, 0x2000, CRC(ea198fa8) SHA1(d8c97ea87d504e77edc38c87c2953c8c4f1a405b) )
2037	2065	ROM_LOAD( "pgf-615.d7",   0xa000, 0x2000, CRC(790ee743) SHA1(14dc84b2bbaab22772e0579f11fe0bf136a0ddab) )
2038	2066
2039		ROM_REGION( 0x10000, "ssiocpu", 0 ) /* ROM's located on the Super Sound I/O Board (90913) */
	2067	ROM_REGION( 0x10000, "ssio:cpu", 0 ) /* ROM's located on the Super Sound I/O Board (90913) */
2040	2068	ROM_LOAD( "ssi_oa.a7",    0x0000, 0x1000, CRC(2cbb332b) SHA1(48d1cbb336733588af728a3d0e02c8613d2b5fb2) )
2041	2069	ROM_LOAD( "ssi_ob.a8",    0x1000, 0x1000, CRC(1355b7e6) SHA1(61ed045212da67cd449910ae601058cf209b37e5) )
2042	2070	ROM_LOAD( "ssi_oc.a9",    0x2000, 0x1000, CRC(6dd4b7c9) SHA1(1ce78c242d1a7d9a4524a663a42fc8bc2870053a) )
r14963	r14964
2071	2099	ROM_LOAD( "kozmkcpu.5d",  0x6000, 0x2000, CRC(a0ec38c1) SHA1(adf3ef36355d255e4ebc0d4dc86b9d7910e26b03) )
2072	2100	ROM_LOAD( "kozmkcpu.6d",  0x8000, 0x2000, CRC(7044f2b6) SHA1(55b64c9233fe0c8b351688fab29aad049d49faf2) )
2073	2101
2074		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2102	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2075	2103	ROM_LOAD( "kozmksnd.7a",  0x0000, 0x1000, CRC(6736e433) SHA1(d43216ef34a67f047b7c35001767d838386add7d) )
2076	2104	ROM_LOAD( "kozmksnd.8a",  0x1000, 0x1000, CRC(ea9cd919) SHA1(a1533b2857c881c83adce2c7bbfaa4a3148ead8e) )
2077	2105	ROM_LOAD( "kozmksnd.9a",  0x2000, 0x1000, CRC(9dfa7994) SHA1(0a2d824e9fe1d48c43027f5f10f4c43476f08e07) )
r14963	r14964
2098	2126	ROM_LOAD( "dmanpg2.bin",  0x4000, 0x2000, CRC(7dd2177a) SHA1(b4b17e2580679fbe340d8b8d8cb7171c49ae0a21) )
2099	2127	ROM_LOAD( "dmanpg3.bin",  0x6000, 0x2000, CRC(f2e0aa44) SHA1(2f04dc74c69dfe3847d5e4330e560b0a9f18c33a) )
2100	2128
2101		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2129	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2102	2130	ROM_LOAD( "dm-a7.snd",    0x0000, 0x1000, CRC(fa982dcc) SHA1(970340bfa0ac13ad8c2bf5adc21d7ca7aa9e525a) )
2103	2131	ROM_LOAD( "dm-a8.snd",    0x1000, 0x1000, CRC(72839019) SHA1(4aa278cfb00fac76cba88600bb300ee88ec3f7ee) )
2104	2132	ROM_LOAD( "dm-a9.snd",    0x2000, 0x1000, CRC(ad760da7) SHA1(024fce0f5d46e82b66c4283925556130735b863e) )
r14963	r14964
2126	2154	ROM_LOAD( "wackocpu.4d",  0x4000, 0x2000, CRC(515edff7) SHA1(9288cb5efb51086ef8610eecf8e3feae1da9fc2a) )
2127	2155	ROM_LOAD( "wackocpu.5d",  0x6000, 0x2000, CRC(9b01bf32) SHA1(d209ba2503d7b54786f74107bb399313a08a09ba) )
2128	2156
2129		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2157	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2130	2158	ROM_LOAD( "wackosnd.7a",  0x0000, 0x1000, CRC(1a58763f) SHA1(37f0870d67d52c86ae2d188e9beaa56a3a8fa130) )
2131	2159	ROM_LOAD( "wackosnd.8a",  0x1000, 0x1000, CRC(a4e3c771) SHA1(fe677090423e1d80cde07d2e74be8380d8c55e95) )
2132	2160	ROM_LOAD( "wackosnd.9a",  0x2000, 0x1000, CRC(155ba3dd) SHA1(51aaeeb68b2b7eb8238c7c3b06e84dcf44683ee9) )
r14963	r14964
2153	2181	ROM_LOAD( "cpu_d4",  0x4000, 0x2000, CRC(f1ab8c4d) SHA1(0c410ddd2e1cd8a19c73bc0c7aca70d8c4308eeb) )
2154	2182	ROM_LOAD( "cpu_d5",  0x6000, 0x2000, CRC(d7129900) SHA1(af5093082cfbc9fa4b42cfc74e62adbf9b6c63db) )
2155	2183
2156		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2184	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2157	2185	ROM_LOAD( "ssio_a7",   0x0000, 0x1000, CRC(64ddc16c) SHA1(e119e1702ea00ffb86d413ed8e68b4e9dfefa79e) )
2158	2186	ROM_LOAD( "ssio_a8",   0x1000, 0x1000, CRC(c3467612) SHA1(c968776d9561a7ac67e95a987b6d826ec2dc748e) )
2159	2187	ROM_LOAD( "ssio_a9",   0x2000, 0x1000, CRC(c50f7b2d) SHA1(0f4779d4955d500c50b544d945fa78a5428b86ce) )
r14963	r14964
2179	2207	ROM_LOAD( "2tgrpg2.bin",  0x4000, 0x2000, CRC(b5ca3f17) SHA1(ac51eefe9ff49bc358daf58525e529070684ed1b) )
2180	2208	ROM_LOAD( "2tgrpg3.bin",  0x6000, 0x2000, CRC(8aa82049) SHA1(6e42d082d29986f5c0698ae39750fb8f9eb1e6cd) )
2181	2209
2182		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2210	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2183	2211	ROM_LOAD( "2tgra7.bin",   0x0000, 0x1000, CRC(4620d970) SHA1(2c2c1da84199b846575a6291dc235f30539959fa) )
2184	2212	ROM_LOAD( "2tgra8.bin",   0x1000, 0x1000, CRC(e95d8cfe) SHA1(846d5543596bb86cf08f998056c1fc695cb4f62c) )
2185	2213	ROM_LOAD( "2tgra9.bin",   0x2000, 0x1000, CRC(81e6ce0e) SHA1(77e145e150763bfe5760ac3e4f68218a65b9bfe0) )
r14963	r14964
2207	2235	ROM_LOAD( "d5",           0x6000, 0x2000, CRC(c3023931) SHA1(e591a18c5fc8befcd9f2b93d9131374c572cdbcd) )
2208	2236	ROM_LOAD( "d6",           0x8000, 0x2000, CRC(5d445c99) SHA1(df2bce203f510b4bda42bb7114b79eb0b2b4e2e0) )
2209	2237
2210		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2238	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2211	2239	ROM_LOAD( "a",            0x0000, 0x1000, CRC(2524a2aa) SHA1(4bd78b4fb42c2506fa6734419b42cbbe4c240e94) )
2212	2240	ROM_LOAD( "b",            0x1000, 0x1000, CRC(b8e35814) SHA1(379308431d1204d6cb5ae8a13e378ec7b3fab0a9) )
2213	2241	ROM_LOAD( "c",            0x2000, 0x1000, CRC(09c488cf) SHA1(7aa3321db748f2612693f8348e590369e8d48140) )
r14963	r14964
2239	2267	ROM_LOAD( "tappg2.bin",   0x08000, 0x4000, CRC(3a1f8778) SHA1(cb46a2248289ced7282b1463f433dcb970c42c1a) )
2240	2268	ROM_LOAD( "tappg3.bin",   0x0c000, 0x2000, CRC(e8dcdaa4) SHA1(45bf1571a2418c7dc00ccc7061a3e04e65cb6bff) )
2241	2269
2242		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2270	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2243	2271	ROM_LOAD( "tapsnda7.bin", 0x0000, 0x1000, CRC(0e8bb9d5) SHA1(9e281c340b7702523c86d56317efad9e3688e585) )
2244	2272	ROM_LOAD( "tapsnda8.bin", 0x1000, 0x1000, CRC(0cf0e29b) SHA1(14334b9d2bfece3fe5bda0cbd53158ead8d27e53) )
2245	2273	ROM_LOAD( "tapsnda9.bin", 0x2000, 0x1000, CRC(31eb6dc6) SHA1(b38bba5f12516d899e023f99147868e3402fbd7b) )
r14963	r14964
2270	2298	ROM_LOAD( "pr02_3c.128",   0x08000, 0x4000, CRC(b3755d41) SHA1(434d3c27b9f1e43def081d79b9f56dbce93a9207) )
2271	2299	ROM_LOAD( "pr03_4c.64",    0x0c000, 0x2000, CRC(77273096) SHA1(5e4e2dc1703b39f588ba374f6a610f273d710532) )
2272	2300
2273		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2301	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2274	2302	ROM_LOAD( "tapsnda7.bin", 0x0000, 0x1000, CRC(0e8bb9d5) SHA1(9e281c340b7702523c86d56317efad9e3688e585) )
2275	2303	ROM_LOAD( "tapsnda8.bin", 0x1000, 0x1000, CRC(0cf0e29b) SHA1(14334b9d2bfece3fe5bda0cbd53158ead8d27e53) )
2276	2304	ROM_LOAD( "tapsnda9.bin", 0x2000, 0x1000, CRC(31eb6dc6) SHA1(b38bba5f12516d899e023f99147868e3402fbd7b) )
r14963	r14964
2301	2329	ROM_LOAD( "5793",         0x8000, 0x4000, CRC(fecbf683) SHA1(de365f4e567d93a9ed9672fabbc739a3a0d47d59) )
2302	2330	ROM_LOAD( "5794",         0xc000, 0x2000, CRC(5bdc1916) SHA1(ee038443ae55598568bd1a53c0a671a2828d3949) )
2303	2331
2304		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2332	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2305	2333	ROM_LOAD( "5788",         0x00000, 0x1000, CRC(5c1d0982) SHA1(c2c94ab26ebce30ce4efc239e555c6368794d265) )
2306	2334	ROM_LOAD( "5787",         0x01000, 0x1000, CRC(09e74ed8) SHA1(f5c8585d443bca67d4065314a06431d1f104c553) )
2307	2335	ROM_LOAD( "5786",         0x02000, 0x1000, CRC(c3e98284) SHA1(2a4dc0deca48f4d2ac9fe673ecb9548415c996a9) )
r14963	r14964
2332	2360	ROM_LOAD( "rbtpg2.bin",   0x08000, 0x4000, CRC(0b332c97) SHA1(b9878c8a61a98e787e547bb6ab81c809875891f3) )
2333	2361	ROM_LOAD( "rbtpg3.bin",   0x0c000, 0x2000, CRC(698c06f2) SHA1(ddb21e39ede2222cb2286ec9dba06341fe1c9db7) )
2334	2362
2335		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2363	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2336	2364	ROM_LOAD( "5788",         0x00000, 0x1000, CRC(5c1d0982) SHA1(c2c94ab26ebce30ce4efc239e555c6368794d265) )
2337	2365	ROM_LOAD( "5787",         0x01000, 0x1000, CRC(09e74ed8) SHA1(f5c8585d443bca67d4065314a06431d1f104c553) )
2338	2366	ROM_LOAD( "5786",         0x02000, 0x1000, CRC(c3e98284) SHA1(2a4dc0deca48f4d2ac9fe673ecb9548415c996a9) )
r14963	r14964
2364	2392	ROM_LOAD( "timpg2.bin",   0x08000, 0x4000, CRC(632989f9) SHA1(9e9dc343746299bb0dc7ada206211366c5a05075) )
2365	2393	ROM_LOAD( "timpg3.bin",   0x0c000, 0x2000, CRC(dae8a0dc) SHA1(f065fa3184efa6524d4f950616f3fbae4ea17513) )
2366	2394
2367		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2395	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2368	2396	ROM_LOAD( "tima7.bin",    0x00000, 0x1000, CRC(c615dc3e) SHA1(664d5e3ac3936fd04a855ee0c88f1c1b4d1dea5b) )
2369	2397	ROM_LOAD( "tima8.bin",    0x01000, 0x1000, CRC(83841c87) SHA1(bd5a2e567e015e10e45651e15b42ffb3b69d2305) )
2370	2398	ROM_LOAD( "tima9.bin",    0x02000, 0x1000, CRC(22bcdcd3) SHA1(69cedc8cec52ca310f828dfe73d7de04729b06d3) )
r14963	r14964
2395	2423	ROM_LOAD( "loc-pg2.3c",   0x08000, 0x4000, CRC(ab0b3800) SHA1(457a18bd98a3c4a9f893a3704dbc7d0fde4ef8ba) )
2396	2424	ROM_LOAD( "loc-pg1.4c",   0x0c000, 0x2000, CRC(f98c9f8e) SHA1(a215f0fd6cd9e8cacbe06cb7bfe4e2cced150c86) )
2397	2425
2398		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2426	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2399	2427	ROM_LOAD( "sound0.a7",    0x00000, 0x1000, CRC(6d39bf19) SHA1(3d27466fcb6d41133f16119cddb815833c8b4eda) )
2400	2428	ROM_LOAD( "sound1.a8",    0x01000, 0x1000, CRC(ac872e1d) SHA1(c2833b20e124c505be3d5be2c885b9cf9927ca4c) )
2401	2429	ROM_LOAD( "sound2.a9",    0x02000, 0x1000, CRC(e8ef6519) SHA1(261b0463a73b403bc46df3e04f3d12173787d6e7) )
r14963	r14964
2426	2454	ROM_LOAD( "aloc-pg2.3c",  0x08000, 0x4000, CRC(cb89c9be) SHA1(c773a68891fbf94808a2ee0036928c0c48d6673d) )
2427	2455	ROM_LOAD( "aloc-pg1.4c",  0x0c000, 0x2000, CRC(5098faf4) SHA1(9f861f99cb170513b68aee48bbfd60ee439d7fa9) )
2428	2456
2429		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2457	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2430	2458	ROM_LOAD( "asound0.a7",   0x00000, 0x1000, CRC(7fb54293) SHA1(6d538a3e48f98e269623850f1f6774848a89fd59) )
2431	2459	ROM_LOAD( "asound1.a8",   0x01000, 0x1000, CRC(edef7326) SHA1(5c9a64604252eea0628bf9d6221e8add82f66abe) )
2432	2460	ROM_LOAD( "sound2.a9",    0x02000, 0x1000, CRC(e8ef6519) SHA1(261b0463a73b403bc46df3e04f3d12173787d6e7) )
r14963	r14964
2457	2485	ROM_LOAD( "loc-cpu3",     0x08000, 0x4000, CRC(94bb1a0e) SHA1(af4769fac39e67eff840675bf93cc4304f2875fd) )
2458	2486	ROM_LOAD( "loc-cpu4",     0x0c000, 0x2000, CRC(c137383c) SHA1(ccf7cf9c7c0528aa819cfca34c1c0e89ab2d586a) )
2459	2487
2460		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2488	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2461	2489	ROM_LOAD( "loc-a",        0x00000, 0x1000, CRC(2de6a8a8) SHA1(6bba00daed8836297f3189db4e4fe8e158adc465) )
2462	2490	ROM_LOAD( "loc-b",        0x01000, 0x1000, CRC(4097663e) SHA1(afb5224529550cec378415a5cd81b47f6c6c101b) )
2463	2491	ROM_LOAD( "loc-c",        0x02000, 0x1000, CRC(f576b9e7) SHA1(4ff39c46c390aa93d900f5f7a0b35fa71f066863) )
2464	2492	ROM_LOAD( "loc-d",        0x03000, 0x1000, CRC(74b0059e) SHA1(1fe393721446538036fb6110fdc3920959ebd596) )
2465	2493
2466		ROM_REGION( 0x10000, "sntcpu", 0 )
	2494	ROM_REGION( 0x10000, "snt:cpu", 0 )
2467	2495	ROM_LOAD( "pre.u3",       0x09000, 0x1000, CRC(c3d0f762) SHA1(a1857641c35b5bcb33f29fe79a1a581c4cbf129b) )
2468	2496	ROM_LOAD( "pre.u4",       0x0a000, 0x1000, CRC(7ca79b43) SHA1(c995e1e67d70706a090eb777e9fec0f1ba03f82d) )
2469	2497	ROM_LOAD( "pre.u5",       0x0b000, 0x1000, CRC(24e9618e) SHA1(eb245ff381a76b314a0ed3519e140444afae341c) )
r14963	r14964
2494	2522	ROM_LOAD( "nflcpupg.2c",  0x04000, 0x4000, CRC(2aa76168) SHA1(608df883f5e960153a963404d5cc4b4ce4ec435d) )
2495	2523	ROM_LOAD( "nflcpupg.3c",  0x08000, 0x4000, CRC(5ec01e09) SHA1(2bf60ab7d47f53583b677195976d6f6a9e90c55c) )
2496	2524
2497		ROM_REGION( 0x10000, "ssiocpu", 0 )
	2525	ROM_REGION( 0x10000, "ssio:cpu", 0 )
2498	2526	ROM_LOAD( "nflsnd.a7",    0x0000, 0x1000, CRC(1339be2e) SHA1(5c1743f4d20f94053eb306d3749057608df4a6a2) )
2499	2527	ROM_LOAD( "nflsnd.a8",    0x1000, 0x1000, CRC(8630b560) SHA1(0c537f48184d3a7a9ee51c30d7c33dc39c46e823) )
2500	2528	ROM_LOAD( "nflsnd.a9",    0x2000, 0x1000, CRC(1e0fe4c8) SHA1(718dfaced2d8d84dab4c32265bed422e07af0f9e) )
2501	2529
2502		ROM_REGION( 0x10000, "sntcpu", 0 )
	2530	ROM_REGION( 0x10000, "snt:cpu", 0 )
2503	2531	ROM_LOAD( "nfl-sqtk-11-15-83.u2", 0x08000, 0x1000, CRC(aeddda31) SHA1(8ebe9d8606c4328b1b3f4633db30d7636acf210b) )
2504	2532	ROM_LOAD( "nfl-sqtk-11-15-83.u3", 0x09000, 0x1000, CRC(36229d13) SHA1(d174098ce1e4bc89ded15a08db37933ab9532f2b) )
2505	2533	ROM_LOAD( "nfl-sqtk-11-15-83.u4", 0x0a000, 0x1000, CRC(b202439b) SHA1(b09e94b0b176f80b12fb4cefa6efd5b2cccb6192) )
r14963	r14964
2534	2562	ROM_LOAD( "dd_pro1",      0x04000, 0x4000, CRC(4c713bfe) SHA1(493b6ba01e86e7586ad123c53cf7f0a0c191d670) )
2535	2563	ROM_LOAD( "dd_pro2",      0x08000, 0x4000, CRC(c2cbd2a4) SHA1(fa642b2f61ff5529ab688a43c1dc14357a4eba6f) )
2536	2564
2537		ROM_REGION( 0x10000, "ssiocpu", ROMREGION_ERASE00 )   /* 64k for the audio CPU, not populated */
	2565	ROM_REGION( 0x10000, "ssio:cpu", ROMREGION_ERASE00 )   /* 64k for the audio CPU, not populated */
2538	2566
2539		ROM_REGION( 0x10000, "tcscpu", 0 )   /* 64k for the Turbo Cheap Squeak */
	2567	ROM_REGION( 0x10000, "tcs:cpu", 0 )   /* 64k for the Turbo Cheap Squeak */
2540	2568	ROM_LOAD( "tcs_u5.bin",   0x0c000, 0x2000, CRC(eca33b2c) SHA1(938b021ea3b0f23aed7a98a930a58af371a02303) )
2541	2569	ROM_LOAD( "tcs_u4.bin",   0x0e000, 0x2000, CRC(3490289a) SHA1(a9d56ea60bb901267da41ab408f8e1ed3742b0ac) )
2542	2570
r14963	r14964
2576	2604
2577	2605	state_save_register_global(machine, input_mux);
2578	2606	state_save_register_global(machine, last_op4);
	2607
	2608	midway_ssio_device *ssio = machine.device<midway_ssio_device>("ssio");
	2609	if (ssio != NULL)
	2610	{
	2611	mcr_state *state = machine.driver_data<mcr_state>();
	2612	ssio->set_custom_output(0, 0xff, write8_delegate(FUNC(mcr_state::mcr_control_port_w), state));
	2613	}
2579	2614	}
2580	2615
2581	2616
2582	2617	static DRIVER_INIT( solarfox )
2583	2618	{
2584	2619	mcr_init(machine, 90009, 91399, 90908);
2585		mcr_sound_init(machine, MCR_SSIO);
2586	2620
2587	2621	mcr_state *state = machine.driver_data<mcr_state>();
2588		ssio_set_custom_input(0, 0x1c, read8_delegate(FUNC(mcr_state::solarfox_ip0_r),state));
2589		ssio_set_custom_input(1, 0xff, read8_delegate(FUNC(mcr_state::solarfox_ip1_r),state));
	2622	machine.device<midway_ssio_device>("ssio")->set_custom_input(0, 0x1c, read8_delegate(FUNC(mcr_state::solarfox_ip0_r),state));
	2623	machine.device<midway_ssio_device>("ssio")->set_custom_input(1, 0xff, read8_delegate(FUNC(mcr_state::solarfox_ip1_r),state));
2590	2624
2591	2625	mcr12_sprite_xoffs = 16;
2592	2626	}
r14963	r14964
2595	2629	static DRIVER_INIT( kick )
2596	2630	{
2597	2631	mcr_init(machine, 90009, 91399, 90908);
2598		mcr_sound_init(machine, MCR_SSIO);
2599	2632
2600	2633	mcr_state *state = machine.driver_data<mcr_state>();
2601		ssio_set_custom_input(1, 0xf0, read8_delegate(FUNC(mcr_state::kick_ip1_r),state));
	2634	machine.device<midway_ssio_device>("ssio")->set_custom_input(1, 0xf0, read8_delegate(FUNC(mcr_state::kick_ip1_r),state));
2602	2635
2603	2636	mcr12_sprite_xoffs_flip = 16;
2604	2637	}
r14963	r14964
2607	2640	static DRIVER_INIT( mcr_90010 )
2608	2641	{
2609	2642	mcr_init(machine, 90010, 91399, 90913);
2610		mcr_sound_init(machine, MCR_SSIO);
2611	2643	}
2612	2644
2613	2645
2614	2646	static DRIVER_INIT( wacko )
2615	2647	{
2616	2648	mcr_init(machine, 90010, 91399, 90913);
2617		mcr_sound_init(machine, MCR_SSIO);
2618	2649
2619	2650	mcr_state *state = machine.driver_data<mcr_state>();
2620		ssio_set_custom_input(1, 0xff, read8_delegate(FUNC(mcr_state::wacko_ip1_r),state));
2621		ssio_set_custom_input(2, 0xff, read8_delegate(FUNC(mcr_state::wacko_ip2_r),state));
2622		ssio_set_custom_output(4, 0x01, write8_delegate(FUNC(mcr_state::wacko_op4_w),state));
	2651	machine.device<midway_ssio_device>("ssio")->set_custom_input(1, 0xff, read8_delegate(FUNC(mcr_state::wacko_ip1_r),state));
	2652	machine.device<midway_ssio_device>("ssio")->set_custom_input(2, 0xff, read8_delegate(FUNC(mcr_state::wacko_ip2_r),state));
	2653	machine.device<midway_ssio_device>("ssio")->set_custom_output(4, 0x01, write8_delegate(FUNC(mcr_state::wacko_op4_w),state));
2623	2654	}
2624	2655
2625	2656
2626	2657	static DRIVER_INIT( twotiger )
2627	2658	{
2628	2659	mcr_init(machine, 90010, 91399, 90913);
2629		mcr_sound_init(machine, MCR_SSIO);
2630	2660
2631	2661	mcr_state *state = machine.driver_data<mcr_state>();
2632		ssio_set_custom_output(4, 0xff, write8_delegate(FUNC(mcr_state::twotiger_op4_w),state));
	2662	machine.device<midway_ssio_device>("ssio")->set_custom_output(4, 0xff, write8_delegate(FUNC(mcr_state::twotiger_op4_w),state));
2633	2663	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xe800, 0xefff, 0, 0x1000, read8_delegate(FUNC(mcr_state::twotiger_videoram_r),state), write8_delegate(FUNC(mcr_state::twotiger_videoram_w),state));
2634	2664	}
2635	2665
r14963	r14964
2637	2667	static DRIVER_INIT( kroozr )
2638	2668	{
2639	2669	mcr_init(machine, 90010, 91399, 91483);
2640		mcr_sound_init(machine, MCR_SSIO);
2641	2670
2642	2671	mcr_state *state = machine.driver_data<mcr_state>();
2643		ssio_set_custom_input(1, 0x47, read8_delegate(FUNC(mcr_state::kroozr_ip1_r),state));
2644		ssio_set_custom_output(4, 0x34, write8_delegate(FUNC(mcr_state::kroozr_op4_w),state));
	2672	machine.device<midway_ssio_device>("ssio")->set_custom_input(1, 0x47, read8_delegate(FUNC(mcr_state::kroozr_ip1_r),state));
	2673	machine.device<midway_ssio_device>("ssio")->set_custom_output(4, 0x34, write8_delegate(FUNC(mcr_state::kroozr_op4_w),state));
2645	2674	}
2646	2675
2647	2676
2648	2677	static DRIVER_INIT( journey )
2649	2678	{
2650	2679	mcr_init(machine, 91475, 91464, 90913);
2651		mcr_sound_init(machine, MCR_SSIO);
2652	2680
2653	2681	mcr_state *state = machine.driver_data<mcr_state>();
2654		ssio_set_custom_output(4, 0x01, write8_delegate(FUNC(mcr_state::journey_op4_w),state));
	2682	machine.device<midway_ssio_device>("ssio")->set_custom_output(4, 0x01, write8_delegate(FUNC(mcr_state::journey_op4_w),state));
2655	2683	}
2656	2684
2657	2685
2658	2686	static DRIVER_INIT( mcr_91490 )
2659	2687	{
2660	2688	mcr_init(machine, 91490, 91464, 90913);
2661		mcr_sound_init(machine, MCR_SSIO);
2662	2689	}
2663	2690
2664	2691
2665	2692	static DRIVER_INIT( dotrone )
2666	2693	{
2667	2694	mcr_init(machine, 91490, 91464, 91657);
2668		mcr_sound_init(machine, MCR_SSIO | MCR_SQUAWK_N_TALK);
2669	2695
2670	2696	mcr_state *state = machine.driver_data<mcr_state>();
2671		ssio_set_custom_output(4, 0xff, write8_delegate(FUNC(mcr_state::dotron_op4_w),state));
	2697	machine.device<midway_ssio_device>("ssio")->set_custom_output(4, 0xff, write8_delegate(FUNC(mcr_state::dotron_op4_w),state));
2672	2698	}
2673	2699
2674	2700
2675	2701	static DRIVER_INIT( nflfoot )
2676	2702	{
2677	2703	mcr_init(machine, 91490, 91464, 91657);
2678		mcr_sound_init(machine, MCR_SSIO | MCR_SQUAWK_N_TALK);
2679	2704
2680	2705	mcr_state *state = machine.driver_data<mcr_state>();
2681		ssio_set_custom_input(2, 0x80, read8_delegate(FUNC(mcr_state::nflfoot_ip2_r),state));
2682		ssio_set_custom_output(4, 0xff, write8_delegate(FUNC(mcr_state::nflfoot_op4_w),state));
	2706	machine.device<midway_ssio_device>("ssio")->set_custom_input(2, 0x80, read8_delegate(FUNC(mcr_state::nflfoot_ip2_r),state));
	2707	machine.device<midway_ssio_device>("ssio")->set_custom_output(4, 0xff, write8_delegate(FUNC(mcr_state::nflfoot_op4_w),state));
2683	2708
2684	2709	nflfoot_serial_out_active = FALSE;
2685	2710	nflfoot_serial_in_active = FALSE;
r14963	r14964
2696	2721	static DRIVER_INIT( demoderb )
2697	2722	{
2698	2723	mcr_init(machine, 91490, 91464, 90913);
2699		mcr_sound_init(machine, MCR_SSIO | MCR_TURBO_CHIP_SQUEAK);
2700	2724
2701	2725	mcr_state *state = machine.driver_data<mcr_state>();
2702		ssio_set_custom_input(1, 0xfc, read8_delegate(FUNC(mcr_state::demoderb_ip1_r),state));
2703		ssio_set_custom_input(2, 0xfc, read8_delegate(FUNC(mcr_state::demoderb_ip2_r),state));
2704		ssio_set_custom_output(4, 0xff, write8_delegate(FUNC(mcr_state::demoderb_op4_w),state));
	2726	machine.device<midway_ssio_device>("ssio")->set_custom_input(1, 0xfc, read8_delegate(FUNC(mcr_state::demoderb_ip1_r),state));
	2727	machine.device<midway_ssio_device>("ssio")->set_custom_input(2, 0xfc, read8_delegate(FUNC(mcr_state::demoderb_ip2_r),state));
	2728	machine.device<midway_ssio_device>("ssio")->set_custom_output(4, 0xff, write8_delegate(FUNC(mcr_state::demoderb_op4_w),state));
2705	2729
2706	2730	/* the SSIO Z80 doesn't have any program to execute */
2707		machine.device<cpu_device>("tcscpu")->suspend(SUSPEND_REASON_DISABLE, 1);
	2731	machine.device<cpu_device>("ssio:cpu")->suspend(SUSPEND_REASON_DISABLE, 1);
2708	2732	}
2709	2733
2710	2734

src/mame/drivers/chqflag.c

r14963	r14964
266	266
267	267	static const ym2151_interface ym2151_config =
268	268	{
269		chqflag_ym2151_irq_w
	269	DEVCB_LINE(chqflag_ym2151_irq_w)
270	270	};
271	271
272	272	static void volume_callback0( device_t *device, int v )

src/mame/drivers/dooyong.c

r14963	r14964
815	815
816	816	static const ym2151_interface ym2151_config =
817	817	{
818		irqhandler
	818	DEVCB_LINE(irqhandler)
819	819	};
820	820
821	821	/***************************************************************************

src/mame/drivers/silvmil.c

r14963	r14964
4	4	yet another Data East / Tumble Pop derived hardware
5	5	this one seems similar to (but not identical to)
6	6	the crospang.c hardware from F2 system
	7	also very close to gotcha.c, which was also a Para
	8	board.
7	9
8	10	todo: refresh rate & audio balance
9	11	verify dipswitches - difficulty & unknown dips
r14963	r14964
289	291	AM_RANGE(0x0000, 0xbfff) AM_ROM
290	292	AM_RANGE(0xd000, 0xd7ff) AM_RAM
291	293	AM_RANGE(0xc000, 0xc001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r, ym2151_w)
292		AM_RANGE(0xc002, 0xc002) AM_DEVREADWRITE("oki", okim6295_device, read, write)
293		AM_RANGE(0xc003, 0xc003) AM_DEVREADWRITE("oki", okim6295_device, read, write)
	294	AM_RANGE(0xc002, 0xc002) AM_DEVREADWRITE("oki", okim6295_device, read, write) AM_MIRROR(1)
294	295	AM_RANGE(0xc006, 0xc006) AM_READ(soundlatch_byte_r)
295	296	AM_RANGE(0xc00f, 0xc00f) AM_WRITENOP // ??
296	297	ADDRESS_MAP_END
r14963	r14964
305	306
306	307	static const ym2151_interface silvmil_ym2151_interface =
307	308	{
308		silvmil_irqhandler
	309	DEVCB_LINE(silvmil_irqhandler)
309	310	};
310	311
311	312

src/mame/drivers/tourtabl.c

r14963	r14964
36	36	}
37	37
38	38
39		static READ16_HANDLER( tourtabl_read_input_port )
	39	static READ16_DEVICE_HANDLER( tourtabl_read_input_port )
40	40	{
41	41	static const char *const tianames[] = { "PADDLE4", "PADDLE3", "PADDLE2", "PADDLE1", "TIA_IN4", "TIA_IN5" };
42	42
43		return input_port_read(space->machine(), tianames[offset]);
	43	return input_port_read(device->machine(), tianames[offset]);
44	44	}
45	45
46		static READ8_HANDLER( tourtabl_get_databus_contents )
	46	static READ8_DEVICE_HANDLER( tourtabl_get_databus_contents )
47	47	{
48	48	return offset;
49	49	}
50	50
51	51
52	52	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, tourtabl_state )
53		AM_RANGE(0x0000, 0x007f) AM_MIRROR(0x0100) AM_READWRITE_LEGACY(tia_r, tia_w)
	53	AM_RANGE(0x0000, 0x007f) AM_MIRROR(0x0100) AM_DEVREADWRITE("tia_video", tia_video_device, read, write)
54	54	AM_RANGE(0x0080, 0x00ff) AM_MIRROR(0x0100) AM_RAM
55	55	AM_RANGE(0x0280, 0x029f) AM_DEVREADWRITE_LEGACY("riot1", riot6532_r, riot6532_w)
56	56	AM_RANGE(0x0400, 0x047f) AM_RAM
r14963	r14964
87	87
88	88	static const struct tia_interface tourtabl_tia_interface =
89	89	{
90		tourtabl_read_input_port,
91		tourtabl_get_databus_contents,
92		NULL
	90	DEVCB_HANDLER(tourtabl_read_input_port),
	91	DEVCB_HANDLER(tourtabl_get_databus_contents),
	92	DEVCB_NULL
93	93	};
94	94
95
96		static MACHINE_START( tourtabl )
97		{
98		tia_init( machine, &tourtabl_tia_interface );
99		}
100
101
102	95	static INPUT_PORTS_START( tourtabl )
103	96
104	97	PORT_START("PADDLE4")
r14963	r14964
179	172	MCFG_CPU_ADD("maincpu", M6502, MASTER_CLOCK / 3)   /* actually M6507 */
180	173	MCFG_CPU_PROGRAM_MAP(main_map)
181	174
182		MCFG_MACHINE_START(tourtabl)
183
184	175	MCFG_RIOT6532_ADD("riot1", MASTER_CLOCK / 3, r6532_interface_0)
185	176	MCFG_RIOT6532_ADD("riot2", MASTER_CLOCK / 3, r6532_interface_1)
186	177
	178	MCFG_TIA_VIDEO_ADD("tia_video", tourtabl_tia_interface)
187	179	/* video hardware */
188	180	MCFG_SCREEN_ADD("screen", RASTER)
189	181	MCFG_SCREEN_RAW_PARAMS( MASTER_CLOCK, 228, 34, 34 + 160, 262, 46, 46 + 200 )
190		MCFG_SCREEN_UPDATE_STATIC(tia)
	182	MCFG_SCREEN_UPDATE_DEVICE("tia_video", tia_video_device, screen_update)
191	183
192	184	MCFG_PALETTE_LENGTH(TIA_PALETTE_LENGTH)
193	185	MCFG_PALETTE_INIT(tia_NTSC)
194	186
195		MCFG_VIDEO_START(tia)
196
197	187	/* sound hardware */
198	188	MCFG_SPEAKER_STANDARD_MONO("mono")
199	189

src/mame/drivers/rpunch.c

r14963	r14964
449	449
450	450	static const ym2151_interface ym2151_config =
451	451	{
452		ym2151_irq_gen
	452	DEVCB_LINE(ym2151_irq_gen)
453	453	};
454	454
455	455

src/mame/drivers/starwars.c

r14963	r14964
120	120	*
121	121	*************************************/
122	122
123		DIRECT_UPDATE_HANDLER( esb_setdirect )
	123	DIRECT_UPDATE_MEMBER(starwars_state::esb_setdirect)
124	124	{
125		starwars_state *state = machine.driver_data<starwars_state>();
126	125	/* if we are in the slapstic region, process it */
127	126	if ((address & 0xe000) == 0x8000)
128	127	{
r14963	r14964
133	132	1. Because we have read/write handlers backing the current address
134	133	2. Because the CPU core executed a jump to a new address
135	134	*/
136		if (pc != state->m_slapstic_last_pc || address != state->m_slapstic_last_address)
	135	if (pc != m_slapstic_last_pc || address != m_slapstic_last_address)
137	136	{
138		state->m_slapstic_last_pc = pc;
139		state->m_slapstic_last_address = address;
	137	m_slapstic_last_pc = pc;
	138	m_slapstic_last_address = address;
140	139	esb_slapstic_tweak(&direct.space(), address & 0x1fff);
141	140	}
142	141	return ~0;
r14963	r14964
520	519
521	520	/* install an opcode base handler */
522	521	address_space *space = machine.device<m6809_device>("maincpu")->space(AS_PROGRAM);
523		space->set_direct_update_handler(direct_update_delegate(FUNC(esb_setdirect), &machine));
	522	space->set_direct_update_handler(direct_update_delegate(FUNC(starwars_state::esb_setdirect), state));
524	523
525	524	/* install read/write handlers for it */
526	525	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x8000, 0x9fff, read8_delegate(FUNC(starwars_state::esb_slapstic_r),state), write8_delegate(FUNC(starwars_state::esb_slapstic_w),state));

src/mame/drivers/rainbow.c

r14963	r14964
631	631
632	632	static const ym2151_interface ym2151_config =
633	633	{
634		irqhandler,
635		bankswitch_w
	634	DEVCB_LINE(irqhandler),
	635	DEVCB_HANDLER(bankswitch_w)
636	636	};
637	637
638	638

src/mame/drivers/madmotor.c

r14963	r14964
227	227
228	228	static const ym2151_interface ym2151_config =
229	229	{
230		sound_irq
	230	DEVCB_LINE(sound_irq)
231	231	};
232	232
233	233	static MACHINE_START( madmotor )

src/mame/drivers/midyunit.c

r14963	r14964
114	114	#include "emu.h"
115	115	#include "cpu/z80/z80.h"
116	116	#include "cpu/tms34010/tms34010.h"
117		#include "audio/williams.h"
118	117	#include "sound/okim6295.h"
119	118	#include "includes/midyunit.h"
120	119
r14963	r14964
152	151
153	152	CUSTOM_INPUT_MEMBER(midyunit_state::narc_talkback_strobe_r)
154	153	{
155		return (williams_narc_talkback_r(machine()) >> 8) & 1;
	154	return (m_narc_sound->read(*machine().memory().first_space(), 0) >> 8) & 1;
156	155	}
157	156
158	157
159	158	CUSTOM_INPUT_MEMBER(midyunit_state::narc_talkback_data_r)
160	159	{
161		return williams_narc_talkback_r(machine()) & 0xff;
	160	return m_narc_sound->read(*machine().memory().first_space(), 0) & 0xff;
162	161	}
163	162
164	163
165	164	CUSTOM_INPUT_MEMBER(midyunit_state::adpcm_irq_state_r)
166	165	{
167		return williams_adpcm_sound_irq_r(machine()) & 1;
	166	return m_adpcm_sound->irq_read() & 1;
168	167	}
169	168
170	169
r14963	r14964
1018	1017	MCFG_VIDEO_START(midzunit)
1019	1018
1020	1019	/* sound hardware */
1021		MCFG_FRAGMENT_ADD(williams_narc_sound)
	1020	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
	1021	MCFG_WILLIAMS_NARC_SOUND_ADD("narcsnd")
	1022	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
	1023	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
1022	1024	MACHINE_CONFIG_END
1023	1025
1024	1026
r14963	r14964
1046	1048	MCFG_SCREEN_ADD("screen", RASTER)
1047	1049	MCFG_SCREEN_RAW_PARAMS(STDRES_PIXEL_CLOCK*2, 505, 0, 399, 289, 0, 253)
1048	1050	MCFG_SCREEN_UPDATE_STATIC(tms340x0_ind16)
	1051
	1052	/* sound hardware */
	1053	MCFG_SPEAKER_STANDARD_MONO("mono")
1049	1054	MACHINE_CONFIG_END
1050	1055
1051	1056
1052	1057	static MACHINE_CONFIG_DERIVED( yunit_cvsd_4bit_slow, yunit_core )
1053	1058
1054	1059	/* basic machine hardware */
1055		MCFG_FRAGMENT_ADD(williams_cvsd_sound)
	1060	MCFG_WILLIAMS_CVSD_SOUND_ADD("cvsd")
	1061	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1056	1062
1057	1063	/* video hardware */
1058	1064	MCFG_PALETTE_LENGTH(256)
r14963	r14964
1065	1071	/* basic machine hardware */
1066	1072	MCFG_CPU_MODIFY("maincpu")
1067	1073	MCFG_CPU_CLOCK(FAST_MASTER_CLOCK)
1068		MCFG_FRAGMENT_ADD(williams_cvsd_sound)
	1074
	1075	MCFG_WILLIAMS_CVSD_SOUND_ADD("cvsd")
	1076	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1069	1077
1070	1078	/* video hardware */
1071	1079	MCFG_PALETTE_LENGTH(256)
r14963	r14964
1076	1084	static MACHINE_CONFIG_DERIVED( yunit_cvsd_6bit_slow, yunit_core )
1077	1085
1078	1086	/* basic machine hardware */
1079		MCFG_FRAGMENT_ADD(williams_cvsd_sound)
	1087	MCFG_WILLIAMS_CVSD_SOUND_ADD("cvsd")
	1088	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1080	1089
1081	1090	/* video hardware */
1082	1091	MCFG_PALETTE_LENGTH(4096)
r14963	r14964
1089	1098	/* basic machine hardware */
1090	1099	MCFG_CPU_MODIFY("maincpu")
1091	1100	MCFG_CPU_CLOCK(FAST_MASTER_CLOCK)
1092		MCFG_FRAGMENT_ADD(williams_adpcm_sound)
	1101
	1102	MCFG_WILLIAMS_ADPCM_SOUND_ADD("adpcm")
	1103	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1093	1104
1094	1105	/* video hardware */
1095	1106	MCFG_PALETTE_LENGTH(4096)
r14963	r14964
1102	1113	/* basic machine hardware */
1103	1114	MCFG_CPU_MODIFY("maincpu")
1104	1115	MCFG_CPU_CLOCK(FASTER_MASTER_CLOCK)
1105		MCFG_FRAGMENT_ADD(williams_adpcm_sound)
	1116
	1117	MCFG_WILLIAMS_ADPCM_SOUND_ADD("adpcm")
	1118	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1106	1119
1107	1120	/* video hardware */
1108	1121	MCFG_PALETTE_LENGTH(4096)
r14963	r14964
1122	1135	MCFG_VIDEO_START(mkyawdim)
1123	1136
1124	1137	/* sound hardware */
1125		MCFG_SPEAKER_STANDARD_MONO("mono")
1126
1127	1138	MCFG_OKIM6295_ADD("oki", 1056000, OKIM6295_PIN7_HIGH) // clock frequency & pin 7 not verified
1128	1139	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1129	1140	MACHINE_CONFIG_END
r14963	r14964
1137	1148	*************************************/
1138	1149
1139	1150	ROM_START( narc )
1140		ROM_REGION( 0x90000, "narc1cpu", 0 )    /* sound CPU */
	1151	ROM_REGION( 0x90000, "narcsnd:cpu0", 0 )    /* sound CPU */
1141	1152	ROM_LOAD( "narcrev2.u4", 0x50000, 0x10000, CRC(450a591a) SHA1(bbda8061262738e5866f2707f69483a0a51d2910) )
1142	1153	ROM_RELOAD(              0x60000, 0x10000 )
1143	1154	ROM_LOAD( "narcrev2.u5", 0x70000, 0x10000, CRC(e551e5e3) SHA1(c8b4f53dbd4c534abb77d4dc07c4d12653b79894) )
1144	1155	ROM_RELOAD(              0x80000, 0x10000 )
1145	1156
1146		ROM_REGION( 0x90000, "narc2cpu", 0 )   /* slave sound CPU */
	1157	ROM_REGION( 0x90000, "narcsnd:cpu1", 0 )   /* slave sound CPU */
1147	1158	ROM_LOAD( "narcrev2.u35", 0x10000, 0x10000, CRC(81295892) SHA1(159664e5ee03c88d6e940e70e87e2150dc5b8b25) )
1148	1159	ROM_RELOAD(               0x20000, 0x10000 )
1149	1160	ROM_LOAD( "narcrev2.u36", 0x30000, 0x10000, CRC(16cdbb13) SHA1(2dfd961a5d909c1804f4fda34de33ee2664c4bc6) )
r14963	r14964
1227	1238
1228	1239
1229	1240	ROM_START( narc3 )
1230		ROM_REGION( 0x90000, "narc1cpu", 0 )   /* sound CPU */
	1241	ROM_REGION( 0x90000, "narcsnd:cpu0", 0 )   /* sound CPU */
1231	1242	ROM_LOAD( "narcrev2.u4", 0x50000, 0x10000, CRC(450a591a) SHA1(bbda8061262738e5866f2707f69483a0a51d2910) )
1232	1243	ROM_RELOAD(              0x60000, 0x10000 )
1233	1244	ROM_LOAD( "narcrev2.u5", 0x70000, 0x10000, CRC(e551e5e3) SHA1(c8b4f53dbd4c534abb77d4dc07c4d12653b79894) )
1234	1245	ROM_RELOAD(              0x80000, 0x10000 )
1235	1246
1236		ROM_REGION( 0x90000, "narc2cpu", 0 )   /* slave sound CPU */
	1247	ROM_REGION( 0x90000, "narcsnd:cpu1", 0 )   /* slave sound CPU */
1237	1248	ROM_LOAD( "narcrev2.u35", 0x10000, 0x10000, CRC(81295892) SHA1(159664e5ee03c88d6e940e70e87e2150dc5b8b25) )
1238	1249	ROM_RELOAD(               0x20000, 0x10000 )
1239	1250	ROM_LOAD( "narcrev2.u36", 0x30000, 0x10000, CRC(16cdbb13) SHA1(2dfd961a5d909c1804f4fda34de33ee2664c4bc6) )
r14963	r14964
1328	1339	ROM_END
1329	1340
1330	1341	ROM_START( narc2 )
1331		ROM_REGION( 0x90000, "narc1cpu", 0 )   /* sound CPU */
	1342	ROM_REGION( 0x90000, "narcsnd:cpu0", 0 )   /* sound CPU */
1332	1343	ROM_LOAD( "narcrev2.u4", 0x50000, 0x10000, CRC(450a591a) SHA1(bbda8061262738e5866f2707f69483a0a51d2910) )
1333	1344	ROM_RELOAD(              0x60000, 0x10000 )
1334	1345	ROM_LOAD( "narcrev2.u5", 0x70000, 0x10000, CRC(e551e5e3) SHA1(c8b4f53dbd4c534abb77d4dc07c4d12653b79894) )
1335	1346	ROM_RELOAD(              0x80000, 0x10000 )
1336	1347
1337		ROM_REGION( 0x90000, "narc2cpu", 0 )   /* slave sound CPU */
	1348	ROM_REGION( 0x90000, "narcsnd:cpu1", 0 )   /* slave sound CPU */
1338	1349	ROM_LOAD( "narcrev2.u35", 0x10000, 0x10000, CRC(81295892) SHA1(159664e5ee03c88d6e940e70e87e2150dc5b8b25) )
1339	1350	ROM_RELOAD(               0x20000, 0x10000 )
1340	1351	ROM_LOAD( "narcrev2.u36", 0x30000, 0x10000, CRC(16cdbb13) SHA1(2dfd961a5d909c1804f4fda34de33ee2664c4bc6) )
r14963	r14964
1430	1441
1431	1442
1432	1443	ROM_START( trog )
1433		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1444	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1434	1445	ROM_LOAD (   "trogu4.bin", 0x10000, 0x10000, CRC(759d0bf4) SHA1(c4c3fa51c43cf7fd241ac1f33d7d220aa9f9edb3) )
1435	1446	ROM_RELOAD(                0x20000, 0x10000 )
1436	1447	ROM_LOAD (  "trogu19.bin", 0x30000, 0x10000, CRC(960c333d) SHA1(da8ce8dfffffe7a2d60b3f75cc5aa88e5e2be659) )
r14963	r14964
1460	1471
1461	1472
1462	1473	ROM_START( trog4 )
1463		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1474	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1464	1475	ROM_LOAD (   "trogu4.bin", 0x10000, 0x10000, CRC(759d0bf4) SHA1(c4c3fa51c43cf7fd241ac1f33d7d220aa9f9edb3) )
1465	1476	ROM_RELOAD(                0x20000, 0x10000 )
1466	1477	ROM_LOAD (  "trogu19.bin", 0x30000, 0x10000, CRC(960c333d) SHA1(da8ce8dfffffe7a2d60b3f75cc5aa88e5e2be659) )
r14963	r14964
1490	1501
1491	1502
1492	1503	ROM_START( trog3 )
1493		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1504	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1494	1505	ROM_LOAD (   "trogu4.bin", 0x10000, 0x10000, CRC(759d0bf4) SHA1(c4c3fa51c43cf7fd241ac1f33d7d220aa9f9edb3) )
1495	1506	ROM_RELOAD(                0x20000, 0x10000 )
1496	1507	ROM_LOAD (  "trogu19.bin", 0x30000, 0x10000, CRC(960c333d) SHA1(da8ce8dfffffe7a2d60b3f75cc5aa88e5e2be659) )
r14963	r14964
1520	1531
1521	1532
1522	1533	ROM_START( trogpa6 )
1523		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1534	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1524	1535	ROM_LOAD (   "trogu4.bin", 0x10000, 0x10000, CRC(759d0bf4) SHA1(c4c3fa51c43cf7fd241ac1f33d7d220aa9f9edb3) )
1525	1536	ROM_RELOAD(                0x20000, 0x10000 )
1526	1537	ROM_LOAD (  "trogu19.bin", 0x30000, 0x10000, CRC(960c333d) SHA1(da8ce8dfffffe7a2d60b3f75cc5aa88e5e2be659) )
r14963	r14964
1550	1561
1551	1562
1552	1563	ROM_START( trogpa4 )
1553		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1564	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1554	1565	ROM_LOAD (   "trogu4.bin", 0x10000, 0x10000, CRC(759d0bf4) SHA1(c4c3fa51c43cf7fd241ac1f33d7d220aa9f9edb3) )
1555	1566	ROM_RELOAD(                0x20000, 0x10000 )
1556	1567	ROM_LOAD (  "trogu19.bin", 0x30000, 0x10000, CRC(960c333d) SHA1(da8ce8dfffffe7a2d60b3f75cc5aa88e5e2be659) )
r14963	r14964
1580	1591
1581	1592
1582	1593	ROM_START( smashtv )
1583		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1594	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1584	1595	ROM_LOAD (  "sl2.u4", 0x10000, 0x10000, CRC(29d3f6c8) SHA1(8a90cdff54f59ddb7dba521504d880515a59df08) )
1585	1596	ROM_RELOAD(           0x20000, 0x10000 )
1586	1597	ROM_LOAD ( "sl2.u19", 0x30000, 0x10000, CRC(ac5a402a) SHA1(c476018062126dc3936caa2c328de490737165ec) )
r14963	r14964
1608	1619
1609	1620
1610	1621	ROM_START( smashtv6 )
1611		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1622	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1612	1623	ROM_LOAD (  "sl2.u4", 0x10000, 0x10000, CRC(29d3f6c8) SHA1(8a90cdff54f59ddb7dba521504d880515a59df08) )
1613	1624	ROM_RELOAD(           0x20000, 0x10000 )
1614	1625	ROM_LOAD ( "sl2.u19", 0x30000, 0x10000, CRC(ac5a402a) SHA1(c476018062126dc3936caa2c328de490737165ec) )
r14963	r14964
1636	1647
1637	1648
1638	1649	ROM_START( smashtv5 )
1639		ROM_REGION( 0x90000, "cvsdcpu", 0 ) /* sound CPU */
	1650	ROM_REGION( 0x90000, "cvsd:cpu", 0 ) /* sound CPU */
1640	1651	ROM_LOAD (  "sl2.u4", 0x10000, 0x10000, CRC(29d3f6c8) SHA1(8a90cdff54f59ddb7dba521504d880515a59df08) )
1641	1652	ROM_RELOAD(           0x20000, 0x10000 )
1642	1653	ROM_LOAD ( "sl2.u19", 0x30000, 0x10000, CRC(ac5a402a) SHA1(c476018062126dc3936caa2c328de490737165ec) )
r14963	r14964
1664	1675
1665	1676
1666	1677	ROM_START( smashtv4 )
1667		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1678	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1668	1679	ROM_LOAD (  "sl2.u4", 0x10000, 0x10000, CRC(29d3f6c8) SHA1(8a90cdff54f59ddb7dba521504d880515a59df08) )
1669	1680	ROM_RELOAD(           0x20000, 0x10000 )
1670	1681	ROM_LOAD ( "sl2.u19", 0x30000, 0x10000, CRC(ac5a402a) SHA1(c476018062126dc3936caa2c328de490737165ec) )
r14963	r14964
1692	1703
1693	1704
1694	1705	ROM_START( smashtv3 )
1695		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1706	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1696	1707	ROM_LOAD (  "sl2.u4", 0x10000, 0x10000, CRC(29d3f6c8) SHA1(8a90cdff54f59ddb7dba521504d880515a59df08) )
1697	1708	ROM_RELOAD(           0x20000, 0x10000 )
1698	1709	ROM_LOAD ( "sl2.u19", 0x30000, 0x10000, CRC(ac5a402a) SHA1(c476018062126dc3936caa2c328de490737165ec) )
r14963	r14964
1720	1731
1721	1732
1722	1733	ROM_START( hiimpact )
1723		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1734	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1724	1735	ROM_LOAD (  "sl1u4.bin", 0x10000, 0x20000, CRC(28effd6a) SHA1(4a839f15e1b453a22fdef7b1801b8cc5cfdf3c29) )
1725	1736	ROM_LOAD ( "sl1u19.bin", 0x30000, 0x20000, CRC(0ea22c89) SHA1(6d4579f6b10cac685be01348451b3537a0626034) )
1726	1737	ROM_LOAD ( "sl1u20.bin", 0x50000, 0x20000, CRC(4e747ab5) SHA1(82040f40aac7dae577376a742eadaaa9644500c1) )
r14963	r14964
1755	1766
1756	1767
1757	1768	ROM_START( hiimpact4 )
1758		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1769	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1759	1770	ROM_LOAD (  "sl1u4.bin", 0x10000, 0x20000, CRC(28effd6a) SHA1(4a839f15e1b453a22fdef7b1801b8cc5cfdf3c29) )
1760	1771	ROM_LOAD ( "sl1u19.bin", 0x30000, 0x20000, CRC(0ea22c89) SHA1(6d4579f6b10cac685be01348451b3537a0626034) )
1761	1772	ROM_LOAD ( "sl1u20.bin", 0x50000, 0x20000, CRC(4e747ab5) SHA1(82040f40aac7dae577376a742eadaaa9644500c1) )
r14963	r14964
1790	1801
1791	1802
1792	1803	ROM_START( hiimpact3 )
1793		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1804	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1794	1805	ROM_LOAD (  "sl1u4.bin", 0x10000, 0x20000, CRC(28effd6a) SHA1(4a839f15e1b453a22fdef7b1801b8cc5cfdf3c29) )
1795	1806	ROM_LOAD ( "sl1u19.bin", 0x30000, 0x20000, CRC(0ea22c89) SHA1(6d4579f6b10cac685be01348451b3537a0626034) )
1796	1807	ROM_LOAD ( "sl1u20.bin", 0x50000, 0x20000, CRC(4e747ab5) SHA1(82040f40aac7dae577376a742eadaaa9644500c1) )
r14963	r14964
1825	1836
1826	1837
1827	1838	ROM_START( hiimpact2 )
1828		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1839	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1829	1840	ROM_LOAD (  "sl1u4.bin", 0x10000, 0x20000, CRC(28effd6a) SHA1(4a839f15e1b453a22fdef7b1801b8cc5cfdf3c29) )
1830	1841	ROM_LOAD ( "sl1u19.bin", 0x30000, 0x20000, CRC(0ea22c89) SHA1(6d4579f6b10cac685be01348451b3537a0626034) )
1831	1842	ROM_LOAD ( "sl1u20.bin", 0x50000, 0x20000, CRC(4e747ab5) SHA1(82040f40aac7dae577376a742eadaaa9644500c1) )
r14963	r14964
1860	1871
1861	1872
1862	1873	ROM_START( hiimpact1 )
1863		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1874	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1864	1875	ROM_LOAD (  "sl1u4.bin", 0x10000, 0x20000, CRC(28effd6a) SHA1(4a839f15e1b453a22fdef7b1801b8cc5cfdf3c29) )
1865	1876	ROM_LOAD ( "sl1u19.bin", 0x30000, 0x20000, CRC(0ea22c89) SHA1(6d4579f6b10cac685be01348451b3537a0626034) )
1866	1877	ROM_LOAD ( "sl1u20.bin", 0x50000, 0x20000, CRC(4e747ab5) SHA1(82040f40aac7dae577376a742eadaaa9644500c1) )
r14963	r14964
1895	1906
1896	1907
1897	1908	ROM_START( hiimpactp )
1898		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1909	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1899	1910	ROM_LOAD (  "sl1u4.bin", 0x10000, 0x20000, CRC(28effd6a) SHA1(4a839f15e1b453a22fdef7b1801b8cc5cfdf3c29) )
1900	1911	ROM_LOAD ( "sl1u19.bin", 0x30000, 0x20000, CRC(0ea22c89) SHA1(6d4579f6b10cac685be01348451b3537a0626034) )
1901	1912	ROM_LOAD ( "sl1u20.bin", 0x50000, 0x20000, CRC(4e747ab5) SHA1(82040f40aac7dae577376a742eadaaa9644500c1) )
r14963	r14964
1930	1941
1931	1942
1932	1943	ROM_START( shimpact )
1933		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1944	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1934	1945	ROM_LOAD (   "shiu4.bin", 0x10000, 0x20000, CRC(1e5a012c) SHA1(4077fc266799a01738b7f88e867535f1fbacd557) )
1935	1946	ROM_LOAD (  "shiu19.bin", 0x30000, 0x20000, CRC(10f9684e) SHA1(1fdc5364f87fb65f4f2a438841e0fe847f765aaf) )
1936	1947	ROM_LOAD (  "shiu20.bin", 0x50000, 0x20000, CRC(1b4a71c1) SHA1(74b7b4ae76ebe65f1f46b2117970bfefefbb5344) )
r14963	r14964
1958	1969
1959	1970
1960	1971	ROM_START( shimpactp6 )
1961		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	1972	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1962	1973	ROM_LOAD (   "shiu4.bin", 0x10000, 0x20000, CRC(1e5a012c) SHA1(4077fc266799a01738b7f88e867535f1fbacd557) )
1963	1974	ROM_LOAD (  "shiu19.bin", 0x30000, 0x20000, CRC(10f9684e) SHA1(1fdc5364f87fb65f4f2a438841e0fe847f765aaf) )
1964	1975	ROM_LOAD (  "shiu20.bin", 0x50000, 0x20000, CRC(1b4a71c1) SHA1(74b7b4ae76ebe65f1f46b2117970bfefefbb5344) )
r14963	r14964
1986	1997
1987	1998
1988	1999	ROM_START( shimpactp5 )
1989		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	2000	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
1990	2001	ROM_LOAD (   "shiu4.bin", 0x10000, 0x20000, CRC(1e5a012c) SHA1(4077fc266799a01738b7f88e867535f1fbacd557) )
1991	2002	ROM_LOAD (  "shiu19.bin", 0x30000, 0x20000, CRC(10f9684e) SHA1(1fdc5364f87fb65f4f2a438841e0fe847f765aaf) )
1992	2003	ROM_LOAD (  "shiu20.bin", 0x50000, 0x20000, CRC(1b4a71c1) SHA1(74b7b4ae76ebe65f1f46b2117970bfefefbb5344) )
r14963	r14964
2014	2025
2015	2026
2016	2027	ROM_START( shimpactp4 ) /* You must manualy reset the high score table or game will hang after initial demo screen, it's best to do a "Full Factory Restore" */
2017		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	2028	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
2018	2029	ROM_LOAD (   "shiu4.bin", 0x10000, 0x20000, CRC(1e5a012c) SHA1(4077fc266799a01738b7f88e867535f1fbacd557) )
2019	2030	ROM_LOAD (  "shiu19.bin", 0x30000, 0x20000, CRC(10f9684e) SHA1(1fdc5364f87fb65f4f2a438841e0fe847f765aaf) )
2020	2031	ROM_LOAD (  "shiu20.bin", 0x50000, 0x20000, CRC(1b4a71c1) SHA1(74b7b4ae76ebe65f1f46b2117970bfefefbb5344) )
r14963	r14964
2042	2053
2043	2054
2044	2055	ROM_START( strkforc )
2045		ROM_REGION( 0x90000, "cvsdcpu", 0 )   /* sound CPU */
	2056	ROM_REGION( 0x90000, "cvsd:cpu", 0 )   /* sound CPU */
2046	2057	ROM_LOAD (  "sfu4.bin", 0x10000, 0x10000, CRC(8f747312) SHA1(729929c209741e72eb83b407cf95d7709ec1b5ae) )
2047	2058	ROM_RELOAD(             0x20000, 0x10000 )
2048	2059	ROM_LOAD ( "sfu19.bin", 0x30000, 0x10000, CRC(afb29926) SHA1(ad904c0968a90b8187cc87d6c171fbc021d2f66f) )
r14963	r14964
2074	2085
2075	2086
2076	2087	ROM_START( mkla4 )
2077		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2088	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2078	2089	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2079	2090
2080		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2091	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2081	2092	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2082	2093	ROM_RELOAD(               0x40000, 0x40000 )
2083	2094	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2106	2117
2107	2118
2108	2119	ROM_START( mkla3 )
2109		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2120	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2110	2121	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2111	2122
2112		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2123	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2113	2124	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2114	2125	ROM_RELOAD(               0x40000, 0x40000 )
2115	2126	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2138	2149
2139	2150
2140	2151	ROM_START( mkla2 )
2141		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2152	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2142	2153	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2143	2154
2144		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2155	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2145	2156	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2146	2157	ROM_RELOAD(               0x40000, 0x40000 )
2147	2158	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2170	2181
2171	2182
2172	2183	ROM_START( mkla1 )
2173		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2184	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2174	2185	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2175	2186
2176		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2187	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2177	2188	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2178	2189	ROM_RELOAD(               0x40000, 0x40000 )
2179	2190	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2202	2213
2203	2214
2204	2215	ROM_START( mkprot9 )
2205		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2216	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2206	2217	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2207	2218
2208		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2219	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2209	2220	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2210	2221	ROM_RELOAD(               0x40000, 0x40000 )
2211	2222	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2234	2245
2235	2246
2236	2247	ROM_START( mkprot8 )
2237		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2248	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2238	2249	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2239	2250
2240		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2251	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2241	2252	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2242	2253	ROM_RELOAD(               0x40000, 0x40000 )
2243	2254	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2265	2276	ROM_END
2266	2277
2267	2278	ROM_START( mkprot4 )
2268		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2279	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2269	2280	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2270	2281
2271		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2282	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2272	2283	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2273	2284	ROM_RELOAD(               0x40000, 0x40000 )
2274	2285	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2296	2307	ROM_END
2297	2308
2298	2309	ROM_START( mkyturbo )
2299		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2310	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2300	2311	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2301	2312
2302		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2313	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2303	2314	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2304	2315	ROM_RELOAD(               0x40000, 0x40000 )
2305	2316	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2328	2339	ROM_END
2329	2340
2330	2341	ROM_START( mkyturboe )
2331		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2342	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2332	2343	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2333	2344
2334		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2345	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2335	2346	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2336	2347	ROM_RELOAD(               0x40000, 0x40000 )
2337	2348	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2359	2370	ROM_END
2360	2371
2361	2372	ROM_START( mknifty )
2362		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2373	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2363	2374	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2364	2375
2365		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2376	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2366	2377	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2367	2378	ROM_RELOAD(               0x40000, 0x40000 )
2368	2379	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2390	2401	ROM_END
2391	2402
2392	2403	ROM_START( mknifty666 )
2393		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2404	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2394	2405	ROM_LOAD (  "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
2395	2406
2396		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2407	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2397	2408	ROM_LOAD ( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
2398	2409	ROM_RELOAD(               0x40000, 0x40000 )
2399	2410	ROM_LOAD ( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
2486	2497
2487	2498
2488	2499	ROM_START( term2 )
2489		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2500	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2490	2501	ROM_LOAD (  "t2_snd.3", 0x10000, 0x20000, CRC(73c3f5c4) SHA1(978dd974590e77294dbe9a647aebd3d24af6397f) )
2491	2502	ROM_RELOAD (            0x30000, 0x20000 )
2492	2503
2493		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2504	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2494	2505	ROM_LOAD ( "t2_snd.12", 0x00000, 0x40000, CRC(e192a40d) SHA1(1f7a0e282c0c8eb66cbe514128bd104433e53b7a) )
2495	2506	ROM_RELOAD(             0x40000, 0x40000 )
2496	2507	ROM_LOAD ( "t2_snd.13", 0x80000, 0x40000, CRC(956fa80b) SHA1(02ab504627f4b25a394fa4192bb134138cbf6a4f) )
r14963	r14964
2519	2530
2520	2531
2521	2532	ROM_START( term2la3 )
2522		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2533	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2523	2534	ROM_LOAD (  "t2_snd.3", 0x10000, 0x20000, CRC(73c3f5c4) SHA1(978dd974590e77294dbe9a647aebd3d24af6397f) )
2524	2535	ROM_RELOAD (            0x30000, 0x20000 )
2525	2536
2526		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2537	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2527	2538	ROM_LOAD ( "t2_snd.12", 0x00000, 0x40000, CRC(e192a40d) SHA1(1f7a0e282c0c8eb66cbe514128bd104433e53b7a) )
2528	2539	ROM_RELOAD(             0x40000, 0x40000 )
2529	2540	ROM_LOAD ( "t2_snd.13", 0x80000, 0x40000, CRC(956fa80b) SHA1(02ab504627f4b25a394fa4192bb134138cbf6a4f) )
r14963	r14964
2552	2563
2553	2564
2554	2565	ROM_START( term2la2 )
2555		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2566	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2556	2567	ROM_LOAD (  "t2_snd.3", 0x10000, 0x20000, CRC(73c3f5c4) SHA1(978dd974590e77294dbe9a647aebd3d24af6397f) )
2557	2568	ROM_RELOAD (            0x30000, 0x20000 )
2558	2569
2559		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2570	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2560	2571	ROM_LOAD ( "t2_snd.12", 0x00000, 0x40000, CRC(e192a40d) SHA1(1f7a0e282c0c8eb66cbe514128bd104433e53b7a) )
2561	2572	ROM_RELOAD(             0x40000, 0x40000 )
2562	2573	ROM_LOAD ( "t2_snd.13", 0x80000, 0x40000, CRC(956fa80b) SHA1(02ab504627f4b25a394fa4192bb134138cbf6a4f) )
r14963	r14964
2585	2596
2586	2597
2587	2598	ROM_START( term2la1 )
2588		ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	2599	ROM_REGION( 0x50000, "adpcm:cpu", 0 ) /* sound CPU */
2589	2600	ROM_LOAD ( "t2_snd.3", 0x10000, 0x20000, CRC(73c3f5c4) SHA1(978dd974590e77294dbe9a647aebd3d24af6397f) )
2590	2601	ROM_RELOAD ( 0x30000, 0x20000 )
2591	2602
2592		ROM_REGION( 0x200000, "oki", 0 ) /* ADPCM */
	2603	ROM_REGION( 0x100000, "adpcm:oki", 0 ) /* ADPCM */
2593	2604	ROM_LOAD ( "t2_snd.12", 0x00000, 0x40000, CRC(e192a40d) SHA1(1f7a0e282c0c8eb66cbe514128bd104433e53b7a) )
2594	2605	ROM_RELOAD(             0x40000, 0x40000 )
2595	2606	ROM_LOAD ( "t2_snd.13", 0x80000, 0x40000, CRC(956fa80b) SHA1(02ab504627f4b25a394fa4192bb134138cbf6a4f) )
r14963	r14964
2618	2629
2619	2630
2620	2631	ROM_START( totcarn )
2621		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2632	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2622	2633	ROM_LOAD (  "tcu3.bin", 0x10000, 0x20000, CRC(5bdb4665) SHA1(c6b90b914785b8703790957cc4bb4983a332fba6) )
2623	2634	ROM_RELOAD (            0x30000, 0x20000 )
2624	2635
2625		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2636	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2626	2637	ROM_LOAD ( "tcu12.bin", 0x00000, 0x40000, CRC(d0000ac7) SHA1(2d476c7727462623feb2f1a23fb797eaeed5ce30) )
2627	2638	ROM_RELOAD(             0x40000, 0x40000 )
2628	2639	ROM_LOAD ( "tcu13.bin", 0x80000, 0x40000, CRC(e48e6f0c) SHA1(bf7d548b6b1901966f99c815129ea160ef36f024) )
r14963	r14964
2651	2662
2652	2663
2653	2664	ROM_START( totcarnp )
2654		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	2665	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
2655	2666	ROM_LOAD (  "tcu3.bin", 0x10000, 0x20000, CRC(5bdb4665) SHA1(c6b90b914785b8703790957cc4bb4983a332fba6) )
2656	2667	ROM_RELOAD (            0x30000, 0x20000 )
2657	2668
2658		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	2669	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
2659	2670	ROM_LOAD ( "tcu12.bin", 0x00000, 0x40000, CRC(d0000ac7) SHA1(2d476c7727462623feb2f1a23fb797eaeed5ce30) )
2660	2671	ROM_RELOAD(             0x40000, 0x40000 )
2661	2672	ROM_LOAD ( "tcu13.bin", 0x80000, 0x40000, CRC(e48e6f0c) SHA1(bf7d548b6b1901966f99c815129ea160ef36f024) )

src/mame/drivers/midtunit.c

r14963	r14964
22	22	#include "emu.h"
23	23	#include "cpu/tms34010/tms34010.h"
24	24	#include "cpu/adsp2100/adsp2100.h"
25		#include "audio/williams.h"
26		#include "audio/dcs.h"
27	25	#include "machine/nvram.h"
28	26	#include "includes/midtunit.h"
29	27
r14963	r14964
626	624	static MACHINE_CONFIG_DERIVED( tunit_adpcm, tunit_core )
627	625
628	626	/* basic machine hardware */
629		MCFG_FRAGMENT_ADD(williams_adpcm_sound)
	627	MCFG_SPEAKER_STANDARD_MONO("mono")
	628	MCFG_WILLIAMS_ADPCM_SOUND_ADD("adpcm")
	629	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
630	630	MACHINE_CONFIG_END
631	631
632	632
r14963	r14964
645	645	*************************************/
646	646
647	647	ROM_START( mk )
648		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	648	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
649	649	ROM_LOAD( "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
650	650
651		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	651	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
652	652	ROM_LOAD( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
653	653	ROM_RELOAD(              0x40000, 0x40000 )
654	654	ROM_LOAD( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
678	678
679	679
680	680	ROM_START( mkr4 )
681		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	681	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
682	682	ROM_LOAD( "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
683	683
684		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	684	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
685	685	ROM_LOAD( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
686	686	ROM_RELOAD(              0x40000, 0x40000 )
687	687	ROM_LOAD( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
711	711
712	712
713	713	ROM_START( mktturbo )
714		ROM_REGION( 0x50000, "adpcm", 0 )   /* sound CPU */
	714	ROM_REGION( 0x50000, "adpcm:cpu", 0 )   /* sound CPU */
715	715	ROM_LOAD( "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
716	716
717		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	717	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
718	718	ROM_LOAD( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
719	719	ROM_RELOAD(              0x40000, 0x40000 )
720	720	ROM_LOAD( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
r14963	r14964
1166	1166
1167	1167
1168	1168	ROM_START( nbajam )
1169		ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	1169	ROM_REGION( 0x50000, "adpcm:cpu", 0 ) /* sound CPU */
1170	1170	ROM_LOAD(  "nbau3.bin", 0x010000, 0x20000, CRC(3a3ea480) SHA1(d12a45cba5c35f046b176661d7877fa4fd0e6c13) )
1171	1171	ROM_RELOAD(             0x030000, 0x20000 )
1172	1172
1173		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	1173	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
1174	1174	ROM_LOAD( "nbau12.bin", 0x000000, 0x80000, CRC(b94847f1) SHA1(e7efa0a379bfa91fe4ffb75f07a5dfbfde9a96b4) )
1175	1175	ROM_LOAD( "nbau13.bin", 0x080000, 0x80000, CRC(b6fe24bd) SHA1(f70f75b5570a2b368ebc74d2a7d264c618940430) )
1176	1176
r14963	r14964
1202	1202
1203	1203
1204	1204	ROM_START( nbajamr2 )
1205		ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	1205	ROM_REGION( 0x50000, "adpcm:cpu", 0 ) /* sound CPU */
1206	1206	ROM_LOAD(  "nbau3.bin", 0x010000, 0x20000, CRC(3a3ea480) SHA1(d12a45cba5c35f046b176661d7877fa4fd0e6c13) )
1207	1207	ROM_RELOAD(             0x030000, 0x20000 )
1208	1208
1209		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	1209	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
1210	1210	ROM_LOAD( "nbau12.bin", 0x000000, 0x80000, CRC(b94847f1) SHA1(e7efa0a379bfa91fe4ffb75f07a5dfbfde9a96b4) )
1211	1211	ROM_LOAD( "nbau13.bin", 0x080000, 0x80000, CRC(b6fe24bd) SHA1(f70f75b5570a2b368ebc74d2a7d264c618940430) )
1212	1212
r14963	r14964
1238	1238
1239	1239
1240	1240	ROM_START( nbajamte )
1241		ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	1241	ROM_REGION( 0x50000, "adpcm:cpu", 0 ) /* sound CPU */
1242	1242	ROM_LOAD(  "te-u3.bin", 0x010000, 0x20000, CRC(d4551195) SHA1(e8908fbe4339fb8c93f7e74113dfd25dda1667ea) )
1243	1243	ROM_RELOAD(             0x030000, 0x20000 )
1244	1244
1245		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	1245	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
1246	1246	ROM_LOAD( "te-u12.bin", 0x000000, 0x80000, CRC(4fac97bc) SHA1(bd88d8c3edab0e35ad9f9350bcbaa17cda61d87a) )
1247	1247	ROM_LOAD( "te-u13.bin", 0x080000, 0x80000, CRC(6f27b202) SHA1(c1f0db15624d1e7102ce9fd1db49ccf86e8611d6) )
1248	1248
r14963	r14964
1274	1274
1275	1275
1276	1276	ROM_START( nbajamt1 )
1277		ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	1277	ROM_REGION( 0x50000, "adpcm:cpu", 0 ) /* sound CPU */
1278	1278	ROM_LOAD(  "te-u3.bin", 0x010000, 0x20000, CRC(d4551195) SHA1(e8908fbe4339fb8c93f7e74113dfd25dda1667ea) )
1279	1279	ROM_RELOAD(             0x030000, 0x20000 )
1280	1280
1281		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	1281	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
1282	1282	ROM_LOAD( "te-u12.bin", 0x000000, 0x80000, CRC(4fac97bc) SHA1(bd88d8c3edab0e35ad9f9350bcbaa17cda61d87a) )
1283	1283	ROM_LOAD( "te-u13.bin", 0x080000, 0x80000, CRC(6f27b202) SHA1(c1f0db15624d1e7102ce9fd1db49ccf86e8611d6) )
1284	1284
r14963	r14964
1310	1310
1311	1311
1312	1312	ROM_START( nbajamt2 )
1313		ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	1313	ROM_REGION( 0x50000, "adpcm:cpu", 0 ) /* sound CPU */
1314	1314	ROM_LOAD(  "te-u3.bin", 0x010000, 0x20000, CRC(d4551195) SHA1(e8908fbe4339fb8c93f7e74113dfd25dda1667ea) )
1315	1315	ROM_RELOAD(             0x030000, 0x20000 )
1316	1316
1317		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	1317	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
1318	1318	ROM_LOAD( "te-u12.bin", 0x000000, 0x80000, CRC(4fac97bc) SHA1(bd88d8c3edab0e35ad9f9350bcbaa17cda61d87a) )
1319	1319	ROM_LOAD( "te-u13.bin", 0x080000, 0x80000, CRC(6f27b202) SHA1(c1f0db15624d1e7102ce9fd1db49ccf86e8611d6) )
1320	1320
r14963	r14964
1346	1346
1347	1347
1348	1348	ROM_START( nbajamt3 )
1349		ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	1349	ROM_REGION( 0x50000, "adpcm:cpu", 0 ) /* sound CPU */
1350	1350	ROM_LOAD(  "te-u3.bin", 0x010000, 0x20000, CRC(d4551195) SHA1(e8908fbe4339fb8c93f7e74113dfd25dda1667ea) )
1351	1351	ROM_RELOAD(             0x030000, 0x20000 )
1352	1352
1353		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	1353	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
1354	1354	ROM_LOAD( "te-u12.bin", 0x000000, 0x80000, CRC(4fac97bc) SHA1(bd88d8c3edab0e35ad9f9350bcbaa17cda61d87a) )
1355	1355	ROM_LOAD( "te-u13.bin", 0x080000, 0x80000, CRC(6f27b202) SHA1(c1f0db15624d1e7102ce9fd1db49ccf86e8611d6) )
1356	1356
r14963	r14964
1382	1382
1383	1383
1384	1384	ROM_START( nbajamtn )
1385		ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	1385	ROM_REGION( 0x50000, "adpcm:cpu", 0 ) /* sound CPU */
1386	1386	ROM_LOAD(  "te-u3.bin", 0x010000, 0x20000, CRC(d4551195) SHA1(e8908fbe4339fb8c93f7e74113dfd25dda1667ea) )
1387	1387	ROM_RELOAD(             0x030000, 0x20000 )
1388	1388
1389		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	1389	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
1390	1390	ROM_LOAD( "te-u12.bin", 0x000000, 0x80000, CRC(4fac97bc) SHA1(bd88d8c3edab0e35ad9f9350bcbaa17cda61d87a) )
1391	1391	ROM_LOAD( "te-u13.bin", 0x080000, 0x80000, CRC(6f27b202) SHA1(c1f0db15624d1e7102ce9fd1db49ccf86e8611d6) )
1392	1392
r14963	r14964
1418	1418
1419	1419
1420	1420	ROM_START( jdreddp )
1421		ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	1421	ROM_REGION( 0x50000, "adpcm:cpu", 0 ) /* sound CPU */
1422	1422	ROM_LOAD(  "jd_u3.rom", 0x010000, 0x20000, CRC(6154d108) SHA1(54328455ec22ba815de85aa3bfe6405353c64f5c) )
1423	1423	ROM_RELOAD(             0x030000, 0x20000 )
1424	1424
1425		ROM_REGION( 0x200000, "oki", 0 )   /* ADPCM */
	1425	ROM_REGION( 0x100000, "adpcm:oki", 0 )   /* ADPCM */
1426	1426	ROM_LOAD( "jd_u12.rom", 0x000000, 0x80000, CRC(ef32f202) SHA1(16aea085e63496dec259291de1a64fbeab52f039) )
1427	1427	ROM_LOAD( "jd_u13.rom", 0x080000, 0x80000, CRC(3dc70473) SHA1(a3d7210301ff0579889009a075092115d9bf0600) )
1428	1428

src/mame/drivers/tmmjprd.c

r14963	r14964
20	20	- tmpdoki isn't a dual screen game, we should remove the dual screen layout from VIDEO_UPDATE and from the MACHINE_DRIVER, also notice that MAME
21	21	doesn't have a macro for removing previously declared screens.
22	22
23		- sound (see rabbit.c for preliminary details, not copied here)
24
25	23	- sprites from one screen are overlapping on the other, probably there's a way to limit them to a single screen
26	24
27	25	- priority is wrong.

src/mame/drivers/sigmab98.c

r14963	r14964
2114	2114	memory_configure_bank(machine, "rambank", 1, 4, bankedram, 0x1000);
2115	2115	memory_set_bank(machine, "rambank", 0);
2116	2116
2117		//state->m_spriteram = auto_alloc_array(machine, UINT8, 0x1000 * 5);
2118		//memset(state->m_spriteram, 0, 0x1000 * 5);
2119		//state->m_spriteram_size = 0x1000;
	2117	state->m_spriteram.allocate(0x1000 * 5);
	2118	memset(state->m_spriteram, 0, 0x1000 * 5);
2120	2119	memory_configure_bank(machine, "sprbank", 0, 5, state->m_spriteram, 0x1000);
2121	2120	memory_set_bank(machine, "sprbank", 0);
2122	2121
r14963	r14964
2162	2161	memory_set_bankptr(machine, "palbank", state->m_generic_paletteram_8);
2163	2162	state->m_rambank = 0x64;
2164	2163
2165		//state->m_spriteram = auto_alloc_array(machine, UINT8, 0x1000 * 5);
2166		//memset(state->m_spriteram, 0, 0x1000 * 5);
2167		//state->m_spriteram_size = 0x1000;
	2164	state->m_spriteram.allocate(0x1000 * 5);
	2165	memset(state->m_spriteram, 0, 0x1000 * 5);
2168	2166	memory_set_bankptr(machine, "sprbank0",  state->m_spriteram + 0x1000*4);   // scratch
2169	2167	memory_set_bankptr(machine, "sprbank1",  state->m_spriteram + 0x1000*4);   // scratch
2170	2168
r14963	r14964
2274	2272	state->m_generic_paletteram_8.allocate(0x200);
2275	2273	memset(state->m_generic_paletteram_8, 0, 0x200);
2276	2274
2277		//state->m_spriteram = auto_alloc_array(machine, UINT8, 0x1000);
2278		//memset(state->m_spriteram, 0, 0x1000);
2279		//state->m_spriteram_size = 0x1000;
	2275	state->m_spriteram.allocate(0x1000);
	2276	memset(state->m_spriteram, 0, 0x1000);
2280	2277
2281	2278	state->m_rombank = 0x65;
2282	2279	state->m_rambank = 0x53;

src/mame/drivers/dbz.c

r14963	r14964
274	274
275	275	static const ym2151_interface ym2151_config =
276	276	{
277		dbz_sound_irq
	277	DEVCB_LINE(dbz_sound_irq)
278	278	};
279	279
280	280	/**********************************************************************************/

src/mame/drivers/bfm_sc4.c

r14963	r14964
11	11	This file contains the set lists only, for the actual hardware
12	12	emulation see bfm_sc4h.c
13	13
	14
	15	note: default Jackpot keys are set to whatever value the game
	16	mentions it should be using with none present, many
	17	games accept multiple keys
	18
14	19	*/
15	20
16	21	#include "emu.h"
r14963	r14964
9941	9946	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
9942	9947	ROM_LOAD16_BYTE( "95400861.lo", 0x00001, 0x080000, CRC(e4949979) SHA1(a00bcd8c839b14b9e1e4b21a8c78a9be789e0cf7) )
9943	9948	ROM_LOAD16_BYTE( "95400862.hi", 0x00000, 0x080000, CRC(b1cd18f0) SHA1(b34a7d5595d3abad45e0cd027c217ac5b2bb3088) )
9944		sc_pacmn_others
	9949	PACMAN_SOUNDS
9945	9950	ROM_END
9946	9951
9947	9952	ROM_START( sc4pacmna )
9948	9953	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
9949	9954	ROM_LOAD16_BYTE( "95402111.lo", 0x00001, 0x080000, CRC(e88b337a) SHA1(ecf7c3fb5e68fba9cbccada502022ae942992699) )
9950	9955	ROM_LOAD16_BYTE( "95402112.hi", 0x00000, 0x080000, CRC(1f17de1d) SHA1(6576f40cf4dc8fd3de1fd121d5a4c19536da87c5) )
9951		sc_pacmn_others
	9956	PACMAN_SOUNDS
9952	9957	ROM_END
9953	9958
9954	9959	ROM_START( sc4pacmnb )
9955	9960	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
9956	9961	ROM_LOAD16_BYTE( "95403111.lo", 0x00001, 0x080000, CRC(259141c0) SHA1(4bb6d8614696548f1f81f6c2045bde45d4316927) )
9957	9962	ROM_LOAD16_BYTE( "95403112.hi", 0x00000, 0x080000, CRC(26c12768) SHA1(41dbde2bbc7df5bb9e50d9380f8199345ae1989c) )
9958		sc_pacmn_others
	9963	PACMAN_SOUNDS
9959	9964	ROM_END
9960	9965
9961		ROM_START( sc4pacmnc )
	9966	ROM_START( sc4pacqp )
9962	9967	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
9963	9968	ROM_LOAD16_BYTE( "96000001.lo", 0x00001, 0x080000, CRC(250b6446) SHA1(d4aaaf1f0eb6833fb90bdfcc46100853db007c98) )
9964	9969	ROM_LOAD16_BYTE( "96000002.hi", 0x00000, 0x080000, CRC(85aded4d) SHA1(a087e3e82664806858f2b36917a56d5326c79544) )
9965		sc_pacmn_others
	9970	QPS_PACP_SOUNDS
9966	9971	ROM_END
9967	9972
9968		ROM_START( sc4pacmnd )
	9973	ROM_START( sc4pacqpa )
9969	9974	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
9970	9975	ROM_LOAD16_BYTE( "96000016.odd", 0x00001, 0x080000, CRC(4e1d764e) SHA1(9c2a5ae820a95448558ed12cbe87a9353c054d44) )
9971	9976	ROM_LOAD16_BYTE( "96000017.evn", 0x00000, 0x080000, CRC(eaf93528) SHA1(d4464eae9cd015e33f305d0458086e845199b8cd) )
9972		sc_pacmn_others
	9977	QPS_PACP_SOUNDS
9973	9978	ROM_END
9974	9979
9975		ROM_START( sc4pacmne )
	9980	ROM_START( sc4pacqpb )
9976	9981	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
9977	9982	ROM_LOAD16_BYTE( "96003001.lo", 0x00001, 0x080000, CRC(70e21196) SHA1(0b7098da61df73f72ba459b1e8e9b6e92aef07d8) )
9978	9983	ROM_LOAD16_BYTE( "96003002.hi", 0x00000, 0x080000, CRC(4ebbe216) SHA1(aca58b3a2d8368014b738ce15d677dbcca885cc5) )
9979		sc_pacmn_others
	9984	QPS_PACP_SOUNDS
9980	9985	ROM_END
9981	9986
9982	9987
r14963	r14964
10255	10260	sc_pgold_others
10256	10261	ROM_END
10257	10262
10258		ROM_START( sc4pglcs )
10259		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
10260		ROM_LOAD16_BYTE( "95406734.lo", 0x00001, 0x080000, CRC(e983d8db) SHA1(045c1f73cacfdcbdfbea74ed23287120433e3341) )
10261		ROM_LOAD16_BYTE( "95406735.hi", 0x00000, 0x080000, CRC(c082ae45) SHA1(5985b87924d44155f55806772e406d3dcaf6b506) )
10262		sc_pgold_others
10263		ROM_END
10264	10263
10265	10264	ROM_START( sc4pgoldf )
10266	10265	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
r14963	r14964
10269	10268	sc_pgold_others
10270	10269	ROM_END
10271	10270
	10271	ROM_START( sc4pglcs )
	10272	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	10273	ROM_LOAD16_BYTE( "95406734.lo", 0x00001, 0x080000, CRC(e983d8db) SHA1(045c1f73cacfdcbdfbea74ed23287120433e3341) )
	10274	ROM_LOAD16_BYTE( "95406735.hi", 0x00000, 0x080000, CRC(c082ae45) SHA1(5985b87924d44155f55806772e406d3dcaf6b506) )
	10275	SC4_95004316_CAS_PHAR_GOLD_PR1261
	10276	ROM_END
	10277
10272	10278	ROM_START( sc4pglcsa )
10273	10279	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
10274	10280	ROM_LOAD16_BYTE( "95408068.lo", 0x00001, 0x080000, CRC(8932a906) SHA1(eca4706dd62e089ad9ce781b2ede0759dbe44bd9) )
10275	10281	ROM_LOAD16_BYTE( "95408069.hi", 0x00000, 0x080000, CRC(f56fff18) SHA1(e123bd7f1af75218dbbef82b33e7c21d882f8105) )
10276		sc_pgold_others
	10282	SC4_95004316_CAS_PHAR_GOLD_PR1261
10277	10283	ROM_END
10278	10284
10279	10285	ROM_START( sc4pglcsb )
10280	10286	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
10281	10287	ROM_LOAD16_BYTE( "95408144.lo", 0x00001, 0x080000, CRC(ee67e3d6) SHA1(963160426e1b2d4399132ff0df9662dc1d46c121) )
10282	10288	ROM_LOAD16_BYTE( "95408145.hi", 0x00000, 0x080000, CRC(b6e8a6d8) SHA1(d443aac2967229de4d6feae634efae9f3cd2f361) )
10283		sc_pgold_others
	10289	SC4_95004316_CAS_PHAR_GOLD_PR1261
10284	10290	ROM_END
10285	10291
10286	10292
r14963	r14964
18303	18309	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18304	18310	ROM_LOAD16_BYTE( "95404206.lo", 0x00001, 0x080000, CRC(bb853407) SHA1(498aad2cf2948d7fbef673186823af6a7dbefd95) )
18305	18311	ROM_LOAD16_BYTE( "95404207.hi", 0x00000, 0x080000, CRC(e4e3f4e0) SHA1(ab8a8eeb5661d6cd3ba5d25f2082c06ac8c343ac) )
18306		sc_gball_pthers
	18312	PR1034_GOLDEN_BALLS_SOUNDS11
18307	18313	ROM_END
18308	18314
18309	18315	ROM_START( sc4gbcasa )
18310	18316	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18311	18317	ROM_LOAD16_BYTE( "95404208.lo", 0x00001, 0x080000, CRC(fc080cdf) SHA1(86084d70e6a68afe3f788661b78cfb8df3bb8104) )
18312	18318	ROM_LOAD16_BYTE( "95404209.hi", 0x00000, 0x080000, CRC(6e4d776f) SHA1(0e09b78e138215ceb693bc86a3fe6d7320da9431) )
18313		sc_gball_pthers
	18319	PR1034_GOLDEN_BALLS_SOUNDS11
18314	18320	ROM_END
18315	18321
18316	18322	ROM_START( sc4gbcasb )
18317	18323	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18318	18324	ROM_LOAD16_BYTE( "95405206.lo", 0x00001, 0x080000, CRC(79f07bc2) SHA1(e85ddf4c18573894ecd51fec283cc46becb8aacc) )
18319	18325	ROM_LOAD16_BYTE( "95405207.hi", 0x00000, 0x080000, CRC(2c295913) SHA1(a8bf658c6ec248e7f53485ce778e9679eae62504) )
18320		sc_gball_pthers
	18326	PR1034_GOLDEN_BALLS_SOUNDS11
18321	18327	ROM_END
18322	18328
18323	18329	ROM_START( sc4gbcasc )
18324	18330	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18325	18331	ROM_LOAD16_BYTE( "95405208.lo", 0x00001, 0x080000, CRC(3e7d431a) SHA1(b7975bbbf369d2eb6b8fad5c7200e0007ce2365b) )
18326	18332	ROM_LOAD16_BYTE( "95405209.hi", 0x00000, 0x080000, CRC(a687da9c) SHA1(99cbc48fe2c9c28fb3b68107402af10c2a7f39fa) )
18327		sc_gball_pthers
	18333	PR1034_GOLDEN_BALLS_SOUNDS11
18328	18334	ROM_END
18329	18335
18330	18336	ROM_START( sc4gball )
r14963	r14964
18356	18362	ROM_END
18357	18363
18358	18364
18359		ROM_START( sc4ggame )
	18365	ROM_START( sc4ggtb )
18360	18366	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18361	18367	ROM_LOAD16_BYTE( "95404762.lo", 0x00001, 0x080000, CRC(613941b4) SHA1(4cc1441b94913d597aa88e973f4514f7278a7cc9) )
18362	18368	ROM_LOAD16_BYTE( "95404763.hi", 0x00000, 0x080000, CRC(dbec56ec) SHA1(bb8f2395afe8d5193320d627ef722c1105b02826) )
18363	18369	sc_ggame_others
18364	18370	ROM_END
18365	18371
	18372	ROM_START( sc4ggtba )
	18373	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	18374	ROM_LOAD16_BYTE( "95408086.lo", 0x00001, 0x080000, CRC(cd0b1ea9) SHA1(ebb5023afa24876d97417db50aa675ec29c0351b) )
	18375	ROM_LOAD16_BYTE( "95408087.hi", 0x00000, 0x080000, CRC(0a21efb4) SHA1(5765431cfc61521d55e00d7fdd2e08f0ef37d12c) )
	18376	sc_ggame_others
	18377	ROM_END
	18378
	18379	ROM_START( sc4ggtbb )
	18380	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	18381	ROM_LOAD16_BYTE( "95414970.lo", 0x00001, 0x080000, CRC(ab09550b) SHA1(004f858e5bcda93653efa511f66d33cbe20a44d1) )
	18382	ROM_LOAD16_BYTE( "95414971.hi", 0x00000, 0x080000, CRC(e137aff0) SHA1(50a2a6819034ca5b04c704da7cfaf029bdc031b2) )
	18383	sc_ggame_others
	18384	ROM_END
	18385
	18386
	18387
18366	18388	ROM_START( sc4ggamea )
18367	18389	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18368	18390	ROM_LOAD16_BYTE( "95406768.lo", 0x00001, 0x080000, CRC(dec1db93) SHA1(b22b874e5ff5da46e2783544781d7387f98dd4fc) )
r14963	r14964
18391	18413	sc_ggame_others
18392	18414	ROM_END
18393	18415
18394		ROM_START( sc4ggamee )
18395		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18396		ROM_LOAD16_BYTE( "95408086.lo", 0x00001, 0x080000, CRC(cd0b1ea9) SHA1(ebb5023afa24876d97417db50aa675ec29c0351b) )
18397		ROM_LOAD16_BYTE( "95408087.hi", 0x00000, 0x080000, CRC(0a21efb4) SHA1(5765431cfc61521d55e00d7fdd2e08f0ef37d12c) )
18398		sc_ggame_others
18399		ROM_END
18400	18416
18401	18417	ROM_START( sc4ggamef )
18402	18418	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
r14963	r14964
18412	18428	sc_ggame_others
18413	18429	ROM_END
18414	18430
18415		ROM_START( sc4ggameh )
	18431	ROM_START( sc4ggame )
18416	18432	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18417	18433	ROM_LOAD16_BYTE( "95414396.lo", 0x00001, 0x080000, CRC(1160d686) SHA1(b531823f970e09c808e2efb284951c79091b44b1) )
18418	18434	ROM_LOAD16_BYTE( "95414397.hi", 0x00000, 0x080000, CRC(886f6d1f) SHA1(532f53d2c9956212ea0086b92c1dad38b417ad9e) )
r14963	r14964
18463	18479
18464	18480
18465	18481
18466		ROM_START( sc4ggameo )
18467		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18468		ROM_LOAD16_BYTE( "95414970.lo", 0x00001, 0x080000, CRC(ab09550b) SHA1(004f858e5bcda93653efa511f66d33cbe20a44d1) )
18469		ROM_LOAD16_BYTE( "95414971.hi", 0x00000, 0x080000, CRC(e137aff0) SHA1(50a2a6819034ca5b04c704da7cfaf029bdc031b2) )
18470		sc_ggame_others
18471		ROM_END
18472	18482
18473	18483
18474	18484	ROM_START( sc4ggamep )
r14963	r14964
18716	18726
18717	18727
18718	18728
18719		ROM_START( sc4ggg )
	18729	ROM_START( sc4gggtb )
18720	18730	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18721	18731	ROM_LOAD16_BYTE( "95420668.lo", 0x00001, 0x080000, CRC(afef1626) SHA1(00d676d0ed36ddf4255d26779b3319f61319a9cb) )
18722	18732	ROM_LOAD16_BYTE( "95420669.hi", 0x00000, 0x080000, CRC(6e273bf4) SHA1(35ba48892d9ea3ebcb00fe33c75ee8e7949ab421) )
18723	18733	sc_ggg_others
18724	18734	ROM_END
18725	18735
18726		ROM_START( sc4ggga )
	18736	ROM_START( sc4gggtba )
18727	18737	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	18738	ROM_LOAD16_BYTE( "95421668.lo", 0x00001, 0x080000, CRC(6f4964c8) SHA1(14948920079694791a66dfd1f07b22badb37bc57) )
	18739	ROM_LOAD16_BYTE( "95421669.hi", 0x00000, 0x080000, CRC(23e030cf) SHA1(85c70ee8f906b48fb75692ec9e58e9072b1a731d) )
	18740	sc_ggg_others
	18741	ROM_END
	18742
	18743	ROM_START( sc4ggg )
	18744	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18728	18745	ROM_LOAD16_BYTE( "95420672.lo", 0x00001, 0x080000, CRC(88dd2622) SHA1(dc30308638d602b76e828cf6c98605a9fb7589b6) )
18729	18746	ROM_LOAD16_BYTE( "95420673.hi", 0x00000, 0x080000, CRC(309a5f9c) SHA1(8592127022c84bc6c36b744d8fa0d44a1bc38ea0) )
18730	18747	sc_ggg_others
r14963	r14964
18787	18804	sc_ggg_others
18788	18805	ROM_END
18789	18806
18790		ROM_START( sc4gggj )
18791		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18792		ROM_LOAD16_BYTE( "95421668.lo", 0x00001, 0x080000, CRC(6f4964c8) SHA1(14948920079694791a66dfd1f07b22badb37bc57) )
18793		ROM_LOAD16_BYTE( "95421669.hi", 0x00000, 0x080000, CRC(23e030cf) SHA1(85c70ee8f906b48fb75692ec9e58e9072b1a731d) )
18794		sc_ggg_others
18795		ROM_END
18796	18807
	18808
18797	18809	ROM_START( sc4gggk )
18798	18810	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18799	18811	ROM_LOAD16_BYTE( "95421672.lo", 0x00001, 0x080000, CRC(297c1a93) SHA1(7d0f8c6998f2970e1cce94a71fa4327edc66e07e) )
r14963	r14964
18930	18942	sc_hapnt_others
18931	18943	ROM_END
18932	18944
18933		ROM_START( sc4hntcs )
18934		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18935		ROM_LOAD16_BYTE( "95410960.lo", 0x00001, 0x080000, CRC(09417c00) SHA1(6d10896bf290c58b6fdb5d735b423a9d2d7db5d7) )
18936		ROM_LOAD16_BYTE( "95410961.hi", 0x00000, 0x080000, CRC(1611d748) SHA1(b5ae00a1e1adaf7af912b3f21fb0cb7b414996b3) )
18937		sc_hapnt_others
18938		ROM_END
18939	18945
18940		ROM_START( sc4hntcsa )
18941		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18942		ROM_LOAD16_BYTE( "95410962.lo", 0x00001, 0x080000, CRC(64cecf4d) SHA1(63f9f5fda15e99a249ea869105461c6d1db0a01a) )
18943		ROM_LOAD16_BYTE( "95410963.hi", 0x00000, 0x080000, CRC(758108b0) SHA1(4de01d82d5ff01adfa3907adb46d666dd9979734) )
18944		sc_hapnt_others
18945		ROM_END
18946
18947		ROM_START( sc4hntcsb )
18948		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18949		ROM_LOAD16_BYTE( "95410964.lo", 0x00001, 0x080000, CRC(fbf06b79) SHA1(8130b8e9f5f18399963db8206f0d6c9ed0312fce) )
18950		ROM_LOAD16_BYTE( "95410965.hi", 0x00000, 0x080000, CRC(a91e7166) SHA1(accaa8c05fe6754b4ac1cf6eee5713de239968ce) )
18951		sc_hapnt_others
18952		ROM_END
18953
18954		ROM_START( sc4hntcsc )
18955		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18956		ROM_LOAD16_BYTE( "95411960.lo", 0x00001, 0x080000, CRC(e4f6033a) SHA1(4bde8c65639e952e4120c9a538d709a88e2a7982) )
18957		ROM_LOAD16_BYTE( "95411961.hi", 0x00000, 0x080000, CRC(f17e876d) SHA1(d90123e04cbf6935ee9cb62abbfa5cabed83c5b5) )
18958		sc_hapnt_others
18959		ROM_END
18960
18961	18946	ROM_START( sc4hapntb )
18962	18947	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18963	18948	ROM_LOAD16_BYTE( "p1306p12.hi", 0x00000, 0x080000, CRC(ea9c501d) SHA1(31f912906f562a04053f58ebed3c7bd0ee864434) )
r14963	r14964
18986	18971	sc_hapnt_others
18987	18972	ROM_END
18988	18973
	18974
	18975	ROM_START( sc4hntcs )
	18976	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	18977	ROM_LOAD16_BYTE( "95410960.lo", 0x00001, 0x080000, CRC(09417c00) SHA1(6d10896bf290c58b6fdb5d735b423a9d2d7db5d7) )
	18978	ROM_LOAD16_BYTE( "95410961.hi", 0x00000, 0x080000, CRC(1611d748) SHA1(b5ae00a1e1adaf7af912b3f21fb0cb7b414996b3) )
	18979	PR1327_CAS_HAPPY_NOTES_SOUNDS11
	18980	ROM_END
	18981
	18982	ROM_START( sc4hntcsa )
	18983	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	18984	ROM_LOAD16_BYTE( "95410962.lo", 0x00001, 0x080000, CRC(64cecf4d) SHA1(63f9f5fda15e99a249ea869105461c6d1db0a01a) )
	18985	ROM_LOAD16_BYTE( "95410963.hi", 0x00000, 0x080000, CRC(758108b0) SHA1(4de01d82d5ff01adfa3907adb46d666dd9979734) )
	18986	PR1327_CAS_HAPPY_NOTES_SOUNDS11
	18987	ROM_END
	18988
	18989	ROM_START( sc4hntcsb )
	18990	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	18991	ROM_LOAD16_BYTE( "95410964.lo", 0x00001, 0x080000, CRC(fbf06b79) SHA1(8130b8e9f5f18399963db8206f0d6c9ed0312fce) )
	18992	ROM_LOAD16_BYTE( "95410965.hi", 0x00000, 0x080000, CRC(a91e7166) SHA1(accaa8c05fe6754b4ac1cf6eee5713de239968ce) )
	18993	PR1327_CAS_HAPPY_NOTES_SOUNDS11
	18994	ROM_END
	18995
	18996	ROM_START( sc4hntcsc )
	18997	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	18998	ROM_LOAD16_BYTE( "95411960.lo", 0x00001, 0x080000, CRC(e4f6033a) SHA1(4bde8c65639e952e4120c9a538d709a88e2a7982) )
	18999	ROM_LOAD16_BYTE( "95411961.hi", 0x00000, 0x080000, CRC(f17e876d) SHA1(d90123e04cbf6935ee9cb62abbfa5cabed83c5b5) )
	19000	PR1327_CAS_HAPPY_NOTES_SOUNDS11
	19001	ROM_END
	19002
18989	19003	ROM_START( sc4hntcsd )
18990	19004	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18991	19005	ROM_LOAD16_BYTE( "p1327p12.hi", 0x00000, 0x080000, CRC(734e60a9) SHA1(911f6c78654020c03b3e906aaf37ce3751f1cd85) )
18992	19006	ROM_LOAD16_BYTE( "p1327p12.lo", 0x00001, 0x080000, CRC(d1d169e0) SHA1(41540cee7ca0fbe2c93a1c55f0f9e9c933ed3f3b) )
18993		sc_hapnt_others
	19007	PR1327_CAS_HAPPY_NOTES_SOUNDS11
18994	19008	ROM_END
18995	19009
18996	19010	ROM_START( sc4hntcse )
18997	19011	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
18998	19012	ROM_LOAD16_BYTE( "p1327p13.hi", 0x00000, 0x080000, CRC(d3141aff) SHA1(7c75e47e1a36979177c220edacc5256342c3405c) )
18999	19013	ROM_LOAD16_BYTE( "p1327p13.lo", 0x00001, 0x080000, CRC(b80f3b5f) SHA1(8b1a3daadb67b2d147184ab7213abe9c29791c6e) )
19000		sc_hapnt_others
	19014	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19001	19015	ROM_END
19002	19016
19003	19017	ROM_START( sc4hntcsf )
19004	19018	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19005	19019	ROM_LOAD16_BYTE( "p1327p41.hi", 0x00000, 0x080000, CRC(0a0305da) SHA1(c4ed571484d13fed4adc83d96efabe060a6452a5) )
19006	19020	ROM_LOAD16_BYTE( "p1327p41.lo", 0x00001, 0x080000, CRC(f0001712) SHA1(5be70eaedca55c4098f236763206cf32bb1c2f4d) )
19007		sc_hapnt_others
	19021	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19008	19022	ROM_END
19009	19023
19010	19024	ROM_START( sc4hntcsg )
19011	19025	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19012	19026	ROM_LOAD16_BYTE( "p1327p42.hi", 0x00000, 0x080000, CRC(c6e34460) SHA1(63ae0930b7b0c104edee067a0e13c0a90c2d027c) )
19013	19027	ROM_LOAD16_BYTE( "p1327p42.lo", 0x00001, 0x080000, CRC(5e055385) SHA1(e42d7a0668bd1069c20bd519c37c1fcacabffca2) )
19014		sc_hapnt_others
	19028	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19015	19029	ROM_END
19016	19030
19017	19031	ROM_START( sc4hntcsh )
19018	19032	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19019	19033	ROM_LOAD16_BYTE( "p1327p61.hi", 0x00000, 0x080000, CRC(27a9e9a7) SHA1(9489bc73a3c806de974a82397c0d9907bcb3b9e5) )
19020	19034	ROM_LOAD16_BYTE( "p1327p61.lo", 0x00001, 0x080000, CRC(13e3aa1e) SHA1(8bd97ebaa6b56e7c846cde2f0b61173c0332c120) )
19021		sc_hapnt_others
	19035	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19022	19036	ROM_END
19023	19037
19024	19038	ROM_START( sc4hntcsi )
19025	19039	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19026	19040	ROM_LOAD16_BYTE( "p1327p71.hi", 0x00000, 0x080000, CRC(d9dd087b) SHA1(872a52bcb42df863407ecb796c8768a02d3614d9) )
19027	19041	ROM_LOAD16_BYTE( "p1327p71.lo", 0x00001, 0x080000, CRC(6cbef7a3) SHA1(11b6dfd24595fd10ce31e3f6361c6e9a7880c6c9) )
19028		sc_hapnt_others
	19042	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19029	19043	ROM_END
19030	19044
19031	19045	ROM_START( sc4hntcsj )
19032	19046	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19033	19047	ROM_LOAD16_BYTE( "p1327s12.hi", 0x00000, 0x080000, CRC(9aae872b) SHA1(fbd5e402d76bfc2b6e99667b6c97f851fc482abb) )
19034	19048	ROM_LOAD16_BYTE( "p1327s12.lo", 0x00001, 0x080000, CRC(c964b987) SHA1(422b59e1ca2f3105ab28b33f4e95314ee525882f) )
19035		sc_hapnt_others
	19049	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19036	19050	ROM_END
19037	19051
19038	19052	ROM_START( sc4hntcsk )
19039	19053	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19040	19054	ROM_LOAD16_BYTE( "p1327s13.hi", 0x00000, 0x080000, CRC(fc9dcc8a) SHA1(20605e20cdb643384f6c268d9e52b362d7369786) )
19041	19055	ROM_LOAD16_BYTE( "p1327s13.lo", 0x00001, 0x080000, CRC(e2327afa) SHA1(bd1c0334fbc5ae4c386ad389c0ec619344c26656) )
19042		sc_hapnt_others
	19056	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19043	19057	ROM_END
19044	19058
19045	19059	ROM_START( sc4hntcsl )
19046	19060	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19047	19061	ROM_LOAD16_BYTE( "p1327s41.hi", 0x00000, 0x080000, CRC(cd03727a) SHA1(fcc802a62d60bb084ea3451730bc685212510320) )
19048	19062	ROM_LOAD16_BYTE( "p1327s41.lo", 0x00001, 0x080000, CRC(346db912) SHA1(83435a6bb3e557a04040cd221474df23c39aa507) )
19049		sc_hapnt_others
	19063	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19050	19064	ROM_END
19051	19065
19052	19066	ROM_START( sc4hntcsm )
19053	19067	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19054	19068	ROM_LOAD16_BYTE( "p1327s42.hi", 0x00000, 0x080000, CRC(2e737e11) SHA1(d1447129e4e1c888527371f1c5625d3e33d9d187) )
19055	19069	ROM_LOAD16_BYTE( "p1327s42.lo", 0x00001, 0x080000, CRC(3916863f) SHA1(d0949fcc6414f42d292a04bd0d056cc51a10371c) )
19056		sc_hapnt_others
	19070	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19057	19071	ROM_END
19058	19072
19059	19073	ROM_START( sc4hntcsn )
19060	19074	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19061	19075	ROM_LOAD16_BYTE( "p1327s61.hi", 0x00000, 0x080000, CRC(d3429de9) SHA1(4e5f6df4a557dd0aa061a0b7c4d30b8f01f1d958) )
19062	19076	ROM_LOAD16_BYTE( "p1327s61.lo", 0x00001, 0x080000, CRC(76e3c418) SHA1(1ec77288096715894e0e179024205fa9dfaf3909) )
19063		sc_hapnt_others
	19077	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19064	19078	ROM_END
19065	19079
19066	19080	ROM_START( sc4hntcso )
19067	19081	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19068	19082	ROM_LOAD16_BYTE( "p1327s71.hi", 0x00000, 0x080000, CRC(2d367c35) SHA1(547ba184d465d90296150595f35a5c4b012108c6) )
19069	19083	ROM_LOAD16_BYTE( "p1327s71.lo", 0x00001, 0x080000, CRC(09be99a5) SHA1(d9ad6f8e4487c7fdf129478ac967d4c0aa96a0f9) )
19070		sc_hapnt_others
	19084	PR1327_CAS_HAPPY_NOTES_SOUNDS11
19071	19085	ROM_END
19072	19086
19073	19087
r14963	r14964
19076	19090	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
19077	19091	ROM_LOAD16_BYTE( "95406678.lo", 0x00001, 0x080000, CRC(82fa3872) SHA1(c1de9c35998c710f22eb95283a5a21d8e22c3c30) )
19078	19092	ROM_LOAD16_BYTE( "95406679.hi", 0x00000, 0x080000, CRC(5b0767c6) SHA1(3a0245ba5822ab3faa74a1f06a3c1648fa97ee40) )
19079		sc_hellb_others
	19093	SC4_95004211_HELLS_BELLS_PR6945
19080	19094	ROM_END
19081	19095
19082	19096	ROM_START( sc4hellba )
r14963	r14964
22452	22466	ROM_END
22453	22467
22454	22468
22455		ROM_START( sc4mowowd )
	22469	ROM_START( sc4mwwtb )
22456	22470	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
22457		ROM_LOAD16_BYTE( "95418078.lo", 0x00001, 0x080000, CRC(73044155) SHA1(f86e25c7c02f65e2f99b3e7b3b7192d2b5fc0b54) )
22458		ROM_LOAD16_BYTE( "95418079.hi", 0x00000, 0x080000, CRC(1d260113) SHA1(834fec1e07e9a2f59adbb052e51dc03493dcee9e) )
22459		sc_mowow_others
22460		ROM_END
22461
22462		ROM_START( sc4mowowe )
22463		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
22464		ROM_LOAD16_BYTE( "95419078.lo", 0x00001, 0x080000, CRC(9205e5fb) SHA1(e77062edcc51e44612c558ee593028934835a41d) )
22465		ROM_LOAD16_BYTE( "95419079.hi", 0x00000, 0x080000, CRC(f80fae88) SHA1(c483f89204489775458112d7ed34ad778d3c9e71) )
22466		sc_mowow_others
22467		ROM_END
22468
22469		ROM_START( sc4mowowf )
22470		ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
22471	22471	ROM_LOAD16_BYTE( "95424056.lo", 0x00001, 0x080000, CRC(255586e1) SHA1(caa32b86ab5f726174bb45402a015e2ae1b6ff68) )
22472	22472	ROM_LOAD16_BYTE( "95424057.hi", 0x00000, 0x080000, CRC(be45b2b1) SHA1(5d17963f705f8bcaa7a93af2c2621677a57ef039) )
22473		sc_mowow_others
	22473	WHEEL_OF_WEALTH_WOWT_SOUNDS
22474	22474	ROM_END
22475	22475
22476		ROM_START( sc4mowowg )
	22476	ROM_START( sc4mwwtba )
22477	22477	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
22478	22478	ROM_LOAD16_BYTE( "95424214.lo", 0x00001, 0x080000, CRC(a8b93c99) SHA1(83e6fa6751634f64d285ba6f93b8d52690c17d4a) )
22479	22479	ROM_LOAD16_BYTE( "95424215.hi", 0x00000, 0x080000, CRC(05c523d6) SHA1(558031df5270567ca2bd88a389b33cfae34b7967) )
22480		sc_mowow_others
	22480	WHEEL_OF_WEALTH_WOWT_SOUNDS
22481	22481	ROM_END
22482	22482
22483		ROM_START( sc4mowowh )
	22483	ROM_START( sc4mwwtbb )
22484	22484	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
22485	22485	ROM_LOAD16_BYTE( "95424512.lo", 0x00001, 0x080000, CRC(14b7ef71) SHA1(675345c95d2a68d1b3092d564a9c6192a7390486) )
22486	22486	ROM_LOAD16_BYTE( "95424513.hi", 0x00000, 0x080000, CRC(dd7c5383) SHA1(fad0cbba52a5c2746d325f437f9d85bee5776201) )
22487		sc_mowow_others
	22487	WHEEL_OF_WEALTH_WOWT_SOUNDS
22488	22488	ROM_END
22489	22489
22490		ROM_START( sc4mowowi )
	22490	ROM_START( sc4mwwtbc )
22491	22491	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
22492	22492	ROM_LOAD16_BYTE( "95425056.lo", 0x00001, 0x080000, CRC(b2c7fe92) SHA1(00e27916482a5fcabde46da8e139b49f789837a8) )
22493	22493	ROM_LOAD16_BYTE( "95425057.hi", 0x00000, 0x080000, CRC(8946e5d6) SHA1(1426c7ea7ded18b03bab7b08d0d13021bc8aa75b) )
22494		sc_mowow_others
	22494	WHEEL_OF_WEALTH_WOWT_SOUNDS
22495	22495	ROM_END
22496	22496
22497		ROM_START( sc4mowowj ) // these were in the dnd perfect game set
	22497	ROM_START( sc4mwwtbd ) // these were in the dnd perfect game set
22498	22498	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
22499	22499	ROM_LOAD16_BYTE( "95425512.lo", 0x00001, 0x080000, CRC(1e66031a) SHA1(b149806fe7c0a996dfda4abcd00aa7ae9b126a7b) )
22500	22500	ROM_LOAD16_BYTE( "95425513.hi", 0x00000, 0x080000, CRC(a668aaae) SHA1(593f846687aa7d851fb38e62046c6174dfa088f5) )
22501		sc_mowow_others
	22501	WHEEL_OF_WEALTH_WOWT_SOUNDS
22502	22502	ROM_END
22503	22503
22504	22504
22505	22505
	22506	ROM_START( sc4bwow )
	22507	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	22508	ROM_LOAD16_BYTE( "95418078.lo", 0x00001, 0x080000, CRC(73044155) SHA1(f86e25c7c02f65e2f99b3e7b3b7192d2b5fc0b54) )
	22509	ROM_LOAD16_BYTE( "95418079.hi", 0x00000, 0x080000, CRC(1d260113) SHA1(834fec1e07e9a2f59adbb052e51dc03493dcee9e) )
	22510	PR1706_WHEEL_OF_WEALTH_SOUNDS11
	22511	ROM_END
22506	22512
	22513	ROM_START( sc4bwowa )
	22514	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
	22515	ROM_LOAD16_BYTE( "95419078.lo", 0x00001, 0x080000, CRC(9205e5fb) SHA1(e77062edcc51e44612c558ee593028934835a41d) )
	22516	ROM_LOAD16_BYTE( "95419079.hi", 0x00000, 0x080000, CRC(f80fae88) SHA1(c483f89204489775458112d7ed34ad778d3c9e71) )
	22517	PR1706_WHEEL_OF_WEALTH_SOUNDS11
	22518	ROM_END
22507	22519
22508	22520
22509	22521
r14963	r14964
24330	24342	GAME( 200?, sc4outlwc   ,sc4outlw,   sc4, sc4, sc4, ROT0, "BFM","Outlaw (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
24331	24343
24332	24344
	24345	// PR7072 PAC MAN         PACP SOUNDS             PAC-MAN
	24346	GAME( 200?, sc4pacqp   ,0,           sc4, sc4, sc4, ROT0, "QPS","Pac Man (PR7072) (QPS) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	24347	GAME( 200?, sc4pacqpa   ,sc4pacqp,   sc4, sc4, sc4, ROT0, "QPS","Pac Man (PR7072) (QPS) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	24348	GAME( 200?, sc4pacqpb   ,sc4pacqp,   sc4, sc4, sc4, ROT0, "QPS","Pac Man (PR7072) (QPS) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	24349
24333	24350	// PR7026 PACMAN         PACMAN SOUNDS
24334		GAME( 200?, sc4pacmn   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Pac Man (PR7026) (Mazooma) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	24351	GAME( 200?, sc4pacmn   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Pac Man (PR7026) (Mazooma) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL ) // this set doesn't start, CPU ends up dead?
24335	24352	GAME( 200?, sc4pacmna   ,sc4pacmn,   sc4, sc4, sc4, ROT0, "Mazooma","Pac Man (PR7026) (Mazooma) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
24336	24353	GAME( 200?, sc4pacmnb   ,sc4pacmn,   sc4, sc4, sc4, ROT0, "Mazooma","Pac Man (PR7026) (Mazooma) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
24337		// PR7072 PAC MAN         PACP SOUNDS             PAC-MAN
24338		GAME( 200?, sc4pacmnc   ,sc4pacmn,   sc4, sc4, sc4, ROT0, "Mazooma","Pac Man (PR7072) (Mazooma) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
24339		GAME( 200?, sc4pacmnd   ,sc4pacmn,   sc4, sc4, sc4, ROT0, "Mazooma","Pac Man (PR7072) (Mazooma) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
24340		GAME( 200?, sc4pacmne   ,sc4pacmn,   sc4, sc4, sc4, ROT0, "Mazooma","Pac Man (PR7072) (Mazooma) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
24341	24354
	24355
24342	24356	// PR7049CASINO PACMAN         PACMAN SOUNDS
24343	24357	GAME( 200?, sc4paccs   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Pac Man Casino (Mazooma) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
24344	24358	GAME( 200?, sc4paccsa   ,sc4paccs,   sc4, sc4, sc4, ROT0, "Mazooma","Pac Man Casino (Mazooma) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
r14963	r14964
24381	24395	//  PR1205 PAY TIME         95004224 PAYTIME PR7156             PAY TIME
24382	24396	GAME( 200?, sc4paytm   ,0,         sc4, sc4, sc4, ROT0, "BFM","Pay Time (Bellfruit) (Scorpion 4)", GAME_IS_SKELETON_MECHANICAL ) // Not English
24383	24397
	24398	const stepper_interface* sc4pgold_reel_configs[6] =
	24399	{
	24400	&starpoint_interface_48step,
	24401	&starpoint_interface_48step,
	24402	&starpoint_interface_48step,
	24403	&starpoint_interface_48step,
	24404	&starpoint_interface_200step_reel,
	24405	0,
	24406	};
	24407
	24408	static DRIVER_INIT( sc4pgold )
	24409	{
	24410	sc4_state *state = machine.driver_data<sc4_state>();
	24411	DRIVER_INIT_CALL( sc4mbus );
	24412	state->m_reel_setup = sc4pgold_reel_configs;
	24413	}
	24414
24384	24415	// PR1012 PHARAOH'S GOLD         PR1012 PHARAOHS GOLD SOUNDS11
24385		GAME( 200?, sc4pgold   ,0,         sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
24386		GAME( 200?, sc4pgolda   ,sc4pgold,   sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
24387		GAME( 200?, sc4pgoldb   ,sc4pgold,   sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
24388		GAME( 200?, sc4pgoldc   ,sc4pgold,   sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
24389		GAME( 200?, sc4pgoldd   ,sc4pgold,   sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
24390		GAME( 200?, sc4pgoldf   ,sc4pgold,   sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
	24416	GAME( 200?, sc4pgold   ,0,         sc4, sc4, sc4pgold, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	24417	GAME( 200?, sc4pgolda   ,sc4pgold,   sc4, sc4, sc4pgold, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	24418	GAME( 200?, sc4pgoldb   ,sc4pgold,   sc4, sc4, sc4pgold, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	24419	GAME( 200?, sc4pgoldc   ,sc4pgold,   sc4, sc4, sc4pgold, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	24420	GAME( 200?, sc4pgoldd   ,sc4pgold,   sc4, sc4, sc4pgold, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
	24421	GAME( 200?, sc4pgoldf   ,sc4pgold,   sc4, sc4, sc4pgold, ROT0, "BFM","Pharaoh's Gold (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
24391	24422
	24423
	24424	// same name, but a different game? (Less reels..)
24392	24425	//  PR1261 PHARAOH'S GOLD         95004316 CAS PHAR GOLD PR1261
24393		GAME( 200?, sc4pglcs   ,0,         sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold Casino (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
24394		GAME( 200?, sc4pglcsa   ,sc4pglcs,   sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold Casino (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
24395		GAME( 200?, sc4pglcsb   ,sc4pglcs,   sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold Casino (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	24426	GAME( 200?, sc4pglcs   ,0,         sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold Casino (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL ) // Not English
	24427	GAME( 200?, sc4pglcsa   ,sc4pglcs,   sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold Casino (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL ) // Not English
	24428	GAME( 200?, sc4pglcsb   ,sc4pglcs,   sc4, sc4, sc4, ROT0, "BFM","Pharaoh's Gold Casino (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL ) // Not English
24396	24429
24397	24430
24398	24431
r14963	r14964
24671	24704	GAME( 200?, sc4rbankc   ,sc4rbank,   sc4, sc4, sc4, ROT0, "BFM","Royle Banker (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
24672	24705
24673	24706
	24707	const stepper_interface* sc4royle_reel_configs[6] =
	24708	{
	24709	&starpoint_interface_48step,
	24710	&starpoint_interface_48step,
	24711	&starpoint_interface_48step,
	24712	0,
	24713	&starpoint_interface_200step_reel,
	24714	0,
	24715	};
24674	24716
	24717	static DRIVER_INIT( sc4royle )
	24718	{
	24719	sc4_state *state = machine.driver_data<sc4_state>();
	24720	DRIVER_INIT_CALL( sc4mbus );
	24721	state->m_reel_setup = sc4royle_reel_configs;
	24722	}
	24723
24675	24724	// PR1102 ROYLEFAMILY         PR1102 ROYLEFAMILY SOUNDS11
24676		GAME( 200?, sc4royle   ,0,         sc4, sc4, sc4, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
24677		GAME( 200?, sc4roylea   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
24678		GAME( 200?, sc4royleb   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
24679		GAME( 200?, sc4roylec   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
24680		GAME( 200?, sc4royled   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
24681		GAME( 200?, sc4roylee   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
24682		GAME( 200?, sc4royleh   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
24683		GAME( 200?, sc4roylei   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
	24725	GAME( 200?, sc4royle   ,0,         sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	24726	GAME( 200?, sc4roylea   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	24727	GAME( 200?, sc4royleb   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	24728	GAME( 200?, sc4roylec   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	24729	GAME( 200?, sc4royled   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
	24730	GAME( 200?, sc4roylee   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
	24731	GAME( 200?, sc4royleh   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
	24732	GAME( 200?, sc4roylei   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
24684	24733	// PR1102 ROYLEFAMILY REV2         PR1102 ROYLEFAMILY SOUNDS11
24685		GAME( 200?, sc4roylef   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
24686		GAME( 200?, sc4royleg   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
24687		GAME( 200?, sc4roylej   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
24688		GAME( 200?, sc4roylek   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
24689		GAME( 200?, sc4roylel   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
24690		GAME( 200?, sc4roylem   ,sc4royle,   sc4, sc4, sc4, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
	24734	GAME( 200?, sc4roylef   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	24735	GAME( 200?, sc4royleg   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	24736	GAME( 200?, sc4roylej   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	24737	GAME( 200?, sc4roylek   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	24738	GAME( 200?, sc4roylel   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
	24739	GAME( 200?, sc4roylem   ,sc4royle,   sc4, sc4, sc4royle, ROT0, "BFM","Royle Family (REV 2) (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
24691	24740
24692	24741	// PR7141 SHAKE RATTLE ROLL         LINE SOUNDS         *  SHAKE RATT ROLL
24693	24742	GAME( 200?, sc4srrmz   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Shake Rattle Roll (Mazooma) (Scorpion 4) (set 1, Top Box)", GAME_IS_SKELETON_MECHANICAL )
r14963	r14964
25478	25527	GAME( 200?, sc4bobh      ,sc4bob,   sc4, sc4, sc4, ROT0, "Mazooma","Bobby Dazzler (Mazooma) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL )
25479	25528	GAME( 200?, sc4bobi      ,sc4bob,   sc4, sc4, sc4, ROT0, "Mazooma","Bobby Dazzler (Mazooma) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )
25480	25529
	25530	const stepper_interface* sc4bull_reel_configs[6] =
	25531	{
	25532	&starpoint_interface_48step,
	25533	&starpoint_interface_48step,
	25534	&starpoint_interface_48step,
	25535	0,
	25536	&starpoint_interface_200step_reel,
	25537	0,
	25538	};
	25539
	25540	static DRIVER_INIT( sc4bull )
	25541	{
	25542	sc4_state *state = machine.driver_data<sc4_state>();
	25543	DRIVER_INIT_CALL( sc4mbus );
	25544	state->m_reel_setup = sc4bull_reel_configs;
	25545	}
	25546
25481	25547	// PR1722 AWP BULLSEYE SCORP4         PR1702 BULLSEYE SOUNDS11         BULLSEYE  S.SITE
25482		GAME( 200?, sc4bull      ,0,         sc4, sc4, sc4mbus, ROT0, "BFM","Bullseye (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
25483		GAME( 200?, sc4bulla   ,sc4bull,   sc4, sc4, sc4mbus, ROT0, "BFM","Bullseye (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
25484		GAME( 200?, sc4bullb   ,sc4bull,   sc4, sc4, sc4mbus, ROT0, "BFM","Bullseye (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
25485		GAME( 200?, sc4bullc   ,sc4bull,   sc4, sc4, sc4mbus, ROT0, "BFM","Bullseye (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	25548	GAME( 200?, sc4bull      ,0,         sc4, sc4, sc4bull, ROT0, "BFM","Bullseye (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	25549	GAME( 200?, sc4bulla   ,sc4bull,   sc4, sc4, sc4bull, ROT0, "BFM","Bullseye (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	25550	GAME( 200?, sc4bullb   ,sc4bull,   sc4, sc4, sc4bull, ROT0, "BFM","Bullseye (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	25551	GAME( 200?, sc4bullc   ,sc4bull,   sc4, sc4, sc4bull, ROT0, "BFM","Bullseye (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
25486	25552
25487	25553	// PR1740 AWP BULLSEYE CLASSIC SCORP4         PR1702 BULLSEYE SOUNDS11         BULLSEYE CLASSIC  S.SITE
25488	25554	GAME( 200?, sc4bulcs   ,0,         sc4, sc4, sc4mbus, ROT0, "BFM","Bullseye Classic (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
r14963	r14964
26616	26682	GAME( 200?, sc4gladf   ,sc4glad,   sc4, sc4, sc4, ROT0, "Mazooma","Gladiator (Mazooma) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
26617	26683	GAME( 200?, sc4gladg   ,sc4glad,   sc4, sc4, sc4, ROT0, "Mazooma","Gladiator (Mazooma) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
26618	26684
	26685	const stepper_interface* sc4gd_reel_configs[6] =
	26686	{
	26687	&starpoint_interface_48step,
	26688	&starpoint_interface_48step,
	26689	&starpoint_interface_48step,
	26690	&starpoint_interface_48step,
	26691	&starpoint_interface_200step_reel,
	26692	0,
	26693	};
	26694
	26695	static DRIVER_INIT( sc4gd )
	26696	{
	26697	sc4_state *state = machine.driver_data<sc4_state>();
	26698	DRIVER_INIT_CALL( sc4 );
	26699	state->m_reel_setup = sc4gd_reel_configs;
	26700	}
	26701
26619	26702	// PR1016 GOLD DIGGER         PR1016 GOLD DIGGER SOUNDS11
26620		GAME( 200?, sc4gd      ,0,         sc4, sc4, sc4, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26621		GAME( 200?, sc4gda      ,sc4gd,      sc4, sc4, sc4, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
26622		GAME( 200?, sc4gdb      ,sc4gd,      sc4, sc4, sc4, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
26623		GAME( 200?, sc4gdc      ,sc4gd,      sc4, sc4, sc4, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
26624		GAME( 200?, sc4gdd      ,sc4gd,      sc4, sc4, sc4, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
26625		GAME( 200?, sc4gde      ,sc4gd,      sc4, sc4, sc4, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
26626		GAME( 200?, sc4gdf      ,sc4gd,      sc4, sc4, sc4, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
26627		GAME( 200?, sc4gdg      ,sc4gd,      sc4, sc4, sc4, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
	26703	GAME( 200?, sc4gd      ,0,         sc4, sc4, sc4gd, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	26704	GAME( 200?, sc4gda      ,sc4gd,      sc4, sc4, sc4gd, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	26705	GAME( 200?, sc4gdb      ,sc4gd,      sc4, sc4, sc4gd, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	26706	GAME( 200?, sc4gdc      ,sc4gd,      sc4, sc4, sc4gd, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	26707	GAME( 200?, sc4gdd      ,sc4gd,      sc4, sc4, sc4gd, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
	26708	GAME( 200?, sc4gde      ,sc4gd,      sc4, sc4, sc4gd, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
	26709	GAME( 200?, sc4gdf      ,sc4gd,      sc4, sc4, sc4gd, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
	26710	GAME( 200?, sc4gdg      ,sc4gd,      sc4, sc4, sc4gd, ROT0, "BFM","Gold Digger (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
26628	26711
26629	26712	// PR2056  GOLDEN X         BARX SOUNDS         GOLDEN X  (are these really Gold Diggers?)
26630	26713	GAME( 200?, sc4gdmz      ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Gold Diggers? / Golden X Game (Mazooma) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26631	26714	GAME( 200?, sc4gdmza   ,sc4gdmz,   sc4, sc4, sc4, ROT0, "Mazooma","Gold Diggers? / Golden X Game (Mazooma) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
26632	26715
	26716	const stepper_interface* sc4gdclb_reel_configs[6] =
	26717	{
	26718	&starpoint_interface_48step,
	26719	&starpoint_interface_48step,
	26720	&starpoint_interface_48step,
	26721	&starpoint_interface_48step,
	26722	&starpoint_interface_48step,
	26723	&starpoint_interface_200step_reel,
	26724	};
	26725
	26726	static DRIVER_INIT( sc4gdclb )
	26727	{
	26728	sc4_state *state = machine.driver_data<sc4_state>();
	26729	DRIVER_INIT_CALL( sc4 );
	26730	state->m_reel_setup = sc4gdclb_reel_configs;
	26731	}
	26732
	26733
26633	26734	// PR1137 CLUB GOLD DIGGER         PR1137 GOLDD CL SOUNDS11
26634		GAME( 200?, sc4gdclb   ,0,         sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26635		GAME( 200?, sc4gdclba   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
26636		GAME( 200?, sc4gdclbb   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
26637		GAME( 200?, sc4gdclbc   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
26638		GAME( 200?, sc4gdclbd   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
26639		GAME( 200?, sc4gdclbe   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
26640		GAME( 200?, sc4gdclbf   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
26641		GAME( 200?, sc4gdclbg   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
26642		GAME( 200?, sc4gdclbh   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL )
26643		GAME( 200?, sc4gdclbi   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )
26644		GAME( 200?, sc4gdclbj   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 11)", GAME_IS_SKELETON_MECHANICAL )
26645		GAME( 200?, sc4gdclbk   ,sc4gdclb,   sc4, sc4, sc4, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 12)", GAME_IS_SKELETON_MECHANICAL )
	26735	GAME( 200?, sc4gdclb   ,0,         sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	26736	GAME( 200?, sc4gdclba   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	26737	GAME( 200?, sc4gdclbb   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	26738	GAME( 200?, sc4gdclbc   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	26739	GAME( 200?, sc4gdclbd   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
	26740	GAME( 200?, sc4gdclbe   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
	26741	GAME( 200?, sc4gdclbf   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
	26742	GAME( 200?, sc4gdclbg   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
	26743	GAME( 200?, sc4gdclbh   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL )
	26744	GAME( 200?, sc4gdclbi   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )
	26745	GAME( 200?, sc4gdclbj   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 11)", GAME_IS_SKELETON_MECHANICAL )
	26746	GAME( 200?, sc4gdclbk   ,sc4gdclb,   sc4, sc4, sc4gdclb, ROT0, "BFM","Gold Digger Club (Bellfruit) (Scorpion 4) (set 12)", GAME_IS_SKELETON_MECHANICAL )
26646	26747
	26748	const stepper_interface* sc4gbcas_reel_configs[6] =
	26749	{
	26750	&starpoint_interface_48step,
	26751	&starpoint_interface_48step,
	26752	&starpoint_interface_48step,
	26753	&starpoint_interface_200step_reel,
	26754	0,
	26755	0,
	26756	};
	26757
	26758	static DRIVER_INIT( sc4gbcas )
	26759	{
	26760	sc4_state *state = machine.driver_data<sc4_state>();
	26761	DRIVER_INIT_CALL( sc4 );
	26762	state->m_reel_setup = sc4gbcas_reel_configs;
	26763	}
	26764
	26765	// this one is a variation of lucky balls
26647	26766	// PR1034 CASINO GOLDEN BALLS         PR1034 GOLDEN BALLS SOUNDS11
26648		GAME( 200?, sc4gbcas   ,0,         sc4, sc4, sc4, ROT0, "BFM","Golden Balls Casino (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26649		GAME( 200?, sc4gbcasa   ,sc4gbcas,   sc4, sc4, sc4, ROT0, "BFM","Golden Balls Casino (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
26650		GAME( 200?, sc4gbcasb   ,sc4gbcas,   sc4, sc4, sc4, ROT0, "BFM","Golden Balls Casino (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
26651		GAME( 200?, sc4gbcasc   ,sc4gbcas,   sc4, sc4, sc4, ROT0, "BFM","Golden Balls Casino (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	26767	GAME( 200?, sc4gbcas   ,0,         sc4, sc4, sc4gbcas, ROT0, "BFM","Golden Balls Casino (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	26768	GAME( 200?, sc4gbcasa   ,sc4gbcas,   sc4, sc4, sc4gbcas, ROT0, "BFM","Golden Balls Casino (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	26769	GAME( 200?, sc4gbcasb   ,sc4gbcas,   sc4, sc4, sc4gbcas, ROT0, "BFM","Golden Balls Casino (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	26770	GAME( 200?, sc4gbcasc   ,sc4gbcas,   sc4, sc4, sc4gbcas, ROT0, "BFM","Golden Balls Casino (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
26652	26771
	26772
	26773	const stepper_interface* sc4gball_reel_configs[6] =
	26774	{
	26775	&starpoint_interface_48step,
	26776	&starpoint_interface_48step,
	26777	&starpoint_interface_48step,
	26778	0,
	26779	&starpoint_interface_48step,
	26780	0,
	26781	};
	26782
	26783	static DRIVER_INIT( sc4gball )
	26784	{
	26785	sc4_state *state = machine.driver_data<sc4_state>();
	26786	DRIVER_INIT_CALL( sc4 );
	26787	state->m_reel_setup = sc4gball_reel_configs;
	26788	}
	26789
	26790	// this is a football themed game...
26653	26791	// PR1604 AWP GOLDEN BALLS         PR1604 GOLDEN BALLS SOUNDS12      GOLDEN BALLS  S.SITE
26654		GAME( 200?, sc4gball   ,0,         sc4, sc4, sc4, ROT0, "BFM","Golden Balls (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26655		GAME( 200?, sc4gballa   ,sc4gball,   sc4, sc4, sc4, ROT0, "BFM","Golden Balls (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
26656		GAME( 200?, sc4gballb   ,sc4gball,   sc4, sc4, sc4, ROT0, "BFM","Golden Balls (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
26657		GAME( 200?, sc4gballc   ,sc4gball,   sc4, sc4, sc4, ROT0, "BFM","Golden Balls (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	26792	GAME( 200?, sc4gball   ,0,         sc4, sc4, sc4gball, ROT0, "BFM","Golden Balls (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	26793	GAME( 200?, sc4gballa   ,sc4gball,   sc4, sc4, sc4gball, ROT0, "BFM","Golden Balls (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	26794	GAME( 200?, sc4gballb   ,sc4gball,   sc4, sc4, sc4gball, ROT0, "BFM","Golden Balls (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	26795	GAME( 200?, sc4gballc   ,sc4gball,   sc4, sc4, sc4gball, ROT0, "BFM","Golden Balls (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
26658	26796
	26797	const stepper_interface* sc4gunp_reel_configs[6] =
	26798	{
	26799	&starpoint_interface_48step,
	26800	&starpoint_interface_48step,
	26801	&starpoint_interface_48step,
	26802	0,
	26803	&starpoint_interface_48step,
	26804	&starpoint_interface_48step,
	26805	};
	26806
	26807	static DRIVER_INIT( sc4gunp )
	26808	{
	26809	sc4_state *state = machine.driver_data<sc4_state>();
	26810	DRIVER_INIT_CALL( sc4mbus );
	26811	state->m_reel_setup = sc4gunp_reel_configs;
	26812	}
	26813
26659	26814	// PR3046 AWP THE GUNPOWDER SLOT S4         PR3016 GUNPOWDER SLOT SOUNDS11    GUNPOWDER SLOT  S.SITE
26660		GAME( 200?, sc4gunp      ,0,         sc4, sc4, sc4mbus, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26661		GAME( 200?, sc4gunpa   ,sc4gunp,   sc4, sc4, sc4mbus, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
26662		GAME( 200?, sc4gunpb   ,sc4gunp,   sc4, sc4, sc4mbus, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
26663		GAME( 200?, sc4gunpc   ,sc4gunp,   sc4, sc4, sc4mbus, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
26664		GAME( 200?, sc4gunpd   ,sc4gunp,   sc4, sc4, sc4mbus, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
26665		GAME( 200?, sc4gunpe   ,sc4gunp,   sc4, sc4, sc4mbus, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
26666		GAME( 200?, sc4gunpf   ,sc4gunp,   sc4, sc4, sc4mbus, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
26667		GAME( 200?, sc4gunpg   ,sc4gunp,   sc4, sc4, sc4mbus, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
	26815	GAME( 200?, sc4gunp      ,0,         sc4, sc4, sc4gunp, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	26816	GAME( 200?, sc4gunpa   ,sc4gunp,   sc4, sc4, sc4gunp, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	26817	GAME( 200?, sc4gunpb   ,sc4gunp,   sc4, sc4, sc4gunp, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	26818	GAME( 200?, sc4gunpc   ,sc4gunp,   sc4, sc4, sc4gunp, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	26819	GAME( 200?, sc4gunpd   ,sc4gunp,   sc4, sc4, sc4gunp, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
	26820	GAME( 200?, sc4gunpe   ,sc4gunp,   sc4, sc4, sc4gunp, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
	26821	GAME( 200?, sc4gunpf   ,sc4gunp,   sc4, sc4, sc4gunp, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
	26822	GAME( 200?, sc4gunpg   ,sc4gunp,   sc4, sc4, sc4gunp, ROT0, "BFM","Gunpowder Slot (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
26668	26823
	26824	const stepper_interface* sc4hapnt_reel_configs[6] =
	26825	{
	26826	&starpoint_interface_48step,
	26827	&starpoint_interface_48step,
	26828	&starpoint_interface_48step,
	26829	0,
	26830	&starpoint_interface_48step,
	26831	0,
	26832	};
26669	26833
	26834	static DRIVER_INIT( sc4hapnt )
	26835	{
	26836	sc4_state *state = machine.driver_data<sc4_state>();
	26837	DRIVER_INIT_CALL( sc4mbus );
	26838	state->m_reel_setup = sc4hapnt_reel_configs;
	26839	}
26670	26840
26671	26841	// PR1306 AWP HAPPY NOTES         PR1306 HAPPY NOTES SOUNDS11
26672		GAME( 200?, sc4hapnt   ,0,         sc4, sc4, sc4, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26673		GAME( 200?, sc4hapnta   ,sc4hapnt,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
26674		GAME( 200?, sc4hapntb   ,sc4hapnt,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
26675		GAME( 200?, sc4hapntc   ,sc4hapnt,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
26676		GAME( 200?, sc4hapntd   ,sc4hapnt,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
26677		GAME( 200?, sc4hapnte   ,sc4hapnt,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
	26842	GAME( 200?, sc4hapnt   ,0,         sc4, sc4, sc4hapnt, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	26843	GAME( 200?, sc4hapnta   ,sc4hapnt,   sc4, sc4, sc4hapnt, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	26844	GAME( 200?, sc4hapntb   ,sc4hapnt,   sc4, sc4, sc4hapnt, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	26845	GAME( 200?, sc4hapntc   ,sc4hapnt,   sc4, sc4, sc4hapnt, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	26846	GAME( 200?, sc4hapntd   ,sc4hapnt,   sc4, sc4, sc4hapnt, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
	26847	GAME( 200?, sc4hapnte   ,sc4hapnt,   sc4, sc4, sc4hapnt, ROT0, "BFM","Happy Notes (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
	26848
	26849	const stepper_interface* sc4hntcs_reel_configs[6] =
	26850	{
	26851	&starpoint_interface_48step,
	26852	&starpoint_interface_48step,
	26853	&starpoint_interface_48step,
	26854	&starpoint_interface_48step,
	26855	0,
	26856	0,
	26857	};
	26858
	26859	static DRIVER_INIT( sc4hntcsm )
	26860	{
	26861	sc4_state *state = machine.driver_data<sc4_state>();
	26862	DRIVER_INIT_CALL( sc4mbus );
	26863	state->m_reel_setup = sc4hntcs_reel_configs;
	26864	}
	26865
	26866
	26867	static DRIVER_INIT( sc4hntcs )
	26868	{
	26869	sc4_state *state = machine.driver_data<sc4_state>();
	26870	DRIVER_INIT_CALL( sc4 );
	26871	state->m_reel_setup = sc4hntcs_reel_configs;
	26872	}
	26873
26678	26874	// PR1327 CASINO HAPPY NOTES         HAPPY NOTES S.SITE  PR1327 CAS_HAPPY_NOTES SOUNDS11
26679		GAME( 200?, sc4hntcs   ,0,         sc4, sc4, sc4mbus, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26680		GAME( 200?, sc4hntcsa   ,sc4hntcs,   sc4, sc4, sc4mbus, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
26681		GAME( 200?, sc4hntcsb   ,sc4hntcs,   sc4, sc4, sc4mbus, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
26682		GAME( 200?, sc4hntcsc   ,sc4hntcs,   sc4, sc4, sc4mbus, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
	26875	GAME( 200?, sc4hntcs   ,0,         sc4, sc4, sc4hntcsm, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	26876	GAME( 200?, sc4hntcsa   ,sc4hntcs,   sc4, sc4, sc4hntcsm, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	26877	GAME( 200?, sc4hntcsb   ,sc4hntcs,   sc4, sc4, sc4hntcsm, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
	26878	GAME( 200?, sc4hntcsc   ,sc4hntcs,   sc4, sc4, sc4hntcsm, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
26683	26879	// PR1327 CASINO HAPPY NOTES         PR1327 CAS_HAPPY_NOTES SOUNDS11
26684		GAME( 200?, sc4hntcsd   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
26685		GAME( 200?, sc4hntcse   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
26686		GAME( 200?, sc4hntcsf   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
26687		GAME( 200?, sc4hntcsg   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
26688		GAME( 200?, sc4hntcsh   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL )
26689		GAME( 200?, sc4hntcsi   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )
26690		GAME( 200?, sc4hntcsj   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 11)", GAME_IS_SKELETON_MECHANICAL )
26691		GAME( 200?, sc4hntcsk   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 12)", GAME_IS_SKELETON_MECHANICAL )
26692		GAME( 200?, sc4hntcsl   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 13)", GAME_IS_SKELETON_MECHANICAL )
26693		GAME( 200?, sc4hntcsm   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 14)", GAME_IS_SKELETON_MECHANICAL )
26694		GAME( 200?, sc4hntcsn   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 15)", GAME_IS_SKELETON_MECHANICAL )
26695		GAME( 200?, sc4hntcso   ,sc4hntcs,   sc4, sc4, sc4, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 16)", GAME_IS_SKELETON_MECHANICAL )
	26880	GAME( 200?, sc4hntcsd   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
	26881	GAME( 200?, sc4hntcse   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
	26882	GAME( 200?, sc4hntcsf   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
	26883	GAME( 200?, sc4hntcsg   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )
	26884	GAME( 200?, sc4hntcsh   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL )
	26885	GAME( 200?, sc4hntcsi   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )
	26886	GAME( 200?, sc4hntcsj   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 11)", GAME_IS_SKELETON_MECHANICAL )
	26887	GAME( 200?, sc4hntcsk   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 12)", GAME_IS_SKELETON_MECHANICAL )
	26888	GAME( 200?, sc4hntcsl   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 13)", GAME_IS_SKELETON_MECHANICAL )
	26889	GAME( 200?, sc4hntcsm   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 14)", GAME_IS_SKELETON_MECHANICAL )
	26890	GAME( 200?, sc4hntcsn   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 15)", GAME_IS_SKELETON_MECHANICAL )
	26891	GAME( 200?, sc4hntcso   ,sc4hntcs,   sc4, sc4, sc4hntcs, ROT0, "BFM","Happy Notes Casino (Bellfruit) (Scorpion 4) (set 16)", GAME_IS_SKELETON_MECHANICAL )
26696	26892
26697	26893
26698	26894
26699	26895
26700	26896	// PR1201 HELLS BELLS         95004211 HELLS BELLS PR6945         HELLS  BELLS  (non english?)
26701		GAME( 200?, sc4hellb   ,0,         sc4, sc4, sc4, ROT0, "BFM","Hells Bells (PR1201) (Dutch?) (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	26897	GAME( 200?, sc4hellb   ,0,         sc4, sc4, sc4, ROT0, "BFM / Eurocoin","Hells Bells (PR1201) (Dutch?) (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26702	26898	// PR1419 AWP HELLS BELLS         PR1402 HELLS BELLS SOUNDS11
26703	26899	GAME( 200?, sc4hellba   ,sc4hellb,   sc4, sc4, sc4, ROT0, "BFM","Hells Bells (PR1419) (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26704	26900	GAME( 200?, sc4hellbb   ,sc4hellb,   sc4, sc4, sc4, ROT0, "BFM","Hells Bells (PR1419) (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
r14963	r14964
26712	26908	GAME( 200?, sc4hellbi   ,sc4hellb,   sc4, sc4, sc4mbus, ROT0, "BFM","Hells Bells (PR1419) (Bellfruit) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL )
26713	26909	GAME( 200?, sc4hellbj   ,sc4hellb,   sc4, sc4, sc4mbus, ROT0, "BFM","Hells Bells (PR1419) (Bellfruit) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )
26714	26910
	26911	const stepper_interface* sc4hill_reel_configs[6] =
	26912	{
	26913	&starpoint_interface_48step,
	26914	&starpoint_interface_48step,
	26915	&starpoint_interface_48step,
	26916	0,
	26917	&starpoint_interface_200step_reel,
	26918	0,
	26919	};
	26920
	26921	static DRIVER_INIT( sc4hill )
	26922	{
	26923	sc4_state *state = machine.driver_data<sc4_state>();
	26924	DRIVER_INIT_CALL( sc4mbus );
	26925	state->m_reel_setup = sc4hill_reel_configs;
	26926	}
	26927
26715	26928	// PR1643 AWP HILLBILLIONAIRE SCORP4         PR1613 HILLBILLIONAIRE SOUNDS11   HILLBILLIONAIRE S.SITE
26716		GAME( 200?, sc4hill      ,0,         sc4, sc4, sc4, ROT0, "BFM","Hill Billionaire (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
26717		GAME( 200?, sc4hilla   ,sc4hill,   sc4, sc4, sc4, ROT0, "BFM","Hill Billionaire (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	26929	GAME( 200?, sc4hill      ,0,         sc4, sc4, sc4hill, ROT0, "BFM","Hill Billionaire (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	26930	GAME( 200?, sc4hilla   ,sc4hill,   sc4, sc4, sc4hill, ROT0, "BFM","Hill Billionaire (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
26718	26931
26719	26932	// PR2176 HISSING QUID         VIPA SOUNDS         HISSING QUID
26720	26933	GAME( 200?, sc4hiss      ,0,         sc4, sc4, sc4, ROT0, "Qps","Hissing Quid (Qps) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
r14963	r14964
27313	27526	GAME( 200?, sc4copsrh   ,sc4copsr,   sc4, sc4, sc4, ROT0, "BFM","Cops 'n' Robbers (Bellfruit) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL )
27314	27527	GAME( 200?, sc4copsri   ,sc4copsr,   sc4, sc4, sc4, ROT0, "BFM","Cops 'n' Robbers (Bellfruit) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )
27315	27528
	27529	/* wrong sound roms */
	27530	GAME( 200?, sc4mowow   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (PR2118) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL ) // PR2118 MONOPOLY WOTW         WOTW SOUNDS         MONOPOLY WOTW   8P
	27531	GAME( 200?, sc4mowowa   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (PR2118) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27532	GAME( 200?, sc4mowowb   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (PR2118) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27533	GAME( 200?, sc4mowowc   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (PR2118) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27316	27534
27317		GAME( 200?, sc4mowow   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL ) // PR2118 MONOPOLY WOTW         WOTW SOUNDS         MONOPOLY WOTW   8P
27318		GAME( 200?, sc4mowowa   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27319		GAME( 200?, sc4mowowb   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27320		GAME( 200?, sc4mowowc   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27321		GAME( 200?, sc4mowowd   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL ) // PR1726 AWP WHEEL OF WEALTH         PR1706 WHEEL OF WEALTH SOUNDS11   WHEEL OF WEALTH S.SITE
27322		GAME( 200?, sc4mowowe   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27323		GAME( 200?, sc4mowowf   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL ) // PR2389  WHEEL OF WEALTH         WOWT SOUNDS         WHEEL OF WEAL
27324		GAME( 200?, sc4mowowg   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27325		GAME( 200?, sc4mowowh   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27326		GAME( 200?, sc4mowowi   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )// ^^
27327		GAME( 200?, sc4mowowj   ,sc4mowow,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (Scorpion 4) (set 11)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27535	GAME( 200?, sc4mwwtb   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (PR2389, Top Box) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL ) // PR2389  WHEEL OF WEALTH         WOWT SOUNDS         WHEEL OF WEAL
	27536	GAME( 200?, sc4mwwtba   ,sc4mwwtb,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (PR2389, Top Box) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27537	GAME( 200?, sc4mwwtbb   ,sc4mwwtb,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (PR2389, Top Box) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27538	GAME( 200?, sc4mwwtbc   ,sc4mwwtb,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (PR2389, Top Box) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27539	GAME( 200?, sc4mwwtbd   ,sc4mwwtb,   sc4, sc4, sc4, ROT0, "Mazooma","Monopoly Wheel Of Wealth (Mazooma) (PR2389, Top Box) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )// ^^
27328	27540
	27541
	27542	const stepper_interface* sc4bwow_reel_configs[6] =
	27543	{
	27544	&starpoint_interface_48step,
	27545	&starpoint_interface_48step,
	27546	&starpoint_interface_48step,
	27547	0,
	27548	&starpoint_interface_48step,
	27549	&starpoint_interface_200step_reel,
	27550	};
	27551
	27552	static DRIVER_INIT( sc4bwow )
	27553	{
	27554	sc4_state *state = machine.driver_data<sc4_state>();
	27555	DRIVER_INIT_CALL( sc4mbus );
	27556	state->m_reel_setup = sc4bwow_reel_configs;
	27557	}
	27558
	27559	GAME( 200?, sc4bwow     ,0,       sc4, sc4, sc4bwow, ROT0, "BFM","Wheel Of Wealth (Bellfruit) (PR1726) (Scorpion 4) (WHEL013, set 1)", GAME_IS_SKELETON_MECHANICAL ) // PR1726 AWP WHEEL OF WEALTH         PR1706 WHEEL OF WEALTH SOUNDS11   WHEEL OF WEALTH S.SITE
	27560	GAME( 200?, sc4bwowa  ,sc4bwow,   sc4, sc4, sc4bwow, ROT0, "BFM","Wheel Of Wealth (Bellfruit) (PR1726) (Scorpion 4) (WHEL013, set 2)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27561
	27562
27329	27563	// PR2166 NUN N ROSES          NANR SOUNDS         NUNS N ROSES
27330	27564	GAME( 200?, sc4nunsm   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Nuns 'n' Roses (Mazooma) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
27331	27565	GAME( 200?, sc4nunsmb   ,sc4nunsm,   sc4, sc4, sc4, ROT0, "Mazooma","Nuns 'n' Roses (Mazooma) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
r14963	r14964
27357	27591	GAME( 200?, sc4gncd      ,sc4gnc,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Club (Mazooma) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )
27358	27592	GAME( 200?, sc4gnce      ,sc4gnc,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Club (Mazooma) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )
27359	27593
27360		GAME( 200?, sc4ggame   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL ) // PR2056  GOLD X TRIPLE         BARX SOUNDS         GOLD X TRIPLE
27361		GAME( 200?, sc4ggamee   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27362		GAME( 200?, sc4ggameo   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 16)", GAME_IS_SKELETON_MECHANICAL )// ^^
27363		GAME( 200?, sc4ggameh   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL ) // PR2056  GOLDEN X         GOLDEN GAME ARCADE  BARX SOUNDS         GOLDEN X
27364		GAME( 200?, sc4ggamei   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )// ^^
27365		GAME( 200?, sc4ggamel   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 13)", GAME_IS_SKELETON_MECHANICAL )// ^^
27366		GAME( 200?, sc4ggamem   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 14)", GAME_IS_SKELETON_MECHANICAL )// ^^
27367		GAME( 200?, sc4ggamep   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 17)", GAME_IS_SKELETON_MECHANICAL )// ^^
27368		GAME( 200?, sc4ggameq   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 18)", GAME_IS_SKELETON_MECHANICAL )// ^^
27369		GAME( 200?, sc4ggamer   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 19)", GAME_IS_SKELETON_MECHANICAL )// ^^
27370		GAME( 200?, sc4ggamew   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 24)", GAME_IS_SKELETON_MECHANICAL )// ^^
27371		GAME( 200?, sc4ggamex   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 25)", GAME_IS_SKELETON_MECHANICAL )// ^^
27372		GAME( 200?, sc4ggamey   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 26)", GAME_IS_SKELETON_MECHANICAL )// ^^
27373		GAME( 200?, sc4ggamez   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 27)", GAME_IS_SKELETON_MECHANICAL )// ^^
27374		GAME( 200?, sc4ggame1   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 29)", GAME_IS_SKELETON_MECHANICAL )// ^^
27375		GAME( 200?, sc4ggame2   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 30)", GAME_IS_SKELETON_MECHANICAL )// ^^
27376		GAME( 200?, sc4ggame7   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 35)", GAME_IS_SKELETON_MECHANICAL )// ^^
27377		GAME( 200?, sc4ggame8   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 36)", GAME_IS_SKELETON_MECHANICAL )// ^^
27378		GAME( 200?, sc4ggame9   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 37)", GAME_IS_SKELETON_MECHANICAL )// ^^
27379		GAME( 200?, sc4ggameaa   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 38)", GAME_IS_SKELETON_MECHANICAL )// ^^
27380		GAME( 200?, sc4ggameab   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 39)", GAME_IS_SKELETON_MECHANICAL )// ^^
27381		GAME( 200?, sc4ggameac   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 40)", GAME_IS_SKELETON_MECHANICAL )// ^^
27382		GAME( 200?, sc4ggamead   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 41)", GAME_IS_SKELETON_MECHANICAL )// ^^
27383		GAME( 200?, sc4ggameae   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 42)", GAME_IS_SKELETON_MECHANICAL )// ^^
27384		GAME( 200?, sc4ggamea   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL ) // PR2056  GOLDEN X         BARX SOUNDS         GOLDEN X
27385		GAME( 200?, sc4ggameb   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27386		GAME( 200?, sc4ggamec   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27387		GAME( 200?, sc4ggamed   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27388		GAME( 200?, sc4ggamef   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27389		GAME( 200?, sc4ggameg   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27390		GAME( 200?, sc4ggamej   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 11)", GAME_IS_SKELETON_MECHANICAL )// ^^
27391		GAME( 200?, sc4ggamek   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 12)", GAME_IS_SKELETON_MECHANICAL )// ^^
27392		GAME( 200?, sc4ggamen   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 15)", GAME_IS_SKELETON_MECHANICAL )// ^^
27393		GAME( 200?, sc4ggames   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 20)", GAME_IS_SKELETON_MECHANICAL )// ^^
27394		GAME( 200?, sc4ggamet   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 21)", GAME_IS_SKELETON_MECHANICAL )// ^^
27395		GAME( 200?, sc4ggameu   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 22)", GAME_IS_SKELETON_MECHANICAL )// ^^
27396		GAME( 200?, sc4ggamev   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 23)", GAME_IS_SKELETON_MECHANICAL )// ^^
27397		GAME( 200?, sc4ggame0   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 28)", GAME_IS_SKELETON_MECHANICAL )// ^^
27398		GAME( 200?, sc4ggame3   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 31)", GAME_IS_SKELETON_MECHANICAL )// ^^
27399		GAME( 200?, sc4ggame4   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 32)", GAME_IS_SKELETON_MECHANICAL )// ^^
27400		GAME( 200?, sc4ggame5   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 33)", GAME_IS_SKELETON_MECHANICAL )// ^^
27401		GAME( 200?, sc4ggame6   ,sc4ggame,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (Scorpion 4) (set 34)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27594	GAME( 200?, sc4ggtb       ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, Top Box) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL ) // PR2056  GOLD X TRIPLE         BARX SOUNDS         GOLD X TRIPLE
	27595	GAME( 200?, sc4ggtba   ,sc4ggtb,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, Top Box) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27596	GAME( 200?, sc4ggtbb   ,sc4ggtb,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, Top Box) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )// ^^
27402	27597
	27598	const stepper_interface* sc4ggame_reel_configs[6] =
	27599	{
	27600	&starpoint_interface_200step_reel,
	27601	&starpoint_interface_200step_reel,
	27602	&starpoint_interface_200step_reel,
	27603	0,
	27604	0,
	27605	0,
	27606	};
	27607
	27608	static DRIVER_INIT( sc4ggamem )
	27609	{
	27610	sc4_state *state = machine.driver_data<sc4_state>();
	27611	DRIVER_INIT_CALL( sc4mbus );
	27612	state->m_reel_setup = sc4ggame_reel_configs;
	27613	}
	27614
	27615	static DRIVER_INIT( sc4ggame )
	27616	{
	27617	sc4_state *state = machine.driver_data<sc4_state>();
	27618	DRIVER_INIT_CALL( sc4 );
	27619	state->m_reel_setup = sc4ggame_reel_configs;
	27620	}
	27621
	27622	// 25GBP sets
	27623	// PR2056  GOLDEN X         GOLDEN GAME ARCADE  BARX SOUNDS         GOLDEN X
	27624	GAME( 200?, sc4ggame   ,0,           sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 25GBP, set 1)", GAME_IS_SKELETON_MECHANICAL )
	27625	GAME( 200?, sc4ggamei   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 25GBP, set 2)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27626	GAME( 200?, sc4ggamep   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 25GBP, set 3)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27627	GAME( 200?, sc4ggameq   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 25GBP, set 4)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27628	GAME( 200?, sc4ggamer   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 25GBP, set 5)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27629	// 35GBP sets
	27630	GAME( 200?, sc4ggame7   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 35GBP, set 1)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27631	GAME( 200?, sc4ggame8   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 35GBP, set 2)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27632	GAME( 200?, sc4ggame9   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 35GBP, set 3)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27633	GAME( 200?, sc4ggameaa   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 35GBP, set 4)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27634	GAME( 200?, sc4ggameab   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 35GBP, set 5)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27635	GAME( 200?, sc4ggameac   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 35GBP, set 6)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27636	GAME( 200?, sc4ggamead   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 35GBP, set 7)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27637	GAME( 200?, sc4ggameae   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (GLDX, 35GBP, set 8)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27638	// pay unit error
	27639	GAME( 200?, sc4ggamel   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27640	GAME( 200?, sc4ggamem   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27641	GAME( 200?, sc4ggamew   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27642	GAME( 200?, sc4ggamex   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27643	GAME( 200?, sc4ggamey   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27644	GAME( 200?, sc4ggamez   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27645	GAME( 200?, sc4ggame1   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27646	GAME( 200?, sc4ggame2   ,sc4ggame,   sc4, sc4, sc4ggamem, ROT0, "Mazooma","Golden Game (Mazooma) (PR2056, newer?) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27647	// 25GBP, no 41 check
	27648	// PR2056  GOLDEN X         BARX SOUNDS         GOLDEN X
	27649	GAME( 200?, sc4ggamea   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 25GBP, set 1)", GAME_IS_SKELETON_MECHANICAL )
	27650	GAME( 200?, sc4ggameb   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 25GBP, set 2)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27651	GAME( 200?, sc4ggamec   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 25GBP, set 3)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27652	GAME( 200?, sc4ggamed   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 25GBP, set 4)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27653	GAME( 200?, sc4ggames   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 25GBP, set 5)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27654	GAME( 200?, sc4ggamet   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 25GBP, set 6)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27655	GAME( 200?, sc4ggameu   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 25GBP, set 7)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27656	// 30GBP, no 41 check
	27657	GAME( 200?, sc4ggamef   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 30GBP, set 1)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27658	GAME( 200?, sc4ggameg   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 30GBP, set 2)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27659	GAME( 200?, sc4ggamej   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 30GBP, set 3)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27660	GAME( 200?, sc4ggamek   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 30GBP, set 4)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27661	GAME( 200?, sc4ggamev   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 30GBP, set 5)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27662	GAME( 200?, sc4ggame3   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 30GBP, set 6)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27663	GAME( 200?, sc4ggame4   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 30GBP, set 7)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27664	GAME( 200?, sc4ggame5   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 30GBP, set 8)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27665	GAME( 200?, sc4ggame6   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (GLDX, 30GBP, set 9)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27666	// pay unit error
	27667	GAME( 200?, sc4ggamen   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27668	GAME( 200?, sc4ggame0   ,sc4ggame,   sc4, sc4, sc4ggame,  ROT0, "Mazooma","Golden Game (Mazooma) (PR2056) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27669
	27670
27403	27671	// these were in the above sets
27404		GAME( 200?, sc4ggdlx   ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )// PR2201  GOLDEN X         GOLDEN GAME MAZ GXDX SOUNDS         GOLDEN GAME DLX
27405		GAME( 200?, sc4ggdlxc   ,sc4ggdlx,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )// ^^
27406		GAME( 200?, sc4ggdlxa   ,sc4ggdlx,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )// PR2201  GOLDEN X         GOLDEN GAME DLX MAZ GXDX SOUNDS         GOLDEN X
27407		GAME( 200?, sc4ggdlxb   ,sc4ggdlx,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )// ^^
27408		GAME( 200?, sc4ggdlxd   ,sc4ggdlx,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )// ^^
27409		GAME( 200?, sc4ggdlxe   ,sc4ggdlx,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )// ^^
27410		GAME( 200?, sc4ggdlxf   ,sc4ggdlx,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )// PR2201  GOLDEN GAME DELUXE         GOLDEN GAME MAZ GXDX SOUNDS         GOLDEN GAME DLX
27411		GAME( 200?, sc4ggdlxg   ,sc4ggdlx,   sc4, sc4, sc4, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27672	// PR2201  GOLDEN X         GOLDEN GAME MAZ GXDX SOUNDS         GOLDEN GAME DLX
	27673	GAME( 200?, sc4ggdlx   ,0,         sc4, sc4, sc4ggame, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (PR2201) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
	27674	GAME( 200?, sc4ggdlxc   ,sc4ggdlx,   sc4, sc4, sc4ggame, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (PR2201) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27675	// PR2201  GOLDEN X         GOLDEN GAME DLX MAZ GXDX SOUNDS         GOLDEN X
	27676	GAME( 200?, sc4ggdlxa   ,sc4ggdlx,   sc4, sc4, sc4ggame, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (PR2201) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
	27677	GAME( 200?, sc4ggdlxb   ,sc4ggdlx,   sc4, sc4, sc4ggame, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (PR2201) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27678	GAME( 200?, sc4ggdlxd   ,sc4ggdlx,   sc4, sc4, sc4ggame, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (PR2201) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27679	GAME( 200?, sc4ggdlxe   ,sc4ggdlx,   sc4, sc4, sc4ggame, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (PR2201) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27680	// PR2201  GOLDEN GAME DELUXE         GOLDEN GAME MAZ GXDX SOUNDS         GOLDEN GAME DLX
	27681	GAME( 200?, sc4ggdlxf   ,sc4ggdlx,   sc4, sc4, sc4ggame, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (PR2201) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL )
	27682	GAME( 200?, sc4ggdlxg   ,sc4ggdlx,   sc4, sc4, sc4ggame, ROT0, "Mazooma","Golden Game Deluxe (Mazooma) (PR2201) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27683
	27684	const stepper_interface* sc4gggtb_reel_configs[6] =
	27685	{
	27686	&starpoint_interface_48step,
	27687	&starpoint_interface_48step,
	27688	&starpoint_interface_48step,
	27689	&starpoint_interface_48step,
	27690	&starpoint_interface_48step,
	27691	&starpoint_interface_48step,
	27692	};
	27693
	27694	static DRIVER_INIT( sc4gggtb )
	27695	{
	27696	sc4_state *state = machine.driver_data<sc4_state>();
	27697	DRIVER_INIT_CALL( sc4 );
	27698	state->m_reel_setup = sc4gggtb_reel_configs;
	27699	}
	27700
27412	27701	// most of these look similar
27413		GAME( 200?, sc4ggg      ,0,         sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL ) // PR2056  GOLD X TRIPLE         BARX SOUNDS           GOLD X TRIPLE
27414		GAME( 200?, sc4gggj      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 11)", GAME_IS_SKELETON_MECHANICAL )// ^^
27415		GAME( 200?, sc4ggga      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL ) // PR2056  GOLDEN X         GOLDEN GAME ARCADE  BARX SOUNDS         GOLDEN X
27416		GAME( 200?, sc4gggb      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27417		GAME( 200?, sc4gggc      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27418		GAME( 200?, sc4gggd      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 5)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27419		GAME( 200?, sc4ggge      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 6)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27420		GAME( 200?, sc4gggf      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 7)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27421		GAME( 200?, sc4gggk      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 12)", GAME_IS_SKELETON_MECHANICAL )// ^^
27422		GAME( 200?, sc4gggl      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 13)", GAME_IS_SKELETON_MECHANICAL )// ^^
27423		GAME( 200?, sc4gggm      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 14)", GAME_IS_SKELETON_MECHANICAL )// ^^
27424		GAME( 200?, sc4gggn      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 15)", GAME_IS_SKELETON_MECHANICAL )// ^^
27425		GAME( 200?, sc4gggo      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 16)", GAME_IS_SKELETON_MECHANICAL )// ^^
27426		GAME( 200?, sc4gggp      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 17)", GAME_IS_SKELETON_MECHANICAL )// ^^
27427		GAME( 200?, sc4gggg      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 8)", GAME_IS_SKELETON_MECHANICAL ) // PR2353 GRAND GOLDEN GAME         GRAND GOLDEN GAME MAZ BARX SOUNDS         GOLDEN GAME
27428		GAME( 200?, sc4gggh      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 9)", GAME_IS_SKELETON_MECHANICAL ) // ^^
27429		GAME( 200?, sc4gggi      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 10)", GAME_IS_SKELETON_MECHANICAL )// ^^
27430		GAME( 200?, sc4gggq      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 18)", GAME_IS_SKELETON_MECHANICAL )// ^^
27431		GAME( 200?, sc4gggr      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 19)", GAME_IS_SKELETON_MECHANICAL )// ^^
27432		GAME( 200?, sc4gggs      ,sc4ggg,   sc4, sc4, sc4, ROT0, "Mazooma","Grand Golden Game (Mazooma) (Scorpion 4) (set 20)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27702	GAME( 200?, sc4gggtb      ,0,         sc4, sc4, sc4gggtb, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056, Top Box) (Scorpion 4) (GGGT, set 1)", GAME_IS_SKELETON_MECHANICAL ) // PR2056  GOLD X TRIPLE         BARX SOUNDS           GOLD X TRIPLE
	27703	GAME( 200?, sc4gggtba      ,sc4ggg,   sc4, sc4, sc4gggtb, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056, Top Box) (Scorpion 4) (GGGT, set 2)", GAME_IS_SKELETON_MECHANICAL )// ^^
27433	27704
27434	27705
	27706	const stepper_interface* sc4ggg_reel_configs[6] =
	27707	{
	27708	&starpoint_interface_200step_reel,
	27709	&starpoint_interface_200step_reel,
	27710	&starpoint_interface_200step_reel,
	27711	0,
	27712	0,
	27713	0,
	27714	};
	27715
	27716	static DRIVER_INIT( sc4ggg )
	27717	{
	27718	sc4_state *state = machine.driver_data<sc4_state>();
	27719	DRIVER_INIT_CALL( sc4 );
	27720	state->m_reel_setup = sc4ggg_reel_configs;
	27721	}
	27722
	27723	// do these sets have the wrong project name / ID strings? they boot at GGGB (Grand Golden Game) but their product ID in the header suggests standard Golden Game
	27724	// PR2056  GOLDEN X         GOLDEN GAME ARCADE  BARX SOUNDS         GOLDEN X
	27725	GAME( 200?, sc4ggg      ,0,        sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 1)", GAME_IS_SKELETON_MECHANICAL )
	27726	GAME( 200?, sc4gggb      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 2)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27727	GAME( 200?, sc4gggc      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 3)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27728	GAME( 200?, sc4gggd      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 4)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27729	GAME( 200?, sc4ggge      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 5)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27730	GAME( 200?, sc4gggf      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 6)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27731	GAME( 200?, sc4gggk      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 7)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27732	GAME( 200?, sc4gggl      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 8)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27733	GAME( 200?, sc4gggm      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 9)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27734	GAME( 200?, sc4gggn      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 10)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27735	GAME( 200?, sc4gggo      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 11)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27736	GAME( 200?, sc4gggp      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 12)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27737	GAME( 200?, sc4gggg      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2056) (Scorpion 4) (GGGB, 35GBP, set 13)", GAME_IS_SKELETON_MECHANICAL )
	27738	// PR2353 GRAND GOLDEN GAME         GRAND GOLDEN GAME MAZ BARX SOUNDS         GOLDEN GAME
	27739	GAME( 200?, sc4gggh      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2353) (Scorpion 4) (GGGB, 35GBP, set 1)", GAME_IS_SKELETON_MECHANICAL ) // ^^
	27740	GAME( 200?, sc4gggi      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2353) (Scorpion 4) (GGGB, 35GBP, set 2)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27741	GAME( 200?, sc4gggq      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2353) (Scorpion 4) (GGGB, 35GBP, set 3)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27742	GAME( 200?, sc4gggr      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2353) (Scorpion 4) (GGGB, 35GBP, set 4)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27743	GAME( 200?, sc4gggs      ,sc4ggg,   sc4, sc4, sc4ggg, ROT0, "Mazooma","Grand Golden Game (Mazooma) (PR2353) (Scorpion 4) (GGGB, 35GBP, set 5)", GAME_IS_SKELETON_MECHANICAL )// ^^
	27744
	27745
27435	27746	// PR1227 4PLAY ART13         95004313 4PLAY PR1227
27436	27747	GAME( 200?, sc4ivply   ,0,         sc4, sc4, sc4, ROT0, "BFM","4 Play (Bellfruit) (Scorpion 4)", GAME_IS_SKELETON_MECHANICAL ) // not english
27437	27748
r14963	r14964
27615	27926	GAME( 200?, sc4ctlcl   ,0,         sc4, sc4, sc4, ROT0, "BFM","Cop The Lot Club (Bellfruit) (Scorpion 4) (set 1)", GAME_IS_SKELETON_MECHANICAL )
27616	27927	GAME( 200?, sc4ctlcla   ,sc4ctlcl,   sc4, sc4, sc4, ROT0, "BFM","Cop The Lot Club (Bellfruit) (Scorpion 4) (set 2)", GAME_IS_SKELETON_MECHANICAL )
27617	27928	// PR1036 CLUB COP THE LOT         COP THE LOT CLUB  PR1036 CLOT SOUNDS11           COP THE LOT
	27929	// shows nothing, but alarms, do these go with the ad4 video roms?
27618	27930	GAME( 200?, sc4ctlclb   ,sc4ctlcl,   sc4, sc4, sc4, ROT0, "BFM","Cop The Lot Club (Bellfruit) (Scorpion 4) (set 3)", GAME_IS_SKELETON_MECHANICAL )
27619	27931	GAME( 200?, sc4ctlclc   ,sc4ctlcl,   sc4, sc4, sc4, ROT0, "BFM","Cop The Lot Club (Bellfruit) (Scorpion 4) (set 4)", GAME_IS_SKELETON_MECHANICAL )
27620	27932

src/mame/drivers/byvid.c

r14963	r14964
23	23	// devices
24	24	required_device<cpu_device> m_maincpu;
25	25	required_device<cpu_device> m_videocpu;
26		required_device<cpu_device> m_pia;
	26	required_device<pia6821_device> m_pia;
27	27
28	28	DECLARE_INPUT_CHANGED_MEMBER(test_switch_press);
29	29	//  UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);

src/mame/drivers/cps1.c

r14963	r14964
3015	3015
3016	3016	static const ym2151_interface ym2151_config =
3017	3017	{
3018		cps1_irq_handler_mus
	3018	DEVCB_LINE(cps1_irq_handler_mus)
3019	3019	};
3020	3020
3021	3021

src/mame/drivers/hyprduel.c

r14963	r14964
436	436	AM_RANGE(0x4788ac, 0x4788ad) AM_RAM AM_SHARE("screenctrl")   /* Screen Control */
437	437	AM_RANGE(0x479700, 0x479713) AM_RAM AM_SHARE("videoregs")   /* Video Registers */
438	438	AM_RANGE(0x800000, 0x800001) AM_WRITE(hyprduel_subcpu_control_w)
439		AM_RANGE(0xc00000, 0xc07fff) AM_RAM AM_SHARE("share1") AM_SHARE("sharedram1")
	439	AM_RANGE(0xc00000, 0xc07fff) AM_RAM AM_SHARE("sharedram1")
440	440	AM_RANGE(0xe00000, 0xe00001) AM_READ_PORT("SERVICE") AM_WRITENOP
441	441	AM_RANGE(0xe00002, 0xe00003) AM_READ_PORT("DSW")
442	442	AM_RANGE(0xe00004, 0xe00005) AM_READ_PORT("P1_P2")
443	443	AM_RANGE(0xe00006, 0xe00007) AM_READ_PORT("SYSTEM")
444	444	AM_RANGE(0xfe0000, 0xfe3fff) AM_RAM AM_SHARE("share2")
445		AM_RANGE(0xfe4000, 0xffffff) AM_RAM AM_SHARE("share3") AM_SHARE("sharedram3")
	445	AM_RANGE(0xfe4000, 0xffffff) AM_RAM AM_SHARE("sharedram3")
446	446	ADDRESS_MAP_END
447	447
448	448	static ADDRESS_MAP_START( hyprduel_map2, AS_PROGRAM, 16, hyprduel_state )
r14963	r14964
628	628
629	629	static const ym2151_interface ym2151_config =
630	630	{
631		sound_irq
	631	DEVCB_LINE(sound_irq)
632	632	};
633	633
634	634	/***************************************************************************

src/mame/drivers/bmcbowl.c

r14963	r14964
112	112	public:
113	113	bmcbowl_state(const machine_config &mconfig, device_type type, const char *tag)
114	114	: driver_device(mconfig, type, tag) ,
115		m_stats_ram(*this, "stats_ram"),
	115	m_stats_ram(*this, "stats_ram", 16),
116	116	m_vid1(*this, "vid1"),
117	117	m_vid2(*this, "vid2"){ }
118	118

src/mame/drivers/lemmings.c

r14963	r14964
249	249
250	250	static const ym2151_interface ym2151_config =
251	251	{
252		sound_irq
	252	DEVCB_LINE(sound_irq)
253	253	};
254	254
255	255	static MACHINE_START( lemmings )

src/mame/drivers/tmnt.c

r14963	r14964
2038	2038
2039	2039	static const ym2151_interface ym2151_interface_cbj =
2040	2040	{
2041		cuebrick_irq_handler
	2041	DEVCB_LINE(cuebrick_irq_handler)
2042	2042	};
2043	2043
2044	2044	static void volume_callback(device_t *device, int v)

src/mame/drivers/funkyjet.c

r14963	r14964
283	283
284	284	static const ym2151_interface ym2151_config =
285	285	{
286		sound_irq
	286	DEVCB_LINE(sound_irq)
287	287	};
288	288
289	289	static const deco16ic_interface funkyjet_deco16ic_tilegen1_intf =

src/mame/drivers/cps3.c

r14963	r14964
620	620
621	621
622	622
623		DIRECT_UPDATE_HANDLER( cps3_direct_handler );
624
625	623	/* Encryption */
626	624
627	625
r14963	r14964
724	722	state->m_0xc0000000_ram_decrypted = auto_alloc_array(machine, UINT32, 0x400/4);
725	723
726	724	address_space *main = machine.device<sh2_device>("maincpu")->space(AS_PROGRAM);
727		main->set_direct_update_handler(direct_update_delegate(FUNC(cps3_direct_handler), &machine));
	725	main->set_direct_update_handler(direct_update_delegate(FUNC(cps3_state::cps3_direct_handler), state));
728	726
729	727	// flash roms
730	728	astring tempstr;
r14963	r14964
1278	1276
1279	1277
1280	1278
1281		DIRECT_UPDATE_HANDLER( cps3_direct_handler )
	1279	DIRECT_UPDATE_MEMBER(cps3_state::cps3_direct_handler)
1282	1280	{
1283		cps3_state *state = machine.driver_data<cps3_state>();
1284	1281	//  if(DEBUG_PRINTF) printf("address %04x\n",address);
1285	1282
1286	1283	/* BIOS ROM */
r14963	r14964
1292	1289	/* RAM */
1293	1290	else if (address >= 0x06000000 && address <= 0x06ffffff)
1294	1291	{
1295		UINT8 *decrypted = (UINT8*)state->m_decrypted_gamerom;
	1292	UINT8 *decrypted = (UINT8*)m_decrypted_gamerom;
1296	1293	UINT8 *raw = decrypted;
1297	1294
1298		if (state->m_altEncryption) raw = (UINT8*) state->m_user4region;
	1295	if (m_altEncryption) raw = (UINT8*) m_user4region;
1299	1296
1300	1297	direct.explicit_configure(0x06000000, 0x06ffffff, 0x00ffffff, raw, decrypted);
1301	1298
r14963	r14964
1303	1300	}
1304	1301	else if (address >= 0xc0000000 && address <= 0xc00003ff)
1305	1302	{
1306		//direct->decrypted = (void*)state->m_0xc0000000_ram_decrypted;
1307		direct.explicit_configure(0xc0000000, 0xc00003ff, 0x3ff, (UINT8*)state->m_0xc0000000_ram.target(), (UINT8*)state->m_0xc0000000_ram_decrypted);
	1303	//direct->decrypted = (void*)m_0xc0000000_ram_decrypted;
	1304	direct.explicit_configure(0xc0000000, 0xc00003ff, 0x3ff, (UINT8*)m_0xc0000000_ram.target(), (UINT8*)m_0xc0000000_ram_decrypted);
1308	1305	return ~0;
1309	1306	}
1310	1307
1311	1308	/* anything else falls through to NOPs */
1312		direct.explicit_configure(address, address, 0, (UINT8*)state->m_nops, (UINT8*)state->m_nops);
	1309	direct.explicit_configure(address, address, 0, (UINT8*)m_nops, (UINT8*)m_nops);
1313	1310	return ~0;
1314	1311	}
1315	1312

src/mame/drivers/subsino.c

r14963	r14964
3555	3555	rom[0x957] = 0x18; //patch "losing protection" check
3556	3556	state->m_stisub_colorram = auto_alloc_array(machine, UINT8, 256*3);
3557	3557
3558		//state->m_reel1_scroll = auto_alloc_array(machine, UINT8, 0x40);
3559		//state->m_reel2_scroll = auto_alloc_array(machine, UINT8, 0x40);
3560		//state->m_reel3_scroll = auto_alloc_array(machine, UINT8, 0x40);
	3558	state->m_reel1_scroll.allocate(0x40);
	3559	state->m_reel2_scroll.allocate(0x40);
	3560	state->m_reel3_scroll.allocate(0x40);
3561	3561
3562	3562	state->m_reel1_attr = auto_alloc_array(machine, UINT8, 0x200);
3563	3563	state->m_reel2_attr = auto_alloc_array(machine, UINT8, 0x200);
r14963	r14964
3569	3569	subsino_state *state = machine.driver_data<subsino_state>();
3570	3570	state->m_stisub_colorram = auto_alloc_array(machine, UINT8, 256*3);
3571	3571
3572		//state->m_reel1_scroll = auto_alloc_array(machine, UINT8, 0x40);
3573		//state->m_reel2_scroll = auto_alloc_array(machine, UINT8, 0x40);
3574		//state->m_reel3_scroll = auto_alloc_array(machine, UINT8, 0x40);
	3572	state->m_reel1_scroll.allocate(0x40);
	3573	state->m_reel2_scroll.allocate(0x40);
	3574	state->m_reel3_scroll.allocate(0x40);
3575	3575
3576	3576	state->m_reel1_attr = auto_alloc_array(machine, UINT8, 0x200);
3577	3577	state->m_reel2_attr = auto_alloc_array(machine, UINT8, 0x200);

src/mame/drivers/mlanding.c

r14963	r14964
738	738
739	739	static const ym2151_interface ym2151_config =
740	740	{
741		irq_handler,
742		sound_bankswitch_w
	741	DEVCB_LINE(irq_handler),
	742	DEVCB_HANDLER(sound_bankswitch_w)
743	743	};
744	744
745	745	static const tc0140syt_interface mlanding_tc0140syt_intf =

src/mame/drivers/atarisy1.c

r14963	r14964
744	744
745	745	static const ym2151_interface ym2151_config =
746	746	{
747		atarigen_ym2151_irq_gen
	747	DEVCB_LINE(atarigen_ym2151_irq_gen)
748	748	};
749	749
750	750

src/mame/drivers/atarig42.c

r14963	r14964
135	135	*
136	136	*************************************/
137	137
138		DIRECT_UPDATE_HANDLER( atarig42_sloop_direct_handler )
	138	DIRECT_UPDATE_MEMBER( atarig42_state::atarig42_sloop_direct_handler )
139	139	{
140	140	if (address < 0x80000)
141	141	{
142		atarig42_state *state = machine.driver_data<atarig42_state>();
143		direct.explicit_configure(0x00000, 0x7ffff, 0x7ffff, state->m_sloop_base);
	142	direct.explicit_configure(0x00000, 0x7ffff, 0x7ffff, m_sloop_base);
144	143	return (offs_t)-1;
145	144	}
146	145	return address;
r14963	r14964
792	791
793	792	address_space *main = machine.device<m68000_device>("maincpu")->space(AS_PROGRAM);
794	793	state->m_sloop_base = main->install_readwrite_handler(0x000000, 0x07ffff, read16_delegate(FUNC(atarig42_state::roadriot_sloop_data_r),state), write16_delegate(FUNC(atarig42_state::roadriot_sloop_data_w),state));
795		main->set_direct_update_handler(direct_update_delegate(FUNC(atarig42_sloop_direct_handler), &machine));
	794	main->set_direct_update_handler(direct_update_delegate(FUNC(atarig42_state::atarig42_sloop_direct_handler), state));
796	795
797	796	asic65_config(machine, ASIC65_ROMBASED);
798	797	/*
r14963	r14964
831	830
832	831	address_space *main = machine.device<m68000_device>("maincpu")->space(AS_PROGRAM);
833	832	state->m_sloop_base = main->install_readwrite_handler(0x000000, 0x07ffff, read16_delegate(FUNC(atarig42_state::guardians_sloop_data_r),state), write16_delegate(FUNC(atarig42_state::guardians_sloop_data_w),state));
834		main->set_direct_update_handler(direct_update_delegate(FUNC(atarig42_sloop_direct_handler), &machine));
	833	main->set_direct_update_handler(direct_update_delegate(FUNC(atarig42_state::atarig42_sloop_direct_handler), state));
835	834
836	835	asic65_config(machine, ASIC65_GUARDIANS);
837	836	/*

src/mame/drivers/opwolf.c

r14963	r14964
699	699
700	700	static const ym2151_interface ym2151_config =
701	701	{
702		irq_handler,
703		sound_bankswitch_w
	702	DEVCB_LINE(irq_handler),
	703	DEVCB_HANDLER(sound_bankswitch_w)
704	704	};
705	705
706	706

src/mame/drivers/shadfrce.c

r14963	r14964
550	550
551	551	static const ym2151_interface ym2151_config =
552	552	{
553		irq_handler
	553	DEVCB_LINE(irq_handler)
554	554	};
555	555
556	556	static MACHINE_CONFIG_START( shadfrce, shadfrce_state )

src/mame/drivers/cbuster.c

r14963	r14964
270	270
271	271	static const ym2151_interface ym2151_config =
272	272	{
273		sound_irq
	273	DEVCB_LINE(sound_irq)
274	274	};
275	275
276	276	static int twocrude_bank_callback( const int bank )

src/mame/drivers/rohga.c

r14963	r14964
732	732
733	733	static const ym2151_interface ym2151_config =
734	734	{
735		sound_irq,
736		sound_bankswitch_w
	735	DEVCB_LINE(sound_irq),
	736	DEVCB_HANDLER(sound_bankswitch_w)
737	737	};
738	738
739	739	/**********************************************************************************/

src/mame/drivers/plygonet.c

r14963	r14964
313	313	return 0x7fff;
314	314	}
315	315
316		DIRECT_UPDATE_HANDLER( plygonet_dsp56k_direct_handler )
	316	DIRECT_UPDATE_MEMBER(polygonet_state::plygonet_dsp56k_direct_handler)
317	317	{
318		polygonet_state *state = machine.driver_data<polygonet_state>();
319
320	318	/* Call the dsp's update handler first */
321		if (!state->m_dsp56k_update_handler.isnull())
	319	if (!m_dsp56k_update_handler.isnull())
322	320	{
323		if (state->m_dsp56k_update_handler(direct, address) == ~0)
	321	if (m_dsp56k_update_handler(direct, address) == ~0)
324	322	return ~0;
325	323	}
326	324
327	325	/* If the requested region wasn't in there, see if it needs to be caught driver-side */
328	326	if (address >= (0x7000<<1) && address <= (0x7fff<<1))
329	327	{
330		direct.explicit_configure(0x7000<<1, 0x7fff<<1, (0xfff<<1) | 1, state->m_dsp56k_p_mirror);
	328	direct.explicit_configure(0x7000<<1, 0x7fff<<1, (0xfff<<1) | 1, m_dsp56k_p_mirror);
331	329	return ~0;
332	330	}
333	331	else if (address >= (0x8000<<1) && address <= (0x87ff<<1))
334	332	{
335		direct.explicit_configure(0x8000<<1, 0x87ff<<1, (0x7ff<<1) | 1, state->m_dsp56k_p_8000);
	333	direct.explicit_configure(0x8000<<1, 0x87ff<<1, (0x7ff<<1) | 1, m_dsp56k_p_8000);
336	334	return ~0;
337	335	}
338	336
r14963	r14964
743	741
744	742	/* The dsp56k occasionally executes out of mapped memory */
745	743	address_space *space = machine.device<dsp56k_device>("dsp")->space(AS_PROGRAM);
746		state->m_dsp56k_update_handler = space->set_direct_update_handler(direct_update_delegate(FUNC(plygonet_dsp56k_direct_handler), &machine));
	744	state->m_dsp56k_update_handler = space->set_direct_update_handler(direct_update_delegate(FUNC(polygonet_state::plygonet_dsp56k_direct_handler), state));
747	745
748	746	/* save states */
749	747	state->save_item(NAME(state->m_dsp56k_bank00_ram));

src/mame/drivers/nemesis.c

r14963	r14964
1521	1521
1522	1522	static const ym2151_interface ym2151_config =
1523	1523	{
1524		sound_irq
	1524	DEVCB_LINE(sound_irq)
1525	1525	};
1526	1526
1527	1527	static const ym3812_interface ym3812_config =

src/mame/drivers/galaga.c

r14963	r14964
988	988	AM_RANGE(0x8400, 0x87ff) AM_RAM AM_SHARE("share1")                     /* work RAM (top half for RAM 0 */
989	989	AM_RANGE(0x8800, 0x8bff) AM_RAM AM_SHARE("digdug_objram")   /* work RAM + sprite registers */
990	990	AM_RANGE(0x9000, 0x93ff) AM_RAM AM_SHARE("digdug_posram")   /* work RAM + sprite registers */
991		AM_RANGE(0x9800, 0x9bff) AM_RAM AM_SHARE("share4") AM_SHARE("digdug_flpram")   /* work RAM + sprite registers */
	991	AM_RANGE(0x9800, 0x9bff) AM_RAM AM_SHARE("digdug_flpram")   /* work RAM + sprite registers */
992	992	AM_RANGE(0xa000, 0xa007) AM_READNOP AM_WRITE_LEGACY(digdug_PORT_w)      /* video latches (spurious reads when setting latch bits) */
993	993	AM_RANGE(0xb800, 0xb83f) AM_DEVREADWRITE("earom", atari_vg_earom_device, read, write)   /* non volatile memory data */
994	994	AM_RANGE(0xb840, 0xb840) AM_DEVWRITE("earom", atari_vg_earom_device, ctrl_w)               /* non volatile memory control */

src/mame/drivers/taito_x.c

r14963	r14964
794	794
795	795	static const ym2151_interface ym2151_config =
796	796	{
797		irqhandler
	797	DEVCB_LINE(irqhandler)
798	798	};
799	799
800	800	static MACHINE_START( taitox )

src/mame/drivers/sidearms.c

r14963	r14964
649	649
650	650	static const ym2151_interface whizz_ym2151_interface =
651	651	{
652		irqhandler
	652	DEVCB_LINE(irqhandler)
653	653	};
654	654
655	655	static MACHINE_CONFIG_START( sidearms, sidearms_state )

src/mame/drivers/tumblep.c

r14963	r14964
280	280
281	281	static const ym2151_interface ym2151_config =
282	282	{
283		sound_irq
	283	DEVCB_LINE(sound_irq)
284	284	};
285	285
286	286	static const deco16ic_interface tumblep_deco16ic_tilegen1_intf =

src/mame/drivers/dietgo.c

r14963	r14964
168	168
169	169	static const ym2151_interface ym2151_config =
170	170	{
171		sound_irq
	171	DEVCB_LINE(sound_irq)
172	172	};
173	173
174	174

src/mame/drivers/blockout.c

r14963	r14964
268	268
269	269	static const ym2151_interface ym2151_config =
270	270	{
271		blockout_irq_handler
	271	DEVCB_LINE(blockout_irq_handler)
272	272	};
273	273
274	274

src/mame/drivers/exzisus.c

r14963	r14964
259	259
260	260	static const ym2151_interface ym2151_config =
261	261	{
262		irqhandler
	262	DEVCB_LINE(irqhandler)
263	263	};
264	264
265	265

src/mame/drivers/merit.c

r14963	r14964
72	72	int m_extra_video_bank_bit;
73	73	int m_question_address;
74	74	int m_decryption_key;
75		required_shared_ptr<UINT8> m_backup_ram;
	75	optional_shared_ptr<UINT8> m_backup_ram;
76	76	DECLARE_READ8_MEMBER(questions_r);
77	77	DECLARE_WRITE8_MEMBER(low_offset_w);
78	78	DECLARE_WRITE8_MEMBER(med_offset_w);

src/mame/drivers/mcr68.c

r14963	r14964
55	55
56	56	#include "emu.h"
57	57	#include "cpu/m68000/m68000.h"
58		#include "audio/mcr.h"
59		#include "audio/williams.h"
60	58	#include "machine/nvram.h"
61	59	#include "includes/mcr.h"
62	60	#include "includes/mcr68.h"
r14963	r14964
103	101	WRITE16_MEMBER(mcr68_state::xenophobe_control_w)
104	102	{
105	103	COMBINE_DATA(&m_control_word);
106		/*  soundsgood_reset_w(~m_control_word & 0x0020);*/
107		soundsgood_data_w(space, offset, ((m_control_word & 0x000f) << 1) | ((m_control_word & 0x0010) >> 4));
	104	/*  m_sounds_good->reset_write(~m_control_word & 0x0020);*/
	105	m_sounds_good->write(space, offset, ((m_control_word & 0x000f) << 1) | ((m_control_word & 0x0010) >> 4));
108	106	}
109	107
110	108
r14963	r14964
118	116	WRITE16_MEMBER(mcr68_state::blasted_control_w)
119	117	{
120	118	COMBINE_DATA(&m_control_word);
121		/*  soundsgood_reset_w(~m_control_word & 0x0020);*/
122		soundsgood_data_w(space, offset, (m_control_word >> 8) & 0x1f);
	119	/*  m_sounds_good->reset_write(~m_control_word & 0x0020);*/
	120	m_sounds_good->write(space, offset, (m_control_word >> 8) & 0x1f);
123	121	}
124	122
125	123
r14963	r14964
137	135	int which = (m_control_word >> 3) & 3;
138	136	int analog = input_port_read(machine(), portnames[which]);
139	137
140		return result | ((soundsgood_status_r(space, 0) & 1) << 5) | (analog << 8);
	138	return result | ((m_sounds_good->read(space, 0) & 1) << 5) | (analog << 8);
141	139	}
142	140
143	141
144	142	READ16_MEMBER(mcr68_state::spyhunt2_port_1_r)
145	143	{
146	144	int result = input_port_read(machine(), "IN1");
147		return result | ((turbocs_status_r(space, 0) & 1) << 7);
	145	return result | ((m_turbo_chip_squeak->read(space, 0) & 1) << 7);
148	146	}
149	147
150	148
r14963	r14964
152	150	{
153	151	COMBINE_DATA(&m_control_word);
154	152
155		/*  turbocs_reset_w(~m_control_word & 0x0080);*/
156		turbocs_data_w(space, offset, (m_control_word >> 8) & 0x001f);
	153	/*  m_turbo_chip_squeak->reset_write(~m_control_word & 0x0080);*/
	154	m_turbo_chip_squeak->write(space, offset, (m_control_word >> 8) & 0x001f);
157	155
158		soundsgood_reset_w(machine(), ~m_control_word & 0x2000);
159		soundsgood_data_w(space, offset, (m_control_word >> 8) & 0x001f);
	156	m_sounds_good->reset_write(~m_control_word & 0x2000);
	157	m_sounds_good->write(space, offset, (m_control_word >> 8) & 0x001f);
160	158	}
161	159
162	160
r14963	r14964
206	204	WRITE16_MEMBER(mcr68_state::archrivl_control_w)
207	205	{
208	206	COMBINE_DATA(&m_control_word);
209		williams_cvsd_reset_w(machine(), ~m_control_word & 0x0400);
210		williams_cvsd_data_w(machine(), m_control_word & 0x3ff);
	207	m_cvsd_sound->reset_write(~m_control_word & 0x0400);
	208	m_cvsd_sound->write(space, 0, m_control_word & 0x3ff);
211	209	}
212	210
213	211
r14963	r14964
305	303	ADDRESS_MAP_GLOBAL_MASK(0x1fffff)
306	304	AM_RANGE(0x000000, 0x03ffff) AM_ROM
307	305	AM_RANGE(0x060000, 0x063fff) AM_RAM
308		AM_RANGE(0x070000, 0x070fff) AM_RAM_WRITE(mcr68_videoram_w) AM_SHARE("videoram16")
	306	AM_RANGE(0x070000, 0x070fff) AM_RAM_WRITE(mcr68_videoram_w) AM_SHARE("videoram")
309	307	AM_RANGE(0x071000, 0x071fff) AM_RAM
310		AM_RANGE(0x080000, 0x080fff) AM_RAM AM_SHARE("spriteram16")
	308	AM_RANGE(0x080000, 0x080fff) AM_RAM AM_SHARE("spriteram")
311	309	AM_RANGE(0x090000, 0x09007f) AM_WRITE(mcr68_paletteram_w) AM_SHARE("paletteram")
312	310	AM_RANGE(0x0a0000, 0x0a000f) AM_READWRITE(mcr68_6840_upper_r, mcr68_6840_upper_w)
313	311	AM_RANGE(0x0b0000, 0x0bffff) AM_WRITE(watchdog_reset16_w)
r14963	r14964
333	331	AM_RANGE(0x104000, 0x104007) AM_DEVREADWRITE8("pia0", pia6821_device, read, write, 0xff00)
334	332	AM_RANGE(0x108000, 0x108007) AM_DEVREADWRITE8("pia1", pia6821_device, read, write, 0x00ff)
335	333	AM_RANGE(0x10c000, 0x10c007) AM_DEVREADWRITE8("pia2", pia6821_device, read, write, 0x00ff)
336		AM_RANGE(0x800000, 0x800fff) AM_RAM_WRITE(zwackery_videoram_w) AM_SHARE("videoram16")
	334	AM_RANGE(0x800000, 0x800fff) AM_RAM_WRITE(zwackery_videoram_w) AM_SHARE("videoram")
337	335	AM_RANGE(0x802000, 0x803fff) AM_RAM_WRITE(zwackery_paletteram_w) AM_SHARE("paletteram")
338		AM_RANGE(0xc00000, 0xc00fff) AM_RAM_WRITE(zwackery_spriteram_w) AM_SHARE("spriteram16")
	336	AM_RANGE(0xc00000, 0xc00fff) AM_RAM_WRITE(zwackery_spriteram_w) AM_SHARE("spriteram")
339	337	ADDRESS_MAP_END
340	338
341	339
r14963	r14964
354	352	AM_RANGE(0x0a0000, 0x0affff) AM_READ(pigskin_port_2_r)
355	353	AM_RANGE(0x0c0000, 0x0c007f) AM_WRITE(mcr68_paletteram_w) AM_SHARE("paletteram")
356	354	AM_RANGE(0x0e0000, 0x0effff) AM_WRITE(watchdog_reset16_w)
357		AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(mcr68_videoram_w) AM_SHARE("videoram16")
	355	AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(mcr68_videoram_w) AM_SHARE("videoram")
358	356	AM_RANGE(0x120000, 0x120001) AM_READWRITE(pigskin_protection_r, pigskin_protection_w)
359	357	AM_RANGE(0x140000, 0x143fff) AM_RAM
360		AM_RANGE(0x160000, 0x1607ff) AM_RAM AM_SHARE("spriteram16")
	358	AM_RANGE(0x160000, 0x1607ff) AM_RAM AM_SHARE("spriteram")
361	359	AM_RANGE(0x180000, 0x18000f) AM_READWRITE(mcr68_6840_upper_r, mcr68_6840_upper_w)
362	360	AM_RANGE(0x1a0000, 0x1affff) AM_WRITE(archrivl_control_w)
363	361	AM_RANGE(0x1e0000, 0x1effff) AM_READ_PORT("IN0")
r14963	r14964
379	377	AM_RANGE(0x0a0000, 0x0affff) AM_READ_PORT("DSW")
380	378	AM_RANGE(0x100000, 0x103fff) AM_RAM AM_SHARE("nvram")
381	379	AM_RANGE(0x120000, 0x12007f) AM_WRITE(mcr68_paletteram_w) AM_SHARE("paletteram")
382		AM_RANGE(0x140000, 0x1407ff) AM_RAM AM_SHARE("spriteram16")
383		AM_RANGE(0x160000, 0x160fff) AM_RAM_WRITE(mcr68_videoram_w) AM_SHARE("videoram16")
	380	AM_RANGE(0x140000, 0x1407ff) AM_RAM AM_SHARE("spriteram")
	381	AM_RANGE(0x160000, 0x160fff) AM_RAM_WRITE(mcr68_videoram_w) AM_SHARE("videoram")
384	382	AM_RANGE(0x180000, 0x18000f) AM_READWRITE(mcr68_6840_upper_r, mcr68_6840_upper_w)
385	383	AM_RANGE(0x1a0000, 0x1affff) AM_WRITE(archrivl_control_w)
386	384	AM_RANGE(0x1c0000, 0x1cffff) AM_WRITE(watchdog_reset16_w)
r14963	r14964
991	989	MCFG_VIDEO_START(zwackery)
992	990
993	991	/* sound hardware */
994		MCFG_FRAGMENT_ADD(chip_squeak_deluxe)
	992	MCFG_SPEAKER_STANDARD_MONO("mono")
	993	MCFG_MIDWAY_CHIP_SQUEAK_DELUXE_ADD("csd")
	994	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
995	995	MACHINE_CONFIG_END
996	996
997	997
r14963	r14964
1020	1020	MCFG_VIDEO_START(mcr68)
1021	1021
1022	1022	/* sound hardware -- determined by specific machine */
	1023	MCFG_SPEAKER_STANDARD_MONO("mono")
1023	1024	MACHINE_CONFIG_END
1024	1025
1025	1026
1026	1027	static MACHINE_CONFIG_DERIVED( xenophob, mcr68 )
1027	1028
1028	1029	/* basic machine hardware */
1029		MCFG_FRAGMENT_ADD(sounds_good)
	1030	MCFG_MIDWAY_SOUNDS_GOOD_ADD("sg")
	1031	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1030	1032	MACHINE_CONFIG_END
1031	1033
1032	1034	static MACHINE_CONFIG_DERIVED( intlaser, mcr68 )
1033	1035
1034	1036	/* basic machine hardware */
1035		MCFG_FRAGMENT_ADD(sounds_good)
	1037	MCFG_MIDWAY_SOUNDS_GOOD_ADD("sg")
	1038	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1036	1039
1037	1040	MCFG_WATCHDOG_VBLANK_INIT(800)
1038	1041	MACHINE_CONFIG_END
r14963	r14964
1041	1044	static MACHINE_CONFIG_DERIVED( spyhunt2, mcr68 )
1042	1045
1043	1046	/* basic machine hardware */
1044		MCFG_FRAGMENT_ADD(sounds_good)
1045		MCFG_DEVICE_REMOVE("mono")
1046		MCFG_FRAGMENT_ADD(turbo_chip_squeak)
	1047	MCFG_MIDWAY_SOUNDS_GOOD_ADD("sg")
	1048	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	1049	MCFG_MIDWAY_TURBO_CHIP_SQUEAK_ADD("tcs")
	1050	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1047	1051	MACHINE_CONFIG_END
1048	1052
1049	1053
1050	1054	static MACHINE_CONFIG_DERIVED( archrivl, mcr68 )
1051	1055
1052	1056	/* basic machine hardware */
1053		MCFG_FRAGMENT_ADD(williams_cvsd_sound)
	1057	MCFG_WILLIAMS_CVSD_SOUND_ADD("cvsd")
	1058	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1054	1059	MACHINE_CONFIG_END
1055	1060
1056	1061
1057	1062	static MACHINE_CONFIG_DERIVED( pigskin, mcr68 )
1058	1063
1059	1064	/* basic machine hardware */
1060		MCFG_FRAGMENT_ADD(williams_cvsd_sound)
	1065	MCFG_WILLIAMS_CVSD_SOUND_ADD("cvsd")
	1066	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1061	1067
1062	1068	MCFG_CPU_MODIFY("maincpu")
1063	1069	MCFG_CPU_PROGRAM_MAP(pigskin_map)
r14963	r14964
1067	1073	static MACHINE_CONFIG_DERIVED( trisport, mcr68 )
1068	1074
1069	1075	/* basic machine hardware */
1070		MCFG_FRAGMENT_ADD(williams_cvsd_sound)
	1076	MCFG_WILLIAMS_CVSD_SOUND_ADD("cvsd")
	1077	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1071	1078
1072	1079	MCFG_CPU_MODIFY("maincpu")
1073	1080	MCFG_CPU_PROGRAM_MAP(trisport_map)
r14963	r14964
1100	1107	ROM_LOAD16_BYTE( "pro12.bin",  0x30000, 0x4000, CRC(e2d25e1f) SHA1(5d8ff303441eccf431422b453a173983a4513630) )
1101	1108	ROM_LOAD16_BYTE( "pro13.bin",  0x30001, 0x4000, CRC(e131f9b8) SHA1(08b131f2acc84d4c2c931bfd24e7de3d92a8a817) )
1102	1109
1103		ROM_REGION( 0x20000, "csdcpu", 0 )
	1110	ROM_REGION( 0x20000, "csd:cpu", 0 )
1104	1111	ROM_LOAD16_BYTE( "csd7.bin",  0x00000, 0x2000, CRC(5501f54b) SHA1(84c0851fb868e81400cfe3ebfd7b91fe98a47bac) )
1105	1112	ROM_LOAD16_BYTE( "csd17.bin", 0x00001, 0x2000, CRC(2e482580) SHA1(92bd3e64ff580800ee16579d97bcb8b3bd9f755c) )
1106	1113	ROM_LOAD16_BYTE( "csd8.bin",  0x04000, 0x2000, CRC(13366575) SHA1(bcf25a7d4c6b2ccd7cd9978edafc66ef0cadfe72) )
r14963	r14964
1158	1165	ROM_LOAD16_BYTE( "xeno_pro.2c",  0x20000, 0x10000, CRC(e45bf669) SHA1(52b0ffd2311e4d300410de57fbddacab4b9857a1) )
1159	1166	ROM_LOAD16_BYTE( "xeno_pro.2b",  0x20001, 0x10000, CRC(da5d39d5) SHA1(f61b239eb3108faec2f3dbb8139c8d01b0e29873) )
1160	1167
1161		ROM_REGION( 0x40000, "sgcpu", 0 )  /* Sounds Good board */
	1168	ROM_REGION( 0x40000, "sg:cpu", 0 )  /* Sounds Good board */
1162	1169	ROM_LOAD16_BYTE( "xeno_snd.u7",  0x00000, 0x10000, CRC(77561d15) SHA1(8c23a9270d54be6380f2d23939b6c6d8c31e334b) )
1163	1170	ROM_LOAD16_BYTE( "xeno_snd.u17", 0x00001, 0x10000, CRC(837a1a71) SHA1(d7d60ef1fd11e5e84dd1ffb9a077686bd2fb452e) )
1164	1171	ROM_LOAD16_BYTE( "xeno_snd.u8",  0x20000, 0x10000, CRC(6e2915c7) SHA1(df1f35f6b743afbab0a3a29adce3639a8c9dc66f) )
r14963	r14964
1202	1209	ROM_LOAD16_BYTE( "sh22c.bin",  0x20000, 0x10000, CRC(8ee65009) SHA1(6adb00888f739b59e3ace1a6eaf1c58c4583d7fd) )
1203	1210	ROM_LOAD16_BYTE( "sh22b.bin",  0x20001, 0x10000, CRC(850c21ad) SHA1(3b944545cb469e2c53166a91eb2834c5f3891ddf) )
1204	1211
1205		ROM_REGION( 0x10000, "tcscpu", 0 )  /* 64k for the Turbo Cheap Squeak */
	1212	ROM_REGION( 0x10000, "tcs:cpu", 0 )  /* 64k for the Turbo Cheap Squeak */
1206	1213	ROM_LOAD( "turbo-cs.u5", 0x08000, 0x4000, CRC(4b1d8a66) SHA1(a1a2f9fe3fc42b668ec97ad6c6ea6032f1dc0695) )
1207	1214	ROM_LOAD( "turbo-cs.u4", 0x0c000, 0x4000, CRC(3722ce48) SHA1(ae064be590c067bda66ca7a72c212ad47f3eb1c5) )
1208	1215
1209		ROM_REGION( 0x40000, "sgcpu", 0 )  /* Sounds Good board */
	1216	ROM_REGION( 0x40000, "sg:cpu", 0 )  /* Sounds Good board */
1210	1217	ROM_LOAD16_BYTE( "sh2u7.bin",  0x00000, 0x10000, CRC(02362ea4) SHA1(2d37f06c9156554b8140ed565f6fdd1ef67bb54f) )
1211	1218	ROM_LOAD16_BYTE( "sh2u17.bin", 0x00001, 0x10000, CRC(e29a2c37) SHA1(e0d4df90b533d3325c905d42ddc6876667f32c82) )
1212	1219
r14963	r14964
1239	1246	ROM_LOAD16_BYTE( "2c",  0x20000, 0x10000, CRC(bc834f3f) SHA1(05f6ab508ce2ebe55665e97114070e9d81db48c8) )
1240	1247	ROM_LOAD16_BYTE( "2b",  0x20001, 0x10000, CRC(8a9f7ef3) SHA1(353ebb0a3782c183cc9be800584903e23ca507d9) )
1241	1248
1242		ROM_REGION( 0x10000, "tcscpu", 0 )  /* 64k for the Turbo Cheap Squeak */
	1249	ROM_REGION( 0x10000, "tcs:cpu", 0 )  /* 64k for the Turbo Cheap Squeak */
1243	1250	ROM_LOAD( "turbo-cs.u5", 0x08000, 0x4000, CRC(4b1d8a66) SHA1(a1a2f9fe3fc42b668ec97ad6c6ea6032f1dc0695) )
1244	1251	ROM_LOAD( "turbo-cs.u4", 0x0c000, 0x4000, CRC(3722ce48) SHA1(ae064be590c067bda66ca7a72c212ad47f3eb1c5) )
1245	1252
1246		ROM_REGION( 0x40000, "sgcpu", 0 )  /* Sounds Good board */
	1253	ROM_REGION( 0x40000, "sg:cpu", 0 )  /* Sounds Good board */
1247	1254	ROM_LOAD16_BYTE( "sh2u7.bin",  0x00000, 0x10000, CRC(02362ea4) SHA1(2d37f06c9156554b8140ed565f6fdd1ef67bb54f) )
1248	1255	ROM_LOAD16_BYTE( "sh2u17.bin", 0x00001, 0x10000, CRC(e29a2c37) SHA1(e0d4df90b533d3325c905d42ddc6876667f32c82) )
1249	1256
r14963	r14964
1276	1283	ROM_LOAD16_BYTE( "2c",  0x20000, 0x10000, CRC(026f30bf) SHA1(de327ab5bd4dc9456fa5a91f3ccd293b3ab8c5c2) )
1277	1284	ROM_LOAD16_BYTE( "2b",  0x20001, 0x10000, CRC(8e0e91a9) SHA1(2dc2927a1fd552ead446606a902a2ba0c4595798) )
1278	1285
1279		ROM_REGION( 0x40000, "sgcpu", 0 )  /* Sounds Good board */
	1286	ROM_REGION( 0x40000, "sg:cpu", 0 )  /* Sounds Good board */
1280	1287	ROM_LOAD16_BYTE( "blasted.u7",  0x00000, 0x10000, CRC(8d7c8ef6) SHA1(a414e91c20202f800f3e01e4c430e3f99e3df5bb) )
1281	1288	ROM_LOAD16_BYTE( "blasted.u17", 0x00001, 0x10000, CRC(c79040b9) SHA1(e6fa173ff5fb681ddfef831f1ef237a7c4303f32) )
1282	1289	ROM_LOAD16_BYTE( "blasted.u8",  0x20000, 0x10000, CRC(c53094c0) SHA1(8c54cefe8030bf18b9585008a4a6cf8a7dc23f71) )
r14963	r14964
1310	1317	ROM_LOAD16_BYTE( "2c.bin",  0x20000, 0x10000, CRC(d2cca853) SHA1(69e4ee8203c6dda7b4ec97c247fbcdc9fdc9ff8d) )
1311	1318	ROM_LOAD16_BYTE( "2b.bin",  0x20001, 0x10000, CRC(3802cfe2) SHA1(d10c802500bae14acc3230ca34c2d1806b68ce4a) )
1312	1319
1313		ROM_REGION( 0x40000, "sgcpu", 0 )  /* Sounds Good board */
	1320	ROM_REGION( 0x40000, "sg:cpu", 0 )  /* Sounds Good board */
1314	1321	ROM_LOAD16_BYTE( "u7.bin",  0x00000, 0x10000, CRC(19ad1e45) SHA1(838ad7304248690d3fdf9e4edf3856936bf36d42) )
1315	1322	ROM_LOAD16_BYTE( "u17.bin", 0x00001, 0x10000, CRC(d6118949) SHA1(9e059f28d9eb8dee10301662a65588cffaf6fd16) )
1316	1323	ROM_LOAD16_BYTE( "u8.bin",  0x20000, 0x10000, CRC(d6cc99aa) SHA1(b970d6e87778959cf7322158b8df26c5028e3f45) )
r14963	r14964
1345	1352	ROM_LOAD16_BYTE( "2c-rev2",  0x20000, 0x10000, CRC(cc2893f7) SHA1(44931299cb98e27ac2f11b3922da76895fbfe0a7) )
1346	1353	ROM_LOAD16_BYTE( "2b-rev2",  0x20001, 0x10000, CRC(fa977050) SHA1(67c66995da755401162f7e668b97eb42ac769ec0) )
1347	1354
1348		ROM_REGION( 0x90000, "cvsdcpu", 0 )  /* Audio System board */
	1355	ROM_REGION( 0x90000, "cvsd:cpu", 0 )  /* Audio System board */
1349	1356	ROM_LOAD( "u4.snd",  0x10000, 0x08000, CRC(96b3c652) SHA1(1bb576d0bf6b6b8df24e7b9352a33e97dd8ebdcb) )
1350	1357	ROM_RELOAD(          0x18000, 0x08000 )
1351	1358	ROM_RELOAD(          0x20000, 0x08000 )
r14963	r14964
1392	1399	ROM_LOAD16_BYTE( "archrivl.3",  0x20000, 0x10000, CRC(d6d08ff7) SHA1(bbbd4b5c3218c9bb461b17e536191d40ab39f67c) )
1393	1400	ROM_LOAD16_BYTE( "archrivl.1",  0x20001, 0x10000, CRC(92f3a43d) SHA1(45fdcbacd65f5898d54cc2ac95639b7ee2c097e6) )
1394	1401
1395		ROM_REGION( 0x90000, "cvsdcpu", 0 )  /* Audio System board */
	1402	ROM_REGION( 0x90000, "cvsd:cpu", 0 )  /* Audio System board */
1396	1403	ROM_LOAD( "u4.snd",  0x10000, 0x08000, CRC(96b3c652) SHA1(1bb576d0bf6b6b8df24e7b9352a33e97dd8ebdcb) )
1397	1404	ROM_RELOAD(          0x18000, 0x08000 )
1398	1405	ROM_RELOAD(          0x20000, 0x08000 )
r14963	r14964
1439	1446	ROM_LOAD16_BYTE( "pigskin-k_la1.a6",  0x20000, 0x10000, CRC(4d8b7e50) SHA1(9e5d0edf1603e11f22d3129a2b8865ebcb5e27f9) )
1440	1447	ROM_LOAD16_BYTE( "pigskin-k_la1.b6",  0x20001, 0x10000, CRC(1194f187) SHA1(e7cebe5322a5c8e382b6773939be5bc88492f289) )
1441	1448
1442		ROM_REGION( 0x90000, "cvsdcpu", 0 )  /* Audio System board */
	1449	ROM_REGION( 0x90000, "cvsd:cpu", 0 )  /* Audio System board */
1443	1450	ROM_LOAD( "pigskin_sl1.u4",  0x10000, 0x10000, CRC(6daf2d37) SHA1(4c8098520fe44e36b01389bcfcfe3ad1d027cbde) )
1444	1451	ROM_RELOAD(                  0x20000, 0x10000 )
1445	1452	ROM_LOAD( "pigskin_sl1.u19", 0x30000, 0x10000, CRC(56fd16a3) SHA1(b91aabdbd3185355f2b7177fc4d3a86fa110f51d) )
r14963	r14964
1466	1473	ROM_LOAD16_BYTE( "pigskin_la2.a6",  0x20000, 0x10000, CRC(2fc91002) SHA1(64d270b78c69d3f4fb36d1233a1632d6ba3d87a5) )
1467	1474	ROM_LOAD16_BYTE( "pigskin_la2.b6",  0x20001, 0x10000, CRC(0b93dc66) SHA1(f3b516a1d1e4abd7b0d56243949e9cd7ac79178b) )
1468	1475
1469		ROM_REGION( 0x90000, "cvsdcpu", 0 )  /* Audio System board */
	1476	ROM_REGION( 0x90000, "cvsd:cpu", 0 )  /* Audio System board */
1470	1477	ROM_LOAD( "pigskin_sl1.u4",  0x10000, 0x10000, CRC(6daf2d37) SHA1(4c8098520fe44e36b01389bcfcfe3ad1d027cbde) )
1471	1478	ROM_RELOAD(                  0x20000, 0x10000 )
1472	1479	ROM_LOAD( "pigskin_sl1.u19", 0x30000, 0x10000, CRC(56fd16a3) SHA1(b91aabdbd3185355f2b7177fc4d3a86fa110f51d) )
r14963	r14964
1493	1500	ROM_LOAD16_BYTE( "la3.a6",  0x20000, 0x10000, CRC(9c6a1398) SHA1(ee115d9207f3a9034b7c9eccd2ff151d9c923c9a) )
1494	1501	ROM_LOAD16_BYTE( "la3.b6",  0x20001, 0x10000, CRC(597b564c) SHA1(090da3ec0c86035cc41a9caea182b8a5419c3be9) )
1495	1502
1496		ROM_REGION( 0x90000, "cvsdcpu", 0 )  /* Audio System board */
	1503	ROM_REGION( 0x90000, "cvsd:cpu", 0 )  /* Audio System board */
1497	1504	ROM_LOAD( "sl1-snd.u4",  0x10000, 0x10000, CRC(0ed8c904) SHA1(21292a001c4c44f87b8782c706e5c346b767cd6b) )
1498	1505	ROM_RELOAD(              0x20000, 0x10000 )
1499	1506	ROM_LOAD( "sl1-snd.u19", 0x30000, 0x10000, CRC(b57d7d7e) SHA1(483f718f1cc4549baf5696935532d30803254a19) )
r14963	r14964
1536	1543	*
1537	1544	*************************************/
1538	1545
1539		static void mcr68_common_init(running_machine &machine, int sound_board, int clip, int xoffset)
	1546	static void mcr68_common_init(running_machine &machine, int clip, int xoffset)
1540	1547	{
1541	1548	mcr68_state *state = machine.driver_data<mcr68_state>();
1542		mcr_sound_init(machine, sound_board);
1543	1549
1544	1550	state->m_sprite_clip = clip;
1545	1551	state->m_sprite_xoffset = xoffset;
r14963	r14964
1551	1557	static DRIVER_INIT( zwackery )
1552	1558	{
1553	1559	mcr68_state *state = machine.driver_data<mcr68_state>();
1554		mcr68_common_init(machine, MCR_CHIP_SQUEAK_DELUXE, 0, 0);
	1560	mcr68_common_init(machine, 0, 0);
1555	1561
1556	1562	/* Zwackery doesn't care too much about this value; currently taken from Blasted */
1557	1563	state->m_timing_factor = attotime::from_hz(machine.device("maincpu")->unscaled_clock() / 10) * (256 + 16);
r14963	r14964
1561	1567	static DRIVER_INIT( xenophob )
1562	1568	{
1563	1569	mcr68_state *state = machine.driver_data<mcr68_state>();
1564		mcr68_common_init(machine, MCR_SOUNDS_GOOD, 0, -4);
	1570	mcr68_common_init(machine, 0, -4);
1565	1571
1566	1572	/* Xenophobe doesn't care too much about this value; currently taken from Blasted */
1567	1573	state->m_timing_factor = attotime::from_hz(machine.device("maincpu")->unscaled_clock() / 10) * (256 + 16);
r14963	r14964
1574	1580	static DRIVER_INIT( spyhunt2 )
1575	1581	{
1576	1582	mcr68_state *state = machine.driver_data<mcr68_state>();
1577		mcr68_common_init(machine, MCR_TURBO_CHIP_SQUEAK | MCR_SOUNDS_GOOD, 0, -6);
	1583	mcr68_common_init(machine, 0, -6);
1578	1584
1579	1585	/* Spy Hunter 2 doesn't care too much about this value; currently taken from Blasted */
1580	1586	state->m_timing_factor = attotime::from_hz(machine.device("maincpu")->unscaled_clock() / 10) * (256 + 16);
r14963	r14964
1589	1595	static DRIVER_INIT( blasted )
1590	1596	{
1591	1597	mcr68_state *state = machine.driver_data<mcr68_state>();
1592		mcr68_common_init(machine, MCR_SOUNDS_GOOD, 0, 0);
	1598	mcr68_common_init(machine, 0, 0);
1593	1599
1594	1600	/* Blasted checks the timing of VBLANK relative to the 493 interrupt */
1595	1601	/* VBLANK is required to come within 220-256 E clocks (i.e., 2200-2560 CPU clocks) */
r14963	r14964
1606	1612	static DRIVER_INIT( intlaser )
1607	1613	{
1608	1614	mcr68_state *state = machine.driver_data<mcr68_state>();
1609		mcr68_common_init(machine, MCR_SOUNDS_GOOD, 0, 0);
	1615	mcr68_common_init(machine, 0, 0);
1610	1616
1611	1617	/* Copied from Blasted */
1612	1618	state->m_timing_factor = attotime::from_hz(machine.device("maincpu")->unscaled_clock() / 10) * (256 + 16);
r14963	r14964
1621	1627	static DRIVER_INIT( archrivl )
1622	1628	{
1623	1629	mcr68_state *state = machine.driver_data<mcr68_state>();
1624		mcr68_common_init(machine, MCR_WILLIAMS_SOUND, 16, 0);
	1630	mcr68_common_init(machine, 16, 0);
1625	1631
1626	1632	/* Arch Rivals doesn't care too much about this value; currently taken from Blasted */
1627	1633	state->m_timing_factor = attotime::from_hz(machine.device("maincpu")->unscaled_clock() / 10) * (256 + 16);
r14963	r14964
1640	1646	static DRIVER_INIT( pigskin )
1641	1647	{
1642	1648	mcr68_state *state = machine.driver_data<mcr68_state>();
1643		mcr68_common_init(machine, MCR_WILLIAMS_SOUND, 16, 0);
	1649	mcr68_common_init(machine, 16, 0);
1644	1650
1645	1651	/* Pigskin doesn't care too much about this value; currently taken from Tri-Sports */
1646	1652	state->m_timing_factor = attotime::from_hz(machine.device("maincpu")->unscaled_clock() / 10) * 115;
r14963	r14964
1652	1658	static DRIVER_INIT( trisport )
1653	1659	{
1654	1660	mcr68_state *state = machine.driver_data<mcr68_state>();
1655		mcr68_common_init(machine, MCR_WILLIAMS_SOUND, 0, 0);
	1661	mcr68_common_init(machine, 0, 0);
1656	1662
1657	1663	/* Tri-Sports checks the timing of VBLANK relative to the 493 interrupt */
1658	1664	/* VBLANK is required to come within 87-119 E clocks (i.e., 870-1190 CPU clocks) */

src/mame/drivers/tecmo16.c

r14963	r14964
368	368
369	369	static const ym2151_interface ym2151_config =
370	370	{
371		irqhandler
	371	DEVCB_LINE(irqhandler)
372	372	};
373	373
374	374	/******************************************************************************/

src/mame/drivers/rastan.c

r14963	r14964
346	346
347	347	static const ym2151_interface ym2151_config =
348	348	{
349		irqhandler,
350		rastan_bankswitch_w
	349	DEVCB_LINE(irqhandler),
	350	DEVCB_HANDLER(rastan_bankswitch_w)
351	351	};
352	352
353	353	static const msm5205_interface msm5205_config =

src/mame/drivers/dlair.c

r14963	r14964
97	97	optional_device<pioneer_ldv1000_device> m_ldv1000;
98	98	optional_device<pioneer_pr7820_device> m_pr7820;
99	99	optional_device<phillips_22vp932_device> m_22vp932;
100		required_shared_ptr<UINT8> m_videoram;
	100	optional_shared_ptr<UINT8> m_videoram;
101	101	UINT8 m_last_misc;
102	102	UINT8 m_laserdisc_data;
103	103	DECLARE_WRITE8_MEMBER(misc_w);

src/mame/drivers/segas24.c

r14963	r14964
1933	1933
1934	1934	static const ym2151_interface ym2151_config =
1935	1935	{
1936		irq_ym
	1936	DEVCB_LINE(irq_ym)
1937	1937	};
1938	1938
1939	1939

src/mame/drivers/mugsmash.c

r14963	r14964
396	396
397	397	static const ym2151_interface ym2151_config =
398	398	{
399		irq_handler
	399	DEVCB_LINE(irq_handler)
400	400	};
401	401
402	402	static MACHINE_START( mugsmash )

src/mame/drivers/hng64.c

r14963	r14964
1090	1090	#define KL5C_MMU_A(xxx) ( (xxx == 0) ? 0x0000 : (state->m_com_mmu_mem[((xxx-1)*2)+1] << 2) | ((state->m_com_mmu_mem[(xxx-1)*2] & 0xc0) >> 6) )
1091	1091	#define KL5C_MMU_B(xxx) ( (xxx == 0) ? 0x0000 : (state->m_com_mmu_mem[(xxx-1)*2] & 0x3f) )
1092	1092
1093		DIRECT_UPDATE_HANDLER( KL5C80_direct_handler )
	1093	DIRECT_UPDATE_MEMBER(hng64_state::KL5C80_direct_handler)
1094	1094	{
1095		hng64_state *state = machine.driver_data<hng64_state>();
1096
1097		direct.explicit_configure(0x0000, 0xffff, 0xffff, state->m_com_op_base);
	1095	direct.explicit_configure(0x0000, 0xffff, 0xffff, m_com_op_base);
1098	1096	return ~0;
1099	1097	}
1100	1098
r14963	r14964
1682	1680	KL5C80_virtual_mem_sync(state);
1683	1681
1684	1682	address_space *space = machine.device<z80_device>("comm")->space(AS_PROGRAM);
1685		space->set_direct_update_handler(direct_update_delegate(FUNC(KL5C80_direct_handler), &machine));
	1683	space->set_direct_update_handler(direct_update_delegate(FUNC(hng64_state::KL5C80_direct_handler), state));
1686	1684
1687	1685	cputag_set_input_line(machine, "comm", INPUT_LINE_RESET, PULSE_LINE);     // reset the CPU and let 'er rip
1688	1686	//  cputag_set_input_line(machine, "comm", INPUT_LINE_HALT, ASSERT_LINE);     // hold on there pardner...

src/mame/drivers/cabal.c

r14963	r14964
464	464
465	465	static const ym2151_interface cabalbl_ym2151_interface =
466	466	{
467		irqhandler
	467	DEVCB_LINE(irqhandler)
468	468	};
469	469
470	470	static const msm5205_interface msm5205_interface_1 =

src/mame/drivers/m107.c

r14963	r14964
761	761
762	762	static const ym2151_interface ym2151_config =
763	763	{
764		sound_irq
	764	DEVCB_LINE(sound_irq)
765	765	};
766	766
767	767	/***************************************************************************/

src/mame/drivers/ninjaw.c

r14963	r14964
430	430	AM_RANGE(0x210000, 0x210001) AM_WRITE(cpua_ctrl_w)
431	431	AM_RANGE(0x220000, 0x220003) AM_READWRITE(ninjaw_sound_r,ninjaw_sound_w)
432	432	AM_RANGE(0x240000, 0x24ffff) AM_RAM AM_SHARE("share1")
433		AM_RANGE(0x260000, 0x263fff) AM_RAM AM_SHARE("share2") AM_SHARE("spriteram")
	433	AM_RANGE(0x260000, 0x263fff) AM_RAM AM_SHARE("spriteram")
434	434	AM_RANGE(0x280000, 0x293fff) AM_DEVREAD_LEGACY("tc0100scn_1", tc0100scn_word_r) AM_WRITE(tc0100scn_triple_screen_w)   /* tilemaps (1st screen/all screens) */
435	435	AM_RANGE(0x2a0000, 0x2a000f) AM_DEVREADWRITE_LEGACY("tc0100scn_1", tc0100scn_ctrl_word_r, tc0100scn_ctrl_word_w)
436	436	AM_RANGE(0x2c0000, 0x2d3fff) AM_DEVREADWRITE_LEGACY("tc0100scn_2", tc0100scn_word_r, tc0100scn_word_w)      /* tilemaps (2nd screen) */
r14963	r14964
484	484	AM_RANGE(0x200000, 0x200001) AM_DEVREADWRITE8_LEGACY("tc0220ioc", tc0220ioc_portreg_r, tc0220ioc_portreg_w, 0x00ff)
485	485	AM_RANGE(0x200002, 0x200003) AM_DEVREADWRITE8_LEGACY("tc0220ioc", tc0220ioc_port_r, tc0220ioc_port_w, 0x00ff)
486	486	AM_RANGE(0x240000, 0x24ffff) AM_RAM AM_SHARE("share1")
487		AM_RANGE(0x260000, 0x263fff) AM_RAM AM_SHARE("share2")
	487	AM_RANGE(0x260000, 0x263fff) AM_RAM AM_SHARE("spriteram")
488	488	AM_RANGE(0x280000, 0x293fff) AM_DEVREAD_LEGACY("tc0100scn_1", tc0100scn_word_r) AM_WRITE(tc0100scn_triple_screen_w)   /* tilemaps (1st screen/all screens) */
489	489	ADDRESS_MAP_END
490	490

src/mame/drivers/megasys1.c

r14963	r14964
1452	1452
1453	1453	static const ym2151_interface ym2151_config =
1454	1454	{
1455		megasys1_sound_irq
	1455	DEVCB_LINE(megasys1_sound_irq)
1456	1456	};
1457	1457
1458	1458	static MACHINE_CONFIG_START( system_A, megasys1_state )

src/mame/drivers/srmp6.c

r14963	r14964
157	157	srmp6_state *state = machine.driver_data<srmp6_state>();
158	158
159	159	state->m_tileram = auto_alloc_array_clear(machine, UINT16, 0x100000*16/2);
160		//state->m_dmaram = auto_alloc_array(machine, UINT16, 0x100/2);
	160	state->m_dmaram.allocate(0x100/2);
161	161	state->m_sprram_old = auto_alloc_array_clear(machine, UINT16, 0x80000/2);
162	162
163	163	/* create the char set (gfx will then be updated dynamically from RAM) */

src/mame/drivers/sf.c

r14963	r14964
794	794
795	795	static const ym2151_interface ym2151_config =
796	796	{
797		irq_handler
	797	DEVCB_LINE(irq_handler)
798	798	};
799	799
800	800	static const msm5205_interface msm5205_config =

src/mame/drivers/cave.c

r14963	r14964
1828	1828
1829	1829	static const ym2151_interface ym2151_config =
1830	1830	{
1831		irqhandler
	1831	DEVCB_LINE(irqhandler)
1832	1832	};
1833	1833
1834	1834	static const ym2203_interface ym2203_config =

src/mame/drivers/williams.c

r14963	r14964
493	493	#include "sound/hc55516.h"
494	494	#include "machine/6821pia.h"
495	495	#include "machine/ticket.h"
496		#include "audio/williams.h"
497	496	#include "includes/williams.h"
498	497	#include "machine/nvram.h"
499	498
r14963	r14964
1694	1693	static MACHINE_CONFIG_DERIVED( joust2, williams2 )
1695	1694
1696	1695	/* basic machine hardware */
1697		MCFG_DEVICE_REMOVE("mono")
1698		MCFG_FRAGMENT_ADD(williams_cvsd_sound)
	1696	MCFG_WILLIAMS_CVSD_SOUND_ADD("cvsd")
	1697	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1699	1698
1700	1699	MCFG_MACHINE_START(joust2)
1701	1700	MCFG_MACHINE_RESET(joust2)
r14963	r14964
2678	2677	ROM_LOAD( "ic08_r1.cpu", 0x0E000, 0x2000, CRC(84517c3c) SHA1(de0b6473953783c091ddcc7aaa89fc1ec3b9d378) )   /* IC08 ROM08 */
2679	2678
2680	2679	/* sound board */
2681		ROM_REGION( 0x90000, "cvsdcpu", 0 )
	2680	ROM_REGION( 0x90000, "cvsd:cpu", 0 )
2682	2681	ROM_LOAD( "u04_r1.snd", 0x10000, 0x8000, CRC(3af6b47d) SHA1(aff19d65a4d9c249dec6a9e04a4066fada0f8fa1) )   /* IC04 ROM23 */
2683	2682	ROM_RELOAD(             0x18000, 0x8000 )
2684	2683	ROM_RELOAD(             0x20000, 0x8000 )

src/mame/drivers/rabbit.c

r14963	r14964
25	25
26	26	- raster effects (rabbit only?, see left side of one of the levels in rabbit)
27	27	- clean up zoom code and make zoom effect more accurate
28		- sound (adpcm of some kind)
29	28	- status bar in rabbit is the wrong colour, timing of blitter / interrupts?
30	29
31	30	Notes:

src/mame/drivers/crimfght.c

r14963	r14964
220	220
221	221	static const ym2151_interface ym2151_config =
222	222	{
223		0,
224		crimfght_snd_bankswitch_w
	223	DEVCB_NULL,
	224	DEVCB_HANDLER(crimfght_snd_bankswitch_w)
225	225	};
226	226
227	227	static void volume_callback( device_t *device, int v )

src/mame/drivers/asuka.c

r14963	r14964
781	781
782	782	static const ym2151_interface ym2151_config =
783	783	{
784		irq_handler,
785		sound_bankswitch_2151_w
	784	DEVCB_LINE(irq_handler),
	785	DEVCB_HANDLER(sound_bankswitch_2151_w)
786	786	};
787	787
788	788	static const msm5205_interface msm5205_config =

src/mame/drivers/shisen.c

r14963	r14964
204	204
205	205	static const ym2151_interface ym2151_config =
206	206	{
207		m72_ym2151_irq_handler
	207	DEVCB_LINE(m72_ym2151_irq_handler)
208	208	};
209	209
210	210

src/mame/drivers/nmk16.c

r14963	r14964
4805	4805
4806	4806	static const ym2151_interface afega_ym2151_intf =
4807	4807	{
4808		irq_handler
	4808	DEVCB_LINE(irq_handler)
4809	4809	};
4810	4810
4811	4811

src/osd/windows/windows.mak

r14963	r14964
160	160	# disable better packing warning
161	161	CPPONLYFLAGS += /wd4371
162	162
	163	# disable side effects warning in STL headers
	164	CPPONLYFLAGS += /wd4548
	165
163	166	# disable macro redefinition warning
164	167	CCOMFLAGS += /wd4005
165	168

src/emu/sound/i5000.c

r14963	r14964
7	7	16-channel ADPCM player.
8	8
9	9	TODO:
10		- improve volume balance (is it really linear?)
11	10	- verify that ADPCM is the same as standard OKI ADPCM
	11	- verify volume balance
	12	- sample command 0x0007
	13	- any more sound formats than 3-bit and 4-bit ADPCM?
12	14
13	15	***************************************************************************/
14	16
r14963	r14964
28	30
29	31	void i5000snd_device::device_start()
30	32	{
	33	// fill volume table
	34	double div = 1.032;
	35	double vol = 2047.0;
	36	for (int i = 0; i < 0x100; i++)
	37	{
	38	m_lut_volume[i] = vol + 0.5;
	39	vol /= div;
	40	}
	41	m_lut_volume[0xff] = 0;
	42
31	43	// create the stream
32	44	m_stream = machine().sound().stream_alloc(*this, 0, 2, clock() / 0x400, this);
33	45
r14963	r14964
113	125
114	126	adpcm_data = m_channels[ch].m_adpcm.clock(adpcm_data & m_channels[ch].shift_mask);
115	127
116		m_channels[ch].output_r = adpcm_data * m_channels[ch].vol_r;
117		m_channels[ch].output_l = adpcm_data * m_channels[ch].vol_l;
	128	m_channels[ch].output_r = adpcm_data * m_channels[ch].vol_r / 128;
	129	m_channels[ch].output_l = adpcm_data * m_channels[ch].vol_l / 128;
118	130	mix_r += m_channels[ch].output_r;
119	131	mix_l += m_channels[ch].output_l;
120	132	}
121	133
122		outputs[0][i] = mix_r / (16*8);
123		outputs[1][i] = mix_l / (16*8);
	134	outputs[0][i] = mix_r / 16;
	135	outputs[1][i] = mix_l / 16;
124	136	}
125	137	}
126	138
r14963	r14964
142	154
143	155	// 3: left/right volume
144	156	case 3:
145		m_channels[ch].vol_r = ~data & 0xff;
146		m_channels[ch].vol_l = ~data >> 8 & 0xff;
	157	m_channels[ch].vol_r = m_lut_volume[data & 0xff];
	158	m_channels[ch].vol_l = m_lut_volume[data >> 8 & 0xff];
147	159	break;
148	160
149	161	default:
r14963	r14964
178	190	// 3-bit ADPCM
179	191	case 0x0104:
180	192	case 0x0304: // same?
181		m_channels[ch].freq_min = 0x100 * (4.0 / 3.0);
	193	m_channels[ch].freq_min = 0x140;
182	194	m_channels[ch].shift_amount = 3;
183	195	m_channels[ch].shift_mask = 0xe;
184	196	break;
r14963	r14964
198	210
199	211	m_channels[ch].freq_timer = 0;
200	212	m_channels[ch].shift_pos = 0;
201		m_channels[ch].output_l = 0;
202		m_channels[ch].output_r = 0;
203	213
204	214	m_channels[ch].m_adpcm.reset();
205	215	m_channels[ch].is_playing = read_sample(ch);

src/emu/sound/i5000.h

r14963	r14964
9	9	#ifndef __I5000_H__
10	10	#define __I5000_H__
11	11
12		#include "sound/okim6295.h"
	12	#include "sound/okiadpcm.h"
13	13
14	14
15	15	//**************************************************************************
r14963	r14964
50	50	typedef struct
51	51	{
52	52	bool is_playing;
53		adpcm_state m_adpcm;   // 4-bit adpcm state (okim6295.h)
	53	oki_adpcm_state m_adpcm;
54	54
55	55	UINT32 address;
56	56	int freq_timer;
r14963	r14964
74	74	UINT16 *m_rom_base;
75	75	UINT32 m_rom_mask;
76	76
	77	int m_lut_volume[0x100];
	78
77	79	bool read_sample(int ch);
78	80	void write_reg16(UINT8 reg, UINT16 data);
79	81	};

src/emu/sound/okim6295.c

r14963	r14964
46	46	// device type definition
47	47	const device_type OKIM6295 = &device_creator<okim6295_device>;
48	48
49		// ADPCM state and tables
50		bool adpcm_state::s_tables_computed = false;
51		const INT8 adpcm_state::s_index_shift[8] = { -1, -1, -1, -1, 2, 4, 6, 8 };
52		int adpcm_state::s_diff_lookup[49*16];
53
54	49	// volume lookup table. The manual lists only 9 steps, ~3dB per step. Given the dB values,
55	50	// that seems to map to a 5-bit volume control. Any volume parameter beyond the 9th index
56	51	// results in silent playback.
r14963	r14964
301	296	{
302	297	okim_voice &voice = m_voice[voicenum];
303	298
304		// determine the start/stop positions
305		offs_t base = m_command * 8;
	299	if (!voice.m_playing) // fixes Got-cha and Steel Force
	300	{
	301	// determine the start/stop positions
	302	offs_t base = m_command * 8;
306	303
307		offs_t start = m_direct->read_raw_byte(base + 0) << 16;
308		start |= m_direct->read_raw_byte(base + 1) << 8;
309		start |= m_direct->read_raw_byte(base + 2) << 0;
310		start &= 0x3ffff;
	304	offs_t start = m_direct->read_raw_byte(base + 0) << 16;
	305	start |= m_direct->read_raw_byte(base + 1) << 8;
	306	start |= m_direct->read_raw_byte(base + 2) << 0;
	307	start &= 0x3ffff;
311	308
312		offs_t stop = m_direct->read_raw_byte(base + 3) << 16;
313		stop |= m_direct->read_raw_byte(base + 4) << 8;
314		stop |= m_direct->read_raw_byte(base + 5) << 0;
315		stop &= 0x3ffff;
	309	offs_t stop = m_direct->read_raw_byte(base + 3) << 16;
	310	stop |= m_direct->read_raw_byte(base + 4) << 8;
	311	stop |= m_direct->read_raw_byte(base + 5) << 0;
	312	stop &= 0x3ffff;
316	313
317		// set up the voice to play this sample
318		if (start < stop)
319		{
320		if (!voice.m_playing) // fixes Got-cha and Steel Force
	314	if (start < stop)
321	315	{
	316	// set up the voice to play this sample
322	317	voice.m_playing = true;
323	318	voice.m_base_offset = start;
324	319	voice.m_sample = 0;
r14963	r14964
328	323	voice.m_adpcm.reset();
329	324	voice.m_volume = s_volume_table[command & 0x0f];
330	325	}
	326
	327	// invalid samples go here
331	328	else
332		logerror("OKIM6295:'%s' requested to play sample %02x on non-stopped voice\n",tag(),m_command);
	329	{
	330	logerror("OKIM6295:'%s' requested to play invalid sample %02x\n",tag(),m_command);
	331	}
333	332	}
334
335		// invalid samples go here
336	333	else
337	334	{
338		logerror("OKIM6295:'%s' requested to play invalid sample %02x\n",tag(),m_command);
339		voice.m_playing = false;
	335	logerror("OKIM6295:'%s' requested to play sample %02x on non-stopped voice\n",tag(),m_command);
340	336	}
341	337	}
342	338
r14963	r14964
422	418	}
423	419	}
424	420
425
426
427		//**************************************************************************
428		//  ADPCM STATE HELPER
429		//**************************************************************************
430
431		//-------------------------------------------------
432		//  reset - reset the ADPCM state
433		//-------------------------------------------------
434
435		void adpcm_state::reset()
436		{
437		// reset the signal/step
438		m_signal = -2;
439		m_step = 0;
440		}
441
442
443		//-------------------------------------------------
444		//  device_clock_changed - called if the clock
445		//  changes
446		//-------------------------------------------------
447
448		INT16 adpcm_state::clock(UINT8 nibble)
449		{
450		// update the signal
451		m_signal += s_diff_lookup[m_step * 16 + (nibble & 15)];
452
453		// clamp to the maximum
454		if (m_signal > 2047)
455		m_signal = 2047;
456		else if (m_signal < -2048)
457		m_signal = -2048;
458
459		// adjust the step size and clamp
460		m_step += s_index_shift[nibble & 7];
461		if (m_step > 48)
462		m_step = 48;
463		else if (m_step < 0)
464		m_step = 0;
465
466		// return the signal
467		return m_signal;
468		}
469
470
471		//-------------------------------------------------
472		//  compute_tables - precompute tables for faster
473		//  sound generation
474		//-------------------------------------------------
475
476		void adpcm_state::compute_tables()
477		{
478		// skip if we already did it
479		if (s_tables_computed)
480		return;
481		s_tables_computed = true;
482
483		// nibble to bit map
484		static const INT8 nbl2bit[16][4] =
485		{
486		{ 1, 0, 0, 0}, { 1, 0, 0, 1}, { 1, 0, 1, 0}, { 1, 0, 1, 1},
487		{ 1, 1, 0, 0}, { 1, 1, 0, 1}, { 1, 1, 1, 0}, { 1, 1, 1, 1},
488		{-1, 0, 0, 0}, {-1, 0, 0, 1}, {-1, 0, 1, 0}, {-1, 0, 1, 1},
489		{-1, 1, 0, 0}, {-1, 1, 0, 1}, {-1, 1, 1, 0}, {-1, 1, 1, 1}
490		};
491
492		// loop over all possible steps
493		for (int step = 0; step <= 48; step++)
494		{
495		// compute the step value
496		int stepval = floor(16.0 * pow(11.0 / 10.0, (double)step));
497
498		// loop over all nibbles and compute the difference
499		for (int nib = 0; nib < 16; nib++)
500		{
501		s_diff_lookup[step*16 + nib] = nbl2bit[nib][0] *
502		(stepval   * nbl2bit[nib][1] +
503		stepval/2 * nbl2bit[nib][2] +
504		stepval/4 * nbl2bit[nib][3] +
505		stepval/8);
506		}
507		}
508		}

src/emu/sound/okim6295.h

r14963	r14964
11	11	#ifndef __OKIM6295_H__
12	12	#define __OKIM6295_H__
13	13
	14	#include "sound/okiadpcm.h"
14	15
15	16
16	17
r14963	r14964
48	49	//**************************************************************************
49	50
50	51
51		// ======================> adpcm_state
52
53		// Internal ADPCM state, used by external ADPCM generators with compatible specs to the OKIM 6295.
54		class adpcm_state
55		{
56		public:
57		adpcm_state() { compute_tables(); reset(); }
58
59		void reset();
60		INT16 clock(UINT8 nibble);
61
62		INT32   m_signal;
63		INT32   m_step;
64
65		private:
66		static const INT8 s_index_shift[8];
67		static int s_diff_lookup[49*16];
68
69		static void compute_tables();
70		static bool s_tables_computed;
71		};
72
73
74
75	52	// ======================> okim6295_device
76	53
77	54	class okim6295_device : public device_t,
r14963	r14964
115	92	okim_voice();
116	93	void generate_adpcm(direct_read_data &direct, stream_sample_t *buffer, int samples);
117	94
118		adpcm_state m_adpcm;         // current ADPCM state
119		bool      m_playing;
120		offs_t      m_base_offset;      // pointer to the base memory location
121		UINT32      m_sample;         // current sample number
122		UINT32      m_count;         // total samples to play
123		INT8      m_volume;         // output volume
	95	oki_adpcm_state m_adpcm;      // current ADPCM state
	96	bool         m_playing;
	97	offs_t         m_base_offset;   // pointer to the base memory location
	98	UINT32         m_sample;      // current sample number
	99	UINT32         m_count;      // total samples to play
	100	INT8         m_volume;      // output volume
124	101	};
125	102
126	103	// configuration state

src/emu/sound/2151intf.c

r14963	r14964
19	19	emu_timer *            timer[2];
20	20	void *               chip;
21	21	UINT8               lastreg;
22		const ym2151_interface *intf;
	22	devcb_resolved_write_line irqhandler;
	23	devcb_resolved_write8 portwritehandler;
23	24	};
24	25
25	26
r14963	r14964
37	38	ym2151_update_one(info->chip, outputs, samples);
38	39	}
39	40
	41	static void ym2151_irq_frontend(device_t *device, int irq)
	42	{
	43	ym2151_state *info = get_safe_token(device);
	44	info->irqhandler(irq);
	45	}
40	46
	47	static void ym2151_port_write_frontend(device_t *device, offs_t offset, UINT8 data)
	48	{
	49	ym2151_state *info = get_safe_token(device);
	50	info->portwritehandler(offset, data);
	51	}
	52
41	53	static DEVICE_START( ym2151 )
42	54	{
43		static const ym2151_interface dummy = { 0 };
	55	static const ym2151_interface dummy = { DEVCB_NULL };
44	56	ym2151_state *info = get_safe_token(device);
45	57	int rate;
46	58
47		info->intf = device->static_config() ? (const ym2151_interface *)device->static_config() : &dummy;
	59	const ym2151_interface *intf = device->static_config() ? (const ym2151_interface *)device->static_config() : &dummy;
	60	info->irqhandler.resolve(intf->irqhandler, *device);
	61	info->portwritehandler.resolve(intf->portwritehandler, *device);
48	62
49	63	rate = device->clock()/64;
50	64
r14963	r14964
54	68	info->chip = ym2151_init(device,device->clock(),rate);
55	69	assert_always(info->chip != NULL, "Error creating YM2151 chip");
56	70
57		ym2151_set_irq_handler(info->chip,info->intf->irqhandler);
58		ym2151_set_port_write_handler(info->chip,info->intf->portwritehandler);
	71	ym2151_set_irq_handler(info->chip,ym2151_irq_frontend);
	72	ym2151_set_port_write_handler(info->chip,ym2151_port_write_frontend);
59	73	}
60	74
61	75

src/emu/sound/2151intf.h

r14963	r14964
8	8	typedef struct _ym2151_interface ym2151_interface;
9	9	struct _ym2151_interface
10	10	{
11		void (*irqhandler)(device_t *device, int irq);
12		write8_device_func portwritehandler;
	11	devcb_write_line irqhandler;
	12	devcb_write8 portwritehandler;
13	13	};
14	14
15	15	READ8_DEVICE_HANDLER( ym2151_r );

src/emu/disound.c

r14963	r14964
71	71	//  a new route to the device
72	72	//-------------------------------------------------
73	73
74		void device_sound_interface::static_add_route(device_t &device, UINT32 output, const char *target, double gain, UINT32 input)
	74	device_sound_interface::sound_route &device_sound_interface::static_add_route(device_t &device, UINT32 output, const char *target, double gain, UINT32 input, UINT32 mixoutput)
75	75	{
76	76	// find our sound interface
77	77	device_sound_interface *sound;
r14963	r14964
79	79	throw emu_fatalerror("MCFG_SOUND_ROUTE called on device '%s' with no sound interface", device.tag());
80	80
81	81	// append a new route to the list
82		sound->m_route_list.append(*global_alloc(sound_route(output, input, gain, target)));
	82	return sound->m_route_list.append(*global_alloc(sound_route(output, input, gain, target, mixoutput)));
83	83	}
84	84
85	85
r14963	r14964
356	356	//  sound_route - constructor
357	357	//-------------------------------------------------
358	358
359		device_sound_interface::sound_route::sound_route(int output, int input, float gain, const char *target)
	359	device_sound_interface::sound_route::sound_route(int output, int input, float gain, const char *target, UINT32 mixoutput)
360	360	: m_next(NULL),
361	361	m_output(output),
362	362	m_input(input),
	363	m_mixoutput(mixoutput),
363	364	m_gain(gain),
364	365	m_target(target)
365	366	{
r14963	r14964
409	410	return;
410	411	}
411	412
	413	// generate the output map
	414	m_outputmap.resize(m_auto_allocated_inputs);
	415
	416	// iterate through all routes that point to us and note their mixer output
	417	sound_interface_iterator iter(m_device.machine().root_device());
	418	for (device_sound_interface *sound = iter.first(); sound != NULL; sound = iter.next())
	419	for (const sound_route *route = sound->first_route(); route != NULL; route = route->next())
	420	{
	421	// see if we are the target of this route
	422	device_t *target_device = sound->device().siblingdevice(route->m_target);
	423	if (target_device == &device() && route->m_input < m_auto_allocated_inputs)
	424	{
	425	int count = (route->m_output == ALL_OUTPUTS) ? sound->outputs() : 1;
	426	for (int output = 0; output < count; output++)
	427	m_outputmap[route->m_input + output] = route->m_mixoutput;
	428	}
	429	}
	430
412	431	// allocate the mixer stream
413	432	m_mixer_stream = stream_alloc(m_auto_allocated_inputs, m_outputs, device().machine().sample_rate());
414	433	}
r14963	r14964
435	454
436	455	void device_mixer_interface::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
437	456	{
	457	// clear output buffers
	458	for (int output = 0; output < m_outputs; output++)
	459	memset(outputs[output], 0, samples * sizeof(outputs[0][0]));
	460
438	461	// loop over samples
	462	const UINT8 *outmap = &m_outputmap[0];
439	463	for (int pos = 0; pos < samples; pos++)
440	464	{
441		// add up all the inputs
442		INT32 sample = inputs[0][pos];
443		for (int inp = 1; inp < m_auto_allocated_inputs; inp++)
444		sample += inputs[inp][pos];
445		outputs[0][pos] = sample;
	465	// for each input, add it to the appropriate output
	466	for (int inp = 0; inp < m_auto_allocated_inputs; inp++)
	467	outputs[outmap[inp]][pos] += inputs[inp][pos];
446	468	}
447	469	}

src/emu/disound.h

r14963	r14964
75	75	#define MCFG_SOUND_CONFIG(_config) \
76	76	MCFG_DEVICE_CONFIG(_config)
77	77
	78	#define MCFG_SOUND_ROUTE(_output, _target, _gain) \
	79	device_sound_interface::static_add_route(*device, _output, _target, _gain); \
	80
78	81	#define MCFG_SOUND_ROUTE_EX(_output, _target, _gain, _input) \
79	82	device_sound_interface::static_add_route(*device, _output, _target, _gain, _input); \
80	83
81		#define MCFG_SOUND_ROUTE(_output, _target, _gain) \
82		MCFG_SOUND_ROUTE_EX(_output, _target, _gain, AUTO_ALLOC_INPUT)
83
84	84	#define MCFG_SOUND_ROUTES_RESET() \
85	85	device_sound_interface::static_reset_routes(*device); \
86	86
87	87
	88	#define MCFG_MIXER_ROUTE(_output, _target, _gain, _mixoutput) \
	89	device_sound_interface::static_add_route(*device, _output, _target, _gain, AUTO_ALLOC_INPUT, _mixoutput); \
88	90
	91
	92
89	93	//**************************************************************************
90	94	//  TYPE DEFINITIONS
91	95	//**************************************************************************
r14963	r14964
101	105	class sound_route
102	106	{
103	107	public:
104		sound_route(int output, int input, float gain, const char *target);
	108	sound_route(int output, int input, float gain, const char *target, UINT32 mixoutput);
105	109
106	110	const sound_route *next() const { return m_next; }
107	111
108	112	sound_route *      m_next;            // pointer to next route
109	113	UINT32            m_output;         // output index, or ALL_OUTPUTS
110	114	UINT32            m_input;         // target input index
	115	UINT32            m_mixoutput;      // target mixer output
111	116	float            m_gain;            // gain
112	117	astring            m_target;         // target tag
113	118	};
r14963	r14964
120	125	const sound_route *first_route() const { return m_route_list.first(); }
121	126
122	127	// static inline configuration helpers
123		static void static_add_route(device_t &device, UINT32 output, const char *target, double gain, UINT32 input = AUTO_ALLOC_INPUT);
	128	static sound_route &static_add_route(device_t &device, UINT32 output, const char *target, double gain, UINT32 input = AUTO_ALLOC_INPUT, UINT32 mixoutput = 0);
124	129	static void static_reset_routes(device_t &device);
125	130
126	131	// sound stream update overrides
r14963	r14964
173	178
174	179	// internal state
175	180	UINT8            m_outputs;            // number of outputs
	181	dynamic_array<UINT8> m_outputmap;         // map of inputs to outputs
176	182	sound_stream *      m_mixer_stream;         // mixing stream
177	183	};
178	184

src/emu/device.c

r14963	r14964
203	203
204	204
205	205	//-------------------------------------------------
	206	//  subregion - return a pointer to the memory
	207	//  bank info for a given bank
	208	//-------------------------------------------------
	209
	210	memory_bank *device_t::subbank(const char *_tag) const
	211	{
	212	// safety first
	213	if (this == NULL)
	214	return NULL;
	215
	216	// build a fully-qualified name and look it up
	217	astring fullpath;
	218	return machine().memory().bank(subtag(fullpath, _tag));
	219	}
	220
	221
	222	//-------------------------------------------------
206	223	//  static_set_clock - set/change the clock on
207	224	//  a device
208	225	//-------------------------------------------------

src/emu/device.h

r14963	r14964
184	184	astring &subtag(astring &dest, const char *tag) const;
185	185	astring &siblingtag(astring &dest, const char *tag) const { return (this != NULL && m_owner != NULL) ? m_owner->subtag(dest, tag) : dest.cpy(tag); }
186	186	const memory_region *subregion(const char *tag) const;
	187	memory_bank *subbank(const char *tag) const;
187	188	device_t *subdevice(const char *tag) const;
188	189	device_t *siblingdevice(const char *tag) const;
189	190	template<class _DeviceClass> inline _DeviceClass *subdevice(const char *tag) const { return downcast<_DeviceClass *>(subdevice(tag)); }

src/emu/memory.c

r14963	r14964
1558	1558	//**************************************************************************
1559	1559
1560	1560	//-------------------------------------------------
1561		//  configure_bank - configure the addresses for a
1562		//  bank
1563		//-------------------------------------------------
1564
1565		void memory_manager::configure_bank(const char *tag, int startentry, int numentries, void *base, offs_t stride)
1566		{
1567		configure_bank(machine().root_device(), tag, startentry, numentries, base, stride);
1568		}
1569
1570		void memory_manager::configure_bank(device_t &device, const char *tag, int startentry, int numentries, void *base, offs_t stride)
1571		{
1572		// validation checks
1573		astring fulltag;
1574		memory_bank *bank = m_bankmap.find_hash_only(device.subtag(fulltag, tag));
1575		if (bank == NULL)
1576		fatalerror("configure_bank called for unknown bank '%s'", fulltag.cstr());
1577		if (base == NULL)
1578		fatalerror("configure_bank called NULL base");
1579
1580		// fill in the requested bank entries (backwards to improve allocation)
1581		for (int entrynum = startentry + numentries - 1; entrynum >= startentry; entrynum--)
1582		bank->configure(entrynum, reinterpret_cast<UINT8 *>(base) + (entrynum - startentry) * stride);
1583		}
1584
1585
1586		//-------------------------------------------------
1587		//  configure_bank_decrypted - configure the
1588		//  decrypted addresses for a bank
1589		//-------------------------------------------------
1590
1591		void memory_manager::configure_bank_decrypted(const char *tag, int startentry, int numentries, void *base, offs_t stride)
1592		{
1593		memory_configure_bank_decrypted(machine().root_device(), tag, startentry, numentries, base, stride);
1594		}
1595
1596		void memory_manager::configure_bank_decrypted(device_t &device, const char *tag, int startentry, int numentries, void *base, offs_t stride)
1597		{
1598		// validation checks
1599		astring fulltag;
1600		memory_bank *bank = m_bankmap.find_hash_only(device.subtag(fulltag, tag));
1601		if (bank == NULL)
1602		fatalerror("configure_bank_decrypted called for unknown bank '%s'", fulltag.cstr());
1603		if (base == NULL)
1604		fatalerror("configure_bank_decrypted called NULL base");
1605
1606		// fill in the requested bank entries (backwards to improve allocation)
1607		for (int entrynum = startentry + numentries - 1; entrynum >= startentry; entrynum--)
1608		bank->configure_decrypted(entrynum, reinterpret_cast<UINT8 *>(base) + (entrynum - startentry) * stride);
1609		}
1610
1611
1612		//-------------------------------------------------
1613		//  set_bank - select one pre-configured entry to
1614		//  be the new bank base
1615		//-------------------------------------------------
1616
1617		void memory_manager::set_bank(const char *tag, int entrynum)
1618		{
1619		set_bank(machine().root_device(), tag, entrynum);
1620		}
1621
1622		void memory_manager::set_bank(device_t &device, const char *tag, int entrynum)
1623		{
1624		// validation checks
1625		astring fulltag;
1626		memory_bank *bank = m_bankmap.find_hash_only(device.subtag(fulltag, tag));
1627		if (bank == NULL)
1628		fatalerror("set_bank called for unknown bank '%s'", fulltag.cstr());
1629
1630		// set the base
1631		bank->set_entry(entrynum);
1632		}
1633
1634
1635		//-------------------------------------------------
1636		//  get_bank - return the currently selected bank
1637		//-------------------------------------------------
1638
1639		int memory_manager::bank(const char *tag)
1640		{
1641		return bank(machine().root_device(), tag);
1642		}
1643
1644		int memory_manager::bank(device_t &device, const char *tag)
1645		{
1646		// validation checks
1647		astring fulltag;
1648		memory_bank *bank = m_bankmap.find_hash_only(device.subtag(fulltag, tag));
1649		if (bank == NULL)
1650		fatalerror("bank() called for unknown bank '%s'", fulltag.cstr());
1651
1652		// return the current entry
1653		return bank->entry();
1654		}
1655
1656
1657		//-------------------------------------------------
1658		//  set_bankptr - set the base of a bank
1659		//-------------------------------------------------
1660
1661		void memory_manager::set_bankptr(const char *tag, void *base)
1662		{
1663		set_bankptr(machine().root_device(), tag, base);
1664		}
1665
1666		void memory_manager::set_bankptr(device_t &device, const char *tag, void *base)
1667		{
1668		// validation checks
1669		astring fulltag;
1670		memory_bank *bank = m_bankmap.find_hash_only(device.subtag(fulltag, tag));
1671		if (bank == NULL)
1672		throw emu_fatalerror("memory_set_bankptr called for unknown bank '%s'", fulltag.cstr());
1673
1674		// set the base
1675		bank->set_base(base);
1676		}
1677
1678
1679		//-------------------------------------------------
1680	1561	//  shared - get a pointer to a shared memory
1681	1562	//  region by tag
1682	1563	//-------------------------------------------------
r14963	r14964
3015	2896	adjust_addresses(bytestart, byteend, bytemask, bytemirror);
3016	2897
3017	2898	// if this bank is named, look it up
3018		memory_bank *bank = NULL;
	2899	memory_bank *membank = NULL;
3019	2900	if (tag != NULL)
3020		bank = manager().m_bankmap.find_hash_only(tag);
	2901	membank = manager().bank(tag);
3021	2902
3022	2903	// else try to find an exact match
3023	2904	else
3024		for (bank = manager().m_banklist.first(); bank != NULL; bank = bank->next())
3025		if (bank->anonymous() && bank->references_space(*this, ROW_READWRITE) && bank->matches_exactly(bytestart, byteend))
	2905	for (membank = manager().m_banklist.first(); membank != NULL; membank = membank->next())
	2906	if (membank->anonymous() && membank->references_space(*this, ROW_READWRITE) && membank->matches_exactly(bytestart, byteend))
3026	2907	break;
3027	2908
3028	2909	// if we don't have a bank yet, find a free one
3029		if (bank == NULL)
	2910	if (membank == NULL)
3030	2911	{
3031	2912	// handle failure
3032	2913	int banknum = manager().m_banknext++;
r14963	r14964
3039	2920	}
3040	2921
3041	2922	// allocate the bank
3042		bank = global_alloc(memory_bank(*this, banknum, bytestart, byteend, tag));
3043		manager().m_banklist.append(*bank);
	2923	membank = global_alloc(memory_bank(*this, banknum, bytestart, byteend, tag));
	2924	manager().m_banklist.append(*membank);
3044	2925
3045	2926	// for named banks, add to the map and register for save states
3046	2927	if (tag != NULL)
3047		manager().m_bankmap.add_unique_hash(tag, bank, false);
	2928	manager().m_bankmap.add_unique_hash(tag, membank, false);
3048	2929	}
3049	2930
3050	2931	// add a reference for this space
3051		bank->add_reference(*this, readorwrite);
3052		return *bank;
	2932	membank->add_reference(*this, readorwrite);
	2933	return *membank;
3053	2934	}
3054	2935
3055	2936
r14963	r14964
4463	4344
4464	4345
4465	4346	//-------------------------------------------------
4466		//  configure - configure an entry
	4347	//  configure_entry - configure an entry
4467	4348	//-------------------------------------------------
4468	4349
4469		void memory_bank::configure(int entrynum, void *base)
	4350	void memory_bank::configure_entry(int entrynum, void *base)
4470	4351	{
4471	4352	// must be positive
4472	4353	if (entrynum < 0)
4473		throw emu_fatalerror("memory_bank::configure called with out-of-range entry %d", entrynum);
	4354	throw emu_fatalerror("memory_bank::configure_entry called with out-of-range entry %d", entrynum);
4474	4355
4475	4356	// if we haven't allocated this many entries yet, expand our array
4476	4357	if (entrynum >= m_entry_count)
r14963	r14964
4486	4367
4487	4368
4488	4369	//-------------------------------------------------
4489		//  configure_decrypted - configure a decrypted
4490		//  entry
	4370	//  configure_entries - configure multiple entries
4491	4371	//-------------------------------------------------
4492	4372
4493		void memory_bank::configure_decrypted(int entrynum, void *base)
	4373	void memory_bank::configure_entries(int startentry, int numentries, void *base, offs_t stride)
4494	4374	{
	4375	// fill in the requested bank entries (backwards to improve allocation)
	4376	for (int entrynum = startentry + numentries - 1; entrynum >= startentry; entrynum--)
	4377	configure_entry(entrynum, reinterpret_cast<UINT8 *>(base) + (entrynum - startentry) * stride);
	4378	}
	4379
	4380
	4381	//-------------------------------------------------
	4382	//  configure_decrypted_entry - configure a
	4383	//  decrypted entry
	4384	//-------------------------------------------------
	4385
	4386	void memory_bank::configure_decrypted_entry(int entrynum, void *base)
	4387	{
4495	4388	// must be positive
4496	4389	if (entrynum < 0)
4497		throw emu_fatalerror("memory_bank::configure called with out-of-range entry %d", entrynum);
	4390	throw emu_fatalerror("memory_bank::configure_decrypted_entry called with out-of-range entry %d", entrynum);
4498	4391
4499	4392	// if we haven't allocated this many entries yet, expand our array
4500	4393	if (entrynum >= m_entry_count)
r14963	r14964
4509	4402	}
4510	4403
4511	4404
	4405	//-------------------------------------------------
	4406	//  configure_decrypted_entries - configure
	4407	//  multiple decrypted entries
	4408	//-------------------------------------------------
4512	4409
	4410	void memory_bank::configure_decrypted_entries(int startentry, int numentries, void *base, offs_t stride)
	4411	{
	4412	// fill in the requested bank entries (backwards to improve allocation)
	4413	for (int entrynum = startentry + numentries - 1; entrynum >= startentry; entrynum--)
	4414	configure_decrypted_entry(entrynum, reinterpret_cast<UINT8 *>(base) + (entrynum - startentry) * stride);
	4415	}
	4416
	4417
4513	4418	//**************************************************************************
4514	4419	//  HANDLER ENTRY
4515	4420	//**************************************************************************
r14963	r14964
5637	5542
5638	5543
5639	5544	// configure the addresses for a bank
5640		void memory_configure_bank(running_machine &machine, const char *tag, int startentry, int numentries, void *base, offs_t stride) { machine.memory().configure_bank(tag, startentry, numentries, base, stride); }
5641		void memory_configure_bank(device_t &device, const char *tag, int startentry, int numentries, void *base, offs_t stride) { device.machine().memory().configure_bank(device, tag, startentry, numentries, base, stride); }
	5545	void memory_configure_bank(running_machine &machine, const char *tag, int startentry, int numentries, void *base, offs_t stride) { machine.root_device().subbank(tag)->configure_entries(startentry, numentries, base, stride); }
5642	5546
5643	5547	// configure the decrypted addresses for a bank
5644		void memory_configure_bank_decrypted(running_machine &machine, const char *tag, int startentry, int numentries, void *base, offs_t stride) { machine.memory().configure_bank_decrypted(tag, startentry, numentries, base, stride); }
5645		void memory_configure_bank_decrypted(device_t &device, const char *tag, int startentry, int numentries, void *base, offs_t stride) { device.machine().memory().configure_bank_decrypted(device, tag, startentry, numentries, base, stride); }
	5548	void memory_configure_bank_decrypted(running_machine &machine, const char *tag, int startentry, int numentries, void *base, offs_t stride) { machine.root_device().subbank(tag)->configure_decrypted_entries(startentry, numentries, base, stride); }
5646	5549
5647	5550	// select one pre-configured entry to be the new bank base
5648		void memory_set_bank(running_machine &machine, const char *tag, int entrynum) { machine.memory().set_bank(tag, entrynum); }
5649		void memory_set_bank(device_t &device, const char *tag, int entrynum) { device.machine().memory().set_bank(device, tag, entrynum); }
	5551	void memory_set_bank(running_machine &machine, const char *tag, int entrynum) { machine.root_device().subbank(tag)->set_entry(entrynum); }
5650	5552
5651	5553	// set the absolute address of a bank base
5652		void memory_set_bankptr(running_machine &machine, const char *tag, void *base) { machine.memory().set_bankptr(tag, base); }
5653		void memory_set_bankptr(device_t &device, const char *tag, void *base) { device.machine().memory().set_bankptr(device, tag, base); }
	5554	void memory_set_bankptr(running_machine &machine, const char *tag, void *base) { machine.root_device().subbank(tag)->set_base(base); }

src/emu/memory.h

r14963	r14964
679	679	void set_base_decrypted(void *base);
680	680
681	681	// configure and set entries
682		void configure(int entrynum, void *base);
683		void configure_decrypted(int entrynum, void *base);
	682	void configure_entry(int entrynum, void *base);
	683	void configure_entries(int startentry, int numentries, void *base, offs_t stride);
	684	void configure_decrypted_entry(int entrynum, void *base);
	685	void configure_decrypted_entries(int startentry, int numentries, void *base, offs_t stride);
684	686	void set_entry(int entrynum);
685	687
686	688	private:
r14963	r14964
753	755	running_machine &machine() const { return m_machine; }
754	756	address_space *first_space() const { return m_spacelist.first(); }
755	757	memory_bank *first_bank() const { return m_banklist.first(); }
	758	memory_bank *bank(const char *tag) const { return m_bankmap.find_hash_only(tag); }
756	759
757		// configure the addresses for a bank
758		void configure_bank(const char *tag, int startentry, int numentries, void *base, offs_t stride);
759		void configure_bank(device_t &device, const char *tag, int startentry, int numentries, void *base, offs_t stride);
760
761		// configure the decrypted addresses for a bank
762		void configure_bank_decrypted(const char *tag, int startentry, int numentries, void *base, offs_t stride);
763		void configure_bank_decrypted(device_t &device, const char *tag, int startentry, int numentries, void *base, offs_t stride);
764
765		// select one pre-configured entry to be the new bank base
766		void set_bank(const char *tag, int entrynum);
767		void set_bank(device_t &device, const char *tag, int entrynum);
768
769		// return the currently selected bank
770		int bank(const char *tag);
771		int bank(device_t &device, const char *tag);
772
773		// set the absolute address of a bank base
774		void set_bankptr(const char *tag, void *base) ATTR_NONNULL(3);
775		void set_bankptr(device_t &device, const char *tag, void *base) ATTR_NONNULL(3);
776
777	760	// get a pointer to a shared memory region by tag
778	761	memory_share *shared(const char *tag);
779	762	memory_share *shared(device_t &device, const char *tag);
r14963	r14964
922	905
923	906	// configure the addresses for a bank
924	907	void memory_configure_bank(running_machine &machine, const char *tag, int startentry, int numentries, void *base, offs_t stride) ATTR_NONNULL(5);
925		void memory_configure_bank(device_t &device, const char *tag, int startentry, int numentries, void *base, offs_t stride) ATTR_NONNULL(5);
926	908
927	909	// configure the decrypted addresses for a bank
928	910	void memory_configure_bank_decrypted(running_machine &machine, const char *tag, int startentry, int numentries, void *base, offs_t stride) ATTR_NONNULL(5);
929		void memory_configure_bank_decrypted(device_t &device, const char *tag, int startentry, int numentries, void *base, offs_t stride) ATTR_NONNULL(5);
930	911
931	912	// select one pre-configured entry to be the new bank base
932	913	void memory_set_bank(running_machine &machine, const char *tag, int entrynum);
933		void memory_set_bank(device_t &device, const char *tag, int entrynum);
934	914
935	915	// set the absolute address of a bank base
936	916	void memory_set_bankptr(running_machine &machine, const char *tag, void *base) ATTR_NONNULL(3);
937		void memory_set_bankptr(device_t &device, const char *tag, void *base) ATTR_NONNULL(3);
938	917
939	918
940	919

src/emu/diexec.c

r14963	r14964
529	529
530	530	void device_execute_interface::interface_pre_start()
531	531	{
	532	// bind delegates
	533	m_vblank_interrupt.bind_relative_to(device());
	534	m_timed_interrupt.bind_relative_to(device());
	535	//   m_driver_irq.bind_relative_to(device());
	536
532	537	// fill in the initial states
533	538	execute_interface_iterator iter(device().machine().root_device());
534	539	int index = iter.indexof(*this);

src/emu/diexec.h

r14963	r14964
123	123	device_execute_interface::static_set_vblank_int(*device, _func, _tag); \
124	124
125	125	#define MCFG_DEVICE_VBLANK_INT_DRIVER(_tag, _class, _func) \
126		device_execute_interface::static_set_vblank_int(*device, device_interrupt_delegate(&_class::_func, #_class "::" #_func, downcast<_class *>(&config.root_device())), _tag); \
	126	device_execute_interface::static_set_vblank_int(*device, device_interrupt_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF_OWNER, (_class *)0), _tag); \
127	127
	128	#define MCFG_DEVICE_VBLANK_INT_DEVICE(_devtag, _tag, _class, _func) \
	129	device_execute_interface::static_set_vblank_int(*device, device_interrupt_delegate(&_class::_func, #_class "::" #_func, _devtag, (_class *)0), _tag); \
	130
128	131	#define MCFG_DEVICE_PERIODIC_INT(_func, _rate)   \
129	132	device_execute_interface::static_set_periodic_int(*device, _func, attotime::from_hz(_rate)); \
130	133
131	134	#define MCFG_DEVICE_PERIODIC_INT_DRIVER(_class, _func, _rate) \
132		device_execute_interface::static_set_periodic_int(*device, device_interrupt_delegate(&_class::_func, #_class "::" #_func, downcast<_class *>(&config.root_device())), attotime::from_hz(_rate)); \
	135	device_execute_interface::static_set_periodic_int(*device, device_interrupt_delegate(&_class::_func, #_class "::" #_func, DEVICE_SELF_OWNER, (_class *)0), attotime::from_hz(_rate)); \
133	136
	137	#define MCFG_DEVICE_PERIODIC_INT_DEVICE(_devtag, _class, _func, _rate) \
	138	device_execute_interface::static_set_periodic_int(*device, device_interrupt_delegate(&_class::_func, #_class "::" #_func, _devtag, (_class *)0), attotime::from_hz(_rate)); \
134	139
135	140
	141
136	142	//**************************************************************************
137	143	//  TYPE DEFINITIONS
138	144	//**************************************************************************
r14963	r14964
142	148
143	149
144	150	// interrupt callback for VBLANK and timed interrupts
145		typedef delegate<void (device_t &)> device_interrupt_delegate;
	151	typedef device_delegate<void (device_t &)> device_interrupt_delegate;
146	152	typedef void (*device_interrupt_func)(device_t *device);
147	153
148	154	// IRQ callback to be called by executing devices when an IRQ is actually taken
149		typedef delegate<void (device_t &, int)> device_irq_acknowledge_delegate;
	155	typedef device_delegate<void (device_t &, int)> device_irq_acknowledge_delegate;
150	156	typedef int (*device_irq_acknowledge_callback)(device_t *device, int irqnum);
151	157
152	158

src/mess/machine/apple3.c

r14963	r14964
48	48
49	49
50	50
51		static UINT8 apple3_profile_r(apple3_state *state, offs_t offset)
	51	UINT8 apple3_state::apple3_profile_r(offs_t offset)
52	52	{
53	53	UINT8 result = 0;
54	54
55	55	offset %= 4;
56	56	apple3_profile_statemachine();
57	57
58		state->m_profile_lastaddr = offset;
	58	m_profile_lastaddr = offset;
59	59
60	60	switch(offset)
61	61	{
62	62	case 1:
63		state->m_profile_gotstrobe = 1;
	63	m_profile_gotstrobe = 1;
64	64	apple3_profile_statemachine();
65		result = state->m_profile_readdata;
	65	result = m_profile_readdata;
66	66	break;
67	67
68	68	case 2:
69		if (state->m_profile_busycount > 0)
	69	if (m_profile_busycount > 0)
70	70	{
71		state->m_profile_busycount--;
	71	m_profile_busycount--;
72	72	result = 0xFF;
73	73	}
74	74	else
75	75	{
76		result = state->m_profile_busy | state->m_profile_online;
	76	result = m_profile_busy | m_profile_online;
77	77	}
78	78	break;
79	79	}
r14963	r14964
82	82
83	83
84	84
85		static void apple3_profile_w(apple3_state *state, offs_t offset, UINT8 data)
	85	void apple3_state::apple3_profile_w(offs_t offset, UINT8 data)
86	86	{
87	87	offset %= 4;
88		state->m_profile_lastaddr = -1;
	88	m_profile_lastaddr = -1;
89	89
90	90	switch(offset)
91	91	{
92	92	case 0:
93		state->m_profile_writedata = data;
94		state->m_profile_gotstrobe = 1;
	93	m_profile_writedata = data;
	94	m_profile_gotstrobe = 1;
95	95	break;
96	96	}
97	97	apple3_profile_statemachine();
r14963	r14964
101	101
102	102	/* ----------------------------------------------------------------------- */
103	103
104		static READ8_HANDLER( apple3_c0xx_r )
	104	READ8_MEMBER(apple3_state::apple3_c0xx_r)
105	105	{
106		apple3_state *state = space->machine().driver_data<apple3_state>();
107		acia6551_device *acia = space->machine().device<acia6551_device>("acia");
108		device_t *fdc = space->machine().device("fdc");
	106	acia6551_device *acia = machine().device<acia6551_device>("acia");
	107	device_t *fdc = machine().device("fdc");
109	108	UINT8 result = 0xFF;
110	109
111	110	switch(offset)
112	111	{
113	112	case 0x00: case 0x01: case 0x02: case 0x03:
114	113	case 0x04: case 0x05: case 0x06: case 0x07:
115		result = AY3600_keydata_strobe_r(space->machine());
	114	result = AY3600_keydata_strobe_r(machine());
116	115	break;
117	116
118	117	case 0x08: case 0x09: case 0x0A: case 0x0B:
r14963	r14964
125	124	case 0x14: case 0x15: case 0x16: case 0x17:
126	125	case 0x18: case 0x19: case 0x1A: case 0x1B:
127	126	case 0x1C: case 0x1D: case 0x1E: case 0x1F:
128		AY3600_anykey_clearstrobe_r(space->machine());
	127	AY3600_anykey_clearstrobe_r(machine());
129	128	break;
130	129
131	130	case 0x50: case 0x51: case 0x52: case 0x53:
132	131	case 0x54: case 0x55: case 0x56: case 0x57:
133	132	/* graphics softswitches */
134	133	if (offset & 1)
135		state->m_flags |= 1 << ((offset - 0x50) / 2);
	134	m_flags |= 1 << ((offset - 0x50) / 2);
136	135	else
137		state->m_flags &= ~(1 << ((offset - 0x50) / 2));
	136	m_flags &= ~(1 << ((offset - 0x50) / 2));
138	137	break;
139	138
140	139	case 0x60: case 0x61: case 0x62: case 0x63:
r14963	r14964
150	149	case 0xC8: case 0xC9: case 0xCA: case 0xCB:
151	150	case 0xCC: case 0xCD: case 0xCE: case 0xCF:
152	151	/* profile */
153		result = apple3_profile_r(state, offset);
	152	result = apple3_profile_r(offset);
154	153	break;
155	154
156	155	case 0xD0: case 0xD1: case 0xD2: case 0xD3:
157	156	case 0xD4: case 0xD5: case 0xD6: case 0xD7:
158	157	/* external drive stuff */
159	158	if (offset & 1)
160		state->m_flags |= VAR_EXTA0 << ((offset - 0xD0) / 2);
	159	m_flags |= VAR_EXTA0 << ((offset - 0xD0) / 2);
161	160	else
162		state->m_flags &= ~(VAR_EXTA0 << ((offset - 0xD0) / 2));
163		apple3_update_drives(space->machine().device("fdc"));
	161	m_flags &= ~(VAR_EXTA0 << ((offset - 0xD0) / 2));
	162	apple3_update_drives(machine().device("fdc"));
164	163	result = 0x00;
165	164	break;
166	165
167	166	case 0xDB:
168		apple3_write_charmem(space->machine());
	167	apple3_write_charmem(machine());
169	168	break;
170	169
171	170	case 0xE0: case 0xE1: case 0xE2: case 0xE3:
r14963	r14964
179	178	case 0xF1:
180	179	case 0xF2:
181	180	case 0xF3:
182		result = acia->read(*space, offset & 0x03);
	181	result = acia->read(space, offset & 0x03);
183	182	break;
184	183	}
185	184	return result;
r14963	r14964
187	186
188	187
189	188
190		static WRITE8_HANDLER( apple3_c0xx_w )
	189	WRITE8_MEMBER(apple3_state::apple3_c0xx_w)
191	190	{
192		apple3_state *state = space->machine().driver_data<apple3_state>();
193		acia6551_device *acia = space->machine().device<acia6551_device>("acia");
194		device_t *fdc = space->machine().device("fdc");
	191	acia6551_device *acia = machine().device<acia6551_device>("acia");
	192	device_t *fdc = machine().device("fdc");
195	193	switch(offset)
196	194	{
197	195	case 0x10: case 0x11: case 0x12: case 0x13:
198	196	case 0x14: case 0x15: case 0x16: case 0x17:
199	197	case 0x18: case 0x19: case 0x1A: case 0x1B:
200	198	case 0x1C: case 0x1D: case 0x1E: case 0x1F:
201		AY3600_anykey_clearstrobe_r(space->machine());
	199	AY3600_anykey_clearstrobe_r(machine());
202	200	break;
203	201
204	202	case 0x50: case 0x51: case 0x52: case 0x53:
205	203	case 0x54: case 0x55: case 0x56: case 0x57:
206	204	/* graphics softswitches */
207	205	if (offset & 1)
208		state->m_flags |= 1 << ((offset - 0x50) / 2);
	206	m_flags |= 1 << ((offset - 0x50) / 2);
209	207	else
210		state->m_flags &= ~(1 << ((offset - 0x50) / 2));
	208	m_flags &= ~(1 << ((offset - 0x50) / 2));
211	209	break;
212	210
213	211	case 0xC0: case 0xC1: case 0xC2: case 0xC3:
r14963	r14964
215	213	case 0xC8: case 0xC9: case 0xCA: case 0xCB:
216	214	case 0xCC: case 0xCD: case 0xCE: case 0xCF:
217	215	/* profile */
218		apple3_profile_w(state, offset, data);
	216	apple3_profile_w(offset, data);
219	217	break;
220	218
221	219	case 0xD0: case 0xD1: case 0xD2: case 0xD3:
222	220	case 0xD4: case 0xD5: case 0xD6: case 0xD7:
223	221	/* external drive stuff */
224	222	if (offset & 1)
225		state->m_flags |= VAR_EXTA0 << ((offset - 0xD0) / 2);
	223	m_flags |= VAR_EXTA0 << ((offset - 0xD0) / 2);
226	224	else
227		state->m_flags &= ~(VAR_EXTA0 << ((offset - 0xD0) / 2));
228		apple3_update_drives(space->machine().device("fdc"));
	225	m_flags &= ~(VAR_EXTA0 << ((offset - 0xD0) / 2));
	226	apple3_update_drives(machine().device("fdc"));
229	227	break;
230	228
231	229	case 0xDB:
232		apple3_write_charmem(space->machine());
	230	apple3_write_charmem(machine());
233	231	break;
234	232
235	233	case 0xE0: case 0xE1: case 0xE2: case 0xE3:
r14963	r14964
243	241	case 0xF1:
244	242	case 0xF2:
245	243	case 0xF3:
246		acia->write(*space, offset & 0x03, data);
	244	acia->write(space, offset & 0x03, data);
247	245	break;
248	246	}
249	247	}
r14963	r14964
308	306
309	307
310	308
311		READ8_HANDLER( apple3_00xx_r )
	309	READ8_MEMBER(apple3_state::apple3_00xx_r)
312	310	{
313		return *apple3_get_zpa_addr(space->machine(),offset);
	311	return *apple3_get_zpa_addr(machine(),offset);
314	312	}
315	313
316	314
317	315
318		WRITE8_HANDLER( apple3_00xx_w )
	316	WRITE8_MEMBER(apple3_state::apple3_00xx_w)
319	317	{
320		*apple3_get_zpa_addr(space->machine(),offset) = data;
	318	*apple3_get_zpa_addr(machine(),offset) = data;
321	319	}
322	320
323	321
r14963	r14964
374	372	/* install bank 8 (C000-CFFF) */
375	373	if (state->m_via_0_a & 0x40)
376	374	{
377		space->install_legacy_read_handler(0xC000, 0xC0FF, FUNC(apple3_c0xx_r));
378		space->install_legacy_write_handler(0xC000, 0xC0FF, FUNC(apple3_c0xx_w));
	375	space->install_read_handler(0xC000, 0xC0FF, read8_delegate(FUNC(apple3_state::apple3_c0xx_r),state));
	376	space->install_write_handler(0xC000, 0xC0FF, write8_delegate(FUNC(apple3_state::apple3_c0xx_w),state));
379	377	}
380	378	else
381	379	{
r14963	r14964
623	621
624	622
625	623
626		READ8_HANDLER( apple3_indexed_read )
	624	READ8_MEMBER(apple3_state::apple3_indexed_read)
627	625	{
628	626	UINT8 result;
629	627	UINT8 *addr;
630	628
631		addr = apple3_get_indexed_addr(space->machine(),offset);
	629	addr = apple3_get_indexed_addr(machine(),offset);
632	630	if (!addr)
633		result = space->read_byte(offset);
	631	result = space.read_byte(offset);
634	632	else if (addr != (UINT8 *) ~0)
635	633	result = *addr;
636	634	else
637		result = space->machine().region("maincpu")->base()[offset % space->machine().region("maincpu")->bytes()];
	635	result = machine().region("maincpu")->base()[offset % machine().region("maincpu")->bytes()];
638	636	return result;
639	637	}
640	638
641	639
642	640
643		WRITE8_HANDLER( apple3_indexed_write )
	641	WRITE8_MEMBER(apple3_state::apple3_indexed_write)
644	642	{
645	643	UINT8 *addr;
646	644
647		addr = apple3_get_indexed_addr(space->machine(),offset);
	645	addr = apple3_get_indexed_addr(machine(),offset);
648	646	if (!addr)
649		space->write_byte(offset, data);
	647	space.write_byte(offset, data);
650	648	else if (addr != (UINT8 *) ~0)
651	649	*addr = data;
652	650	}

src/mess/machine/dai.c

r14963	r14964
29	29
30	30	/* Memory */
31	31
32		WRITE8_HANDLER( dai_stack_interrupt_circuit_w )
	32	WRITE8_MEMBER(dai_state::dai_stack_interrupt_circuit_w)
33	33	{
34		dai_state *state = space->machine().driver_data<dai_state>();
35		tms5501_sensor (state->m_tms5501, 1);
36		tms5501_sensor (state->m_tms5501, 0);
	34	tms5501_sensor (m_tms5501, 1);
	35	tms5501_sensor (m_tms5501, 0);
37	36	}
38	37
39	38	static void dai_update_memory(running_machine &machine, int dai_rom_bank)
r14963	r14964
187	186	bit 6-7         ROM bank switching
188	187	***************************************************************************/
189	188
190		READ8_HANDLER( dai_io_discrete_devices_r )
	189	READ8_MEMBER(dai_state::dai_io_discrete_devices_r)
191	190	{
192	191	UINT8 data = 0x00;
193	192
194	193	switch(offset & 0x000f) {
195	194	case 0x00:
196		data = input_port_read(space->machine(), "IN8");
	195	data = input_port_read(machine(), "IN8");
197	196	data |= 0x08;         // serial ready
198		if (space->machine().rand()&0x01)
	197	if (machine().rand()&0x01)
199	198	data |= 0x40;      // random number generator
200		if (space->machine().device<cassette_image_device>(CASSETTE_TAG)->input() > 0.01)
	199	if (machine().device<cassette_image_device>(CASSETTE_TAG)->input() > 0.01)
201	200	data |= 0x80;      // tape input
202	201	break;
203	202
r14963	r14964
210	209	return data;
211	210	}
212	211
213		WRITE8_HANDLER( dai_io_discrete_devices_w )
	212	WRITE8_MEMBER(dai_state::dai_io_discrete_devices_w)
214	213	{
215		dai_state *state = space->machine().driver_data<dai_state>();
216	214	switch(offset & 0x000f) {
217	215	case 0x04:
218		dai_set_volume(state->m_sound, offset, data);
	216	dai_set_volume(m_sound, offset, data);
219	217	LOG_DAI_PORT_W (offset, data&0x0f, "discrete devices - osc. 0 volume");
220	218	LOG_DAI_PORT_W (offset, (data&0xf0)>>4, "discrete devices - osc. 1 volume");
221	219	break;
222	220
223	221	case 0x05:
224		dai_set_volume(state->m_sound, offset, data);
	222	dai_set_volume(m_sound, offset, data);
225	223	LOG_DAI_PORT_W (offset, data&0x0f, "discrete devices - osc. 2 volume");
226	224	LOG_DAI_PORT_W (offset, (data&0xf0)>>4, "discrete devices - noise volume");
227	225	break;
228	226
229	227	case 0x06:
230		state->m_paddle_select = (data&0x06)>>2;
231		state->m_paddle_enable = (data&0x08)>>3;
232		state->m_cassette_motor[0] = (data&0x10)>>4;
233		state->m_cassette_motor[1] = (data&0x20)>>5;
234		space->machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(state->m_cassette_motor[0]?CASSETTE_MOTOR_DISABLED:CASSETTE_MOTOR_ENABLED, CASSETTE_MASK_MOTOR);
235		space->machine().device<cassette_image_device>(CASSETTE_TAG)->output((data & 0x01) ? -1.0 : 1.0);
236		dai_update_memory (space->machine(), (data&0xc0)>>6);
	228	m_paddle_select = (data&0x06)>>2;
	229	m_paddle_enable = (data&0x08)>>3;
	230	m_cassette_motor[0] = (data&0x10)>>4;
	231	m_cassette_motor[1] = (data&0x20)>>5;
	232	machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(m_cassette_motor[0]?CASSETTE_MOTOR_DISABLED:CASSETTE_MOTOR_ENABLED, CASSETTE_MASK_MOTOR);
	233	machine().device<cassette_image_device>(CASSETTE_TAG)->output((data & 0x01) ? -1.0 : 1.0);
	234	dai_update_memory (machine(), (data&0xc0)>>6);
237	235	LOG_DAI_PORT_W (offset, (data&0x06)>>2, "discrete devices - paddle select");
238	236	LOG_DAI_PORT_W (offset, (data&0x08)>>3, "discrete devices - paddle enable");
239	237	LOG_DAI_PORT_W (offset, (data&0x10)>>4, "discrete devices - cassette motor 1");
r14963	r14964
253	251
254	252	***************************************************************************/
255	253
256		READ8_HANDLER( dai_amd9511_r )
	254	READ8_MEMBER(dai_state::dai_amd9511_r)
257	255	{
258	256	/* optional and no present at this moment */
259	257	return 0xff;
260	258	}
261	259
262		WRITE8_HANDLER( dai_amd9511_w )
	260	WRITE8_MEMBER(dai_state::dai_amd9511_w)
263	261	{
264	262	logerror ("Writing to AMD9511 math chip, %04x, %02x\n", offset, data);
265	263	}

src/mess/machine/cbmb.c

r14963	r14964
270	270	DEVCB_NULL
271	271	};
272	272
273		WRITE8_HANDLER( cbmb_colorram_w )
	273	WRITE8_MEMBER(cbmb_state::cbmb_colorram_w)
274	274	{
275		cbmb_state *state = space->machine().driver_data<cbmb_state>();
276		state->m_colorram[offset] = data | 0xf0;
	275	m_colorram[offset] = data | 0xf0;
277	276	}
278	277
279	278	WRITE_LINE_DEVICE_HANDLER( cbmb_change_font )

src/mess/machine/pmd85.c

r14963	r14964
516	516
517	517	*******************************************************************************/
518	518
519		READ8_HANDLER ( pmd85_io_r )
	519	READ8_MEMBER(pmd85_state::pmd85_io_r)
520	520	{
521		pmd85_state *state = space->machine().driver_data<pmd85_state>();
522		i8251_device *uart = space->machine().device<i8251_device>("uart");
523		if (state->m_startup_mem_map)
	521	i8251_device *uart = machine().device<i8251_device>("uart");
	522	if (m_startup_mem_map)
524	523	{
525	524	return 0xff;
526	525	}
r14963	r14964
531	530	switch (offset & 0x80)
532	531	{
533	532	case 0x80:   /* Motherboard 8255 */
534		return space->machine().device<i8255_device>("ppi8255_0")->read(*space, offset & 0x03);
	533	return machine().device<i8255_device>("ppi8255_0")->read(space, offset & 0x03);
535	534	}
536	535	break;
537	536	case 0x08:   /* ROM module connector */
538		switch (state->m_model)
	537	switch (m_model)
539	538	{
540	539	case PMD85_1:
541	540	case PMD85_2:
542	541	case PMD85_2A:
543	542	case C2717:
544	543	case PMD85_3:
545		if (state->m_rom_module_present)
	544	if (m_rom_module_present)
546	545	{
547	546	switch (offset & 0x80)
548	547	{
549	548	case 0x80:   /* ROM module 8255 */
550		return space->machine().device<i8255_device>("ppi8255_3")->read(*space, offset & 0x03);
	549	return machine().device<i8255_device>("ppi8255_3")->read(space, offset & 0x03);
551	550	}
552	551	}
553	552	break;
r14963	r14964
562	561	case 0x10:   /* 8251 (casette recorder, V24) */
563	562	switch (offset & 0x01)
564	563	{
565		case 0x00: return uart->data_r(*space, offset & 0x01);
566		case 0x01: return uart->status_r(*space, offset & 0x01);
	564	case 0x00: return uart->data_r(space, offset & 0x01);
	565	case 0x01: return uart->status_r(space, offset & 0x01);
567	566	}
568	567	break;
569	568	case 0x40:      /* 8255 (GPIO/0, GPIO/1) */
570		return space->machine().device<i8255_device>("ppi8255_1")->read(*space, offset & 0x03);
	569	return machine().device<i8255_device>("ppi8255_1")->read(space, offset & 0x03);
571	570	case 0x50:   /* 8253 */
572		return pit8253_r( space->machine().device("pit8253"), offset & 0x03);
	571	return pit8253_r( machine().device("pit8253"), offset & 0x03);
573	572	case 0x70:   /* 8255 (IMS-2) */
574		return space->machine().device<i8255_device>("ppi8255_2")->read(*space, offset & 0x03);
	573	return machine().device<i8255_device>("ppi8255_2")->read(space, offset & 0x03);
575	574	}
576	575	break;
577	576	case 0x80:   /* external interfaces */
r14963	r14964
584	583	return 0xff;
585	584	}
586	585
587		WRITE8_HANDLER ( pmd85_io_w )
	586	WRITE8_MEMBER(pmd85_state::pmd85_io_w)
588	587	{
589		pmd85_state *state = space->machine().driver_data<pmd85_state>();
590		i8251_device *uart = space->machine().device<i8251_device>("uart");
591		if (state->m_startup_mem_map)
	588	i8251_device *uart = machine().device<i8251_device>("uart");
	589	if (m_startup_mem_map)
592	590	{
593		state->m_startup_mem_map = 0;
594		(*state->update_memory)(space->machine());
	591	m_startup_mem_map = 0;
	592	(*update_memory)(machine());
595	593	}
596	594
597	595	switch (offset & 0x0c)
r14963	r14964
600	598	switch (offset & 0x80)
601	599	{
602	600	case 0x80:   /* Motherboard 8255 */
603		space->machine().device<i8255_device>("ppi8255_0")->write(*space, offset & 0x03, data);
	601	machine().device<i8255_device>("ppi8255_0")->write(space, offset & 0x03, data);
604	602	/* PMD-85.3 memory banking */
605	603	if ((offset & 0x03) == 0x03)
606	604	{
607		state->m_pmd853_memory_mapping = data & 0x01;
608		(*state->update_memory)(space->machine());
	605	m_pmd853_memory_mapping = data & 0x01;
	606	(*update_memory)(machine());
609	607	}
610	608	break;
611	609	}
612	610	break;
613	611	case 0x08:   /* ROM module connector */
614		switch (state->m_model)
	612	switch (m_model)
615	613	{
616	614	case PMD85_1:
617	615	case PMD85_2:
618	616	case PMD85_2A:
619	617	case C2717:
620	618	case PMD85_3:
621		if (state->m_rom_module_present)
	619	if (m_rom_module_present)
622	620	{
623	621	switch (offset & 0x80)
624	622	{
625	623	case 0x80:   /* ROM module 8255 */
626		space->machine().device<i8255_device>("ppi8255_3")->write(*space, offset & 0x03, data);
	624	machine().device<i8255_device>("ppi8255_3")->write(space, offset & 0x03, data);
627	625	break;
628	626	}
629	627	}
r14963	r14964
639	637	case 0x10:   /* 8251 (casette recorder, V24) */
640	638	switch (offset & 0x01)
641	639	{
642		case 0x00: uart->data_w(*space, offset & 0x01, data); break;
643		case 0x01: uart->control_w(*space, offset & 0x01, data); break;
	640	case 0x00: uart->data_w(space, offset & 0x01, data); break;
	641	case 0x01: uart->control_w(space, offset & 0x01, data); break;
644	642	}
645	643	break;
646	644	case 0x40:      /* 8255 (GPIO/0, GPIO/0) */
647		space->machine().device<i8255_device>("ppi8255_1")->write(*space, offset & 0x03, data);
	645	machine().device<i8255_device>("ppi8255_1")->write(space, offset & 0x03, data);
648	646	break;
649	647	case 0x50:   /* 8253 */
650		pit8253_w(space->machine().device("pit8253"), offset & 0x03, data);
	648	pit8253_w(machine().device("pit8253"), offset & 0x03, data);
651	649	logerror ("8253 writing. Address: %02x, Data: %02x\n", offset, data);
652	650	break;
653	651	case 0x70:   /* 8255 (IMS-2) */
654		space->machine().device<i8255_device>("ppi8255_2")->write(*space, offset & 0x03, data);
	652	machine().device<i8255_device>("ppi8255_2")->write(space, offset & 0x03, data);
655	653	break;
656	654	}
657	655	break;
r14963	r14964
672	670
673	671	*******************************************************************************/
674	672
675		READ8_HANDLER ( mato_io_r )
	673	READ8_MEMBER(pmd85_state::mato_io_r)
676	674	{
677		pmd85_state *state = space->machine().driver_data<pmd85_state>();
678		if (state->m_startup_mem_map)
	675	if (m_startup_mem_map)
679	676	{
680	677	return 0xff;
681	678	}
r14963	r14964
686	683	switch (offset & 0x80)
687	684	{
688	685	case 0x80:   /* Motherboard 8255 */
689		return space->machine().device<i8255_device>("ppi8255_0")->read(*space, offset & 0x03);
	686	return machine().device<i8255_device>("ppi8255_0")->read(space, offset & 0x03);
690	687	}
691	688	break;
692	689	}
r14963	r14964
695	692	return 0xff;
696	693	}
697	694
698		WRITE8_HANDLER ( mato_io_w )
	695	WRITE8_MEMBER(pmd85_state::mato_io_w)
699	696	{
700		pmd85_state *state = space->machine().driver_data<pmd85_state>();
701		if (state->m_startup_mem_map)
	697	if (m_startup_mem_map)
702	698	{
703		state->m_startup_mem_map = 0;
704		(*state->update_memory)(space->machine());
	699	m_startup_mem_map = 0;
	700	(*update_memory)(machine());
705	701	}
706	702
707	703	switch (offset & 0x0c)
r14963	r14964
710	706	switch (offset & 0x80)
711	707	{
712	708	case 0x80:   /* Motherboard 8255 */
713		return space->machine().device<i8255_device>("ppi8255_0")->write(*space, offset & 0x03, data);
	709	return machine().device<i8255_device>("ppi8255_0")->write(space, offset & 0x03, data);
714	710	break;
715	711	}
716	712	break;

src/mess/machine/at.c

r14963	r14964
161	161	i8237_hlda_w( m_dma8237_2, state );
162	162	}
163	163
164		static READ8_HANDLER( pc_dma_read_byte )
	164	READ8_MEMBER(at_state::pc_dma_read_byte)
165	165	{
166		at_state *st = space->machine().driver_data<at_state>();
167	166	UINT8 result;
168		offs_t page_offset = (((offs_t) st->m_dma_offset[0][st->m_dma_channel]) << 16) & 0xFF0000;
	167	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
169	168
170		result = space->read_byte(page_offset + offset);
	169	result = space.read_byte(page_offset + offset);
171	170	return result;
172	171	}
173	172
174	173
175		static WRITE8_HANDLER( pc_dma_write_byte )
	174	WRITE8_MEMBER(at_state::pc_dma_write_byte)
176	175	{
177		at_state *st = space->machine().driver_data<at_state>();
178		offs_t page_offset = (((offs_t) st->m_dma_offset[0][st->m_dma_channel]) << 16) & 0xFF0000;
	176	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
179	177
180		space->write_byte(page_offset + offset, data);
	178	space.write_byte(page_offset + offset, data);
181	179	}
182	180
183	181
184		static READ8_HANDLER( pc_dma_read_word )
	182	READ8_MEMBER(at_state::pc_dma_read_word)
185	183	{
186		at_state *st = space->machine().driver_data<at_state>();
187	184	UINT16 result;
188		offs_t page_offset = (((offs_t) st->m_dma_offset[1][st->m_dma_channel & 3]) << 16) & 0xFF0000;
	185	offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFF0000;
189	186
190		result = space->read_word(page_offset + ( offset << 1 ) );
191		st->m_dma_high_byte = result & 0xFF00;
	187	result = space.read_word(page_offset + ( offset << 1 ) );
	188	m_dma_high_byte = result & 0xFF00;
192	189
193	190	return result & 0xFF;
194	191	}
195	192
196	193
197		static WRITE8_HANDLER( pc_dma_write_word )
	194	WRITE8_MEMBER(at_state::pc_dma_write_word)
198	195	{
199		at_state *st = space->machine().driver_data<at_state>();
200		offs_t page_offset = (((offs_t) st->m_dma_offset[1][st->m_dma_channel & 3]) << 16) & 0xFF0000;
	196	offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFF0000;
201	197
202		space->write_word(page_offset + ( offset << 1 ), st->m_dma_high_byte | data);
	198	space.write_word(page_offset + ( offset << 1 ), m_dma_high_byte | data);
203	199	}
204	200
205	201
r14963	r14964
242	238	{
243	239	DEVCB_DEVICE_LINE("dma8237_2",i8237_dreq0_w),
244	240	DEVCB_DRIVER_LINE_MEMBER(at_state, at_dma8237_out_eop),
245		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
246		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
	241	DEVCB_DRIVER_MEMBER(at_state, pc_dma_read_byte),
	242	DEVCB_DRIVER_MEMBER(at_state, pc_dma_write_byte),
247	243	{ DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_0_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_1_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_2_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_3_dack_r) },
248	244	{ DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_0_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_1_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_2_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_3_dack_w) },
249	245	{ DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack3_w) }
r14963	r14964
254	250	{
255	251	DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dma_hrq_changed),
256	252	DEVCB_NULL,
257		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_word),
258		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_word),
	253	DEVCB_DRIVER_MEMBER(at_state, pc_dma_read_word),
	254	DEVCB_DRIVER_MEMBER(at_state, pc_dma_write_word),
259	255	{ DEVCB_NULL, DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_5_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_6_dack_r), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_7_dack_r) },
260	256	{ DEVCB_NULL, DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_5_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_6_dack_w), DEVCB_DRIVER_MEMBER(at_state, pc_dma8237_7_dack_w) },
261	257	{ DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack4_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack5_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack6_w), DEVCB_DRIVER_LINE_MEMBER(at_state, pc_dack7_w) }

src/mess/machine/electron.c

r14963	r14964
18	18	return machine.device<cassette_image_device>(CASSETTE_TAG);
19	19	}
20	20
21		static void electron_tape_start( electron_state *state )
	21	void electron_state::electron_tape_start()
22	22	{
23		if ( state->m_ula.tape_running )
	23	if (m_ula.tape_running )
24	24	{
25	25	return;
26	26	}
27		state->m_ula.tape_steps = 0;
28		state->m_ula.tape_value = 0x80808080;
29		state->m_ula.high_tone_set = 0;
30		state->m_ula.bit_count = 0;
31		state->m_ula.tape_running = 1;
32		state->m_tape_timer->adjust(attotime::zero, 0, attotime::from_hz(4800));
	27	m_ula.tape_steps = 0;
	28	m_ula.tape_value = 0x80808080;
	29	m_ula.high_tone_set = 0;
	30	m_ula.bit_count = 0;
	31	m_ula.tape_running = 1;
	32	m_tape_timer->adjust(attotime::zero, 0, attotime::from_hz(4800));
33	33	}
34	34
35		static void electron_tape_stop( electron_state *state )
	35	void electron_state::electron_tape_stop()
36	36	{
37		state->m_ula.tape_running = 0;
38		state->m_tape_timer->reset(  );
	37	m_ula.tape_running = 0;
	38	m_tape_timer->reset();
39	39	}
40	40
41	41	#define TAPE_LOW   0x00;
r14963	r14964
114	114	}
115	115	}
116	116
117		static READ8_HANDLER( electron_read_keyboard )
	117	READ8_MEMBER(electron_state::electron_read_keyboard)
118	118	{
119	119	UINT8 data = 0;
120	120	int i;
r14963	r14964
127	127	for( i = 0; i < 14; i++ )
128	128	{
129	129	if( !(offset & 1) )
130		data |= input_port_read(space->machine(), keynames[i]) & 0x0f;
	130	data |= input_port_read(machine(), keynames[i]) & 0x0f;
131	131
132	132	offset = offset >> 1;
133	133	}
r14963	r14964
135	135	return data;
136	136	}
137	137
138		READ8_HANDLER( electron_jim_r )
	138	READ8_MEMBER(electron_state::electron_jim_r)
139	139	{
140	140	return 0xff;
141	141	}
142	142
143		WRITE8_HANDLER( electron_jim_w )
	143	WRITE8_MEMBER(electron_state::electron_jim_w)
144	144	{
145	145	}
146	146
147		READ8_HANDLER( electron_1mhz_r )
	147	READ8_MEMBER(electron_state::electron_1mhz_r)
148	148	{
149	149	return 0xff;
150	150	}
151	151
152		WRITE8_HANDLER( electron_1mhz_w )
	152	WRITE8_MEMBER(electron_state::electron_1mhz_w)
153	153	{
154	154	}
155	155
156		READ8_HANDLER( electron_ula_r )
	156	READ8_MEMBER(electron_state::electron_ula_r)
157	157	{
158		electron_state *state = space->machine().driver_data<electron_state>();
159		UINT8 data = ((UINT8 *)space->machine().region("user1")->base())[0x43E00 + offset];
	158	UINT8 data = ((UINT8 *)machine().region("user1")->base())[0x43E00 + offset];
160	159	switch ( offset & 0x0f )
161	160	{
162	161	case 0x00:   /* Interrupt status */
163		data = state->m_ula.interrupt_status;
164		state->m_ula.interrupt_status &= ~0x02;
	162	data = m_ula.interrupt_status;
	163	m_ula.interrupt_status &= ~0x02;
165	164	break;
166	165	case 0x01:   /* Unknown */
167	166	break;
168	167	case 0x04:   /* Casette data shift register */
169		electron_interrupt_handler(space->machine(), INT_CLEAR, INT_RECEIVE_FULL );
170		data = state->m_ula.tape_byte;
	168	electron_interrupt_handler(machine(), INT_CLEAR, INT_RECEIVE_FULL );
	169	data = m_ula.tape_byte;
171	170	break;
172	171	}
173	172	logerror( "ULA: read offset %02x: %02x\n", offset, data );
r14963	r14964
177	176	static const int electron_palette_offset[4] = { 0, 4, 5, 1 };
178	177	static const UINT16 electron_screen_base[8] = { 0x3000, 0x3000, 0x3000, 0x4000, 0x5800, 0x5800, 0x6000, 0x5800 };
179	178
180		WRITE8_HANDLER( electron_ula_w )
	179	WRITE8_MEMBER(electron_state::electron_ula_w)
181	180	{
182		electron_state *state = space->machine().driver_data<electron_state>();
183		device_t *speaker = space->machine().device(BEEPER_TAG);
	181	device_t *speaker = machine().device(BEEPER_TAG);
184	182	int i = electron_palette_offset[(( offset >> 1 ) & 0x03)];
185	183	logerror( "ULA: write offset %02x <- %02x\n", offset & 0x0f, data );
186	184	switch( offset & 0x0f )
187	185	{
188	186	case 0x00:   /* Interrupt control */
189		state->m_ula.interrupt_control = data;
	187	m_ula.interrupt_control = data;
190	188	break;
191	189	case 0x01:   /* Unknown */
192	190	break;
193	191	case 0x02:   /* Screen start address #1 */
194		state->m_ula.screen_start = ( state->m_ula.screen_start & 0x7e00 ) | ( ( data & 0xe0 ) << 1 );
195		logerror( "screen_start changed to %04x\n", state->m_ula.screen_start );
	192	m_ula.screen_start = ( m_ula.screen_start & 0x7e00 ) | ( ( data & 0xe0 ) << 1 );
	193	logerror( "screen_start changed to %04x\n", m_ula.screen_start );
196	194	break;
197	195	case 0x03:   /* Screen start addres #2 */
198		state->m_ula.screen_start = ( state->m_ula.screen_start & 0x1c0 ) | ( ( data & 0x3f ) << 9 );
199		logerror( "screen_start changed to %04x\n", state->m_ula.screen_start );
	196	m_ula.screen_start = ( m_ula.screen_start & 0x1c0 ) | ( ( data & 0x3f ) << 9 );
	197	logerror( "screen_start changed to %04x\n", m_ula.screen_start );
200	198	break;
201	199	case 0x04:   /* Cassette data shift register */
202	200	break;
r14963	r14964
207	205	* Rompages 10 and 11 both select the Basic ROM.
208	206	* Rompages 8 and 9 both select the keyboard.
209	207	*/
210		if ( ( ( state->m_ula.rompage & 0x0C ) != 0x08 ) || ( data & 0x08 ) )
	208	if ( ( ( m_ula.rompage & 0x0C ) != 0x08 ) || ( data & 0x08 ) )
211	209	{
212		state->m_ula.rompage = data & 0x0f;
213		if ( state->m_ula.rompage == 8 || state->m_ula.rompage == 9 )
	210	m_ula.rompage = data & 0x0f;
	211	if ( m_ula.rompage == 8 || m_ula.rompage == 9 )
214	212	{
215		state->m_ula.rompage = 8;
216		space->install_legacy_read_handler( 0x8000, 0xbfff, FUNC(electron_read_keyboard) );
	213	m_ula.rompage = 8;
	214	space.install_read_handler( 0x8000, 0xbfff, read8_delegate(FUNC(electron_state::electron_read_keyboard),this));
217	215	}
218	216	else
219	217	{
220		space->install_read_bank( 0x8000, 0xbfff, "bank2");
	218	space.install_read_bank( 0x8000, 0xbfff, "bank2");
221	219	}
222		memory_set_bank(space->machine(), "bank2", state->m_ula.rompage);
	220	memory_set_bank(machine(), "bank2", m_ula.rompage);
223	221	}
224	222	if ( data & 0x10 )
225	223	{
226		electron_interrupt_handler( space->machine(), INT_CLEAR, INT_DISPLAY_END );
	224	electron_interrupt_handler( machine(), INT_CLEAR, INT_DISPLAY_END );
227	225	}
228	226	if ( data & 0x20 )
229	227	{
230		electron_interrupt_handler( space->machine(), INT_CLEAR, INT_RTC );
	228	electron_interrupt_handler( machine(), INT_CLEAR, INT_RTC );
231	229	}
232	230	if ( data & 0x40 )
233	231	{
234		electron_interrupt_handler( space->machine(), INT_CLEAR, INT_HIGH_TONE );
	232	electron_interrupt_handler( machine(), INT_CLEAR, INT_HIGH_TONE );
235	233	}
236	234	if ( data & 0x80 )
237	235	{
238	236	}
239	237	break;
240	238	case 0x06:   /* Counter divider */
241		if ( state->m_ula.communication_mode == 0x01)
	239	if ( m_ula.communication_mode == 0x01)
242	240	{
243	241	beep_set_frequency( speaker, 1000000 / ( 16 * ( data + 1 ) ) );
244	242	}
245	243	break;
246	244	case 0x07:   /* Misc. */
247		state->m_ula.communication_mode = ( data >> 1 ) & 0x03;
248		switch( state->m_ula.communication_mode )
	245	m_ula.communication_mode = ( data >> 1 ) & 0x03;
	246	switch( m_ula.communication_mode )
249	247	{
250	248	case 0x00:   /* cassette input */
251	249	beep_set_state( speaker, 0 );
252		electron_tape_start(state);
	250	electron_tape_start();
253	251	break;
254	252	case 0x01:   /* sound generation */
255	253	beep_set_state( speaker, 1 );
256		electron_tape_stop(state);
	254	electron_tape_stop();
257	255	break;
258	256	case 0x02:   /* cassette output */
259	257	beep_set_state( speaker, 0 );
260		electron_tape_stop(state);
	258	electron_tape_stop();
261	259	break;
262	260	case 0x03:   /* not used */
263	261	beep_set_state( speaker, 0 );
264		electron_tape_stop(state);
	262	electron_tape_stop();
265	263	break;
266	264	}
267		state->m_ula.screen_mode = ( data >> 3 ) & 0x07;
268		state->m_ula.screen_base = electron_screen_base[ state->m_ula.screen_mode ];
269		state->m_ula.screen_size = 0x8000 - state->m_ula.screen_base;
270		state->m_ula.vram = (UINT8 *)space->get_read_ptr(state->m_ula.screen_base );
271		logerror( "ULA: screen mode set to %d\n", state->m_ula.screen_mode );
272		state->m_ula.cassette_motor_mode = ( data >> 6 ) & 0x01;
273		cassette_device_image(space->machine())->change_state(state->m_ula.cassette_motor_mode ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED, CASSETTE_MOTOR_DISABLED );
274		state->m_ula.capslock_mode = ( data >> 7 ) & 0x01;
	265	m_ula.screen_mode = ( data >> 3 ) & 0x07;
	266	m_ula.screen_base = electron_screen_base[ m_ula.screen_mode ];
	267	m_ula.screen_size = 0x8000 - m_ula.screen_base;
	268	m_ula.vram = (UINT8 *)space.get_read_ptr(m_ula.screen_base );
	269	logerror( "ULA: screen mode set to %d\n", m_ula.screen_mode );
	270	m_ula.cassette_motor_mode = ( data >> 6 ) & 0x01;
	271	cassette_device_image(machine())->change_state(m_ula.cassette_motor_mode ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED, CASSETTE_MOTOR_DISABLED );
	272	m_ula.capslock_mode = ( data >> 7 ) & 0x01;
275	273	break;
276	274	case 0x08: case 0x0A: case 0x0C: case 0x0E:
277	275	// video_update
278		state->m_ula.current_pal[i+10] = (state->m_ula.current_pal[i+10] & 0x01) | (((data & 0x80) >> 5) | ((data & 0x08) >> 1));
279		state->m_ula.current_pal[i+8] = (state->m_ula.current_pal[i+8] & 0x01) | (((data & 0x40) >> 4) | ((data & 0x04) >> 1));
280		state->m_ula.current_pal[i+2] = (state->m_ula.current_pal[i+2] & 0x03) | ((data & 0x20) >> 3);
281		state->m_ula.current_pal[i] = (state->m_ula.current_pal[i] & 0x03) | ((data & 0x10) >> 2);
	276	m_ula.current_pal[i+10] = (m_ula.current_pal[i+10] & 0x01) | (((data & 0x80) >> 5) | ((data & 0x08) >> 1));
	277	m_ula.current_pal[i+8] = (m_ula.current_pal[i+8] & 0x01) | (((data & 0x40) >> 4) | ((data & 0x04) >> 1));
	278	m_ula.current_pal[i+2] = (m_ula.current_pal[i+2] & 0x03) | ((data & 0x20) >> 3);
	279	m_ula.current_pal[i] = (m_ula.current_pal[i] & 0x03) | ((data & 0x10) >> 2);
282	280	break;
283	281	case 0x09: case 0x0B: case 0x0D: case 0x0F:
284	282	// video_update
285		state->m_ula.current_pal[i+10] = (state->m_ula.current_pal[i+10] & 0x06) | ((data & 0x08) >> 3);
286		state->m_ula.current_pal[i+8] = (state->m_ula.current_pal[i+8] & 0x06) | ((data & 0x04) >> 2);
287		state->m_ula.current_pal[i+2] = (state->m_ula.current_pal[i+2] & 0x04) | (((data & 0x20) >> 4) | ((data & 0x02) >> 1));
288		state->m_ula.current_pal[i] = (state->m_ula.current_pal[i] & 0x04) | (((data & 0x10) >> 3) | ((data & 0x01)));
	283	m_ula.current_pal[i+10] = (m_ula.current_pal[i+10] & 0x06) | ((data & 0x08) >> 3);
	284	m_ula.current_pal[i+8] = (m_ula.current_pal[i+8] & 0x06) | ((data & 0x04) >> 2);
	285	m_ula.current_pal[i+2] = (m_ula.current_pal[i+2] & 0x04) | (((data & 0x20) >> 4) | ((data & 0x02) >> 1));
	286	m_ula.current_pal[i] = (m_ula.current_pal[i] & 0x04) | (((data & 0x10) >> 3) | ((data & 0x01)));
289	287	break;
290	288	}
291	289	}

src/mess/machine/irisha.c

r14963	r14964
66	66	return 0;
67	67	}
68	68
69		READ8_HANDLER (irisha_keyboard_r)
	69	READ8_MEMBER(irisha_state::irisha_keyboard_r)
70	70	{
71		irisha_state *state = space->machine().driver_data<irisha_state>();
72	71	UINT8 keycode;
73		if (state->m_keyboard_cnt!=0 && state->m_keyboard_cnt<11) {
74		keycode = input_port_read(space->machine(), keynames[state->m_keyboard_cnt-1]) ^ 0xff;
	72	if (m_keyboard_cnt!=0 && m_keyboard_cnt<11) {
	73	keycode = input_port_read(machine(), keynames[m_keyboard_cnt-1]) ^ 0xff;
75	74	} else {
76	75	keycode = 0xff;
77	76	}
78		state->m_keyboard_cnt++;
	77	m_keyboard_cnt++;
79	78	return keycode;
80	79	}
81	80

src/mess/machine/orion.c

r14963	r14964
63	63	state->m_video_mode_mask = 7;
64	64	}
65	65
66		READ8_HANDLER ( orion128_system_r )
	66	READ8_MEMBER(orion_state::orion128_system_r)
67	67	{
68		return space->machine().device<i8255_device>("ppi8255_2")->read(*space, offset & 3);
	68	return machine().device<i8255_device>("ppi8255_2")->read(space, offset & 3);
69	69	}
70	70
71		WRITE8_HANDLER ( orion128_system_w )
	71	WRITE8_MEMBER(orion_state::orion128_system_w)
72	72	{
73		space->machine().device<i8255_device>("ppi8255_2")->write(*space, offset & 3, data);
	73	machine().device<i8255_device>("ppi8255_2")->write(space, offset & 3, data);
74	74	}
75	75
76		READ8_HANDLER ( orion128_romdisk_r )
	76	READ8_MEMBER(orion_state::orion128_romdisk_r)
77	77	{
78		return space->machine().device<i8255_device>("ppi8255_1")->read(*space, offset & 3);
	78	return machine().device<i8255_device>("ppi8255_1")->read(space, offset & 3);
79	79	}
80	80
81		WRITE8_HANDLER ( orion128_romdisk_w )
	81	WRITE8_MEMBER(orion_state::orion128_romdisk_w)
82	82	{
83		space->machine().device<i8255_device>("ppi8255_1")->write(*space, offset & 3, data);
	83	machine().device<i8255_device>("ppi8255_1")->write(space, offset & 3, data);
84	84	}
85	85
86	86	static void orion_set_video_mode(running_machine &machine, int width)
r14963	r14964
89	89	machine.primary_screen->configure(width, 256, visarea, machine.primary_screen->frame_period().attoseconds);
90	90	}
91	91
92		WRITE8_HANDLER ( orion128_video_mode_w )
	92	WRITE8_MEMBER(orion_state::orion128_video_mode_w)
93	93	{
94		orion_state *state = space->machine().driver_data<orion_state>();
95		if ((data & 0x80)!=(state->m_orion128_video_mode & 0x80))
	94	if ((data & 0x80)!=(m_orion128_video_mode & 0x80))
96	95	{
97	96	if ((data & 0x80)==0x80)
98	97	{
99		if (state->m_video_mode_mask == 31)
	98	if (m_video_mode_mask == 31)
100	99	{
101		state->m_orion128_video_width = SCREEN_WIDTH_512;
102		orion_set_video_mode(space->machine(),512);
	100	m_orion128_video_width = SCREEN_WIDTH_512;
	101	orion_set_video_mode(machine(),512);
103	102	}
104	103	else
105	104	{
106		state->m_orion128_video_width = SCREEN_WIDTH_480;
107		orion_set_video_mode(space->machine(),480);
	105	m_orion128_video_width = SCREEN_WIDTH_480;
	106	orion_set_video_mode(machine(),480);
108	107	}
109	108	}
110	109	else
111	110	{
112		state->m_orion128_video_width = SCREEN_WIDTH_384;
113		orion_set_video_mode(space->machine(),384);
	111	m_orion128_video_width = SCREEN_WIDTH_384;
	112	orion_set_video_mode(machine(),384);
114	113	}
115	114	}
116	115
117		state->m_orion128_video_mode = data;
	116	m_orion128_video_mode = data;
118	117	}
119	118
120		WRITE8_HANDLER ( orion128_video_page_w )
	119	WRITE8_MEMBER(orion_state::orion128_video_page_w)
121	120	{
122		orion_state *state = space->machine().driver_data<orion_state>();
123		if (state->m_orion128_video_page != data)
	121	if (m_orion128_video_page != data)
124	122	{
125		if ((data & 0x80)!=(state->m_orion128_video_page & 0x80))
	123	if ((data & 0x80)!=(m_orion128_video_page & 0x80))
126	124	{
127	125	if ((data & 0x80)==0x80)
128	126	{
129		if (state->m_video_mode_mask == 31)
	127	if (m_video_mode_mask == 31)
130	128	{
131		state->m_orion128_video_width = SCREEN_WIDTH_512;
132		orion_set_video_mode(space->machine(),512);
	129	m_orion128_video_width = SCREEN_WIDTH_512;
	130	orion_set_video_mode(machine(),512);
133	131	}
134	132	else
135	133	{
136		state->m_orion128_video_width = SCREEN_WIDTH_480;
137		orion_set_video_mode(space->machine(),480);
	134	m_orion128_video_width = SCREEN_WIDTH_480;
	135	orion_set_video_mode(machine(),480);
138	136	}
139	137	}
140	138	else
141	139	{
142		state->m_orion128_video_width = SCREEN_WIDTH_384;
143		orion_set_video_mode(space->machine(),384);
	140	m_orion128_video_width = SCREEN_WIDTH_384;
	141	orion_set_video_mode(machine(),384);
144	142	}
145	143	}
146	144	}
147		state->m_orion128_video_page = data;
	145	m_orion128_video_page = data;
148	146	}
149	147
150	148
151		WRITE8_HANDLER ( orion128_memory_page_w )
	149	WRITE8_MEMBER(orion_state::orion128_memory_page_w)
152	150	{
153		orion_state *state = space->machine().driver_data<orion_state>();
154		if (data!=state->m_orion128_memory_page )
	151	if (data!=m_orion128_memory_page )
155	152	{
156		memory_set_bankptr(space->machine(), "bank1", space->machine().device<ram_device>(RAM_TAG)->pointer() + (data & 3) * 0x10000);
157		state->m_orion128_memory_page = (data & 3);
	153	memory_set_bankptr(machine(), "bank1", machine().device<ram_device>(RAM_TAG)->pointer() + (data & 3) * 0x10000);
	154	m_orion128_memory_page = (data & 3);
158	155	}
159	156	}
160	157
r14963	r14964
171	168	radio86_init_keyboard(machine);
172	169	}
173	170
174		static WRITE8_HANDLER ( orion_disk_control_w )
	171	WRITE8_MEMBER(orion_state::orion_disk_control_w)
175	172	{
176		device_t *fdc = space->machine().device("wd1793");
	173	device_t *fdc = machine().device("wd1793");
177	174
178	175	wd17xx_set_side(fdc,((data & 0x10) >> 4) ^ 1);
179	176	wd17xx_set_drive(fdc,data & 3);
180	177	}
181	178
182		READ8_HANDLER ( orion128_floppy_r )
	179	READ8_MEMBER(orion_state::orion128_floppy_r)
183	180	{
184		device_t *fdc = space->machine().device("wd1793");
	181	device_t *fdc = machine().device("wd1793");
185	182
186	183	switch(offset)
187	184	{
r14963	r14964
197	194	return 0xff;
198	195	}
199	196
200		WRITE8_HANDLER ( orion128_floppy_w )
	197	WRITE8_MEMBER(orion_state::orion128_floppy_w)
201	198	{
202		device_t *fdc = space->machine().device("wd1793");
	199	device_t *fdc = machine().device("wd1793");
203	200
204	201	switch(offset)
205	202	{
r14963	r14964
216	213	case 0x20 : orion_disk_control_w(space, offset, data);break;
217	214	}
218	215	}
219		static READ8_HANDLER ( orionz80_floppy_rtc_r )
	216	READ8_MEMBER(orion_state::orionz80_floppy_rtc_r)
220	217	{
221	218	if ((offset >= 0x60) && (offset <= 0x6f))
222	219	{
223		return space->machine().device<mc146818_device>("rtc")->read(*space,offset-0x60);
	220	return machine().device<mc146818_device>("rtc")->read(space,offset-0x60);
224	221	}
225	222	else
226	223	{
r14963	r14964
228	225	}
229	226	}
230	227
231		static WRITE8_HANDLER ( orionz80_floppy_rtc_w )
	228	WRITE8_MEMBER(orion_state::orionz80_floppy_rtc_w)
232	229	{
233	230	if ((offset >= 0x60) && (offset <= 0x6f))
234	231	{
235		space->machine().device<mc146818_device>("rtc")->write(*space,offset-0x60,data);
	232	machine().device<mc146818_device>("rtc")->write(space,offset-0x60,data);
236	233	}
237	234	else
238	235	{
r14963	r14964
247	244	state->m_video_mode_mask = 7;
248	245	}
249	246
250		WRITE8_HANDLER ( orionz80_sound_w )
	247	WRITE8_MEMBER(orion_state::orionz80_sound_w)
251	248	{
252		orion_state *state = space->machine().driver_data<orion_state>();
253		device_t *speaker = space->machine().device(SPEAKER_TAG);
254		if (state->m_speaker == 0)
	249	device_t *speaker = machine().device(SPEAKER_TAG);
	250	if (m_speaker == 0)
255	251	{
256		state->m_speaker = data;
	252	m_speaker = data;
257	253	}
258	254	else
259	255	{
260		state->m_speaker = 0 ;
	256	m_speaker = 0 ;
261	257	}
262		speaker_level_w(speaker,state->m_speaker);
	258	speaker_level_w(speaker,m_speaker);
263	259
264	260	}
265	261
266		static WRITE8_HANDLER ( orionz80_sound_fe_w )
	262	WRITE8_MEMBER(orion_state::orionz80_sound_fe_w)
267	263	{
268		device_t *speaker = space->machine().device(SPEAKER_TAG);
	264	device_t *speaker = machine().device(SPEAKER_TAG);
269	265	speaker_level_w(speaker,(data>>4) & 0x01);
270	266	}
271	267
r14963	r14964
294	290
295	291	if ((state->m_orionz80_dispatcher & 0x20) == 0)
296	292	{
297		space->install_legacy_write_handler(0xf400, 0xf4ff, FUNC(orion128_system_w));
298		space->install_legacy_write_handler(0xf500, 0xf5ff, FUNC(orion128_romdisk_w));
299		space->install_legacy_write_handler(0xf700, 0xf7ff, FUNC(orionz80_floppy_rtc_w));
300		space->install_legacy_read_handler(0xf400, 0xf4ff, FUNC(orion128_system_r));
301		space->install_legacy_read_handler(0xf500, 0xf5ff, FUNC(orion128_romdisk_r));
302		space->install_legacy_read_handler(0xf700, 0xf7ff, FUNC(orionz80_floppy_rtc_r));
	293	space->install_write_handler(0xf400, 0xf4ff, write8_delegate(FUNC(orion_state::orion128_system_w),state));
	294	space->install_write_handler(0xf500, 0xf5ff, write8_delegate(FUNC(orion_state::orion128_romdisk_w),state));
	295	space->install_write_handler(0xf700, 0xf7ff, write8_delegate(FUNC(orion_state::orionz80_floppy_rtc_w),state));
	296	space->install_read_handler(0xf400, 0xf4ff, read8_delegate(FUNC(orion_state::orion128_system_r),state));
	297	space->install_read_handler(0xf500, 0xf5ff, read8_delegate(FUNC(orion_state::orion128_romdisk_r),state));
	298	space->install_read_handler(0xf700, 0xf7ff, read8_delegate(FUNC(orion_state::orionz80_floppy_rtc_r),state));
303	299
304		space->install_legacy_write_handler(0xf800, 0xf8ff, FUNC(orion128_video_mode_w));
305		space->install_legacy_write_handler(0xf900, 0xf9ff, FUNC(orionz80_memory_page_w));
306		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(orion128_video_page_w));
307		space->install_legacy_write_handler(0xfb00, 0xfbff, FUNC(orionz80_dispatcher_w));
	300	space->install_write_handler(0xf800, 0xf8ff, write8_delegate(FUNC(orion_state::orion128_video_mode_w),state));
	301	space->install_write_handler(0xf900, 0xf9ff, write8_delegate(FUNC(orion_state::orionz80_memory_page_w),state));
	302	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(orion_state::orion128_video_page_w),state));
	303	space->install_write_handler(0xfb00, 0xfbff, write8_delegate(FUNC(orion_state::orionz80_dispatcher_w),state));
308	304	space->unmap_write(0xfc00, 0xfeff);
309		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(orionz80_sound_w));
	305	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(orion_state::orionz80_sound_w),state));
310	306
311	307	memory_set_bankptr(machine, "bank3", machine.device<ram_device>(RAM_TAG)->pointer() + 0xf000);
312	308	memory_set_bankptr(machine, "bank5", machine.region("maincpu")->base() + 0xf800);
r14963	r14964
321	317	}
322	318	}
323	319
324		WRITE8_HANDLER ( orionz80_memory_page_w )
	320	WRITE8_MEMBER(orion_state::orionz80_memory_page_w)
325	321	{
326		orion_state *state = space->machine().driver_data<orion_state>();
327		state->m_orionz80_memory_page = data & 7;
328		orionz80_switch_bank(space->machine());
	322	m_orionz80_memory_page = data & 7;
	323	orionz80_switch_bank(machine());
329	324	}
330	325
331		WRITE8_HANDLER ( orionz80_dispatcher_w )
	326	WRITE8_MEMBER(orion_state::orionz80_dispatcher_w)
332	327	{
333		orion_state *state = space->machine().driver_data<orion_state>();
334		state->m_orionz80_dispatcher = data;
335		orionz80_switch_bank(space->machine());
	328	m_orionz80_dispatcher = data;
	329	orionz80_switch_bank(machine());
336	330	}
337	331
338	332	MACHINE_RESET ( orionz80 )
r14963	r14964
344	338	space->install_write_bank(0x4000, 0xefff, "bank2");
345	339	space->install_write_bank(0xf000, 0xf3ff, "bank3");
346	340
347		space->install_legacy_write_handler(0xf400, 0xf4ff, FUNC(orion128_system_w));
348		space->install_legacy_write_handler(0xf500, 0xf5ff, FUNC(orion128_romdisk_w));
349		space->install_legacy_write_handler(0xf700, 0xf7ff, FUNC(orionz80_floppy_rtc_w));
350		space->install_legacy_read_handler(0xf400, 0xf4ff, FUNC(orion128_system_r));
351		space->install_legacy_read_handler(0xf500, 0xf5ff, FUNC(orion128_romdisk_r));
352		space->install_legacy_read_handler(0xf700, 0xf7ff, FUNC(orionz80_floppy_rtc_r));
	341	space->install_write_handler(0xf400, 0xf4ff, write8_delegate(FUNC(orion_state::orion128_system_w),state));
	342	space->install_write_handler(0xf500, 0xf5ff, write8_delegate(FUNC(orion_state::orion128_romdisk_w),state));
	343	space->install_write_handler(0xf700, 0xf7ff, write8_delegate(FUNC(orion_state::orionz80_floppy_rtc_w),state));
	344	space->install_read_handler(0xf400, 0xf4ff, read8_delegate(FUNC(orion_state::orion128_system_r),state));
	345	space->install_read_handler(0xf500, 0xf5ff, read8_delegate(FUNC(orion_state::orion128_romdisk_r),state));
	346	space->install_read_handler(0xf700, 0xf7ff, read8_delegate(FUNC(orion_state::orionz80_floppy_rtc_r),state));
353	347
354		space->install_legacy_write_handler(0xf800, 0xf8ff, FUNC(orion128_video_mode_w));
355		space->install_legacy_write_handler(0xf900, 0xf9ff, FUNC(orionz80_memory_page_w));
356		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(orion128_video_page_w));
357		space->install_legacy_write_handler(0xfb00, 0xfbff, FUNC(orionz80_dispatcher_w));
	348	space->install_write_handler(0xf800, 0xf8ff, write8_delegate(FUNC(orion_state::orion128_video_mode_w),state));
	349	space->install_write_handler(0xf900, 0xf9ff, write8_delegate(FUNC(orion_state::orionz80_memory_page_w),state));
	350	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(orion_state::orion128_video_page_w),state));
	351	space->install_write_handler(0xfb00, 0xfbff, write8_delegate(FUNC(orion_state::orionz80_dispatcher_w),state));
358	352	space->unmap_write(0xfc00, 0xfeff);
359		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(orionz80_sound_w));
	353	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(orion_state::orionz80_sound_w),state));
360	354
361	355
362	356	memory_set_bankptr(machine, "bank1", machine.region("maincpu")->base() + 0xf800);
r14963	r14964
384	378	}
385	379	}
386	380
387		READ8_HANDLER ( orionz80_io_r )
	381	READ8_MEMBER(orion_state::orionz80_io_r)
388	382	{
389	383	if (offset == 0xFFFD)
390	384	{
391		return ay8910_r (space->machine().device("ay8912"), 0);
	385	return ay8910_r (machine().device("ay8912"), 0);
392	386	}
393	387	return 0xff;
394	388	}
395	389
396		WRITE8_HANDLER ( orionz80_io_w )
	390	WRITE8_MEMBER(orion_state::orionz80_io_w)
397	391	{
398	392	switch (offset & 0xff)
399	393	{
r14963	r14964
406	400	}
407	401	switch(offset)
408	402	{
409		case 0xfffd : ay8910_address_w(space->machine().device("ay8912"), 0, data);
	403	case 0xfffd : ay8910_address_w(machine().device("ay8912"), 0, data);
410	404	break;
411	405	case 0xbffd :
412		case 0xbefd : ay8910_data_w(space->machine().device("ay8912"), 0, data);
	406	case 0xbefd : ay8910_data_w(machine().device("ay8912"), 0, data);
413	407	break;
414	408	}
415	409	}
r14963	r14964
418	412
419	413
420	414
421		static WRITE8_HANDLER ( orionpro_memory_page_w );
422	415
	416
423	417	static void orionpro_bank_switch(running_machine &machine)
424	418	{
425	419	orion_state *state = machine.driver_data<orion_state>();
r14963	r14964
487	481	{
488	482	memory_set_bankptr(machine, "bank6", ram + 0x10000 * 0 + 0xf000);
489	483
490		space->install_legacy_write_handler(0xf400, 0xf4ff, FUNC(orion128_system_w));
491		space->install_legacy_write_handler(0xf500, 0xf5ff, FUNC(orion128_romdisk_w));
	484	space->install_write_handler(0xf400, 0xf4ff, write8_delegate(FUNC(orion_state::orion128_system_w),state));
	485	space->install_write_handler(0xf500, 0xf5ff, write8_delegate(FUNC(orion_state::orion128_romdisk_w),state));
492	486	space->unmap_write(0xf600, 0xf6ff);
493		space->install_legacy_write_handler(0xf700, 0xf7ff, FUNC(orion128_floppy_w));
494		space->install_legacy_read_handler(0xf400, 0xf4ff, FUNC(orion128_system_r));
495		space->install_legacy_read_handler(0xf500, 0xf5ff, FUNC(orion128_romdisk_r));
	487	space->install_write_handler(0xf700, 0xf7ff, write8_delegate(FUNC(orion_state::orion128_floppy_w),state));
	488	space->install_read_handler(0xf400, 0xf4ff, read8_delegate(FUNC(orion_state::orion128_system_r),state));
	489	space->install_read_handler(0xf500, 0xf5ff, read8_delegate(FUNC(orion_state::orion128_romdisk_r),state));
496	490	space->unmap_read(0xf600, 0xf6ff);
497		space->install_legacy_read_handler(0xf700, 0xf7ff, FUNC(orion128_floppy_r));
	491	space->install_read_handler(0xf700, 0xf7ff, read8_delegate(FUNC(orion_state::orion128_floppy_r),state));
498	492
499		space->install_legacy_write_handler(0xf800, 0xf8ff, FUNC(orion128_video_mode_w));
500		space->install_legacy_write_handler(0xf900, 0xf9ff, FUNC(orionpro_memory_page_w));
501		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(orion128_video_page_w));
	493	space->install_write_handler(0xf800, 0xf8ff, write8_delegate(FUNC(orion_state::orion128_video_mode_w),state));
	494	space->install_write_handler(0xf900, 0xf9ff, write8_delegate(FUNC(orion_state::orionpro_memory_page_w),state));
	495	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(orion_state::orion128_video_page_w),state));
502	496	space->unmap_write(0xfb00, 0xfeff);
503		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(orionz80_sound_w));
	497	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(orion_state::orionz80_sound_w),state));
504	498
505	499
506	500	memory_set_bankptr(machine, "bank8", ram + 0x10000 * 0 + 0xf800);
r14963	r14964
522	516	}
523	517	}
524	518
525		static WRITE8_HANDLER ( orionpro_memory_page_w )
	519	WRITE8_MEMBER(orion_state::orionpro_memory_page_w)
526	520	{
527		orion_state *state = space->machine().driver_data<orion_state>();
528		state->m_orionpro_128_page = data;
529		orionpro_bank_switch(space->machine());
	521	m_orionpro_128_page = data;
	522	orionpro_bank_switch(machine());
530	523	}
531	524
532	525	MACHINE_RESET ( orionpro )
r14963	r14964
555	548	state->m_orionpro_pseudo_color = 0;
556	549	}
557	550
558		READ8_HANDLER ( orionpro_io_r )
	551	READ8_MEMBER(orion_state::orionpro_io_r)
559	552	{
560		orion_state *state = space->machine().driver_data<orion_state>();
561		device_t *fdc = space->machine().device("wd1793");
	553	device_t *fdc = machine().device("wd1793");
562	554
563	555	switch (offset & 0xff)
564	556	{
565	557	case 0x00 : return 0x56;
566		case 0x04 : return state->m_orionpro_ram0_segment;
567		case 0x05 : return state->m_orionpro_ram1_segment;
568		case 0x06 : return state->m_orionpro_ram2_segment;
569		case 0x08 : return state->m_orionpro_page;
570		case 0x09 : return state->m_orionpro_rom2_segment;
571		case 0x0a : return state->m_orionpro_dispatcher;
	558	case 0x04 : return m_orionpro_ram0_segment;
	559	case 0x05 : return m_orionpro_ram1_segment;
	560	case 0x06 : return m_orionpro_ram2_segment;
	561	case 0x08 : return m_orionpro_page;
	562	case 0x09 : return m_orionpro_rom2_segment;
	563	case 0x0a : return m_orionpro_dispatcher;
572	564	case 0x10 : return wd17xx_status_r(fdc,0);
573	565	case 0x11 : return wd17xx_track_r(fdc,0);
574	566	case 0x12 : return wd17xx_sector_r(fdc,0);
r14963	r14964
585	577	}
586	578	if (offset == 0xFFFD)
587	579	{
588		return ay8910_r (space->machine().device("ay8912"), 0);
	580	return ay8910_r (machine().device("ay8912"), 0);
589	581	}
590	582	return 0xff;
591	583	}
592	584
593		WRITE8_HANDLER ( orionpro_io_w )
	585	WRITE8_MEMBER(orion_state::orionpro_io_w)
594	586	{
595		orion_state *state = space->machine().driver_data<orion_state>();
596		device_t *fdc = space->machine().device("wd1793");
	587	device_t *fdc = machine().device("wd1793");
597	588
598	589	switch (offset & 0xff)
599	590	{
600		case 0x04 : state->m_orionpro_ram0_segment = data; orionpro_bank_switch(space->machine()); break;
601		case 0x05 : state->m_orionpro_ram1_segment = data; orionpro_bank_switch(space->machine()); break;
602		case 0x06 : state->m_orionpro_ram2_segment = data; orionpro_bank_switch(space->machine()); break;
603		case 0x08 : state->m_orionpro_page = data;        orionpro_bank_switch(space->machine()); break;
604		case 0x09 : state->m_orionpro_rom2_segment = data; orionpro_bank_switch(space->machine()); break;
605		case 0x0a : state->m_orionpro_dispatcher = data;   orionpro_bank_switch(space->machine()); break;
	591	case 0x04 : m_orionpro_ram0_segment = data; orionpro_bank_switch(machine()); break;
	592	case 0x05 : m_orionpro_ram1_segment = data; orionpro_bank_switch(machine()); break;
	593	case 0x06 : m_orionpro_ram2_segment = data; orionpro_bank_switch(machine()); break;
	594	case 0x08 : m_orionpro_page = data;        orionpro_bank_switch(machine()); break;
	595	case 0x09 : m_orionpro_rom2_segment = data; orionpro_bank_switch(machine()); break;
	596	case 0x0a : m_orionpro_dispatcher = data;   orionpro_bank_switch(machine()); break;
606	597	case 0x10 : wd17xx_command_w(fdc,0,data); break;
607	598	case 0x11 : wd17xx_track_w(fdc,0,data);break;
608	599	case 0x12 : wd17xx_sector_w(fdc,0,data);break;
r14963	r14964
618	609	case 0x2a : orion128_romdisk_w(space,2,data); break;
619	610	case 0x2b : orion128_romdisk_w(space,3,data); break;
620	611	case 0xf8 : orion128_video_mode_w(space,0,data);break;
621		case 0xf9 : state->m_orionpro_128_page = data;     orionpro_bank_switch(space->machine()); break;
	612	case 0xf9 : m_orionpro_128_page = data;     orionpro_bank_switch(machine()); break;
622	613	case 0xfa : orion128_video_page_w(space,0,data);break;
623		case 0xfc : state->m_orionpro_pseudo_color = data;break;
	614	case 0xfc : m_orionpro_pseudo_color = data;break;
624	615	case 0xfe : orionz80_sound_fe_w(space,0,data);break;
625	616	case 0xff : orionz80_sound_w(space,0,data);break;
626	617	}
627	618	switch(offset)
628	619	{
629		case 0xfffd : ay8910_address_w(space->machine().device("ay8912"), 0, data);
	620	case 0xfffd : ay8910_address_w(machine().device("ay8912"), 0, data);
630	621	break;
631	622	case 0xbffd :
632		case 0xbefd : ay8910_data_w(space->machine().device("ay8912"), 0, data);
	623	case 0xbefd : ay8910_data_w(machine().device("ay8912"), 0, data);
633	624	break;
634	625	}
635	626	}

src/mess/machine/a7800.c

r14963	r14964
393	393	}
394	394
395	395
396		WRITE8_HANDLER( a7800_RAM0_w )
	396	WRITE8_MEMBER(a7800_state::a7800_RAM0_w)
397	397	{
398		a7800_state *state = space->machine().driver_data<a7800_state>();
399		state->m_ROM[0x2040 + offset] = data;
400		state->m_ROM[0x40 + offset] = data;
	398	m_ROM[0x2040 + offset] = data;
	399	m_ROM[0x40 + offset] = data;
401	400	}
402	401
403	402
404		WRITE8_HANDLER( a7800_cart_w )
	403	WRITE8_MEMBER(a7800_state::a7800_cart_w)
405	404	{
406		a7800_state *state = space->machine().driver_data<a7800_state>();
407		UINT8 *memory = space->machine().region("maincpu")->base();
	405	UINT8 *memory = machine().region("maincpu")->base();
408	406
409	407	if(offset < 0x4000)
410	408	{
411		if(state->m_cart_type & 0x04)
	409	if(m_cart_type & 0x04)
412	410	{
413		state->m_ROM[0x4000 + offset] = data;
	411	m_ROM[0x4000 + offset] = data;
414	412	}
415		else if(state->m_cart_type & 0x01)
	413	else if(m_cart_type & 0x01)
416	414	{
417		device_t *pokey = space->machine().device("pokey");
	415	device_t *pokey = machine().device("pokey");
418	416	pokey_w(pokey, offset, data);
419	417	}
420	418	else
r14963	r14964
423	421	}
424	422	}
425	423
426		if(( state->m_cart_type & 0x02 ) &&( offset >= 0x4000 ) )
	424	if(( m_cart_type & 0x02 ) &&( offset >= 0x4000 ) )
427	425	{
428	426	/* fix for 64kb supercart */
429		if( state->m_cart_size == 0x10000 )
	427	if( m_cart_size == 0x10000 )
430	428	{
431	429	data &= 0x03;
432	430	}
r14963	r14964
434	432	{
435	433	data &= 0x07;
436	434	}
437		memory_set_bankptr(space->machine(), "bank2",memory + 0x10000 + (data << 14));
438		memory_set_bankptr(space->machine(), "bank3",memory + 0x12000 + (data << 14));
	435	memory_set_bankptr(machine(), "bank2",memory + 0x10000 + (data << 14));
	436	memory_set_bankptr(machine(), "bank3",memory + 0x12000 + (data << 14));
439	437	/*  logerror("BANK SEL: %d\n",data); */
440	438	}
441		else if(( state->m_cart_type == MBANK_TYPE_ABSOLUTE ) &&( offset == 0x4000 ) )
	439	else if(( m_cart_type == MBANK_TYPE_ABSOLUTE ) &&( offset == 0x4000 ) )
442	440	{
443	441	/* F18 Hornet */
444	442	/*logerror( "F18 BANK SEL: %d\n", data );*/
445	443	if( data & 1 )
446	444	{
447		memory_set_bankptr(space->machine(), "bank1",memory + 0x10000 );
	445	memory_set_bankptr(machine(), "bank1",memory + 0x10000 );
448	446	}
449	447	else if( data & 2 )
450	448	{
451		memory_set_bankptr(space->machine(), "bank1",memory + 0x14000 );
	449	memory_set_bankptr(machine(), "bank1",memory + 0x14000 );
452	450	}
453	451	}
454		else if(( state->m_cart_type == MBANK_TYPE_ACTIVISION ) &&( offset >= 0xBF80 ) )
	452	else if(( m_cart_type == MBANK_TYPE_ACTIVISION ) &&( offset >= 0xBF80 ) )
455	453	{
456	454	/* Activision */
457	455	data = offset & 7;
458	456
459	457	/*logerror( "Activision BANK SEL: %d\n", data );*/
460	458
461		memory_set_bankptr(space->machine(),  "bank3", memory + 0x10000 + ( data << 14 ) );
462		memory_set_bankptr(space->machine(),  "bank4", memory + 0x12000 + ( data << 14 ) );
	459	memory_set_bankptr(machine(),  "bank3", memory + 0x10000 + ( data << 14 ) );
	460	memory_set_bankptr(machine(),  "bank4", memory + 0x12000 + ( data << 14 ) );
463	461	}
464	462	}
465	463
r14963	r14964
468	466	TIA
469	467	***************************************************************************/
470	468
471		READ8_HANDLER( a7800_TIA_r )
	469	READ8_MEMBER(a7800_state::a7800_TIA_r)
472	470	{
473		a7800_state *state = space->machine().driver_data<a7800_state>();
474	471	switch(offset & 0x0f)
475	472	{
476	473	case 0x00:
r14963	r14964
485	482	still return a reasonable value */
486	483	return 0x00;
487	484	case 0x08:
488		return((input_port_read(space->machine(), "buttons") & 0x02) << 6);
	485	return((input_port_read(machine(), "buttons") & 0x02) << 6);
489	486	case 0x09:
490		return((input_port_read(space->machine(), "buttons") & 0x08) << 4);
	487	return((input_port_read(machine(), "buttons") & 0x08) << 4);
491	488	case 0x0A:
492		return((input_port_read(space->machine(), "buttons") & 0x01) << 7);
	489	return((input_port_read(machine(), "buttons") & 0x01) << 7);
493	490	case 0x0B:
494		return((input_port_read(space->machine(), "buttons") & 0x04) << 5);
	491	return((input_port_read(machine(), "buttons") & 0x04) << 5);
495	492	case 0x0c:
496		if(((input_port_read(space->machine(), "buttons") & 0x08) ||(input_port_read(space->machine(), "buttons") & 0x02)) && state->m_p1_one_button)
	493	if(((input_port_read(machine(), "buttons") & 0x08) ||(input_port_read(machine(), "buttons") & 0x02)) && m_p1_one_button)
497	494	return 0x00;
498	495	else
499	496	return 0x80;
500	497	case 0x0d:
501		if(((input_port_read(space->machine(), "buttons") & 0x01) ||(input_port_read(space->machine(), "buttons") & 0x04)) && state->m_p2_one_button)
	498	if(((input_port_read(machine(), "buttons") & 0x01) ||(input_port_read(machine(), "buttons") & 0x04)) && m_p2_one_button)
502	499	return 0x00;
503	500	else
504	501	return 0x80;
r14963	r14964
510	507	}
511	508
512	509
513		WRITE8_HANDLER( a7800_TIA_w )
	510	WRITE8_MEMBER(a7800_state::a7800_TIA_w)
514	511	{
515		a7800_state *state = space->machine().driver_data<a7800_state>();
516	512	switch(offset) {
517	513	case 0x01:
518	514	if(data & 0x01)
519	515	{
520		state->m_maria_flag=1;
	516	m_maria_flag=1;
521	517	}
522		if(!state->m_ctrl_lock)
	518	if(!m_ctrl_lock)
523	519	{
524		state->m_ctrl_lock = data & 0x01;
525		state->m_ctrl_reg = data;
	520	m_ctrl_lock = data & 0x01;
	521	m_ctrl_reg = data;
526	522
527	523	if (data & 0x04)
528		memcpy( state->m_ROM + 0xC000, state->m_cart_bkup, 0x4000 );
	524	memcpy( m_ROM + 0xC000, m_cart_bkup, 0x4000 );
529	525	else
530		memcpy( state->m_ROM + 0xC000, state->m_bios_bkup, 0x4000 );
	526	memcpy( m_ROM + 0xC000, m_bios_bkup, 0x4000 );
531	527	}
532	528	break;
533	529	}
534		tia_sound_w(space->machine().device("tia"), offset, data);
535		state->m_ROM[offset] = data;
	530	tia_sound_w(machine().device("tia"), offset, data);
	531	m_ROM[offset] = data;
536	532	}

src/mess/machine/nascom1.c

r14963	r14964
60	60	};
61	61
62	62
63		READ8_HANDLER( nascom2_fdc_select_r )
	63	READ8_MEMBER(nascom1_state::nascom2_fdc_select_r)
64	64	{
65		nascom1_state *state = space->machine().driver_data<nascom1_state>();
66		return state->m_nascom2_fdc.select | 0xa0;
	65	return m_nascom2_fdc.select | 0xa0;
67	66	}
68	67
69	68
70		WRITE8_HANDLER( nascom2_fdc_select_w )
	69	WRITE8_MEMBER(nascom1_state::nascom2_fdc_select_w)
71	70	{
72		nascom1_state *state = space->machine().driver_data<nascom1_state>();
73		device_t *fdc = space->machine().device("wd1793");
74		state->m_nascom2_fdc.select = data;
	71	device_t *fdc = machine().device("wd1793");
	72	m_nascom2_fdc.select = data;
75	73
76	74	logerror("nascom2_fdc_select_w: %02x\n", data);
77	75
r14963	r14964
90	88	* D7 -- WD1793 DRQ
91	89	*
92	90	*/
93		READ8_HANDLER( nascom2_fdc_status_r )
	91	READ8_MEMBER(nascom1_state::nascom2_fdc_status_r)
94	92	{
95		nascom1_state *state = space->machine().driver_data<nascom1_state>();
96		return (state->m_nascom2_fdc.drq << 7) | state->m_nascom2_fdc.irq;
	93	return (m_nascom2_fdc.drq << 7) | m_nascom2_fdc.irq;
97	94	}
98	95
99	96	/*************************************
r14963	r14964
102	99	*
103	100	*************************************/
104	101
105		READ8_HANDLER ( nascom1_port_00_r )
	102	READ8_MEMBER(nascom1_state::nascom1_port_00_r)
106	103	{
107		nascom1_state *state = space->machine().driver_data<nascom1_state>();
108	104	static const char *const keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4", "KEY5", "KEY6", "KEY7", "KEY8" };
109	105
110		if (state->m_portstat.stat_count < 9)
111		return (input_port_read(space->machine(), keynames[state->m_portstat.stat_count]) | ~0x7f);
	106	if (m_portstat.stat_count < 9)
	107	return (input_port_read(machine(), keynames[m_portstat.stat_count]) | ~0x7f);
112	108
113	109	return (0xff);
114	110	}
115	111
116	112
117		WRITE8_HANDLER( nascom1_port_00_w )
	113	WRITE8_MEMBER(nascom1_state::nascom1_port_00_w)
118	114	{
119		nascom1_state *state = space->machine().driver_data<nascom1_state>();
120	115
121		space->machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(
	116	machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(
122	117	( data & 0x10 ) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR );
123	118
124	119	if (!(data & NASCOM1_KEY_RESET))
125	120	{
126		if (state->m_portstat.stat_flags & NASCOM1_KEY_RESET)
127		state->m_portstat.stat_count = 0;
	121	if (m_portstat.stat_flags & NASCOM1_KEY_RESET)
	122	m_portstat.stat_count = 0;
128	123	}
129	124	else
130		state->m_portstat.stat_flags = NASCOM1_KEY_RESET;
	125	m_portstat.stat_flags = NASCOM1_KEY_RESET;
131	126
132	127	if (!(data & NASCOM1_KEY_INCR))
133	128	{
134		if (state->m_portstat.stat_flags & NASCOM1_KEY_INCR)
135		state->m_portstat.stat_count++;
	129	if (m_portstat.stat_flags & NASCOM1_KEY_INCR)
	130	m_portstat.stat_count++;
136	131	}
137	132	else
138		state->m_portstat.stat_flags = NASCOM1_KEY_INCR;
	133	m_portstat.stat_flags = NASCOM1_KEY_INCR;
139	134	}
140	135
141	136
r14963	r14964
148	143	*************************************/
149	144
150	145
151		READ8_HANDLER( nascom1_port_01_r )
	146	READ8_MEMBER(nascom1_state::nascom1_port_01_r)
152	147	{
153		nascom1_state *state = space->machine().driver_data<nascom1_state>();
154		return ay31015_get_received_data( state->m_hd6402 );
	148	return ay31015_get_received_data( m_hd6402 );
155	149	}
156	150
157	151
158		WRITE8_HANDLER( nascom1_port_01_w )
	152	WRITE8_MEMBER(nascom1_state::nascom1_port_01_w)
159	153	{
160		nascom1_state *state = space->machine().driver_data<nascom1_state>();
161		ay31015_set_transmit_data( state->m_hd6402, data );
	154	ay31015_set_transmit_data( m_hd6402, data );
162	155	}
163	156
164		READ8_HANDLER( nascom1_port_02_r )
	157	READ8_MEMBER(nascom1_state::nascom1_port_02_r)
165	158	{
166		nascom1_state *state = space->machine().driver_data<nascom1_state>();
167	159	UINT8 data = 0x31;
168	160
169		ay31015_set_input_pin( state->m_hd6402, AY31015_SWE, 0 );
170		data |= ay31015_get_output_pin( state->m_hd6402, AY31015_OR ) ? 0x02 : 0;
171		data |= ay31015_get_output_pin( state->m_hd6402, AY31015_PE ) ? 0x04 : 0;
172		data |= ay31015_get_output_pin( state->m_hd6402, AY31015_FE ) ? 0x08 : 0;
173		data |= ay31015_get_output_pin( state->m_hd6402, AY31015_TBMT ) ? 0x40 : 0;
174		data |= ay31015_get_output_pin( state->m_hd6402, AY31015_DAV ) ? 0x80 : 0;
175		ay31015_set_input_pin( state->m_hd6402, AY31015_SWE, 1 );
	161	ay31015_set_input_pin( m_hd6402, AY31015_SWE, 0 );
	162	data |= ay31015_get_output_pin( m_hd6402, AY31015_OR ) ? 0x02 : 0;
	163	data |= ay31015_get_output_pin( m_hd6402, AY31015_PE ) ? 0x04 : 0;
	164	data |= ay31015_get_output_pin( m_hd6402, AY31015_FE ) ? 0x08 : 0;
	165	data |= ay31015_get_output_pin( m_hd6402, AY31015_TBMT ) ? 0x40 : 0;
	166	data |= ay31015_get_output_pin( m_hd6402, AY31015_DAV ) ? 0x80 : 0;
	167	ay31015_set_input_pin( m_hd6402, AY31015_SWE, 1 );
176	168
177	169	return data;
178	170	}

src/mess/machine/microtan.c

r14963	r14964
345	345	via_0->write_cb2(1);
346	346	}
347	347
348		READ8_HANDLER( microtan_sound_r )
	348	READ8_MEMBER(microtan_state::microtan_sound_r)
349	349	{
350	350	int data = 0xff;
351	351	LOG(("microtan_sound_r: -> %02x\n", data));
352	352	return data;
353	353	}
354	354
355		WRITE8_HANDLER( microtan_sound_w )
	355	WRITE8_MEMBER(microtan_state::microtan_sound_w)
356	356	{
357	357	LOG(("microtan_sound_w: <- %02x\n", data));
358	358	}
359	359
360	360
361		READ8_HANDLER ( microtan_bffx_r )
	361	READ8_MEMBER(microtan_state::microtan_bffx_r)
362	362	{
363		microtan_state *state = space->machine().driver_data<microtan_state>();
364	363	int data = 0xff;
365	364	switch( offset & 3 )
366	365	{
367	366	case  0: /* BFF0: read enables chunky graphics */
368		state->m_chunky_graphics = 1;
	367	m_chunky_graphics = 1;
369	368	LOG(("microtan_bff0_r: -> %02x (chunky graphics on)\n", data));
370	369	break;
371	370	case  1: /* BFF1: read undefined (?) */
r14963	r14964
375	374	LOG(("microtan_bff2_r: -> %02x\n", data));
376	375	break;
377	376	default: /* BFF3: read keyboard ASCII value */
378		data = state->m_keyboard_ascii;
	377	data = m_keyboard_ascii;
379	378	LOG(("microtan_bff3_r: -> %02x (keyboard ASCII)\n", data));
380	379	}
381	380	return data;
r14963	r14964
388	387	cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, PULSE_LINE);
389	388	}
390	389
391		WRITE8_HANDLER ( microtan_bffx_w )
	390	WRITE8_MEMBER(microtan_state::microtan_bffx_w)
392	391	{
393		microtan_state *state = space->machine().driver_data<microtan_state>();
394	392	switch( offset & 3 )
395	393	{
396	394	case 0: /* BFF0: write reset keyboard interrupt flag */
397	395	/* This removes bit 7 from the ASCII value of the last key pressed. */
398	396	LOG(("microtan_bff0_w: %d <- %02x (keyboard IRQ clear )\n", offset, data));
399		state->m_keyboard_ascii &= ~0x80;
400		state->m_kbd_irq_line = CLEAR_LINE;
401		microtan_set_irq_line(space->machine());
	397	m_keyboard_ascii &= ~0x80;
	398	m_kbd_irq_line = CLEAR_LINE;
	399	microtan_set_irq_line(machine());
402	400	break;
403	401	case 1: /* BFF1: write delayed NMI */
404	402	LOG(("microtan_bff1_w: %d <- %02x (delayed NMI)\n", offset, data));
405		space->machine().scheduler().timer_set(space->machine().device<cpu_device>("maincpu")->cycles_to_attotime(8), FUNC(microtan_pulse_nmi));
	403	machine().scheduler().timer_set(machine().device<cpu_device>("maincpu")->cycles_to_attotime(8), FUNC(microtan_pulse_nmi));
406	404	break;
407	405	case 2: /* BFF2: write keypad column write (what is this meant for?) */
408	406	LOG(("microtan_bff2_w: %d <- %02x (keypad column)\n", offset, data));
409		state->m_keypad_column = data;
	407	m_keypad_column = data;
410	408	break;
411	409	default: /* BFF3: write disable chunky graphics */
412	410	LOG(("microtan_bff3_w: %d <- %02x (chunky graphics off)\n", offset, data));
413		state->m_chunky_graphics = 0;
	411	m_chunky_graphics = 0;
414	412	}
415	413	}
416	414

src/mess/machine/poly88.c

r14963	r14964
19	19	device_set_input_line(machine.device("maincpu"), 0, HOLD_LINE);
20	20	}
21	21
22		WRITE8_HANDLER(poly88_baud_rate_w)
	22	WRITE8_MEMBER(poly88_state::poly88_baud_rate_w)
23	23	{
24		poly88_state *state = space->machine().driver_data<poly88_state>();
25	24	logerror("poly88_baud_rate_w %02x\n",data);
26		state->m_usart_timer = space->machine().scheduler().timer_alloc(FUNC(poly88_usart_timer_callback));
27		state->m_usart_timer->adjust(attotime::zero, 0, attotime::from_hz(300));
	25	m_usart_timer = machine().scheduler().timer_alloc(FUNC(poly88_usart_timer_callback));
	26	m_usart_timer->adjust(attotime::zero, 0, attotime::from_hz(300));
28	27
29	28	}
30	29
r14963	r14964
246	245	DEVCB_NULL
247	246	};
248	247
249		READ8_HANDLER(poly88_keyboard_r)
	248	READ8_MEMBER(poly88_state::poly88_keyboard_r)
250	249	{
251		poly88_state *state = space->machine().driver_data<poly88_state>();
252		UINT8 retVal = state->m_last_code;
253		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
254		state->m_last_code = 0x00;
	250	UINT8 retVal = m_last_code;
	251	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
	252	m_last_code = 0x00;
255	253	return retVal;
256	254	}
257	255
258		WRITE8_HANDLER(poly88_intr_w)
	256	WRITE8_MEMBER(poly88_state::poly88_intr_w)
259	257	{
260		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	258	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
261	259	}
262	260
263	261	SNAPSHOT_LOAD( poly88 )

src/mess/machine/samcoupe.c

r14963	r14964
137	137	}
138	138
139	139
140		WRITE8_HANDLER( samcoupe_ext_mem_w )
	140	WRITE8_MEMBER(samcoupe_state::samcoupe_ext_mem_w)
141	141	{
142		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
143		address_space *space_program = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
	142	address_space *space_program = machine().device("maincpu")->memory().space(AS_PROGRAM);
144	143
145	144	if (offset & 1)
146		state->m_hext = data;
	145	m_hext = data;
147	146	else
148		state->m_lext = data;
	147	m_lext = data;
149	148
150	149	/* external RAM enabled? */
151		if (state->m_hmpr & HMPR_MCNTRL)
	150	if (m_hmpr & HMPR_MCNTRL)
152	151	{
153	152	samcoupe_install_ext_mem(space_program);
154	153	}

src/mess/machine/primo.c

r14963	r14964
76	76
77	77	*******************************************************************************/
78	78
79		READ8_HANDLER( primo_be_1_r )
	79	READ8_MEMBER(primo_state::primo_be_1_r)
80	80	{
81	81	UINT8 data = 0x00;
82	82	static const char *const portnames[] = { "IN0", "IN1", "IN2", "IN3" };
r14963	r14964
84	84	// bit 7, 6 - not used
85	85
86	86	// bit 5 - VBLANK
87		data |= (space->machine().primary_screen->vblank()) ? 0x20 : 0x00;
	87	data |= (machine().primary_screen->vblank()) ? 0x20 : 0x00;
88	88
89	89	// bit 4 - I4 (external bus)
90	90
91	91	// bit 3 - I3 (external bus)
92	92
93	93	// bit 2 - cassette
94		data |= ((space->machine().device<cassette_image_device>(CASSETTE_TAG))->input() < 0.1) ? 0x04 : 0x00;
	94	data |= ((machine().device<cassette_image_device>(CASSETTE_TAG))->input() < 0.1) ? 0x04 : 0x00;
95	95
96	96	// bit 1 - reset button
97		data |= (input_port_read(space->machine(), "RESET")) ? 0x02 : 0x00;
	97	data |= (input_port_read(machine(), "RESET")) ? 0x02 : 0x00;
98	98
99	99	// bit 0 - keyboard
100		data |= (input_port_read(space->machine(), portnames[(offset & 0x0030) >> 4]) >> (offset&0x000f)) & 0x0001 ? 0x01 : 0x00;
	100	data |= (input_port_read(machine(), portnames[(offset & 0x0030) >> 4]) >> (offset&0x000f)) & 0x0001 ? 0x01 : 0x00;
101	101
102	102	return data;
103	103	}
104	104
105		READ8_HANDLER( primo_be_2_r )
	105	READ8_MEMBER(primo_state::primo_be_2_r)
106	106	{
107		primo_state *state = space->machine().driver_data<primo_state>();
108	107	UINT8 data = 0xff;
109	108
110	109	// bit 7, 6 - not used
111	110
112	111	// bit 5 - SCLK
113		if (!state->m_iec->clk_r())
	112	if (!m_iec->clk_r())
114	113	data &= ~0x20;
115	114
116	115	// bit 4 - SDATA
117		if (!state->m_iec->data_r())
	116	if (!m_iec->data_r())
118	117	data &= ~0x10;
119	118
120	119	// bit 3 - SRQ
121		if (!state->m_iec->srq_r())
	120	if (!m_iec->srq_r())
122	121	data &= ~0x08;
123	122
124	123	// bit 2 - joystic 2 (not implemeted yet)
125	124
126	125	// bit 1 - ATN
127		if (!state->m_iec->atn_r())
	126	if (!m_iec->atn_r())
128	127	data &= ~0x02;
129	128
130	129	// bit 0 - joystic 1 (not implemeted yet)
r14963	r14964
133	132	return data;
134	133	}
135	134
136		WRITE8_HANDLER( primo_ki_1_w )
	135	WRITE8_MEMBER(primo_state::primo_ki_1_w)
137	136	{
138		primo_state *state = space->machine().driver_data<primo_state>();
139		device_t *speaker = space->machine().device(SPEAKER_TAG);
	137	device_t *speaker = machine().device(SPEAKER_TAG);
140	138	// bit 7 - NMI generator enable/disable
141		state->m_nmi = (data & 0x80) ? 1 : 0;
	139	m_nmi = (data & 0x80) ? 1 : 0;
142	140
143	141	// bit 6 - joystick register shift (not emulated)
144	142
r14963	r14964
149	147
150	148	// bit 3 - display buffer
151	149	if (data & 0x08)
152		state->m_video_memory_base |= 0x2000;
	150	m_video_memory_base |= 0x2000;
153	151	else
154		state->m_video_memory_base &= 0xdfff;
	152	m_video_memory_base &= 0xdfff;
155	153
156	154	// bit 2 - V.24 (1) / tape control (not emulated)
157	155
r14963	r14964
159	157	switch (data & 0x03)
160	158	{
161	159	case 0:
162		space->machine().device<cassette_image_device>(CASSETTE_TAG)->output(-1.0);
	160	machine().device<cassette_image_device>(CASSETTE_TAG)->output(-1.0);
163	161	break;
164	162	case 1:
165	163	case 2:
166		space->machine().device<cassette_image_device>(CASSETTE_TAG)->output(0.0);
	164	machine().device<cassette_image_device>(CASSETTE_TAG)->output(0.0);
167	165	break;
168	166	case 3:
169		space->machine().device<cassette_image_device>(CASSETTE_TAG)->output(1.0);
	167	machine().device<cassette_image_device>(CASSETTE_TAG)->output(1.0);
170	168	break;
171	169	}
172	170	}
173	171
174		WRITE8_HANDLER( primo_ki_2_w )
	172	WRITE8_MEMBER(primo_state::primo_ki_2_w)
175	173	{
176		primo_state *state = space->machine().driver_data<primo_state>();
177	174
178	175	// bit 7, 6 - not used
179	176
180	177	// bit 5 - SCLK
181		state->m_iec->clk_w(!BIT(data, 5));
	178	m_iec->clk_w(!BIT(data, 5));
182	179
183	180	// bit 4 - SDATA
184		state->m_iec->data_w(!BIT(data, 4));
	181	m_iec->data_w(!BIT(data, 4));
185	182
186	183	// bit 3 - not used
187	184
188	185	// bit 2 - SRQ
189		state->m_iec->srq_w(!BIT(data, 2));
	186	m_iec->srq_w(!BIT(data, 2));
190	187
191	188	// bit 1 - ATN
192		state->m_iec->atn_w(!BIT(data, 1));
	189	m_iec->atn_w(!BIT(data, 1));
193	190
194	191	// bit 0 - not used
195	192
196	193	//  logerror ("IOW KI-2 data:%02x\n", data);
197	194	}
198	195
199		WRITE8_HANDLER( primo_FD_w )
	196	WRITE8_MEMBER(primo_state::primo_FD_w)
200	197	{
201		primo_state *state = space->machine().driver_data<primo_state>();
202		if (!input_port_read(space->machine(), "MEMORY_EXPANSION"))
	198	if (!input_port_read(machine(), "MEMORY_EXPANSION"))
203	199	{
204		state->m_port_FD = data;
205		primo_update_memory(space->machine());
	200	m_port_FD = data;
	201	primo_update_memory(machine());
206	202	}
207	203	}
208	204

src/mess/machine/svi318.c

r14963	r14964
234	234	DEVCB_HANDLER(svi318_ppi_port_c_w)
235	235	};
236	236
237		WRITE8_HANDLER( svi318_ppi_w )
	237	WRITE8_MEMBER(svi318_state::svi318_ppi_w)
238	238	{
239		i8255_device *ppi = space->machine().device<i8255_device>("ppi8255");
240		ppi->write(*space, offset + 2, data);
	239	i8255_device *ppi = machine().device<i8255_device>("ppi8255");
	240	ppi->write(space, offset + 2, data);
241	241	}
242	242
243	243
r14963	r14964
256	256	8  RIGHT2 Joystick 2, Right
257	257	*/
258	258
259		READ8_HANDLER( svi318_psg_port_a_r )
	259	READ8_MEMBER(svi318_state::svi318_psg_port_a_r)
260	260	{
261		return input_port_read(space->machine(), "JOYSTICKS");
	261	return input_port_read(machine(), "JOYSTICKS");
262	262	}
263	263
264	264	/*
r14963	r14964
277	277	with RAM are disabled.
278	278	*/
279	279
280		WRITE8_HANDLER( svi318_psg_port_b_w )
	280	WRITE8_MEMBER(svi318_state::svi318_psg_port_b_w)
281	281	{
282		svi318_state *state = space->machine().driver_data<svi318_state>();
283		if ( (state->m_svi.bank_switch ^ data) & 0x20)
284		set_led_status (space->machine(), 0, !(data & 0x20) );
	282	if ( (m_svi.bank_switch ^ data) & 0x20)
	283	set_led_status (machine(), 0, !(data & 0x20) );
285	284
286		state->m_svi.bank_switch = data;
287		svi318_set_banks(space->machine());
	285	m_svi.bank_switch = data;
	286	svi318_set_banks(machine());
288	287	}
289	288
290	289	/* Disk drives  */
r14963	r14964
309	308	{FLOPPY_0, FLOPPY_1, NULL, NULL}
310	309	};
311	310
312		static WRITE8_HANDLER( svi318_fdc_drive_motor_w )
	311	WRITE8_MEMBER(svi318_state::svi318_fdc_drive_motor_w)
313	312	{
314		svi318_state *state = space->machine().driver_data<svi318_state>();
315		device_t *fdc = space->machine().device("wd179x");
	313	device_t *fdc = machine().device("wd179x");
316	314	switch (data & 3)
317	315	{
318	316	case 1:
319	317	wd17xx_set_drive(fdc,0);
320		state->m_fdc.driveselect = 0;
	318	m_fdc.driveselect = 0;
321	319	break;
322	320	case 2:
323	321	wd17xx_set_drive(fdc,1);
324		state->m_fdc.driveselect = 1;
	322	m_fdc.driveselect = 1;
325	323	break;
326	324	}
327	325	}
328	326
329		static WRITE8_HANDLER( svi318_fdc_density_side_w )
	327	WRITE8_MEMBER(svi318_state::svi318_fdc_density_side_w)
330	328	{
331		device_t *fdc = space->machine().device("wd179x");
	329	device_t *fdc = machine().device("wd179x");
332	330
333	331	wd17xx_dden_w(fdc, BIT(data, 0));
334	332	wd17xx_set_side(fdc, BIT(data, 1));
335	333	}
336	334
337		static READ8_HANDLER( svi318_fdc_irqdrq_r )
	335	READ8_MEMBER(svi318_state::svi318_fdc_irqdrq_r)
338	336	{
339		svi318_state *state = space->machine().driver_data<svi318_state>();
340	337	UINT8 result = 0;
341	338
342		result |= state->m_fdc.drq << 6;
343		result |= state->m_fdc.irq << 7;
	339	result |= m_fdc.drq << 6;
	340	result |= m_fdc.irq << 7;
344	341
345	342	return result;
346	343	}
r14963	r14964
383	380	}
384	381
385	382
386		static WRITE8_HANDLER( svi806_ram_enable_w )
	383	WRITE8_MEMBER(svi318_state::svi806_ram_enable_w)
387	384	{
388		svi318_state *state = space->machine().driver_data<svi318_state>();
389		state->m_svi.svi806_ram_enabled = ( data & 0x01 );
390		svi318_set_banks(space->machine());
	385	m_svi.svi806_ram_enabled = ( data & 0x01 );
	386	svi318_set_banks(machine());
391	387	}
392	388
393	389	VIDEO_START( svi328_806 )
r14963	r14964
597	593
598	594	/* Memory */
599	595
600		WRITE8_HANDLER( svi318_writemem1 )
	596	WRITE8_MEMBER(svi318_state::svi318_writemem1)
601	597	{
602		svi318_state *state = space->machine().driver_data<svi318_state>();
603		if ( state->m_svi.bankLow_read_only )
	598	if ( m_svi.bankLow_read_only )
604	599	return;
605	600
606		state->m_svi.bankLow_ptr[offset] = data;
	601	m_svi.bankLow_ptr[offset] = data;
607	602	}
608	603
609		WRITE8_HANDLER( svi318_writemem2 )
	604	WRITE8_MEMBER(svi318_state::svi318_writemem2)
610	605	{
611		svi318_state *state = space->machine().driver_data<svi318_state>();
612		if ( state->m_svi.bankHigh1_read_only)
	606	if ( m_svi.bankHigh1_read_only)
613	607	return;
614	608
615		state->m_svi.bankHigh1_ptr[offset] = data;
	609	m_svi.bankHigh1_ptr[offset] = data;
616	610	}
617	611
618		WRITE8_HANDLER( svi318_writemem3 )
	612	WRITE8_MEMBER(svi318_state::svi318_writemem3)
619	613	{
620		svi318_state *state = space->machine().driver_data<svi318_state>();
621		if ( state->m_svi.bankHigh2_read_only)
	614	if ( m_svi.bankHigh2_read_only)
622	615	return;
623	616
624		state->m_svi.bankHigh2_ptr[offset] = data;
	617	m_svi.bankHigh2_ptr[offset] = data;
625	618	}
626	619
627		WRITE8_HANDLER( svi318_writemem4 )
	620	WRITE8_MEMBER(svi318_state::svi318_writemem4)
628	621	{
629		svi318_state *state = space->machine().driver_data<svi318_state>();
630		if ( state->m_svi.svi806_ram_enabled )
	622	if ( m_svi.svi806_ram_enabled )
631	623	{
632	624	if ( offset < 0x800 )
633	625	{
634		state->m_svi.svi806_ram->u8(offset) = data;
	626	m_svi.svi806_ram->u8(offset) = data;
635	627	}
636	628	}
637	629	else
638	630	{
639		if ( state->m_svi.bankHigh2_read_only )
	631	if ( m_svi.bankHigh2_read_only )
640	632	return;
641	633
642		state->m_svi.bankHigh2_ptr[ 0x3000 + offset] = data;
	634	m_svi.bankHigh2_ptr[ 0x3000 + offset] = data;
643	635	}
644	636	}
645	637
r14963	r14964
770	762
771	763	/* External I/O */
772	764
773		READ8_HANDLER( svi318_io_ext_r )
	765	READ8_MEMBER(svi318_state::svi318_io_ext_r)
774	766	{
775		svi318_state *state = space->machine().driver_data<svi318_state>();
776	767	UINT8 data = 0xff;
777	768	device_t *device;
778	769	ins8250_device *uart;
779		centronics_device *centronics = space->machine().device<centronics_device>("centronics");
	770	centronics_device *centronics = machine().device<centronics_device>("centronics");
780	771
781		if (state->m_svi.bankLow == SVI_CART)
	772	if (m_svi.bankLow == SVI_CART)
782	773	{
783	774	return 0xff;
784	775	}
r14963	r14964
797	788	case 0x25:
798	789	case 0x26:
799	790	case 0x27:
800		uart = space->machine().device<ins8250_device>("ins8250_0");
801		data = uart->ins8250_r(*space, offset & 7);
	791	uart = machine().device<ins8250_device>("ins8250_0");
	792	data = uart->ins8250_r(space, offset & 7);
802	793	break;
803	794
804	795	case 0x28:
r14963	r14964
809	800	case 0x2D:
810	801	case 0x2E:
811	802	case 0x2F:
812		uart = space->machine().device<ins8250_device>("ins8250_1");
813		data = uart->ins8250_r(*space, offset & 7);
	803	uart = machine().device<ins8250_device>("ins8250_1");
	804	data = uart->ins8250_r(space, offset & 7);
814	805	break;
815	806
816	807	case 0x30:
817		device = space->machine().device("wd179x");
	808	device = machine().device("wd179x");
818	809	data = wd17xx_status_r(device, 0);
819	810	break;
820	811	case 0x31:
821		device = space->machine().device("wd179x");
	812	device = machine().device("wd179x");
822	813	data = wd17xx_track_r(device, 0);
823	814	break;
824	815	case 0x32:
825		device = space->machine().device("wd179x");
	816	device = machine().device("wd179x");
826	817	data = wd17xx_sector_r(device, 0);
827	818	break;
828	819	case 0x33:
829		device = space->machine().device("wd179x");
	820	device = machine().device("wd179x");
830	821	data = wd17xx_data_r(device, 0);
831	822	break;
832	823	case 0x34:
833	824	data = svi318_fdc_irqdrq_r(space, 0);
834	825	break;
835	826	case 0x51:
836		device = space->machine().device("crtc");
837		data = downcast<mc6845_device *>(device)->register_r( *space, offset );
	827	device = machine().device("crtc");
	828	data = downcast<mc6845_device *>(device)->register_r( space, offset );
838	829	break;
839	830	}
840	831
841	832	return data;
842	833	}
843	834
844		WRITE8_HANDLER( svi318_io_ext_w )
	835	WRITE8_MEMBER(svi318_state::svi318_io_ext_w)
845	836	{
846		svi318_state *state = space->machine().driver_data<svi318_state>();
847	837	device_t *device;
848	838	ins8250_device *uart;
849		centronics_device *centronics = space->machine().device<centronics_device>("centronics");
	839	centronics_device *centronics = machine().device<centronics_device>("centronics");
850	840
851		if (state->m_svi.bankLow == SVI_CART)
	841	if (m_svi.bankLow == SVI_CART)
852	842	{
853	843	return;
854	844	}
r14963	r14964
856	846	switch( offset )
857	847	{
858	848	case 0x10:
859		centronics->write(*space, 0, data);
	849	centronics->write(space, 0, data);
860	850	break;
861	851
862	852	case 0x11:
r14963	r14964
871	861	case 0x25:
872	862	case 0x26:
873	863	case 0x27:
874		uart = space->machine().device<ins8250_device>("ins8250_0");
875		uart->ins8250_w(*space, offset & 7, data);
	864	uart = machine().device<ins8250_device>("ins8250_0");
	865	uart->ins8250_w(space, offset & 7, data);
876	866	break;
877	867
878	868	case 0x28:
r14963	r14964
883	873	case 0x2D:
884	874	case 0x2E:
885	875	case 0x2F:
886		uart = space->machine().device<ins8250_device>("ins8250_1");
887		uart->ins8250_w(*space, offset & 7, data);
	876	uart = machine().device<ins8250_device>("ins8250_1");
	877	uart->ins8250_w(space, offset & 7, data);
888	878	break;
889	879
890	880	case 0x30:
891		device = space->machine().device("wd179x");
	881	device = machine().device("wd179x");
892	882	wd17xx_command_w(device, 0, data);
893	883	break;
894	884	case 0x31:
895		device = space->machine().device("wd179x");
	885	device = machine().device("wd179x");
896	886	wd17xx_track_w(device, 0, data);
897	887	break;
898	888	case 0x32:
899		device = space->machine().device("wd179x");
	889	device = machine().device("wd179x");
900	890	wd17xx_sector_w(device, 0, data);
901	891	break;
902	892	case 0x33:
903		device = space->machine().device("wd179x");
	893	device = machine().device("wd179x");
904	894	wd17xx_data_w(device, 0, data);
905	895	break;
906	896	case 0x34:
r14963	r14964
911	901	break;
912	902
913	903	case 0x50:
914		device = space->machine().device("crtc");
915		downcast<mc6845_device *>(device)->address_w(*space, offset, data);
	904	device = machine().device("crtc");
	905	downcast<mc6845_device *>(device)->address_w(space, offset, data);
916	906	break;
917	907	case 0x51:
918		device = space->machine().device("crtc");
919		downcast<mc6845_device *>(device)->register_w(*space, offset, data);
	908	device = machine().device("crtc");
	909	downcast<mc6845_device *>(device)->register_w(space, offset, data);
920	910	break;
921	911
922	912	case 0x58:

src/mess/machine/z80ne.c

r14963	r14964
339	339	ay31015_set_transmitter_clock( state->m_ay31015, state->m_cass_data.speed * 16.0);
340	340
341	341	state->m_nmi_delay_counter = 0;
342		lx385_ctrl_w(space, 0, 0);
	342	state->lx385_ctrl_w(*space, 0, 0);
343	343
344	344	}
345	345
r14963	r14964
431	431	******************************************************************************/
432	432
433	433	/* LX.383 - LX.384 HEX keyboard and display */
434		READ8_HANDLER( lx383_r )
	434	READ8_MEMBER(z80ne_state::lx383_r)
435	435	{
436		z80ne_state *state = space->machine().driver_data<z80ne_state>();
437	436	/*
438	437	* Keyboard scanning
439	438	*
r14963	r14964
451	450	*      D6 - 0
452	451	*      D7 - ~KEY Pressed
453	452	*/
454		return state->m_lx383_key[state->m_lx383_scan_counter];
	453	return m_lx383_key[m_lx383_scan_counter];
455	454	}
456	455
457		WRITE8_HANDLER( lx383_w )
	456	WRITE8_MEMBER(z80ne_state::lx383_w)
458	457	{
459		z80ne_state *state = space->machine().driver_data<z80ne_state>();
460	458	/*
461	459	* First 8 locations (F0-F7) are mapped to a dual-port 8-byte RAM
462	460	* The 1KHz NE-555 astable oscillator circuit drive
r14963	r14964
486	484	output_set_digit_value( offset, data ^ 0xff );
487	485	else
488	486	/* after writing to port 0xF8 and the first ~M1 cycles strike a NMI for single step execution */
489		state->m_nmi_delay_counter = 1;
490		space->machine().device("z80ne")->memory().space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_nmi_delay_count), &space->machine()));
	487	m_nmi_delay_counter = 1;
	488	machine().device("z80ne")->memory().space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_nmi_delay_count), &machine()));
491	489	}
492	490
493	491
r14963	r14964
534	532	data on the positive-edge of the clock pulse.
535	533	*
536	534	*/
537		READ8_HANDLER(lx385_data_r)
	535	READ8_MEMBER(z80ne_state::lx385_data_r)
538	536	{
539		z80ne_state *state = space->machine().driver_data<z80ne_state>();
540		return ay31015_get_received_data( state->m_ay31015 );
	537	return ay31015_get_received_data( m_ay31015 );
541	538	}
542	539
543		READ8_HANDLER(lx385_ctrl_r)
	540	READ8_MEMBER(z80ne_state::lx385_ctrl_r)
544	541	{
545		z80ne_state *state = space->machine().driver_data<z80ne_state>();
546	542	/* set unused bits high */
547	543	UINT8 data = 0xc0;
548	544
549		ay31015_set_input_pin( state->m_ay31015, AY31015_SWE, 0 );
550		data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_OR   ) ? 0x01 : 0);
551		data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_FE   ) ? 0x02 : 0);
552		data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_PE   ) ? 0x04 : 0);
553		data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_TBMT ) ? 0x08 : 0);
554		data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_DAV  ) ? 0x10 : 0);
555		data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_EOC  ) ? 0x20 : 0);
556		ay31015_set_input_pin( state->m_ay31015, AY31015_SWE, 1 );
	545	ay31015_set_input_pin( m_ay31015, AY31015_SWE, 0 );
	546	data |= (ay31015_get_output_pin( m_ay31015, AY31015_OR   ) ? 0x01 : 0);
	547	data |= (ay31015_get_output_pin( m_ay31015, AY31015_FE   ) ? 0x02 : 0);
	548	data |= (ay31015_get_output_pin( m_ay31015, AY31015_PE   ) ? 0x04 : 0);
	549	data |= (ay31015_get_output_pin( m_ay31015, AY31015_TBMT ) ? 0x08 : 0);
	550	data |= (ay31015_get_output_pin( m_ay31015, AY31015_DAV  ) ? 0x10 : 0);
	551	data |= (ay31015_get_output_pin( m_ay31015, AY31015_EOC  ) ? 0x20 : 0);
	552	ay31015_set_input_pin( m_ay31015, AY31015_SWE, 1 );
557	553
558	554	return data;
559	555	}
560	556
561		WRITE8_HANDLER(lx385_data_w)
	557	WRITE8_MEMBER(z80ne_state::lx385_data_w)
562	558	{
563		z80ne_state *state = space->machine().driver_data<z80ne_state>();
564		ay31015_set_transmit_data( state->m_ay31015, data );
	559	ay31015_set_transmit_data( m_ay31015, data );
565	560	}
566	561
567	562	#define LX385_CASSETTE_MOTOR_MASK ((1<<3)|(1<<4))
568	563
569		WRITE8_HANDLER(lx385_ctrl_w)
	564	WRITE8_MEMBER(z80ne_state::lx385_ctrl_w)
570	565	{
571		z80ne_state *state = space->machine().driver_data<z80ne_state>();
572	566	/* Translate data to control signals
573	567	*     0 bit1=0, bit0=0   UART Reset pulse
574	568	*     1 bit1=0, bit0=1   UART RDAV (Reset Data Available) pulse
r14963	r14964
578	572	*/
579	573	UINT8 uart_reset, uart_rdav, uart_tx_clock;
580	574	UINT8 motor_a, motor_b;
581		UINT8 changed_bits = (state->m_lx385_ctrl ^ data) & 0x1C;
582		state->m_lx385_ctrl = data;
	575	UINT8 changed_bits = (m_lx385_ctrl ^ data) & 0x1C;
	576	m_lx385_ctrl = data;
583	577
584	578	uart_reset = ((data & 0x03) == 0x00);
585	579	uart_rdav  = ((data & 0x03) == 0x01);
r14963	r14964
590	584	/* UART Reset and RDAV */
591	585	if(uart_reset)
592	586	{
593		ay31015_set_input_pin( state->m_ay31015, AY31015_XR, 1 );
594		ay31015_set_input_pin( state->m_ay31015, AY31015_XR, 0 );
	587	ay31015_set_input_pin( m_ay31015, AY31015_XR, 1 );
	588	ay31015_set_input_pin( m_ay31015, AY31015_XR, 0 );
595	589	}
596	590
597	591	if(uart_rdav)
598	592	{
599		ay31015_set_input_pin( state->m_ay31015, AY31015_RDAV, 1 );
600		ay31015_set_input_pin( state->m_ay31015, AY31015_RDAV, 0 );
	593	ay31015_set_input_pin( m_ay31015, AY31015_RDAV, 1 );
	594	ay31015_set_input_pin( m_ay31015, AY31015_RDAV, 0 );
601	595	}
602	596
603	597	if (!changed_bits) return;
604	598
605	599	/* UART Tx Clock enable/disable */
606	600	if(changed_bits & 0x04)
607		ay31015_set_transmitter_clock( state->m_ay31015, uart_tx_clock ? state->m_cass_data.speed * 16.0 : 0.0);
	601	ay31015_set_transmitter_clock( m_ay31015, uart_tx_clock ? m_cass_data.speed * 16.0 : 0.0);
608	602
609	603	/* motors */
610	604	if(changed_bits & 0x18)
611	605	{
612		space->machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(
	606	machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(
613	607	(motor_a) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
614	608
615		space->machine().device<cassette_image_device>(CASSETTE2_TAG)->change_state(
	609	machine().device<cassette_image_device>(CASSETTE2_TAG)->change_state(
616	610	(motor_b) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
617	611
618	612	if (motor_a || motor_b)
619		state->m_cassette_timer->adjust(attotime::zero, 0, attotime::from_hz(LX385_TAPE_SAMPLE_FREQ));
	613	m_cassette_timer->adjust(attotime::zero, 0, attotime::from_hz(LX385_TAPE_SAMPLE_FREQ));
620	614	else
621		state->m_cassette_timer->adjust(attotime::zero);
	615	m_cassette_timer->adjust(attotime::zero);
622	616	}
623	617	}
624	618
r14963	r14964
638	632	return videoram[offset];
639	633	}
640	634
641		READ8_HANDLER(lx388_data_r)
	635	READ8_MEMBER(z80ne_state::lx388_data_r)
642	636	{
643		z80ne_state *state = space->machine().driver_data<z80ne_state>();
644	637	UINT8 data;
645	638
646		data = kr2376_data_r(state->m_lx388_kr2376, 0) & 0x7f;
647		data |= kr2376_get_output_pin(state->m_lx388_kr2376, KR2376_SO) << 7;
	639	data = kr2376_data_r(m_lx388_kr2376, 0) & 0x7f;
	640	data |= kr2376_get_output_pin(m_lx388_kr2376, KR2376_SO) << 7;
648	641	return data;
649	642	}
650	643
651		READ8_HANDLER( lx388_read_field_sync )
	644	READ8_MEMBER(z80ne_state::lx388_read_field_sync)
652	645	{
653		z80ne_state *state = space->machine().driver_data<z80ne_state>();
654		return state->m_vdg->fs_r() << 7;
	646	return m_vdg->fs_r() << 7;
655	647	}
656	648
657	649	/*

src/mess/machine/nes.c

r14963	r14964
25	25
26	26	static void init_nes_core(running_machine &machine);
27	27	static void nes_machine_stop(running_machine &machine);
28		static READ8_HANDLER(nes_fds_r);
29		static WRITE8_HANDLER(nes_fds_w);
	28
	29
30	30	static void fds_irq(device_t *device, int scanline, int vblank, int blanked);
31	31
32	32	/***************************************************************************
r14963	r14964
68	68	if (state->m_fds_ram == NULL)
69	69	state->m_fds_ram = auto_alloc_array(machine, UINT8, 0x8000);
70	70
71		space->install_legacy_read_handler(0x4030, 0x403f, FUNC(nes_fds_r));
	71	space->install_read_handler(0x4030, 0x403f, read8_delegate(FUNC(nes_state::nes_fds_r),state));
72	72	space->install_read_bank(0x6000, 0xdfff, "bank2");
73	73	space->install_read_bank(0xe000, 0xffff, "bank1");
74	74
75		space->install_legacy_write_handler(0x4020, 0x402f, FUNC(nes_fds_w));
	75	space->install_write_handler(0x4020, 0x402f, write8_delegate(FUNC(nes_state::nes_fds_w),state));
76	76	space->install_write_bank(0x6000, 0xdfff, "bank2");
77	77
78	78	memory_set_bankptr(machine, "bank1", &state->m_rom[0xe000]);
r14963	r14964
331	331
332	332
333	333
334		READ8_HANDLER( nes_IN0_r )
	334	READ8_MEMBER(nes_state::nes_IN0_r)
335	335	{
336		nes_state *state = space->machine().driver_data<nes_state>();
337		int cfg = input_port_read(space->machine(), "CTRLSEL");
	336	int cfg = input_port_read(machine(), "CTRLSEL");
338	337	int ret;
339	338
340	339	if ((cfg & 0x000f) >= 0x07)   // for now we treat the FC keyboard separately from other inputs!
r14963	r14964
348	347	/* in the unused upper 3 bits, so typically a read from $4016 leaves 0x40 there. */
349	348	ret = 0x40;
350	349
351		ret |= ((state->m_in_0.i0 >> state->m_in_0.shift) & 0x01);
	350	ret |= ((m_in_0.i0 >> m_in_0.shift) & 0x01);
352	351
353	352	/* zapper */
354	353	if ((cfg & 0x000f) == 0x0002)
355	354	{
356		int x = state->m_in_0.i1;   /* read Zapper x-position */
357		int y = state->m_in_0.i2;   /* read Zapper y-position */
	355	int x = m_in_0.i1;   /* read Zapper x-position */
	356	int y = m_in_0.i2;   /* read Zapper y-position */
358	357	UINT32 pix, color_base;
359	358
360	359	/* get the pixel at the gun position */
361		pix = state->m_ppu->get_pixel(x, y);
	360	pix = m_ppu->get_pixel(x, y);
362	361
363	362	/* get the color base from the ppu */
364		color_base = state->m_ppu->get_colorbase();
	363	color_base = m_ppu->get_colorbase();
365	364
366	365	/* look at the screen and see if the cursor is over a bright pixel */
367	366	if ((pix == color_base + 0x20) || (pix == color_base + 0x30) ||
r14963	r14964
373	372	ret |= 0x08;  /* no sprite hit */
374	373
375	374	/* If button 1 is pressed, indicate the light gun trigger is pressed */
376		ret |= ((state->m_in_0.i0 & 0x01) << 4);
	375	ret |= ((m_in_0.i0 & 0x01) << 4);
377	376	}
378	377
379	378	if (LOG_JOY)
380		logerror("joy 0 read, val: %02x, pc: %04x, bits read: %d, chan0: %08x\n", ret, cpu_get_pc(&space->device()), state->m_in_0.shift, state->m_in_0.i0);
	379	logerror("joy 0 read, val: %02x, pc: %04x, bits read: %d, chan0: %08x\n", ret, cpu_get_pc(&space.device()), m_in_0.shift, m_in_0.i0);
381	380
382		state->m_in_0.shift++;
	381	m_in_0.shift++;
383	382	}
384	383
385	384	return ret;
r14963	r14964
399	398	return ((input_port_read(machine, sub_keyport_names[scan]) >> (mode * 4)) & 0x0f) << 1;
400	399	}
401	400
402		READ8_HANDLER( nes_IN1_r )
	401	READ8_MEMBER(nes_state::nes_IN1_r)
403	402	{
404		nes_state *state = space->machine().driver_data<nes_state>();
405		int cfg = input_port_read(space->machine(), "CTRLSEL");
	403	int cfg = input_port_read(machine(), "CTRLSEL");
406	404	int ret;
407	405
408	406	if ((cfg & 0x000f) == 0x07)   // for now we treat the FC keyboard separately from other inputs!
409	407	{
410		if (state->m_fck_scan < 9)
411		ret = ~nes_read_fc_keyboard_line(space->machine(), state->m_fck_scan, state->m_fck_mode) & 0x1e;
	408	if (m_fck_scan < 9)
	409	ret = ~nes_read_fc_keyboard_line(machine(), m_fck_scan, m_fck_mode) & 0x1e;
412	410	else
413	411	ret = 0x1e;
414	412	}
415	413	else if ((cfg & 0x000f) == 0x08)   // for now we treat the Subor keyboard separately from other inputs!
416	414	{
417		if (state->m_fck_scan < 12)
418		ret = ~nes_read_subor_keyboard_line(space->machine(), state->m_fck_scan, state->m_fck_mode) & 0x1e;
	415	if (m_fck_scan < 12)
	416	ret = ~nes_read_subor_keyboard_line(machine(), m_fck_scan, m_fck_mode) & 0x1e;
419	417	else
420	418	ret = 0x1e;
421	419	}
r14963	r14964
426	424	ret = 0x40;
427	425
428	426	/* Handle data line 0's serial output */
429		ret |= ((state->m_in_1.i0 >> state->m_in_1.shift) & 0x01);
	427	ret |= ((m_in_1.i0 >> m_in_1.shift) & 0x01);
430	428
431	429	/* zapper */
432	430	if ((cfg & 0x00f0) == 0x0030)
433	431	{
434		int x = state->m_in_1.i1;   /* read Zapper x-position */
435		int y = state->m_in_1.i2;   /* read Zapper y-position */
	432	int x = m_in_1.i1;   /* read Zapper x-position */
	433	int y = m_in_1.i2;   /* read Zapper y-position */
436	434	UINT32 pix, color_base;
437	435
438	436	/* get the pixel at the gun position */
439		pix = state->m_ppu->get_pixel(x, y);
	437	pix = m_ppu->get_pixel(x, y);
440	438
441	439	/* get the color base from the ppu */
442		color_base = state->m_ppu->get_colorbase();
	440	color_base = m_ppu->get_colorbase();
443	441
444	442	/* look at the screen and see if the cursor is over a bright pixel */
445	443	if ((pix == color_base + 0x20) || (pix == color_base + 0x30) ||
r14963	r14964
451	449	ret |= 0x08;  /* no sprite hit */
452	450
453	451	/* If button 1 is pressed, indicate the light gun trigger is pressed */
454		ret |= ((state->m_in_1.i0 & 0x01) << 4);
	452	ret |= ((m_in_1.i0 & 0x01) << 4);
455	453	}
456	454
457	455	/* arkanoid dial */
458	456	else if ((cfg & 0x00f0) == 0x0040)
459	457	{
460	458	/* Handle data line 2's serial output */
461		ret |= ((state->m_in_1.i2 >> state->m_in_1.shift) & 0x01) << 3;
	459	ret |= ((m_in_1.i2 >> m_in_1.shift) & 0x01) << 3;
462	460
463	461	/* Handle data line 3's serial output - bits are reversed */
464	462	/* NPW 27-Nov-2007 - there is no third subscript! commenting out */
465		/* ret |= ((state->m_in_1[3] >> state->m_in_1.shift) & 0x01) << 4; */
466		/* ret |= ((state->m_in_1[3] << state->m_in_1.shift) & 0x80) >> 3; */
	463	/* ret |= ((m_in_1[3] >> m_in_1.shift) & 0x01) << 4; */
	464	/* ret |= ((m_in_1[3] << m_in_1.shift) & 0x80) >> 3; */
467	465	}
468	466
469	467	if (LOG_JOY)
470		logerror("joy 1 read, val: %02x, pc: %04x, bits read: %d, chan0: %08x\n", ret, cpu_get_pc(&space->device()), state->m_in_1.shift, state->m_in_1.i0);
	468	logerror("joy 1 read, val: %02x, pc: %04x, bits read: %d, chan0: %08x\n", ret, cpu_get_pc(&space.device()), m_in_1.shift, m_in_1.i0);
471	469
472		state->m_in_1.shift++;
	470	m_in_1.shift++;
473	471	}
474	472
475	473	return ret;
r14963	r14964
553	551	}
554	552	}
555	553
556		WRITE8_HANDLER( nes_IN0_w )
	554	WRITE8_MEMBER(nes_state::nes_IN0_w)
557	555	{
558		nes_state *state = space->machine().driver_data<nes_state>();
559		int cfg = input_port_read(space->machine(), "CTRLSEL");
	556	int cfg = input_port_read(machine(), "CTRLSEL");
560	557
561	558	/* Check if lightgun has been chosen as input: if so, enable crosshair */
562		space->machine().scheduler().timer_set(attotime::zero, FUNC(lightgun_tick));
	559	machine().scheduler().timer_set(attotime::zero, FUNC(lightgun_tick));
563	560
564	561	if ((cfg & 0x000f) >= 0x07)   // for now we treat the FC keyboard separately from other inputs!
565	562	{
r14963	r14964
570	567	int lines = ((cfg & 0x000f) == 0x04) ? 9 : 12;
571	568	UINT8 out = BIT(data, 1);   // scan
572	569
573		if (state->m_fck_mode && !out && ++state->m_fck_scan > lines)
574		state->m_fck_scan = 0;
	570	if (m_fck_mode && !out && ++m_fck_scan > lines)
	571	m_fck_scan = 0;
575	572
576		state->m_fck_mode = out;   // access lower or upper 4 bits
	573	m_fck_mode = out;   // access lower or upper 4 bits
577	574
578	575	if (BIT(data, 0))   // reset
579		state->m_fck_scan = 0;
	576	m_fck_scan = 0;
580	577	}
581	578	}
582	579	else
r14963	r14964
585	582	return;
586	583
587	584	if (LOG_JOY)
588		logerror("joy 0 bits read: %d\n", state->m_in_0.shift);
	585	logerror("joy 0 bits read: %d\n", m_in_0.shift);
589	586
590	587	/* Toggling bit 0 high then low resets both controllers */
591		state->m_in_0.shift = 0;
592		state->m_in_1.shift = 0;
	588	m_in_0.shift = 0;
	589	m_in_1.shift = 0;
593	590
594	591	/* Read the input devices */
595	592	if ((cfg & 0x000f) != 0x06)
596	593	{
597		nes_read_input_device(space->machine(), cfg >>  0, &state->m_in_0, 0,  TRUE);
598		nes_read_input_device(space->machine(), cfg >>  4, &state->m_in_1, 1,  TRUE);
599		nes_read_input_device(space->machine(), cfg >>  8, &state->m_in_2, 2, FALSE);
600		nes_read_input_device(space->machine(), cfg >> 12, &state->m_in_3, 3, FALSE);
	594	nes_read_input_device(machine(), cfg >>  0, &m_in_0, 0,  TRUE);
	595	nes_read_input_device(machine(), cfg >>  4, &m_in_1, 1,  TRUE);
	596	nes_read_input_device(machine(), cfg >>  8, &m_in_2, 2, FALSE);
	597	nes_read_input_device(machine(), cfg >> 12, &m_in_3, 3, FALSE);
601	598	}
602	599	else // crazy climber pad
603	600	{
604		nes_read_input_device(space->machine(), 0, &state->m_in_1, 1,  TRUE);
605		nes_read_input_device(space->machine(), 0, &state->m_in_2, 2, FALSE);
606		nes_read_input_device(space->machine(), 0, &state->m_in_3, 3, FALSE);
607		nes_read_input_device(space->machine(), cfg >>  0, &state->m_in_0, 0,  TRUE);
	601	nes_read_input_device(machine(), 0, &m_in_1, 1,  TRUE);
	602	nes_read_input_device(machine(), 0, &m_in_2, 2, FALSE);
	603	nes_read_input_device(machine(), 0, &m_in_3, 3, FALSE);
	604	nes_read_input_device(machine(), cfg >>  0, &m_in_0, 0,  TRUE);
608	605	}
609	606
610	607	if (cfg & 0x0f00)
611		state->m_in_0.i0 |= (state->m_in_2.i0 << 8) | (0x08 << 16);
	608	m_in_0.i0 |= (m_in_2.i0 << 8) | (0x08 << 16);
612	609
613	610	if (cfg & 0xf000)
614		state->m_in_1.i0 |= (state->m_in_3.i0 << 8) | (0x04 << 16);
	611	m_in_1.i0 |= (m_in_3.i0 << 8) | (0x04 << 16);
615	612	}
616	613	}
617	614
618	615
619		WRITE8_HANDLER( nes_IN1_w )
	616	WRITE8_MEMBER(nes_state::nes_IN1_w)
620	617	{
621	618	}
622	619
r14963	r14964
1552	1549	}
1553	1550	}
1554	1551
1555		static READ8_HANDLER( nes_fds_r )
	1552	READ8_MEMBER(nes_state::nes_fds_r)
1556	1553	{
1557		nes_state *state = space->machine().driver_data<nes_state>();
1558	1554	UINT8 ret = 0x00;
1559	1555
1560	1556	switch (offset)
1561	1557	{
1562	1558	case 0x00: /* $4030 - disk status 0 */
1563		ret = state->m_fds_status0;
	1559	ret = m_fds_status0;
1564	1560	/* clear the disk IRQ detect flag */
1565		state->m_fds_status0 &= ~0x01;
	1561	m_fds_status0 &= ~0x01;
1566	1562	break;
1567	1563	case 0x01: /* $4031 - data latch */
1568	1564	/* don't read data if disk is unloaded */
1569		if (state->m_fds_data == NULL)
	1565	if (m_fds_data == NULL)
1570	1566	ret = 0;
1571		else if (state->m_fds_current_side)
	1567	else if (m_fds_current_side)
1572	1568	{
1573	1569	// a bunch of games (e.g. bshashsc and fairypin) keep reading beyond the last track
1574	1570	// what is the expected behavior?
1575		if (state->m_fds_head_position > 65500)
1576		state->m_fds_head_position = 0;
1577		ret = state->m_fds_data[(state->m_fds_current_side - 1) * 65500 + state->m_fds_head_position++];
	1571	if (m_fds_head_position > 65500)
	1572	m_fds_head_position = 0;
	1573	ret = m_fds_data[(m_fds_current_side - 1) * 65500 + m_fds_head_position++];
1578	1574	}
1579	1575	else
1580	1576	ret = 0;
1581	1577	break;
1582	1578	case 0x02: /* $4032 - disk status 1 */
1583	1579	/* return "no disk" status if disk is unloaded */
1584		if (state->m_fds_data == NULL)
	1580	if (m_fds_data == NULL)
1585	1581	ret = 1;
1586		else if (state->m_fds_last_side != state->m_fds_current_side)
	1582	else if (m_fds_last_side != m_fds_current_side)
1587	1583	{
1588	1584	/* If we've switched disks, report "no disk" for a few reads */
1589	1585	ret = 1;
1590		state->m_fds_count++;
1591		if (state->m_fds_count == 50)
	1586	m_fds_count++;
	1587	if (m_fds_count == 50)
1592	1588	{
1593		state->m_fds_last_side = state->m_fds_current_side;
1594		state->m_fds_count = 0;
	1589	m_fds_last_side = m_fds_current_side;
	1590	m_fds_count = 0;
1595	1591	}
1596	1592	}
1597	1593	else
1598		ret = (state->m_fds_current_side == 0); /* 0 if a disk is inserted */
	1594	ret = (m_fds_current_side == 0); /* 0 if a disk is inserted */
1599	1595	break;
1600	1596	case 0x03: /* $4033 */
1601	1597	ret = 0x80;
r14963	r14964
1608	1604	return ret;
1609	1605	}
1610	1606
1611		static WRITE8_HANDLER( nes_fds_w )
	1607	WRITE8_MEMBER(nes_state::nes_fds_w)
1612	1608	{
1613		nes_state *state = space->machine().driver_data<nes_state>();
1614	1609
1615	1610	switch (offset)
1616	1611	{
1617	1612	case 0x00:
1618		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0xff00) | data;
	1613	m_IRQ_count_latch = (m_IRQ_count_latch & 0xff00) | data;
1619	1614	break;
1620	1615	case 0x01:
1621		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0x00ff) | (data << 8);
	1616	m_IRQ_count_latch = (m_IRQ_count_latch & 0x00ff) | (data << 8);
1622	1617	break;
1623	1618	case 0x02:
1624		state->m_IRQ_count = state->m_IRQ_count_latch;
1625		state->m_IRQ_enable = data;
	1619	m_IRQ_count = m_IRQ_count_latch;
	1620	m_IRQ_enable = data;
1626	1621	break;
1627	1622	case 0x03:
1628	1623	// d0 = sound io (1 = enable)
r14963	r14964
1632	1627	/* write data out to disk */
1633	1628	break;
1634	1629	case 0x05:
1635		state->m_fds_motor_on = BIT(data, 0);
	1630	m_fds_motor_on = BIT(data, 0);
1636	1631
1637	1632	if (BIT(data, 1))
1638		state->m_fds_head_position = 0;
	1633	m_fds_head_position = 0;
1639	1634
1640		state->m_fds_read_mode = BIT(data, 2);
1641		set_nt_mirroring(space->machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1635	m_fds_read_mode = BIT(data, 2);
	1636	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1642	1637
1643		if ((!(data & 0x40)) && (state->m_fds_write_reg & 0x40))
1644		state->m_fds_head_position -= 2; // ???
	1638	if ((!(data & 0x40)) && (m_fds_write_reg & 0x40))
	1639	m_fds_head_position -= 2; // ???
1645	1640
1646		state->m_IRQ_enable_latch = BIT(data, 7);
1647		state->m_fds_write_reg = data;
	1641	m_IRQ_enable_latch = BIT(data, 7);
	1642	m_fds_write_reg = data;
1648	1643	break;
1649	1644	}
1650	1645	}

src/mess/machine/apollo.c

r14963	r14964
223	223	DN3000/DN3500 CPU Status Register at 0x8000/0x10000
224	224	-------------------------------------------------*/
225	225
226		WRITE16_HANDLER( apollo_csr_status_register_w ) {
	226	WRITE16_MEMBER(apollo_state::apollo_csr_status_register_w){
227	227	// To clear bus timeouts or parity conditions from status register,
228	228	// write to the status register. This register is readonly.
229	229	// in DN3500 bit 15 is always set (undocumented !?)
r14963	r14964
231	231	SLOG1(("writing CPU Status Register at offset %X = %04x & %04x (%04x)", offset, data, mem_mask, cpu_status_register));
232	232	}
233	233
234		READ16_HANDLER( apollo_csr_status_register_r ) {
	234	READ16_MEMBER(apollo_state::apollo_csr_status_register_r){
235	235	SLOG2(("reading CPU Status Register at offset %X = %04x & %04x", offset, cpu_status_register, mem_mask));
236	236	return cpu_status_register & mem_mask;
237	237	}
r14963	r14964
240	240	DN3000/DN3500 CPU Control Register at 0x8100/0x10100
241	241	-------------------------------------------------*/
242	242
243		WRITE16_HANDLER( apollo_csr_control_register_w )
	243	WRITE16_MEMBER(apollo_state::apollo_csr_control_register_w)
244	244	{
245	245	int leds;
246	246
r14963	r14964
255	255	else if ((data & APOLLO_CSR_CR_FPU_TRAP_ENABLE) == 0)
256	256	{
257	257	// enable FPU (i.e. FPU opcodes in CPU)
258		apollo_set_cpu_has_fpu(&space->device(), 1);
	258	apollo_set_cpu_has_fpu(&space.device(), 1);
259	259	}
260	260	else
261	261	{
262	262	// disable FPU (i.e. FPU opcodes in CPU)
263		apollo_set_cpu_has_fpu(&space->device(), 0);
	263	apollo_set_cpu_has_fpu(&space.device(), 0);
264	264
265	265	if (!apollo_is_dn3000())
266	266	{
r14963	r14964
294	294	}
295	295	}
296	296
297		READ16_HANDLER( apollo_csr_control_register_r )
	297	READ16_MEMBER(apollo_state::apollo_csr_control_register_r)
298	298	{
299	299	SLOG1(("reading CPU Control Register at offset %X = %04x & %04x", offset, cpu_control_register, mem_mask));
300	300	return cpu_control_register & mem_mask;
r14963	r14964
339	339	DN3000/DN3500 DMA Controller 1 at 0x9000/0x10c00
340	340	-------------------------------------------------*/
341	341
342		WRITE8_HANDLER(apollo_dma_1_w ) {
	342	WRITE8_MEMBER(apollo_state::apollo_dma_1_w){
343	343	SLOG1(("apollo_dma_1_w: writing DMA Controller 1 at offset %02x = %02x", offset, data));
344		i8237_w(get_device_dma8237_1(&space->device()), offset, data);
	344	i8237_w(get_device_dma8237_1(&space.device()), offset, data);
345	345	}
346	346
347		READ8_HANDLER( apollo_dma_1_r ) {
348		UINT8 data = i8237_r(get_device_dma8237_1(&space->device()), offset);
	347	READ8_MEMBER(apollo_state::apollo_dma_1_r){
	348	UINT8 data = i8237_r(get_device_dma8237_1(&space.device()), offset);
349	349	SLOG1(("apollo_dma_1_r: reading DMA Controller 1 at offset %02x = %02x", offset, data));
350	350	return data;
351	351	}
r14963	r14964
354	354	DN3000/DN3500 DMA Controller 2 at 0x9100/0x10d00
355	355	-------------------------------------------------*/
356	356
357		WRITE8_HANDLER(apollo_dma_2_w ) {
	357	WRITE8_MEMBER(apollo_state::apollo_dma_2_w){
358	358	SLOG1(("apollo_dma_2_w: writing DMA Controller 2 at offset %02x = %02x", offset/2, data));
359		i8237_w(get_device_dma8237_2(&space->device()), offset / 2, data);
	359	i8237_w(get_device_dma8237_2(&space.device()), offset / 2, data);
360	360	}
361	361
362		READ8_HANDLER( apollo_dma_2_r ) {
363		UINT8 data = i8237_r(get_device_dma8237_2(&space->device()), offset / 2);
	362	READ8_MEMBER(apollo_state::apollo_dma_2_r){
	363	UINT8 data = i8237_r(get_device_dma8237_2(&space.device()), offset / 2);
364	364	SLOG1(("apollo_dma_2_r: reading DMA Controller 2 at offset %02x = %02x", offset/2, data));
365	365	return data;
366	366	}
r14963	r14964
369	369	DN3000 DMA Page Register at 0x9200
370	370	***************************************************************************/
371	371
372		WRITE8_HANDLER(apollo_dma_page_register_w ) {
	372	WRITE8_MEMBER(apollo_state::apollo_dma_page_register_w){
373	373	dma_page_register[offset & 0x0f] = data;
374	374	SLOG1(("writing DMA Page Register at offset %02x = %02x", offset,  data));
375	375	}
376	376
377		READ8_HANDLER( apollo_dma_page_register_r ) {
	377	READ8_MEMBER(apollo_state::apollo_dma_page_register_r){
378	378	UINT8 data = dma_page_register[offset & 0x0f];
379	379	SLOG1(("reading DMA Page Register at offset %02x = %02x", offset, data));
380	380	return data;
r14963	r14964
384	384	DN3500 Address Translation Map at 0x017000
385	385	-------------------------------------------------*/
386	386
387		WRITE16_HANDLER(apollo_address_translation_map_w ) {
	387	WRITE16_MEMBER(apollo_state::apollo_address_translation_map_w){
388	388	address_translation_map[offset & 0x3ff] = data;
389	389	SLOG2(("writing Address Translation Map at offset %02x = %04x", offset, data));
390	390	}
391	391
392		READ16_HANDLER( apollo_address_translation_map_r ) {
	392	READ16_MEMBER(apollo_state::apollo_address_translation_map_r){
393	393	UINT16 data = address_translation_map[offset & 0x3ff];
394	394	SLOG2(("reading Address Translation Map at offset %02x = %04x", offset, data));
395	395	return data;
396	396	}
397	397
398		static READ8_HANDLER( apollo_dma_read_byte ) {
	398	READ8_MEMBER(apollo_state::apollo_dma_read_byte){
399	399	UINT8 data;
400	400	offs_t page_offset;
401	401
r14963	r14964
407	407	offset &= 0x3ff;
408	408	}
409	409
410		data = space->read_byte(page_offset + offset);
	410	data = space.read_byte(page_offset + offset);
411	411
412	412	if (VERBOSE > 1 || offset < 4 || (offset & 0xff) == 0 || (offset & 0xff) == 0xff)
413	413	{
r14963	r14964
417	417	return data;
418	418	}
419	419
420		static WRITE8_HANDLER( apollo_dma_write_byte ) {
	420	WRITE8_MEMBER(apollo_state::apollo_dma_write_byte){
421	421	offs_t page_offset;
422	422	if (apollo_is_dn3000()) {
423	423	page_offset = dma_page_register[channel2page_register[dn3000_dma_channel1]] << 16;
r14963	r14964
427	427	offset &= 0x3ff;
428	428	}
429	429	// FIXME: MSB not available, writing only LSB
430		space->write_byte(page_offset + offset, data);
	430	space.write_byte(page_offset + offset, data);
431	431
432	432	if (VERBOSE > 1 || offset < 4 || (offset & 0xff) == 0 || (offset & 0xff) == 0xff)
433	433	{
r14963	r14964
435	435	}
436	436	}
437	437
438		static READ8_HANDLER( apollo_dma_read_word ) {
	438	READ8_MEMBER(apollo_state::apollo_dma_read_word){
439	439	UINT16 data;
440	440	offs_t page_offset;
441	441
r14963	r14964
449	449	offset = (offset << 1) & 0x3ff;
450	450	}
451	451
452		data = space->read_byte(page_offset + offset);
	452	data = space.read_byte(page_offset + offset);
453	453
454	454	SLOG1(("dma read word at offset %x+%03x = %04x", page_offset, offset , data));
455	455	// FIXME: MSB will get lost
456	456	return data;
457	457	}
458	458
459		static WRITE8_HANDLER( apollo_dma_write_word ) {
	459	WRITE8_MEMBER(apollo_state::apollo_dma_write_word){
460	460	offs_t page_offset;
461	461
462	462	SLOG1(("dma write word at offset %x = %02x", offset, data));
r14963	r14964
473	473	offset = (offset << 1) & 0x3ff;
474	474	}
475	475
476		space->write_byte(page_offset + offset, data);
	476	space.write_byte(page_offset + offset, data);
477	477	SLOG1(("dma write word at offset %x+%03x = %02x", page_offset, offset, data));
478	478	}
479	479
r14963	r14964
556	556	{
557	557	DEVCB_LINE(apollo_dma_1_hrq_changed),
558	558	DEVCB_LINE(apollo_dma8237_out_eop),
559		DEVCB_MEMORY_HANDLER(MAINCPU, PROGRAM, apollo_dma_read_byte),
560		DEVCB_MEMORY_HANDLER(MAINCPU, PROGRAM, apollo_dma_write_byte),
	559	DEVCB_DRIVER_MEMBER(apollo_state, apollo_dma_read_byte),
	560	DEVCB_DRIVER_MEMBER(apollo_state, apollo_dma_write_byte),
561	561	{   DEVCB_NULL, DEVCB_HANDLER(apollo_dma8237_ctape_dack_r), DEVCB_HANDLER(apollo_dma8237_fdc_dack_r), DEVCB_NULL},
562	562	{   DEVCB_NULL, DEVCB_HANDLER(apollo_dma8237_ctape_dack_w), DEVCB_HANDLER(apollo_dma8237_fdc_dack_w), DEVCB_NULL},
563	563	{   DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL}
r14963	r14964
567	567	{
568	568	DEVCB_LINE(apollo_dma_2_hrq_changed),
569	569	DEVCB_NULL,
570		DEVCB_MEMORY_HANDLER(MAINCPU, PROGRAM, apollo_dma_read_word),
571		DEVCB_MEMORY_HANDLER(MAINCPU, PROGRAM, apollo_dma_write_word),
	570	DEVCB_DRIVER_MEMBER(apollo_state, apollo_dma_read_word),
	571	DEVCB_DRIVER_MEMBER(apollo_state, apollo_dma_write_word),
572	572	{   DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_HANDLER(apollo_dma8237_wdc_dack_r)},
573	573	{   DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_HANDLER(apollo_dma8237_wdc_dack_w)},
574	574	{   DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL}
r14963	r14964
799	799
800	800	static DEVICE_RESET( apollo_rtc ) {
801	801	address_space *space = device->machine().device(MAINCPU)->memory().space(AS_PROGRAM);
802		UINT8 year = apollo_rtc_r(space, 9);
	802	apollo_state *state = device->machine().driver_data<apollo_state>();
	803	UINT8 year = state->apollo_rtc_r(*space, 9);
803	804
804	805	// change year according to configuration settings
805	806	if (year < 20 && apollo_config(APOLLO_CONF_DATE_1990))
806	807	{
807	808	year+=80;
808		apollo_rtc_w(space, 9, year);
	809	state->apollo_rtc_w(*space, 9, year);
809	810	}
810	811	else if (year >= 80 && !apollo_config(APOLLO_CONF_DATE_1990))
811	812	{
812	813	year -=80;
813		apollo_rtc_w(space, 9, year);
	814	state->apollo_rtc_w(*space, 9, year);
814	815	}
815	816
816		SLOG1(("reset apollo_rtc year=%d", year));
	817	//SLOG1(("reset apollo_rtc year=%d", year));
817	818	}
818	819
819		WRITE8_HANDLER( apollo_rtc_w )
	820	WRITE8_MEMBER(apollo_state::apollo_rtc_w)
820	821	{
821		mc146818_device *rtc = space->machine().device<mc146818_device> (APOLLO_RTC_TAG);
822		rtc->write(*space, 0, offset);
823		rtc->write(*space, 1, data);
	822	mc146818_device *rtc = machine().device<mc146818_device> (APOLLO_RTC_TAG);
	823	rtc->write(space, 0, offset);
	824	rtc->write(space, 1, data);
824	825	if (offset >= 0x0b && offset <= 0x0c)
825	826	{
826	827	SLOG2(("writing MC146818 at offset %02x = %02x", offset, data));
827	828	}
828	829	}
829	830
830		READ8_HANDLER( apollo_rtc_r )
	831	READ8_MEMBER(apollo_state::apollo_rtc_r)
831	832	{
832	833	UINT8 data;
833		mc146818_device *rtc = space->machine().device<mc146818_device> (APOLLO_RTC_TAG);
834		rtc->write(*space, 0, offset);
835		data = rtc->read(*space, 1);
	834	mc146818_device *rtc = machine().device<mc146818_device> (APOLLO_RTC_TAG);
	835	rtc->write(space, 0, offset);
	836	data = rtc->read(space, 1);
836	837	if (offset >= 0x0b && offset <= 0x0c)
837	838	{
838	839	SLOG2(("reading MC146818 at offset %02x = %02x", offset, data));
r14963	r14964
842	843
843	844	static TIMER_CALLBACK( apollo_rtc_timer )
844	845	{
	846	apollo_state *state = machine.driver_data<apollo_state>();
845	847	address_space *space = machine.device(MAINCPU)->memory().space(AS_PROGRAM);
846	848
847	849	// FIXME: reading register 0x0c will clear all interrupt flags
848		if ((apollo_rtc_r(space, 0x0c) & 0x80))
	850	if ((state->apollo_rtc_r(*space, 0x0c) & 0x80))
849	851	{
850		SLOG2(("apollo_rtc_timer - set_irq_line %d", APOLLO_IRQ_RTC));
	852	//SLOG2(("apollo_rtc_timer - set_irq_line %d", APOLLO_IRQ_RTC));
851	853	apollo_pic_set_irq_line(&space->device(), APOLLO_IRQ_RTC, 1);
852	854	}
853	855	}
r14963	r14964
1311	1313	//  upd765_hack_for_apollo();
1312	1314	}
1313	1315
1314		WRITE8_HANDLER(apollo_fdc_w ) {
	1316	WRITE8_MEMBER(apollo_state::apollo_fdc_w){
1315	1317	SLOG1(("writing FDC upd765 at offset %X = %02x", offset, data));
1316		pc_fdc_w(space, offset, data);
	1318	pc_fdc_w(&space, offset, data);
1317	1319	}
1318	1320
1319		READ8_HANDLER( apollo_fdc_r ) {
1320		UINT8 data = pc_fdc_r(space, offset);
	1321	READ8_MEMBER(apollo_state::apollo_fdc_r){
	1322	UINT8 data = pc_fdc_r(&space, offset);
1321	1323	SLOG1(("reading FDC upd765 at offset %X = %02x", offset, data));
1322	1324	return data;
1323	1325	}

src/mess/machine/ondra.c

r14963	r14964
20	20	}
21	21
22	22
23		static READ8_HANDLER( ondra_keyboard_r )
	23	READ8_MEMBER(ondra_state::ondra_keyboard_r)
24	24	{
25	25	UINT8 retVal = 0x00;
26	26	UINT8 ondra_keyboard_line = offset & 0x000f;
27	27	static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7", "LINE8", "LINE9" };
28		double valcas = (cassette_device_image(space->machine())->input());
	28	double valcas = (cassette_device_image(machine())->input());
29	29	if ( valcas < 0.00) {
30	30	retVal = 0x80;
31	31	}
32	32	if (ondra_keyboard_line > 9) {
33	33	retVal |= 0x1f;
34	34	} else {
35		retVal |= input_port_read(space->machine(), keynames[ondra_keyboard_line]);
	35	retVal |= input_port_read(machine(), keynames[ondra_keyboard_line]);
36	36	}
37	37	return retVal;
38	38	}
r14963	r14964
54	54	memory_set_bankptr(machine, "bank3", machine.device<ram_device>(RAM_TAG)->pointer() + 0xe000);
55	55	} else {
56	56	machine.device("maincpu")->memory().space(AS_PROGRAM)->unmap_write(0xe000, 0xffff);
57		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler (0xe000, 0xffff, FUNC(ondra_keyboard_r));
	57	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler (0xe000, 0xffff, read8_delegate(FUNC(ondra_state::ondra_keyboard_r),state));
58	58	}
59	59	}
60	60
61		WRITE8_HANDLER( ondra_port_03_w )
	61	WRITE8_MEMBER(ondra_state::ondra_port_03_w)
62	62	{
63		ondra_state *state = space->machine().driver_data<ondra_state>();
64		state->m_video_enable = data & 1;
65		state->m_bank1_status = (data >> 1) & 1;
66		state->m_bank2_status = (data >> 2) & 1;
67		ondra_update_banks(space->machine());
68		cassette_device_image(space->machine())->output(((data >> 3) & 1) ? -1.0 : +1.0);
	63	m_video_enable = data & 1;
	64	m_bank1_status = (data >> 1) & 1;
	65	m_bank2_status = (data >> 2) & 1;
	66	ondra_update_banks(machine());
	67	cassette_device_image(machine())->output(((data >> 3) & 1) ? -1.0 : +1.0);
69	68	}
70	69
71		WRITE8_HANDLER( ondra_port_09_w )
	70	WRITE8_MEMBER(ondra_state::ondra_port_09_w)
72	71	{
73	72	}
74	73
75		WRITE8_HANDLER( ondra_port_0a_w )
	74	WRITE8_MEMBER(ondra_state::ondra_port_0a_w)
76	75	{
77	76	}
78	77

src/mess/machine/partner.c

r14963	r14964
80	80	}
81	81	}
82	82
83		static READ8_HANDLER ( partner_floppy_r ) {
84		device_t *fdc = space->machine().device("wd1793");
	83	READ8_MEMBER(partner_state::partner_floppy_r){
	84	device_t *fdc = machine().device("wd1793");
85	85
86	86	if (offset<0x100) {
87	87	switch(offset & 3) {
r14963	r14964
96	96	}
97	97	}
98	98
99		static WRITE8_HANDLER ( partner_floppy_w ) {
100		device_t *fdc = space->machine().device("wd1793");
	99	WRITE8_MEMBER(partner_state::partner_floppy_w){
	100	device_t *fdc = machine().device("wd1793");
101	101
102	102	if (offset<0x100) {
103	103	switch(offset & 3) {
r14963	r14964
107	107	default   : wd17xx_data_w(fdc,0,data);break;
108	108	}
109	109	} else {
110		floppy_mon_w(floppy_get_device(space->machine(), 0), 1);
111		floppy_mon_w(floppy_get_device(space->machine(), 1), 1);
	110	floppy_mon_w(floppy_get_device(machine(), 0), 1);
	111	floppy_mon_w(floppy_get_device(machine(), 1), 1);
112	112	if (((data >> 6) & 1)==1) {
113	113	wd17xx_set_drive(fdc,0);
114		floppy_mon_w(floppy_get_device(space->machine(), 0), 0);
115		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), 1, 1);
	114	floppy_mon_w(floppy_get_device(machine(), 0), 0);
	115	floppy_drive_set_ready_state(floppy_get_device(machine(), 0), 1, 1);
116	116	}
117	117	if (((data >> 3) & 1)==1) {
118	118	wd17xx_set_drive(fdc,1);
119		floppy_mon_w(floppy_get_device(space->machine(), 1), 0);
120		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), 1, 1);
	119	floppy_mon_w(floppy_get_device(machine(), 1), 0);
	120	floppy_drive_set_ready_state(floppy_get_device(machine(), 1), 1, 1);
121	121	}
122	122	wd17xx_set_side(fdc,data >> 7);
123	123	}
r14963	r14964
130	130	switch(state->m_win_mem_page) {
131	131	case 2 :
132	132	// FDD
133		space->install_legacy_write_handler(0xdc00, 0xddff, FUNC(partner_floppy_w));
134		space->install_legacy_read_handler (0xdc00, 0xddff, FUNC(partner_floppy_r));
	133	space->install_write_handler(0xdc00, 0xddff, write8_delegate(FUNC(partner_state::partner_floppy_w),state));
	134	space->install_read_handler (0xdc00, 0xddff, read8_delegate(FUNC(partner_state::partner_floppy_r),state));
135	135	break;
136	136	case 4 :
137	137	// Timer
r14963	r14964
346	346	}
347	347	}
348	348
349		WRITE8_HANDLER ( partner_win_memory_page_w )
	349	WRITE8_MEMBER(partner_state::partner_win_memory_page_w)
350	350	{
351		partner_state *state = space->machine().driver_data<partner_state>();
352		state->m_win_mem_page = ~data;
353		partner_bank_switch(space->machine());
	351	m_win_mem_page = ~data;
	352	partner_bank_switch(machine());
354	353	}
355	354
356		WRITE8_HANDLER (partner_mem_page_w )
	355	WRITE8_MEMBER(partner_state::partner_mem_page_w)
357	356	{
358		partner_state *state = space->machine().driver_data<partner_state>();
359		state->m_mem_page = (data >> 4) & 0x0f;
360		partner_bank_switch(space->machine());
	357	m_mem_page = (data >> 4) & 0x0f;
	358	partner_bank_switch(machine());
361	359	}
362	360
363	361	static WRITE_LINE_DEVICE_HANDLER( hrq_w )

src/mess/machine/hec2hrp.c

r14963	r14964
122	122
123	123	}
124	124
125		READ8_HANDLER( hector_179x_register_r)
	125	READ8_MEMBER(hec2hrp_state::hector_179x_register_r)
126	126	{
127	127	int data=0;
128		device_t *fdc = space->machine().device("wd179x");
	128	device_t *fdc = machine().device("wd179x");
129	129
130	130	switch (offset & 0x0ff)
131	131	{
r14963	r14964
148	148
149	149	return data;
150	150	}
151		WRITE8_HANDLER( hector_179x_register_w)
	151	WRITE8_MEMBER(hec2hrp_state::hector_179x_register_w)
152	152	{
153		device_t *fdc = space->machine().device("wd179x");
	153	device_t *fdc = machine().device("wd179x");
154	154	switch (offset)
155	155	{
156	156	/* minidisc floppy disc interface */
r14963	r14964
171	171	/*General purpose port (0x08) for the minidisk I/O */
172	172	{
173	173	// Rom page bank switching
174		memory_set_bank(space->machine(), "bank2",BIT(data, 5) ? HECTOR_BANK_BASE : HECTOR_BANK_DISC );
	174	memory_set_bank(machine(), "bank2",BIT(data, 5) ? HECTOR_BANK_BASE : HECTOR_BANK_DISC );
175	175
176	176	// Set drive number
177	177	if (BIT(data, 6)) wd17xx_set_drive(fdc, 0);  // Set the correct drive number 0
r14963	r14964
186	186	break;
187	187	}
188	188	}
189		WRITE8_HANDLER( hector_switch_bank_w )
	189	WRITE8_MEMBER(hec2hrp_state::hector_switch_bank_w)
190	190	{
191		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
192	191	if (offset==0x00)   {   /* 0x800 et 0x000=> video page, HR*/
193		if (isHectoreXtend(space->machine()))
194		memory_set_bank(space->machine(), "bank1", HECTOR_BANK_VIDEO);
195		if (state->m_flag_clk ==1)
	192	if (isHectoreXtend(machine()))
	193	memory_set_bank(machine(), "bank1", HECTOR_BANK_VIDEO);
	194	if (m_flag_clk ==1)
196	195	{
197		state->m_flag_clk=0;
198		space->machine().device("maincpu")->set_unscaled_clock(XTAL_5MHz);  /* increase CPU*/
	196	m_flag_clk=0;
	197	machine().device("maincpu")->set_unscaled_clock(XTAL_5MHz);  /* increase CPU*/
199	198	}
200	199	}
201	200	if (offset==0x04)   {   /* 0x804 => video page, BR*/
202		state->m_hector_flag_hr=0;
203		if (isHectoreXtend(space->machine()))
204		memory_set_bank(space->machine(), "bank1", HECTOR_BANK_VIDEO);
205		if (state->m_flag_clk ==0)
	201	m_hector_flag_hr=0;
	202	if (isHectoreXtend(machine()))
	203	memory_set_bank(machine(), "bank1", HECTOR_BANK_VIDEO);
	204	if (m_flag_clk ==0)
206	205	{
207		state->m_flag_clk=1;
208		space->machine().device("maincpu")->set_unscaled_clock(XTAL_1_75MHz);  /* slowdown CPU*/
	206	m_flag_clk=1;
	207	machine().device("maincpu")->set_unscaled_clock(XTAL_1_75MHz);  /* slowdown CPU*/
209	208	}
210	209	}
211	210	if (offset==0x08)   {   /* 0x808 => base page, HR*/
212		if (isHectoreXtend(space->machine()))
213		memory_set_bank(space->machine(), "bank1", HECTOR_BANK_PROG);
214		if (state->m_flag_clk ==1)
	211	if (isHectoreXtend(machine()))
	212	memory_set_bank(machine(), "bank1", HECTOR_BANK_PROG);
	213	if (m_flag_clk ==1)
215	214	{
216		state->m_flag_clk=0;
217		space->machine().device("maincpu")->set_unscaled_clock(XTAL_5MHz);  /* increase CPU*/
	215	m_flag_clk=0;
	216	machine().device("maincpu")->set_unscaled_clock(XTAL_5MHz);  /* increase CPU*/
218	217	}
219	218
220	219	}
221	220	if (offset==0x0c)   {   /* 0x80c => base page, BR*/
222		state->m_hector_flag_hr=0;
223		if (isHectoreXtend(space->machine()))
224		memory_set_bank(space->machine(), "bank1", HECTOR_BANK_PROG);
225		if (state->m_flag_clk ==0)
	221	m_hector_flag_hr=0;
	222	if (isHectoreXtend(machine()))
	223	memory_set_bank(machine(), "bank1", HECTOR_BANK_PROG);
	224	if (m_flag_clk ==0)
226	225	{
227		state->m_flag_clk=1;
228		space->machine().device("maincpu")->set_unscaled_clock(XTAL_1_75MHz);  /* slowdown CPU*/
	226	m_flag_clk=1;
	227	machine().device("maincpu")->set_unscaled_clock(XTAL_1_75MHz);  /* slowdown CPU*/
229	228	}
230	229	}
231	230	}
232	231
233		WRITE8_HANDLER( hector_keyboard_w )
	232	WRITE8_MEMBER(hec2hrp_state::hector_keyboard_w)
234	233	{
235	234	/*nothing to do => read function manage the value*/
236	235	}
237	236
238		READ8_HANDLER( hector_keyboard_r )
	237	READ8_MEMBER(hec2hrp_state::hector_keyboard_r)
239	238	{
240		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
241	239	UINT8 data = 0xff;
242		running_machine &machine = space->machine();
243
244	240	static const char *const keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4", "KEY5", "KEY6", "KEY7", "KEY8" };
245	241
246	242	if (offset ==7) /* Only when joy reading*/
247	243	{
248	244	/* Read special key for analog joystick emulation only (button and pot are analog signal!) and the reset */
249		data=input_port_read(machine, keynames[8]);
	245	data=input_port_read(machine(), keynames[8]);
250	246
251	247	if (data & 0x01) /* Reset machine ! (on ESC key)*/
252	248	{
253		cputag_set_input_line(machine, "maincpu", INPUT_LINE_RESET, PULSE_LINE);
254		if (isHectorHR(machine)) /* aviable for HR and up */
	249	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE);
	250	if (isHectorHR(machine())) /* aviable for HR and up */
255	251	{
256		state->m_hector_flag_hr=1;
257		if (isHectoreXtend(machine))
	252	m_hector_flag_hr=1;
	253	if (isHectoreXtend(machine()))
258	254	{
259		memory_set_bank(machine, "bank1", HECTOR_BANK_PROG);
260		memory_set_bank(machine, "bank2", HECTORMX_BANK_PAGE0);
	255	memory_set_bank(machine(), "bank1", HECTOR_BANK_PROG);
	256	memory_set_bank(machine(), "bank2", HECTORMX_BANK_PAGE0);
261	257	}
262	258	//RESET DISC II unit
263		if (isHectorWithDisc2(machine) )
264		hector_disc2_reset(machine);
	259	if (isHectorWithDisc2(machine()) )
	260	hector_disc2_reset(machine());
265	261
266	262	/* floppy md master reset */
267		if (isHectorWithMiniDisc(machine))
268		wd17xx_mr_w(machine.device("wd179x"), 1);
	263	if (isHectorWithMiniDisc(machine()))
	264	wd17xx_mr_w(machine().device("wd179x"), 1);
269	265
270	266	}
271	267
272	268	else /* aviable for BR machines */
273		state->m_hector_flag_hr=0;
	269	m_hector_flag_hr=0;
274	270
275	271
276	272	/*Common flag*/
277		state->m_hector_flag_80c = 0;
278		state->m_flag_clk = 0;
	273	m_hector_flag_80c = 0;
	274	m_flag_clk = 0;
279	275	}
280	276
281		state->m_actions = 0;
	277	m_actions = 0;
282	278	if (data & 0x02) /* Fire(0)*/
283		state->m_actions += 1;
	279	m_actions += 1;
284	280
285	281	if (data & 0x04) /* Fire(1)*/
286		state->m_actions += 2;
	282	m_actions += 2;
287	283
288	284	if (data & 0x08) /* Pot(0)+*/
289		state->m_pot0 += 1;
290		if (state->m_pot0>128) state->m_pot0 = 128;
	285	m_pot0 += 1;
	286	if (m_pot0>128) m_pot0 = 128;
291	287
292	288	if (data & 0x10) /* Pot(0)-*/
293		state->m_pot0 -= 1;
	289	m_pot0 -= 1;
294	290
295		if (state->m_pot0>250) state->m_pot0 = 0;
	291	if (m_pot0>250) m_pot0 = 0;
296	292
297	293	if (data & 0x20) /* Pot(1)+*/
298		state->m_pot1 += 1;
299		if (state->m_pot1>128) state->m_pot1 = 128;
	294	m_pot1 += 1;
	295	if (m_pot1>128) m_pot1 = 128;
300	296
301	297	if (data & 0x40) /* Pot(1)-*/
302		state->m_pot1 -= 1;
	298	m_pot1 -= 1;
303	299
304		if (state->m_pot1>250) state->m_pot1 = 0;
	300	if (m_pot1>250) m_pot1 = 0;
305	301	}
306	302
307	303	/* in all case return the request value*/
308		return input_port_read(space->machine(), keynames[offset]);
	304	return input_port_read(machine(), keynames[offset]);
309	305	}
310	306
311		WRITE8_HANDLER( hector_sn_2000_w )
	307	WRITE8_MEMBER(hec2hrp_state::hector_sn_2000_w)
312	308	{
313		Mise_A_Jour_Etat(space->machine(), 0x2000+ offset, data);
314		Update_Sound(space, data);
	309	Mise_A_Jour_Etat(machine(), 0x2000+ offset, data);
	310	Update_Sound(&space, data);
315	311	}
316		WRITE8_HANDLER( hector_sn_2800_w )
	312	WRITE8_MEMBER(hec2hrp_state::hector_sn_2800_w)
317	313	{
318		Mise_A_Jour_Etat(space->machine(), 0x2800+ offset, data);
319		Update_Sound(space, data);
	314	Mise_A_Jour_Etat(machine(), 0x2800+ offset, data);
	315	Update_Sound(&space, data);
320	316	}
321		READ8_HANDLER( hector_cassette_r )
	317	READ8_MEMBER(hec2hrp_state::hector_cassette_r)
322	318	{
323		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
324	319	double level;
325	320	UINT8 value=0;
326	321
327		if ((state->m_state3000 & 0x38) != 0x38 )   /* Selon Sb choix cassette ou timer (74153)*/
	322	if ((m_state3000 & 0x38) != 0x38 )   /* Selon Sb choix cassette ou timer (74153)*/
328	323	{
329		state->m_Data_K7 =  0x00;  /* No cassette => clear bit*/
330		switch (state->m_state3000 & 0x38 )
	324	m_Data_K7 =  0x00;  /* No cassette => clear bit*/
	325	switch (m_state3000 & 0x38 )
331	326	{
332		case 0x08: value = (state->m_actions & 1) ? 0x80 : 0; break;
333		case 0x10: value = state->m_pot0; break;
334		case 0x20: value = (state->m_actions & 2) ? 0x80 : 0; break;
335		case 0x28: value = state->m_pot1; break;
	327	case 0x08: value = (m_actions & 1) ? 0x80 : 0; break;
	328	case 0x10: value = m_pot0; break;
	329	case 0x20: value = (m_actions & 2) ? 0x80 : 0; break;
	330	case 0x28: value = m_pot1; break;
336	331	default: value = 0; break;
337	332	}
338	333	}
339	334	else
340	335	{
341		if (state->m_write_cassette == 0)
	336	if (m_write_cassette == 0)
342	337	{
343	338	/* Accee a la cassette*/
344		level = (cassette_device_image(space->machine())->input());
	339	level = (cassette_device_image(machine())->input());
345	340
346	341	/* Travail du 741 en trigger*/
347	342	if  (level < -0.08)
348		state->m_cassette_bit = 0x00;
	343	m_cassette_bit = 0x00;
349	344	if (level > +0.08)
350		state->m_cassette_bit = 0x01;
	345	m_cassette_bit = 0x01;
351	346	}
352		/* Programme du sn7474 (bascule) : Changement ??tat bit Data K7 ?? chaque front montant de state->m_cassette_bit*/
353		if ((state->m_cassette_bit != state->m_cassette_bit_mem) && (state->m_cassette_bit !=0))
	347	/* Programme du sn7474 (bascule) : Changement ??tat bit Data K7 ?? chaque front montant de m_cassette_bit*/
	348	if ((m_cassette_bit != m_cassette_bit_mem) && (m_cassette_bit !=0))
354	349	{
355		if (state->m_Data_K7 == 0x00)
356		state->m_Data_K7 =  0x80;/* En poids fort*/
	350	if (m_Data_K7 == 0x00)
	351	m_Data_K7 =  0x80;/* En poids fort*/
357	352	else
358		state->m_Data_K7 =  0x00;
	353	m_Data_K7 =  0x00;
359	354	}
360		value = ( state->m_CK_signal & 0x7F ) + state->m_Data_K7;
361		state->m_cassette_bit_mem = state->m_cassette_bit;  /* Memorisation etat bit cassette*/
	355	value = ( m_CK_signal & 0x7F ) + m_Data_K7;
	356	m_cassette_bit_mem = m_cassette_bit;  /* Memorisation etat bit cassette*/
362	357	}
363	358	return value;
364	359	}
365		WRITE8_HANDLER( hector_sn_3000_w )
	360	WRITE8_MEMBER(hec2hrp_state::hector_sn_3000_w)
366	361	{
367		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
368		state->m_state3000 = data & 0xf8; /* except bit 0 to 2*/
369		if ((data & 7) != state->m_oldstate3000 )
	362	m_state3000 = data & 0xf8; /* except bit 0 to 2*/
	363	if ((data & 7) != m_oldstate3000 )
370	364	{
371	365	/* Update sn76477 only when necessary!*/
372		Mise_A_Jour_Etat( space->machine(), 0x3000, data & 7 );
373		Update_Sound(space, data & 7);
	366	Mise_A_Jour_Etat( machine(), 0x3000, data & 7 );
	367	Update_Sound(&space, data & 7);
374	368	}
375		state->m_oldstate3000 = data & 7;
	369	m_oldstate3000 = data & 7;
376	370	}
377	371
378	372	/* Color Interface */
379		WRITE8_HANDLER( hector_color_a_w )
	373	WRITE8_MEMBER(hec2hrp_state::hector_color_a_w)
380	374	{
381		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
382	375
383	376	if (data & 0x40)
384	377	{
385	378	/* Bit 6 => motor ON/OFF => for cassette state!*/
386		if (state->m_write_cassette==0)
	379	if (m_write_cassette==0)
387	380	{
388		cassette_device_image(space->machine())->change_state(
	381	cassette_device_image(machine())->change_state(
389	382	CASSETTE_MOTOR_ENABLED ,
390	383	CASSETTE_MASK_MOTOR);
391		// cassette_device_image(space->machine())->set_state((cassette_state)(CASSETTE_PLAY | CASSETTE_SPEAKER_ENABLED | CASSETTE_MOTOR_ENABLED ));
	384	// cassette_device_image(machine())->set_state((cassette_state)(CASSETTE_PLAY | CASSETTE_SPEAKER_ENABLED | CASSETTE_MOTOR_ENABLED ));
392	385	}
393	386	}
394	387	else
395	388	{   /* stop motor*/
396		cassette_device_image(space->machine())->set_state(CASSETTE_STOPPED);
397		state->m_write_cassette=0;
398		state->m_counter_write =0;
	389	cassette_device_image(machine())->set_state(CASSETTE_STOPPED);
	390	m_write_cassette=0;
	391	m_counter_write =0;
399	392	}
400		if (((data & 0x80) != (state->m_oldstate1000 & 0x80)) && ((state->m_oldstate1000 & 7)==(data & 7)) ) /* Bit7 had change but not the color statement*/
	393	if (((data & 0x80) != (m_oldstate1000 & 0x80)) && ((m_oldstate1000 & 7)==(data & 7)) ) /* Bit7 had change but not the color statement*/
401	394	{
402	395	/* Bit 7 => Write bit for cassette!*/
403		state->m_counter_write +=1;
	396	m_counter_write +=1;
404	397
405		if (state->m_counter_write > 5)
	398	if (m_counter_write > 5)
406	399	{
407	400	/* Wait several cycle before lauch the record to prevent somes bugs*/
408		state->m_counter_write = 6;
409		if (state->m_write_cassette==0)
	401	m_counter_write = 6;
	402	if (m_write_cassette==0)
410	403	{   /* C'est la 1er fois => record*/
411		cassette_device_image(space->machine())->change_state(
	404	cassette_device_image(machine())->change_state(
412	405	CASSETTE_MOTOR_ENABLED ,
413	406	CASSETTE_MASK_MOTOR);
414		cassette_device_image(space->machine())->set_state(CASSETTE_RECORD);
415		state->m_write_cassette=1;
	407	cassette_device_image(machine())->set_state(CASSETTE_RECORD);
	408	m_write_cassette=1;
416	409	}
417	410	}
418	411	/* cassette data */
419		cassette_device_image(space->machine())->output(((data & 0x80) == 0x80) ? -1.0 : +1.0);
	412	cassette_device_image(machine())->output(((data & 0x80) == 0x80) ? -1.0 : +1.0);
420	413	}
421	414
422	415	/* Other bit : color definition*/
423		state->m_hector_color[0] =  data        & 0x07 ;
424		state->m_hector_color[2] = ((data >> 3)  & 0x07) | (state->m_hector_color[2] & 0x40);
	416	m_hector_color[0] =  data        & 0x07 ;
	417	m_hector_color[2] = ((data >> 3)  & 0x07) | (m_hector_color[2] & 0x40);
425	418
426		state->m_oldstate1000=data; /* For next step*/
	419	m_oldstate1000=data; /* For next step*/
427	420	}
428	421
429		WRITE8_HANDLER( hector_color_b_w )
	422	WRITE8_MEMBER(hec2hrp_state::hector_color_b_w)
430	423	{
431		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
432		device_t *discrete = space->machine().device("discrete");
433		state->m_hector_color[1] =  data        & 0x07;
434		state->m_hector_color[3] = (data >> 3)  & 0x07;
	424	device_t *discrete = machine().device("discrete");
	425	m_hector_color[1] =  data        & 0x07;
	426	m_hector_color[3] = (data >> 3)  & 0x07;
435	427
436	428	/* Half light on color 2 only on HR machines:*/
437		if (data & 0x40) state->m_hector_color[2] |= 8; else state->m_hector_color[2] &= 7;
	429	if (data & 0x40) m_hector_color[2] |= 8; else m_hector_color[2] &= 7;
438	430
439	431	/* Play bit*/
440	432	discrete_sound_w(discrete, NODE_01,  (data & 0x80) ? 0:1 );
r14963	r14964
456	448	********************************************************************************/
457	449
458	450	/*******************  READ PIO 8255 *******************/
459		READ8_HANDLER( hector_io_8255_r)
	451	READ8_MEMBER(hec2hrp_state::hector_io_8255_r)
460	452	{
461		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
462	453
463	454	/* 8255 in mode 0 */
464	455	UINT8 data =0;
r14963	r14964
467	458
468	459
469	460	if ((offset & 0x3) == 0x0) /* Port A */
470		data = state->m_hector_port_a;
	461	data = m_hector_port_a;
471	462
472	463	if ((offset & 0x3) == 0x1) /* Port B */
473	464	{
474		data = state->m_hector_port_b;
	465	data = m_hector_port_b;
475	466	#ifdef DEBUG_TRACE_COM_HECTOR
476	467	printf("\nLecture data par Hector %x (portB)",data);
477	468	#endif
r14963	r14964
479	470
480	471	if ((offset & 0x3) == 0x2) /* Port C */
481	472	{
482		data_l = (state->m_hector_port_c_l & 0x0f);
483		data_h = (state->m_hector_port_c_h & 0xf0);
	473	data_l = (m_hector_port_c_l & 0x0f);
	474	data_h = (m_hector_port_c_h & 0xf0);
484	475
485		if (BIT(state->m_hector_port_cmd, 0))               /* Quartet inf en entree ?*/
486		data_l = (state->m_hector_port_c_l & 0x0f);  /*no change*/
	476	if (BIT(m_hector_port_cmd, 0))               /* Quartet inf en entree ?*/
	477	data_l = (m_hector_port_c_l & 0x0f);  /*no change*/
487	478
488		if (BIT(state->m_hector_port_cmd, 3))               /* Quartet sup en entree ?*/
	479	if (BIT(m_hector_port_cmd, 3))               /* Quartet sup en entree ?*/
489	480	{
490		state->m_hector_port_c_h = (state->m_hector_port_c_h & 0x0c0);   /* Clear bits 4 & 5*/
	481	m_hector_port_c_h = (m_hector_port_c_h & 0x0c0);   /* Clear bits 4 & 5*/
491	482
492		if (state->m_hector_disc2_data_w_ready != 0x00)
493		state->m_hector_port_c_h = state->m_hector_port_c_h + 0x010;   // PC4 (data write ready from Disc II to Hector)
	483	if (m_hector_disc2_data_w_ready != 0x00)
	484	m_hector_port_c_h = m_hector_port_c_h + 0x010;   // PC4 (data write ready from Disc II to Hector)
494	485
495		if (state->m_hector_disc2_data_r_ready != 0x00)
496		state->m_hector_port_c_h = state->m_hector_port_c_h + 0x020;   // PC5 (data read ready from Hector to Disc2)
	486	if (m_hector_disc2_data_r_ready != 0x00)
	487	m_hector_port_c_h = m_hector_port_c_h + 0x020;   // PC5 (data read ready from Hector to Disc2)
497	488
498		state->m_hector_port_c_h = state->m_hector_port_c_h & 0x07F;      // PC7 (printer busy=0)
499		data_h =  state->m_hector_port_c_h;
	489	m_hector_port_c_h = m_hector_port_c_h & 0x07F;      // PC7 (printer busy=0)
	490	data_h =  m_hector_port_c_h;
500	491	}
501	492	data= data_l + data_h;
502	493	}
r14963	r14964
505	496
506	497	/*******************  WRITE PIO 8255 *******************/
507	498
508		WRITE8_HANDLER( hector_io_8255_w)
	499	WRITE8_MEMBER(hec2hrp_state::hector_io_8255_w)
509	500	{
510		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
511	501	/* 8255 in mode 0 */
512	502	if ((offset & 0x3) == 0x0) /* Port A => to printer or Disc II*/
513	503	{
514		state->m_hector_port_a = data;
	504	m_hector_port_a = data;
515	505	/* Port A => to printer*/
516	506	/*  Caution : The strobe connection to the printer seems not be used
517	507	So, all what is send to the Disc2 unit will be printed too! */
518	508
519		if (BIT(state->m_hector_port_c_l, 0)) {      // PC0 (bit X0)= strobe printer !
520		printer_image_device *printer = space->machine().device<printer_image_device>("printer");
521		printer->output(state->m_hector_port_a);
	509	if (BIT(m_hector_port_c_l, 0)) {      // PC0 (bit X0)= strobe printer !
	510	printer_image_device *printer = machine().device<printer_image_device>("printer");
	511	printer->output(m_hector_port_a);
522	512	}
523	513
524	514	#ifdef DEBUG_TRACE_COM_HECTOR
r14963	r14964
527	517	}
528	518
529	519	if ((offset & 0x3) == 0x1) /* Port B */
530		state->m_hector_port_b = data;
	520	m_hector_port_b = data;
531	521
532	522
533	523	if ((offset & 0x3) == 0x2) /* Port C => depending cmd word */
534	524	{
535		if (!BIT(state->m_hector_port_cmd, 0))    /* cmd -> Quartet inf en sortie ?*/
	525	if (!BIT(m_hector_port_cmd, 0))    /* cmd -> Quartet inf en sortie ?*/
536	526	{
537		state->m_hector_port_c_l = data & 0x0f;
	527	m_hector_port_c_l = data & 0x0f;
538	528	// Utilizing bits port C : PC0 for the printer : strobe!
539		if (BIT(state->m_hector_port_c_l  , 0))      // PC0 (bit X0)= true
	529	if (BIT(m_hector_port_c_l  , 0))      // PC0 (bit X0)= true
540	530	{
541	531	/* Port A => to printer*/
542		//printer_output(space->machine().device("printer"), state->m_hector_port_a);
	532	//printer_output(machine().device("printer"), m_hector_port_a);
543	533	}
544	534	// Utilizing bits port C : PC1 // PC2  for the communication with disc2
545		if (!BIT(state->m_hector_port_c_l  , 1))      // PC1 (bit X1)= true
	535	if (!BIT(m_hector_port_c_l  , 1))      // PC1 (bit X1)= true
546	536	{
547		// Lecture effectuee => RAZ memoire donnee state->m_hector_disc2_data_write dispo
548		state->m_hector_port_b = state->m_hector_disc2_data_write; // Mep sur port B si 2eme 74374 existant !
549		state->m_hector_disc2_data_w_ready = 0x00;
	537	// Lecture effectuee => RAZ memoire donnee m_hector_disc2_data_write dispo
	538	m_hector_port_b = m_hector_disc2_data_write; // Mep sur port B si 2eme 74374 existant !
	539	m_hector_disc2_data_w_ready = 0x00;
550	540	#ifdef DEBUG_TRACE_COM_HECTOR
551		printf("\nEcriture port B vers state->m_hector_disc2_data_write suite a PC1");
	541	printf("\nEcriture port B vers m_hector_disc2_data_write suite a PC1");
552	542	#endif
553	543	}
554		if (!BIT(state->m_hector_port_c_l, 2))      // PC2 (bit X2)= true
	544	if (!BIT(m_hector_port_c_l, 2))      // PC2 (bit X2)= true
555	545	{
556		state->m_hector_disc2_data_read = state->m_hector_port_a; /* mise en place de l'info presente sur le port A */
557		state->m_hector_disc2_data_r_ready = 0x08;       /* memorisation de l'info */
	546	m_hector_disc2_data_read = m_hector_port_a; /* mise en place de l'info presente sur le port A */
	547	m_hector_disc2_data_r_ready = 0x08;       /* memorisation de l'info */
558	548	#ifdef DEBUG_TRACE_COM_HECTOR
559		printf("\nEcriture port A pour state->m_hector_disc2_data_read suite a PC2");
	549	printf("\nEcriture port A pour m_hector_disc2_data_read suite a PC2");
560	550	#endif
561	551	}
562	552	}
563		if (!BIT(state->m_hector_port_cmd, 3))    /* cmd -> Quartet sup en sortie ?*/
564		state->m_hector_port_c_h = (data & 0xf0);
	553	if (!BIT(m_hector_port_cmd, 3))    /* cmd -> Quartet sup en sortie ?*/
	554	m_hector_port_c_h = (data & 0xf0);
565	555	}
566	556
567	557	if ((offset & 0x3) == 0x3) /* Port commande */
568	558	{
569		state->m_hector_port_cmd = data;
	559	m_hector_port_cmd = data;
570	560	}
571	561	}
572	562	/* End of 8255 managing */
573	563
574	564
575	565	/*******************  Ecriture PIO specifique machine MX40 *******************/
576		WRITE8_HANDLER( hector_mx40_io_port_w)
	566	WRITE8_MEMBER(hec2hrp_state::hector_mx40_io_port_w)
577	567	{
578		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
579	568	/* Bank switching on several address */
580	569	if ((offset &0x0ff) == 0x40) /* Port page 0*/
581		memory_set_bank(space->machine(), "bank2", HECTORMX_BANK_PAGE0);
	570	memory_set_bank(machine(), "bank2", HECTORMX_BANK_PAGE0);
582	571	if ((offset &0x0ff) == 0x41) /* Port page 1*/
583	572	{
584		memory_set_bank(space->machine(), "bank2", HECTORMX_BANK_PAGE1);
585		state->m_hector_flag_80c=0;
	573	memory_set_bank(machine(), "bank2", HECTORMX_BANK_PAGE1);
	574	m_hector_flag_80c=0;
586	575	}
587	576	if ((offset &0x0ff) == 0x44) /* Port page 2  => 42 pour MX80*/
588		memory_set_bank(space->machine(), "bank2", HECTORMX_BANK_PAGE2);
	577	memory_set_bank(machine(), "bank2", HECTORMX_BANK_PAGE2);
589	578	if ((offset &0x0ff) == 0x49) /* Port screen resolution*/
590		state->m_hector_flag_80c=0;/* No 80c in 40c !*/
	579	m_hector_flag_80c=0;/* No 80c in 40c !*/
591	580	}
592	581
593	582	/*******************  Ecriture PIO specifique machine MX80 *******************/
594		WRITE8_HANDLER( hector_mx80_io_port_w)
	583	WRITE8_MEMBER(hec2hrp_state::hector_mx80_io_port_w)
595	584	{
596		hec2hrp_state *state = space->machine().driver_data<hec2hrp_state>();
597	585	if ((offset &0x0ff) == 0x40) /* Port page 0*/
598		memory_set_bank(space->machine(), "bank2", HECTORMX_BANK_PAGE0);
	586	memory_set_bank(machine(), "bank2", HECTORMX_BANK_PAGE0);
599	587	if ((offset &0x0ff) == 0x41) /* Port page 1*/
600	588	{
601		memory_set_bank(space->machine(), "bank2", HECTORMX_BANK_PAGE1);
602		state->m_hector_flag_80c=0;
	589	memory_set_bank(machine(), "bank2", HECTORMX_BANK_PAGE1);
	590	m_hector_flag_80c=0;
603	591	}
604	592	if ((offset &0x0ff) == 0x42) /* Port page 2  => port different du MX40*/
605		memory_set_bank(space->machine(), "bank2", HECTORMX_BANK_PAGE2);
	593	memory_set_bank(machine(), "bank2", HECTORMX_BANK_PAGE2);
606	594	if ((offset &0x0ff) == 0x49) /* Port screen resolution*/
607		state->m_hector_flag_80c=1;
	595	m_hector_flag_80c=1;
608	596	}
609	597
610	598	/********************************************************************************

src/mess/machine/mikro80.c

r14963	r14964
32	32	state->m_key_mask = 0xff;
33	33	}
34	34
35		READ8_HANDLER (mikro80_8255_portb_r )
	35	READ8_MEMBER(mikro80_state::mikro80_8255_portb_r)
36	36	{
37		mikro80_state *state = space->machine().driver_data<mikro80_state>();
38	37	UINT8 key = 0xff;
39		if ((state->m_keyboard_mask & 0x01)!=0) { key &= input_port_read(space->machine(),"LINE0"); }
40		if ((state->m_keyboard_mask & 0x02)!=0) { key &= input_port_read(space->machine(),"LINE1"); }
41		if ((state->m_keyboard_mask & 0x04)!=0) { key &= input_port_read(space->machine(),"LINE2"); }
42		if ((state->m_keyboard_mask & 0x08)!=0) { key &= input_port_read(space->machine(),"LINE3"); }
43		if ((state->m_keyboard_mask & 0x10)!=0) { key &= input_port_read(space->machine(),"LINE4"); }
44		if ((state->m_keyboard_mask & 0x20)!=0) { key &= input_port_read(space->machine(),"LINE5"); }
45		if ((state->m_keyboard_mask & 0x40)!=0) { key &= input_port_read(space->machine(),"LINE6"); }
46		if ((state->m_keyboard_mask & 0x80)!=0) { key &= input_port_read(space->machine(),"LINE7"); }
47		return key & state->m_key_mask;
	38	if ((m_keyboard_mask & 0x01)!=0) { key &= input_port_read(machine(),"LINE0"); }
	39	if ((m_keyboard_mask & 0x02)!=0) { key &= input_port_read(machine(),"LINE1"); }
	40	if ((m_keyboard_mask & 0x04)!=0) { key &= input_port_read(machine(),"LINE2"); }
	41	if ((m_keyboard_mask & 0x08)!=0) { key &= input_port_read(machine(),"LINE3"); }
	42	if ((m_keyboard_mask & 0x10)!=0) { key &= input_port_read(machine(),"LINE4"); }
	43	if ((m_keyboard_mask & 0x20)!=0) { key &= input_port_read(machine(),"LINE5"); }
	44	if ((m_keyboard_mask & 0x40)!=0) { key &= input_port_read(machine(),"LINE6"); }
	45	if ((m_keyboard_mask & 0x80)!=0) { key &= input_port_read(machine(),"LINE7"); }
	46	return key & m_key_mask;
48	47	}
49	48
50		READ8_HANDLER (mikro80_8255_portc_r )
	49	READ8_MEMBER(mikro80_state::mikro80_8255_portc_r)
51	50	{
52		return input_port_read(space->machine(), "LINE8");
	51	return input_port_read(machine(), "LINE8");
53	52	}
54	53
55		WRITE8_HANDLER (mikro80_8255_porta_w )
	54	WRITE8_MEMBER(mikro80_state::mikro80_8255_porta_w)
56	55	{
57		mikro80_state *state = space->machine().driver_data<mikro80_state>();
58		state->m_keyboard_mask = data ^ 0xff;
	56	m_keyboard_mask = data ^ 0xff;
59	57	}
60	58
61		WRITE8_HANDLER (mikro80_8255_portc_w )
	59	WRITE8_MEMBER(mikro80_state::mikro80_8255_portc_w)
62	60	{
63	61	}
64	62
65		static READ8_DEVICE_HANDLER( mikro80_8255_portb_device_r ) { return mikro80_8255_portb_r(device->machine().device("maincpu")->memory().space(AS_PROGRAM), offset); }
66		static READ8_DEVICE_HANDLER( mikro80_8255_portc_device_r ) { return mikro80_8255_portc_r(device->machine().device("maincpu")->memory().space(AS_PROGRAM), offset); }
67		static WRITE8_DEVICE_HANDLER( mikro80_8255_porta_device_w ) { mikro80_8255_porta_w(device->machine().device("maincpu")->memory().space(AS_PROGRAM), offset, data); }
68
69	63	I8255_INTERFACE( mikro80_ppi8255_interface )
70	64	{
71	65	DEVCB_NULL,
72		DEVCB_HANDLER(mikro80_8255_porta_device_w),
73		DEVCB_HANDLER(mikro80_8255_portb_device_r),
	66	DEVCB_DRIVER_MEMBER(mikro80_state, mikro80_8255_porta_w),
	67	DEVCB_DRIVER_MEMBER(mikro80_state, mikro80_8255_portb_r),
74	68	DEVCB_NULL,
75		DEVCB_HANDLER(mikro80_8255_portc_device_r),
	69	DEVCB_DRIVER_MEMBER(mikro80_state, mikro80_8255_portc_r),
76	70	DEVCB_NULL,
77	71	};
78	72
r14963	r14964
91	85	}
92	86
93	87
94		READ8_HANDLER( mikro80_keyboard_r )
	88	READ8_MEMBER(mikro80_state::mikro80_keyboard_r)
95	89	{
96		i8255_device *ppi = space->machine().device<i8255_device>("ppi8255");
97		return ppi->read(*space, offset^0x03);
	90	i8255_device *ppi = machine().device<i8255_device>("ppi8255");
	91	return ppi->read(space, offset^0x03);
98	92	}
99	93
100		WRITE8_HANDLER( mikro80_keyboard_w )
	94	WRITE8_MEMBER(mikro80_state::mikro80_keyboard_w)
101	95	{
102		i8255_device *ppi = space->machine().device<i8255_device>("ppi8255");
103		ppi->write(*space, offset^0x03, data);
	96	i8255_device *ppi = machine().device<i8255_device>("ppi8255");
	97	ppi->write(space, offset^0x03, data);
104	98	}
105	99
106	100
107		WRITE8_HANDLER( mikro80_tape_w )
	101	WRITE8_MEMBER(mikro80_state::mikro80_tape_w)
108	102	{
109		space->machine().device<cassette_image_device>(CASSETTE_TAG)->output(data & 0x01 ? 1 : -1);
	103	machine().device<cassette_image_device>(CASSETTE_TAG)->output(data & 0x01 ? 1 : -1);
110	104	}
111	105
112	106
113		READ8_HANDLER( mikro80_tape_r )
	107	READ8_MEMBER(mikro80_state::mikro80_tape_r)
114	108	{
115		double level = space->machine().device<cassette_image_device>(CASSETTE_TAG)->input();
	109	double level = machine().device<cassette_image_device>(CASSETTE_TAG)->input();
116	110	if (level <  0) {
117	111	return 0x00;
118	112	}

src/mess/machine/pc.c

r14963	r14964
65	65	*
66	66	*************************************************************************/
67	67
68		READ8_HANDLER(pc_page_r)
	68	READ8_MEMBER(pc_state::pc_page_r)
69	69	{
70	70	return 0xFF;
71	71	}
72	72
73	73
74		WRITE8_HANDLER(pc_page_w)
	74	WRITE8_MEMBER(pc_state::pc_page_w)
75	75	{
76		pc_state *st = space->machine().driver_data<pc_state>();
77	76	switch(offset % 4)
78	77	{
79	78	case 1:
80		st->m_dma_offset[0][2] = data;
	79	m_dma_offset[0][2] = data;
81	80	break;
82	81	case 2:
83		st->m_dma_offset[0][3] = data;
	82	m_dma_offset[0][3] = data;
84	83	break;
85	84	case 3:
86		st->m_dma_offset[0][0] = st->m_dma_offset[0][1] = data;
	85	m_dma_offset[0][0] = m_dma_offset[0][1] = data;
87	86	break;
88	87	}
89	88	}
r14963	r14964
99	98	}
100	99
101	100
102		static READ8_HANDLER( pc_dma_read_byte )
	101	READ8_MEMBER(pc_state::pc_dma_read_byte)
103	102	{
104	103	UINT8 result;
105		pc_state *st = space->machine().driver_data<pc_state>();
106		offs_t page_offset = (((offs_t) st->m_dma_offset[0][st->m_dma_channel]) << 16)
	104	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
107	105	& 0x0F0000;
108	106
109		result = space->read_byte( page_offset + offset);
	107	result = space.read_byte( page_offset + offset);
110	108	return result;
111	109	}
112	110
113	111
114		static WRITE8_HANDLER( pc_dma_write_byte )
	112	WRITE8_MEMBER(pc_state::pc_dma_write_byte)
115	113	{
116		pc_state *st = space->machine().driver_data<pc_state>();
117		offs_t page_offset = (((offs_t) st->m_dma_offset[0][st->m_dma_channel]) << 16)
	114	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
118	115	& 0x0F0000;
119	116
120		space->write_byte( page_offset + offset, data);
	117	space.write_byte( page_offset + offset, data);
121	118	}
122	119
123	120
r14963	r14964
173	170	{
174	171	DEVCB_DEVICE_LINE("dma8237", pc_dma_hrq_changed),
175	172	DEVCB_DEVICE_LINE("dma8237", pc_dma8237_out_eop),
176		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
177		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
	173	DEVCB_DRIVER_MEMBER(pc_state, pc_dma_read_byte),
	174	DEVCB_DRIVER_MEMBER(pc_state, pc_dma_write_byte),
178	175	{ DEVCB_NULL, DEVCB_NULL, DEVCB_DEVICE_HANDLER("dma8237", pc_dma8237_fdc_dack_r), DEVCB_DEVICE_HANDLER("dma8237", pc_dma8237_hdc_dack_r) },
179	176	{ DEVCB_DEVICE_HANDLER("dma8237", pc_dma8237_0_dack_w), DEVCB_NULL, DEVCB_DEVICE_HANDLER("dma8237", pc_dma8237_fdc_dack_w), DEVCB_DEVICE_HANDLER("dma8237", pc_dma8237_hdc_dack_w) },
180	177	{ DEVCB_DEVICE_LINE("dma8237", pc_dack0_w), DEVCB_DEVICE_LINE("dma8237", pc_dack1_w), DEVCB_DEVICE_LINE("dma8237", pc_dack2_w), DEVCB_DEVICE_LINE("dma8237", pc_dack3_w) }
r14963	r14964
432	429
433	430	static UINT8   nmi_enabled;
434	431
435		WRITE8_HANDLER( pc_nmi_enable_w )
	432	WRITE8_MEMBER(pc_state::pc_nmi_enable_w)
436	433	{
437		logerror( "%08X: changing NMI state to %s\n", cpu_get_pc(&space->device()), data & 0x80 ? "enabled" : "disabled" );
	434	logerror( "%08X: changing NMI state to %s\n", cpu_get_pc(&space.device()), data & 0x80 ? "enabled" : "disabled" );
438	435
439	436	nmi_enabled = data & 0x80;
440	437	}
r14963	r14964
486	483	} pcjr_keyb;
487	484
488	485
489		READ8_HANDLER( pcjr_nmi_enable_r )
	486	READ8_MEMBER(pc_state::pcjr_nmi_enable_r)
490	487	{
491	488	pcjr_keyb.latch = 0;
492	489
r14963	r14964
622	619	**********************************************************/
623	620
624	621
625		WRITE8_HANDLER( ibm5150_kb_set_clock_signal )
	622	WRITE8_MEMBER(pc_state::ibm5150_kb_set_clock_signal)
626	623	{
627		pc_state *st = space->machine().driver_data<pc_state>();
628		device_t *keyboard = space->machine().device("keyboard");
	624	device_t *keyboard = machine().device("keyboard");
629	625
630		if ( st->m_ppi_clock_signal != data )
	626	if ( m_ppi_clock_signal != data )
631	627	{
632		if ( st->m_ppi_keyb_clock && st->m_ppi_shift_enable )
	628	if ( m_ppi_keyb_clock && m_ppi_shift_enable )
633	629	{
634		st->m_ppi_clock_signal = data;
635		if ( ! st->m_ppi_keyboard_clear )
	630	m_ppi_clock_signal = data;
	631	if ( ! m_ppi_keyboard_clear )
636	632	{
637	633	/* Data is clocked in on a high->low transition */
638	634	if ( ! data )
639	635	{
640		UINT8   trigger_irq = st->m_ppi_shift_register & 0x01;
	636	UINT8   trigger_irq = m_ppi_shift_register & 0x01;
641	637
642		st->m_ppi_shift_register = ( st->m_ppi_shift_register >> 1 ) | ( st->m_ppi_data_signal << 7 );
	638	m_ppi_shift_register = ( m_ppi_shift_register >> 1 ) | ( m_ppi_data_signal << 7 );
643	639	if ( trigger_irq )
644	640	{
645		pic8259_ir1_w(st->m_pic8259, 1);
646		st->m_ppi_shift_enable = 0;
647		st->m_ppi_clock_signal = 0;
648		kb_keytronic_clock_w(keyboard, st->m_ppi_clock_signal);
	641	pic8259_ir1_w(m_pic8259, 1);
	642	m_ppi_shift_enable = 0;
	643	m_ppi_clock_signal = 0;
	644	kb_keytronic_clock_w(keyboard, m_ppi_clock_signal);
649	645	}
650	646	}
651	647	}
652	648	}
653	649	}
654	650
655		kb_keytronic_clock_w(keyboard, st->m_ppi_clock_signal);
	651	kb_keytronic_clock_w(keyboard, m_ppi_clock_signal);
656	652	}
657	653
658	654
659		WRITE8_HANDLER( ibm5150_kb_set_data_signal )
	655	WRITE8_MEMBER(pc_state::ibm5150_kb_set_data_signal)
660	656	{
661		pc_state *st = space->machine().driver_data<pc_state>();
662		device_t *keyboard = space->machine().device("keyboard");
	657	device_t *keyboard = machine().device("keyboard");
663	658
664		st->m_ppi_data_signal = data;
	659	m_ppi_data_signal = data;
665	660
666		kb_keytronic_data_w(keyboard, st->m_ppi_data_signal);
	661	kb_keytronic_data_w(keyboard, m_ppi_data_signal);
667	662	}
668	663
669	664	static READ8_DEVICE_HANDLER (ibm5160_ppi_porta_r)
r14963	r14964
1390	1385	pc_rtc.timer->adjust(attotime::zero, 0, attotime(1,0));
1391	1386	}
1392	1387
1393		READ8_HANDLER( pc_rtc_r )
	1388	READ8_MEMBER(pc_state::pc_rtc_r)
1394	1389	{
1395	1390	int data;
1396	1391	switch (offset) {
r14963	r14964
1401	1396	return data;
1402	1397	}
1403	1398
1404		WRITE8_HANDLER( pc_rtc_w )
	1399	WRITE8_MEMBER(pc_state::pc_rtc_w)
1405	1400	{
1406	1401	logerror( "rtc write %.2x %.2x\n", offset, data);
1407	1402	switch(offset) {
r14963	r14964
1410	1405	}
1411	1406	}
1412	1407
1413		READ16_HANDLER( pc16le_rtc_r ) { return read16le_with_read8_handler(pc_rtc_r, space, offset, mem_mask); }
1414		WRITE16_HANDLER( pc16le_rtc_w ) { write16le_with_write8_handler(pc_rtc_w, space, offset, data, mem_mask); }
1415
1416	1408	/*************************************************************************
1417	1409	*
1418	1410	*      EXP
r14963	r14964
1432	1424	UINT8 reg[8];
1433	1425	} pc_expansion={ { 0,0,0,0,0,0,1 } };
1434	1426
1435		WRITE8_HANDLER ( pc_EXP_w )
	1427	WRITE8_MEMBER(pc_state::pc_EXP_w)
1436	1428	{
1437		running_machine &machine = space->machine();
1438
1439		DBG_LOG(1,"EXP_unit_w",("%.2x $%02x\n", offset, data));
	1429	//DBG_LOG(1,"EXP_unit_w",("%.2x $%02x\n", offset, data));
1440	1430	switch (offset) {
1441	1431	case 4:
1442	1432	pc_expansion.reg[4]=pc_expansion.reg[5]=pc_expansion.reg[6]=data;
r14963	r14964
1446	1436	}
1447	1437	}
1448	1438
1449		READ8_HANDLER ( pc_EXP_r )
	1439	READ8_MEMBER(pc_state::pc_EXP_r)
1450	1440	{
1451	1441	int data;
1452	1442	UINT16 a;
1453		running_machine &machine = space->machine();
1454
1455	1443	switch (offset) {
1456	1444	case 6:
1457	1445	data = pc_expansion.reg[offset];
r14963	r14964
1463	1451	default:
1464	1452	data = pc_expansion.reg[offset];
1465	1453	}
1466		DBG_LOG(1,"EXP_unit_r",("%.2x $%02x\n", offset, data));
	1454	//DBG_LOG(1,"EXP_unit_r",("%.2x $%02x\n", offset, data));
1467	1455	return data;
1468	1456	}
1469	1457

src/mess/machine/pecom.c

r14963	r14964
48	48	state->m_reset_timer->adjust(attotime::from_msec(5));
49	49	}
50	50
51		static READ8_HANDLER( pecom_cdp1869_charram_r )
	51	READ8_MEMBER(pecom_state::pecom_cdp1869_charram_r)
52	52	{
53		pecom_state *state = space->machine().driver_data<pecom_state>();
54		return state->m_cdp1869->char_ram_r(*space, offset);
	53	return m_cdp1869->char_ram_r(space, offset);
55	54	}
56	55
57		static WRITE8_HANDLER( pecom_cdp1869_charram_w )
	56	WRITE8_MEMBER(pecom_state::pecom_cdp1869_charram_w)
58	57	{
59		pecom_state *state = space->machine().driver_data<pecom_state>();
60		return state->m_cdp1869->char_ram_w(*space, offset, data);
	58	return m_cdp1869->char_ram_w(space, offset, data);
61	59	}
62	60
63		static READ8_HANDLER( pecom_cdp1869_pageram_r )
	61	READ8_MEMBER(pecom_state::pecom_cdp1869_pageram_r)
64	62	{
65		pecom_state *state = space->machine().driver_data<pecom_state>();
66		return state->m_cdp1869->page_ram_r(*space, offset);
	63	return m_cdp1869->page_ram_r(space, offset);
67	64	}
68	65
69		static WRITE8_HANDLER( pecom_cdp1869_pageram_w )
	66	WRITE8_MEMBER(pecom_state::pecom_cdp1869_pageram_w)
70	67	{
71		pecom_state *state = space->machine().driver_data<pecom_state>();
72		return state->m_cdp1869->page_ram_w(*space, offset, data);
	68	return m_cdp1869->page_ram_w(space, offset, data);
73	69	}
74	70
75		WRITE8_HANDLER( pecom_bank_w )
	71	WRITE8_MEMBER(pecom_state::pecom_bank_w)
76	72	{
77		//  pecom_state *state = space->machine().driver_data<pecom_state>();
78		address_space *space2 = space->machine().device(CDP1802_TAG)->memory().space(AS_PROGRAM);
79		UINT8 *rom = space->machine().region(CDP1802_TAG)->base();
80		space->machine().device(CDP1802_TAG)->memory().space(AS_PROGRAM)->install_write_bank(0x0000, 0x3fff, "bank1");
81		memory_set_bankptr(space->machine(), "bank1", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0x0000);
	73	address_space *space2 = machine().device(CDP1802_TAG)->memory().space(AS_PROGRAM);
	74	UINT8 *rom = machine().region(CDP1802_TAG)->base();
	75	machine().device(CDP1802_TAG)->memory().space(AS_PROGRAM)->install_write_bank(0x0000, 0x3fff, "bank1");
	76	memory_set_bankptr(machine(), "bank1", machine().device<ram_device>(RAM_TAG)->pointer() + 0x0000);
82	77
83	78	if (data==2)
84	79	{
85		space2->install_legacy_read_handler (0xf000, 0xf7ff, FUNC(pecom_cdp1869_charram_r));
86		space2->install_legacy_write_handler(0xf000, 0xf7ff, FUNC(pecom_cdp1869_charram_w));
87		space2->install_legacy_read_handler (0xf800, 0xffff, FUNC(pecom_cdp1869_pageram_r));
88		space2->install_legacy_write_handler(0xf800, 0xffff, FUNC(pecom_cdp1869_pageram_w));
	80	space2->install_read_handler (0xf000, 0xf7ff, read8_delegate(FUNC(pecom_state::pecom_cdp1869_charram_r),this));
	81	space2->install_write_handler(0xf000, 0xf7ff, write8_delegate(FUNC(pecom_state::pecom_cdp1869_charram_w),this));
	82	space2->install_read_handler (0xf800, 0xffff, read8_delegate(FUNC(pecom_state::pecom_cdp1869_pageram_r),this));
	83	space2->install_write_handler(0xf800, 0xffff, write8_delegate(FUNC(pecom_state::pecom_cdp1869_pageram_w),this));
89	84	}
90	85	else
91	86	{
r14963	r14964
93	88	space2->unmap_write(0xf800, 0xffff);
94	89	space2->install_read_bank (0xf000, 0xf7ff, "bank3");
95	90	space2->install_read_bank (0xf800, 0xffff, "bank4");
96		memory_set_bankptr(space->machine(), "bank3", rom + 0xf000);
97		memory_set_bankptr(space->machine(), "bank4", rom + 0xf800);
	91	memory_set_bankptr(machine(), "bank3", rom + 0xf000);
	92	memory_set_bankptr(machine(), "bank4", rom + 0xf800);
98	93	}
99	94	}
100	95
101		READ8_HANDLER (pecom_keyboard_r)
	96	READ8_MEMBER(pecom_state::pecom_keyboard_r)
102	97	{
103	98	static const char *const keynames[] = {
104	99	"LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7",
r14963	r14964
111	106	Address is available on address bus during reading of value from port, and that is
112	107	used to determine keyboard line reading
113	108	*/
114		UINT16 addr = cpu_get_reg(space->machine().device(CDP1802_TAG), COSMAC_R0 + cpu_get_reg(space->machine().device(CDP1802_TAG), COSMAC_X));
	109	UINT16 addr = cpu_get_reg(machine().device(CDP1802_TAG), COSMAC_R0 + cpu_get_reg(machine().device(CDP1802_TAG), COSMAC_X));
115	110	/* just in case somone is reading non existing ports */
116	111	if (addr<0x7cca || addr>0x7ce3) return 0;
117		return input_port_read(space->machine(), keynames[addr - 0x7cca]) & 0x03;
	112	return input_port_read(machine(), keynames[addr - 0x7cca]) & 0x03;
118	113	}
119	114
120	115	/* CDP1802 Interface */

src/mess/machine/pce.c

r14963	r14964
109	109	static TIMER_CALLBACK( pce_cd_adpcm_fadeout_callback );
110	110	static TIMER_CALLBACK( pce_cd_adpcm_fadein_callback );
111	111
112		static WRITE8_HANDLER( pce_sf2_banking_w )
	112	WRITE8_MEMBER(pce_state::pce_sf2_banking_w)
113	113	{
114		memory_set_bankptr( space->machine(), "bank2", space->machine().region("user1")->base() + offset * 0x080000 + 0x080000 );
115		memory_set_bankptr( space->machine(), "bank3", space->machine().region("user1")->base() + offset * 0x080000 + 0x088000 );
116		memory_set_bankptr( space->machine(), "bank4", space->machine().region("user1")->base() + offset * 0x080000 + 0x0D0000 );
	114	memory_set_bankptr( machine(), "bank2", machine().region("user1")->base() + offset * 0x080000 + 0x080000 );
	115	memory_set_bankptr( machine(), "bank3", machine().region("user1")->base() + offset * 0x080000 + 0x088000 );
	116	memory_set_bankptr( machine(), "bank4", machine().region("user1")->base() + offset * 0x080000 + 0x0D0000 );
117	117	}
118	118
119		static WRITE8_HANDLER( pce_cartridge_ram_w )
	119	WRITE8_MEMBER(pce_state::pce_cartridge_ram_w)
120	120	{
121		pce_state *state = space->machine().driver_data<pce_state>();
122		state->m_cartridge_ram[offset] = data;
	121	m_cartridge_ram[offset] = data;
123	122	}
124	123
125	124	DEVICE_IMAGE_LOAD(pce_cart)
r14963	r14964
221	220	/* Check for Street fighter 2 */
222	221	if (size == PCE_ROM_MAXSIZE)
223	222	{
224		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x01ff0, 0x01ff3, FUNC(pce_sf2_banking_w));
	223	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x01ff0, 0x01ff3, write8_delegate(FUNC(pce_state::pce_sf2_banking_w),state));
225	224	}
226	225
227	226	/* Check for Populous */
r14963	r14964
229	228	{
230	229	state->m_cartridge_ram = auto_alloc_array(image.device().machine(), UINT8, 0x8000);
231	230	memory_set_bankptr(image.device().machine(), "bank2", state->m_cartridge_ram);
232		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x080000, 0x087FFF, FUNC(pce_cartridge_ram_w));
	231	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x080000, 0x087FFF, write8_delegate(FUNC(pce_state::pce_cartridge_ram_w),state));
233	232	}
234	233
235	234	/* Check for CD system card */
r14963	r14964
244	243	{
245	244	state->m_cartridge_ram = auto_alloc_array(image.device().machine(), UINT8, 0x30000);
246	245	memory_set_bankptr(image.device().machine(), "bank4", state->m_cartridge_ram);
247		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x0D0000, 0x0FFFFF, FUNC(pce_cartridge_ram_w));
248		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0x080000, 0x087FFF, FUNC(pce_cd_acard_wram_r),FUNC(pce_cd_acard_wram_w));
	246	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x0D0000, 0x0FFFFF, write8_delegate(FUNC(pce_state::pce_cartridge_ram_w),state));
	247	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x080000, 0x087FFF, read8_delegate(FUNC(pce_state::pce_cd_acard_wram_r),state),write8_delegate(FUNC(pce_state::pce_cd_acard_wram_w),state));
249	248	}
250	249	}
251	250	return 0;
r14963	r14964
300	299	}
301	300
302	301	/* todo: how many input ports does the PCE have? */
303		WRITE8_HANDLER ( mess_pce_joystick_w )
	302	WRITE8_MEMBER(pce_state::mess_pce_joystick_w)
304	303	{
305		pce_state *state = space->machine().driver_data<pce_state>();
306	304	int joy_i;
307		UINT8 joy_type = input_port_read(space->machine(),"JOY_TYPE");
	305	UINT8 joy_type = input_port_read(machine(),"JOY_TYPE");
308	306
309		h6280io_set_buffer(&space->device(), data);
	307	h6280io_set_buffer(&space.device(), data);
310	308
311	309	/* bump counter on a low-to-high transition of bit 1 */
312		if ((!state->m_joystick_data_select) && (data & JOY_CLOCK))
	310	if ((!m_joystick_data_select) && (data & JOY_CLOCK))
313	311	{
314		state->m_joystick_port_select = (state->m_joystick_port_select + 1) & 0x07;
	312	m_joystick_port_select = (m_joystick_port_select + 1) & 0x07;
315	313	}
316	314
317	315	/* do we want buttons or direction? */
318		state->m_joystick_data_select = data & JOY_CLOCK;
	316	m_joystick_data_select = data & JOY_CLOCK;
319	317
320	318	/* clear counter if bit 2 is set */
321	319	if (data & JOY_RESET)
322	320	{
323		state->m_joystick_port_select = 0;
	321	m_joystick_port_select = 0;
324	322
325	323	for (joy_i = 0; joy_i < 5; joy_i++)
326	324	{
327	325	if (((joy_type >> (joy_i*2)) & 3) == 2)
328		state->m_joy_6b_packet[joy_i] ^= 1;
	326	m_joy_6b_packet[joy_i] ^= 1;
329	327	}
330	328	}
331	329	}
332	330
333		READ8_HANDLER ( mess_pce_joystick_r )
	331	READ8_MEMBER(pce_state::mess_pce_joystick_r)
334	332	{
335		pce_state *state = space->machine().driver_data<pce_state>();
336	333	static const char *const joyname[4][5] = {
337	334	{ "JOY_P1", "JOY_P2", "JOY_P3", "JOY_P4", "JOY_P5" },
338	335	{ },
339	336	{ "JOY6B_P1", "JOY6B_P2", "JOY6B_P3", "JOY6B_P4", "JOY6B_P5" },
340	337	{ }
341	338	};
342		UINT8 joy_type = input_port_read(space->machine(), "JOY_TYPE");
	339	UINT8 joy_type = input_port_read(machine(), "JOY_TYPE");
343	340	UINT8 ret, data;
344	341
345		if (state->m_joystick_port_select <= 4)
	342	if (m_joystick_port_select <= 4)
346	343	{
347		switch((joy_type >> (state->m_joystick_port_select*2)) & 3)
	344	switch((joy_type >> (m_joystick_port_select*2)) & 3)
348	345	{
349	346	case 0: //2-buttons pad
350		data = input_port_read(space->machine(), joyname[0][state->m_joystick_port_select]);
	347	data = input_port_read(machine(), joyname[0][m_joystick_port_select]);
351	348	break;
352	349	case 2: //6-buttons pad
353	350	/*
r14963	r14964
357	354	Note that six buttons pad just doesn't work with (almost?) every single 2-button-only games, it's really just an after-thought and it is like this
358	355	on real HW.
359	356	*/
360		data = input_port_read(space->machine(), joyname[2][state->m_joystick_port_select]) >> (state->m_joy_6b_packet[state->m_joystick_port_select]*8);
	357	data = input_port_read(machine(), joyname[2][m_joystick_port_select]) >> (m_joy_6b_packet[m_joystick_port_select]*8);
361	358	break;
362	359	default:
363	360	data = 0xff;
r14963	r14964
368	365	data = 0xff;
369	366
370	367
371		if (state->m_joystick_data_select)
	368	if (m_joystick_data_select)
372	369	data >>= 4;
373	370
374		ret = (data & 0x0f) | state->m_io_port_options;
	371	ret = (data & 0x0f) | m_io_port_options;
375	372	#ifdef UNIFIED_PCE
376	373	ret &= ~0x40;
377	374	#endif
r14963	r14964
1229	1226	pce_cd.adpcm_fadein_timer->adjust(attotime::never);
1230	1227	}
1231	1228
1232		WRITE8_HANDLER( pce_cd_bram_w )
	1229	WRITE8_MEMBER(pce_state::pce_cd_bram_w)
1233	1230	{
1234		pce_state *state = space->machine().driver_data<pce_state>();
1235		pce_cd_t &pce_cd = state->m_cd;
	1231	pce_cd_t &pce_cd = m_cd;
1236	1232	if ( ! pce_cd.bram_locked )
1237	1233	{
1238	1234	pce_cd.bram[ offset ] = data;
r14963	r14964
1332	1328	}
1333	1329
1334	1330
1335		WRITE8_HANDLER( pce_cd_intf_w )
	1331	WRITE8_MEMBER(pce_state::pce_cd_intf_w)
1336	1332	{
1337		pce_state *state = space->machine().driver_data<pce_state>();
1338		pce_cd_t &pce_cd = state->m_cd;
1339		pce_cd_update(space->machine());
	1333	pce_cd_t &pce_cd = m_cd;
	1334	pce_cd_update(machine());
1340	1335
1341		if(offset & 0x200 && state->m_sys3_card && state->m_acard) // route Arcade Card handling ports
	1336	if(offset & 0x200 && m_sys3_card && m_acard) // route Arcade Card handling ports
1342	1337	return pce_cd_acard_w(space,offset,data);
1343	1338
1344		logerror("%04X: write to CD interface offset %02X, data %02X\n", cpu_get_pc(&space->device()), offset, data );
	1339	logerror("%04X: write to CD interface offset %02X, data %02X\n", cpu_get_pc(&space.device()), offset, data );
1345	1340
1346	1341	switch( offset & 0xf )
1347	1342	{
1348	1343	case 0x00:   /* CDC status */
1349	1344	/* select device (which bits??) */
1350	1345	pce_cd.scsi_SEL = 1;
1351		pce_cd_update(space->machine());
	1346	pce_cd_update(machine());
1352	1347	pce_cd.scsi_SEL = 0;
1353	1348	pce_cd.adpcm_dma_timer->adjust(attotime::never); // stop ADPCM DMA here
1354	1349	/* any write here clears CD transfer irqs */
1355	1350	pce_cd.regs[0x03] &= ~0x70;
1356		cputag_set_input_line(space->machine(), "maincpu", 1, CLEAR_LINE );
	1351	cputag_set_input_line(machine(), "maincpu", 1, CLEAR_LINE );
1357	1352	break;
1358	1353	case 0x01:   /* CDC command / status / data */
1359	1354	break;
r14963	r14964
1365	1360	/* bit 2 - ?? irq */
1366	1361	pce_cd.scsi_ACK = data & 0x80;
1367	1362	/* Don't set or reset any irq lines, but just verify the current state */
1368		pce_cd_set_irq_line( space->machine(), 0, 0 );
	1363	pce_cd_set_irq_line( machine(), 0, 0 );
1369	1364	break;
1370	1365	case 0x03:   /* BRAM lock / CD status / IRQ - Read Only register */
1371	1366	break;
r14963	r14964
1379	1374	if ( data & 0x80 )
1380	1375	{
1381	1376	pce_cd.bram_locked = 0;
1382		pce_set_cd_bram(space->machine());
	1377	pce_set_cd_bram(machine());
1383	1378	}
1384	1379	break;
1385	1380	case 0x08:   /* ADPCM address (LSB) / CD data */
r14963	r14964
1387	1382	case 0x09:   /* ADPCM address (MSB) */
1388	1383	break;
1389	1384	case 0x0A:   /* ADPCM RAM data port */
1390		pce_cd_set_adpcm_ram_byte(space->machine(), data);
	1385	pce_cd_set_adpcm_ram_byte(machine(), data);
1391	1386	break;
1392	1387	case 0x0B:   /* ADPCM DMA control */
1393	1388	if ( data & 0x03 )
r14963	r14964
1409	1404	pce_cd.msm_end_addr = 0;
1410	1405	pce_cd.msm_half_addr = 0;
1411	1406	pce_cd.msm_nibble = 0;
1412		adpcm_stop(space->machine(), 0);
1413		msm5205_reset_w( space->machine().device( "msm5205"), 1 );
	1407	adpcm_stop(machine(), 0);
	1408	msm5205_reset_w( machine().device( "msm5205"), 1 );
1414	1409	}
1415	1410
1416	1411	if ( ( data & 0x40) && ((pce_cd.regs[0x0D] & 0x40) == 0) ) // ADPCM play
r14963	r14964
1419	1414	pce_cd.msm_end_addr = (pce_cd.adpcm_read_ptr + pce_cd.adpcm_length) & 0xffff;
1420	1415	pce_cd.msm_half_addr = (pce_cd.adpcm_read_ptr + (pce_cd.adpcm_length / 2)) & 0xffff;
1421	1416	pce_cd.msm_nibble = 0;
1422		adpcm_play(space->machine());
1423		msm5205_reset_w( space->machine().device( "msm5205"), 0 );
	1417	adpcm_play(machine());
	1418	msm5205_reset_w( machine().device( "msm5205"), 0 );
1424	1419
1425	1420	//popmessage("%08x %08x",pce_cd.adpcm_read_ptr,pce_cd.adpcm_length);
1426	1421	}
1427	1422	else if ( (data & 0x40) == 0 )
1428	1423	{
1429	1424	/* used by Buster Bros to cancel an in-flight sample */
1430		adpcm_stop(space->machine(), 0);
1431		msm5205_reset_w( space->machine().device( "msm5205"), 1 );
	1425	adpcm_stop(machine(), 0);
	1426	msm5205_reset_w( machine().device( "msm5205"), 1 );
1432	1427	}
1433	1428
1434	1429	pce_cd.msm_repeat = (data & 0x20) >> 5;
r14963	r14964
1450	1445	break;
1451	1446	case 0x0E:   /* ADPCM playback rate */
1452	1447	pce_cd.adpcm_clock_divider = 0x10 - ( data & 0x0F );
1453		msm5205_change_clock_w(space->machine().device("msm5205"), (PCE_CD_CLOCK / 6) / pce_cd.adpcm_clock_divider);
	1448	msm5205_change_clock_w(machine().device("msm5205"), (PCE_CD_CLOCK / 6) / pce_cd.adpcm_clock_divider);
1454	1449	break;
1455	1450	case 0x0F:   /* ADPCM and CD audio fade timer */
1456	1451	/* TODO: timers needs HW tests */
r14963	r14964
1517	1512	return;
1518	1513	}
1519	1514	pce_cd.regs[offset & 0xf] = data;
1520		pce_cd_update(space->machine());
	1515	pce_cd_update(machine());
1521	1516	}
1522	1517
1523	1518	static TIMER_CALLBACK( pce_cd_clear_ack )
r14963	r14964
1583	1578	}
1584	1579	}
1585	1580
1586		READ8_HANDLER( pce_cd_intf_r )
	1581	READ8_MEMBER(pce_state::pce_cd_intf_r)
1587	1582	{
1588		pce_state *state = space->machine().driver_data<pce_state>();
1589		pce_cd_t &pce_cd = state->m_cd;
	1583	pce_cd_t &pce_cd = m_cd;
1590	1584	UINT8 data = pce_cd.regs[offset & 0x0F];
1591	1585
1592		pce_cd_update(space->machine());
	1586	pce_cd_update(machine());
1593	1587
1594		if(offset & 0x200 && state->m_sys3_card && state->m_acard) // route Arcade Card handling ports
	1588	if(offset & 0x200 && m_sys3_card && m_acard) // route Arcade Card handling ports
1595	1589	return pce_cd_acard_r(space,offset);
1596	1590
1597		logerror("%04X: read from CD interface offset %02X\n", cpu_get_pc(&space->device()), offset );
	1591	logerror("%04X: read from CD interface offset %02X\n", cpu_get_pc(&space.device()), offset );
1598	1592
1599		if((offset & 0xc0) == 0xc0 && state->m_sys3_card) //System 3 Card header handling
	1593	if((offset & 0xc0) == 0xc0 && m_sys3_card) //System 3 Card header handling
1600	1594	{
1601	1595	switch(offset & 0xcf)
1602	1596	{
1603	1597	case 0xc1: return 0xaa;
1604	1598	case 0xc2: return 0x55;
1605	1599	case 0xc3: return 0x00;
1606		case 0xc5: return (state->m_sys3_card & 2) ? 0x55 : 0xaa;
1607		case 0xc6: return (state->m_sys3_card & 2) ? 0xaa : 0x55;
	1600	case 0xc5: return (m_sys3_card & 2) ? 0x55 : 0xaa;
	1601	case 0xc6: return (m_sys3_card & 2) ? 0xaa : 0x55;
1608	1602	case 0xc7: return 0x03;
1609	1603	}
1610	1604	}
r14963	r14964
1627	1621	/* bit 4 set when CD motor is on */
1628	1622	/* bit 2 set when less than half of the ADPCM data is remaining ?? */
1629	1623	pce_cd.bram_locked = 1;
1630		pce_set_cd_bram(space->machine());
	1624	pce_set_cd_bram(machine());
1631	1625	data = data & 0x6E;
1632	1626	data |= ( pce_cd.cd_motor_on ? 0x10 : 0 );
1633	1627	pce_cd.regs[0x03] ^= 0x02;         /* TODO: get rid of this hack */
r14963	r14964
1641	1635	data = ( pce_cd.bram_locked ? ( data & 0x7F ) : ( data | 0x80 ) );
1642	1636	break;
1643	1637	case 0x08:   /* ADPCM address (LSB) / CD data */
1644		data = pce_cd_get_cd_data_byte(space->machine());
	1638	data = pce_cd_get_cd_data_byte(machine());
1645	1639	break;
1646	1640	case 0x0A:   /* ADPCM RAM data port */
1647		data = pce_cd_get_adpcm_ram_byte(space->machine());
	1641	data = pce_cd_get_adpcm_ram_byte(machine());
1648	1642	break;
1649	1643	case 0x0B:   /* ADPCM DMA control */
1650	1644	break;
r14963	r14964
1672	1666
1673	1667	*/
1674	1668
1675		READ8_HANDLER( pce_cd_acard_r )
	1669	READ8_MEMBER(pce_state::pce_cd_acard_r)
1676	1670	{
1677		pce_state *state = space->machine().driver_data<pce_state>();
1678		pce_cd_t &pce_cd = state->m_cd;
	1671	pce_cd_t &pce_cd = m_cd;
1679	1672	UINT8 r_num;
1680	1673
1681	1674	if((offset & 0x2e0) == 0x2e0)
r14963	r14964
1737	1730	return 0;
1738	1731	}
1739	1732
1740		WRITE8_HANDLER( pce_cd_acard_w )
	1733	WRITE8_MEMBER(pce_state::pce_cd_acard_w)
1741	1734	{
1742		pce_state *state = space->machine().driver_data<pce_state>();
1743		pce_cd_t &pce_cd = state->m_cd;
	1735	pce_cd_t &pce_cd = m_cd;
1744	1736	UINT8 w_num;
1745	1737
1746	1738	if((offset & 0x2e0) == 0x2e0)
r14963	r14964
1821	1813	}
1822	1814	}
1823	1815
1824		READ8_HANDLER( pce_cd_acard_wram_r )
	1816	READ8_MEMBER(pce_state::pce_cd_acard_wram_r)
1825	1817	{
1826	1818	return pce_cd_intf_r(space,0x200 | (offset & 0x6000) >> 9);
1827	1819	}
1828	1820
1829		WRITE8_HANDLER( pce_cd_acard_wram_w )
	1821	WRITE8_MEMBER(pce_state::pce_cd_acard_wram_w)
1830	1822	{
1831	1823	pce_cd_intf_w(space,0x200 | (offset & 0x6000) >> 9,data);
1832	1824	}

src/mess/machine/bbc.c

r14963	r14964
34	34	*************************/
35	35
36	36	/* for the model A just address the 4 on board ROM sockets */
37		WRITE8_HANDLER ( bbc_page_selecta_w )
	37	WRITE8_MEMBER(bbc_state::bbc_page_selecta_w)
38	38	{
39		memory_set_bankptr(space->machine(),"bank4",space->machine().region("user1")->base()+((data&0x03)<<14));
	39	memory_set_bankptr(machine(),"bank4",machine().region("user1")->base()+((data&0x03)<<14));
40	40	}
41	41
42	42
43		WRITE8_HANDLER ( bbc_memorya1_w )
	43	WRITE8_MEMBER(bbc_state::bbc_memorya1_w)
44	44	{
45		space->machine().region("maincpu")->base()[offset]=data;
	45	machine().region("maincpu")->base()[offset]=data;
46	46	}
47	47
48	48	/*************************
r14963	r14964
51	51
52	52	/* the model B address all 16 of the ROM sockets */
53	53	/* I have set bank 1 as a special case to load different DFS roms selectable from MESS's DIP settings var:bbc_DFSTypes */
54		WRITE8_HANDLER ( bbc_page_selectb_w )
	54	WRITE8_MEMBER(bbc_state::bbc_page_selectb_w)
55	55	{
56		bbc_state *state = space->machine().driver_data<bbc_state>();
57		state->m_rombank=data&0x0f;
58		if (state->m_rombank!=1)
	56	m_rombank=data&0x0f;
	57	if (m_rombank!=1)
59	58	{
60		memory_set_bankptr(space->machine(), "bank4", space->machine().region("user1")->base() + (state->m_rombank << 14));
	59	memory_set_bankptr(machine(), "bank4", machine().region("user1")->base() + (m_rombank << 14));
61	60	}
62	61	else
63	62	{
64		memory_set_bankptr(space->machine(), "bank4", space->machine().region("user2")->base() + ((state->m_DFSType) << 14));
	63	memory_set_bankptr(machine(), "bank4", machine().region("user2")->base() + ((m_DFSType) << 14));
65	64	}
66	65	}
67	66
68	67
69		WRITE8_HANDLER ( bbc_memoryb3_w )
	68	WRITE8_MEMBER(bbc_state::bbc_memoryb3_w)
70	69	{
71		bbc_state *state = space->machine().driver_data<bbc_state>();
72		if (state->m_RAMSize)
	70	if (m_RAMSize)
73	71	{
74		space->machine().region("maincpu")->base()[offset + 0x4000] = data;
	72	machine().region("maincpu")->base()[offset + 0x4000] = data;
75	73	}
76	74	else
77	75	{
78		space->machine().region("maincpu")->base()[offset] = data;
	76	machine().region("maincpu")->base()[offset] = data;
79	77	}
80	78
81	79	}
r14963	r14964
90	88	static const unsigned short bbc_SWRAMtype2[16]={0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0};
91	89	static const unsigned short bbc_SWRAMtype3[16]={0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1};
92	90
93		WRITE8_HANDLER ( bbc_memoryb4_w )
	91	WRITE8_MEMBER(bbc_state::bbc_memoryb4_w)
94	92	{
95		bbc_state *state = space->machine().driver_data<bbc_state>();
96		if (state->m_rombank == 1)
	93	if (m_rombank == 1)
97	94	{
98	95	// special DFS case for Acorn DFS E00 Hack that can write to the DFS RAM Bank;
99		if (state->m_DFSType == 3) space->machine().region("user2")->base()[((state->m_DFSType) << 14) + offset] = data;
	96	if (m_DFSType == 3) machine().region("user2")->base()[((m_DFSType) << 14) + offset] = data;
100	97	} else
101	98	{
102		switch (state->m_SWRAMtype)
	99	switch (m_SWRAMtype)
103	100	{
104		case 1:   if (bbc_SWRAMtype1[state->m_userport]) space->machine().region("user1")->base()[(state->m_userport << 14) + offset] = data;
105		case 2:   if (bbc_SWRAMtype2[state->m_rombank])  space->machine().region("user1")->base()[(state->m_rombank << 14) + offset] = data;
106		case 3:   if (bbc_SWRAMtype3[state->m_rombank])  space->machine().region("user1")->base()[(state->m_rombank << 14) + offset] = data;
	101	case 1:   if (bbc_SWRAMtype1[m_userport]) machine().region("user1")->base()[(m_userport << 14) + offset] = data;
	102	case 2:   if (bbc_SWRAMtype2[m_rombank])  machine().region("user1")->base()[(m_rombank << 14) + offset] = data;
	103	case 3:   if (bbc_SWRAMtype3[m_rombank])  machine().region("user1")->base()[(m_rombank << 14) + offset] = data;
107	104	}
108	105	}
109	106	}
r14963	r14964
130	127
131	128	/* the model B Plus addresses all 16 of the ROM sockets plus the extra 12K of ram at 0x8000
132	129	and 20K of shadow ram at 0x3000 */
133		WRITE8_HANDLER ( bbc_page_selectbp_w )
	130	WRITE8_MEMBER(bbc_state::bbc_page_selectbp_w)
134	131	{
135		bbc_state *state = space->machine().driver_data<bbc_state>();
136	132	if ((offset&0x04)==0)
137	133	{
138		state->m_pagedRAM = (data >> 7) & 0x01;
139		state->m_rombank =  data & 0x0f;
	134	m_pagedRAM = (data >> 7) & 0x01;
	135	m_rombank =  data & 0x0f;
140	136
141		if (state->m_pagedRAM)
	137	if (m_pagedRAM)
142	138	{
143	139	/* if paged ram then set 8000 to afff to read from the ram 8000 to afff */
144		memory_set_bankptr(space->machine(), "bank4", space->machine().region("maincpu")->base() + 0x8000);
	140	memory_set_bankptr(machine(), "bank4", machine().region("maincpu")->base() + 0x8000);
145	141	}
146	142	else
147	143	{
148	144	/* if paged rom then set the rom to be read from 8000 to afff */
149		memory_set_bankptr(space->machine(), "bank4", space->machine().region("user1")->base() + (state->m_rombank << 14));
	145	memory_set_bankptr(machine(), "bank4", machine().region("user1")->base() + (m_rombank << 14));
150	146	};
151	147
152	148	/* set the rom to be read from b000 to bfff */
153		memory_set_bank(space->machine(), "bank6", state->m_rombank);
	149	memory_set_bank(machine(), "bank6", m_rombank);
154	150	}
155	151	else
156	152	{
157	153	//the video display should now use this flag to display the shadow ram memory
158		state->m_vdusel=(data>>7)&0x01;
159		bbcbp_setvideoshadow(space->machine(), state->m_vdusel);
	154	m_vdusel=(data>>7)&0x01;
	155	bbcbp_setvideoshadow(machine(), m_vdusel);
160	156	//need to make the video display do a full screen refresh for the new memory area
161		memory_set_bankptr(space->machine(), "bank2", space->machine().region("maincpu")->base()+0x3000);
	157	memory_set_bankptr(machine(), "bank2", machine().region("maincpu")->base()+0x3000);
162	158	}
163	159	}
164	160
r14963	r14964
167	163	the writes to this memory are just done the normal
168	164	way */
169	165
170		WRITE8_HANDLER ( bbc_memorybp1_w )
	166	WRITE8_MEMBER(bbc_state::bbc_memorybp1_w)
171	167	{
172		space->machine().region("maincpu")->base()[offset]=data;
	168	machine().region("maincpu")->base()[offset]=data;
173	169	}
174	170
175	171
r14963	r14964
209	205	}
210	206
211	207
212		WRITE8_HANDLER ( bbc_memorybp2_w )
	208	WRITE8_MEMBER(bbc_state::bbc_memorybp2_w)
213	209	{
214		bbc_state *state = space->machine().driver_data<bbc_state>();
215		UINT8 *ram = space->machine().region("maincpu")->base();
216		if (state->m_vdusel==0)
	210	UINT8 *ram = machine().region("maincpu")->base();
	211	if (m_vdusel==0)
217	212	{
218	213	// not in shadow ram mode so just write to normal ram
219	214	ram[offset + 0x3000] = data;
220	215	}
221	216	else
222	217	{
223		if (vdudriverset(space->machine()))
	218	if (vdudriverset(machine()))
224	219	{
225	220	// if VDUDriver set then write to shadow ram
226	221	ram[offset + 0xb000] = data;
r14963	r14964
236	231
237	232	/* if the pagedRAM is set write to RAM between 0x8000 to 0xafff
238	233	otherwise this area contains ROM so no write is required */
239		WRITE8_HANDLER ( bbc_memorybp4_w )
	234	WRITE8_MEMBER(bbc_state::bbc_memorybp4_w)
240	235	{
241		bbc_state *state = space->machine().driver_data<bbc_state>();
242		if (state->m_pagedRAM)
	236	if (m_pagedRAM)
243	237	{
244		space->machine().region("maincpu")->base()[offset+0x8000]=data;
	238	machine().region("maincpu")->base()[offset+0x8000]=data;
245	239	}
246	240	}
247	241
r14963	r14964
257	251	static const unsigned short bbc_b_plus_sideways_ram_banks[16]={ 1,1,0,0,0,0,0,0,0,0,0,0,1,1,0,0 };
258	252
259	253
260		WRITE8_HANDLER ( bbc_memorybp4_128_w )
	254	WRITE8_MEMBER(bbc_state::bbc_memorybp4_128_w)
261	255	{
262		bbc_state *state = space->machine().driver_data<bbc_state>();
263		if (state->m_pagedRAM)
	256	if (m_pagedRAM)
264	257	{
265		space->machine().region("maincpu")->base()[offset+0x8000]=data;
	258	machine().region("maincpu")->base()[offset+0x8000]=data;
266	259	}
267	260	else
268	261	{
269		if (bbc_b_plus_sideways_ram_banks[state->m_rombank])
	262	if (bbc_b_plus_sideways_ram_banks[m_rombank])
270	263	{
271		space->machine().region("user1")->base()[offset+(state->m_rombank<<14)]=data;
	264	machine().region("user1")->base()[offset+(m_rombank<<14)]=data;
272	265	}
273	266	}
274	267	}
275	268
276		WRITE8_HANDLER ( bbc_memorybp6_128_w )
	269	WRITE8_MEMBER(bbc_state::bbc_memorybp6_128_w)
277	270	{
278		bbc_state *state = space->machine().driver_data<bbc_state>();
279		if (bbc_b_plus_sideways_ram_banks[state->m_rombank])
	271	if (bbc_b_plus_sideways_ram_banks[m_rombank])
280	272	{
281		space->machine().region("user1")->base()[offset+(state->m_rombank<<14)+0x3000]=data;
	273	machine().region("user1")->base()[offset+(m_rombank<<14)+0x3000]=data;
282	274	}
283	275	}
284	276
r14963	r14964
336	328	*/
337	329
338	330
339		READ8_HANDLER ( bbcm_ACCCON_read )
	331	READ8_MEMBER(bbc_state::bbcm_ACCCON_read)
340	332	{
341		bbc_state *state = space->machine().driver_data<bbc_state>();
342	333	logerror("ACCCON read %d\n",offset);
343		return state->m_ACCCON;
	334	return m_ACCCON;
344	335	}
345	336
346		WRITE8_HANDLER ( bbcm_ACCCON_write )
	337	WRITE8_MEMBER(bbc_state::bbcm_ACCCON_write)
347	338	{
348		bbc_state *state = space->machine().driver_data<bbc_state>();
349	339	int tempIRR;
350		state->m_ACCCON=data;
	340	m_ACCCON=data;
351	341
352	342	logerror("ACCCON write  %d %d \n",offset,data);
353	343
354		tempIRR=state->m_ACCCON_IRR;
	344	tempIRR=m_ACCCON_IRR;
355	345
356	346
357		state->m_ACCCON_IRR=(data>>7)&1;
358		state->m_ACCCON_TST=(data>>6)&1;
359		state->m_ACCCON_IFJ=(data>>5)&1;
360		state->m_ACCCON_ITU=(data>>4)&1;
361		state->m_ACCCON_Y  =(data>>3)&1;
362		state->m_ACCCON_X  =(data>>2)&1;
363		state->m_ACCCON_E  =(data>>1)&1;
364		state->m_ACCCON_D  =(data>>0)&1;
	347	m_ACCCON_IRR=(data>>7)&1;
	348	m_ACCCON_TST=(data>>6)&1;
	349	m_ACCCON_IFJ=(data>>5)&1;
	350	m_ACCCON_ITU=(data>>4)&1;
	351	m_ACCCON_Y  =(data>>3)&1;
	352	m_ACCCON_X  =(data>>2)&1;
	353	m_ACCCON_E  =(data>>1)&1;
	354	m_ACCCON_D  =(data>>0)&1;
365	355
366		if (tempIRR!=state->m_ACCCON_IRR)
	356	if (tempIRR!=m_ACCCON_IRR)
367	357	{
368		state->check_interrupts();
	358	check_interrupts();
369	359	}
370	360
371		if (state->m_ACCCON_Y)
	361	if (m_ACCCON_Y)
372	362	{
373		memory_set_bankptr(space->machine(), "bank7", space->machine().region("maincpu")->base() + 0x9000);
	363	memory_set_bankptr(machine(), "bank7", machine().region("maincpu")->base() + 0x9000);
374	364	}
375	365	else
376	366	{
377		memory_set_bankptr(space->machine(), "bank7", space->machine().region("user1")->base() + 0x40000);
	367	memory_set_bankptr(machine(), "bank7", machine().region("user1")->base() + 0x40000);
378	368	}
379	369
380		bbcbp_setvideoshadow(space->machine(), state->m_ACCCON_D);
	370	bbcbp_setvideoshadow(machine(), m_ACCCON_D);
381	371
382	372
383		if (state->m_ACCCON_X)
	373	if (m_ACCCON_X)
384	374	{
385		memory_set_bankptr(space->machine(), "bank2", space->machine().region( "maincpu" )->base() + 0xb000 );
	375	memory_set_bankptr(machine(), "bank2", machine().region( "maincpu" )->base() + 0xb000 );
386	376	}
387	377	else
388	378	{
389		memory_set_bankptr(space->machine(), "bank2", space->machine().region( "maincpu" )->base() + 0x3000 );
	379	memory_set_bankptr(machine(), "bank2", machine().region( "maincpu" )->base() + 0x3000 );
390	380	}
391	381
392	382	/* ACCCON_TST controls paging of rom reads in the 0xFC00-0xFEFF reigon */
393	383	/* if 0 the I/O is paged for both reads and writes */
394	384	/* if 1 the the ROM is paged in for reads but writes still go to I/O   */
395		if (state->m_ACCCON_TST)
	385	if (m_ACCCON_TST)
396	386	{
397		memory_set_bankptr(space->machine(), "bank8", space->machine().region("user1")->base()+0x43c00);
398		space->install_read_bank(0xFC00,0xFEFF,"bank8");
	387	memory_set_bankptr(machine(), "bank8", machine().region("user1")->base()+0x43c00);
	388	space.install_read_bank(0xFC00,0xFEFF,"bank8");
399	389	}
400	390	else
401	391	{
402		space->install_legacy_read_handler(0xFC00,0xFEFF,FUNC(bbcm_r));
	392	space.install_read_handler(0xFC00,0xFEFF,read8_delegate(FUNC(bbc_state::bbcm_r),this));
403	393	}
404	394
405	395	}
r14963	r14964
413	403	}
414	404
415	405
416		static WRITE8_HANDLER ( page_selectbm_w )
	406	WRITE8_MEMBER(bbc_state::page_selectbm_w)
417	407	{
418		bbc_state *state = space->machine().driver_data<bbc_state>();
419		state->m_pagedRAM = (data & 0x80) >> 7;
420		state->m_rombank = data & 0x0f;
	408	m_pagedRAM = (data & 0x80) >> 7;
	409	m_rombank = data & 0x0f;
421	410
422		if (state->m_pagedRAM)
	411	if (m_pagedRAM)
423	412	{
424		memory_set_bankptr(space->machine(), "bank4", space->machine().region("maincpu")->base() + 0x8000);
425		memory_set_bank(space->machine(), "bank5", state->m_rombank);
	413	memory_set_bankptr(machine(), "bank4", machine().region("maincpu")->base() + 0x8000);
	414	memory_set_bank(machine(), "bank5", m_rombank);
426	415	}
427	416	else
428	417	{
429		memory_set_bankptr(space->machine(), "bank4", space->machine().region("user1")->base() + ((state->m_rombank) << 14));
430		memory_set_bank(space->machine(), "bank5", state->m_rombank);
	418	memory_set_bankptr(machine(), "bank4", machine().region("user1")->base() + ((m_rombank) << 14));
	419	memory_set_bank(machine(), "bank5", m_rombank);
431	420	}
432	421	}
433	422
434	423
435	424
436		WRITE8_HANDLER ( bbc_memorybm1_w )
	425	WRITE8_MEMBER(bbc_state::bbc_memorybm1_w)
437	426	{
438		space->machine().region("maincpu")->base()[offset] = data;
	427	machine().region("maincpu")->base()[offset] = data;
439	428	}
440	429
441	430
r14963	r14964
463	452
464	453
465	454
466		WRITE8_HANDLER ( bbc_memorybm2_w )
	455	WRITE8_MEMBER(bbc_state::bbc_memorybm2_w)
467	456	{
468		bbc_state *state = space->machine().driver_data<bbc_state>();
469		UINT8 *ram = space->machine().region("maincpu")->base();
470		if (state->m_ACCCON_X)
	457	UINT8 *ram = machine().region("maincpu")->base();
	458	if (m_ACCCON_X)
471	459	{
472	460	ram[offset + 0xb000] = data;
473	461	}
474	462	else
475	463	{
476		if (state->m_ACCCON_E && bbcm_vdudriverset(space->machine()))
	464	if (m_ACCCON_E && bbcm_vdudriverset(machine()))
477	465	{
478	466	ram[offset + 0xb000] = data;
479	467	}
r14963	r14964
490	478	};
491	479
492	480
493		WRITE8_HANDLER ( bbc_memorybm4_w )
	481	WRITE8_MEMBER(bbc_state::bbc_memorybm4_w)
494	482	{
495		bbc_state *state = space->machine().driver_data<bbc_state>();
496		if (state->m_pagedRAM)
	483	if (m_pagedRAM)
497	484	{
498		space->machine().region("maincpu")->base()[offset+0x8000]=data;
	485	machine().region("maincpu")->base()[offset+0x8000]=data;
499	486	}
500	487	else
501	488	{
502		if (bbc_master_sideways_ram_banks[state->m_rombank])
	489	if (bbc_master_sideways_ram_banks[m_rombank])
503	490	{
504		space->machine().region("user1")->base()[offset+(state->m_rombank<<14)]=data;
	491	machine().region("user1")->base()[offset+(m_rombank<<14)]=data;
505	492	}
506	493	}
507	494	}
508	495
509	496
510		WRITE8_HANDLER ( bbc_memorybm5_w )
	497	WRITE8_MEMBER(bbc_state::bbc_memorybm5_w)
511	498	{
512		bbc_state *state = space->machine().driver_data<bbc_state>();
513		if (bbc_master_sideways_ram_banks[state->m_rombank])
	499	if (bbc_master_sideways_ram_banks[m_rombank])
514	500	{
515		space->machine().region("user1")->base()[offset+(state->m_rombank<<14)+0x1000]=data;
	501	machine().region("user1")->base()[offset+(m_rombank<<14)+0x1000]=data;
516	502	}
517	503	}
518	504
519	505
520		WRITE8_HANDLER ( bbc_memorybm7_w )
	506	WRITE8_MEMBER(bbc_state::bbc_memorybm7_w)
521	507	{
522		bbc_state *state = space->machine().driver_data<bbc_state>();
523		if (state->m_ACCCON_Y)
	508	if (m_ACCCON_Y)
524	509	{
525		space->machine().region("maincpu")->base()[offset+0x9000]=data;
	510	machine().region("maincpu")->base()[offset+0x9000]=data;
526	511	}
527	512	}
528	513
r14963	r14964
550	535	&E0-&FF Tube ULA        Tube system interface   Tube system interface   32 (32 bytes x  1 ) 2MHz
551	536	******************************************************************************/
552	537
553		READ8_HANDLER ( bbcm_r )
	538	READ8_MEMBER(bbc_state::bbcm_r)
554	539	{
555		//bbc_state *state = space->machine().driver_data<bbc_state>();
556	540	long myo;
557	541
558	542	/* Now handled in bbcm_ACCCON_write PHS - 2008-10-11 */
559		//  if ( state->m_ACCCON_TST )
	543	//  if ( m_ACCCON_TST )
560	544	//  {
561		//      return space->machine().region("user1")->base()[offset+0x43c00];
	545	//      return machine().region("user1")->base()[offset+0x43c00];
562	546	//  };
563	547
564	548	if (offset<=0x0ff) /* FRED */
r14963	r14964
574	558
575	559	if ((offset>=0x200) && (offset<=0x2ff)) /* SHEILA */
576	560	{
577		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
578		via6522_device *via_1 = space->machine().device<via6522_device>("via6522_1");
	561	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	562	via6522_device *via_1 = machine().device<via6522_device>("via6522_1");
579	563
580	564	myo=offset-0x200;
581	565	if ((myo>=0x00) && (myo<=0x07)) return bbc_6845_r(space, myo-0x00);      /* Video Controller */
582	566	if ((myo>=0x08) && (myo<=0x0f))
583	567	{
584		acia6850_device *acia = space->machine().device<acia6850_device>("acia6850");
	568	acia6850_device *acia = machine().device<acia6850_device>("acia6850");
585	569
586	570	if ((myo - 0x08) & 1)
587		return acia->status_read(*space,0);
	571	return acia->status_read(space,0);
588	572	else
589		return acia->data_read(*space,0);
	573	return acia->data_read(space,0);
590	574	}
591	575	if ((myo>=0x10) && (myo<=0x17)) return 0xfe;                  /* Serial System Chip */
592		if ((myo>=0x18) && (myo<=0x1f)) return uPD7002_r(space->machine().device("upd7002"), myo-0x18);         /* A to D converter */
	576	if ((myo>=0x18) && (myo<=0x1f)) return uPD7002_r(machine().device("upd7002"), myo-0x18);         /* A to D converter */
593	577	if ((myo>=0x20) && (myo<=0x23)) return 0xfe;                  /* VideoULA */
594	578	if ((myo>=0x24) && (myo<=0x27)) return bbcm_wd1770l_read(space, myo-0x24); /* 1770 */
595	579	if ((myo>=0x28) && (myo<=0x2f)) return bbcm_wd1770_read(space, myo-0x28);  /* disc control latch */
596	580	if ((myo>=0x30) && (myo<=0x33)) return 0xfe;                  /* page select */
597	581	if ((myo>=0x34) && (myo<=0x37)) return bbcm_ACCCON_read(space, myo-0x34);   /* ACCCON */
598	582	if ((myo>=0x38) && (myo<=0x3f)) return 0xfe;                  /* NC ?? */
599		if ((myo>=0x40) && (myo<=0x5f)) return via_0->read(*space,myo-0x40);
600		if ((myo>=0x60) && (myo<=0x7f)) return via_1->read(*space,myo-0x60);
	583	if ((myo>=0x40) && (myo<=0x5f)) return via_0->read(space,myo-0x40);
	584	if ((myo>=0x60) && (myo<=0x7f)) return via_1->read(space,myo-0x60);
601	585	if ((myo>=0x80) && (myo<=0x9f)) return 0xfe;
602	586	if ((myo>=0xa0) && (myo<=0xbf)) return 0xfe;
603	587	if ((myo>=0xc0) && (myo<=0xdf)) return 0xfe;
r14963	r14964
607	591	return 0xfe;
608	592	}
609	593
610		WRITE8_HANDLER ( bbcm_w )
	594	WRITE8_MEMBER(bbc_state::bbcm_w)
611	595	{
612		//bbc_state *state = space->machine().driver_data<bbc_state>();
613	596	long myo;
614	597
615	598	if ((offset>=0x200) && (offset<=0x2ff)) /* SHEILA */
616	599	{
617		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
618		via6522_device *via_1 = space->machine().device<via6522_device>("via6522_1");
	600	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	601	via6522_device *via_1 = machine().device<via6522_device>("via6522_1");
619	602
620	603	myo=offset-0x200;
621	604	if ((myo>=0x00) && (myo<=0x07)) bbc_6845_w(space, myo-0x00,data);         /* Video Controller */
622	605	if ((myo>=0x08) && (myo<=0x0f))
623	606	{
624		acia6850_device *acia = space->machine().device<acia6850_device>("acia6850");
	607	acia6850_device *acia = machine().device<acia6850_device>("acia6850");
625	608
626	609	if ((myo - 0x08) & 1)
627		acia->control_write(*space, 0, data);
	610	acia->control_write(space, 0, data);
628	611	else
629		acia->data_write(*space, 0, data);
	612	acia->data_write(space, 0, data);
630	613	}
631	614	if ((myo>=0x10) && (myo<=0x17)) bbc_SerialULA_w(space, myo-0x10,data);      /* Serial System Chip */
632		if ((myo>=0x18) && (myo<=0x1f)) uPD7002_w(space->machine().device("upd7002"),myo-0x18,data);         /* A to D converter */
	615	if ((myo>=0x18) && (myo<=0x1f)) uPD7002_w(machine().device("upd7002"),myo-0x18,data);         /* A to D converter */
633	616	if ((myo>=0x20) && (myo<=0x23)) bbc_videoULA_w(space, myo-0x20,data);         /* VideoULA */
634	617	if ((myo>=0x24) && (myo<=0x27)) bbcm_wd1770l_write(space, myo-0x24,data);   /* 1770 */
635	618	if ((myo>=0x28) && (myo<=0x2f)) bbcm_wd1770_write(space, myo-0x28,data);   /* disc control latch */
636	619	if ((myo>=0x30) && (myo<=0x33)) page_selectbm_w(space, myo-0x30,data);      /* page select */
637	620	if ((myo>=0x34) && (myo<=0x37)) bbcm_ACCCON_write(space, myo-0x34,data);   /* ACCCON */
638	621	//if ((myo>=0x38) && (myo<=0x3f))                                   /* NC ?? */
639		if ((myo>=0x40) && (myo<=0x5f)) via_0->write(*space,myo-0x40, data);
640		if ((myo>=0x60) && (myo<=0x7f)) via_1->write(*space,myo-0x60, data);
	622	if ((myo>=0x40) && (myo<=0x5f)) via_0->write(space,myo-0x40, data);
	623	if ((myo>=0x60) && (myo<=0x7f)) via_1->write(space,myo-0x60, data);
641	624	//if ((myo>=0x80) && (myo<=0x9f))
642	625	//if ((myo>=0xa0) && (myo<=0xbf))
643	626	//if ((myo>=0xc0) && (myo<=0xdf))
r14963	r14964
1416	1399
1417	1400
1418	1401
1419		WRITE8_HANDLER ( bbc_SerialULA_w )
	1402	WRITE8_MEMBER(bbc_state::bbc_SerialULA_w)
1420	1403	{
1421		BBC_Cassette_motor(space->machine(), (data & 0x80) >> 7);
	1404	BBC_Cassette_motor(machine(), (data & 0x80) >> 7);
1422	1405	}
1423	1406
1424	1407	/**************************************
r14963	r14964
1457	1440	};
1458	1441
1459	1442
1460		static READ8_HANDLER( bbc_i8271_read )
	1443	READ8_MEMBER(bbc_state::bbc_i8271_read)
1461	1444	{
1462	1445	int ret;
1463		device_t *i8271 = space->machine().device("i8271");
	1446	device_t *i8271 = machine().device("i8271");
1464	1447	logerror("i8271 read %d  ",offset);
1465	1448	switch (offset)
1466	1449	{
r14963	r14964
1484	1467	return ret;
1485	1468	}
1486	1469
1487		static WRITE8_HANDLER( bbc_i8271_write )
	1470	WRITE8_MEMBER(bbc_state::bbc_i8271_write)
1488	1471	{
1489		device_t *i8271 = space->machine().device("i8271");
	1472	device_t *i8271 = machine().device("i8271");
1490	1473	logerror("i8271 write  %d  %d\n",offset,data);
1491	1474
1492	1475	switch (offset)
r14963	r14964
1605	1588	{FLOPPY_0, FLOPPY_1, NULL, NULL}
1606	1589	};
1607	1590
1608		static WRITE8_HANDLER(bbc_wd177x_status_w)
	1591	WRITE8_MEMBER(bbc_state::bbc_wd177x_status_w)
1609	1592	{
1610		bbc_state *state = space->machine().driver_data<bbc_state>();
1611		device_t *fdc = space->machine().device("wd177x");
1612		state->m_drive_control = data;
	1593	device_t *fdc = machine().device("wd177x");
	1594	m_drive_control = data;
1613	1595
1614	1596	/* set drive */
1615	1597	if ((data>>0) & 0x01) wd17xx_set_drive(fdc,0);
r14963	r14964
1621	1603	/* set density */
1622	1604	wd17xx_dden_w(fdc, BIT(data, 3));
1623	1605
1624		state->m_1770_IntEnabled=(((data>>4) & 0x01)==0);
	1606	m_1770_IntEnabled=(((data>>4) & 0x01)==0);
1625	1607
1626	1608	}
1627	1609
1628	1610
1629	1611
1630		READ8_HANDLER ( bbc_wd1770_read )
	1612	READ8_MEMBER(bbc_state::bbc_wd1770_read)
1631	1613	{
1632	1614	int retval=0xff;
1633		device_t *fdc = space->machine().device("wd177x");
	1615	device_t *fdc = machine().device("wd177x");
1634	1616	switch (offset)
1635	1617	{
1636	1618	case 4:
r14963	r14964
1653	1635	return retval;
1654	1636	}
1655	1637
1656		WRITE8_HANDLER ( bbc_wd1770_write )
	1638	WRITE8_MEMBER(bbc_state::bbc_wd1770_write)
1657	1639	{
1658		device_t *fdc = space->machine().device("wd177x");
	1640	device_t *fdc = machine().device("wd177x");
1659	1641	logerror("wd177x write: $%02X  $%02X\n", offset,data);
1660	1642	switch (offset)
1661	1643	{
r14963	r14964
1716	1698	**********************************************/
1717	1699
1718	1700
1719		static WRITE8_HANDLER( bbc_opus_status_w )
	1701	WRITE8_MEMBER(bbc_state::bbc_opus_status_w)
1720	1702	{
1721		bbc_state *state = space->machine().driver_data<bbc_state>();
1722		device_t *fdc = space->machine().device("wd177x");
1723		state->m_drive_control = data;
	1703	device_t *fdc = machine().device("wd177x");
	1704	m_drive_control = data;
1724	1705
1725	1706	/* set drive */
1726	1707	if ((data>>1) & 0x01) wd17xx_set_drive(fdc,0);
r14963	r14964
1732	1713	/* set density */
1733	1714	wd17xx_dden_w(fdc, BIT(data, 5));
1734	1715
1735		state->m_1770_IntEnabled=(data>>4) & 0x01;
	1716	m_1770_IntEnabled=(data>>4) & 0x01;
1736	1717
1737	1718	}
1738	1719
1739		READ8_HANDLER( bbc_opus_read )
	1720	READ8_MEMBER(bbc_state::bbc_opus_read)
1740	1721	{
1741		bbc_state *state = space->machine().driver_data<bbc_state>();
1742		device_t *fdc = space->machine().device("wd177x");
	1722	device_t *fdc = machine().device("wd177x");
1743	1723	logerror("wd177x read: $%02X\n", offset);
1744	1724
1745		if (state->m_DFSType==6)
	1725	if (m_DFSType==6)
1746	1726	{
1747	1727	if (offset<0x100)
1748	1728	{
r14963	r14964
1761	1741	}
1762	1742	else
1763	1743	{
1764		return space->machine().region("disks")->base()[offset + (state->m_opusbank << 8)];
	1744	return machine().region("disks")->base()[offset + (m_opusbank << 8)];
1765	1745	}
1766	1746	}
1767	1747	return 0xff;
1768	1748	}
1769	1749
1770		WRITE8_HANDLER (bbc_opus_write)
	1750	WRITE8_MEMBER(bbc_state::bbc_opus_write)
1771	1751	{
1772		bbc_state *state = space->machine().driver_data<bbc_state>();
1773		device_t *fdc = space->machine().device("wd177x");
	1752	device_t *fdc = machine().device("wd177x");
1774	1753	logerror("wd177x write: $%02X  $%02X\n", offset,data);
1775	1754
1776		if (state->m_DFSType==6)
	1755	if (m_DFSType==6)
1777	1756	{
1778	1757	if (offset<0x100)
1779	1758	{
r14963	r14964
1795	1774	bbc_opus_status_w(space, 0,data);
1796	1775	break;
1797	1776	case 0xfe:
1798		state->m_opusbank=(state->m_opusbank & 0xff) | (data<<8);
	1777	m_opusbank=(m_opusbank & 0xff) | (data<<8);
1799	1778	break;
1800	1779	case 0xff:
1801		state->m_opusbank=(state->m_opusbank & 0xff00) | data;
	1780	m_opusbank=(m_opusbank & 0xff00) | data;
1802	1781	break;
1803	1782	}
1804	1783	}
1805	1784	else
1806	1785	{
1807		space->machine().region("disks")->base()[offset + (state->m_opusbank << 8)] = data;
	1786	machine().region("disks")->base()[offset + (m_opusbank << 8)] = data;
1808	1787	}
1809	1788	}
1810	1789	}
r14963	r14964
1815	1794	***************************************/
1816	1795
1817	1796
1818		READ8_HANDLER ( bbcm_wd1770_read )
	1797	READ8_MEMBER(bbc_state::bbcm_wd1770_read)
1819	1798	{
1820	1799	int retval=0xff;
1821		device_t *fdc = space->machine().device("wd177x");
	1800	device_t *fdc = machine().device("wd177x");
1822	1801	switch (offset)
1823	1802	{
1824	1803	case 0:
r14963	r14964
1840	1819	}
1841	1820
1842	1821
1843		WRITE8_HANDLER ( bbcm_wd1770_write )
	1822	WRITE8_MEMBER(bbc_state::bbcm_wd1770_write)
1844	1823	{
1845		device_t *fdc = space->machine().device("wd177x");
	1824	device_t *fdc = machine().device("wd177x");
1846	1825	//logerror("wd177x write: $%02X  $%02X\n", offset,data);
1847	1826	switch (offset)
1848	1827	{
r14963	r14964
1864	1843	}
1865	1844
1866	1845
1867		READ8_HANDLER ( bbcm_wd1770l_read )
	1846	READ8_MEMBER(bbc_state::bbcm_wd1770l_read)
1868	1847	{
1869		bbc_state *state = space->machine().driver_data<bbc_state>();
1870		return state->m_drive_control;
	1848	return m_drive_control;
1871	1849	}
1872	1850
1873		WRITE8_HANDLER ( bbcm_wd1770l_write )
	1851	WRITE8_MEMBER(bbc_state::bbcm_wd1770l_write)
1874	1852	{
1875		bbc_state *state = space->machine().driver_data<bbc_state>();
1876		device_t *fdc = space->machine().device("wd177x");
1877		state->m_drive_control = data;
	1853	device_t *fdc = machine().device("wd177x");
	1854	m_drive_control = data;
1878	1855
1879	1856	/* set drive */
1880	1857	if ((data>>0) & 0x01) wd17xx_set_drive(fdc,0);
r14963	r14964
1886	1863	/* set density */
1887	1864	wd17xx_dden_w(fdc, BIT(data, 5));
1888	1865
1889		//  state->m_1770_IntEnabled=(((data>>4) & 0x01)==0);
1890		state->m_1770_IntEnabled=1;
	1866	//  m_1770_IntEnabled=(((data>>4) & 0x01)==0);
	1867	m_1770_IntEnabled=1;
1891	1868
1892	1869	}
1893	1870
r14963	r14964
1896	1873	DFS Hardware mapping for different Disc Controller types
1897	1874	***************************************/
1898	1875
1899		READ8_HANDLER( bbc_disc_r )
	1876	READ8_MEMBER(bbc_state::bbc_disc_r)
1900	1877	{
1901		bbc_state *state = space->machine().driver_data<bbc_state>();
1902		switch (state->m_DFSType){
	1878	switch (m_DFSType){
1903	1879	/* case 0 to 3 are all standard 8271 interfaces */
1904	1880	case 0: case 1: case 2: case 3:
1905	1881	return bbc_i8271_read(space, offset);
r14963	r14964
1920	1896	return 0x0ff;
1921	1897	}
1922	1898
1923		WRITE8_HANDLER ( bbc_disc_w )
	1899	WRITE8_MEMBER(bbc_state::bbc_disc_w)
1924	1900	{
1925		bbc_state *state = space->machine().driver_data<bbc_state>();
1926		switch (state->m_DFSType){
	1901	switch (m_DFSType){
1927	1902	/* case 0 to 3 are all standard 8271 interfaces */
1928	1903	case 0: case 1: case 2: case 3:
1929	1904	bbc_i8271_write(space, offset,data);

src/mess/machine/gb.c

r14963	r14964
66	66	#define CGB_START_VRAM_BANKS   0x0000
67	67	#define CGB_START_RAM_BANKS   ( 2 * 8 * 1024 )
68	68
69		#define JOYPAD      state->m_gb_io[0x00]   /* Joystick: 1.1.P15.P14.P13.P12.P11.P10       */
70		#define SIODATA      state->m_gb_io[0x01]   /* Serial IO data buffer                       */
71		#define SIOCONT      state->m_gb_io[0x02]   /* Serial IO control register                  */
72		#define DIVREG      state->m_gb_io[0x04]   /* Divider register (???)                      */
73		#define TIMECNT      state->m_gb_io[0x05]   /* Timer counter. Gen. int. when it overflows  */
74		#define TIMEMOD      state->m_gb_io[0x06]   /* New value of TimeCount after it overflows   */
75		#define TIMEFRQ      state->m_gb_io[0x07]   /* Timer frequency and start/stop switch       */
	69	#define JOYPAD      m_gb_io[0x00]   /* Joystick: 1.1.P15.P14.P13.P12.P11.P10       */
	70	#define SIODATA      m_gb_io[0x01]   /* Serial IO data buffer                       */
	71	#define SIOCONT      m_gb_io[0x02]   /* Serial IO control register                  */
	72	#define DIVREG      m_gb_io[0x04]   /* Divider register (???)                      */
	73	#define TIMECNT      m_gb_io[0x05]   /* Timer counter. Gen. int. when it overflows  */
	74	#define TIMEMOD      m_gb_io[0x06]   /* New value of TimeCount after it overflows   */
	75	#define TIMEFRQ      m_gb_io[0x07]   /* Timer frequency and start/stop switch       */
76	76
77	77
78	78
r14963	r14964
82	82
83	83	static TIMER_CALLBACK(gb_serial_timer_proc);
84	84	static void gb_machine_stop(running_machine &machine);
85		static WRITE8_HANDLER( gb_rom_bank_select_mbc1 );
86		static WRITE8_HANDLER( gb_ram_bank_select_mbc1 );
87		static WRITE8_HANDLER( gb_mem_mode_select_mbc1 );
88		static WRITE8_HANDLER( gb_rom_bank_select_mbc2 );
89		static WRITE8_HANDLER( gb_rom_bank_select_mbc3 );
90		static WRITE8_HANDLER( gb_ram_bank_select_mbc3 );
91		static WRITE8_HANDLER( gb_mem_mode_select_mbc3 );
92		static WRITE8_HANDLER( gb_rom_bank_select_mbc5 );
93		static WRITE8_HANDLER( gb_ram_bank_select_mbc5 );
94		static WRITE8_HANDLER( gb_ram_bank_select_mbc6 );
95		static WRITE8_HANDLER( gb_rom_bank_select_mbc6_1 );
96		static WRITE8_HANDLER( gb_rom_bank_select_mbc6_2 );
97		static WRITE8_HANDLER( gb_rom_bank_select_mbc7 );
98		static WRITE8_HANDLER( gb_rom_bank_unknown_mbc7 );
99		static WRITE8_HANDLER( gb_ram_tama5 );
100		static WRITE8_HANDLER( gb_rom_bank_select_wisdom );
101		static WRITE8_HANDLER( gb_rom_bank_mmm01_0000_w );
102		static WRITE8_HANDLER( gb_rom_bank_mmm01_2000_w );
103		static WRITE8_HANDLER( gb_rom_bank_mmm01_4000_w );
104		static WRITE8_HANDLER( gb_rom_bank_mmm01_6000_w );
105		static WRITE8_HANDLER( gb_rom_bank_select_mbc1_kor );
106		static WRITE8_HANDLER( gb_ram_bank_select_mbc1_kor );
107		static WRITE8_HANDLER( gb_mem_mode_select_mbc1_kor );
	85
	86
	87
	88
	89
	90
	91
	92
	93
	94
	95
	96
	97
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	107
108	108	static void gb_timer_increment( running_machine &machine );
109	109
110	110	#ifdef MAME_DEBUG
r14963	r14964
116	116	{
117	117	gb_state *state = machine.driver_data<gb_state>();
118	118	/* Initialize the registers */
119		SIODATA = 0x00;
120		SIOCONT = 0x7E;
	119	state->SIODATA = 0x00;
	120	state->SIOCONT = 0x7E;
121	121
122		gb_io_w( machine.device("maincpu")->memory().space(AS_PROGRAM ), 0x05, 0x00 );      /* TIMECNT */
123		gb_io_w( machine.device("maincpu")->memory().space(AS_PROGRAM ), 0x06, 0x00 );      /* TIMEMOD */
	122	state->gb_io_w( *machine.device("maincpu")->memory().space(AS_PROGRAM ), 0x05, 0x00 );      /* TIMECNT */
	123	state->gb_io_w( *machine.device("maincpu")->memory().space(AS_PROGRAM ), 0x06, 0x00 );      /* TIMEMOD */
124	124	}
125	125
126	126	static void gb_rom16_0000( running_machine &machine, UINT8 *addr )
r14963	r14964
178	178	case MBC_NONE:
179	179	break;
180	180	case MBC_MMM01:
181		space->install_legacy_write_handler( 0x0000, 0x1fff, FUNC(gb_rom_bank_mmm01_0000_w) );
182		space->install_legacy_write_handler( 0x2000, 0x3fff, FUNC(gb_rom_bank_mmm01_2000_w));
183		space->install_legacy_write_handler( 0x4000, 0x5fff, FUNC(gb_rom_bank_mmm01_4000_w));
184		space->install_legacy_write_handler( 0x6000, 0x7fff, FUNC(gb_rom_bank_mmm01_6000_w));
	181	space->install_write_handler( 0x0000, 0x1fff, write8_delegate(FUNC(gb_state::gb_rom_bank_mmm01_0000_w),state) );
	182	space->install_write_handler( 0x2000, 0x3fff, write8_delegate(FUNC(gb_state::gb_rom_bank_mmm01_2000_w),state));
	183	space->install_write_handler( 0x4000, 0x5fff, write8_delegate(FUNC(gb_state::gb_rom_bank_mmm01_4000_w),state));
	184	space->install_write_handler( 0x6000, 0x7fff, write8_delegate(FUNC(gb_state::gb_rom_bank_mmm01_6000_w),state));
185	185	break;
186	186	case MBC_MBC1:
187		space->install_legacy_write_handler( 0x0000, 0x1fff, FUNC(gb_ram_enable) );   /* We don't emulate RAM enable yet */
188		space->install_legacy_write_handler( 0x2000, 0x3fff, FUNC(gb_rom_bank_select_mbc1) );
189		space->install_legacy_write_handler( 0x4000, 0x5fff, FUNC(gb_ram_bank_select_mbc1) );
190		space->install_legacy_write_handler( 0x6000, 0x7fff, FUNC(gb_mem_mode_select_mbc1) );
	187	space->install_write_handler( 0x0000, 0x1fff, write8_delegate(FUNC(gb_state::gb_ram_enable),state) );   /* We don't emulate RAM enable yet */
	188	space->install_write_handler( 0x2000, 0x3fff, write8_delegate(FUNC(gb_state::gb_rom_bank_select_mbc1),state) );
	189	space->install_write_handler( 0x4000, 0x5fff, write8_delegate(FUNC(gb_state::gb_ram_bank_select_mbc1),state) );
	190	space->install_write_handler( 0x6000, 0x7fff, write8_delegate(FUNC(gb_state::gb_mem_mode_select_mbc1),state) );
191	191	break;
192	192	case MBC_MBC2:
193		space->install_legacy_write_handler( 0x2000, 0x3fff, FUNC(gb_rom_bank_select_mbc2) );
	193	space->install_write_handler( 0x2000, 0x3fff, write8_delegate(FUNC(gb_state::gb_rom_bank_select_mbc2),state) );
194	194	break;
195	195	case MBC_MBC3:
196	196	case MBC_HUC1:   /* Possibly wrong */
197	197	case MBC_HUC3:   /* Possibly wrong */
198		space->install_legacy_write_handler( 0x0000, 0x1fff, FUNC(gb_ram_enable) );   /* We don't emulate RAM enable yet */
199		space->install_legacy_write_handler( 0x2000, 0x3fff, FUNC(gb_rom_bank_select_mbc3) );
200		space->install_legacy_write_handler( 0x4000, 0x5fff, FUNC(gb_ram_bank_select_mbc3) );
201		space->install_legacy_write_handler( 0x6000, 0x7fff, FUNC(gb_mem_mode_select_mbc3) );
	198	space->install_write_handler( 0x0000, 0x1fff, write8_delegate(FUNC(gb_state::gb_ram_enable),state) );   /* We don't emulate RAM enable yet */
	199	space->install_write_handler( 0x2000, 0x3fff, write8_delegate(FUNC(gb_state::gb_rom_bank_select_mbc3),state) );
	200	space->install_write_handler( 0x4000, 0x5fff, write8_delegate(FUNC(gb_state::gb_ram_bank_select_mbc3),state) );
	201	space->install_write_handler( 0x6000, 0x7fff, write8_delegate(FUNC(gb_state::gb_mem_mode_select_mbc3),state) );
202	202	break;
203	203	case MBC_MBC5:
204		space->install_legacy_write_handler( 0x0000, 0x1fff, FUNC(gb_ram_enable) );
205		space->install_legacy_write_handler( 0x2000, 0x3fff, FUNC(gb_rom_bank_select_mbc5) );
206		space->install_legacy_write_handler( 0x4000, 0x5fff, FUNC(gb_ram_bank_select_mbc5) );
	204	space->install_write_handler( 0x0000, 0x1fff, write8_delegate(FUNC(gb_state::gb_ram_enable),state) );
	205	space->install_write_handler( 0x2000, 0x3fff, write8_delegate(FUNC(gb_state::gb_rom_bank_select_mbc5),state) );
	206	space->install_write_handler( 0x4000, 0x5fff, write8_delegate(FUNC(gb_state::gb_ram_bank_select_mbc5),state) );
207	207	break;
208	208	case MBC_MBC6:
209		space->install_legacy_write_handler( 0x0000, 0x1fff, FUNC(gb_ram_bank_select_mbc6) );
210		space->install_legacy_write_handler( 0x2000, 0x2fff, FUNC(gb_rom_bank_select_mbc6_1) );
211		space->install_legacy_write_handler( 0x3000, 0x3fff, FUNC(gb_rom_bank_select_mbc6_2) );
	209	space->install_write_handler( 0x0000, 0x1fff, write8_delegate(FUNC(gb_state::gb_ram_bank_select_mbc6),state) );
	210	space->install_write_handler( 0x2000, 0x2fff, write8_delegate(FUNC(gb_state::gb_rom_bank_select_mbc6_1),state) );
	211	space->install_write_handler( 0x3000, 0x3fff, write8_delegate(FUNC(gb_state::gb_rom_bank_select_mbc6_2),state) );
212	212	break;
213	213	case MBC_MBC7:
214		space->install_legacy_write_handler( 0x0000, 0x1fff, FUNC(gb_ram_enable) );
215		space->install_legacy_write_handler( 0x2000, 0x2fff, FUNC(gb_rom_bank_select_mbc7) );
216		space->install_legacy_write_handler( 0x3000, 0x7fff, FUNC(gb_rom_bank_unknown_mbc7) );
	214	space->install_write_handler( 0x0000, 0x1fff, write8_delegate(FUNC(gb_state::gb_ram_enable),state) );
	215	space->install_write_handler( 0x2000, 0x2fff, write8_delegate(FUNC(gb_state::gb_rom_bank_select_mbc7),state) );
	216	space->install_write_handler( 0x3000, 0x7fff, write8_delegate(FUNC(gb_state::gb_rom_bank_unknown_mbc7),state) );
217	217	break;
218	218	case MBC_TAMA5:
219		space->install_legacy_write_handler( 0xA000, 0xBFFF, FUNC(gb_ram_tama5) );
	219	space->install_write_handler( 0xA000, 0xBFFF, write8_delegate(FUNC(gb_state::gb_ram_tama5),state) );
220	220	break;
221	221	case MBC_WISDOM:
222		space->install_legacy_write_handler( 0x0000, 0x3fff, FUNC(gb_rom_bank_select_wisdom) );
	222	space->install_write_handler( 0x0000, 0x3fff, write8_delegate(FUNC(gb_state::gb_rom_bank_select_wisdom),state) );
223	223	break;
224	224	case MBC_MBC1_KOR:
225		space->install_legacy_write_handler( 0x0000, 0x1fff, FUNC(gb_ram_enable) ); /* We don't emulate RAM enable yet */
226		space->install_legacy_write_handler( 0x2000, 0x3fff, FUNC(gb_rom_bank_select_mbc1_kor) );
227		space->install_legacy_write_handler( 0x4000, 0x5fff, FUNC(gb_ram_bank_select_mbc1_kor) );
228		space->install_legacy_write_handler( 0x6000, 0x7fff, FUNC(gb_mem_mode_select_mbc1_kor) );
	225	space->install_write_handler( 0x0000, 0x1fff, write8_delegate(FUNC(gb_state::gb_ram_enable),state) ); /* We don't emulate RAM enable yet */
	226	space->install_write_handler( 0x2000, 0x3fff, write8_delegate(FUNC(gb_state::gb_rom_bank_select_mbc1_kor),state) );
	227	space->install_write_handler( 0x4000, 0x5fff, write8_delegate(FUNC(gb_state::gb_ram_bank_select_mbc1_kor),state) );
	228	space->install_write_handler( 0x6000, 0x7fff, write8_delegate(FUNC(gb_state::gb_mem_mode_select_mbc1_kor),state) );
229	229	break;
230	230
231	231	case MBC_MEGADUCK:
232		space->install_legacy_write_handler( 0x0001, 0x0001, FUNC(megaduck_rom_bank_select_type1) );
233		space->install_legacy_write_handler( 0xB000, 0xB000, FUNC(megaduck_rom_bank_select_type2) );
	232	space->install_write_handler( 0x0001, 0x0001, write8_delegate(FUNC(gb_state::megaduck_rom_bank_select_type1),state) );
	233	space->install_write_handler( 0xB000, 0xB000, write8_delegate(FUNC(gb_state::megaduck_rom_bank_select_type2),state) );
234	234	break;
235	235	}
236	236
r14963	r14964
398	398	memory_set_bankptr( machine, "bank2", state->m_RAMMap[ state->m_MBC1Mode ? ( state->m_ROMBank >> 5 ) : 0 ] );
399	399	}
400	400
401		static WRITE8_HANDLER( gb_rom_bank_select_mbc1 )
	401	WRITE8_MEMBER(gb_state::gb_rom_bank_select_mbc1)
402	402	{
403		gb_state *state = space->machine().driver_data<gb_state>();
404	403	data &= 0x1F; /* Only uses lower 5 bits */
405	404	/* Selecting bank 0 == selecting bank 1 */
406	405	if( data == 0 )
407	406	data = 1;
408	407
409		state->m_ROMBank = ( state->m_ROMBank & 0x01E0 ) | data;
	408	m_ROMBank = ( m_ROMBank & 0x01E0 ) | data;
410	409	/* Switch banks */
411		gb_set_mbc1_banks(space->machine());
	410	gb_set_mbc1_banks(machine());
412	411	}
413	412
414		static WRITE8_HANDLER( gb_rom_bank_select_mbc2 )
	413	WRITE8_MEMBER(gb_state::gb_rom_bank_select_mbc2)
415	414	{
416		gb_state *state = space->machine().driver_data<gb_state>();
417	415	data &= 0x0F; /* Only uses lower 4 bits */
418	416	/* Selecting bank 0 == selecting bank 1 */
419	417	if( data == 0 )
r14963	r14964
421	419
422	420	/* The least significant bit of the upper address byte must be 1 */
423	421	if( offset & 0x0100 )
424		state->m_ROMBank = ( state->m_ROMBank & 0x100 ) | data;
	422	m_ROMBank = ( m_ROMBank & 0x100 ) | data;
425	423	/* Switch banks */
426		gb_rom16_4000( space->machine(), state->m_ROMMap[state->m_ROMBank] );
	424	gb_rom16_4000( machine(), m_ROMMap[m_ROMBank] );
427	425	}
428	426
429		static WRITE8_HANDLER( gb_rom_bank_select_mbc3 )
	427	WRITE8_MEMBER(gb_state::gb_rom_bank_select_mbc3)
430	428	{
431		gb_state *state = space->machine().driver_data<gb_state>();
432		logerror( "0x%04X: write to mbc3 rom bank select register 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), offset, data );
	429	logerror( "0x%04X: write to mbc3 rom bank select register 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), offset, data );
433	430	data &= 0x7F; /* Only uses lower 7 bits */
434	431	/* Selecting bank 0 == selecting bank 1 */
435	432	if( data == 0 )
436	433	data = 1;
437	434
438		state->m_ROMBank = ( state->m_ROMBank & 0x0100 ) | data;
	435	m_ROMBank = ( m_ROMBank & 0x0100 ) | data;
439	436	/* Switch banks */
440		gb_rom16_4000( space->machine(), state->m_ROMMap[state->m_ROMBank] );
	437	gb_rom16_4000( machine(), m_ROMMap[m_ROMBank] );
441	438	}
442	439
443		static WRITE8_HANDLER( gb_rom_bank_select_mbc5 )
	440	WRITE8_MEMBER(gb_state::gb_rom_bank_select_mbc5)
444	441	{
445		gb_state *state = space->machine().driver_data<gb_state>();
446	442	/* MBC5 has a 9 bit bank select
447	443	Writing into 2000-2FFF sets the lower 8 bits
448	444	Writing into 3000-3FFF sets the 9th bit
449	445	*/
450		logerror( "0x%04X: MBC5 ROM Bank select write 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), offset, data );
	446	logerror( "0x%04X: MBC5 ROM Bank select write 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), offset, data );
451	447	if( offset & 0x1000 )
452	448	{
453		state->m_ROMBank = (state->m_ROMBank & 0xFF ) | ( ( data & 0x01 ) << 8 );
	449	m_ROMBank = (m_ROMBank & 0xFF ) | ( ( data & 0x01 ) << 8 );
454	450	}
455	451	else
456	452	{
457		state->m_ROMBank = (state->m_ROMBank & 0x100 ) | data;
	453	m_ROMBank = (m_ROMBank & 0x100 ) | data;
458	454	}
459	455	/* Switch banks */
460		gb_rom16_4000( space->machine(), state->m_ROMMap[state->m_ROMBank] );
	456	gb_rom16_4000( machine(), m_ROMMap[m_ROMBank] );
461	457	}
462	458
463		static WRITE8_HANDLER( gb_ram_bank_select_mbc6 )
	459	WRITE8_MEMBER(gb_state::gb_ram_bank_select_mbc6)
464	460	{
465		logerror( "0x%04X: write to mbc6 ram enable area: %04X <- 0x%02X\n", cpu_get_pc( &space->device() ), offset, data );
	461	logerror( "0x%04X: write to mbc6 ram enable area: %04X <- 0x%02X\n", cpu_get_pc( &space.device() ), offset, data );
466	462	}
467	463
468		static WRITE8_HANDLER( gb_rom_bank_select_mbc6_1 )
	464	WRITE8_MEMBER(gb_state::gb_rom_bank_select_mbc6_1)
469	465	{
470		gb_state *state = space->machine().driver_data<gb_state>();
471		logerror( "0x%04X: write to mbc6 rom area: 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), 0x2000 + offset, data );
	466	logerror( "0x%04X: write to mbc6 rom area: 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), 0x2000 + offset, data );
472	467	if ( offset & 0x0800 )
473	468	{
474	469	if ( data == 0x00 )
475	470	{
476		gb_rom8_4000( space->machine(), state->m_ROMMap[state->m_ROMBank>>1] + ( ( state->m_ROMBank & 0x01 ) ? 0x2000 : 0x0000 ) );
	471	gb_rom8_4000( machine(), m_ROMMap[m_ROMBank>>1] + ( ( m_ROMBank & 0x01 ) ? 0x2000 : 0x0000 ) );
477	472	}
478	473	}
479	474	else
480	475	{
481		state->m_ROMBank = data;
	476	m_ROMBank = data;
482	477	}
483	478	}
484	479
485		static WRITE8_HANDLER( gb_rom_bank_select_mbc6_2 )
	480	WRITE8_MEMBER(gb_state::gb_rom_bank_select_mbc6_2)
486	481	{
487		gb_state *state = space->machine().driver_data<gb_state>();
488		logerror( "0x%04X: write to mbc6 rom area: 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), 0x3000 + offset, data );
	482	logerror( "0x%04X: write to mbc6 rom area: 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), 0x3000 + offset, data );
489	483	if ( offset & 0x0800 )
490	484	{
491	485	if ( data == 0x00 )
492	486	{
493		gb_rom8_6000( space->machine(), state->m_ROMMap[state->m_ROMBank00>>1] + ( ( state->m_ROMBank00 & 0x01 ) ? 0x2000 : 0x0000 ) );
	487	gb_rom8_6000( machine(), m_ROMMap[m_ROMBank00>>1] + ( ( m_ROMBank00 & 0x01 ) ? 0x2000 : 0x0000 ) );
494	488	}
495	489	}
496	490	else
497	491	{
498		state->m_ROMBank00 = data;
	492	m_ROMBank00 = data;
499	493	}
500	494	}
501	495
502		static WRITE8_HANDLER( gb_rom_bank_select_mbc7 )
	496	WRITE8_MEMBER(gb_state::gb_rom_bank_select_mbc7)
503	497	{
504		gb_state *state = space->machine().driver_data<gb_state>();
505		logerror( "0x%04X: write to mbc7 rom select register: 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), 0x2000 + offset, data );
	498	logerror( "0x%04X: write to mbc7 rom select register: 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), 0x2000 + offset, data );
506	499	/* Bit 12 must be set for writing to the mbc register */
507	500	if ( offset & 0x0100 )
508	501	{
509		state->m_ROMBank = data;
510		gb_rom16_4000( space->machine(), state->m_ROMMap[state->m_ROMBank] );
	502	m_ROMBank = data;
	503	gb_rom16_4000( machine(), m_ROMMap[m_ROMBank] );
511	504	}
512	505	}
513	506
514		static WRITE8_HANDLER( gb_rom_bank_unknown_mbc7 )
	507	WRITE8_MEMBER(gb_state::gb_rom_bank_unknown_mbc7)
515	508	{
516		logerror( "0x%04X: write to mbc7 rom area: 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), 0x3000 + offset, data );
	509	logerror( "0x%04X: write to mbc7 rom area: 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), 0x3000 + offset, data );
517	510	/* Bit 12 must be set for writing to the mbc register */
518	511	if ( offset & 0x0100 )
519	512	{
r14963	r14964
529	522	}
530	523	}
531	524
532		static WRITE8_HANDLER( gb_rom_bank_select_wisdom )
	525	WRITE8_MEMBER(gb_state::gb_rom_bank_select_wisdom)
533	526	{
534		gb_state *state = space->machine().driver_data<gb_state>();
535		logerror( "0x%04X: wisdom tree mapper write to address 0x%04X\n", cpu_get_pc( &space->device() ), offset );
	527	logerror( "0x%04X: wisdom tree mapper write to address 0x%04X\n", cpu_get_pc( &space.device() ), offset );
536	528	/* The address determines the bank to select */
537		state->m_ROMBank = ( offset << 1 ) & 0x1FF;
538		memory_set_bankptr( space->machine(), "bank5", state->m_ROMMap[ state->m_ROMBank ] );
539		memory_set_bankptr( space->machine(), "bank10", state->m_ROMMap[ state->m_ROMBank ] + 0x0100 );
540		gb_rom16_4000( space->machine(), state->m_ROMMap[ state->m_ROMBank + 1 ] );
	529	m_ROMBank = ( offset << 1 ) & 0x1FF;
	530	memory_set_bankptr( machine(), "bank5", m_ROMMap[ m_ROMBank ] );
	531	memory_set_bankptr( machine(), "bank10", m_ROMMap[ m_ROMBank ] + 0x0100 );
	532	gb_rom16_4000( machine(), m_ROMMap[ m_ROMBank + 1 ] );
541	533	}
542	534
543		static WRITE8_HANDLER( gb_ram_bank_select_mbc1 )
	535	WRITE8_MEMBER(gb_state::gb_ram_bank_select_mbc1)
544	536	{
545		gb_state *state = space->machine().driver_data<gb_state>();
546	537	data &= 0x3; /* Only uses the lower 2 bits */
547	538
548	539	/* Select the upper bits of the ROMMask */
549		state->m_ROMBank = ( state->m_ROMBank & 0x1F ) | ( data << 5 );
	540	m_ROMBank = ( m_ROMBank & 0x1F ) | ( data << 5 );
550	541
551	542	/* Switch banks */
552		gb_set_mbc1_banks(space->machine());
	543	gb_set_mbc1_banks(machine());
553	544	}
554	545
555		static WRITE8_HANDLER( gb_ram_bank_select_mbc3 )
	546	WRITE8_MEMBER(gb_state::gb_ram_bank_select_mbc3)
556	547	{
557		gb_state *state = space->machine().driver_data<gb_state>();
558		logerror( "0x%04X: write mbc3 ram bank select register 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), offset, data );
	548	logerror( "0x%04X: write mbc3 ram bank select register 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), offset, data );
559	549	if( data & 0x8 )
560	550	{   /* RTC banks */
561		if ( state->m_CartType & TIMER )
	551	if ( m_CartType & TIMER )
562	552	{
563		state->m_MBC3RTCBank = data & 0x07;
	553	m_MBC3RTCBank = data & 0x07;
564	554	if ( data < 5 )
565	555	{
566		memset( state->m_MBC3RTCData, state->m_MBC3RTCMap[state->m_MBC3RTCBank], 0x2000 );
567		memory_set_bankptr( space->machine(), "bank2", state->m_MBC3RTCData );
	556	memset( m_MBC3RTCData, m_MBC3RTCMap[m_MBC3RTCBank], 0x2000 );
	557	memory_set_bankptr( machine(), "bank2", m_MBC3RTCData );
568	558	}
569	559	}
570	560	}
571	561	else
572	562	{   /* RAM banks */
573		state->m_RAMBank = data & 0x3;
574		state->m_MBC3RTCBank = 0xFF;
	563	m_RAMBank = data & 0x3;
	564	m_MBC3RTCBank = 0xFF;
575	565	/* Switch banks */
576		memory_set_bankptr( space->machine(), "bank2", state->m_RAMMap[state->m_RAMBank] );
	566	memory_set_bankptr( machine(), "bank2", m_RAMMap[m_RAMBank] );
577	567	}
578	568	}
579	569
580		static WRITE8_HANDLER( gb_ram_bank_select_mbc5 )
	570	WRITE8_MEMBER(gb_state::gb_ram_bank_select_mbc5)
581	571	{
582		gb_state *state = space->machine().driver_data<gb_state>();
583		logerror( "0x%04X: MBC5 RAM Bank select write 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), offset, data );
	572	logerror( "0x%04X: MBC5 RAM Bank select write 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), offset, data );
584	573	data &= 0x0F;
585		if( state->m_CartType & RUMBLE )
	574	if( m_CartType & RUMBLE )
586	575	{
587	576	data &= 0x7;
588	577	}
589		state->m_RAMBank = data;
	578	m_RAMBank = data;
590	579	/* Switch banks */
591		memory_set_bankptr (space->machine(), "bank2", state->m_RAMMap[state->m_RAMBank] );
	580	memory_set_bankptr (machine(), "bank2", m_RAMMap[m_RAMBank] );
592	581	}
593	582
594		WRITE8_HANDLER ( gb_ram_enable )
	583	WRITE8_MEMBER(gb_state::gb_ram_enable)
595	584	{
596	585	/* FIXME: Currently we don't handle this, but a value of 0xA will enable
597	586	* writing to the cart's RAM banks */
598		logerror( "0x%04X: Write to ram enable register 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), offset, data );
	587	logerror( "0x%04X: Write to ram enable register 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), offset, data );
599	588	}
600	589
601		static WRITE8_HANDLER( gb_mem_mode_select_mbc1 )
	590	WRITE8_MEMBER(gb_state::gb_mem_mode_select_mbc1)
602	591	{
603		gb_state *state = space->machine().driver_data<gb_state>();
604		state->m_MBC1Mode = data & 0x1;
605		gb_set_mbc1_banks(space->machine());
	592	m_MBC1Mode = data & 0x1;
	593	gb_set_mbc1_banks(machine());
606	594	}
607	595
608		static WRITE8_HANDLER( gb_mem_mode_select_mbc3 )
	596	WRITE8_MEMBER(gb_state::gb_mem_mode_select_mbc3)
609	597	{
610		gb_state *state = space->machine().driver_data<gb_state>();
611		logerror( "0x%04X: Write to mbc3 mem mode select register 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), offset, data );
612		if( state->m_CartType & TIMER )
	598	logerror( "0x%04X: Write to mbc3 mem mode select register 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), offset, data );
	599	if( m_CartType & TIMER )
613	600	{
614	601	/* FIXME: RTC Latch goes here */
615		state->m_MBC3RTCMap[0] = 50;    /* Seconds */
616		state->m_MBC3RTCMap[1] = 40;    /* Minutes */
617		state->m_MBC3RTCMap[2] = 15;    /* Hours */
618		state->m_MBC3RTCMap[3] = 25;    /* Day counter lowest 8 bits */
619		state->m_MBC3RTCMap[4] = 0x01;  /* Day counter upper bit, timer off, no day overflow occurred (bit7) */
	602	m_MBC3RTCMap[0] = 50;    /* Seconds */
	603	m_MBC3RTCMap[1] = 40;    /* Minutes */
	604	m_MBC3RTCMap[2] = 15;    /* Hours */
	605	m_MBC3RTCMap[3] = 25;    /* Day counter lowest 8 bits */
	606	m_MBC3RTCMap[4] = 0x01;  /* Day counter upper bit, timer off, no day overflow occurred (bit7) */
620	607	}
621	608	}
622	609
623		static WRITE8_HANDLER( gb_ram_tama5 )
	610	WRITE8_MEMBER(gb_state::gb_ram_tama5)
624	611	{
625		gb_state *state = space->machine().driver_data<gb_state>();
626		logerror( "0x%04X: TAMA5 write 0x%04X <- 0x%02X\n", cpu_get_pc( &space->device() ), 0xA000 + offset, data );
	612	logerror( "0x%04X: TAMA5 write 0x%04X <- 0x%02X\n", cpu_get_pc( &space.device() ), 0xA000 + offset, data );
627	613	switch( offset & 0x0001 )
628	614	{
629	615	case 0x0000:    /* Write to data register */
630		switch( state->m_gbLastTama5Command )
	616	switch( m_gbLastTama5Command )
631	617	{
632	618	case 0x00:      /* Bits 0-3 for rom bank selection */
633		state->m_ROMBank = ( state->m_ROMBank & 0xF0 ) | ( data & 0x0F );
634		gb_rom16_4000( space->machine(), state->m_ROMMap[state->m_ROMBank] );
	619	m_ROMBank = ( m_ROMBank & 0xF0 ) | ( data & 0x0F );
	620	gb_rom16_4000( machine(), m_ROMMap[m_ROMBank] );
635	621	break;
636	622	case 0x01:      /* Bit 4(-7?) for rom bank selection */
637		state->m_ROMBank = ( state->m_ROMBank & 0x0F ) | ( ( data & 0x0F ) << 4 );
638		gb_rom16_4000( space->machine(), state->m_ROMMap[state->m_ROMBank] );
	623	m_ROMBank = ( m_ROMBank & 0x0F ) | ( ( data & 0x0F ) << 4 );
	624	gb_rom16_4000( machine(), m_ROMMap[m_ROMBank] );
639	625	break;
640	626	case 0x04:      /* Data to write lo */
641		state->m_gbTama5Byte = ( state->m_gbTama5Byte & 0xF0 ) | ( data & 0x0F );
	627	m_gbTama5Byte = ( m_gbTama5Byte & 0xF0 ) | ( data & 0x0F );
642	628	break;
643	629	case 0x05:      /* Data to write hi */
644		state->m_gbTama5Byte = ( state->m_gbTama5Byte & 0x0F ) | ( ( data & 0x0F ) << 4 );
	630	m_gbTama5Byte = ( m_gbTama5Byte & 0x0F ) | ( ( data & 0x0F ) << 4 );
645	631	break;
646	632	case 0x06:      /* Address selection hi */
647		state->m_gbTama5Address = ( state->m_gbTama5Address & 0x0F ) | ( ( data & 0x0F ) << 4 );
	633	m_gbTama5Address = ( m_gbTama5Address & 0x0F ) | ( ( data & 0x0F ) << 4 );
648	634	break;
649	635	case 0x07:      /* Address selection lo */
650	636	/* This address always seems to written last, so we'll just
651	637	execute the command here */
652		state->m_gbTama5Address = ( state->m_gbTama5Address & 0xF0 ) | ( data & 0x0F );
653		switch ( state->m_gbTama5Address & 0xE0 )
	638	m_gbTama5Address = ( m_gbTama5Address & 0xF0 ) | ( data & 0x0F );
	639	switch ( m_gbTama5Address & 0xE0 )
654	640	{
655	641	case 0x00:      /* Write memory */
656		logerror( "Write tama5 memory 0x%02X <- 0x%02X\n", state->m_gbTama5Address & 0x1F, state->m_gbTama5Byte );
657		state->m_gbTama5Memory[ state->m_gbTama5Address & 0x1F ] = state->m_gbTama5Byte;
	642	logerror( "Write tama5 memory 0x%02X <- 0x%02X\n", m_gbTama5Address & 0x1F, m_gbTama5Byte );
	643	m_gbTama5Memory[ m_gbTama5Address & 0x1F ] = m_gbTama5Byte;
658	644	break;
659	645	case 0x20:      /* Read memory */
660		logerror( "Read tama5 memory 0x%02X\n", state->m_gbTama5Address & 0x1F );
661		state->m_gbTama5Byte = state->m_gbTama5Memory[ state->m_gbTama5Address & 0x1F ];
	646	logerror( "Read tama5 memory 0x%02X\n", m_gbTama5Address & 0x1F );
	647	m_gbTama5Byte = m_gbTama5Memory[ m_gbTama5Address & 0x1F ];
662	648	break;
663	649	case 0x40:      /* Unknown, some kind of read */
664		if ( ( state->m_gbTama5Address & 0x1F ) == 0x12 )
	650	if ( ( m_gbTama5Address & 0x1F ) == 0x12 )
665	651	{
666		state->m_gbTama5Byte = 0xFF;
	652	m_gbTama5Byte = 0xFF;
667	653	}
668	654	case 0x80:      /* Unknown, some kind of read (when 07=01)/write (when 07=00/02) */
669	655	default:
670		logerror( "0x%04X: Unknown addressing mode\n", cpu_get_pc( &space->device() ) );
	656	logerror( "0x%04X: Unknown addressing mode\n", cpu_get_pc( &space.device() ) );
671	657	break;
672	658	}
673	659	break;
r14963	r14964
684	670	case 0x07:      /* Address register lo */
685	671	break;
686	672	case 0x0A:      /* Are we ready for the next command? */
687		state->m_MBC3RTCData[0] = 0x01;
688		memory_set_bankptr( space->machine(), "bank2", state->m_MBC3RTCData );
	673	m_MBC3RTCData[0] = 0x01;
	674	memory_set_bankptr( machine(), "bank2", m_MBC3RTCData );
689	675	break;
690	676	case 0x0C:      /* Data read register lo */
691		state->m_MBC3RTCData[0] = state->m_gbTama5Byte & 0x0F;
	677	m_MBC3RTCData[0] = m_gbTama5Byte & 0x0F;
692	678	break;
693	679	case 0x0D:      /* Data read register hi */
694		state->m_MBC3RTCData[0] = ( state->m_gbTama5Byte & 0xF0 ) >> 4;
	680	m_MBC3RTCData[0] = ( m_gbTama5Byte & 0xF0 ) >> 4;
695	681	break;
696	682	default:
697		logerror( "0x%04X: Unknown tama5 command 0x%02X\n", cpu_get_pc( &space->device() ), data );
	683	logerror( "0x%04X: Unknown tama5 command 0x%02X\n", cpu_get_pc( &space.device() ), data );
698	684	break;
699	685	}
700		state->m_gbLastTama5Command = data;
	686	m_gbLastTama5Command = data;
701	687	break;
702	688	}
703	689	}
r14963	r14964
705	691	/* This mmm01 implementation is mostly guess work, no clue how correct it all is */
706	692
707	693
708		static WRITE8_HANDLER( gb_rom_bank_mmm01_0000_w )
	694	WRITE8_MEMBER(gb_state::gb_rom_bank_mmm01_0000_w)
709	695	{
710		gb_state *state = space->machine().driver_data<gb_state>();
711		logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( &space->device() ), data, offset+0x000 );
	696	logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( &space.device() ), data, offset+0x000 );
712	697	if ( data & 0x40 )
713	698	{
714		state->m_mmm01_bank_offset = state->m_mmm01_reg1;
715		memory_set_bankptr( space->machine(), "bank5", state->m_ROMMap[ state->m_mmm01_bank_offset ] );
716		memory_set_bankptr( space->machine(), "bank10", state->m_ROMMap[ state->m_mmm01_bank_offset ] + 0x0100 );
717		gb_rom16_4000( space->machine(), state->m_ROMMap[ state->m_mmm01_bank_offset + state->m_mmm01_bank ] );
	699	m_mmm01_bank_offset = m_mmm01_reg1;
	700	memory_set_bankptr( machine(), "bank5", m_ROMMap[ m_mmm01_bank_offset ] );
	701	memory_set_bankptr( machine(), "bank10", m_ROMMap[ m_mmm01_bank_offset ] + 0x0100 );
	702	gb_rom16_4000( machine(), m_ROMMap[ m_mmm01_bank_offset + m_mmm01_bank ] );
718	703	}
719	704	}
720	705
721		static WRITE8_HANDLER( gb_rom_bank_mmm01_2000_w )
	706	WRITE8_MEMBER(gb_state::gb_rom_bank_mmm01_2000_w)
722	707	{
723		gb_state *state = space->machine().driver_data<gb_state>();
724		logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( &space->device() ), data, offset+0x2000 );
	708	logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( &space.device() ), data, offset+0x2000 );
725	709
726		state->m_mmm01_reg1 = data & state->m_ROMMask;
727		state->m_mmm01_bank = state->m_mmm01_reg1 & state->m_mmm01_bank_mask;
728		if ( state->m_mmm01_bank == 0 )
	710	m_mmm01_reg1 = data & m_ROMMask;
	711	m_mmm01_bank = m_mmm01_reg1 & m_mmm01_bank_mask;
	712	if ( m_mmm01_bank == 0 )
729	713	{
730		state->m_mmm01_bank = 1;
	714	m_mmm01_bank = 1;
731	715	}
732		gb_rom16_4000( space->machine(), state->m_ROMMap[ state->m_mmm01_bank_offset + state->m_mmm01_bank ] );
	716	gb_rom16_4000( machine(), m_ROMMap[ m_mmm01_bank_offset + m_mmm01_bank ] );
733	717	}
734	718
735		static WRITE8_HANDLER( gb_rom_bank_mmm01_4000_w )
	719	WRITE8_MEMBER(gb_state::gb_rom_bank_mmm01_4000_w)
736	720	{
737		logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( &space->device() ), data, offset+0x4000 );
	721	logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( &space.device() ), data, offset+0x4000 );
738	722	}
739	723
740		static WRITE8_HANDLER( gb_rom_bank_mmm01_6000_w )
	724	WRITE8_MEMBER(gb_state::gb_rom_bank_mmm01_6000_w)
741	725	{
742		gb_state *state = space->machine().driver_data<gb_state>();
743		logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( &space->device() ), data, offset+0x6000 );
	726	logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( &space.device() ), data, offset+0x6000 );
744	727	/* Not sure if this is correct, Taito Variety Pack sets these values */
745	728	/* Momotarou Collection 2 writes 01 and 21 here */
746	729	switch( data )
747	730	{
748		case 0x30:   state->m_mmm01_bank_mask = 0x07;   break;
749		case 0x38:   state->m_mmm01_bank_mask = 0x03;   break;
750		default:   state->m_mmm01_bank_mask = 0xFF; break;
	731	case 0x30:   m_mmm01_bank_mask = 0x07;   break;
	732	case 0x38:   m_mmm01_bank_mask = 0x03;   break;
	733	default:   m_mmm01_bank_mask = 0xFF; break;
751	734	}
752	735	}
753	736
r14963	r14964
764	747	memory_set_bankptr( machine, "bank2", state->m_RAMMap[ state->m_MBC1Mode ? ( state->m_ROMBank >> 5 ) : 0 ] );
765	748	}
766	749
767		static WRITE8_HANDLER( gb_rom_bank_select_mbc1_kor )
	750	WRITE8_MEMBER(gb_state::gb_rom_bank_select_mbc1_kor)
768	751	{
769		gb_state *state = space->machine().driver_data<gb_state>();
770	752	data &= 0x0F; /* Only uses lower 5 bits */
771	753	/* Selecting bank 0 == selecting bank 1 */
772	754	if( data == 0 )
773	755	data = 1;
774	756
775		state->m_ROMBank = ( state->m_ROMBank & 0x01F0 ) | data;
	757	m_ROMBank = ( m_ROMBank & 0x01F0 ) | data;
776	758	/* Switch banks */
777		gb_set_mbc1_kor_banks(space->machine());
	759	gb_set_mbc1_kor_banks(machine());
778	760	}
779	761
780		static WRITE8_HANDLER( gb_ram_bank_select_mbc1_kor )
	762	WRITE8_MEMBER(gb_state::gb_ram_bank_select_mbc1_kor)
781	763	{
782		gb_state *state = space->machine().driver_data<gb_state>();
783	764	data &= 0x3; /* Only uses the lower 2 bits */
784	765
785	766	/* Select the upper bits of the ROMMask */
786		state->m_ROMBank = ( state->m_ROMBank & 0x0F ) | ( data << 4 );
	767	m_ROMBank = ( m_ROMBank & 0x0F ) | ( data << 4 );
787	768
788	769	/* Switch banks */
789		gb_set_mbc1_kor_banks(space->machine());
	770	gb_set_mbc1_kor_banks(machine());
790	771	}
791	772
792		static WRITE8_HANDLER( gb_mem_mode_select_mbc1_kor )
	773	WRITE8_MEMBER(gb_state::gb_mem_mode_select_mbc1_kor)
793	774	{
794		gb_state *state = space->machine().driver_data<gb_state>();
795		state->m_MBC1Mode = data & 0x1;
796		gb_set_mbc1_kor_banks(space->machine());
	775	m_MBC1Mode = data & 0x1;
	776	gb_set_mbc1_kor_banks(machine());
797	777	}
798	778
799		WRITE8_HANDLER ( gb_io_w )
	779	WRITE8_MEMBER(gb_state::gb_io_w)
800	780	{
801		gb_state *state = space->machine().driver_data<gb_state>();
802	781	static const UINT8 timer_shifts[4] = {10, 4, 6, 8};
803	782
804	783	switch (offset)
r14963	r14964
806	785	case 0x00:                  /* JOYP - Joypad */
807	786	JOYPAD = 0xCF | data;
808	787	if (!(data & 0x20))
809		JOYPAD &= (input_port_read(space->machine(), "INPUTS") >> 4) | 0xF0;
	788	JOYPAD &= (input_port_read(machine(), "INPUTS") >> 4) | 0xF0;
810	789	if (!(data & 0x10))
811		JOYPAD &= input_port_read(space->machine(), "INPUTS") | 0xF0;
	790	JOYPAD &= input_port_read(machine(), "INPUTS") | 0xF0;
812	791	return;
813	792	case 0x01:                  /* SB - Serial transfer data */
814	793	break;
r14963	r14964
818	797	case 0x00:
819	798	case 0x01:
820	799	case 0x80:            /* enabled & external clock */
821		state->m_SIOCount = 0;
	800	m_SIOCount = 0;
822	801	break;
823	802	case 0x81:            /* enabled & internal clock */
824	803	SIODATA = 0xFF;
825		state->m_SIOCount = 8;
826		state->m_gb_serial_timer->adjust(space->machine().device<cpu_device>("maincpu")->cycles_to_attotime(512), 0, space->machine().device<cpu_device>("maincpu")->cycles_to_attotime(512));
827		state->m_gb_serial_timer->enable( 1 );
	804	m_SIOCount = 8;
	805	m_gb_serial_timer->adjust(machine().device<cpu_device>("maincpu")->cycles_to_attotime(512), 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(512));
	806	m_gb_serial_timer->enable( 1 );
828	807	break;
829	808	}
830	809	break;
831	810	case 0x04:                  /* DIV - Divider register */
832	811	/* Force increment of TIMECNT register */
833		if ( state->m_divcount >= 16 )
834		gb_timer_increment(space->machine());
835		state->m_divcount = 0;
	812	if ( m_divcount >= 16 )
	813	gb_timer_increment(machine());
	814	m_divcount = 0;
836	815	return;
837	816	case 0x05:                  /* TIMA - Timer counter */
838	817	/* Check if the counter is being reloaded in this cycle */
839		if ( state->m_reloading && ( state->m_divcount & ( state->m_shift_cycles - 1 ) ) == 4 )
	818	if ( m_reloading && ( m_divcount & ( m_shift_cycles - 1 ) ) == 4 )
840	819	{
841	820	data = TIMECNT;
842	821	}
843	822	break;
844	823	case 0x06:                  /* TMA - Timer module */
845	824	/* Check if the counter is being reloaded in this cycle */
846		if ( state->m_reloading && ( state->m_divcount & ( state->m_shift_cycles - 1 ) ) == 4 )
	825	if ( m_reloading && ( m_divcount & ( m_shift_cycles - 1 ) ) == 4 )
847	826	{
848	827	TIMECNT = data;
849	828	}
r14963	r14964
854	833	if ( ( ! ( data & 0x04 ) && ( TIMEFRQ & 0x04 ) ) || ( ( data & 0x04 ) && ( TIMEFRQ & 0x04 ) && ( data & 0x03 ) != ( TIMEFRQ & 0x03 ) ) )
855	834	{
856	835	/* Check if TIMECNT should be incremented */
857		if ( ( state->m_divcount & ( state->m_shift_cycles - 1 ) ) >= ( state->m_shift_cycles >> 1 ) )
	836	if ( ( m_divcount & ( m_shift_cycles - 1 ) ) >= ( m_shift_cycles >> 1 ) )
858	837	{
859		gb_timer_increment(space->machine());
	838	gb_timer_increment(machine());
860	839	}
861	840	}
862		state->m_shift = timer_shifts[data & 0x03];
863		state->m_shift_cycles = 1 << state->m_shift;
	841	m_shift = timer_shifts[data & 0x03];
	842	m_shift_cycles = 1 << m_shift;
864	843	break;
865	844	case 0x0F:                  /* IF - Interrupt flag */
866	845	data &= 0x1F;
867		space->machine().device<lr35902_cpu_device>(":maincpu")->set_if( data );
	846	machine().device<lr35902_cpu_device>(":maincpu")->set_if( data );
868	847	break;
869	848	}
870	849
871		state->m_gb_io[offset] = data;
	850	m_gb_io[offset] = data;
872	851	}
873	852
874		WRITE8_HANDLER ( gb_io2_w )
	853	WRITE8_MEMBER(gb_state::gb_io2_w)
875	854	{
876		gb_state *state = space->machine().driver_data<gb_state>();
877	855	if ( offset == 0x10 )
878	856	{
879	857	/* disable BIOS ROM */
880		gb_rom16_0000( space->machine(), state->m_ROMMap[state->m_ROMBank00] );
	858	gb_rom16_0000( machine(), m_ROMMap[m_ROMBank00] );
881	859	}
882	860	else
883	861	{
r14963	r14964
917	895	};
918	896	#endif
919	897
920		WRITE8_HANDLER ( sgb_io_w )
	898	WRITE8_MEMBER(gb_state::sgb_io_w)
921	899	{
922		gb_state *state = space->machine().driver_data<gb_state>();
923		UINT8 *sgb_data = state->m_sgb_data;
	900	UINT8 *sgb_data = m_sgb_data;
924	901
925	902	switch( offset )
926	903	{
r14963	r14964
928	905	switch (data & 0x30)
929	906	{
930	907	case 0x00:               /* start condition */
931		if (state->m_sgb_start)
	908	if (m_sgb_start)
932	909	logerror("SGB: Start condition before end of transfer ??\n");
933		state->m_sgb_bitcount = 0;
934		state->m_sgb_start = 1;
935		state->m_sgb_rest = 0;
936		JOYPAD = 0x0F & ((input_port_read(space->machine(), "INPUTS") >> 4) | input_port_read(space->machine(), "INPUTS") | 0xF0);
	910	m_sgb_bitcount = 0;
	911	m_sgb_start = 1;
	912	m_sgb_rest = 0;
	913	JOYPAD = 0x0F & ((input_port_read(machine(), "INPUTS") >> 4) | input_port_read(machine(), "INPUTS") | 0xF0);
937	914	break;
938	915	case 0x10:               /* data true */
939		if (state->m_sgb_rest)
	916	if (m_sgb_rest)
940	917	{
941	918	/* We should test for this case , but the code below won't
942	919	work with the current setup */
943	920	#if 0
944		if (state->m_sgb_bytecount == 16)
	921	if (m_sgb_bytecount == 16)
945	922	{
946	923	logerror("SGB: end of block is not zero!");
947		state->m_sgb_start = 0;
	924	m_sgb_start = 0;
948	925	}
949	926	#endif
950		sgb_data[state->m_sgb_bytecount] >>= 1;
951		sgb_data[state->m_sgb_bytecount] |= 0x80;
952		state->m_sgb_bitcount++;
953		if (state->m_sgb_bitcount == 8)
	927	sgb_data[m_sgb_bytecount] >>= 1;
	928	sgb_data[m_sgb_bytecount] |= 0x80;
	929	m_sgb_bitcount++;
	930	if (m_sgb_bitcount == 8)
954	931	{
955		state->m_sgb_bitcount = 0;
956		state->m_sgb_bytecount++;
	932	m_sgb_bitcount = 0;
	933	m_sgb_bytecount++;
957	934	}
958		state->m_sgb_rest = 0;
	935	m_sgb_rest = 0;
959	936	}
960		JOYPAD = 0x1F & ((input_port_read(space->machine(), "INPUTS") >> 4) | 0xF0);
	937	JOYPAD = 0x1F & ((input_port_read(machine(), "INPUTS") >> 4) | 0xF0);
961	938	break;
962	939	case 0x20:            /* data false */
963		if (state->m_sgb_rest)
	940	if (m_sgb_rest)
964	941	{
965		if( state->m_sgb_bytecount == 16 && state->m_sgb_packets == -1 )
	942	if( m_sgb_bytecount == 16 && m_sgb_packets == -1 )
966	943	{
967	944	#ifdef MAME_DEBUG
968	945	logerror("SGB: %s (%02X) pkts: %d data: %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
r14963	r14964
971	948	sgb_data[8], sgb_data[9], sgb_data[10], sgb_data[11],
972	949	sgb_data[12], sgb_data[13], sgb_data[14], sgb_data[15]);
973	950	#endif
974		state->m_sgb_packets = sgb_data[0] & 0x07;
975		state->m_sgb_start = 0;
	951	m_sgb_packets = sgb_data[0] & 0x07;
	952	m_sgb_start = 0;
976	953	}
977		if (state->m_sgb_bytecount == (state->m_sgb_packets << 4) )
	954	if (m_sgb_bytecount == (m_sgb_packets << 4) )
978	955	{
979	956	switch( sgb_data[0] >> 3 )
980	957	{
981	958	case 0x00:   /* PAL01 */
982		state->m_sgb_pal[0*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
983		state->m_sgb_pal[0*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
984		state->m_sgb_pal[0*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
985		state->m_sgb_pal[0*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
986		state->m_sgb_pal[1*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
987		state->m_sgb_pal[1*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
988		state->m_sgb_pal[1*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
989		state->m_sgb_pal[1*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
	959	m_sgb_pal[0*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	960	m_sgb_pal[0*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
	961	m_sgb_pal[0*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
	962	m_sgb_pal[0*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
	963	m_sgb_pal[1*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	964	m_sgb_pal[1*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
	965	m_sgb_pal[1*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
	966	m_sgb_pal[1*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
990	967	break;
991	968	case 0x01:   /* PAL23 */
992		state->m_sgb_pal[2*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
993		state->m_sgb_pal[2*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
994		state->m_sgb_pal[2*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
995		state->m_sgb_pal[2*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
996		state->m_sgb_pal[3*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
997		state->m_sgb_pal[3*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
998		state->m_sgb_pal[3*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
999		state->m_sgb_pal[3*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
	969	m_sgb_pal[2*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	970	m_sgb_pal[2*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
	971	m_sgb_pal[2*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
	972	m_sgb_pal[2*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
	973	m_sgb_pal[3*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	974	m_sgb_pal[3*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
	975	m_sgb_pal[3*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
	976	m_sgb_pal[3*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
1000	977	break;
1001	978	case 0x02:   /* PAL03 */
1002		state->m_sgb_pal[0*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1003		state->m_sgb_pal[0*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
1004		state->m_sgb_pal[0*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
1005		state->m_sgb_pal[0*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
1006		state->m_sgb_pal[3*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1007		state->m_sgb_pal[3*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
1008		state->m_sgb_pal[3*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
1009		state->m_sgb_pal[3*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
	979	m_sgb_pal[0*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	980	m_sgb_pal[0*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
	981	m_sgb_pal[0*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
	982	m_sgb_pal[0*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
	983	m_sgb_pal[3*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	984	m_sgb_pal[3*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
	985	m_sgb_pal[3*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
	986	m_sgb_pal[3*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
1010	987	break;
1011	988	case 0x03:   /* PAL12 */
1012		state->m_sgb_pal[1*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1013		state->m_sgb_pal[1*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
1014		state->m_sgb_pal[1*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
1015		state->m_sgb_pal[1*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
1016		state->m_sgb_pal[2*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1017		state->m_sgb_pal[2*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
1018		state->m_sgb_pal[2*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
1019		state->m_sgb_pal[2*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
	989	m_sgb_pal[1*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	990	m_sgb_pal[1*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
	991	m_sgb_pal[1*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
	992	m_sgb_pal[1*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
	993	m_sgb_pal[2*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	994	m_sgb_pal[2*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
	995	m_sgb_pal[2*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
	996	m_sgb_pal[2*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
1020	997	break;
1021	998	case 0x04:   /* ATTR_BLK */
1022	999	{
r14963	r14964
1030	1007	{
1031	1008	for( J = sgb_data[o + 5]; J <= sgb_data[o + 7]; J++ )
1032	1009	{
1033		state->m_sgb_pal_map[I][J] = sgb_data[o + 3] & 0x3;
	1010	m_sgb_pal_map[I][J] = sgb_data[o + 3] & 0x3;
1034	1011	}
1035	1012	}
1036	1013	}
r14963	r14964
1048	1025	{
1049	1026	for( J = 0; J < 20; J++ )
1050	1027	{
1051		state->m_sgb_pal_map[J][sgb_data[K + 1] & 0x1f] = (sgb_data[K + 1] & 0x60) >> 5;
	1028	m_sgb_pal_map[J][sgb_data[K + 1] & 0x1f] = (sgb_data[K + 1] & 0x60) >> 5;
1052	1029	}
1053	1030	}
1054	1031	else
1055	1032	{
1056	1033	for( J = 0; J < 18; J++ )
1057	1034	{
1058		state->m_sgb_pal_map[sgb_data[K + 1] & 0x1f][J] = (sgb_data[K + 1] & 0x60) >> 5;
	1035	m_sgb_pal_map[sgb_data[K + 1] & 0x1f][J] = (sgb_data[K + 1] & 0x60) >> 5;
1059	1036	}
1060	1037	}
1061	1038	}
r14963	r14964
1070	1047	{
1071	1048	for( J = 0; J < 20; J++ )
1072	1049	{
1073		state->m_sgb_pal_map[J][I] = (sgb_data[1] & 0xC) >> 2;
	1050	m_sgb_pal_map[J][I] = (sgb_data[1] & 0xC) >> 2;
1074	1051	}
1075	1052	}
1076	1053	for( J = 0; J < 20; J++ )
1077	1054	{
1078		state->m_sgb_pal_map[J][sgb_data[2]] = (sgb_data[1] & 0x30) >> 4;
	1055	m_sgb_pal_map[J][sgb_data[2]] = (sgb_data[1] & 0x30) >> 4;
1079	1056	}
1080	1057	for( I = sgb_data[2] + 1; I < 18; I++ )
1081	1058	{
1082	1059	for( J = 0; J < 20; J++ )
1083	1060	{
1084		state->m_sgb_pal_map[J][I] = sgb_data[1] & 0x3;
	1061	m_sgb_pal_map[J][I] = sgb_data[1] & 0x3;
1085	1062	}
1086	1063	}
1087	1064	}
r14963	r14964
1091	1068	{
1092	1069	for( J = 0; J < 18; J++ )
1093	1070	{
1094		state->m_sgb_pal_map[I][J] = (sgb_data[1] & 0xC) >> 2;
	1071	m_sgb_pal_map[I][J] = (sgb_data[1] & 0xC) >> 2;
1095	1072	}
1096	1073	}
1097	1074	for( J = 0; J < 18; J++ )
1098	1075	{
1099		state->m_sgb_pal_map[sgb_data[2]][J] = (sgb_data[1] & 0x30) >> 4;
	1076	m_sgb_pal_map[sgb_data[2]][J] = (sgb_data[1] & 0x30) >> 4;
1100	1077	}
1101	1078	for( I = sgb_data[2] + 1; I < 20; I++ )
1102	1079	{
1103	1080	for( J = 0; J < 18; J++ )
1104	1081	{
1105		state->m_sgb_pal_map[I][J] = sgb_data[1] & 0x3;
	1082	m_sgb_pal_map[I][J] = sgb_data[1] & 0x3;
1106	1083	}
1107	1084	}
1108	1085	}
r14963	r14964
1123	1100	{
1124	1101	for( I = 6; I < sets; I++ )
1125	1102	{
1126		state->m_sgb_pal_map[x][y++] = (sgb_data[I] & 0xC0) >> 6;
	1103	m_sgb_pal_map[x][y++] = (sgb_data[I] & 0xC0) >> 6;
1127	1104	if( y > 17 )
1128	1105	{
1129	1106	y = 0;
r14963	r14964
1132	1109	x = 0;
1133	1110	}
1134	1111
1135		state->m_sgb_pal_map[x][y++] = (sgb_data[I] & 0x30) >> 4;
	1112	m_sgb_pal_map[x][y++] = (sgb_data[I] & 0x30) >> 4;
1136	1113	if( y > 17 )
1137	1114	{
1138	1115	y = 0;
r14963	r14964
1141	1118	x = 0;
1142	1119	}
1143	1120
1144		state->m_sgb_pal_map[x][y++] = (sgb_data[I] & 0xC) >> 2;
	1121	m_sgb_pal_map[x][y++] = (sgb_data[I] & 0xC) >> 2;
1145	1122	if( y > 17 )
1146	1123	{
1147	1124	y = 0;
r14963	r14964
1150	1127	x = 0;
1151	1128	}
1152	1129
1153		state->m_sgb_pal_map[x][y++] = sgb_data[I] & 0x3;
	1130	m_sgb_pal_map[x][y++] = sgb_data[I] & 0x3;
1154	1131	if( y > 17 )
1155	1132	{
1156	1133	y = 0;
r14963	r14964
1164	1141	{
1165	1142	for( I = 6; I < sets; I++ )
1166	1143	{
1167		state->m_sgb_pal_map[x++][y] = (sgb_data[I] & 0xC0) >> 6;
	1144	m_sgb_pal_map[x++][y] = (sgb_data[I] & 0xC0) >> 6;
1168	1145	if( x > 19 )
1169	1146	{
1170	1147	x = 0;
r14963	r14964
1173	1150	y = 0;
1174	1151	}
1175	1152
1176		state->m_sgb_pal_map[x++][y] = (sgb_data[I] & 0x30) >> 4;
	1153	m_sgb_pal_map[x++][y] = (sgb_data[I] & 0x30) >> 4;
1177	1154	if( x > 19 )
1178	1155	{
1179	1156	x = 0;
r14963	r14964
1182	1159	y = 0;
1183	1160	}
1184	1161
1185		state->m_sgb_pal_map[x++][y] = (sgb_data[I] & 0xC) >> 2;
	1162	m_sgb_pal_map[x++][y] = (sgb_data[I] & 0xC) >> 2;
1186	1163	if( x > 19 )
1187	1164	{
1188	1165	x = 0;
r14963	r14964
1191	1168	y = 0;
1192	1169	}
1193	1170
1194		state->m_sgb_pal_map[x++][y] = sgb_data[I] & 0x3;
	1171	m_sgb_pal_map[x++][y] = sgb_data[I] & 0x3;
1195	1172	if( x > 19 )
1196	1173	{
1197	1174	x = 0;
r14963	r14964
1218	1195
1219	1196	/* Palette 0 */
1220	1197	index_ = (UINT16)(sgb_data[1] | (sgb_data[2] << 8)) * 4;
1221		state->m_sgb_pal[0] = state->m_sgb_pal_data[index_];
1222		state->m_sgb_pal[1] = state->m_sgb_pal_data[index_ + 1];
1223		state->m_sgb_pal[2] = state->m_sgb_pal_data[index_ + 2];
1224		state->m_sgb_pal[3] = state->m_sgb_pal_data[index_ + 3];
	1198	m_sgb_pal[0] = m_sgb_pal_data[index_];
	1199	m_sgb_pal[1] = m_sgb_pal_data[index_ + 1];
	1200	m_sgb_pal[2] = m_sgb_pal_data[index_ + 2];
	1201	m_sgb_pal[3] = m_sgb_pal_data[index_ + 3];
1225	1202	/* Palette 1 */
1226	1203	index_ = (UINT16)(sgb_data[3] | (sgb_data[4] << 8)) * 4;
1227		state->m_sgb_pal[4] = state->m_sgb_pal_data[index_];
1228		state->m_sgb_pal[5] = state->m_sgb_pal_data[index_ + 1];
1229		state->m_sgb_pal[6] = state->m_sgb_pal_data[index_ + 2];
1230		state->m_sgb_pal[7] = state->m_sgb_pal_data[index_ + 3];
	1204	m_sgb_pal[4] = m_sgb_pal_data[index_];
	1205	m_sgb_pal[5] = m_sgb_pal_data[index_ + 1];
	1206	m_sgb_pal[6] = m_sgb_pal_data[index_ + 2];
	1207	m_sgb_pal[7] = m_sgb_pal_data[index_ + 3];
1231	1208	/* Palette 2 */
1232	1209	index_ = (UINT16)(sgb_data[5] | (sgb_data[6] << 8)) * 4;
1233		state->m_sgb_pal[8] = state->m_sgb_pal_data[index_];
1234		state->m_sgb_pal[9] = state->m_sgb_pal_data[index_ + 1];
1235		state->m_sgb_pal[10] = state->m_sgb_pal_data[index_ + 2];
1236		state->m_sgb_pal[11] = state->m_sgb_pal_data[index_ + 3];
	1210	m_sgb_pal[8] = m_sgb_pal_data[index_];
	1211	m_sgb_pal[9] = m_sgb_pal_data[index_ + 1];
	1212	m_sgb_pal[10] = m_sgb_pal_data[index_ + 2];
	1213	m_sgb_pal[11] = m_sgb_pal_data[index_ + 3];
1237	1214	/* Palette 3 */
1238	1215	index_ = (UINT16)(sgb_data[7] | (sgb_data[8] << 8)) * 4;
1239		state->m_sgb_pal[12] = state->m_sgb_pal_data[index_];
1240		state->m_sgb_pal[13] = state->m_sgb_pal_data[index_ + 1];
1241		state->m_sgb_pal[14] = state->m_sgb_pal_data[index_ + 2];
1242		state->m_sgb_pal[15] = state->m_sgb_pal_data[index_ + 3];
	1216	m_sgb_pal[12] = m_sgb_pal_data[index_];
	1217	m_sgb_pal[13] = m_sgb_pal_data[index_ + 1];
	1218	m_sgb_pal[14] = m_sgb_pal_data[index_ + 2];
	1219	m_sgb_pal[15] = m_sgb_pal_data[index_ + 3];
1243	1220	/* Attribute File */
1244	1221	if( sgb_data[9] & 0x40 )
1245		state->m_sgb_window_mask = 0;
1246		state->m_sgb_atf = (sgb_data[9] & 0x3f) * (18 * 5);
	1222	m_sgb_window_mask = 0;
	1223	m_sgb_atf = (sgb_data[9] & 0x3f) * (18 * 5);
1247	1224	if( sgb_data[9] & 0x80 )
1248	1225	{
1249	1226	for( J = 0; J < 18; J++ )
1250	1227	{
1251	1228	for( I = 0; I < 5; I++ )
1252	1229	{
1253		state->m_sgb_pal_map[I * 4][J] = (state->m_sgb_atf_data[(J * 5) + state->m_sgb_atf + I] & 0xC0) >> 6;
1254		state->m_sgb_pal_map[(I * 4) + 1][J] = (state->m_sgb_atf_data[(J * 5) + state->m_sgb_atf + I] & 0x30) >> 4;
1255		state->m_sgb_pal_map[(I * 4) + 2][J] = (state->m_sgb_atf_data[(J * 5) + state->m_sgb_atf + I] & 0xC) >> 2;
1256		state->m_sgb_pal_map[(I * 4) + 3][J] = state->m_sgb_atf_data[(J * 5) + state->m_sgb_atf + I] & 0x3;
	1230	m_sgb_pal_map[I * 4][J] = (m_sgb_atf_data[(J * 5) + m_sgb_atf + I] & 0xC0) >> 6;
	1231	m_sgb_pal_map[(I * 4) + 1][J] = (m_sgb_atf_data[(J * 5) + m_sgb_atf + I] & 0x30) >> 4;
	1232	m_sgb_pal_map[(I * 4) + 2][J] = (m_sgb_atf_data[(J * 5) + m_sgb_atf + I] & 0xC) >> 2;
	1233	m_sgb_pal_map[(I * 4) + 3][J] = m_sgb_atf_data[(J * 5) + m_sgb_atf + I] & 0x3;
1257	1234	}
1258	1235	}
1259	1236	}
r14963	r14964
1261	1238	break;
1262	1239	case 0x0B:   /* PAL_TRN */
1263	1240	{
1264		UINT8 *gb_vram = gb_get_vram_ptr(space->machine());
	1241	UINT8 *gb_vram = gb_get_vram_ptr(machine());
1265	1242	UINT16 I, col;
1266	1243
1267	1244	for( I = 0; I < 2048; I++ )
1268	1245	{
1269	1246	col = ( gb_vram[ 0x0800 + (I*2) + 1 ] << 8 ) | gb_vram[ 0x0800 + (I*2) ];
1270		state->m_sgb_pal_data[I] = col;
	1247	m_sgb_pal_data[I] = col;
1271	1248	}
1272	1249	}
1273	1250	break;
r14963	r14964
1288	1265	break;
1289	1266	case 0x11:   /* MLT_REQ - Multi controller request */
1290	1267	if (sgb_data[1] == 0x00)
1291		state->m_sgb_controller_mode = 0;
	1268	m_sgb_controller_mode = 0;
1292	1269	else if (sgb_data[1] == 0x01)
1293		state->m_sgb_controller_mode = 2;
	1270	m_sgb_controller_mode = 2;
1294	1271	break;
1295	1272	case 0x12:   /* JUMP */
1296	1273	/* Not Implemented */
1297	1274	break;
1298	1275	case 0x13:   /* CHR_TRN */
1299	1276	if( sgb_data[1] & 0x1 )
1300		memcpy( state->m_sgb_tile_data + 4096, gb_get_vram_ptr(space->machine()) + 0x0800, 4096 );
	1277	memcpy( m_sgb_tile_data + 4096, gb_get_vram_ptr(machine()) + 0x0800, 4096 );
1301	1278	else
1302		memcpy( state->m_sgb_tile_data, gb_get_vram_ptr(space->machine()) + 0x0800, 4096 );
	1279	memcpy( m_sgb_tile_data, gb_get_vram_ptr(machine()) + 0x0800, 4096 );
1303	1280	break;
1304	1281	case 0x14:   /* PCT_TRN */
1305	1282	{
1306	1283	int I;
1307	1284	UINT16 col;
1308		UINT8 *gb_vram = gb_get_vram_ptr(space->machine());
1309		if( state->m_sgb_hack )
	1285	UINT8 *gb_vram = gb_get_vram_ptr(machine());
	1286	if( m_sgb_hack )
1310	1287	{
1311		memcpy( state->m_sgb_tile_map, gb_vram + 0x1000, 2048 );
	1288	memcpy( m_sgb_tile_map, gb_vram + 0x1000, 2048 );
1312	1289	for( I = 0; I < 64; I++ )
1313	1290	{
1314	1291	col = ( gb_vram[ 0x0800 + (I*2) + 1 ] << 8 ) | gb_vram[ 0x0800 + (I*2) ];
1315		state->m_sgb_pal[SGB_BORDER_PAL_OFFSET + I] = col;
	1292	m_sgb_pal[SGB_BORDER_PAL_OFFSET + I] = col;
1316	1293	}
1317	1294	}
1318	1295	else /* Do things normally */
1319	1296	{
1320		memcpy( state->m_sgb_tile_map, gb_vram + 0x0800, 2048 );
	1297	memcpy( m_sgb_tile_map, gb_vram + 0x0800, 2048 );
1321	1298	for( I = 0; I < 64; I++ )
1322	1299	{
1323	1300	col = ( gb_vram[ 0x1000 + (I*2) + 1 ] << 8 ) | gb_vram[ 0x1000 + (I*2) ];
1324		state->m_sgb_pal[SGB_BORDER_PAL_OFFSET + I] = col;
	1301	m_sgb_pal[SGB_BORDER_PAL_OFFSET + I] = col;
1325	1302	}
1326	1303	}
1327	1304	}
1328	1305	break;
1329	1306	case 0x15:   /* ATTR_TRN */
1330		memcpy( state->m_sgb_atf_data, gb_get_vram_ptr(space->machine()) + 0x0800, 4050 );
	1307	memcpy( m_sgb_atf_data, gb_get_vram_ptr(machine()) + 0x0800, 4050 );
1331	1308	break;
1332	1309	case 0x16:   /* ATTR_SET */
1333	1310	{
r14963	r14964
1335	1312
1336	1313	/* Attribute File */
1337	1314	if( sgb_data[1] & 0x40 )
1338		state->m_sgb_window_mask = 0;
1339		state->m_sgb_atf = (sgb_data[1] & 0x3f) * (18 * 5);
	1315	m_sgb_window_mask = 0;
	1316	m_sgb_atf = (sgb_data[1] & 0x3f) * (18 * 5);
1340	1317	for( J = 0; J < 18; J++ )
1341	1318	{
1342	1319	for( I = 0; I < 5; I++ )
1343	1320	{
1344		state->m_sgb_pal_map[I * 4][J] = (state->m_sgb_atf_data[(J * 5) + state->m_sgb_atf + I] & 0xC0) >> 6;
1345		state->m_sgb_pal_map[(I * 4) + 1][J] = (state->m_sgb_atf_data[(J * 5) + state->m_sgb_atf + I] & 0x30) >> 4;
1346		state->m_sgb_pal_map[(I * 4) + 2][J] = (state->m_sgb_atf_data[(J * 5) + state->m_sgb_atf + I] & 0xC) >> 2;
1347		state->m_sgb_pal_map[(I * 4) + 3][J] = state->m_sgb_atf_data[(J * 5) + state->m_sgb_atf + I] & 0x3;
	1321	m_sgb_pal_map[I * 4][J] = (m_sgb_atf_data[(J * 5) + m_sgb_atf + I] & 0xC0) >> 6;
	1322	m_sgb_pal_map[(I * 4) + 1][J] = (m_sgb_atf_data[(J * 5) + m_sgb_atf + I] & 0x30) >> 4;
	1323	m_sgb_pal_map[(I * 4) + 2][J] = (m_sgb_atf_data[(J * 5) + m_sgb_atf + I] & 0xC) >> 2;
	1324	m_sgb_pal_map[(I * 4) + 3][J] = m_sgb_atf_data[(J * 5) + m_sgb_atf + I] & 0x3;
1348	1325	}
1349	1326	}
1350	1327	}
1351	1328	break;
1352	1329	case 0x17:   /* MASK_EN */
1353		state->m_sgb_window_mask = sgb_data[1];
	1330	m_sgb_window_mask = sgb_data[1];
1354	1331	break;
1355	1332	case 0x18:   /* OBJ_TRN */
1356	1333	/* Not Implemnted */
r14963	r14964
1368	1345	logerror( "SGB: Unknown Command 0x%02x!\n", sgb_data[0] >> 3 );
1369	1346	}
1370	1347
1371		state->m_sgb_start = 0;
1372		state->m_sgb_bytecount = 0;
1373		state->m_sgb_packets = -1;
	1348	m_sgb_start = 0;
	1349	m_sgb_bytecount = 0;
	1350	m_sgb_packets = -1;
1374	1351	}
1375		if( state->m_sgb_start )
	1352	if( m_sgb_start )
1376	1353	{
1377		sgb_data[state->m_sgb_bytecount] >>= 1;
1378		state->m_sgb_bitcount++;
1379		if (state->m_sgb_bitcount == 8)
	1354	sgb_data[m_sgb_bytecount] >>= 1;
	1355	m_sgb_bitcount++;
	1356	if (m_sgb_bitcount == 8)
1380	1357	{
1381		state->m_sgb_bitcount = 0;
1382		state->m_sgb_bytecount++;
	1358	m_sgb_bitcount = 0;
	1359	m_sgb_bytecount++;
1383	1360	}
1384	1361	}
1385		state->m_sgb_rest = 0;
	1362	m_sgb_rest = 0;
1386	1363	}
1387		JOYPAD = 0x2F & (input_port_read(space->machine(), "INPUTS") | 0xF0);
	1364	JOYPAD = 0x2F & (input_port_read(machine(), "INPUTS") | 0xF0);
1388	1365	break;
1389	1366	case 0x30:               /* rest condition */
1390		if (state->m_sgb_start)
1391		state->m_sgb_rest = 1;
1392		if (state->m_sgb_controller_mode)
	1367	if (m_sgb_start)
	1368	m_sgb_rest = 1;
	1369	if (m_sgb_controller_mode)
1393	1370	{
1394		state->m_sgb_controller_no++;
1395		if (state->m_sgb_controller_no == state->m_sgb_controller_mode)
1396		state->m_sgb_controller_no = 0;
1397		JOYPAD = 0x3F - state->m_sgb_controller_no;
	1371	m_sgb_controller_no++;
	1372	if (m_sgb_controller_no == m_sgb_controller_mode)
	1373	m_sgb_controller_no = 0;
	1374	JOYPAD = 0x3F - m_sgb_controller_no;
1398	1375	}
1399	1376	else
1400	1377	JOYPAD = 0x3F;
r14963	r14964
1411	1388	return;
1412	1389	}
1413	1390
1414		state->m_gb_io[offset] = data;
	1391	m_gb_io[offset] = data;
1415	1392	}
1416	1393
1417	1394	/* Interrupt Enable register */
1418		READ8_HANDLER( gb_ie_r )
	1395	READ8_MEMBER(gb_state::gb_ie_r)
1419	1396	{
1420		return space->machine().device<lr35902_cpu_device>(":maincpu")->get_ie();
	1397	return machine().device<lr35902_cpu_device>(":maincpu")->get_ie();
1421	1398	}
1422	1399
1423		WRITE8_HANDLER ( gb_ie_w )
	1400	WRITE8_MEMBER(gb_state::gb_ie_w)
1424	1401	{
1425		space->machine().device<lr35902_cpu_device>(":maincpu")->set_ie( data & 0x1F );
	1402	machine().device<lr35902_cpu_device>(":maincpu")->set_ie( data & 0x1F );
1426	1403	}
1427	1404
1428	1405	/* IO read */
1429		READ8_HANDLER ( gb_io_r )
	1406	READ8_MEMBER(gb_state::gb_io_r)
1430	1407	{
1431		gb_state *state = space->machine().driver_data<gb_state>();
1432	1408	switch(offset)
1433	1409	{
1434	1410	case 0x04:
1435		return ( state->m_divcount >> 8 ) & 0xFF;
	1411	return ( m_divcount >> 8 ) & 0xFF;
1436	1412	case 0x00:
1437	1413	case 0x01:
1438	1414	case 0x02:
r14963	r14964
1440	1416	case 0x05:
1441	1417	case 0x06:
1442	1418	case 0x07:
1443		return state->m_gb_io[offset];
	1419	return m_gb_io[offset];
1444	1420	case 0x0F:
1445	1421	/* Make sure the internal states are up to date */
1446		return 0xE0 | space->machine().device<lr35902_cpu_device>(":maincpu")->get_if();
	1422	return 0xE0 | machine().device<lr35902_cpu_device>(":maincpu")->get_if();
1447	1423	default:
1448	1424	/* It seems unsupported registers return 0xFF */
1449	1425	return 0xFF;
r14963	r14964
1927	1903	{
1928	1904	gb_state *state = machine.driver_data<gb_state>();
1929	1905	/* Shift in a received bit */
1930		SIODATA = (SIODATA << 1) | 0x01;
	1906	state->SIODATA = (state->SIODATA << 1) | 0x01;
1931	1907	/* Decrement number of handled bits */
1932	1908	state->m_SIOCount--;
1933	1909	/* If all bits done, stop timer and trigger interrupt */
1934	1910	if ( ! state->m_SIOCount )
1935	1911	{
1936		SIOCONT &= 0x7F;
	1912	state->SIOCONT &= 0x7F;
1937	1913	state->m_gb_serial_timer->enable( 0 );
1938	1914	cputag_set_input_line(machine, "maincpu", SIO_INT, ASSERT_LINE);
1939	1915	}
r14963	r14964
1946	1922	if ( state->m_triggering_irq )
1947	1923	{
1948	1924	state->m_triggering_irq = 0;
1949		if ( TIMECNT == 0 )
	1925	if ( state->TIMECNT == 0 )
1950	1926	{
1951		TIMECNT = TIMEMOD;
	1927	state->TIMECNT = state->TIMEMOD;
1952	1928	cputag_set_input_line(machine, "maincpu", TIM_INT, ASSERT_LINE );
1953	1929	state->m_reloading = 1;
1954	1930	}
r14963	r14964
1960	1936	gb_state *state = machine.driver_data<gb_state>();
1961	1937	gb_timer_check_irq(machine);
1962	1938
1963		TIMECNT += 1;
1964		if ( TIMECNT == 0 )
	1939	state->TIMECNT += 1;
	1940	if ( state->TIMECNT == 0 )
1965	1941	{
1966	1942	state->m_triggering_irq = 1;
1967	1943	}
r14963	r14964
1975	1951
1976	1952	gb_timer_check_irq(device->machine());
1977	1953
1978		if ( TIMEFRQ & 0x04 )
	1954	if ( state->TIMEFRQ & 0x04 )
1979	1955	{
1980	1956	UINT16 old_count = old_gb_divcount >> state->m_shift;
1981	1957	UINT16 new_count = state->m_divcount >> state->m_shift;
r14963	r14964
1995	1971	}
1996	1972	}
1997	1973
1998		WRITE8_HANDLER ( gbc_io2_w )
	1974	WRITE8_MEMBER(gb_state::gbc_io2_w)
1999	1975	{
2000		gb_state *state = space->machine().driver_data<gb_state>();
2001	1976	switch( offset )
2002	1977	{
2003	1978	case 0x0D:   /* KEY1 - Prepare speed switch */
2004		space->machine().device<lr35902_cpu_device>(":maincpu")->set_speed( data );
	1979	machine().device<lr35902_cpu_device>(":maincpu")->set_speed( data );
2005	1980	return;
2006	1981	case 0x10:   /* BFF - Bios disable */
2007		gb_rom16_0000( space->machine(), state->m_ROMMap[state->m_ROMBank00] );
	1982	gb_rom16_0000( machine(), m_ROMMap[m_ROMBank00] );
2008	1983	return;
2009	1984	case 0x16:   /* RP - Infrared port */
2010	1985	break;
2011	1986	case 0x30:   /* SVBK - RAM bank select */
2012		state->m_GBC_RAMBank = data & 0x7;
2013		if ( ! state->m_GBC_RAMBank )
2014		state->m_GBC_RAMBank = 1;
2015		memory_set_bankptr (space->machine(), "bank3", state->m_GBC_RAMMap[state->m_GBC_RAMBank]);
	1987	m_GBC_RAMBank = data & 0x7;
	1988	if ( ! m_GBC_RAMBank )
	1989	m_GBC_RAMBank = 1;
	1990	memory_set_bankptr (machine(), "bank3", m_GBC_RAMMap[m_GBC_RAMBank]);
2016	1991	break;
2017	1992	default:
2018	1993	break;
r14963	r14964
2020	1995	gbc_video_w( space, offset, data );
2021	1996	}
2022	1997
2023		READ8_HANDLER( gbc_io2_r )
	1998	READ8_MEMBER(gb_state::gbc_io2_r)
2024	1999	{
2025		gb_state *state = space->machine().driver_data<gb_state>();
2026	2000	switch( offset )
2027	2001	{
2028	2002	case 0x0D:   /* KEY1 */
2029		space->machine().device<lr35902_cpu_device>(":maincpu")->get_speed();
	2003	machine().device<lr35902_cpu_device>(":maincpu")->get_speed();
2030	2004	case 0x16:   /* RP - Infrared port */
2031	2005	break;
2032	2006	case 0x30:   /* SVBK - RAM bank select */
2033		return state->m_GBC_RAMBank;
	2007	return m_GBC_RAMBank;
2034	2008	default:
2035	2009	break;
2036	2010	}
r14963	r14964
2097	2071
2098	2072	**************/
2099	2073
2100		READ8_HANDLER( megaduck_video_r )
	2074	READ8_MEMBER(gb_state::megaduck_video_r)
2101	2075	{
2102	2076	UINT8 data;
2103	2077
r14963	r14964
2111	2085	return BITSWAP8(data,7,0,5,4,6,3,2,1);
2112	2086	}
2113	2087
2114		WRITE8_HANDLER ( megaduck_video_w )
	2088	WRITE8_MEMBER(gb_state::megaduck_video_w)
2115	2089	{
2116	2090	if ( !offset )
2117	2091	{
r14963	r14964
2128	2102
2129	2103	static const UINT8 megaduck_sound_offsets[16] = { 0, 2, 1, 3, 4, 6, 5, 7, 8, 9, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F };
2130	2104
2131		WRITE8_HANDLER( megaduck_sound_w1 )
	2105	WRITE8_MEMBER(gb_state::megaduck_sound_w1)
2132	2106	{
2133		gb_sound_w(space->machine().device("custom"), megaduck_sound_offsets[offset], data );
	2107	gb_sound_w(machine().device("custom"), megaduck_sound_offsets[offset], data );
2134	2108	}
2135	2109
2136		READ8_HANDLER( megaduck_sound_r1 )
	2110	READ8_MEMBER(gb_state::megaduck_sound_r1)
2137	2111	{
2138		return gb_sound_r( space->machine().device("custom"), megaduck_sound_offsets[offset] );
	2112	return gb_sound_r( machine().device("custom"), megaduck_sound_offsets[offset] );
2139	2113	}
2140	2114
2141		WRITE8_HANDLER( megaduck_sound_w2 )
	2115	WRITE8_MEMBER(gb_state::megaduck_sound_w2)
2142	2116	{
2143	2117	switch(offset)
2144	2118	{
2145		case 0x00:   gb_sound_w(space->machine().device("custom"), 0x10, data );   break;
2146		case 0x01:   gb_sound_w(space->machine().device("custom"), 0x12, data );   break;
2147		case 0x02:   gb_sound_w(space->machine().device("custom"), 0x11, data );   break;
2148		case 0x03:   gb_sound_w(space->machine().device("custom"), 0x13, data );   break;
2149		case 0x04:   gb_sound_w(space->machine().device("custom"), 0x14, data );   break;
2150		case 0x05:   gb_sound_w(space->machine().device("custom"), 0x16, data );   break;
2151		case 0x06:   gb_sound_w(space->machine().device("custom"), 0x15, data );   break;
	2119	case 0x00:   gb_sound_w(machine().device("custom"), 0x10, data );   break;
	2120	case 0x01:   gb_sound_w(machine().device("custom"), 0x12, data );   break;
	2121	case 0x02:   gb_sound_w(machine().device("custom"), 0x11, data );   break;
	2122	case 0x03:   gb_sound_w(machine().device("custom"), 0x13, data );   break;
	2123	case 0x04:   gb_sound_w(machine().device("custom"), 0x14, data );   break;
	2124	case 0x05:   gb_sound_w(machine().device("custom"), 0x16, data );   break;
	2125	case 0x06:   gb_sound_w(machine().device("custom"), 0x15, data );   break;
2152	2126	case 0x07:
2153	2127	case 0x08:
2154	2128	case 0x09:
r14963	r14964
2162	2136	}
2163	2137	}
2164	2138
2165		READ8_HANDLER( megaduck_sound_r2 )
	2139	READ8_MEMBER(gb_state::megaduck_sound_r2)
2166	2140	{
2167		return gb_sound_r(space->machine().device("custom"), 0x10 + megaduck_sound_offsets[offset]);
	2141	return gb_sound_r(machine().device("custom"), 0x10 + megaduck_sound_offsets[offset]);
2168	2142	}
2169	2143
2170		WRITE8_HANDLER( megaduck_rom_bank_select_type1 )
	2144	WRITE8_MEMBER(gb_state::megaduck_rom_bank_select_type1)
2171	2145	{
2172		gb_state *state = space->machine().driver_data<gb_state>();
2173		if( state->m_ROMMask )
	2146	if( m_ROMMask )
2174	2147	{
2175		state->m_ROMBank = data & state->m_ROMMask;
	2148	m_ROMBank = data & m_ROMMask;
2176	2149
2177	2150	/* Switch banks */
2178		memory_set_bankptr (space->machine(), "bank1", state->m_ROMMap[state->m_ROMBank]);
	2151	memory_set_bankptr (machine(), "bank1", m_ROMMap[m_ROMBank]);
2179	2152	}
2180	2153	}
2181	2154
2182		WRITE8_HANDLER( megaduck_rom_bank_select_type2 )
	2155	WRITE8_MEMBER(gb_state::megaduck_rom_bank_select_type2)
2183	2156	{
2184		gb_state *state = space->machine().driver_data<gb_state>();
2185		if( state->m_ROMMask )
	2157	if( m_ROMMask )
2186	2158	{
2187		state->m_ROMBank = (data << 1) & state->m_ROMMask;
	2159	m_ROMBank = (data << 1) & m_ROMMask;
2188	2160
2189	2161	/* Switch banks */
2190		memory_set_bankptr( space->machine(), "bank10", state->m_ROMMap[state->m_ROMBank]);
2191		memory_set_bankptr( space->machine(), "bank1", state->m_ROMMap[state->m_ROMBank + 1]);
	2162	memory_set_bankptr( machine(), "bank10", m_ROMMap[m_ROMBank]);
	2163	memory_set_bankptr( machine(), "bank1", m_ROMMap[m_ROMBank + 1]);
2192	2164	}
2193	2165	}
2194	2166

src/mess/machine/radio86.c

r14963	r14964
161	161	}
162	162
163	163
164		READ8_HANDLER (radio_cpu_state_r )
	164	READ8_MEMBER(radio86_state::radio_cpu_state_r)
165	165	{
166		return cpu_get_reg(&space->device(), I8085_STATUS);
	166	return cpu_get_reg(&space.device(), I8085_STATUS);
167	167	}
168	168
169		READ8_HANDLER (radio_io_r )
	169	READ8_MEMBER(radio86_state::radio_io_r)
170	170	{
171		return space->machine().device("maincpu")->memory().space(AS_PROGRAM)->read_byte((offset << 8) + offset);
	171	return machine().device("maincpu")->memory().space(AS_PROGRAM)->read_byte((offset << 8) + offset);
172	172	}
173	173
174		WRITE8_HANDLER(radio_io_w )
	174	WRITE8_MEMBER(radio86_state::radio_io_w)
175	175	{
176		space->machine().device("maincpu")->memory().space(AS_PROGRAM)->write_byte((offset << 8) + offset,data);
	176	machine().device("maincpu")->memory().space(AS_PROGRAM)->write_byte((offset << 8) + offset,data);
177	177	}
178	178
179	179	MACHINE_RESET( radio86 )
r14963	r14964
187	187	}
188	188
189	189
190		WRITE8_HANDLER ( radio86_pagesel )
	190	WRITE8_MEMBER(radio86_state::radio86_pagesel)
191	191	{
192		radio86_state *state = space->machine().driver_data<radio86_state>();
193		state->m_disk_sel = data;
	192	m_disk_sel = data;
194	193	}
195	194
196	195	static READ8_DEVICE_HANDLER (radio86_romdisk_porta_r )

src/mess/machine/b2m.c

r14963	r14964
19	19	#include "machine/ram.h"
20	20	#include "imagedev/flopdrv.h"
21	21
22		static READ8_HANDLER (b2m_keyboard_r )
	22	READ8_MEMBER(b2m_state::b2m_keyboard_r)
23	23	{
24	24	UINT8 key = 0x00;
25	25	if (offset < 0x100) {
26		if ((offset & 0x01)!=0) { key |= input_port_read(space->machine(),"LINE0"); }
27		if ((offset & 0x02)!=0) { key |= input_port_read(space->machine(),"LINE1"); }
28		if ((offset & 0x04)!=0) { key |= input_port_read(space->machine(),"LINE2"); }
29		if ((offset & 0x08)!=0) { key |= input_port_read(space->machine(),"LINE3"); }
30		if ((offset & 0x10)!=0) { key |= input_port_read(space->machine(),"LINE4"); }
31		if ((offset & 0x20)!=0) { key |= input_port_read(space->machine(),"LINE5"); }
32		if ((offset & 0x40)!=0) { key |= input_port_read(space->machine(),"LINE6"); }
33		if ((offset & 0x80)!=0) { key |= input_port_read(space->machine(),"LINE7"); }
	26	if ((offset & 0x01)!=0) { key |= input_port_read(machine(),"LINE0"); }
	27	if ((offset & 0x02)!=0) { key |= input_port_read(machine(),"LINE1"); }
	28	if ((offset & 0x04)!=0) { key |= input_port_read(machine(),"LINE2"); }
	29	if ((offset & 0x08)!=0) { key |= input_port_read(machine(),"LINE3"); }
	30	if ((offset & 0x10)!=0) { key |= input_port_read(machine(),"LINE4"); }
	31	if ((offset & 0x20)!=0) { key |= input_port_read(machine(),"LINE5"); }
	32	if ((offset & 0x40)!=0) { key |= input_port_read(machine(),"LINE6"); }
	33	if ((offset & 0x80)!=0) { key |= input_port_read(machine(),"LINE7"); }
34	34	} else {
35		if ((offset & 0x01)!=0) { key |= input_port_read(space->machine(),"LINE8"); }
36		if ((offset & 0x02)!=0) { key |= input_port_read(space->machine(),"LINE9"); }
37		if ((offset & 0x04)!=0) { key |= input_port_read(space->machine(),"LINE10"); }
	35	if ((offset & 0x01)!=0) { key |= input_port_read(machine(),"LINE8"); }
	36	if ((offset & 0x02)!=0) { key |= input_port_read(machine(),"LINE9"); }
	37	if ((offset & 0x04)!=0) { key |= input_port_read(machine(),"LINE10"); }
38	38	}
39	39	return key;
40	40	}
r14963	r14964
43	43	static void b2m_set_bank(running_machine &machine,int bank)
44	44	{
45	45	UINT8 *rom;
	46	b2m_state *state =  machine.driver_data<b2m_state>();
46	47	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
47	48	UINT8 *ram = machine.device<ram_device>(RAM_TAG)->pointer();
48	49
r14963	r14964
81	82	space->unmap_write(0xe000, 0xffff);
82	83
83	84	memory_set_bankptr(machine, "bank1", ram);
84		space->install_legacy_read_handler(0x2800, 0x2fff, FUNC(b2m_keyboard_r));
	85	space->install_read_handler(0x2800, 0x2fff, read8_delegate(FUNC(b2m_state::b2m_keyboard_r),state));
85	86	memory_set_bankptr(machine, "bank3", ram + 0x10000);
86	87	memory_set_bankptr(machine, "bank4", ram + 0x7000);
87	88	memory_set_bankptr(machine, "bank5", rom + 0x10000);
r14963	r14964
91	92	space->unmap_write(0xe000, 0xffff);
92	93
93	94	memory_set_bankptr(machine, "bank1", ram);
94		space->install_legacy_read_handler(0x2800, 0x2fff, FUNC(b2m_keyboard_r));
	95	space->install_read_handler(0x2800, 0x2fff, read8_delegate(FUNC(b2m_state::b2m_keyboard_r),state));
95	96	memory_set_bankptr(machine, "bank3", ram + 0x14000);
96	97	memory_set_bankptr(machine, "bank4", ram + 0x7000);
97	98	memory_set_bankptr(machine, "bank5", rom + 0x10000);
r14963	r14964
101	102	space->unmap_write(0xe000, 0xffff);
102	103
103	104	memory_set_bankptr(machine, "bank1", ram);
104		space->install_legacy_read_handler(0x2800, 0x2fff, FUNC(b2m_keyboard_r));
	105	space->install_read_handler(0x2800, 0x2fff, read8_delegate(FUNC(b2m_state::b2m_keyboard_r),state));
105	106	memory_set_bankptr(machine, "bank3", ram + 0x18000);
106	107	memory_set_bankptr(machine, "bank4", ram + 0x7000);
107	108	memory_set_bankptr(machine, "bank5", rom + 0x10000);
r14963	r14964
112	113	space->unmap_write(0xe000, 0xffff);
113	114
114	115	memory_set_bankptr(machine, "bank1", ram);
115		space->install_legacy_read_handler(0x2800, 0x2fff, FUNC(b2m_keyboard_r));
	116	space->install_read_handler(0x2800, 0x2fff, read8_delegate(FUNC(b2m_state::b2m_keyboard_r),state));
116	117	memory_set_bankptr(machine, "bank3", ram + 0x1c000);
117	118	memory_set_bankptr(machine, "bank4", ram + 0x7000);
118	119	memory_set_bankptr(machine, "bank5", rom + 0x10000);
r14963	r14964
282	283	state->m_vblank_state = 0;
283	284	}
284	285
285		WRITE8_HANDLER ( b2m_palette_w )
	286	WRITE8_MEMBER(b2m_state::b2m_palette_w)
286	287	{
287		b2m_state *state = space->machine().driver_data<b2m_state>();
288	288
289	289	UINT8 b = (3 - ((data >> 6) & 3)) * 0x55;
290	290	UINT8 g = (3 - ((data >> 4) & 3)) * 0x55;
r14963	r14964
292	292
293	293	UINT8 bw = (3 - (data & 3)) * 0x55;
294	294
295		state->m_b2m_color[offset & 3] = data;
	295	m_b2m_color[offset & 3] = data;
296	296
297		if (input_port_read(space->machine(),"MONITOR")==1) {
298		palette_set_color_rgb(space->machine(),offset, r, g, b);
	297	if (input_port_read(machine(),"MONITOR")==1) {
	298	palette_set_color_rgb(machine(),offset, r, g, b);
299	299	} else {
300		palette_set_color_rgb(space->machine(),offset, bw, bw, bw);
	300	palette_set_color_rgb(machine(),offset, bw, bw, bw);
301	301	}
302	302	}
303	303
304		READ8_HANDLER ( b2m_palette_r )
	304	READ8_MEMBER(b2m_state::b2m_palette_r)
305	305	{
306		b2m_state *state = space->machine().driver_data<b2m_state>();
307		return state->m_b2m_color[offset];
	306	return m_b2m_color[offset];
308	307	}
309	308
310		WRITE8_HANDLER ( b2m_localmachine_w )
	309	WRITE8_MEMBER(b2m_state::b2m_localmachine_w)
311	310	{
312		b2m_state *state = space->machine().driver_data<b2m_state>();
313		state->m_b2m_localmachine = data;
	311	m_b2m_localmachine = data;
314	312	}
315	313
316		READ8_HANDLER ( b2m_localmachine_r )
	314	READ8_MEMBER(b2m_state::b2m_localmachine_r)
317	315	{
318		b2m_state *state = space->machine().driver_data<b2m_state>();
319		return state->m_b2m_localmachine;
	316	return m_b2m_localmachine;
320	317	}
321	318
322	319	static void b2m_postload(b2m_state *state)

src/mess/machine/oric.c

r14963	r14964
140	140
141	141
142	142	/* this is executed when a write to psg port a is done */
143		WRITE8_HANDLER (oric_psg_porta_write)
	143	WRITE8_MEMBER(oric_state::oric_psg_porta_write)
144	144	{
145		oric_state *state = space->machine().driver_data<oric_state>();
146		state->m_keyboard_mask = data;
	145	m_keyboard_mask = data;
147	146	}
148	147
149	148
r14963	r14964
473	472	if (state->m_is_telestrat)
474	473	return;
475	474
476		space->install_legacy_read_handler(0x0300, 0x030f, FUNC(oric_IO_r));
	475	space->install_read_handler(0x0300, 0x030f, read8_delegate(FUNC(oric_state::oric_IO_r),state));
477	476	space->install_legacy_read_handler(*fdc, 0x0310, 0x031f, FUNC(applefdc_r));
478	477	space->install_read_bank(0x0320, 0x03ff, "bank4");
479	478
480		space->install_legacy_write_handler(0x0300, 0x030f, FUNC(oric_IO_w));
	479	space->install_write_handler(0x0300, 0x030f, write8_delegate(FUNC(oric_state::oric_IO_w),state));
481	480	space->install_legacy_write_handler(*fdc, 0x0310, 0x031f, FUNC(applefdc_w));
482	481	memory_set_bankptr(machine, "bank4",   machine.region("maincpu")->base() + 0x014000 + 0x020);
483	482	}
r14963	r14964
543	542	CALL &320 to start, or use BOBY rom.
544	543	*/
545	544
546		static WRITE8_HANDLER(apple2_v2_interface_w)
	545	WRITE8_MEMBER(oric_state::apple2_v2_interface_w)
547	546	{
548		oric_state *state = space->machine().driver_data<oric_state>();
549	547	/* data is ignored, address is used to decode operation */
550		if (state->m_is_telestrat)
	548	if (m_is_telestrat)
551	549	return;
552	550
553	551	/*  logerror("apple 2 interface v2 rom page: %01x\n",(offset & 0x02)>>1); */
554	552
555	553	/* bit 0 is 0 for page 0, 1 for page 1 */
556		memory_set_bankptr(space->machine(), "bank4", space->machine().region("maincpu")->base() + 0x014000 + 0x0100 + (((offset & 0x02)>>1)<<8));
	554	memory_set_bankptr(machine(), "bank4", machine().region("maincpu")->base() + 0x014000 + 0x0100 + (((offset & 0x02)>>1)<<8));
557	555
558		oric_enable_memory(space->machine(), 1, 3, TRUE, TRUE);
	556	oric_enable_memory(machine(), 1, 3, TRUE, TRUE);
559	557
560	558	/* bit 1 is 0, rom enabled, bit 1 is 1 ram enabled */
561	559	if ((offset & 0x01)==0)
r14963	r14964
565	563	/* logerror("apple 2 interface v2: rom enabled\n"); */
566	564
567	565	/* enable rom */
568		rom_ptr = space->machine().region("maincpu")->base() + 0x010000;
569		memory_set_bankptr(space->machine(), "bank1", rom_ptr);
570		memory_set_bankptr(space->machine(), "bank2", rom_ptr+0x02000);
571		memory_set_bankptr(space->machine(), "bank3", rom_ptr+0x03800);
572		memory_set_bankptr(space->machine(), "bank5", state->m_ram_0x0c000);
573		memory_set_bankptr(space->machine(), "bank6", state->m_ram_0x0c000+0x02000);
574		memory_set_bankptr(space->machine(), "bank7", state->m_ram_0x0c000+0x03800);
	566	rom_ptr = machine().region("maincpu")->base() + 0x010000;
	567	memory_set_bankptr(machine(), "bank1", rom_ptr);
	568	memory_set_bankptr(machine(), "bank2", rom_ptr+0x02000);
	569	memory_set_bankptr(machine(), "bank3", rom_ptr+0x03800);
	570	memory_set_bankptr(machine(), "bank5", m_ram_0x0c000);
	571	memory_set_bankptr(machine(), "bank6", m_ram_0x0c000+0x02000);
	572	memory_set_bankptr(machine(), "bank7", m_ram_0x0c000+0x03800);
575	573	}
576	574	else
577	575	{
578	576	/*logerror("apple 2 interface v2: ram enabled\n"); */
579	577
580	578	/* enable ram */
581		memory_set_bankptr(space->machine(), "bank1", state->m_ram_0x0c000);
582		memory_set_bankptr(space->machine(), "bank2", state->m_ram_0x0c000+0x02000);
583		memory_set_bankptr(space->machine(), "bank3", state->m_ram_0x0c000+0x03800);
584		memory_set_bankptr(space->machine(), "bank5", state->m_ram_0x0c000);
585		memory_set_bankptr(space->machine(), "bank6", state->m_ram_0x0c000+0x02000);
586		memory_set_bankptr(space->machine(), "bank7", state->m_ram_0x0c000+0x03800);
	579	memory_set_bankptr(machine(), "bank1", m_ram_0x0c000);
	580	memory_set_bankptr(machine(), "bank2", m_ram_0x0c000+0x02000);
	581	memory_set_bankptr(machine(), "bank3", m_ram_0x0c000+0x03800);
	582	memory_set_bankptr(machine(), "bank5", m_ram_0x0c000);
	583	memory_set_bankptr(machine(), "bank6", m_ram_0x0c000+0x02000);
	584	memory_set_bankptr(machine(), "bank7", m_ram_0x0c000+0x03800);
587	585	}
588	586	}
589	587
r14963	r14964
591	589	/* APPLE 2 INTERFACE V2 */
592	590	static void oric_install_apple2_v2_interface(running_machine &machine)
593	591	{
	592	oric_state *state = machine.driver_data<oric_state>();
594	593	device_t *fdc = machine.device("fdc");
595	594	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
596	595
597		space->install_legacy_read_handler(0x0300, 0x030f, FUNC(oric_IO_r));
	596	space->install_read_handler(0x0300, 0x030f, read8_delegate(FUNC(oric_state::oric_IO_r),state));
598	597	space->install_legacy_read_handler(*fdc, 0x0310, 0x031f, FUNC(applefdc_r));
599	598	space->install_read_bank(0x0320, 0x03ff, "bank4");
600	599
601		space->install_legacy_write_handler(0x0300, 0x030f, FUNC(oric_IO_w));
	600	space->install_write_handler(0x0300, 0x030f, write8_delegate(FUNC(oric_state::oric_IO_w),state));
602	601	space->install_legacy_write_handler(*fdc, 0x0310, 0x031f, FUNC(applefdc_w));
603		space->install_legacy_write_handler(0x0380, 0x0383, FUNC(apple2_v2_interface_w));
	602	space->install_write_handler(0x0380, 0x0383, write8_delegate(FUNC(oric_state::apple2_v2_interface_w),state));
604	603
605		apple2_v2_interface_w(space, 0, 0);
	604	state->apple2_v2_interface_w(*space, 0, 0);
606	605	}
607	606
608	607	/********************/
r14963	r14964
710	709	oric_refresh_ints(device->machine());
711	710	}
712	711
713		static READ8_HANDLER (oric_jasmin_r)
	712	READ8_MEMBER(oric_state::oric_jasmin_r)
714	713	{
715		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
716		device_t *fdc = space->machine().device("wd179x");
	714	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	715	device_t *fdc = machine().device("wd179x");
717	716	unsigned char data = 0x0ff;
718	717
719	718	switch (offset & 0x0f)
r14963	r14964
732	731	data = wd17xx_data_r(fdc, 0);
733	732	break;
734	733	default:
735		data = via_0->read(*space,offset & 0x0f);
	734	data = via_0->read(space,offset & 0x0f);
736	735	//logerror("unhandled io read: %04x %02x\n", offset, data);
737	736	break;
738	737
r14963	r14964
741	740	return data;
742	741	}
743	742
744		static WRITE8_HANDLER(oric_jasmin_w)
	743	WRITE8_MEMBER(oric_state::oric_jasmin_w)
745	744	{
746		oric_state *state = space->machine().driver_data<oric_state>();
747		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
748		device_t *fdc = space->machine().device("wd179x");
	745	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	746	device_t *fdc = machine().device("wd179x");
749	747	switch (offset & 0x0f)
750	748	{
751	749	/* microdisc floppy disc interface */
r14963	r14964
770	768	wd17xx_reset(fdc);
771	769	break;
772	770	case 0x0a:
773		//logerror("jasmin overlay ram w: %02x PC: %04x\n", data, cpu_get_pc(space->machine().device("maincpu")));
774		state->m_port_3fa_w = data;
775		oric_jasmin_set_mem_0x0c000(space->machine());
	771	//logerror("jasmin overlay ram w: %02x PC: %04x\n", data, cpu_get_pc(machine().device("maincpu")));
	772	m_port_3fa_w = data;
	773	oric_jasmin_set_mem_0x0c000(machine());
776	774	break;
777	775	case 0x0b:
778		//logerror("jasmin romdis w: %02x PC: %04x\n", data, cpu_get_pc(space->machine().device("maincpu")));
779		state->m_port_3fb_w = data;
780		oric_jasmin_set_mem_0x0c000(space->machine());
	776	//logerror("jasmin romdis w: %02x PC: %04x\n", data, cpu_get_pc(machine().device("maincpu")));
	777	m_port_3fb_w = data;
	778	oric_jasmin_set_mem_0x0c000(machine());
781	779	break;
782	780	/* bit 0,1 of addr is the drive */
783	781	case 0x0c:
r14963	r14964
788	786	break;
789	787
790	788	default:
791		via_0->write(*space,offset & 0x0f, data);
	789	via_0->write(space,offset & 0x0f, data);
792	790	break;
793	791	}
794	792	}
r14963	r14964
802	800	state->m_port_3fb_w = 1;
803	801	oric_jasmin_set_mem_0x0c000(machine);
804	802
805		space->install_legacy_read_handler(0x0300, 0x03ef, FUNC(oric_IO_r));
806		space->install_legacy_read_handler(0x03f0, 0x03ff, FUNC(oric_jasmin_r));
	803	space->install_read_handler(0x0300, 0x03ef, read8_delegate(FUNC(oric_state::oric_IO_r),state));
	804	space->install_read_handler(0x03f0, 0x03ff, read8_delegate(FUNC(oric_state::oric_jasmin_r),state));
807	805
808		space->install_legacy_write_handler(0x0300, 0x03ef, FUNC(oric_IO_w));
809		space->install_legacy_write_handler(0x03f0, 0x03ff, FUNC(oric_jasmin_w));
	806	space->install_write_handler(0x0300, 0x03ef, write8_delegate(FUNC(oric_state::oric_IO_w),state));
	807	space->install_write_handler(0x03f0, 0x03ff, write8_delegate(FUNC(oric_state::oric_jasmin_w),state));
810	808	}
811	809
812	810	/*********************************/
r14963	r14964
930	928
931	929
932	930
933		READ8_HANDLER (oric_microdisc_r)
	931	READ8_MEMBER(oric_state::oric_microdisc_r)
934	932	{
935		oric_state *state = space->machine().driver_data<oric_state>();
936	933	unsigned char data = 0x0ff;
937		device_t *fdc = space->machine().device("wd179x");
	934	device_t *fdc = machine().device("wd179x");
938	935
939	936	switch (offset & 0x0ff)
940	937	{
r14963	r14964
952	949	data = wd17xx_data_r(fdc, 0);
953	950	break;
954	951	case 0x04:
955		data = state->m_port_314_r | 0x07f;
	952	data = m_port_314_r | 0x07f;
956	953	/*          logerror("port_314_r: %02x\n",data); */
957	954	break;
958	955	case 0x08:
959		data = state->m_port_318_r | 0x07f;
	956	data = m_port_318_r | 0x07f;
960	957	/*          logerror("port_318_r: %02x\n",data); */
961	958	break;
962	959
963	960	default:
964	961	{
965		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
966		data = via_0->read(*space, offset & 0x0f);
	962	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	963	data = via_0->read(space, offset & 0x0f);
967	964	}
968	965	break;
969	966
r14963	r14964
972	969	return data;
973	970	}
974	971
975		WRITE8_HANDLER(oric_microdisc_w)
	972	WRITE8_MEMBER(oric_state::oric_microdisc_w)
976	973	{
977		oric_state *state = space->machine().driver_data<oric_state>();
978		device_t *fdc = space->machine().device("wd179x");
	974	device_t *fdc = machine().device("wd179x");
979	975	switch (offset & 0x0ff)
980	976	{
981	977	/* microdisc floppy disc interface */
r14963	r14964
993	989	break;
994	990	case 0x04:
995	991	{
996		state->m_port_314_w = data;
	992	m_port_314_w = data;
997	993
998	994	//logerror("port_314_w: %02x\n",data);
999	995
r14963	r14964
1005	1001	wd17xx_set_side(fdc,(data>>4) & 0x01);
1006	1002	wd17xx_dden_w(fdc, !BIT(data, 3));
1007	1003
1008		oric_microdisc_set_mem_0x0c000(space->machine());
1009		oric_microdisc_refresh_wd179x_ints(space->machine());
	1004	oric_microdisc_set_mem_0x0c000(machine());
	1005	oric_microdisc_refresh_wd179x_ints(machine());
1010	1006	}
1011	1007	break;
1012	1008
1013	1009	default:
1014	1010	{
1015		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
1016		via_0->write(*space, offset & 0x0f, data);
	1011	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	1012	via_0->write(space, offset & 0x0f, data);
1017	1013	}
1018	1014	break;
1019	1015	}
r14963	r14964
1024	1020	oric_state *state = machine.driver_data<oric_state>();
1025	1021	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
1026	1022
1027		space->install_legacy_read_handler(0x0300, 0x030f, FUNC(oric_IO_r));
1028		space->install_legacy_read_handler(0x0310, 0x031f, FUNC(oric_microdisc_r));
1029		space->install_legacy_read_handler(0x0320, 0x03ff, FUNC(oric_IO_r));
	1023	space->install_read_handler(0x0300, 0x030f, read8_delegate(FUNC(oric_state::oric_IO_r),state));
	1024	space->install_read_handler(0x0310, 0x031f, read8_delegate(FUNC(oric_state::oric_microdisc_r),state));
	1025	space->install_read_handler(0x0320, 0x03ff, read8_delegate(FUNC(oric_state::oric_IO_r),state));
1030	1026
1031		space->install_legacy_write_handler(0x0300, 0x030f, FUNC(oric_IO_w));
1032		space->install_legacy_write_handler(0x0310, 0x031f, FUNC(oric_microdisc_w));
1033		space->install_legacy_write_handler(0x0320, 0x03ff, FUNC(oric_IO_w));
	1027	space->install_write_handler(0x0300, 0x030f, write8_delegate(FUNC(oric_state::oric_IO_w),state));
	1028	space->install_write_handler(0x0310, 0x031f, write8_delegate(FUNC(oric_state::oric_microdisc_w),state));
	1029	space->install_write_handler(0x0320, 0x03ff, write8_delegate(FUNC(oric_state::oric_IO_w),state));
1034	1030
1035	1031	/* disable os rom, enable microdisc rom */
1036	1032	/* 0x0c000-0x0dfff will be ram, 0x0e000-0x0ffff will be microdisc rom */
r14963	r14964
1130	1126	}
1131	1127	else
1132	1128	{
1133		space->install_legacy_read_handler(0x0300, 0x03ff, FUNC(oric_IO_r));
1134		space->install_legacy_write_handler(0x0300, 0x03ff, FUNC(oric_IO_w));
	1129	space->install_read_handler(0x0300, 0x03ff, read8_delegate(FUNC(oric_state::oric_IO_r),state));
	1130	space->install_write_handler(0x0300, 0x03ff, write8_delegate(FUNC(oric_state::oric_IO_w),state));
1135	1131	}
1136	1132	}
1137	1133	break;
r14963	r14964
1159	1155	}
1160	1156
1161	1157
1162		READ8_HANDLER ( oric_IO_r )
	1158	READ8_MEMBER(oric_state::oric_IO_r)
1163	1159	{
1164		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
1165		switch (input_port_read(space->machine(), "FLOPPY") & 0x07)
	1160	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	1161	switch (input_port_read(machine(), "FLOPPY") & 0x07)
1166	1162	{
1167	1163	default:
1168	1164	case ORIC_FLOPPY_INTERFACE_NONE:
r14963	r14964
1190	1186	{
1191	1187	if ((offset & 0x0f)!=0x0d)
1192	1188	{
1193		//logerror("via 0 r: %04x %04x\n",offset, (unsigned) cpu_get_reg(space->machine().device("maincpu"), STATE_GENPC));
	1189	//logerror("via 0 r: %04x %04x\n",offset, (unsigned) cpu_get_reg(machine().device("maincpu"), STATE_GENPC));
1194	1190	}
1195	1191	}
1196	1192	/* it is repeated */
1197		return via_0->read(*space, offset & 0x0f);
	1193	return via_0->read(space, offset & 0x0f);
1198	1194	}
1199	1195
1200		WRITE8_HANDLER ( oric_IO_w )
	1196	WRITE8_MEMBER(oric_state::oric_IO_w)
1201	1197	{
1202		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
1203		switch (input_port_read(space->machine(), "FLOPPY") & 0x07)
	1198	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	1199	switch (input_port_read(machine(), "FLOPPY") & 0x07)
1204	1200	{
1205	1201	default:
1206	1202	case ORIC_FLOPPY_INTERFACE_NONE:
r14963	r14964
1229	1225	}
1230	1226	if (enable_logging)
1231	1227	{
1232		//logerror("via 0 w: %04x %02x %04x\n", offset, data,(unsigned) cpu_get_reg(space->machine().device("maincpu"), STATE_GENPC));
	1228	//logerror("via 0 w: %04x %02x %04x\n", offset, data,(unsigned) cpu_get_reg(machine().device("maincpu"), STATE_GENPC));
1233	1229	}
1234	1230
1235		via_0->write(*space, offset & 0x0f, data);
	1231	via_0->write(space, offset & 0x0f, data);
1236	1232	}
1237	1233
1238	1234

src/mess/machine/orao.c

r14963	r14964
30	30	{
31	31	}
32	32
33		READ8_HANDLER( orao_io_r )
	33	READ8_MEMBER(orao_state::orao_io_r)
34	34	{
35	35	double level;
36	36
37	37	switch(offset) {
38	38	/* Keyboard*/
39		case 0x07FC : return input_port_read(space->machine(), "LINE0");
40		case 0x07FD : return input_port_read(space->machine(), "LINE1");
41		case 0x07FA : return input_port_read(space->machine(), "LINE2");
42		case 0x07FB : return input_port_read(space->machine(), "LINE3");
43		case 0x07F6 : return input_port_read(space->machine(), "LINE4");
44		case 0x07F7 : return input_port_read(space->machine(), "LINE5");
45		case 0x07EE : return input_port_read(space->machine(), "LINE6");
46		case 0x07EF : return input_port_read(space->machine(), "LINE7");
47		case 0x07DE : return input_port_read(space->machine(), "LINE8");
48		case 0x07DF : return input_port_read(space->machine(), "LINE9");
49		case 0x07BE : return input_port_read(space->machine(), "LINE10");
50		case 0x07BF : return input_port_read(space->machine(), "LINE11");
51		case 0x077E : return input_port_read(space->machine(), "LINE12");
52		case 0x077F : return input_port_read(space->machine(), "LINE13");
53		case 0x06FE : return input_port_read(space->machine(), "LINE14");
54		case 0x06FF : return input_port_read(space->machine(), "LINE15");
55		case 0x05FE : return input_port_read(space->machine(), "LINE16");
56		case 0x05FF : return input_port_read(space->machine(), "LINE17");
57		case 0x03FE : return input_port_read(space->machine(), "LINE18");
58		case 0x03FF : return input_port_read(space->machine(), "LINE19");
	39	case 0x07FC : return input_port_read(machine(), "LINE0");
	40	case 0x07FD : return input_port_read(machine(), "LINE1");
	41	case 0x07FA : return input_port_read(machine(), "LINE2");
	42	case 0x07FB : return input_port_read(machine(), "LINE3");
	43	case 0x07F6 : return input_port_read(machine(), "LINE4");
	44	case 0x07F7 : return input_port_read(machine(), "LINE5");
	45	case 0x07EE : return input_port_read(machine(), "LINE6");
	46	case 0x07EF : return input_port_read(machine(), "LINE7");
	47	case 0x07DE : return input_port_read(machine(), "LINE8");
	48	case 0x07DF : return input_port_read(machine(), "LINE9");
	49	case 0x07BE : return input_port_read(machine(), "LINE10");
	50	case 0x07BF : return input_port_read(machine(), "LINE11");
	51	case 0x077E : return input_port_read(machine(), "LINE12");
	52	case 0x077F : return input_port_read(machine(), "LINE13");
	53	case 0x06FE : return input_port_read(machine(), "LINE14");
	54	case 0x06FF : return input_port_read(machine(), "LINE15");
	55	case 0x05FE : return input_port_read(machine(), "LINE16");
	56	case 0x05FF : return input_port_read(machine(), "LINE17");
	57	case 0x03FE : return input_port_read(machine(), "LINE18");
	58	case 0x03FF : return input_port_read(machine(), "LINE19");
59	59	/* Tape */
60	60	case 0x07FF :
61		level = (space->machine().device<cassette_image_device>(CASSETTE_TAG)->input());
	61	level = (machine().device<cassette_image_device>(CASSETTE_TAG)->input());
62	62	if (level <  0) {
63	63	return 0x00;
64	64	}
r14963	r14964
70	70	}
71	71
72	72
73		WRITE8_HANDLER( orao_io_w )
	73	WRITE8_MEMBER(orao_state::orao_io_w)
74	74	{
75	75	if (offset == 0x0800)
76	76	{
77		device_t *dac_device = space->machine().device("dac");
	77	device_t *dac_device = machine().device("dac");
78	78	dac_data_w(dac_device, data); //beeper
79	79	}
80	80	}

src/mess/machine/bk.c

r14963	r14964
87	87	state->m_scrool = 01330;
88	88	}
89	89
90		READ16_HANDLER (bk_key_state_r)
	90	READ16_MEMBER(bk_state::bk_key_state_r)
91	91	{
92		bk_state *state = space->machine().driver_data<bk_state>();
93		return state->m_kbd_state;
	92	return m_kbd_state;
94	93	}
95		READ16_HANDLER (bk_key_code_r)
	94	READ16_MEMBER(bk_state::bk_key_code_r)
96	95	{
97		bk_state *state = space->machine().driver_data<bk_state>();
98		state->m_kbd_state &= ~0x80; // mark reading done
99		state->m_key_pressed = 0;
100		return state->m_key_code;
	96	m_kbd_state &= ~0x80; // mark reading done
	97	m_key_pressed = 0;
	98	return m_key_code;
101	99	}
102		READ16_HANDLER (bk_vid_scrool_r)
	100	READ16_MEMBER(bk_state::bk_vid_scrool_r)
103	101	{
104		bk_state *state = space->machine().driver_data<bk_state>();
105		return state->m_scrool;
	102	return m_scrool;
106	103	}
107	104
108		READ16_HANDLER (bk_key_press_r)
	105	READ16_MEMBER(bk_state::bk_key_press_r)
109	106	{
110		bk_state *state = space->machine().driver_data<bk_state>();
111		double level = (space->machine().device<cassette_image_device>(CASSETTE_TAG)->input());
	107	double level = (machine().device<cassette_image_device>(CASSETTE_TAG)->input());
112	108	UINT16 cas;
113	109	if (level < 0)
114	110	{
r14963	r14964
119	115	cas = 0x20;
120	116	}
121	117
122		return 0x8080 | state->m_key_pressed | cas;
	118	return 0x8080 | m_key_pressed | cas;
123	119	}
124	120
125		WRITE16_HANDLER(bk_key_state_w)
	121	WRITE16_MEMBER(bk_state::bk_key_state_w)
126	122	{
127		bk_state *state = space->machine().driver_data<bk_state>();
128		state->m_kbd_state = (state->m_kbd_state & ~0x40) | (data & 0x40);
	123	m_kbd_state = (m_kbd_state & ~0x40) | (data & 0x40);
129	124	}
130	125
131		WRITE16_HANDLER(bk_vid_scrool_w)
	126	WRITE16_MEMBER(bk_state::bk_vid_scrool_w)
132	127	{
133		bk_state *state = space->machine().driver_data<bk_state>();
134		state->m_scrool = data;
	128	m_scrool = data;
135	129	}
136	130
137		WRITE16_HANDLER(bk_key_press_w)
	131	WRITE16_MEMBER(bk_state::bk_key_press_w)
138	132	{
139	133	}
140	134
141		READ16_HANDLER (bk_floppy_cmd_r)
	135	READ16_MEMBER(bk_state::bk_floppy_cmd_r)
142	136	{
143	137	return 0;
144	138	}
145	139
146		WRITE16_HANDLER(bk_floppy_cmd_w)
	140	WRITE16_MEMBER(bk_state::bk_floppy_cmd_w)
147	141	{
148		bk_state *state = space->machine().driver_data<bk_state>();
149	142	if ((data & 1) == 1)
150	143	{
151		state->m_drive = 0;
	144	m_drive = 0;
152	145	}
153	146	if ((data & 2) == 2)
154	147	{
155		state->m_drive = 1;
	148	m_drive = 1;
156	149	}
157	150	if ((data & 4) == 4)
158	151	{
159		state->m_drive = 2;
	152	m_drive = 2;
160	153	}
161	154	if ((data & 8) == 8)
162	155	{
163		state->m_drive = 3;
	156	m_drive = 3;
164	157	}
165	158	if (data == 0)
166	159	{
167		state->m_drive = -1;
	160	m_drive = -1;
168	161	}
169	162	}
170	163
171		READ16_HANDLER (bk_floppy_data_r)
	164	READ16_MEMBER(bk_state::bk_floppy_data_r)
172	165	{
173	166	return 0;
174	167	}
175	168
176		WRITE16_HANDLER(bk_floppy_data_w)
	169	WRITE16_MEMBER(bk_state::bk_floppy_data_w)
177	170	{
178	171	}
179	172

src/mess/machine/sapi1.c

r14963	r14964
27	27	{
28	28	}
29	29
30		READ8_HANDLER (sapi1_keyboard_r )
	30	READ8_MEMBER(sapi1_state::sapi1_keyboard_r)
31	31	{
32		sapi1_state *state = space->machine().driver_data<sapi1_state>();
33	32	UINT8 key = 0xff;
34		if ((state->m_keyboard_mask & 0x01)!=0) { key &= input_port_read(space->machine(),"LINE0"); }
35		if ((state->m_keyboard_mask & 0x02)!=0) { key &= input_port_read(space->machine(),"LINE1"); }
36		if ((state->m_keyboard_mask & 0x04)!=0) { key &= input_port_read(space->machine(),"LINE2"); }
37		if ((state->m_keyboard_mask & 0x08)!=0) { key &= input_port_read(space->machine(),"LINE3"); }
38		if ((state->m_keyboard_mask & 0x10)!=0) { key &= input_port_read(space->machine(),"LINE4"); }
	33	if ((m_keyboard_mask & 0x01)!=0) { key &= input_port_read(machine(),"LINE0"); }
	34	if ((m_keyboard_mask & 0x02)!=0) { key &= input_port_read(machine(),"LINE1"); }
	35	if ((m_keyboard_mask & 0x04)!=0) { key &= input_port_read(machine(),"LINE2"); }
	36	if ((m_keyboard_mask & 0x08)!=0) { key &= input_port_read(machine(),"LINE3"); }
	37	if ((m_keyboard_mask & 0x10)!=0) { key &= input_port_read(machine(),"LINE4"); }
39	38	return key;
40	39	}
41		WRITE8_HANDLER(sapi1_keyboard_w )
	40	WRITE8_MEMBER(sapi1_state::sapi1_keyboard_w)
42	41	{
43		sapi1_state *state = space->machine().driver_data<sapi1_state>();
44		state->m_keyboard_mask = (data ^ 0xff ) & 0x1f;
	42	m_keyboard_mask = (data ^ 0xff ) & 0x1f;
45	43	}
46	44
47	45

src/mess/machine/amstrad.c

r14963	r14964
1191	1191
1192	1192	if ( state->m_asic.enabled && ( state->m_asic.rmr2 & 0x18 ) == 0x18 )
1193	1193	{
1194		space->install_legacy_read_handler(0x4000, 0x5fff, FUNC(amstrad_plus_asic_4000_r));
1195		space->install_legacy_read_handler(0x6000, 0x7fff, FUNC(amstrad_plus_asic_6000_r));
1196		space->install_legacy_write_handler(0x4000, 0x5fff, FUNC(amstrad_plus_asic_4000_w));
1197		space->install_legacy_write_handler(0x6000, 0x7fff, FUNC(amstrad_plus_asic_6000_w));
	1194	space->install_read_handler(0x4000, 0x5fff, read8_delegate(FUNC(amstrad_state::amstrad_plus_asic_4000_r),state));
	1195	space->install_read_handler(0x6000, 0x7fff, read8_delegate(FUNC(amstrad_state::amstrad_plus_asic_6000_r),state));
	1196	space->install_write_handler(0x4000, 0x5fff, write8_delegate(FUNC(amstrad_state::amstrad_plus_asic_4000_w),state));
	1197	space->install_write_handler(0x6000, 0x7fff, write8_delegate(FUNC(amstrad_state::amstrad_plus_asic_6000_w),state));
1198	1198	}
1199	1199	else
1200	1200	{
r14963	r14964
1394	1394
1395	1395	*/
1396	1396
1397		WRITE8_HANDLER( amstrad_plus_asic_4000_w )
	1397	WRITE8_MEMBER(amstrad_state::amstrad_plus_asic_4000_w)
1398	1398	{
1399		amstrad_state *state = space->machine().driver_data<amstrad_state>();
1400	1399	//  logerror("ASIC: Write to register at &%04x\n",offset+0x4000);
1401		state->m_asic.ram[offset] = data & 0x0f;
	1400	m_asic.ram[offset] = data & 0x0f;
1402	1401	}
1403	1402
1404	1403
1405		WRITE8_HANDLER( amstrad_plus_asic_6000_w )
	1404	WRITE8_MEMBER(amstrad_state::amstrad_plus_asic_6000_w)
1406	1405	{
1407		amstrad_state *state = space->machine().driver_data<amstrad_state>();
1408		state->m_asic.ram[offset+0x2000] = data;
	1406	m_asic.ram[offset+0x2000] = data;
1409	1407	if(offset >= 0x0400 && offset < 0x440 && ( offset & 0x01 ) ) // ASIC palette
1410	1408	{
1411		state->m_asic.ram[ offset + 0x2000 ] = data & 0x0f;
	1409	m_asic.ram[ offset + 0x2000 ] = data & 0x0f;
1412	1410	}
1413	1411	if(offset == 0x0800)  // Programmable raster interrupt
1414	1412	{
1415	1413	//      logerror("ASIC: Wrote %02x to PRI\n",data);
1416		state->m_asic.pri = data;
	1414	m_asic.pri = data;
1417	1415	}
1418	1416	if(offset >= 0x0801 && offset <= 0x0803)  // Split screen registers
1419	1417	{
1420		logerror("ASIC: Split screen at line %i, address &%04x\n",state->m_asic.ram[0x2801],state->m_asic.ram[0x2803] + (state->m_asic.ram[0x2802] << 8));
	1418	logerror("ASIC: Split screen at line %i, address &%04x\n",m_asic.ram[0x2801],m_asic.ram[0x2803] + (m_asic.ram[0x2802] << 8));
1421	1419	}
1422	1420	if(offset == 0x0804)  // Soft scroll register
1423	1421	{
r14963	r14964
1427	1425	// high 5 bits go to interrupt vector
1428	1426	int vector;
1429	1427
1430		if ( state->m_asic.enabled )
	1428	if ( m_asic.enabled )
1431	1429	{
1432		vector = (data & 0xf8) + (state->m_plus_irq_cause);
1433		device_set_input_line_vector(space->machine().device("maincpu"), 0, vector);
	1430	vector = (data & 0xf8) + (m_plus_irq_cause);
	1431	device_set_input_line_vector(machine().device("maincpu"), 0, vector);
1434	1432	logerror("ASIC: IM 2 vector write %02x, data = &%02x\n",vector,data);
1435	1433	}
1436		state->m_asic.dma_clear = data & 0x01;
	1434	m_asic.dma_clear = data & 0x01;
1437	1435	}
1438	1436	// DMA channels
1439	1437	switch(offset)
1440	1438	{
1441	1439	case 0x0c00:
1442	1440	case 0x0c01:
1443		state->m_asic.dma_addr[0] = (state->m_asic.ram[0x2c01] << 8) + state->m_asic.ram[0x2c00];
1444		state->m_asic.dma_status &= ~0x01;
1445		logerror("ASIC: DMA 0 address set to &%04x\n",state->m_asic.dma_addr[0]);
	1441	m_asic.dma_addr[0] = (m_asic.ram[0x2c01] << 8) + m_asic.ram[0x2c00];
	1442	m_asic.dma_status &= ~0x01;
	1443	logerror("ASIC: DMA 0 address set to &%04x\n",m_asic.dma_addr[0]);
1446	1444	break;
1447	1445	case 0x0c04:
1448	1446	case 0x0c05:
1449		state->m_asic.dma_addr[1] = (state->m_asic.ram[0x2c05] << 8) + state->m_asic.ram[0x2c04];
1450		state->m_asic.dma_status &= ~0x02;
1451		logerror("ASIC: DMA 1 address set to &%04x\n",state->m_asic.dma_addr[1]);
	1447	m_asic.dma_addr[1] = (m_asic.ram[0x2c05] << 8) + m_asic.ram[0x2c04];
	1448	m_asic.dma_status &= ~0x02;
	1449	logerror("ASIC: DMA 1 address set to &%04x\n",m_asic.dma_addr[1]);
1452	1450	break;
1453	1451	case 0x0c08:
1454	1452	case 0x0c09:
1455		state->m_asic.dma_addr[2] = (state->m_asic.ram[0x2c09] << 8) + state->m_asic.ram[0x2c08];
1456		state->m_asic.dma_status &= ~0x04;
1457		logerror("ASIC: DMA 2 address set to &%04x\n",state->m_asic.dma_addr[2]);
	1453	m_asic.dma_addr[2] = (m_asic.ram[0x2c09] << 8) + m_asic.ram[0x2c08];
	1454	m_asic.dma_status &= ~0x04;
	1455	logerror("ASIC: DMA 2 address set to &%04x\n",m_asic.dma_addr[2]);
1458	1456	break;
1459	1457	case 0x0c02:
1460		state->m_asic.dma_prescaler[0] = data + 1;
	1458	m_asic.dma_prescaler[0] = data + 1;
1461	1459	logerror("ASIC: DMA 0 pause prescaler set to %i\n",data);
1462	1460	break;
1463	1461	case 0x0c06:
1464		state->m_asic.dma_prescaler[1] = data + 1;
	1462	m_asic.dma_prescaler[1] = data + 1;
1465	1463	logerror("ASIC: DMA 1 pause prescaler set to %i\n",data);
1466	1464	break;
1467	1465	case 0x0c0a:
1468		state->m_asic.dma_prescaler[2] = data + 1;
	1466	m_asic.dma_prescaler[2] = data + 1;
1469	1467	logerror("ASIC: DMA 2 pause prescaler set to %i\n",data);
1470	1468	break;
1471	1469	case 0x0c0f:
1472		state->m_asic.dma_status = data;
	1470	m_asic.dma_status = data;
1473	1471	logerror("ASIC: DMA status write - %02x\n",data);
1474	1472	if(data & 0x40)
1475	1473	{
1476	1474	logerror("ASIC: DMA 0 IRQ acknowledge\n");
1477		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
1478		state->m_plus_irq_cause = 0x06;
1479		state->m_asic.ram[0x2c0f] &= ~0x40;
	1475	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
	1476	m_plus_irq_cause = 0x06;
	1477	m_asic.ram[0x2c0f] &= ~0x40;
1480	1478	}
1481	1479	if(data & 0x20)
1482	1480	{
1483	1481	logerror("ASIC: DMA 1 IRQ acknowledge\n");
1484		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
1485		state->m_plus_irq_cause = 0x06;
1486		state->m_asic.ram[0x2c0f] &= ~0x20;
	1482	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
	1483	m_plus_irq_cause = 0x06;
	1484	m_asic.ram[0x2c0f] &= ~0x20;
1487	1485	}
1488	1486	if(data & 0x10)
1489	1487	{
1490	1488	logerror("ASIC: DMA 2 IRQ acknowledge\n");
1491		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
1492		state->m_plus_irq_cause = 0x06;
1493		state->m_asic.ram[0x2c0f] &= ~0x10;
	1489	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
	1490	m_plus_irq_cause = 0x06;
	1491	m_asic.ram[0x2c0f] &= ~0x10;
1494	1492	}
1495		state->m_asic.ram[0x2c0f] = (state->m_asic.ram[0x2c0f] & 0xf8) | (data & 0x07);
	1493	m_asic.ram[0x2c0f] = (m_asic.ram[0x2c0f] & 0xf8) | (data & 0x07);
1496	1494	break;
1497	1495	}
1498	1496	}
1499	1497
1500	1498
1501		READ8_HANDLER( amstrad_plus_asic_4000_r )
	1499	READ8_MEMBER(amstrad_state::amstrad_plus_asic_4000_r)
1502	1500	{
1503		amstrad_state *state = space->machine().driver_data<amstrad_state>();
1504	1501	//  logerror("RAM: read from &%04x\n",offset+0x4000);
1505		return state->m_asic.ram[offset];
	1502	return m_asic.ram[offset];
1506	1503	}
1507	1504
1508	1505
1509		READ8_HANDLER( amstrad_plus_asic_6000_r )
	1506	READ8_MEMBER(amstrad_state::amstrad_plus_asic_6000_r)
1510	1507	{
1511		amstrad_state *state = space->machine().driver_data<amstrad_state>();
1512	1508	//  logerror("RAM: read from &%04x\n",offset+0x6000);
1513	1509	// Analogue ports
1514	1510	if(offset == 0x0808)
1515	1511	{
1516		return (input_port_read(space->machine(), "analog1") & 0x3f);
	1512	return (input_port_read(machine(), "analog1") & 0x3f);
1517	1513	}
1518	1514	if(offset == 0x0809)
1519	1515	{
1520		return (input_port_read(space->machine(), "analog2") & 0x3f);
	1516	return (input_port_read(machine(), "analog2") & 0x3f);
1521	1517	}
1522	1518	if(offset == 0x080a)
1523	1519	{
1524		return (input_port_read(space->machine(), "analog3") & 0x3f);
	1520	return (input_port_read(machine(), "analog3") & 0x3f);
1525	1521	}
1526	1522	if(offset == 0x080b)
1527	1523	{
1528		return (input_port_read(space->machine(), "analog4") & 0x3f);
	1524	return (input_port_read(machine(), "analog4") & 0x3f);
1529	1525	}
1530	1526	if(offset == 0x080c || offset == 0x080e)
1531	1527	{
r14963	r14964
1539	1535	if(offset == 0x0c0f)  // DMA status and control
1540	1536	{
1541	1537	int result = 0;
1542		if(state->m_plus_irq_cause == 0x00)
	1538	if(m_plus_irq_cause == 0x00)
1543	1539	result |= 0x40;
1544		if(state->m_plus_irq_cause == 0x02)
	1540	if(m_plus_irq_cause == 0x02)
1545	1541	result |= 0x20;
1546		if(state->m_plus_irq_cause == 0x04)
	1542	if(m_plus_irq_cause == 0x04)
1547	1543	result |= 0x10;
1548		if(state->m_plus_irq_cause == 0x06)
	1544	if(m_plus_irq_cause == 0x06)
1549	1545	result |= 0x80;
1550	1546	return result;
1551	1547	}
1552	1548	#endif
1553		return state->m_asic.ram[offset+0x2000];
	1549	return m_asic.ram[offset+0x2000];
1554	1550	}
1555	1551
1556	1552
r14963	r14964
1705	1701	}
1706	1702
1707	1703
1708		static WRITE8_HANDLER( aleste_msx_mapper )
	1704	WRITE8_MEMBER(amstrad_state::aleste_msx_mapper)
1709	1705	{
1710		amstrad_state *state = space->machine().driver_data<amstrad_state>();
1711	1706	int page = (offset & 0x0300) >> 8;
1712	1707	int ramptr = (data & 0x1f) * 0x4000;
1713	1708	int rampage = data & 0x1f;
1714	1709	int function = (data & 0xc0) >> 6;
1715		UINT8 *ram = space->machine().device<ram_device>(RAM_TAG)->pointer();
	1710	UINT8 *ram = machine().device<ram_device>(RAM_TAG)->pointer();
1716	1711
1717	1712	// It is assumed that functions are all mapped to each port &7cff-&7fff, and b8 and b9 are only used for RAM bank location
1718	1713	switch(function)
1719	1714	{
1720	1715	case 0:  // Pen select (same as Gate Array?)
1721		amstrad_GateArray_write(space->machine(), data);
	1716	amstrad_GateArray_write(machine(), data);
1722	1717	break;
1723	1718	case 1:  // Colour select (6-bit palette)
1724		aleste_vh_update_colour( space->machine(), state->m_gate_array.pen_selected, data & 0x3f );
	1719	aleste_vh_update_colour( machine(), m_gate_array.pen_selected, data & 0x3f );
1725	1720	break;
1726	1721	case 2:  // Screen mode, Upper/Lower ROM select
1727		amstrad_GateArray_write(space->machine(), data);
	1722	amstrad_GateArray_write(machine(), data);
1728	1723	break;
1729	1724	case 3: // RAM banks
1730	1725	switch(page)
1731	1726	{
1732	1727	case 0:  /* 0x0000 - 0x3fff */
1733		memory_set_bankptr(space->machine(),"bank1",ram+ramptr);
1734		memory_set_bankptr(space->machine(),"bank2",ram+ramptr+0x2000);
1735		memory_set_bankptr(space->machine(),"bank9",ram+ramptr);
1736		memory_set_bankptr(space->machine(),"bank10",ram+ramptr+0x2000);
1737		state->m_Aleste_RamBanks[0] = ram+ramptr;
1738		state->m_aleste_active_page[0] = data;
	1728	memory_set_bankptr(machine(),"bank1",ram+ramptr);
	1729	memory_set_bankptr(machine(),"bank2",ram+ramptr+0x2000);
	1730	memory_set_bankptr(machine(),"bank9",ram+ramptr);
	1731	memory_set_bankptr(machine(),"bank10",ram+ramptr+0x2000);
	1732	m_Aleste_RamBanks[0] = ram+ramptr;
	1733	m_aleste_active_page[0] = data;
1739	1734	logerror("RAM: RAM location 0x%06x (page %02x) mapped to 0x0000\n",ramptr,rampage);
1740	1735	break;
1741	1736	case 1:  /* 0x4000 - 0x7fff */
1742		memory_set_bankptr(space->machine(),"bank3",ram+ramptr);
1743		memory_set_bankptr(space->machine(),"bank4",ram+ramptr+0x2000);
1744		memory_set_bankptr(space->machine(),"bank11",ram+ramptr);
1745		memory_set_bankptr(space->machine(),"bank12",ram+ramptr+0x2000);
1746		state->m_Aleste_RamBanks[1] = ram+ramptr;
1747		state->m_aleste_active_page[1] = data;
	1737	memory_set_bankptr(machine(),"bank3",ram+ramptr);
	1738	memory_set_bankptr(machine(),"bank4",ram+ramptr+0x2000);
	1739	memory_set_bankptr(machine(),"bank11",ram+ramptr);
	1740	memory_set_bankptr(machine(),"bank12",ram+ramptr+0x2000);
	1741	m_Aleste_RamBanks[1] = ram+ramptr;
	1742	m_aleste_active_page[1] = data;
1748	1743	logerror("RAM: RAM location 0x%06x (page %02x) mapped to 0x4000\n",ramptr,rampage);
1749	1744	break;
1750	1745	case 2:  /* 0x8000 - 0xbfff */
1751		memory_set_bankptr(space->machine(),"bank5",ram+ramptr);
1752		memory_set_bankptr(space->machine(),"bank6",ram+ramptr+0x2000);
1753		memory_set_bankptr(space->machine(),"bank13",ram+ramptr);
1754		memory_set_bankptr(space->machine(),"bank14",ram+ramptr+0x2000);
1755		state->m_Aleste_RamBanks[2] = ram+ramptr;
1756		state->m_aleste_active_page[2] = data;
	1746	memory_set_bankptr(machine(),"bank5",ram+ramptr);
	1747	memory_set_bankptr(machine(),"bank6",ram+ramptr+0x2000);
	1748	memory_set_bankptr(machine(),"bank13",ram+ramptr);
	1749	memory_set_bankptr(machine(),"bank14",ram+ramptr+0x2000);
	1750	m_Aleste_RamBanks[2] = ram+ramptr;
	1751	m_aleste_active_page[2] = data;
1757	1752	logerror("RAM: RAM location 0x%06x (page %02x) mapped to 0x8000\n",ramptr,rampage);
1758	1753	break;
1759	1754	case 3:  /* 0xc000 - 0xffff */
1760		memory_set_bankptr(space->machine(),"bank7",ram+ramptr);
1761		memory_set_bankptr(space->machine(),"bank8",ram+ramptr+0x2000);
1762		memory_set_bankptr(space->machine(),"bank15",ram+ramptr);
1763		memory_set_bankptr(space->machine(),"bank16",ram+ramptr+0x2000);
1764		state->m_Aleste_RamBanks[3] = ram+ramptr;
1765		state->m_aleste_active_page[3] = data;
	1755	memory_set_bankptr(machine(),"bank7",ram+ramptr);
	1756	memory_set_bankptr(machine(),"bank8",ram+ramptr+0x2000);
	1757	memory_set_bankptr(machine(),"bank15",ram+ramptr);
	1758	memory_set_bankptr(machine(),"bank16",ram+ramptr+0x2000);
	1759	m_Aleste_RamBanks[3] = ram+ramptr;
	1760	m_aleste_active_page[3] = data;
1766	1761	logerror("RAM: RAM location 0x%06x (page %02x) mapped to 0xc000\n",ramptr,rampage);
1767	1762	break;
1768	1763	}
r14963	r14964
1832	1827
1833	1828	*/
1834	1829
1835		READ8_HANDLER ( amstrad_cpc_io_r )
	1830	READ8_MEMBER(amstrad_state::amstrad_cpc_io_r)
1836	1831	{
1837		amstrad_state *state = space->machine().driver_data<amstrad_state>();
1838		device_t *fdc = space->machine().device("upd765");
1839		mc6845_device *mc6845 = space->machine().device<mc6845_device>("mc6845" );
	1832	device_t *fdc = machine().device("upd765");
	1833	mc6845_device *mc6845 = machine().device<mc6845_device>("mc6845" );
1840	1834
1841	1835	unsigned char data = 0xFF;
1842	1836	unsigned int r1r0 = (unsigned int)((offset & 0x0300) >> 8);
1843	1837	//  m6845_personality_t crtc_type;
1844	1838	int page;
1845	1839
1846		//  crtc_type = input_port_read_safe(space->machine(), "crtc", 0);
	1840	//  crtc_type = input_port_read_safe(machine(), "crtc", 0);
1847	1841	//  m6845_set_personality(crtc_type);
1848	1842
1849		if(state->m_aleste_mode & 0x04)
	1843	if(m_aleste_mode & 0x04)
1850	1844	{
1851	1845	if ((offset & (1<<15)) == 0)  // Aleste Mapper is readable?
1852	1846	{
1853	1847	page = (offset & 0x0300) >> 8;
1854		data = state->m_aleste_active_page[page];
	1848	data = m_aleste_active_page[page];
1855	1849	return data;
1856	1850	}
1857	1851	}
r14963	r14964
1862	1856	switch(r1r0)
1863	1857	{
1864	1858	case 0x02:
1865		data = mc6845->status_r( *space, 0 );
	1859	data = mc6845->status_r( space, 0 );
1866	1860	#if 0
1867	1861	/* CRTC Type 1 : Read Status Register
1868	1862	CRTC Type 3 or 4 : Read from selected internal 6845 register */
r14963	r14964
1881	1875	break;
1882	1876	case 0x03:
1883	1877	/* All CRTC type : Read from selected internal 6845 register Read only */
1884		data = mc6845->register_r( *space, (offs_t)0 );
	1878	data = mc6845->register_r( space, (offs_t)0 );
1885	1879	break;
1886	1880	}
1887	1881	}
r14963	r14964
1897	1891	if ((offset & (1<<11)) == 0)
1898	1892	{
1899	1893	if (r1r0 < 0x03 )
1900		data = space->machine().device<i8255_device>("ppi8255")->read(*space, r1r0);
	1894	data = machine().device<i8255_device>("ppi8255")->read(space, r1r0);
1901	1895	}
1902	1896
1903	1897	/* if b10 = 0 : Expansion Peripherals Read selected
r14963	r14964
1918	1912	If b10 is reset but none of b7-b5 are reset, user expansion peripherals are selected.
1919	1913	The exception is the case where none of b7-b0 are reset (i.e. port &FBFF), which causes the expansion peripherals to reset.
1920	1914	*/
1921		if ( state->m_system_type != SYSTEM_GX4000 )
	1915	if ( m_system_type != SYSTEM_GX4000 )
1922	1916	{
1923	1917	if ( ( offset & (1<<10) ) == 0 )
1924	1918	{
r14963	r14964
1945	1939
1946	1940
1947	1941	// Handler for checking the ASIC unlocking sequence
1948		static void amstrad_plus_seqcheck(amstrad_state *state, int data)
	1942	void amstrad_state::amstrad_plus_seqcheck(int data)
1949	1943	{
1950		if(data == 0 && state->m_prev_data != 0)
	1944	if(data == 0 && m_prev_data != 0)
1951	1945	{
1952		state->m_asic.seqptr = 0;  // non-zero value followed by zero will sync the locking mechanism
	1946	m_asic.seqptr = 0;  // non-zero value followed by zero will sync the locking mechanism
1953	1947	}
1954		if(data == asic_unlock_seq[state->m_asic.seqptr])
	1948	if(data == asic_unlock_seq[m_asic.seqptr])
1955	1949	{
1956		state->m_asic.seqptr++;
1957		if ( state->m_asic.seqptr == 14 && state->m_asic.enabled )
	1950	m_asic.seqptr++;
	1951	if ( m_asic.seqptr == 14 && m_asic.enabled )
1958	1952	{
1959	1953	logerror("SYS: ASIC locked\n");
1960		state->m_asic.enabled = 0;
	1954	m_asic.enabled = 0;
1961	1955	}
1962		if ( state->m_asic.seqptr >= 15 )  // end of sequence
	1956	if ( m_asic.seqptr >= 15 )  // end of sequence
1963	1957	{
1964	1958	logerror("SYS: ASIC unlocked\n");
1965		state->m_asic.enabled = 1;
	1959	m_asic.enabled = 1;
1966	1960	}
1967	1961	}
1968		state->m_prev_data = data;
	1962	m_prev_data = data;
1969	1963	}
1970	1964
1971	1965
1972	1966	/* Offset handler for write */
1973		WRITE8_HANDLER ( amstrad_cpc_io_w )
	1967	WRITE8_MEMBER(amstrad_state::amstrad_cpc_io_w)
1974	1968	{
1975		amstrad_state *state = space->machine().driver_data<amstrad_state>();
1976		device_t *fdc = space->machine().device("upd765");
1977		mc6845_device *mc6845 = space->machine().device<mc6845_device>("mc6845");
	1969	device_t *fdc = machine().device("upd765");
	1970	mc6845_device *mc6845 = machine().device<mc6845_device>("mc6845");
1978	1971	cpc_multiface2_device* mface2;
1979	1972
1980	1973	if ((offset & (1<<15)) == 0)
1981	1974	{
1982		if(state->m_aleste_mode & 0x04) // Aleste mode
	1975	if(m_aleste_mode & 0x04) // Aleste mode
1983	1976	{
1984	1977	aleste_msx_mapper(space, offset, data);
1985	1978	}
r14963	r14964
1987	1980	{
1988	1981	/* if b15 = 0 and b14 = 1 : Gate-Array Write Selected*/
1989	1982	if ((offset & (1<<14)) != 0)
1990		amstrad_GateArray_write(space->machine(), data);
	1983	amstrad_GateArray_write(machine(), data);
1991	1984
1992	1985	/* if b15 = 0 : RAM Configuration Write Selected*/
1993		AmstradCPC_GA_SetRamConfiguration(space->machine());
	1986	AmstradCPC_GA_SetRamConfiguration(machine());
1994	1987	}
1995	1988	}
1996	1989
r14963	r14964
2001	1994	switch ((offset & 0x0300) >> 8) // r1r0
2002	1995	{
2003	1996	case 0x00:      /* Select internal 6845 register Write Only */
2004		mc6845->address_w( *space, 0, data );
2005		if ( state->m_system_type == SYSTEM_PLUS || state->m_system_type == SYSTEM_GX4000 )
2006		amstrad_plus_seqcheck(state, data);
	1997	mc6845->address_w( space, 0, data );
	1998	if ( m_system_type == SYSTEM_PLUS || m_system_type == SYSTEM_GX4000 )
	1999	amstrad_plus_seqcheck(data);
2007	2000
2008	2001	/* printer port d7 */
2009		if (data == 0x0c && state->m_system_type == SYSTEM_PLUS)
2010		state->m_printer_bit8_selected = TRUE;
	2002	if (data == 0x0c && m_system_type == SYSTEM_PLUS)
	2003	m_printer_bit8_selected = TRUE;
2011	2004
2012		state->m_asic.addr_6845 = data;
	2005	m_asic.addr_6845 = data;
2013	2006	break;
2014	2007	case 0x01:      /* Write to selected internal 6845 register Write Only */
2015		if ( state->m_system_type == SYSTEM_PLUS || state->m_system_type == SYSTEM_GX4000 )
2016		amstrad_plus_update_video(space->machine());
	2008	if ( m_system_type == SYSTEM_PLUS || m_system_type == SYSTEM_GX4000 )
	2009	amstrad_plus_update_video(machine());
2017	2010	else
2018		amstrad_update_video(space->machine());
2019		mc6845->register_w( *space, 0, data );
	2011	amstrad_update_video(machine());
	2012	mc6845->register_w( space, 0, data );
2020	2013
2021	2014	/* printer port bit 8 */
2022		if (state->m_printer_bit8_selected && state->m_system_type == SYSTEM_PLUS)
	2015	if (m_printer_bit8_selected && m_system_type == SYSTEM_PLUS)
2023	2016	{
2024		centronics_device *printer = space->machine().device<centronics_device>("centronics");
	2017	centronics_device *printer = machine().device<centronics_device>("centronics");
2025	2018	printer->d7_w(BIT(data, 3));
2026		state->m_printer_bit8_selected = FALSE;
	2019	m_printer_bit8_selected = FALSE;
2027	2020	}
2028	2021
2029		if ( state->m_asic.addr_6845 == 0x01 )
2030		state->m_asic.horiz_disp = data;
	2022	if ( m_asic.addr_6845 == 0x01 )
	2023	m_asic.horiz_disp = data;
2031	2024
2032	2025	break;
2033	2026	default:
r14963	r14964
2039	2032	/* b13 = 0 : ROM select Write Selected*/
2040	2033	if ((offset & (1<<13)) == 0)
2041	2034	{
2042		state->m_gate_array.upper_bank = data;
2043		amstrad_setUpperRom(space->machine());
	2035	m_gate_array.upper_bank = data;
	2036	amstrad_setUpperRom(machine());
2044	2037	}
2045	2038
2046	2039	/* b12 = 0 : Printer port Write Selected*/
2047		if(state->m_system_type != SYSTEM_GX4000)
	2040	if(m_system_type != SYSTEM_GX4000)
2048	2041	{
2049	2042	if ((offset & (1<<12)) == 0)
2050	2043	{
2051		centronics_device *printer = space->machine().device<centronics_device>("centronics");
	2044	centronics_device *printer = machine().device<centronics_device>("centronics");
2052	2045
2053	2046	/* CPC has a 7-bit data port, bit 8 is the STROBE signal */
2054		printer->write(*space, 0, data & 0x7f);
	2047	printer->write(space, 0, data & 0x7f);
2055	2048	printer->strobe_w(BIT(data, 7));
2056	2049	}
2057	2050	}
r14963	r14964
2067	2060	{
2068	2061	unsigned int Index = ((offset & 0x0300) >> 8);
2069	2062
2070		space->machine().device<i8255_device>("ppi8255")->write(*space, Index, data);
	2063	machine().device<i8255_device>("ppi8255")->write(space, Index, data);
2071	2064	}
2072	2065
2073	2066	/* if b10 = 0 : Expansion Peripherals Write selected */
r14963	r14964
2090	2083	If b10 is reset but none of b7-b5 are reset, user expansion peripherals are selected.
2091	2084	The exception is the case where none of b7-b0 are reset (i.e. port &FBFF), which causes the expansion peripherals to reset.
2092	2085	*/
2093		if(state->m_system_type != SYSTEM_GX4000)
	2086	if(m_system_type != SYSTEM_GX4000)
2094	2087	{
2095	2088	if ((offset & (1<<7)) == 0)
2096	2089	{
r14963	r14964
2102	2095	/* FDC Motor Control - Bit 0 defines the state of the FDD motor:
2103	2096	* "1" the FDD motor will be active.
2104	2097	* "0" the FDD motor will be in-active.*/
2105		floppy_mon_w(floppy_get_device(space->machine(), 0), !BIT(data, 0));
2106		floppy_mon_w(floppy_get_device(space->machine(), 1), !BIT(data, 0));
2107		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), 1,1);
2108		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), 1,1);
	2098	floppy_mon_w(floppy_get_device(machine(), 0), !BIT(data, 0));
	2099	floppy_mon_w(floppy_get_device(machine(), 1), !BIT(data, 0));
	2100	floppy_drive_set_ready_state(floppy_get_device(machine(), 0), 1,1);
	2101	floppy_drive_set_ready_state(floppy_get_device(machine(), 1), 1,1);
2109	2102	break;
2110	2103
2111	2104	case 0x03: /* Write Data register of FDC */
r14963	r14964
2128	2121	D5 - 0-AY8910 ,1-512WI1 */
2129	2122	if(offset == 0xfabf)
2130	2123	{
2131		state->m_aleste_mode = data;
	2124	m_aleste_mode = data;
2132	2125	logerror("EXTEND: Port &FABF write 0x%02x\n",data);
2133		mc6845->set_clock( ( state->m_aleste_mode & 0x02 ) ? ( XTAL_16MHz / 8 ) : ( XTAL_16MHz / 16 ) );
	2126	mc6845->set_clock( ( m_aleste_mode & 0x02 ) ? ( XTAL_16MHz / 8 ) : ( XTAL_16MHz / 16 ) );
2134	2127	}
2135	2128
2136		mface2 = dynamic_cast<cpc_multiface2_device*>(get_expansion_device(space->machine(),"multiface2"));
	2129	mface2 = dynamic_cast<cpc_multiface2_device*>(get_expansion_device(machine(),"multiface2"));
2137	2130	if(mface2 != NULL)
2138	2131	{
2139	2132	if(mface2->multiface_io_write(offset, data) != 0)
2140		amstrad_rethinkMemory(space->machine());
	2133	amstrad_rethinkMemory(machine());
2141	2134	}
2142	2135	}
2143	2136
r14963	r14964
2624	2617	*/
2625	2618
2626	2619	/* read PSG port A */
2627		READ8_HANDLER ( amstrad_psg_porta_read )
	2620	READ8_MEMBER(amstrad_state::amstrad_psg_porta_read)
2628	2621	{
2629		amstrad_state *state = space->machine().driver_data<amstrad_state>();
2630	2622	/* Read CPC Keyboard
2631	2623	If keyboard matrix line 11-14 are selected, the byte is always &ff.
2632	2624	After testing on a real CPC, it is found that these never change, they always return &FF. */
r14963	r14964
2637	2629	"keyboard_row_10"
2638	2630	};
2639	2631
2640		if ( ( state->m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F ) > 10)
	2632	if ( ( m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F ) > 10)
2641	2633	{
2642	2634	return 0xFF;
2643	2635	}
2644	2636	else
2645	2637	{
2646		if(state->m_aleste_mode == 0x08 && ( state->m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F ) == 10)
	2638	if(m_aleste_mode == 0x08 && ( m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F ) == 10)
2647	2639	return 0xff;
2648	2640
2649		return input_port_read_safe(space->machine(), keynames[state->m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F], 0) & 0xFF;
	2641	return input_port_read_safe(machine(), keynames[m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F], 0) & 0xFF;
2650	2642	}
2651	2643	}
2652	2644

src/mess/machine/sms.c

r14963	r14964
233	233	}
234	234
235	235
236		static WRITE8_HANDLER( sms_input_write )
	236	WRITE8_MEMBER(sms_state::sms_input_write)
237	237	{
238		sms_state *state = space->machine().driver_data<sms_state>();
239	238
240	239	switch (offset)
241	240	{
242	241	case 0:
243		switch (input_port_read_safe(space->machine(), "CTRLSEL", 0x00) & 0x0f)
	242	switch (input_port_read_safe(machine(), "CTRLSEL", 0x00) & 0x0f)
244	243	{
245	244	case 0x04:   /* Sports Pad */
246		if (data != state->m_sports_pad_last_data_1)
	245	if (data != m_sports_pad_last_data_1)
247	246	{
248		UINT32 cpu_cycles = downcast<cpu_device *>(&space->device())->total_cycles();
	247	UINT32 cpu_cycles = downcast<cpu_device *>(&space.device())->total_cycles();
249	248
250		state->m_sports_pad_last_data_1 = data;
251		if (cpu_cycles - state->m_last_sports_pad_time_1 > 512)
	249	m_sports_pad_last_data_1 = data;
	250	if (cpu_cycles - m_last_sports_pad_time_1 > 512)
252	251	{
253		state->m_sports_pad_state_1 = 3;
254		state->m_sports_pad_1_x = input_port_read(space->machine(), "SPORT0");
255		state->m_sports_pad_1_y = input_port_read(space->machine(), "SPORT1");
	252	m_sports_pad_state_1 = 3;
	253	m_sports_pad_1_x = input_port_read(machine(), "SPORT0");
	254	m_sports_pad_1_y = input_port_read(machine(), "SPORT1");
256	255	}
257		state->m_last_sports_pad_time_1 = cpu_cycles;
258		state->m_sports_pad_state_1 = (state->m_sports_pad_state_1 + 1) & 3;
	256	m_last_sports_pad_time_1 = cpu_cycles;
	257	m_sports_pad_state_1 = (m_sports_pad_state_1 + 1) & 3;
259	258	}
260	259	break;
261	260	}
262	261	break;
263	262
264	263	case 1:
265		switch (input_port_read_safe(space->machine(), "CTRLSEL", 0x00) & 0xf0)
	264	switch (input_port_read_safe(machine(), "CTRLSEL", 0x00) & 0xf0)
266	265	{
267	266	case 0x40:   /* Sports Pad */
268		if (data != state->m_sports_pad_last_data_2)
	267	if (data != m_sports_pad_last_data_2)
269	268	{
270		UINT32 cpu_cycles = downcast<cpu_device *>(&space->device())->total_cycles();
	269	UINT32 cpu_cycles = downcast<cpu_device *>(&space.device())->total_cycles();
271	270
272		state->m_sports_pad_last_data_2 = data;
273		if (cpu_cycles - state->m_last_sports_pad_time_2 > 2048)
	271	m_sports_pad_last_data_2 = data;
	272	if (cpu_cycles - m_last_sports_pad_time_2 > 2048)
274	273	{
275		state->m_sports_pad_state_2 = 3;
276		state->m_sports_pad_2_x = input_port_read(space->machine(), "SPORT2");
277		state->m_sports_pad_2_y = input_port_read(space->machine(), "SPORT3");
	274	m_sports_pad_state_2 = 3;
	275	m_sports_pad_2_x = input_port_read(machine(), "SPORT2");
	276	m_sports_pad_2_y = input_port_read(machine(), "SPORT3");
278	277	}
279		state->m_last_sports_pad_time_2 = cpu_cycles;
280		state->m_sports_pad_state_2 = (state->m_sports_pad_state_2 + 1) & 3;
	278	m_last_sports_pad_time_2 = cpu_cycles;
	279	m_sports_pad_state_2 = (m_sports_pad_state_2 + 1) & 3;
281	280	}
282	281	break;
283	282	}
r14963	r14964
700	699	}
701	700
702	701
703		WRITE8_HANDLER( sms_fm_detect_w )
	702	WRITE8_MEMBER(sms_state::sms_fm_detect_w)
704	703	{
705		sms_state *state = space->machine().driver_data<sms_state>();
706	704
707		if (state->m_has_fm)
708		state->m_fm_detect = (data & 0x01);
	705	if (m_has_fm)
	706	m_fm_detect = (data & 0x01);
709	707	}
710	708
711	709
712		READ8_HANDLER( sms_fm_detect_r )
	710	READ8_MEMBER(sms_state::sms_fm_detect_r)
713	711	{
714		sms_state *state = space->machine().driver_data<sms_state>();
715	712
716		if (state->m_has_fm)
	713	if (m_has_fm)
717	714	{
718		return state->m_fm_detect;
	715	return m_fm_detect;
719	716	}
720	717	else
721	718	{
722		if (state->m_bios_port & IO_CHIP)
	719	if (m_bios_port & IO_CHIP)
723	720	{
724	721	return 0xff;
725	722	}
726	723	else
727	724	{
728		sms_get_inputs(space);
729		return state->m_input_port0;
	725	sms_get_inputs(&space);
	726	return m_input_port0;
730	727	}
731	728	}
732	729	}
733	730
734		WRITE8_HANDLER( sms_io_control_w )
	731	WRITE8_MEMBER(sms_state::sms_io_control_w)
735	732	{
736		sms_state *state = space->machine().driver_data<sms_state>();
737	733	bool hcount_latch = false;
738	734
739	735	if (data & 0x08)
740	736	{
741	737	/* check if TH pin level is high (1) and was low last time */
742		if (data & 0x80 && !(state->m_ctrl_reg & 0x80))
	738	if (data & 0x80 && !(m_ctrl_reg & 0x80))
743	739	{
744	740	hcount_latch = true;
745	741	}
r14963	r14964
748	744
749	745	if (data & 0x02)
750	746	{
751		if (data & 0x20 && !(state->m_ctrl_reg & 0x20))
	747	if (data & 0x20 && !(m_ctrl_reg & 0x20))
752	748	{
753	749	hcount_latch = true;
754	750	}
r14963	r14964
757	753
758	754	if (hcount_latch)
759	755	{
760		sms_vdp_hcount_latch(space);
	756	sms_vdp_hcount_latch(&space);
761	757	}
762	758
763		state->m_ctrl_reg = data;
	759	m_ctrl_reg = data;
764	760	}
765	761
766	762
767		READ8_HANDLER( sms_count_r )
	763	READ8_MEMBER(sms_state::sms_count_r)
768	764	{
769		sms_state *state = space->machine().driver_data<sms_state>();
770	765
771	766	if (offset & 0x01)
772		return state->m_vdp->hcount_latch_read(*state->m_space, offset);
	767	return m_vdp->hcount_latch_read(*m_space, offset);
773	768	else
774		return state->m_vdp->vcount_read(*state->m_space, offset);
	769	return m_vdp->vcount_read(*m_space, offset);
775	770	}
776	771
777	772
r14963	r14964
804	799	driver_state->m_lphaser_2_latch = 0;
805	800	}
806	801
807		READ8_HANDLER( sms_input_port_0_r )
	802	READ8_MEMBER(sms_state::sms_input_port_0_r)
808	803	{
809		sms_state *state = space->machine().driver_data<sms_state>();
810	804
811		if (state->m_bios_port & IO_CHIP)
	805	if (m_bios_port & IO_CHIP)
812	806	{
813	807	return 0xff;
814	808	}
815	809	else
816	810	{
817		sms_get_inputs(space);
818		return state->m_input_port0;
	811	sms_get_inputs(&space);
	812	return m_input_port0;
819	813	}
820	814	}
821	815
822	816
823		READ8_HANDLER( sms_input_port_1_r )
	817	READ8_MEMBER(sms_state::sms_input_port_1_r)
824	818	{
825		sms_state *state = space->machine().driver_data<sms_state>();
826	819
827		if (state->m_bios_port & IO_CHIP)
	820	if (m_bios_port & IO_CHIP)
828	821	return 0xff;
829	822
830		sms_get_inputs(space);
	823	sms_get_inputs(&space);
831	824
832	825	/* Reset Button */
833		state->m_input_port1 = (state->m_input_port1 & 0xef) | (input_port_read_safe(space->machine(), "RESET", 0x01) & 0x01) << 4;
	826	m_input_port1 = (m_input_port1 & 0xef) | (input_port_read_safe(machine(), "RESET", 0x01) & 0x01) << 4;
834	827
835	828	/* Do region detection if TH of ports A and B are set to output (0) */
836		if (!(state->m_ctrl_reg & 0x0a))
	829	if (!(m_ctrl_reg & 0x0a))
837	830	{
838	831	/* Move bits 7,5 of IO control port into bits 7, 6 */
839		state->m_input_port1 = (state->m_input_port1 & 0x3f) | (state->m_ctrl_reg & 0x80) | (state->m_ctrl_reg & 0x20) << 1;
	832	m_input_port1 = (m_input_port1 & 0x3f) | (m_ctrl_reg & 0x80) | (m_ctrl_reg & 0x20) << 1;
840	833
841	834	/* Inverse region detect value for Japanese machines */
842		if (state->m_is_region_japan)
843		state->m_input_port1 ^= 0xc0;
	835	if (m_is_region_japan)
	836	m_input_port1 ^= 0xc0;
844	837	}
845	838	else
846	839	{
847		if (state->m_ctrl_reg & 0x02 && state->m_lphaser_1_latch)
	840	if (m_ctrl_reg & 0x02 && m_lphaser_1_latch)
848	841	{
849		state->m_input_port1 &= ~0x40;
850		state->m_lphaser_1_latch = 0;
	842	m_input_port1 &= ~0x40;
	843	m_lphaser_1_latch = 0;
851	844	}
852	845
853		if (state->m_ctrl_reg & 0x08 && state->m_lphaser_2_latch)
	846	if (m_ctrl_reg & 0x08 && m_lphaser_2_latch)
854	847	{
855		state->m_input_port1 &= ~0x80;
856		state->m_lphaser_2_latch = 0;
	848	m_input_port1 &= ~0x80;
	849	m_lphaser_2_latch = 0;
857	850	}
858	851	}
859	852
860		return state->m_input_port1;
	853	return m_input_port1;
861	854	}
862	855
863	856
864	857
865		WRITE8_HANDLER( sms_ym2413_register_port_0_w )
	858	WRITE8_MEMBER(sms_state::sms_ym2413_register_port_0_w)
866	859	{
867		sms_state *state = space->machine().driver_data<sms_state>();
868	860
869		if (state->m_has_fm)
870		ym2413_w(state->m_ym, 0, (data & 0x3f));
	861	if (m_has_fm)
	862	ym2413_w(m_ym, 0, (data & 0x3f));
871	863	}
872	864
873	865
874		WRITE8_HANDLER( sms_ym2413_data_port_0_w )
	866	WRITE8_MEMBER(sms_state::sms_ym2413_data_port_0_w)
875	867	{
876		sms_state *state = space->machine().driver_data<sms_state>();
877	868
878		if (state->m_has_fm)
	869	if (m_has_fm)
879	870	{
880	871	logerror("data_port_0_w %x %x\n", offset, data);
881		ym2413_w(state->m_ym, 1, data);
	872	ym2413_w(m_ym, 1, data);
882	873	}
883	874	}
884	875
885	876
886		READ8_HANDLER( gg_input_port_2_r )
	877	READ8_MEMBER(sms_state::gg_input_port_2_r)
887	878	{
888		sms_state *state = space->machine().driver_data<sms_state>();
889	879
890		//logerror("joy 2 read, val: %02x, pc: %04x\n", ((state->m_is_region_japan ? 0x00 : 0x40) | (input_port_read(machine, "START") & 0x80)), activecpu_get_pc());
891		return ((state->m_is_region_japan ? 0x00 : 0x40) | (input_port_read(space->machine(), "START") & 0x80));
	880	//logerror("joy 2 read, val: %02x, pc: %04x\n", ((m_is_region_japan ? 0x00 : 0x40) | (input_port_read(machine, "START") & 0x80)), activecpu_get_pc());
	881	return ((m_is_region_japan ? 0x00 : 0x40) | (input_port_read(machine(), "START") & 0x80));
892	882	}
893	883
894	884
895		READ8_HANDLER( sms_sscope_r )
	885	READ8_MEMBER(sms_state::sms_sscope_r)
896	886	{
897		sms_state *state = space->machine().driver_data<sms_state>();
898		return state->m_sscope_state;
	887	return m_sscope_state;
899	888	}
900	889
901	890
902		WRITE8_HANDLER( sms_sscope_w )
	891	WRITE8_MEMBER(sms_state::sms_sscope_w)
903	892	{
904		sms_state *state = space->machine().driver_data<sms_state>();
905		state->m_sscope_state = data;
	893	m_sscope_state = data;
906	894	}
907	895
908	896
909		READ8_HANDLER( sms_mapper_r )
	897	READ8_MEMBER(sms_state::sms_mapper_r)
910	898	{
911		sms_state *state = space->machine().driver_data<sms_state>();
912		return state->m_mapper[offset];
	899	return m_mapper[offset];
913	900	}
914	901
915	902	/* Terebi Oekaki */
916	903	/* The following code comes from sg1000.c. We should eventually merge these TV Draw implementations */
917		static WRITE8_HANDLER( sms_tvdraw_axis_w )
	904	WRITE8_MEMBER(sms_state::sms_tvdraw_axis_w)
918	905	{
919		sms_state *state = space->machine().driver_data<sms_state>();
920		UINT8 tvboard_on = input_port_read_safe(space->machine(), "TVDRAW", 0x00);
	906	UINT8 tvboard_on = input_port_read_safe(machine(), "TVDRAW", 0x00);
921	907
922	908	if (data & 0x01)
923	909	{
924		state->m_cartridge[state->m_current_cartridge].m_tvdraw_data = tvboard_on ? input_port_read(space->machine(), "TVDRAW_X") : 0x80;
	910	m_cartridge[m_current_cartridge].m_tvdraw_data = tvboard_on ? input_port_read(machine(), "TVDRAW_X") : 0x80;
925	911
926		if (state->m_cartridge[state->m_current_cartridge].m_tvdraw_data < 4) state->m_cartridge[state->m_current_cartridge].m_tvdraw_data = 4;
927		if (state->m_cartridge[state->m_current_cartridge].m_tvdraw_data > 251) state->m_cartridge[state->m_current_cartridge].m_tvdraw_data = 251;
	912	if (m_cartridge[m_current_cartridge].m_tvdraw_data < 4) m_cartridge[m_current_cartridge].m_tvdraw_data = 4;
	913	if (m_cartridge[m_current_cartridge].m_tvdraw_data > 251) m_cartridge[m_current_cartridge].m_tvdraw_data = 251;
928	914	}
929	915	else
930	916	{
931		state->m_cartridge[state->m_current_cartridge].m_tvdraw_data = tvboard_on ? input_port_read(space->machine(), "TVDRAW_Y") + 0x20 : 0x80;
	917	m_cartridge[m_current_cartridge].m_tvdraw_data = tvboard_on ? input_port_read(machine(), "TVDRAW_Y") + 0x20 : 0x80;
932	918	}
933	919	}
934	920
935		static READ8_HANDLER( sms_tvdraw_status_r )
	921	READ8_MEMBER(sms_state::sms_tvdraw_status_r)
936	922	{
937		UINT8 tvboard_on = input_port_read_safe(space->machine(), "TVDRAW", 0x00);
938		return tvboard_on ? input_port_read(space->machine(), "TVDRAW_PEN") : 0x01;
	923	UINT8 tvboard_on = input_port_read_safe(machine(), "TVDRAW", 0x00);
	924	return tvboard_on ? input_port_read(machine(), "TVDRAW_PEN") : 0x01;
939	925	}
940	926
941		static READ8_HANDLER( sms_tvdraw_data_r )
	927	READ8_MEMBER(sms_state::sms_tvdraw_data_r)
942	928	{
943		sms_state *state = space->machine().driver_data<sms_state>();
944		return state->m_cartridge[state->m_current_cartridge].m_tvdraw_data;
	929	return m_cartridge[m_current_cartridge].m_tvdraw_data;
945	930	}
946	931
947	932
948		static WRITE8_HANDLER( sms_93c46_w )
	933	WRITE8_MEMBER(sms_state::sms_93c46_w)
949	934	{
950		sms_state *state = space->machine().driver_data<sms_state>();
951	935
952		if ( state->m_cartridge[state->m_current_cartridge].m_93c46_enabled )
	936	if ( m_cartridge[m_current_cartridge].m_93c46_enabled )
953	937	{
954		state->m_cartridge[state->m_current_cartridge].m_93c46_lines = data;
	938	m_cartridge[m_current_cartridge].m_93c46_lines = data;
955	939
956	940	logerror( "sms_93c46_w: setting eeprom lines: DI=%s CLK=%s CS=%s\n", data & 0x01 ? "1" : "0", data & 0x02 ? "1" : "0", data & 0x04 ? "1" : "0" );
957		state->m_eeprom->write_bit( ( data & 0x01 ) ? ASSERT_LINE : CLEAR_LINE );
958		state->m_eeprom->set_cs_line( !( data & 0x04 ) ? ASSERT_LINE : CLEAR_LINE );
959		state->m_eeprom->set_clock_line( ( data & 0x02 ) ? ASSERT_LINE : CLEAR_LINE );
	941	m_eeprom->write_bit( ( data & 0x01 ) ? ASSERT_LINE : CLEAR_LINE );
	942	m_eeprom->set_cs_line( !( data & 0x04 ) ? ASSERT_LINE : CLEAR_LINE );
	943	m_eeprom->set_clock_line( ( data & 0x02 ) ? ASSERT_LINE : CLEAR_LINE );
960	944	}
961	945	}
962	946
963	947
964		static READ8_HANDLER( sms_93c46_r )
	948	READ8_MEMBER(sms_state::sms_93c46_r)
965	949	{
966		sms_state *state = space->machine().driver_data<sms_state>();
967		UINT8 data = state->m_banking_cart[5][0];
	950	UINT8 data = m_banking_cart[5][0];
968	951
969		if ( state->m_cartridge[state->m_current_cartridge].m_93c46_enabled )
	952	if ( m_cartridge[m_current_cartridge].m_93c46_enabled )
970	953	{
971		data = ( state->m_cartridge[state->m_current_cartridge].m_93c46_lines & 0xFC ) | 0x02;
972		data |= state->m_eeprom->read_bit() ? 1 : 0;
	954	data = ( m_cartridge[m_current_cartridge].m_93c46_lines & 0xFC ) | 0x02;
	955	data |= m_eeprom->read_bit() ? 1 : 0;
973	956	}
974	957
975	958	return data;
976	959	}
977	960
978	961
979		WRITE8_HANDLER( sms_mapper_w )
	962	WRITE8_MEMBER(sms_state::sms_mapper_w)
980	963	{
981		sms_state *state = space->machine().driver_data<sms_state>();
982	964	bool bios_selected = false;
983	965	bool cartridge_selected = false;
984	966
985	967	offset &= 3;
986	968
987		state->m_mapper[offset] = data;
988		state->m_mapper_ram[offset] = data;
	969	m_mapper[offset] = data;
	970	m_mapper_ram[offset] = data;
989	971
990		if (state->m_bios_port & IO_BIOS_ROM || (state->m_is_gamegear && state->m_BIOS == NULL))
	972	if (m_bios_port & IO_BIOS_ROM || (m_is_gamegear && m_BIOS == NULL))
991	973	{
992		if (!(state->m_bios_port & IO_CARTRIDGE) || (state->m_is_gamegear && state->m_BIOS == NULL))
	974	if (!(m_bios_port & IO_CARTRIDGE) || (m_is_gamegear && m_BIOS == NULL))
993	975	{
994		if (!state->m_cartridge[state->m_current_cartridge].ROM)
	976	if (!m_cartridge[m_current_cartridge].ROM)
995	977	return;
996	978	cartridge_selected = true;
997	979	}
r14963	r14964
1003	985	}
1004	986	else
1005	987	{
1006		if (!state->m_BIOS)
	988	if (!m_BIOS)
1007	989	return;
1008	990	bios_selected = true;
1009	991	}
r14963	r14964
1014	996	/* Is it ram or rom? */
1015	997	if (data & 0x08) /* it's ram */
1016	998	{
1017		if ( state->m_cartridge[state->m_current_cartridge].features & CF_93C46_EEPROM )
	999	if ( m_cartridge[m_current_cartridge].features & CF_93C46_EEPROM )
1018	1000	{
1019	1001	if ( data & 0x80 )
1020	1002	{
1021		state->m_eeprom->reset();
	1003	m_eeprom->reset();
1022	1004	logerror("sms_mapper_w: eeprom CS=1\n");
1023		state->m_eeprom->set_cs_line( ASSERT_LINE );
	1005	m_eeprom->set_cs_line( ASSERT_LINE );
1024	1006	}
1025	1007	logerror("sms_mapper_w: eeprom enabled\n");
1026		state->m_cartridge[state->m_current_cartridge].m_93c46_enabled = true;
	1008	m_cartridge[m_current_cartridge].m_93c46_enabled = true;
1027	1009	}
1028	1010	else
1029	1011	{
1030	1012	UINT8 *sram = NULL;
1031		state->m_cartridge[state->m_current_cartridge].sram_save = 1;         /* SRAM should be saved on exit. */
	1013	m_cartridge[m_current_cartridge].sram_save = 1;         /* SRAM should be saved on exit. */
1032	1014	if (data & 0x04)
1033	1015	{
1034		sram = state->m_cartridge[state->m_current_cartridge].cartSRAM + 0x4000;
	1016	sram = m_cartridge[m_current_cartridge].cartSRAM + 0x4000;
1035	1017	}
1036	1018	else
1037	1019	{
1038		sram = state->m_cartridge[state->m_current_cartridge].cartSRAM;
	1020	sram = m_cartridge[m_current_cartridge].cartSRAM;
1039	1021	}
1040		memory_set_bankptr(space->machine(),  "bank5", sram);
1041		memory_set_bankptr(space->machine(),  "bank6", sram + 0x2000);
	1022	memory_set_bankptr(machine(),  "bank5", sram);
	1023	memory_set_bankptr(machine(),  "bank6", sram + 0x2000);
1042	1024	}
1043	1025	}
1044	1026	else /* it's rom */
1045	1027	{
1046		if (state->m_bios_port & IO_BIOS_ROM || ! state->m_has_bios)
	1028	if (m_bios_port & IO_BIOS_ROM || ! m_has_bios)
1047	1029	{
1048		if ( ! ( state->m_cartridge[state->m_current_cartridge].features & ( CF_KOREAN_NOBANK_MAPPER | CF_KOREAN_ZEMINA_MAPPER ) ) )
	1030	if ( ! ( m_cartridge[m_current_cartridge].features & ( CF_KOREAN_NOBANK_MAPPER | CF_KOREAN_ZEMINA_MAPPER ) ) )
1049	1031	{
1050		if ( state->m_cartridge[state->m_current_cartridge].features & CF_93C46_EEPROM )
	1032	if ( m_cartridge[m_current_cartridge].features & CF_93C46_EEPROM )
1051	1033	{
1052	1034	if ( data & 0x80 )
1053	1035	{
1054		state->m_eeprom->reset();
	1036	m_eeprom->reset();
1055	1037	logerror("sms_mapper_w: eeprom CS=1\n");
1056		state->m_eeprom->set_cs_line( ASSERT_LINE );
	1038	m_eeprom->set_cs_line( ASSERT_LINE );
1057	1039	}
1058	1040	logerror("sms_mapper_w: eeprom disabled\n");
1059		state->m_cartridge[state->m_current_cartridge].m_93c46_enabled = false;
	1041	m_cartridge[m_current_cartridge].m_93c46_enabled = false;
1060	1042	}
1061	1043	else
1062	1044	{
1063		state->map_cart_16k( 0x8000, state->m_mapper[3] );
	1045	map_cart_16k( 0x8000, m_mapper[3] );
1064	1046	}
1065	1047	}
1066	1048	}
1067	1049	else
1068	1050	{
1069		state->map_bios_16k( 0x8000, state->m_mapper[3] );
	1051	map_bios_16k( 0x8000, m_mapper[3] );
1070	1052	}
1071	1053	}
1072	1054	break;
1073	1055
1074	1056	case 1: /* Select 16k ROM bank for 0400-3FFF */
1075		if ( cartridge_selected || state->m_is_gamegear )
	1057	if ( cartridge_selected || m_is_gamegear )
1076	1058	{
1077		if ( ! ( state->m_cartridge[state->m_current_cartridge].features & ( CF_KOREAN_NOBANK_MAPPER | CF_KOREAN_ZEMINA_MAPPER ) ) )
	1059	if ( ! ( m_cartridge[m_current_cartridge].features & ( CF_KOREAN_NOBANK_MAPPER | CF_KOREAN_ZEMINA_MAPPER ) ) )
1078	1060	{
1079		state->map_cart_16k( 0x400, data );
	1061	map_cart_16k( 0x400, data );
1080	1062	}
1081	1063	}
1082	1064	if ( bios_selected )
1083	1065	{
1084		state->map_bios_16k( 0x400, data );
	1066	map_bios_16k( 0x400, data );
1085	1067	}
1086	1068	break;
1087	1069
1088	1070	case 2: /* Select 16k ROM bank for 4000-7FFF */
1089		if ( cartridge_selected || state->m_is_gamegear )
	1071	if ( cartridge_selected || m_is_gamegear )
1090	1072	{
1091		if ( ! ( state->m_cartridge[state->m_current_cartridge].features & ( CF_KOREAN_NOBANK_MAPPER | CF_KOREAN_ZEMINA_MAPPER ) ) )
	1073	if ( ! ( m_cartridge[m_current_cartridge].features & ( CF_KOREAN_NOBANK_MAPPER | CF_KOREAN_ZEMINA_MAPPER ) ) )
1092	1074	{
1093		state->map_cart_16k( 0x4000, data );
	1075	map_cart_16k( 0x4000, data );
1094	1076	}
1095	1077	}
1096	1078	if ( bios_selected )
1097	1079	{
1098		state->map_bios_16k( 0x4000, data );
	1080	map_bios_16k( 0x4000, data );
1099	1081	}
1100	1082	break;
1101	1083
1102	1084	case 3: /* Select 16k ROM bank for 8000-BFFF */
1103		if ( cartridge_selected || state->m_is_gamegear )
	1085	if ( cartridge_selected || m_is_gamegear )
1104	1086	{
1105		if ( state->m_cartridge[state->m_current_cartridge].features & CF_CODEMASTERS_MAPPER)
	1087	if ( m_cartridge[m_current_cartridge].features & CF_CODEMASTERS_MAPPER)
1106	1088	{
1107	1089	return;
1108	1090	}
1109	1091
1110		if ( ! ( state->m_mapper[0] & 0x08 ) )      // Is RAM disabled
	1092	if ( ! ( m_mapper[0] & 0x08 ) )      // Is RAM disabled
1111	1093	{
1112		if ( ! ( state->m_cartridge[state->m_current_cartridge].features & ( CF_KOREAN_NOBANK_MAPPER | CF_KOREAN_ZEMINA_MAPPER ) ) )
	1094	if ( ! ( m_cartridge[m_current_cartridge].features & ( CF_KOREAN_NOBANK_MAPPER | CF_KOREAN_ZEMINA_MAPPER ) ) )
1113	1095	{
1114		state->map_cart_16k( 0x8000, data );
	1096	map_cart_16k( 0x8000, data );
1115	1097	}
1116	1098	}
1117	1099	}
1118	1100
1119	1101	if ( bios_selected )
1120	1102	{
1121		if ( ! ( state->m_mapper[0] & 0x08 ) )      // Is RAM disabled
	1103	if ( ! ( m_mapper[0] & 0x08 ) )      // Is RAM disabled
1122	1104	{
1123		state->map_bios_16k( 0x8000, data );
	1105	map_bios_16k( 0x8000, data );
1124	1106	}
1125	1107	}
1126	1108	break;
1127	1109	}
1128	1110	}
1129	1111
1130		static WRITE8_HANDLER( sms_korean_zemina_banksw_w )
	1112	WRITE8_MEMBER(sms_state::sms_korean_zemina_banksw_w)
1131	1113	{
1132		sms_state *state = space->machine().driver_data<sms_state>();
1133	1114
1134		if (state->m_cartridge[state->m_current_cartridge].features & CF_KOREAN_ZEMINA_MAPPER)
	1115	if (m_cartridge[m_current_cartridge].features & CF_KOREAN_ZEMINA_MAPPER)
1135	1116	{
1136		if (!state->m_cartridge[state->m_current_cartridge].ROM)
	1117	if (!m_cartridge[m_current_cartridge].ROM)
1137	1118	return;
1138	1119
1139	1120	switch (offset & 3)
1140	1121	{
1141	1122	case 0:
1142		state->map_cart_8k( 0x8000, data );
	1123	map_cart_8k( 0x8000, data );
1143	1124	break;
1144	1125	case 1:
1145		state->map_cart_8k( 0xA000, data );
	1126	map_cart_8k( 0xA000, data );
1146	1127	break;
1147	1128	case 2:
1148		state->map_cart_8k( 0x4000, data );
	1129	map_cart_8k( 0x4000, data );
1149	1130	break;
1150	1131	case 3:
1151		state->map_cart_8k( 0x6000, data );
	1132	map_cart_8k( 0x6000, data );
1152	1133	break;
1153	1134	}
1154	1135	LOG(("Zemina mapper write: offset %x data %x.\n", offset, data));
1155	1136	}
1156	1137	}
1157	1138
1158		static WRITE8_HANDLER( sms_codemasters_page0_w )
	1139	WRITE8_MEMBER(sms_state::sms_codemasters_page0_w)
1159	1140	{
1160		sms_state *state = space->machine().driver_data<sms_state>();
1161	1141
1162		if (state->m_cartridge[state->m_current_cartridge].ROM && state->m_cartridge[state->m_current_cartridge].features & CF_CODEMASTERS_MAPPER)
	1142	if (m_cartridge[m_current_cartridge].ROM && m_cartridge[m_current_cartridge].features & CF_CODEMASTERS_MAPPER)
1163	1143	{
1164		state->map_cart_16k( 0x0000, data );
	1144	map_cart_16k( 0x0000, data );
1165	1145	}
1166	1146	}
1167	1147
1168	1148
1169		static WRITE8_HANDLER( sms_codemasters_page1_w )
	1149	WRITE8_MEMBER(sms_state::sms_codemasters_page1_w)
1170	1150	{
1171		sms_state *state = space->machine().driver_data<sms_state>();
1172	1151
1173		if (state->m_cartridge[state->m_current_cartridge].ROM && state->m_cartridge[state->m_current_cartridge].features & CF_CODEMASTERS_MAPPER)
	1152	if (m_cartridge[m_current_cartridge].ROM && m_cartridge[m_current_cartridge].features & CF_CODEMASTERS_MAPPER)
1174	1153	{
1175	1154	/* Check if we need to switch in some RAM */
1176	1155	if (data & 0x80)
1177	1156	{
1178		state->m_cartridge[state->m_current_cartridge].ram_page = data & 0x07;
1179		memory_set_bankptr(space->machine(), "bank6", state->m_cartridge[state->m_current_cartridge].cartRAM + state->m_cartridge[state->m_current_cartridge].ram_page * 0x2000);
	1157	m_cartridge[m_current_cartridge].ram_page = data & 0x07;
	1158	memory_set_bankptr(machine(), "bank6", m_cartridge[m_current_cartridge].cartRAM + m_cartridge[m_current_cartridge].ram_page * 0x2000);
1180	1159	}
1181	1160	else
1182	1161	{
1183		state->map_cart_16k( 0x4000, data );
1184		memory_set_bankptr(space->machine(), "bank6", state->m_banking_cart[5] + 0x2000);
	1162	map_cart_16k( 0x4000, data );
	1163	memory_set_bankptr(machine(), "bank6", m_banking_cart[5] + 0x2000);
1185	1164	}
1186	1165	}
1187	1166	}
1188	1167
1189	1168
1190		WRITE8_HANDLER( sms_4pak_page0_w )
	1169	WRITE8_MEMBER(sms_state::sms_4pak_page0_w)
1191	1170	{
1192		sms_state *state = space->machine().driver_data<sms_state>();
1193	1171
1194		state->m_cartridge[state->m_current_cartridge].m_4pak_page0 = data;
	1172	m_cartridge[m_current_cartridge].m_4pak_page0 = data;
1195	1173
1196		state->map_cart_16k( 0x0000, data );
1197		state->map_cart_16k( 0x8000, ( state->m_cartridge[state->m_current_cartridge].m_4pak_page0 & 0x30 ) + state->m_cartridge[state->m_current_cartridge].m_4pak_page2 );
	1174	map_cart_16k( 0x0000, data );
	1175	map_cart_16k( 0x8000, ( m_cartridge[m_current_cartridge].m_4pak_page0 & 0x30 ) + m_cartridge[m_current_cartridge].m_4pak_page2 );
1198	1176	}
1199	1177
1200	1178
1201		WRITE8_HANDLER( sms_4pak_page1_w )
	1179	WRITE8_MEMBER(sms_state::sms_4pak_page1_w)
1202	1180	{
1203		sms_state *state = space->machine().driver_data<sms_state>();
1204	1181
1205		state->m_cartridge[state->m_current_cartridge].m_4pak_page1 = data;
	1182	m_cartridge[m_current_cartridge].m_4pak_page1 = data;
1206	1183
1207		state->map_cart_16k( 0x4000, data );
	1184	map_cart_16k( 0x4000, data );
1208	1185	}
1209	1186
1210	1187
1211		WRITE8_HANDLER( sms_4pak_page2_w )
	1188	WRITE8_MEMBER(sms_state::sms_4pak_page2_w)
1212	1189	{
1213		sms_state *state = space->machine().driver_data<sms_state>();
1214	1190
1215		state->m_cartridge[state->m_current_cartridge].m_4pak_page2 = data;
	1191	m_cartridge[m_current_cartridge].m_4pak_page2 = data;
1216	1192
1217		state->map_cart_16k( 0x8000, ( state->m_cartridge[state->m_current_cartridge].m_4pak_page0 & 0x30 ) + state->m_cartridge[state->m_current_cartridge].m_4pak_page2 );
	1193	map_cart_16k( 0x8000, ( m_cartridge[m_current_cartridge].m_4pak_page0 & 0x30 ) + m_cartridge[m_current_cartridge].m_4pak_page2 );
1218	1194	}
1219	1195
1220	1196
1221		WRITE8_HANDLER( sms_janggun_bank0_w )
	1197	WRITE8_MEMBER(sms_state::sms_janggun_bank0_w)
1222	1198	{
1223		sms_state *state = space->machine().driver_data<sms_state>();
1224	1199
1225		state->map_cart_8k( 0x4000, data );
	1200	map_cart_8k( 0x4000, data );
1226	1201	}
1227	1202
1228	1203
1229		WRITE8_HANDLER( sms_janggun_bank1_w )
	1204	WRITE8_MEMBER(sms_state::sms_janggun_bank1_w)
1230	1205	{
1231		sms_state *state = space->machine().driver_data<sms_state>();
1232	1206
1233		state->map_cart_8k( 0x6000, data );
	1207	map_cart_8k( 0x6000, data );
1234	1208	}
1235	1209
1236	1210
1237		WRITE8_HANDLER( sms_janggun_bank2_w )
	1211	WRITE8_MEMBER(sms_state::sms_janggun_bank2_w)
1238	1212	{
1239		sms_state *state = space->machine().driver_data<sms_state>();
1240	1213
1241		state->map_cart_8k( 0x8000, data );
	1214	map_cart_8k( 0x8000, data );
1242	1215	}
1243	1216
1244	1217
1245		WRITE8_HANDLER( sms_janggun_bank3_w )
	1218	WRITE8_MEMBER(sms_state::sms_janggun_bank3_w)
1246	1219	{
1247		sms_state *state = space->machine().driver_data<sms_state>();
1248	1220
1249		state->map_cart_8k( 0xA000, data );
	1221	map_cart_8k( 0xA000, data );
1250	1222	}
1251	1223
1252	1224
1253		WRITE8_HANDLER( sms_bios_w )
	1225	WRITE8_MEMBER(sms_state::sms_bios_w)
1254	1226	{
1255		sms_state *state = space->machine().driver_data<sms_state>();
1256		state->m_bios_port = data;
	1227	m_bios_port = data;
1257	1228
1258		logerror("bios write %02x, pc: %04x\n", data, cpu_get_pc(&space->device()));
	1229	logerror("bios write %02x, pc: %04x\n", data, cpu_get_pc(&space.device()));
1259	1230
1260		setup_rom(space);
	1231	setup_rom(&space);
1261	1232	}
1262	1233
1263	1234
1264		WRITE8_HANDLER( sms_cartram2_w )
	1235	WRITE8_MEMBER(sms_state::sms_cartram2_w)
1265	1236	{
1266		sms_state *state = space->machine().driver_data<sms_state>();
1267	1237
1268		if (state->m_mapper[0] & 0x08)
	1238	if (m_mapper[0] & 0x08)
1269	1239	{
1270	1240	logerror("write %02X to cartram at offset #%04X\n", data, offset + 0x2000);
1271		if (state->m_mapper[0] & 0x04)
	1241	if (m_mapper[0] & 0x04)
1272	1242	{
1273		state->m_cartridge[state->m_current_cartridge].cartSRAM[offset + 0x6000] = data;
	1243	m_cartridge[m_current_cartridge].cartSRAM[offset + 0x6000] = data;
1274	1244	}
1275	1245	else
1276	1246	{
1277		state->m_cartridge[state->m_current_cartridge].cartSRAM[offset + 0x2000] = data;
	1247	m_cartridge[m_current_cartridge].cartSRAM[offset + 0x2000] = data;
1278	1248	}
1279	1249	}
1280	1250
1281		if (state->m_cartridge[state->m_current_cartridge].features & CF_CODEMASTERS_MAPPER)
	1251	if (m_cartridge[m_current_cartridge].features & CF_CODEMASTERS_MAPPER)
1282	1252	{
1283		state->m_cartridge[state->m_current_cartridge].cartRAM[state->m_cartridge[state->m_current_cartridge].ram_page * 0x2000 + offset] = data;
	1253	m_cartridge[m_current_cartridge].cartRAM[m_cartridge[m_current_cartridge].ram_page * 0x2000 + offset] = data;
1284	1254	}
1285	1255
1286		if (state->m_cartridge[state->m_current_cartridge].features & CF_KOREAN_MAPPER && offset == 0) /* Dodgeball King mapper */
	1256	if (m_cartridge[m_current_cartridge].features & CF_KOREAN_MAPPER && offset == 0) /* Dodgeball King mapper */
1287	1257	{
1288		state->map_cart_16k( 0x8000, data );
	1258	map_cart_16k( 0x8000, data );
1289	1259	}
1290	1260	}
1291	1261
1292	1262
1293		WRITE8_HANDLER( sms_cartram_w )
	1263	WRITE8_MEMBER(sms_state::sms_cartram_w)
1294	1264	{
1295		sms_state *state = space->machine().driver_data<sms_state>();
1296	1265	int page;
1297	1266
1298		if (state->m_mapper[0] & 0x08)
	1267	if (m_mapper[0] & 0x08)
1299	1268	{
1300	1269	logerror("write %02X to cartram at offset #%04X\n", data, offset);
1301		if (state->m_mapper[0] & 0x04)
	1270	if (m_mapper[0] & 0x04)
1302	1271	{
1303		state->m_cartridge[state->m_current_cartridge].cartSRAM[offset + 0x4000] = data;
	1272	m_cartridge[m_current_cartridge].cartSRAM[offset + 0x4000] = data;
1304	1273	}
1305	1274	else
1306	1275	{
1307		state->m_cartridge[state->m_current_cartridge].cartSRAM[offset] = data;
	1276	m_cartridge[m_current_cartridge].cartSRAM[offset] = data;
1308	1277	}
1309	1278	}
1310	1279	else
1311	1280	{
1312		if (state->m_cartridge[state->m_current_cartridge].features & CF_CODEMASTERS_MAPPER && offset == 0) /* Codemasters mapper */
	1281	if (m_cartridge[m_current_cartridge].features & CF_CODEMASTERS_MAPPER && offset == 0) /* Codemasters mapper */
1313	1282	{
1314		UINT8 rom_page_count = state->m_cartridge[state->m_current_cartridge].size / 0x4000;
	1283	UINT8 rom_page_count = m_cartridge[m_current_cartridge].size / 0x4000;
1315	1284	page = (rom_page_count > 0) ? data % rom_page_count : 0;
1316		if (!state->m_cartridge[state->m_current_cartridge].ROM)
	1285	if (!m_cartridge[m_current_cartridge].ROM)
1317	1286	return;
1318		state->m_banking_cart[5] = state->m_cartridge[state->m_current_cartridge].ROM + page * 0x4000;
1319		memory_set_bankptr(space->machine(), "bank5", state->m_banking_cart[5]);
1320		memory_set_bankptr(space->machine(), "bank6", state->m_banking_cart[5] + 0x2000);
	1287	m_banking_cart[5] = m_cartridge[m_current_cartridge].ROM + page * 0x4000;
	1288	memory_set_bankptr(machine(), "bank5", m_banking_cart[5]);
	1289	memory_set_bankptr(machine(), "bank6", m_banking_cart[5] + 0x2000);
1321	1290	LOG(("rom 2 paged in %x (Codemasters mapper).\n", page));
1322	1291	}
1323		else if (state->m_cartridge[state->m_current_cartridge].features & CF_ONCART_RAM)
	1292	else if (m_cartridge[m_current_cartridge].features & CF_ONCART_RAM)
1324	1293	{
1325		state->m_cartridge[state->m_current_cartridge].cartRAM[offset & (state->m_cartridge[state->m_current_cartridge].ram_size - 1)] = data;
	1294	m_cartridge[m_current_cartridge].cartRAM[offset & (m_cartridge[m_current_cartridge].ram_size - 1)] = data;
1326	1295	}
1327	1296	else
1328	1297	{
r14963	r14964
1332	1301	}
1333	1302
1334	1303
1335		WRITE8_HANDLER( gg_sio_w )
	1304	WRITE8_MEMBER(sms_state::gg_sio_w)
1336	1305	{
1337		sms_state *state = space->machine().driver_data<sms_state>();
1338	1306	logerror("*** write %02X to SIO register #%d\n", data, offset);
1339	1307
1340		state->m_gg_sio[offset & 0x07] = data;
	1308	m_gg_sio[offset & 0x07] = data;
1341	1309	switch (offset & 7)
1342	1310	{
1343	1311	case 0x00: /* Parallel Data */
r14963	r14964
1358	1326	}
1359	1327
1360	1328
1361		READ8_HANDLER( gg_sio_r )
	1329	READ8_MEMBER(sms_state::gg_sio_r)
1362	1330	{
1363		sms_state *state = space->machine().driver_data<sms_state>();
1364	1331	logerror("*** read SIO register #%d\n", offset);
1365	1332
1366	1333	switch (offset & 7)
r14963	r14964
1381	1348	break;
1382	1349	}
1383	1350
1384		return state->m_gg_sio[offset];
	1351	return m_gg_sio[offset];
1385	1352	}
1386	1353
1387	1354	static void sms_machine_stop( running_machine &machine )
r14963	r14964
1999	1966	if ( state->m_cartridge[state->m_current_cartridge].features & CF_CODEMASTERS_MAPPER )
2000	1967	{
2001	1968	/* Install special memory handlers */
2002		space->install_legacy_write_handler(0x0000, 0x0000, FUNC(sms_codemasters_page0_w));
2003		space->install_legacy_write_handler(0x4000, 0x4000, FUNC(sms_codemasters_page1_w));
	1969	space->install_write_handler(0x0000, 0x0000, write8_delegate(FUNC(sms_state::sms_codemasters_page0_w),state));
	1970	space->install_write_handler(0x4000, 0x4000, write8_delegate(FUNC(sms_state::sms_codemasters_page1_w),state));
2004	1971	}
2005	1972
2006	1973	if ( state->m_cartridge[state->m_current_cartridge].features & CF_KOREAN_ZEMINA_MAPPER )
2007	1974	{
2008		space->install_legacy_write_handler(0x0000, 0x0003, FUNC(sms_korean_zemina_banksw_w));
	1975	space->install_write_handler(0x0000, 0x0003, write8_delegate(FUNC(sms_state::sms_korean_zemina_banksw_w),state));
2009	1976	}
2010	1977
2011	1978	if ( state->m_cartridge[state->m_current_cartridge].features & CF_JANGGUN_MAPPER )
2012	1979	{
2013		space->install_legacy_write_handler(0x4000, 0x4000, FUNC(sms_janggun_bank0_w));
2014		space->install_legacy_write_handler(0x6000, 0x6000, FUNC(sms_janggun_bank1_w));
2015		space->install_legacy_write_handler(0x8000, 0x8000, FUNC(sms_janggun_bank2_w));
2016		space->install_legacy_write_handler(0xA000, 0xA000, FUNC(sms_janggun_bank3_w));
	1980	space->install_write_handler(0x4000, 0x4000, write8_delegate(FUNC(sms_state::sms_janggun_bank0_w),state));
	1981	space->install_write_handler(0x6000, 0x6000, write8_delegate(FUNC(sms_state::sms_janggun_bank1_w),state));
	1982	space->install_write_handler(0x8000, 0x8000, write8_delegate(FUNC(sms_state::sms_janggun_bank2_w),state));
	1983	space->install_write_handler(0xA000, 0xA000,write8_delegate(FUNC(sms_state::sms_janggun_bank3_w),state));
2017	1984	}
2018	1985
2019	1986	if ( state->m_cartridge[state->m_current_cartridge].features & CF_4PAK_MAPPER )
2020	1987	{
2021		space->install_legacy_write_handler(0x3ffe, 0x3ffe, FUNC(sms_4pak_page0_w));
2022		space->install_legacy_write_handler(0x7fff, 0x7fff, FUNC(sms_4pak_page1_w));
2023		space->install_legacy_write_handler(0xbfff, 0xbfff, FUNC(sms_4pak_page2_w));
	1988	space->install_write_handler(0x3ffe, 0x3ffe, write8_delegate(FUNC(sms_state::sms_4pak_page0_w),state));
	1989	space->install_write_handler(0x7fff, 0x7fff, write8_delegate(FUNC(sms_state::sms_4pak_page1_w),state));
	1990	space->install_write_handler(0xbfff, 0xbfff, write8_delegate(FUNC(sms_state::sms_4pak_page2_w),state));
2024	1991	}
2025	1992
2026	1993	if ( state->m_cartridge[state->m_current_cartridge].features & CF_TVDRAW )
2027	1994	{
2028		space->install_legacy_write_handler(0x6000, 0x6000, FUNC(sms_tvdraw_axis_w));
2029		space->install_legacy_read_handler(0x8000, 0x8000, FUNC(sms_tvdraw_status_r));
2030		space->install_legacy_read_handler(0xa000, 0xa000, FUNC(sms_tvdraw_data_r));
	1995	space->install_write_handler(0x6000, 0x6000, write8_delegate(FUNC(sms_state::sms_tvdraw_axis_w),state));
	1996	space->install_read_handler(0x8000, 0x8000, read8_delegate(FUNC(sms_state::sms_tvdraw_status_r),state));
	1997	space->install_read_handler(0xa000, 0xa000, read8_delegate(FUNC(sms_state::sms_tvdraw_data_r),state));
2031	1998	space->nop_write(0xa000, 0xa000);
2032	1999	state->m_cartridge[state->m_current_cartridge].m_tvdraw_data = 0;
2033	2000	}
2034	2001
2035	2002	if ( state->m_cartridge[state->m_current_cartridge].features & CF_93C46_EEPROM )
2036	2003	{
2037		space->install_legacy_write_handler(0x8000,0x8000, FUNC(sms_93c46_w));
2038		space->install_legacy_read_handler(0x8000,0x8000, FUNC(sms_93c46_r));
	2004	space->install_write_handler(0x8000,0x8000, write8_delegate(FUNC(sms_state::sms_93c46_w),state));
	2005	space->install_read_handler(0x8000,0x8000, read8_delegate(FUNC(sms_state::sms_93c46_r),state));
2039	2006	}
2040	2007
2041	2008	if (state->m_cartridge[state->m_current_cartridge].features & CF_GG_SMS_MODE)
r14963	r14964
2079	2046	state->m_sscope_state = 0;
2080	2047	}
2081	2048
2082		READ8_HANDLER( sms_store_cart_select_r )
	2049	READ8_MEMBER(sms_state::sms_store_cart_select_r)
2083	2050	{
2084	2051	return 0xff;
2085	2052	}
2086	2053
2087	2054
2088		WRITE8_HANDLER( sms_store_cart_select_w )
	2055	WRITE8_MEMBER(sms_state::sms_store_cart_select_w)
2089	2056	{
2090		sms_state *state = space->machine().driver_data<sms_state>();
2091	2057	UINT8 slot = data >> 4;
2092	2058	UINT8 slottype = data & 0x08;
2093	2059
2094	2060	logerror("switching in part of %s slot #%d\n", slottype ? "card" : "cartridge", slot );
2095	2061	/* cartridge? slot #0 */
2096	2062	if (slottype == 0)
2097		state->m_current_cartridge = slot;
	2063	m_current_cartridge = slot;
2098	2064
2099		setup_cart_banks(space->machine());
2100		memory_set_bankptr(space->machine(), "bank10", state->m_banking_cart[3] + 0x2000);
2101		setup_rom(space);
	2065	setup_cart_banks(machine());
	2066	memory_set_bankptr(machine(), "bank10", m_banking_cart[3] + 0x2000);
	2067	setup_rom(&space);
2102	2068	}
2103	2069
2104	2070
2105		READ8_HANDLER( sms_store_select1 )
	2071	READ8_MEMBER(sms_state::sms_store_select1)
2106	2072	{
2107	2073	return 0xff;
2108	2074	}
2109	2075
2110	2076
2111		READ8_HANDLER( sms_store_select2 )
	2077	READ8_MEMBER(sms_state::sms_store_select2)
2112	2078	{
2113	2079	return 0xff;
2114	2080	}
2115	2081
2116	2082
2117		READ8_HANDLER( sms_store_control_r )
	2083	READ8_MEMBER(sms_state::sms_store_control_r)
2118	2084	{
2119		sms_state *state = space->machine().driver_data<sms_state>();
2120		return state->m_store_control;
	2085	return m_store_control;
2121	2086	}
2122	2087
2123	2088
2124		WRITE8_HANDLER( sms_store_control_w )
	2089	WRITE8_MEMBER(sms_state::sms_store_control_w)
2125	2090	{
2126		sms_state *state = space->machine().driver_data<sms_state>();
2127		logerror("0x%04X: sms_store_control write 0x%02X\n", cpu_get_pc(&space->device()), data);
	2091	logerror("0x%04X: sms_store_control write 0x%02X\n", cpu_get_pc(&space.device()), data);
2128	2092	if (data & 0x02)
2129	2093	{
2130		space->machine().device<cpu_device>("maincpu")->resume(SUSPEND_REASON_HALT);
	2094	machine().device<cpu_device>("maincpu")->resume(SUSPEND_REASON_HALT);
2131	2095	}
2132	2096	else
2133	2097	{
2134	2098	/* Pull reset line of CPU #0 low */
2135		space->machine().device("maincpu")->reset();
2136		space->machine().device<cpu_device>("maincpu")->suspend(SUSPEND_REASON_HALT, 1);
	2099	machine().device("maincpu")->reset();
	2100	machine().device<cpu_device>("maincpu")->suspend(SUSPEND_REASON_HALT, 1);
2137	2101	}
2138		state->m_store_control = data;
	2102	m_store_control = data;
2139	2103	}
2140	2104
2141	2105	WRITE_LINE_DEVICE_HANDLER( sms_store_int_callback )

src/mess/machine/llc.c

r14963	r14964
128	128
129	129	}
130	130
131		WRITE8_HANDLER( llc2_rom_disable_w )
	131	WRITE8_MEMBER(llc_state::llc2_rom_disable_w)
132	132	{
133		address_space *mem_space = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
134		UINT8 *ram = space->machine().device<ram_device>(RAM_TAG)->pointer();
	133	address_space *mem_space = machine().device("maincpu")->memory().space(AS_PROGRAM);
	134	UINT8 *ram = machine().device<ram_device>(RAM_TAG)->pointer();
135	135
136	136	mem_space->install_write_bank(0x0000, 0xbfff, "bank1");
137		memory_set_bankptr(space->machine(), "bank1", ram);
	137	memory_set_bankptr(machine(), "bank1", ram);
138	138
139	139	mem_space->install_write_bank(0x4000, 0x5fff, "bank2");
140		memory_set_bankptr(space->machine(), "bank2", ram + 0x4000);
	140	memory_set_bankptr(machine(), "bank2", ram + 0x4000);
141	141
142	142	mem_space->install_write_bank(0x6000, 0xbfff, "bank3");
143		memory_set_bankptr(space->machine(), "bank3", ram + 0x6000);
	143	memory_set_bankptr(machine(), "bank3", ram + 0x6000);
144	144
145	145	mem_space->install_write_bank(0xc000, 0xffff, "bank4");
146		memory_set_bankptr(space->machine(), "bank4", ram + 0xc000);
	146	memory_set_bankptr(machine(), "bank4", ram + 0xc000);
147	147
148	148	}
149	149
150		WRITE8_HANDLER( llc2_basic_enable_w )
	150	WRITE8_MEMBER(llc_state::llc2_basic_enable_w)
151	151	{
152	152
153		address_space *mem_space = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
	153	address_space *mem_space = machine().device("maincpu")->memory().space(AS_PROGRAM);
154	154	if (data & 0x02) {
155	155	mem_space->unmap_write(0x4000, 0x5fff);
156		memory_set_bankptr(space->machine(), "bank2", space->machine().region("maincpu")->base() + 0x10000);
	156	memory_set_bankptr(machine(), "bank2", machine().region("maincpu")->base() + 0x10000);
157	157	} else {
158	158	mem_space->install_write_bank(0x4000, 0x5fff, "bank2");
159		memory_set_bankptr(space->machine(), "bank2", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0x4000);
	159	memory_set_bankptr(machine(), "bank2", machine().device<ram_device>(RAM_TAG)->pointer() + 0x4000);
160	160	}
161	161
162	162	}

src/mess/machine/odyssey2.c

r14963	r14964
39	39	drvstate->m_the_voice_lrq_state = state;
40	40	}
41	41
42		READ8_HANDLER( odyssey2_t0_r ) {
43		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
44		return ( state->m_the_voice_lrq_state == ASSERT_LINE ) ? 0 : 1;
	42	READ8_MEMBER(odyssey2_state::odyssey2_t0_r){
	43	return ( m_the_voice_lrq_state == ASSERT_LINE ) ? 0 : 1;
45	44	}
46	45
47	46	DRIVER_INIT( odyssey2 )
r14963	r14964
85	84
86	85	/****** External RAM ******************************/
87	86
88		READ8_HANDLER( odyssey2_bus_r )
	87	READ8_MEMBER(odyssey2_state::odyssey2_bus_r)
89	88	{
90		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
91		if ((state->m_p1 & (P1_VDC_COPY_MODE_ENABLE | P1_VDC_ENABLE)) == 0)
	89	if ((m_p1 & (P1_VDC_COPY_MODE_ENABLE | P1_VDC_ENABLE)) == 0)
92	90	return odyssey2_video_r(space, offset); /* seems to have higher priority than ram??? */
93	91
94		else if (!(state->m_p1 & P1_EXT_RAM_ENABLE))
95		return state->m_ram[offset];
	92	else if (!(m_p1 & P1_EXT_RAM_ENABLE))
	93	return m_ram[offset];
96	94
97	95	return 0;
98	96	}
99	97
100		WRITE8_HANDLER( odyssey2_bus_w )
	98	WRITE8_MEMBER(odyssey2_state::odyssey2_bus_w)
101	99	{
102		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
103		if ((state->m_p1 & (P1_EXT_RAM_ENABLE | P1_VDC_COPY_MODE_ENABLE)) == 0x00) {
104		state->m_ram[offset] = data;
	100	if ((m_p1 & (P1_EXT_RAM_ENABLE | P1_VDC_COPY_MODE_ENABLE)) == 0x00) {
	101	m_ram[offset] = data;
105	102	if ( offset & 0x80 ) {
106	103	if ( data & 0x20 ) {
107		logerror("voice write %02X, data = %02X (p1 = %02X)\n", offset, data, state->m_p1 );
108		sp0256_ALD_w( space->machine().device("sp0256_speech"), 0, offset & 0x7F );
	104	logerror("voice write %02X, data = %02X (p1 = %02X)\n", offset, data, m_p1 );
	105	sp0256_ALD_w( machine().device("sp0256_speech"), 0, offset & 0x7F );
109	106	} else {
110	107	/* TODO: Reset sp0256 in this case */
111	108	}
112	109	}
113	110	}
114	111
115		else if (!(state->m_p1 & P1_VDC_ENABLE))
	112	else if (!(m_p1 & P1_VDC_ENABLE))
116	113	odyssey2_video_w(space, offset, data);
117	114	}
118	115
119		READ8_HANDLER( g7400_bus_r )
	116	READ8_MEMBER(odyssey2_state::g7400_bus_r)
120	117	{
121		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
122		if ((state->m_p1 & (P1_VDC_COPY_MODE_ENABLE | P1_VDC_ENABLE)) == 0) {
	118	if ((m_p1 & (P1_VDC_COPY_MODE_ENABLE | P1_VDC_ENABLE)) == 0) {
123	119	return odyssey2_video_r(space, offset); /* seems to have higher priority than ram??? */
124	120	}
125		else if (!(state->m_p1 & P1_EXT_RAM_ENABLE)) {
126		return state->m_ram[offset];
	121	else if (!(m_p1 & P1_EXT_RAM_ENABLE)) {
	122	return m_ram[offset];
127	123	} else {
128	124	//      return ef9341_r( offset & 0x02, offset & 0x01 );
129	125	}
r14963	r14964
131	127	return 0;
132	128	}
133	129
134		WRITE8_HANDLER( g7400_bus_w )
	130	WRITE8_MEMBER(odyssey2_state::g7400_bus_w)
135	131	{
136		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
137		if ((state->m_p1 & (P1_EXT_RAM_ENABLE | P1_VDC_COPY_MODE_ENABLE)) == 0x00) {
138		state->m_ram[offset] = data;
	132	if ((m_p1 & (P1_EXT_RAM_ENABLE | P1_VDC_COPY_MODE_ENABLE)) == 0x00) {
	133	m_ram[offset] = data;
139	134	}
140		else if (!(state->m_p1 & P1_VDC_ENABLE)) {
	135	else if (!(m_p1 & P1_VDC_ENABLE)) {
141	136	odyssey2_video_w(space, offset, data);
142	137	} else {
143	138	//      ef9341_w( offset & 0x02, offset & 0x01, data );
r14963	r14964
146	141
147	142	/***** 8048 Ports ************************/
148	143
149		READ8_HANDLER( odyssey2_getp1 )
	144	READ8_MEMBER(odyssey2_state::odyssey2_getp1)
150	145	{
151		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
152		UINT8 data = state->m_p1;
	146	UINT8 data = m_p1;
153	147
154		logerror("%.9f p1 read %.2x\n", space->machine().time().as_double(), data);
	148	logerror("%.9f p1 read %.2x\n", machine().time().as_double(), data);
155	149	return data;
156	150	}
157	151
158		WRITE8_HANDLER( odyssey2_putp1 )
	152	WRITE8_MEMBER(odyssey2_state::odyssey2_putp1)
159	153	{
160		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
161		state->m_p1 = data;
	154	m_p1 = data;
162	155
163		odyssey2_switch_banks(space->machine());
	156	odyssey2_switch_banks(machine());
164	157
165		odyssey2_lum_w ( space, 0, state->m_p1 >> 7 );
	158	odyssey2_lum_w ( space, 0, m_p1 >> 7 );
166	159
167		logerror("%.6f p1 written %.2x\n", space->machine().time().as_double(), data);
	160	logerror("%.6f p1 written %.2x\n", machine().time().as_double(), data);
168	161	}
169	162
170		READ8_HANDLER( odyssey2_getp2 )
	163	READ8_MEMBER(odyssey2_state::odyssey2_getp2)
171	164	{
172		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
173	165	UINT8 h = 0xFF;
174	166	int i, j;
175	167	static const char *const keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4", "KEY5" };
176	168
177		if (!(state->m_p1 & P1_KEYBOARD_SCAN_ENABLE))
	169	if (!(m_p1 & P1_KEYBOARD_SCAN_ENABLE))
178	170	{
179		if ((state->m_p2 & P2_KEYBOARD_SELECT_MASK) <= 5)  /* read keyboard */
	171	if ((m_p2 & P2_KEYBOARD_SELECT_MASK) <= 5)  /* read keyboard */
180	172	{
181		h &= input_port_read(space->machine(), keynames[state->m_p2 & P2_KEYBOARD_SELECT_MASK]);
	173	h &= input_port_read(machine(), keynames[m_p2 & P2_KEYBOARD_SELECT_MASK]);
182	174	}
183	175
184	176	for (i= 0x80, j = 0; i > 0; i >>= 1, j++)
185	177	{
186	178	if (!(h & i))
187	179	{
188		state->m_p2 &= ~0x10;                   /* set key was pressed indicator */
189		state->m_p2 = (state->m_p2 & ~0xE0) | (j << 5);  /* column that was pressed */
	180	m_p2 &= ~0x10;                   /* set key was pressed indicator */
	181	m_p2 = (m_p2 & ~0xE0) | (j << 5);  /* column that was pressed */
190	182
191	183	break;
192	184	}
193	185	}
194	186
195	187	if (h == 0xFF)  /* active low inputs, so no keypresses */
196		state->m_p2 = state->m_p2 | 0xF0;
	188	m_p2 = m_p2 | 0xF0;
197	189	}
198	190
199	191	else
200		state->m_p2 = state->m_p2 | 0xF0;
	192	m_p2 = m_p2 | 0xF0;
201	193
202		logerror("%.6f p2 read %.2x\n", space->machine().time().as_double(), state->m_p2);
203		return state->m_p2;
	194	logerror("%.6f p2 read %.2x\n", machine().time().as_double(), m_p2);
	195	return m_p2;
204	196	}
205	197
206		WRITE8_HANDLER( odyssey2_putp2 )
	198	WRITE8_MEMBER(odyssey2_state::odyssey2_putp2)
207	199	{
208		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
209		state->m_p2 = data;
	200	m_p2 = data;
210	201
211		logerror("%.6f p2 written %.2x\n", space->machine().time().as_double(), data);
	202	logerror("%.6f p2 written %.2x\n", machine().time().as_double(), data);
212	203	}
213	204
214		READ8_HANDLER( odyssey2_getbus )
	205	READ8_MEMBER(odyssey2_state::odyssey2_getbus)
215	206	{
216		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
217	207	UINT8 data = 0xff;
218	208
219		if ((state->m_p2 & P2_KEYBOARD_SELECT_MASK) == 1)
220		data &= input_port_read(space->machine(), "JOY0");       /* read joystick 1 */
	209	if ((m_p2 & P2_KEYBOARD_SELECT_MASK) == 1)
	210	data &= input_port_read(machine(), "JOY0");       /* read joystick 1 */
221	211
222		if ((state->m_p2 & P2_KEYBOARD_SELECT_MASK) == 0)
223		data &= input_port_read(space->machine(), "JOY1");       /* read joystick 2 */
	212	if ((m_p2 & P2_KEYBOARD_SELECT_MASK) == 0)
	213	data &= input_port_read(machine(), "JOY1");       /* read joystick 2 */
224	214
225		logerror("%.6f bus read %.2x\n", space->machine().time().as_double(), data);
	215	logerror("%.6f bus read %.2x\n", machine().time().as_double(), data);
226	216	return data;
227	217	}
228	218
229		WRITE8_HANDLER( odyssey2_putbus )
	219	WRITE8_MEMBER(odyssey2_state::odyssey2_putbus)
230	220	{
231		logerror("%.6f bus written %.2x\n", space->machine().time().as_double(), data);
	221	logerror("%.6f bus written %.2x\n", machine().time().as_double(), data);
232	222	}
233	223
234	224	///////////////////////////////////

src/mess/machine/ti85.c

r14963	r14964
225	225
226	226	/* I/O ports handlers */
227	227
228		READ8_HANDLER ( ti85_port_0000_r )
	228	READ8_MEMBER(ti85_state::ti85_port_0000_r)
229	229	{
230	230	return 0xff;
231	231	}
232	232
233		READ8_HANDLER ( ti8x_keypad_r )
	233	READ8_MEMBER(ti85_state::ti8x_keypad_r)
234	234	{
235		ti85_state *state = space->machine().driver_data<ti85_state>();
236	235	int data = 0xff;
237	236	int port;
238	237	int bit;
239	238	static const char *const bitnames[] = { "BIT0", "BIT1", "BIT2", "BIT3", "BIT4", "BIT5", "BIT6", "BIT7" };
240	239
241		if (state->m_keypad_mask == 0x7f) return data;
	240	if (m_keypad_mask == 0x7f) return data;
242	241
243	242	for (bit = 0; bit < 7; bit++)
244	243	{
245		if (~state->m_keypad_mask&(0x01<<bit))
	244	if (~m_keypad_mask&(0x01<<bit))
246	245	{
247	246	for (port = 0; port < 8; port++)
248	247	{
249		data ^= input_port_read(space->machine(), bitnames[port]) & (0x01<<bit) ? 0x01<<port : 0x00;
	248	data ^= input_port_read(machine(), bitnames[port]) & (0x01<<bit) ? 0x01<<port : 0x00;
250	249	}
251	250	}
252	251	}
253	252	return data;
254	253	}
255	254
256		READ8_HANDLER ( ti85_port_0002_r )
	255	READ8_MEMBER(ti85_state::ti85_port_0002_r )
257	256	{
258	257	return 0xff;
259	258	}
260	259
261		READ8_HANDLER ( ti85_port_0003_r )
	260	READ8_MEMBER(ti85_state::ti85_port_0003_r )
262	261	{
263		ti85_state *state = space->machine().driver_data<ti85_state>();
264	262	int data = 0;
265	263
266		if (state->m_LCD_status)
267		data |= state->m_LCD_mask;
268		if (state->m_ON_interrupt_status)
	264	if (m_LCD_status)
	265	data |= m_LCD_mask;
	266	if (m_ON_interrupt_status)
269	267	data |= 0x01;
270		if (state->m_timer_interrupt_status)
	268	if (m_timer_interrupt_status)
271	269	data |= 0x04;
272		if (!state->m_ON_pressed)
	270	if (!m_ON_pressed)
273	271	data |= 0x08;
274		state->m_ON_interrupt_status = 0;
275		state->m_timer_interrupt_status = 0;
	272	m_ON_interrupt_status = 0;
	273	m_timer_interrupt_status = 0;
276	274	return data;
277	275	}
278	276
279		READ8_HANDLER ( ti85_port_0004_r )
	277	READ8_MEMBER(ti85_state::ti85_port_0004_r )
280	278	{
281	279	return 0xff;
282	280	}
283	281
284		READ8_HANDLER ( ti85_port_0005_r )
	282	READ8_MEMBER(ti85_state::ti85_port_0005_r )
285	283	{
286		ti85_state *state = space->machine().driver_data<ti85_state>();
287		return state->m_ti8x_memory_page_1;
	284	return m_ti8x_memory_page_1;
288	285	}
289	286
290		READ8_HANDLER ( ti85_port_0006_r )
	287	READ8_MEMBER(ti85_state::ti85_port_0006_r)
291	288	{
292		ti85_state *state = space->machine().driver_data<ti85_state>();
293		return state->m_power_mode;
	289	return m_power_mode;
294	290	}
295	291
296		READ8_HANDLER ( ti8x_serial_r )
	292	READ8_MEMBER(ti85_state::ti8x_serial_r)
297	293	{
298		ti85_state *state = space->machine().driver_data<ti85_state>();
299	294
300		//ti85_update_serial(state->m_serial);
301		return (state->m_white_out<<3)
302		| (state->m_red_out<<2)
303		//| ((ti85serial_white_in(state->m_serial,0)&(1-state->m_white_out))<<1)
304		//| (ti85serial_red_in(state->m_serial,0)&(1-state->m_red_out))
	295	//ti85_update_serial(m_serial);
	296	return (m_white_out<<3)
	297	| (m_red_out<<2)
	298	//| ((ti85serial_white_in(m_serial,0)&(1-m_white_out))<<1)
	299	//| (ti85serial_red_in(m_serial,0)&(1-m_red_out))
305	300	| 0x03   // no link cable
306		| state->m_PCR;
	301	| m_PCR;
307	302	}
308	303
309		READ8_HANDLER ( ti82_port_0002_r )
	304	READ8_MEMBER(ti85_state::ti82_port_0002_r )
310	305	{
311		ti85_state *state = space->machine().driver_data<ti85_state>();
312		return state->m_ti8x_port2;
	306	return m_ti8x_port2;
313	307	}
314	308
315		READ8_HANDLER ( ti86_port_0005_r )
	309	READ8_MEMBER(ti85_state::ti86_port_0005_r)
316	310	{
317		ti85_state *state = space->machine().driver_data<ti85_state>();
318		return state->m_ti8x_memory_page_1;
	311	return m_ti8x_memory_page_1;
319	312	}
320	313
321		READ8_HANDLER ( ti86_port_0006_r )
	314	READ8_MEMBER(ti85_state::ti86_port_0006_r )
322	315	{
323		ti85_state *state = space->machine().driver_data<ti85_state>();
324		return state->m_ti8x_memory_page_2;
	316	return m_ti8x_memory_page_2;
325	317	}
326	318
327		READ8_HANDLER ( ti83_port_0000_r )
	319	READ8_MEMBER(ti85_state::ti83_port_0000_r)
328	320	{
329		ti85_state *state = space->machine().driver_data<ti85_state>();
330		return ((state->m_ti8x_memory_page_1 & 0x08) << 1) | 0x0C;
	321	return ((m_ti8x_memory_page_1 & 0x08) << 1) | 0x0C;
331	322	}
332	323
333		READ8_HANDLER ( ti83_port_0002_r )
	324	READ8_MEMBER(ti85_state::ti83_port_0002_r )
334	325	{
335		ti85_state *state = space->machine().driver_data<ti85_state>();
336		return state->m_ti8x_port2;
	326	return m_ti8x_port2;
337	327	}
338	328
339		READ8_HANDLER ( ti83_port_0003_r )
	329	READ8_MEMBER(ti85_state::ti83_port_0003_r )
340	330	{
341		ti85_state *state = space->machine().driver_data<ti85_state>();
342	331	int data = 0;
343	332
344		data |= state->m_LCD_mask;
	333	data |= m_LCD_mask;
345	334
346		if (state->m_ON_interrupt_status)
	335	if (m_ON_interrupt_status)
347	336	data |= 0x01;
348		if (!state->m_ON_pressed)
	337	if (!m_ON_pressed)
349	338	data |= 0x08;
350		state->m_ON_interrupt_status = 0;
351		state->m_timer_interrupt_status = 0;
	339	m_ON_interrupt_status = 0;
	340	m_timer_interrupt_status = 0;
352	341	return data;
353	342	}
354	343
355		READ8_HANDLER ( ti8x_plus_serial_r )
	344	READ8_MEMBER(ti85_state::ti8x_plus_serial_r)
356	345	{
357		ti85_state *state = space->machine().driver_data<ti85_state>();
358	346
359		//ti85_update_serial(state->m_serial);
360		return (state->m_white_out<<3)
361		| (state->m_red_out<<2)
362		//| ((ti85serial_white_in(state->m_serial,0)&(1-state->m_white_out))<<1)
363		//| (ti85serial_red_in(state->m_serial,0)&(1-state->m_red_out))
	347	//ti85_update_serial(m_serial);
	348	return (m_white_out<<3)
	349	| (m_red_out<<2)
	350	//| ((ti85serial_white_in(m_serial,0)&(1-m_white_out))<<1)
	351	//| (ti85serial_red_in(m_serial,0)&(1-m_red_out))
364	352	| 0x03   // no link cable
365		| state->m_PCR;
	353	| m_PCR;
366	354	}
367	355
368		READ8_HANDLER ( ti83p_port_0002_r )
	356	READ8_MEMBER(ti85_state::ti83p_port_0002_r )
369	357	{
370		ti85_state *state = space->machine().driver_data<ti85_state>();
371		return state->m_ti8x_port2|3;
	358	return m_ti8x_port2|3;
372	359	}
373	360
374		WRITE8_HANDLER ( ti81_port_0007_w )
	361	WRITE8_MEMBER(ti85_state::ti81_port_0007_w)
375	362	{
376		ti85_state *state = space->machine().driver_data<ti85_state>();
377		state->m_ti81_port_7_data = data;
	363	m_ti81_port_7_data = data;
378	364	}
379	365
380		WRITE8_HANDLER ( ti85_port_0000_w )
	366	WRITE8_MEMBER(ti85_state::ti85_port_0000_w)
381	367	{
382		ti85_state *state = space->machine().driver_data<ti85_state>();
383		state->m_LCD_memory_base = data;
	368	m_LCD_memory_base = data;
384	369	}
385	370
386		WRITE8_HANDLER ( ti8x_keypad_w )
	371	WRITE8_MEMBER(ti85_state::ti8x_keypad_w)
387	372	{
388		ti85_state *state = space->machine().driver_data<ti85_state>();
389		state->m_keypad_mask = data&0x7f;
	373	m_keypad_mask = data&0x7f;
390	374	}
391	375
392		WRITE8_HANDLER ( ti85_port_0002_w )
	376	WRITE8_MEMBER(ti85_state::ti85_port_0002_w)
393	377	{
394		ti85_state *state = space->machine().driver_data<ti85_state>();
395		state->m_LCD_contrast = data&0x1f;
	378	m_LCD_contrast = data&0x1f;
396	379	}
397	380
398		WRITE8_HANDLER ( ti85_port_0003_w )
	381	WRITE8_MEMBER(ti85_state::ti85_port_0003_w)
399	382	{
400		ti85_state *state = space->machine().driver_data<ti85_state>();
401		if (state->m_LCD_status && !(data&0x08))   state->m_timer_interrupt_mask = 0;
402		state->m_ON_interrupt_mask = data&0x01;
403		//  state->m_timer_interrupt_mask = data&0x04;
404		state->m_LCD_mask = data&0x02;
405		state->m_LCD_status = data&0x08;
	383	if (m_LCD_status && !(data&0x08))   m_timer_interrupt_mask = 0;
	384	m_ON_interrupt_mask = data&0x01;
	385	//  m_timer_interrupt_mask = data&0x04;
	386	m_LCD_mask = data&0x02;
	387	m_LCD_status = data&0x08;
406	388	}
407	389
408		WRITE8_HANDLER ( ti85_port_0004_w )
	390	WRITE8_MEMBER(ti85_state::ti85_port_0004_w)
409	391	{
410		ti85_state *state = space->machine().driver_data<ti85_state>();
411		state->m_video_buffer_width = (data>>3)&0x03;
412		state->m_interrupt_speed = (data>>1)&0x03;
413		state->m_port4_bit0 = data&0x01;
	392	m_video_buffer_width = (data>>3)&0x03;
	393	m_interrupt_speed = (data>>1)&0x03;
	394	m_port4_bit0 = data&0x01;
414	395	}
415	396
416		WRITE8_HANDLER ( ti85_port_0005_w )
	397	WRITE8_MEMBER(ti85_state::ti85_port_0005_w)
417	398	{
418		ti85_state *state = space->machine().driver_data<ti85_state>();
419		state->m_ti8x_memory_page_1 = data;
420		update_ti85_memory(space->machine());
	399	m_ti8x_memory_page_1 = data;
	400	update_ti85_memory(machine());
421	401	}
422	402
423		WRITE8_HANDLER ( ti85_port_0006_w )
	403	WRITE8_MEMBER(ti85_state::ti85_port_0006_w)
424	404	{
425		ti85_state *state = space->machine().driver_data<ti85_state>();
426		state->m_power_mode = data;
	405	m_power_mode = data;
427	406	}
428	407
429		WRITE8_HANDLER ( ti8x_serial_w )
	408	WRITE8_MEMBER(ti85_state::ti8x_serial_w)
430	409	{
431		ti85_state *state = space->machine().driver_data<ti85_state>();
432	410
433		speaker_level_w(state->m_speaker, ( (data>>2)|(data>>3) ) & 0x01);
434		state->m_red_out=(data>>2)&0x01;
435		state->m_white_out=(data>>3)&0x01;
436		//ti85serial_red_out( state->m_serial, 0, state->m_red_out );
437		//ti85serial_white_out( state->m_serial, 0, state->m_white_out );
438		//ti85_update_serial(state->m_serial);
439		state->m_PCR = data&0xf0;
	411	speaker_level_w(m_speaker, ( (data>>2)|(data>>3) ) & 0x01);
	412	m_red_out=(data>>2)&0x01;
	413	m_white_out=(data>>3)&0x01;
	414	//ti85serial_red_out( m_serial, 0, m_red_out );
	415	//ti85serial_white_out( m_serial, 0, m_white_out );
	416	//ti85_update_serial(m_serial);
	417	m_PCR = data&0xf0;
440	418	}
441	419
442		WRITE8_HANDLER ( ti86_port_0005_w )
	420	WRITE8_MEMBER(ti85_state::ti86_port_0005_w)
443	421	{
444		ti85_state *state = space->machine().driver_data<ti85_state>();
445		state->m_ti8x_memory_page_1 = data&((data&0x40)?0x47:0x4f);
446		update_ti86_memory(space->machine());
	422	m_ti8x_memory_page_1 = data&((data&0x40)?0x47:0x4f);
	423	update_ti86_memory(machine());
447	424	}
448	425
449		WRITE8_HANDLER ( ti86_port_0006_w )
	426	WRITE8_MEMBER(ti85_state::ti86_port_0006_w)
450	427	{
451		ti85_state *state = space->machine().driver_data<ti85_state>();
452		state->m_ti8x_memory_page_2 = data&((data&0x40)?0x47:0x4f);
453		update_ti86_memory(space->machine());
	428	m_ti8x_memory_page_2 = data&((data&0x40)?0x47:0x4f);
	429	update_ti86_memory(machine());
454	430	}
455	431
456		WRITE8_HANDLER ( ti82_port_0002_w )
	432	WRITE8_MEMBER(ti85_state::ti82_port_0002_w)
457	433	{
458		ti85_state *state = space->machine().driver_data<ti85_state>();
459		state->m_ti8x_memory_page_1 = (data & 0x07);
460		update_ti85_memory(space->machine());
461		state->m_ti8x_port2 = data;
	434	m_ti8x_memory_page_1 = (data & 0x07);
	435	update_ti85_memory(machine());
	436	m_ti8x_port2 = data;
462	437	}
463	438
464		WRITE8_HANDLER ( ti83_port_0000_w )
	439	WRITE8_MEMBER(ti85_state::ti83_port_0000_w)
465	440	{
466		ti85_state *state = space->machine().driver_data<ti85_state>();
467		state->m_ti8x_memory_page_1 = (state->m_ti8x_memory_page_1 & 7) | ((data & 16) >> 1);
468		update_ti85_memory(space->machine());
	441	m_ti8x_memory_page_1 = (m_ti8x_memory_page_1 & 7) | ((data & 16) >> 1);
	442	update_ti85_memory(machine());
469	443	}
470	444
471		WRITE8_HANDLER ( ti83_port_0002_w )
	445	WRITE8_MEMBER(ti85_state::ti83_port_0002_w)
472	446	{
473		ti85_state *state = space->machine().driver_data<ti85_state>();
474		state->m_ti8x_memory_page_1 = (state->m_ti8x_memory_page_1 & 8) | (data & 7);
475		update_ti85_memory(space->machine());
476		state->m_ti8x_port2 = data;
	447	m_ti8x_memory_page_1 = (m_ti8x_memory_page_1 & 8) | (data & 7);
	448	update_ti85_memory(machine());
	449	m_ti8x_port2 = data;
477	450	}
478	451
479		WRITE8_HANDLER ( ti83_port_0003_w )
	452	WRITE8_MEMBER(ti85_state::ti83_port_0003_w)
480	453	{
481		ti85_state *state = space->machine().driver_data<ti85_state>();
482		if (state->m_LCD_status && !(data&0x08))   state->m_timer_interrupt_mask = 0;
483		state->m_ON_interrupt_mask = data&0x01;
484		//state->m_timer_interrupt_mask = data&0x04;
485		state->m_LCD_mask = data&0x02;
486		state->m_LCD_status = data&0x08;
	454	if (m_LCD_status && !(data&0x08))   m_timer_interrupt_mask = 0;
	455	m_ON_interrupt_mask = data&0x01;
	456	//m_timer_interrupt_mask = data&0x04;
	457	m_LCD_mask = data&0x02;
	458	m_LCD_status = data&0x08;
487	459	}
488	460
489		WRITE8_HANDLER ( ti8x_plus_serial_w )
	461	WRITE8_MEMBER(ti85_state::ti8x_plus_serial_w)
490	462	{
491		ti85_state *state = space->machine().driver_data<ti85_state>();
492	463
493		speaker_level_w(state->m_speaker,( (data>>0)|(data>>1) )&0x01 );
494		state->m_red_out=(data>>0)&0x01;
495		state->m_white_out=(data>>1)&0x01;
496		//ti85serial_red_out( state->m_serial, 0, state->m_red_out );
497		//ti85serial_white_out( state->m_serial, 0, state->m_white_out );
498		//ti85_update_serial(state->m_serial);
499		state->m_PCR = data&0xf0;
	464	speaker_level_w(m_speaker,( (data>>0)|(data>>1) )&0x01 );
	465	m_red_out=(data>>0)&0x01;
	466	m_white_out=(data>>1)&0x01;
	467	//ti85serial_red_out( m_serial, 0, m_red_out );
	468	//ti85serial_white_out( m_serial, 0, m_white_out );
	469	//ti85_update_serial(m_serial);
	470	m_PCR = data&0xf0;
500	471	}
501	472
502		WRITE8_HANDLER ( ti83p_port_0002_w )
	473	WRITE8_MEMBER(ti85_state::ti83p_port_0002_w)
503	474	{
504		ti85_state *state = space->machine().driver_data<ti85_state>();
505		state->m_ti8x_port2 = data;
	475	m_ti8x_port2 = data;
506	476	}
507	477
508		WRITE8_HANDLER ( ti83p_port_0003_w )
	478	WRITE8_MEMBER(ti85_state::ti83p_port_0003_w)
509	479	{
510		ti85_state *state = space->machine().driver_data<ti85_state>();
511		state->m_LCD_mask = (data&0x08) >> 2;
512		state->m_ON_interrupt_mask = data & 0x01;
	480	m_LCD_mask = (data&0x08) >> 2;
	481	m_ON_interrupt_mask = data & 0x01;
513	482	}
514	483
515		WRITE8_HANDLER ( ti83p_port_0004_w )
	484	WRITE8_MEMBER(ti85_state::ti83p_port_0004_w)
516	485	{
517		ti85_state *state = space->machine().driver_data<ti85_state>();
518		if ((data & 1) && !(state->m_ti83p_port4 & 1))
	486	if ((data & 1) && !(m_ti83p_port4 & 1))
519	487	{
520		state->m_ti8x_memory_page_1 = 0x1f;
521		state->m_ti8x_memory_page_2 = 0x1f;
	488	m_ti8x_memory_page_1 = 0x1f;
	489	m_ti8x_memory_page_2 = 0x1f;
522	490	}
523		else if (!(data & 1) && (state->m_ti83p_port4 & 1))
	491	else if (!(data & 1) && (m_ti83p_port4 & 1))
524	492	{
525		state->m_ti8x_memory_page_1 = 0x1f;
526		state->m_ti8x_memory_page_2 = 0x40;
	493	m_ti8x_memory_page_1 = 0x1f;
	494	m_ti8x_memory_page_2 = 0x40;
527	495	}
528		update_ti83p_memory(space->machine());
529		state->m_ti83p_port4 = data;
	496	update_ti83p_memory(machine());
	497	m_ti83p_port4 = data;
530	498	}
531	499
532		WRITE8_HANDLER ( ti83p_port_0006_w )
	500	WRITE8_MEMBER(ti85_state::ti83p_port_0006_w)
533	501	{
534		ti85_state *state = space->machine().driver_data<ti85_state>();
535		state->m_ti8x_memory_page_1 = data & ((data&0x40) ? 0x41 : 0x5f);
536		update_ti83p_memory(space->machine());
	502	m_ti8x_memory_page_1 = data & ((data&0x40) ? 0x41 : 0x5f);
	503	update_ti83p_memory(machine());
537	504	}
538	505
539		WRITE8_HANDLER ( ti83p_port_0007_w )
	506	WRITE8_MEMBER(ti85_state::ti83p_port_0007_w)
540	507	{
541		ti85_state *state = space->machine().driver_data<ti85_state>();
542		state->m_ti8x_memory_page_2 = data & ((data&0x40) ? 0x41 : 0x5f);
543		update_ti83p_memory(space->machine());
	508	m_ti8x_memory_page_2 = data & ((data&0x40) ? 0x41 : 0x5f);
	509	update_ti83p_memory(machine());
544	510	}
545	511
546	512	/* NVRAM functions */

src/mess/machine/galaxy.c

r14963	r14964
17	17	I/O devices
18	18	***************************************************************************/
19	19
20		READ8_HANDLER( galaxy_keyboard_r )
	20	READ8_MEMBER(galaxy_state::galaxy_keyboard_r)
21	21	{
22	22	static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7" };
23	23
24	24	if (offset == 0)
25	25	{
26		double level = (space->machine().device<cassette_image_device>(CASSETTE_TAG)->input());
	26	double level = (machine().device<cassette_image_device>(CASSETTE_TAG)->input());
27	27	return (level >  0) ? 0xfe : 0xff;
28	28	}
29	29	else
30	30	{
31		return input_port_read(space->machine(), keynames[(offset>>3) & 0x07]) & (0x01<<(offset & 0x07)) ? 0xfe : 0xff;
	31	return input_port_read(machine(), keynames[(offset>>3) & 0x07]) & (0x01<<(offset & 0x07)) ? 0xfe : 0xff;
32	32	}
33	33	}
34	34
35		WRITE8_HANDLER( galaxy_latch_w )
	35	WRITE8_MEMBER(galaxy_state::galaxy_latch_w)
36	36	{
37		galaxy_state *state = space->machine().driver_data<galaxy_state>();
38	37	double val = (((data >>6) & 1 ) + ((data >> 2) & 1) - 1) * 32000;
39		state->m_latch_value = data;
40		space->machine().device<cassette_image_device>(CASSETTE_TAG)->output(val);
	38	m_latch_value = data;
	39	machine().device<cassette_image_device>(CASSETTE_TAG)->output(val);
41	40	}
42	41
43	42

src/mess/machine/vtech2.c

r14963	r14964
114	114	logerror("laser_machine_init(): bank mask $%04X, video %d [$%05X]\n", state->m_laser_bank_mask, state->m_laser_video_bank, state->m_laser_video_bank * 0x04000);
115	115
116	116	for (i = 0; i < ARRAY_LENGTH(state->m_laser_bank); i++)
117		laser_bank_select_w(machine.device("maincpu")->memory().space(AS_PROGRAM), i, 0);
	117	state->laser_bank_select_w(*machine.device("maincpu")->memory().space(AS_PROGRAM), i, 0);
118	118	}
119	119
120	120	MACHINE_RESET( laser350 )
r14963	r14964
136	136	}
137	137
138	138
139		WRITE8_HANDLER( laser_bank_select_w )
	139	WRITE8_MEMBER(vtech2_state::laser_bank_select_w)
140	140	{
141		vtech2_state *state = space->machine().driver_data<vtech2_state>();
142	141	static const char *const bank_name[16] = {
143	142	"ROM lo","ROM hi","MM I/O","Video RAM lo",
144	143	"RAM #0","RAM #1","RAM #2","RAM #3",
r14963	r14964
149	148	offset %= 4;
150	149	data &= 15;
151	150
152		if( data != state->m_laser_bank[offset] )
	151	if( data != m_laser_bank[offset] )
153	152	{
154		state->m_laser_bank[offset] = data;
	153	m_laser_bank[offset] = data;
155	154	logerror("select bank #%d $%02X [$%05X] %s\n", offset+1, data, 0x4000 * (data & 15), bank_name[data]);
156	155
157	156	/* memory mapped I/O bank selected? */
158	157	if (data == 2)
159	158	{
160		space->machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(offset * 0x4000, offset * 0x4000 + 0x3fff, mra_bank_soft[offset].func, mra_bank_soft[offset].name);
161		space->machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(offset * 0x4000, offset * 0x4000 + 0x3fff, mwa_bank_soft[offset].func, mwa_bank_soft[offset].name);
	159	machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(offset * 0x4000, offset * 0x4000 + 0x3fff, mra_bank_soft[offset].func, mra_bank_soft[offset].name);
	160	machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(offset * 0x4000, offset * 0x4000 + 0x3fff, mwa_bank_soft[offset].func, mwa_bank_soft[offset].name);
162	161	}
163	162	else
164	163	{
165	164	sprintf(bank,"bank%d",offset+1);
166		memory_set_bankptr(space->machine(), bank, &state->m_mem[0x4000*state->m_laser_bank[offset]]);
167		if( state->m_laser_bank_mask & (1 << data) )
	165	memory_set_bankptr(machine(), bank, &m_mem[0x4000*m_laser_bank[offset]]);
	166	if( m_laser_bank_mask & (1 << data) )
168	167	{
169	168	/* video RAM bank selected? */
170		if( data == state->m_laser_video_bank )
	169	if( data == m_laser_video_bank )
171	170	{
172	171	logerror("select bank #%d VIDEO!\n", offset+1);
173	172	}
174		space->machine().device("maincpu")->memory().space(AS_PROGRAM)->install_read_bank(offset * 0x4000, offset * 0x4000 + 0x3fff, mra_bank_hard[offset]);
175		space->machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_bank(offset * 0x4000, offset * 0x4000 + 0x3fff, mwa_bank_hard[offset]);
	173	machine().device("maincpu")->memory().space(AS_PROGRAM)->install_read_bank(offset * 0x4000, offset * 0x4000 + 0x3fff, mra_bank_hard[offset]);
	174	machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_bank(offset * 0x4000, offset * 0x4000 + 0x3fff, mwa_bank_hard[offset]);
176	175
177	176	}
178	177	else
179	178	{
180	179	logerror("select bank #%d MASKED!\n", offset+1);
181		space->machine().device("maincpu")->memory().space(AS_PROGRAM)->nop_readwrite(offset * 0x4000, offset * 0x4000 + 0x3fff);
	180	machine().device("maincpu")->memory().space(AS_PROGRAM)->nop_readwrite(offset * 0x4000, offset * 0x4000 + 0x3fff);
182	181
183	182	}
184	183	}
r14963	r14964
399	398	#define PHI2(n) (((n)>>2)&1)
400	399	#define PHI3(n) (((n)>>3)&1)
401	400
402		READ8_HANDLER( laser_fdc_r )
	401	READ8_MEMBER(vtech2_state::laser_fdc_r)
403	402	{
404		vtech2_state *state = space->machine().driver_data<vtech2_state>();
405	403	int data = 0xff;
406	404	switch( offset )
407	405	{
408	406	case 1: /* data (read-only) */
409		if( state->m_laser_fdc_bits > 0 )
	407	if( m_laser_fdc_bits > 0 )
410	408	{
411		if( state->m_laser_fdc_status & 0x80 )
412		state->m_laser_fdc_bits--;
413		data = (state->m_laser_data >> state->m_laser_fdc_bits) & 0xff;
	409	if( m_laser_fdc_status & 0x80 )
	410	m_laser_fdc_bits--;
	411	data = (m_laser_data >> m_laser_fdc_bits) & 0xff;
414	412	#if 0
415	413	logerror("laser_fdc_r bits %d%d%d%d%d%d%d%d\n",
416	414	(data>>7)&1,(data>>6)&1,(data>>5)&1,(data>>4)&1,
417	415	(data>>3)&1,(data>>2)&1,(data>>1)&1,(data>>0)&1 );
418	416	#endif
419	417	}
420		if( state->m_laser_fdc_bits == 0 )
	418	if( m_laser_fdc_bits == 0 )
421	419	{
422		state->m_laser_data = state->m_laser_fdc_data[state->m_laser_fdc_offs];
423		logerror("laser_fdc_r %d : data ($%04X) $%02X\n", offset, state->m_laser_fdc_offs, state->m_laser_data);
424		if( state->m_laser_fdc_status & 0x80 )
	420	m_laser_data = m_laser_fdc_data[m_laser_fdc_offs];
	421	logerror("laser_fdc_r %d : data ($%04X) $%02X\n", offset, m_laser_fdc_offs, m_laser_data);
	422	if( m_laser_fdc_status & 0x80 )
425	423	{
426		state->m_laser_fdc_bits = 8;
427		state->m_laser_fdc_offs = (state->m_laser_fdc_offs + 1) % TRKSIZE_FM;
	424	m_laser_fdc_bits = 8;
	425	m_laser_fdc_offs = (m_laser_fdc_offs + 1) % TRKSIZE_FM;
428	426	}
429		state->m_laser_fdc_status &= ~0x80;
	427	m_laser_fdc_status &= ~0x80;
430	428	}
431	429	break;
432	430	case 2: /* polling (read-only) */
433	431	/* fake */
434		if( state->m_laser_drive >= 0 )
435		state->m_laser_fdc_status |= 0x80;
436		data = state->m_laser_fdc_status;
	432	if( m_laser_drive >= 0 )
	433	m_laser_fdc_status |= 0x80;
	434	data = m_laser_fdc_status;
437	435	break;
438	436	case 3: /* write protect status (read-only) */
439		if( state->m_laser_drive >= 0 )
440		data = laser_fdc_wrprot[state->m_laser_drive];
	437	if( m_laser_drive >= 0 )
	438	data = laser_fdc_wrprot[m_laser_drive];
441	439	logerror("laser_fdc_r %d : write_protect $%02X\n", offset, data);
442	440	break;
443	441	}
444	442	return data;
445	443	}
446	444
447		WRITE8_HANDLER( laser_fdc_w )
	445	WRITE8_MEMBER(vtech2_state::laser_fdc_w)
448	446	{
449		vtech2_state *state = space->machine().driver_data<vtech2_state>();
450	447	int drive;
451	448
452	449	switch( offset )
453	450	{
454	451	case 0: /* latch (write-only) */
455	452	drive = (data & 0x10) ? 0 : (data & 0x80) ? 1 : -1;
456		if( drive != state->m_laser_drive )
	453	if( drive != m_laser_drive )
457	454	{
458		state->m_laser_drive = drive;
459		if( state->m_laser_drive >= 0 )
460		laser_get_track(space->machine());
	455	m_laser_drive = drive;
	456	if( m_laser_drive >= 0 )
	457	laser_get_track(machine());
461	458	}
462		if( state->m_laser_drive >= 0 )
	459	if( m_laser_drive >= 0 )
463	460	{
464		if( (PHI0(data) && !(PHI1(data) || PHI2(data) || PHI3(data)) && PHI1(state->m_laser_fdc_latch)) ||
465		(PHI1(data) && !(PHI0(data) || PHI2(data) || PHI3(data)) && PHI2(state->m_laser_fdc_latch)) ||
466		(PHI2(data) && !(PHI0(data) || PHI1(data) || PHI3(data)) && PHI3(state->m_laser_fdc_latch)) ||
467		(PHI3(data) && !(PHI0(data) || PHI1(data) || PHI2(data)) && PHI0(state->m_laser_fdc_latch)) )
	461	if( (PHI0(data) && !(PHI1(data) || PHI2(data) || PHI3(data)) && PHI1(m_laser_fdc_latch)) ||
	462	(PHI1(data) && !(PHI0(data) || PHI2(data) || PHI3(data)) && PHI2(m_laser_fdc_latch)) ||
	463	(PHI2(data) && !(PHI0(data) || PHI1(data) || PHI3(data)) && PHI3(m_laser_fdc_latch)) ||
	464	(PHI3(data) && !(PHI0(data) || PHI1(data) || PHI2(data)) && PHI0(m_laser_fdc_latch)) )
468	465	{
469		if( state->m_laser_track_x2[state->m_laser_drive] > 0 )
470		state->m_laser_track_x2[state->m_laser_drive]--;
471		logerror("laser_fdc_w(%d) $%02X drive %d: stepout track #%2d.%d\n", offset, data, state->m_laser_drive, state->m_laser_track_x2[state->m_laser_drive]/2,5*(state->m_laser_track_x2[state->m_laser_drive]&1));
472		if( (state->m_laser_track_x2[state->m_laser_drive] & 1) == 0 )
473		laser_get_track(space->machine());
	466	if( m_laser_track_x2[m_laser_drive] > 0 )
	467	m_laser_track_x2[m_laser_drive]--;
	468	logerror("laser_fdc_w(%d) $%02X drive %d: stepout track #%2d.%d\n", offset, data, m_laser_drive, m_laser_track_x2[m_laser_drive]/2,5*(m_laser_track_x2[m_laser_drive]&1));
	469	if( (m_laser_track_x2[m_laser_drive] & 1) == 0 )
	470	laser_get_track(machine());
474	471	}
475	472	else
476		if( (PHI0(data) && !(PHI1(data) || PHI2(data) || PHI3(data)) && PHI3(state->m_laser_fdc_latch)) ||
477		(PHI1(data) && !(PHI0(data) || PHI2(data) || PHI3(data)) && PHI0(state->m_laser_fdc_latch)) ||
478		(PHI2(data) && !(PHI0(data) || PHI1(data) || PHI3(data)) && PHI1(state->m_laser_fdc_latch)) ||
479		(PHI3(data) && !(PHI0(data) || PHI1(data) || PHI2(data)) && PHI2(state->m_laser_fdc_latch)) )
	473	if( (PHI0(data) && !(PHI1(data) || PHI2(data) || PHI3(data)) && PHI3(m_laser_fdc_latch)) ||
	474	(PHI1(data) && !(PHI0(data) || PHI2(data) || PHI3(data)) && PHI0(m_laser_fdc_latch)) ||
	475	(PHI2(data) && !(PHI0(data) || PHI1(data) || PHI3(data)) && PHI1(m_laser_fdc_latch)) ||
	476	(PHI3(data) && !(PHI0(data) || PHI1(data) || PHI2(data)) && PHI2(m_laser_fdc_latch)) )
480	477	{
481		if( state->m_laser_track_x2[state->m_laser_drive] < 2*40 )
482		state->m_laser_track_x2[state->m_laser_drive]++;
483		logerror("laser_fdc_w(%d) $%02X drive %d: stepin track #%2d.%d\n", offset, data, state->m_laser_drive, state->m_laser_track_x2[state->m_laser_drive]/2,5*(state->m_laser_track_x2[state->m_laser_drive]&1));
484		if( (state->m_laser_track_x2[state->m_laser_drive] & 1) == 0 )
485		laser_get_track(space->machine());
	478	if( m_laser_track_x2[m_laser_drive] < 2*40 )
	479	m_laser_track_x2[m_laser_drive]++;
	480	logerror("laser_fdc_w(%d) $%02X drive %d: stepin track #%2d.%d\n", offset, data, m_laser_drive, m_laser_track_x2[m_laser_drive]/2,5*(m_laser_track_x2[m_laser_drive]&1));
	481	if( (m_laser_track_x2[m_laser_drive] & 1) == 0 )
	482	laser_get_track(machine());
486	483	}
487	484	if( (data & 0x40) == 0 )
488	485	{
489		state->m_laser_data <<= 1;
490		if( (state->m_laser_fdc_latch ^ data) & 0x20 )
491		state->m_laser_data |= 1;
492		if( (state->m_laser_fdc_edge ^= 1) == 0 )
	486	m_laser_data <<= 1;
	487	if( (m_laser_fdc_latch ^ data) & 0x20 )
	488	m_laser_data |= 1;
	489	if( (m_laser_fdc_edge ^= 1) == 0 )
493	490	{
494		if( --state->m_laser_fdc_bits == 0 )
	491	if( --m_laser_fdc_bits == 0 )
495	492	{
496	493	UINT8 value = 0;
497		state->m_laser_data &= 0xffff;
498		if( state->m_laser_data & 0x4000 ) value |= 0x80;
499		if( state->m_laser_data & 0x1000 ) value |= 0x40;
500		if( state->m_laser_data & 0x0400 ) value |= 0x20;
501		if( state->m_laser_data & 0x0100 ) value |= 0x10;
502		if( state->m_laser_data & 0x0040 ) value |= 0x08;
503		if( state->m_laser_data & 0x0010 ) value |= 0x04;
504		if( state->m_laser_data & 0x0004 ) value |= 0x02;
505		if( state->m_laser_data & 0x0001 ) value |= 0x01;
506		logerror("laser_fdc_w(%d) data($%04X) $%02X <- $%02X ($%04X)\n", offset, state->m_laser_fdc_offs, state->m_laser_fdc_data[state->m_laser_fdc_offs], value, state->m_laser_data);
507		state->m_laser_fdc_data[state->m_laser_fdc_offs] = value;
508		state->m_laser_fdc_offs = (state->m_laser_fdc_offs + 1) % TRKSIZE_FM;
509		state->m_laser_fdc_write++;
510		state->m_laser_fdc_bits = 8;
	494	m_laser_data &= 0xffff;
	495	if( m_laser_data & 0x4000 ) value |= 0x80;
	496	if( m_laser_data & 0x1000 ) value |= 0x40;
	497	if( m_laser_data & 0x0400 ) value |= 0x20;
	498	if( m_laser_data & 0x0100 ) value |= 0x10;
	499	if( m_laser_data & 0x0040 ) value |= 0x08;
	500	if( m_laser_data & 0x0010 ) value |= 0x04;
	501	if( m_laser_data & 0x0004 ) value |= 0x02;
	502	if( m_laser_data & 0x0001 ) value |= 0x01;
	503	logerror("laser_fdc_w(%d) data($%04X) $%02X <- $%02X ($%04X)\n", offset, m_laser_fdc_offs, m_laser_fdc_data[m_laser_fdc_offs], value, m_laser_data);
	504	m_laser_fdc_data[m_laser_fdc_offs] = value;
	505	m_laser_fdc_offs = (m_laser_fdc_offs + 1) % TRKSIZE_FM;
	506	m_laser_fdc_write++;
	507	m_laser_fdc_bits = 8;
511	508	}
512	509	}
513	510	}
514	511	/* change of write signal? */
515		if( (state->m_laser_fdc_latch ^ data) & 0x40 )
	512	if( (m_laser_fdc_latch ^ data) & 0x40 )
516	513	{
517	514	/* falling edge? */
518		if ( state->m_laser_fdc_latch & 0x40 )
	515	if ( m_laser_fdc_latch & 0x40 )
519	516	{
520		sprintf(state->m_laser_frame_message, "#%d put track %02d", state->m_laser_drive, state->m_laser_track_x2[state->m_laser_drive]/2);
521		state->m_laser_frame_time = 30;
522		state->m_laser_fdc_start = state->m_laser_fdc_offs;
523		state->m_laser_fdc_edge = 0;
	517	sprintf(m_laser_frame_message, "#%d put track %02d", m_laser_drive, m_laser_track_x2[m_laser_drive]/2);
	518	m_laser_frame_time = 30;
	519	m_laser_fdc_start = m_laser_fdc_offs;
	520	m_laser_fdc_edge = 0;
524	521	}
525	522	else
526	523	{
527	524	/* data written to track before? */
528		if( state->m_laser_fdc_write )
529		laser_put_track(space->machine());
	525	if( m_laser_fdc_write )
	526	laser_put_track(machine());
530	527	}
531		state->m_laser_fdc_bits = 8;
532		state->m_laser_fdc_write = 0;
	528	m_laser_fdc_bits = 8;
	529	m_laser_fdc_write = 0;
533	530	}
534	531	}
535		state->m_laser_fdc_latch = data;
	532	m_laser_fdc_latch = data;
536	533	break;
537	534	}
538	535	}

src/mess/machine/zx.c

r14963	r14964
18	18	#define LOG_ZX81_VSYNC do { if (DEBUG_ZX81_VSYNC) logerror("VSYNC starts in scanline: %d\n", space->machine().primary_screen->vpos()); } while (0)
19	19
20	20
21		static WRITE8_HANDLER( zx_ram_w )
	21	WRITE8_MEMBER(zx_state::zx_ram_w)
22	22	{
23		UINT8 *RAM = space->machine().region("maincpu")->base();
	23	UINT8 *RAM = machine().region("maincpu")->base();
24	24	RAM[offset + 0x4000] = data;
25	25
26	26	if (data & 0x40)
27	27	{
28		space->write_byte(offset | 0xc000, data);
	28	space.write_byte(offset | 0xc000, data);
29	29	RAM[offset | 0xc000] = data;
30	30	}
31	31	else
32	32	{
33		space->write_byte(offset | 0xc000, 0);
	33	space.write_byte(offset | 0xc000, 0);
34	34	RAM[offset | 0xc000] = 0;
35	35	}
36	36	}
r14963	r14964
44	44
45	45	DRIVER_INIT( zx )
46	46	{
	47	zx_state *state = machine.driver_data<zx_state>();
47	48	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
48	49
49	50	space->install_read_bank(0x4000, 0x4000 + machine.device<ram_device>(RAM_TAG)->size() - 1, "bank1");
50		space->install_legacy_write_handler(0x4000, 0x4000 + machine.device<ram_device>(RAM_TAG)->size() - 1, FUNC(zx_ram_w));
	51	space->install_write_handler(0x4000, 0x4000 + machine.device<ram_device>(RAM_TAG)->size() - 1, write8_delegate(FUNC(zx_state::zx_ram_w),state));
51	52	memory_set_bankptr(machine, "bank1", machine.region("maincpu")->base() + 0x4000);
52	53	}
53	54

src/mess/machine/concept.c

r14963	r14964
255	255	concept_set_interrupt(device->machine(), TIMINT_level, state);
256	256	}
257	257
258		READ16_HANDLER(concept_io_r)
	258	READ16_MEMBER(concept_state::concept_io_r)
259	259	{
260		concept_state *state = space->machine().driver_data<concept_state>();
261	260	if (! ACCESSING_BITS_0_7)
262	261	return 0;
263	262
r14963	r14964
277	276	/* IO4 registers */
278	277	{
279	278	int slot = ((offset >> 4) & 7) - 1;
280		if (state->m_expansion_slots[slot].reg_read)
281		return state->m_expansion_slots[slot].reg_read(space, offset & 0xf);
	279	if (m_expansion_slots[slot].reg_read)
	280	return m_expansion_slots[slot].reg_read(&space, offset & 0xf);
282	281	}
283	282	break;
284	283
r14963	r14964
300	299	{
301	300	int slot = ((offset >> 8) & 7) - 1;
302	301	LOG(("concept_io_r: Slot ROM memory accessed for slot %d at address 0x03%4.4x\n", slot, offset << 1));
303		if (state->m_expansion_slots[slot].rom_read)
304		return state->m_expansion_slots[slot].rom_read(space, offset & 0xff);
	302	if (m_expansion_slots[slot].rom_read)
	303	return m_expansion_slots[slot].rom_read(&space, offset & 0xff);
305	304	}
306	305	break;
307	306
r14963	r14964
313	312	case 6:
314	313	/* calendar R/W */
315	314	VLOG(("concept_io_r: Calendar read at address 0x03%4.4x\n", offset << 1));
316		if (!state->m_clock_enable)
317		return mm58274c_r(space->machine().device("mm58274c"), state->m_clock_address);
	315	if (!m_clock_enable)
	316	return mm58274c_r(machine().device("mm58274c"), m_clock_address);
318	317	break;
319	318
320	319	case 7:
r14963	r14964
331	330	/* data */
332	331	reply = 0;
333	332
334		if (state->m_KeyQueueLen)
	333	if (m_KeyQueueLen)
335	334	{
336		reply = state->m_KeyQueue[state->m_KeyQueueHead];
337		state->m_KeyQueueHead = (state->m_KeyQueueHead + 1) % KeyQueueSize;
338		state->m_KeyQueueLen--;
	335	reply = m_KeyQueue[m_KeyQueueHead];
	336	m_KeyQueueHead = (m_KeyQueueHead + 1) % KeyQueueSize;
	337	m_KeyQueueLen--;
339	338	}
340	339
341		if (!state->m_KeyQueueLen)
342		concept_set_interrupt(space->machine(), KEYINT_level, 0);
	340	if (!m_KeyQueueLen)
	341	concept_set_interrupt(machine(), KEYINT_level, 0);
343	342
344	343	return reply;
345	344
346	345	case 1:
347	346	/* always tell transmit is empty */
348		reply = state->m_KeyQueueLen ? 0x98 : 0x10;
	347	reply = m_KeyQueueLen ? 0x98 : 0x10;
349	348	break;
350	349	}
351	350	break;
r14963	r14964
362	361	/* NVIA versatile system interface */
363	362	LOG(("concept_io_r: VIA read at address 0x03%4.4x\n", offset << 1));
364	363	{
365		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
366		return via_0->read(*space, offset & 0xf);
	364	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	365	return via_0->read(space, offset & 0xf);
367	366	}
368	367	break;
369	368
r14963	r14964
394	393	return 0;
395	394	}
396	395
397		WRITE16_HANDLER(concept_io_w)
	396	WRITE16_MEMBER(concept_state::concept_io_w)
398	397	{
399		concept_state *state = space->machine().driver_data<concept_state>();
400	398	if (! ACCESSING_BITS_0_7)
401	399	return;
402	400
r14963	r14964
420	418	int slot = ((offset >> 4) & 7) - 1;
421	419	LOG(("concept_io_w: Slot I/O register written for slot %d at address 0x03%4.4x, data: 0x%4.4x\n",
422	420	slot, offset << 1, data));
423		if (state->m_expansion_slots[slot].reg_write)
424		state->m_expansion_slots[slot].reg_write(space, offset & 0xf, data);
	421	if (m_expansion_slots[slot].reg_write)
	422	m_expansion_slots[slot].reg_write(&space, offset & 0xf, data);
425	423	}
426	424	break;
427	425
r14963	r14964
443	441	{
444	442	int slot = ((offset >> 8) & 7) - 1;
445	443	LOG(("concept_io_w: Slot ROM memory written to for slot %d at address 0x03%4.4x, data: 0x%4.4x\n", slot, offset << 1, data));
446		if (state->m_expansion_slots[slot].rom_write)
447		state->m_expansion_slots[slot].rom_write(space, offset & 0xff, data);
	444	if (m_expansion_slots[slot].rom_write)
	445	m_expansion_slots[slot].rom_write(&space, offset & 0xff, data);
448	446	}
449	447	break;
450	448
r14963	r14964
456	454	case 6:
457	455	/* calendar R/W */
458	456	LOG(("concept_io_w: Calendar written to at address 0x03%4.4x, data: 0x%4.4x\n", offset << 1, data));
459		if (!state->m_clock_enable)
460		mm58274c_w(space->machine().device("mm58274c"), state->m_clock_address, data & 0xf);
	457	if (!m_clock_enable)
	458	mm58274c_w(machine().device("mm58274c"), m_clock_address, data & 0xf);
461	459	break;
462	460
463	461	case 7:
r14963	r14964
476	474	case 3:
477	475	/* NVIA versatile system interface */
478	476	{
479		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
480		via_0->write(*space, offset & 0xf, data);
	477	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	478	via_0->write(space, offset & 0xf, data);
481	479	}
482	480	break;
483	481
484	482	case 4:
485	483	/* NCALM clock calendar address and strobe register */
486		if (state->m_clock_enable != ((data & 0x10) != 0))
	484	if (m_clock_enable != ((data & 0x10) != 0))
487	485	{
488		state->m_clock_enable = (data & 0x10) != 0;
489		if (! state->m_clock_enable)
	486	m_clock_enable = (data & 0x10) != 0;
	487	if (! m_clock_enable)
490	488	/* latch address when enable goes low */
491		state->m_clock_address = data & 0x0f;
	489	m_clock_address = data & 0x0f;
492	490	}
493	491	/*volume_control = (data & 0x20) != 0;*/
494	492	/*alt_map = (data & 0x40) != 0;*/

src/mess/machine/msx.c

r14963	r14964
552	552	*/
553	553
554	554
555		READ8_HANDLER ( msx_psg_port_a_r )
	555	READ8_MEMBER(msx_state::msx_psg_port_a_r)
556	556	{
557		msx_state *state = space->machine().driver_data<msx_state>();
558	557	UINT8 data;
559	558
560		data = (state->m_cass->input() > 0.0038 ? 0x80 : 0);
	559	data = (m_cass->input() > 0.0038 ? 0x80 : 0);
561	560
562		if ( (state->m_psg_b ^ input_port_read(space->machine(), "DSW") ) & 0x40)
	561	if ( (m_psg_b ^ input_port_read(machine(), "DSW") ) & 0x40)
563	562	{
564	563	/* game port 2 */
565		UINT8 inp = input_port_read(space->machine(), "JOY1");
	564	UINT8 inp = input_port_read(machine(), "JOY1");
566	565	if ( !(inp & 0x80) )
567	566	{
568	567	/* joystick */
r14963	r14964
572	571	{
573	572	/* mouse */
574	573	data |= ( inp & 0x70 );
575		if (state->m_mouse_stat[1] < 0)
	574	if (m_mouse_stat[1] < 0)
576	575	data |= 0xf;
577	576	else
578		data |= ~(state->m_mouse[1] >> (4*state->m_mouse_stat[1]) ) & 15;
	577	data |= ~(m_mouse[1] >> (4*m_mouse_stat[1]) ) & 15;
579	578	}
580	579	}
581	580	else
582	581	{
583	582	/* game port 1 */
584		UINT8 inp = input_port_read(space->machine(), "JOY0");
	583	UINT8 inp = input_port_read(machine(), "JOY0");
585	584	if ( !(inp & 0x80) )
586	585	{
587	586	/* joystick */
r14963	r14964
591	590	{
592	591	/* mouse */
593	592	data |= ( inp & 0x70 );
594		if (state->m_mouse_stat[0] < 0)
	593	if (m_mouse_stat[0] < 0)
595	594	data |= 0xf;
596	595	else
597		data |= ~(state->m_mouse[0] >> (4*state->m_mouse_stat[0]) ) & 15;
	596	data |= ~(m_mouse[0] >> (4*m_mouse_stat[0]) ) & 15;
598	597	}
599	598	}
600	599
601	600	return data;
602	601	}
603	602
604		READ8_HANDLER ( msx_psg_port_b_r )
	603	READ8_MEMBER(msx_state::msx_psg_port_b_r)
605	604	{
606		msx_state *state = space->machine().driver_data<msx_state>();
607		return state->m_psg_b;
	605	return m_psg_b;
608	606	}
609	607
610		WRITE8_HANDLER ( msx_psg_port_a_w )
	608	WRITE8_MEMBER(msx_state::msx_psg_port_a_w)
611	609	{
612	610	}
613	611
614		WRITE8_HANDLER ( msx_psg_port_b_w )
	612	WRITE8_MEMBER(msx_state::msx_psg_port_b_w)
615	613	{
616		msx_state *state = space->machine().driver_data<msx_state>();
617	614	/* Arabic or kana mode led */
618		if ( (data ^ state->m_psg_b) & 0x80)
619		set_led_status (space->machine(), 2, !(data & 0x80) );
	615	if ( (data ^ m_psg_b) & 0x80)
	616	set_led_status (machine(), 2, !(data & 0x80) );
620	617
621		if ( (state->m_psg_b ^ data) & 0x10)
	618	if ( (m_psg_b ^ data) & 0x10)
622	619	{
623		if (++state->m_mouse_stat[0] > 3) state->m_mouse_stat[0] = -1;
	620	if (++m_mouse_stat[0] > 3) m_mouse_stat[0] = -1;
624	621	}
625		if ( (state->m_psg_b ^ data) & 0x20)
	622	if ( (m_psg_b ^ data) & 0x20)
626	623	{
627		if (++state->m_mouse_stat[1] > 3) state->m_mouse_stat[1] = -1;
	624	if (++m_mouse_stat[1] > 3) m_mouse_stat[1] = -1;
628	625	}
629	626
630		state->m_psg_b = data;
	627	m_psg_b = data;
631	628	}
632	629
633	630	WRITE8_DEVICE_HANDLER( msx_printer_strobe_w )

src/mess/machine/mz700.c

r14963	r14964
114	114	mz->m_ppi = machine.device<i8255_device>("ppi8255");
115	115
116	116	/* reset memory map to defaults */
117		mz700_bank_4_w(machine.device("maincpu")->memory().space(AS_PROGRAM), 0, 0);
	117	mz->mz700_bank_4_w(*machine.device("maincpu")->memory().space(AS_PROGRAM), 0, 0);
118	118	}
119	119
120	120
r14963	r14964
122	122	MMIO
123	123	***************************************************************************/
124	124
125		static READ8_HANDLER( mz700_e008_r )
	125	READ8_MEMBER(mz_state::mz700_e008_r)
126	126	{
127		mz_state *mz = space->machine().driver_data<mz_state>();
128	127	UINT8 data = 0;
129	128
130		data |= mz->m_other_timer;
131		data |= input_port_read(space->machine(), "JOY");
132		data |= space->machine().primary_screen->hblank() << 7;
	129	data |= m_other_timer;
	130	data |= input_port_read(machine(), "JOY");
	131	data |= machine().primary_screen->hblank() << 7;
133	132
134		LOG(1, "mz700_e008_r", ("%02X\n", data), space->machine());
	133	LOG(1, "mz700_e008_r", ("%02X\n", data), machine());
135	134
136	135	return data;
137	136	}
138	137
139		static WRITE8_HANDLER( mz700_e008_w )
	138	WRITE8_MEMBER(mz_state::mz700_e008_w)
140	139	{
141		mz_state *mz = space->machine().driver_data<mz_state>();
142		pit8253_gate0_w(mz->m_pit, BIT(data, 0));
	140	pit8253_gate0_w(m_pit, BIT(data, 0));
143	141	}
144	142
145	143
r14963	r14964
147	145	BANK SWITCHING
148	146	***************************************************************************/
149	147
150		READ8_HANDLER( mz800_bank_0_r )
	148	READ8_MEMBER(mz_state::mz800_bank_0_r)
151	149	{
152		mz_state *state = space->machine().driver_data<mz_state>();
153		UINT8 *videoram = state->m_videoram;
154		address_space *spc = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
155		mz_state *mz = space->machine().driver_data<mz_state>();
	150	UINT8 *videoram = m_videoram;
	151	address_space *spc = machine().device("maincpu")->memory().space(AS_PROGRAM);
156	152
157	153	/* switch in cgrom */
158	154	spc->install_read_bank(0x1000, 0x1fff, "bank2");
159	155	spc->nop_write(0x1000, 0x1fff);
160		memory_set_bankptr(space->machine(), "bank2", space->machine().region("monitor")->base() + 0x1000);
	156	memory_set_bankptr(machine(), "bank2", machine().region("monitor")->base() + 0x1000);
161	157
162		if (mz->m_mz700_mode)
	158	if (m_mz700_mode)
163	159	{
164	160	/* cgram from 0xc000 to 0xcfff */
165	161	spc->install_read_bank(0xc000, 0xcfff, "bank6");
166		spc->install_legacy_write_handler(0xc000, 0xcfff, FUNC(mz800_cgram_w));
167		memory_set_bankptr(space->machine(), "bank6", mz->m_cgram);
	162	spc->install_write_handler(0xc000, 0xcfff, write8_delegate(FUNC(mz_state::mz800_cgram_w),this));
	163	memory_set_bankptr(machine(), "bank6", m_cgram);
168	164	}
169	165	else
170	166	{
171		if (mz->m_hires_mode)
	167	if (m_hires_mode)
172	168	{
173	169	/* vram from 0x8000 to 0xbfff */
174	170	spc->install_readwrite_bank(0x8000, 0xbfff, "bank4");
175		memory_set_bankptr(space->machine(), "bank4", videoram);
	171	memory_set_bankptr(machine(), "bank4", videoram);
176	172	}
177	173	else
178	174	{
179	175	/* vram from 0x8000 to 0x9fff */
180	176	spc->install_readwrite_bank(0x8000, 0x9fff, "bank4");
181		memory_set_bankptr(space->machine(), "bank4", videoram);
	177	memory_set_bankptr(machine(), "bank4", videoram);
182	178
183	179	/* ram from 0xa000 to 0xbfff */
184	180	spc->install_readwrite_bank(0xa000, 0xbfff, "bank5");
185		memory_set_bankptr(space->machine(), "bank5", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0xa000);
	181	memory_set_bankptr(machine(), "bank5", machine().device<ram_device>(RAM_TAG)->pointer() + 0xa000);
186	182	}
187	183	}
188	184
189	185	return 0xff;
190	186	}
191	187
192		WRITE8_HANDLER( mz700_bank_0_w )
	188	WRITE8_MEMBER(mz_state::mz700_bank_0_w)
193	189	{
194		address_space *spc = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
	190	address_space *spc = machine().device("maincpu")->memory().space(AS_PROGRAM);
195	191
196	192	spc->install_readwrite_bank(0x0000, 0x0fff, "bank1");
197		memory_set_bankptr(space->machine(), "bank1", space->machine().device<ram_device>(RAM_TAG)->pointer());
	193	memory_set_bankptr(machine(), "bank1", machine().device<ram_device>(RAM_TAG)->pointer());
198	194	}
199	195
200		WRITE8_HANDLER( mz800_bank_0_w )
	196	WRITE8_MEMBER(mz_state::mz800_bank_0_w)
201	197	{
202		address_space *spc = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
	198	address_space *spc = machine().device("maincpu")->memory().space(AS_PROGRAM);
203	199
204	200	spc->install_readwrite_bank(0x0000, 0x7fff, "bank1");
205		memory_set_bankptr(space->machine(), "bank1", space->machine().device<ram_device>(RAM_TAG)->pointer());
	201	memory_set_bankptr(machine(), "bank1", machine().device<ram_device>(RAM_TAG)->pointer());
206	202	}
207	203
208		READ8_HANDLER( mz800_bank_1_r )
	204	READ8_MEMBER(mz_state::mz800_bank_1_r)
209	205	{
210		address_space *spc = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
211		mz_state *mz = space->machine().driver_data<mz_state>();
	206	address_space *spc = machine().device("maincpu")->memory().space(AS_PROGRAM);
212	207
213	208	/* switch in ram from 0x1000 to 0x1fff */
214	209	spc->install_readwrite_bank(0x1000, 0x1fff, "bank2");
215		memory_set_bankptr(space->machine(), "bank2", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0x1000);
	210	memory_set_bankptr(machine(), "bank2", machine().device<ram_device>(RAM_TAG)->pointer() + 0x1000);
216	211
217		if (mz->m_mz700_mode)
	212	if (m_mz700_mode)
218	213	{
219	214	/* ram from 0xc000 to 0xcfff */
220	215	spc->install_readwrite_bank(0xc000, 0xcfff, "bank6");
221		memory_set_bankptr(space->machine(), "bank6", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0xc000);
	216	memory_set_bankptr(machine(), "bank6", machine().device<ram_device>(RAM_TAG)->pointer() + 0xc000);
222	217	}
223	218	else
224	219	{
225	220	/* ram from 0x8000 to 0xbfff */
226	221	spc->install_readwrite_bank(0x8000, 0xbfff, "bank4");
227		memory_set_bankptr(space->machine(), "bank4", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0x8000);
	222	memory_set_bankptr(machine(), "bank4", machine().device<ram_device>(RAM_TAG)->pointer() + 0x8000);
228	223	}
229	224
230	225	return 0xff;
231	226	}
232	227
233		WRITE8_HANDLER( mz700_bank_1_w )
	228	WRITE8_MEMBER(mz_state::mz700_bank_1_w)
234	229	{
235		address_space *spc = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
236		mz_state *mz = space->machine().driver_data<mz_state>();
	230	address_space *spc = machine().device("maincpu")->memory().space(AS_PROGRAM);
237	231
238		if (mz->m_mz700_mode)
	232	if (m_mz700_mode)
239	233	{
240	234	/* switch in ram when not locked */
241		if (!mz->m_mz700_ram_lock)
	235	if (!m_mz700_ram_lock)
242	236	{
243	237	spc->install_readwrite_bank(0xd000, 0xffff, "bank7");
244		memory_set_bankptr(space->machine(), "bank7", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0xd000);
245		mz->m_mz700_ram_vram = FALSE;
	238	memory_set_bankptr(machine(), "bank7", machine().device<ram_device>(RAM_TAG)->pointer() + 0xd000);
	239	m_mz700_ram_vram = FALSE;
246	240	}
247	241	}
248	242	else
249	243	{
250	244	/* switch in ram when not locked */
251		if (!mz->m_mz800_ram_lock)
	245	if (!m_mz800_ram_lock)
252	246	{
253	247	spc->install_readwrite_bank(0xe000, 0xffff, "bank8");
254		memory_set_bankptr(space->machine(), "bank8", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0xe000);
255		mz->m_mz800_ram_monitor = FALSE;
	248	memory_set_bankptr(machine(), "bank8", machine().device<ram_device>(RAM_TAG)->pointer() + 0xe000);
	249	m_mz800_ram_monitor = FALSE;
256	250	}
257	251	}
258	252	}
259	253
260		WRITE8_HANDLER( mz700_bank_2_w )
	254	WRITE8_MEMBER(mz_state::mz700_bank_2_w)
261	255	{
262		address_space *spc = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
	256	address_space *spc = machine().device("maincpu")->memory().space(AS_PROGRAM);
263	257
264	258	spc->install_read_bank(0x0000, 0x0fff, "bank1");
265	259	spc->nop_write(0x0000, 0x0fff);
266		memory_set_bankptr(space->machine(), "bank1", space->machine().region("monitor")->base());
	260	memory_set_bankptr(machine(), "bank1", machine().region("monitor")->base());
267	261	}
268	262
269		WRITE8_HANDLER( mz700_bank_3_w )
	263	WRITE8_MEMBER(mz_state::mz700_bank_3_w)
270	264	{
271		mz_state *state = space->machine().driver_data<mz_state>();
272		UINT8 *videoram = state->m_videoram;
273		address_space *spc = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
274		mz_state *mz = space->machine().driver_data<mz_state>();
	265	UINT8 *videoram = m_videoram;
	266	address_space *spc = machine().device("maincpu")->memory().space(AS_PROGRAM);
275	267
276		if (mz->m_mz700_mode)
	268	if (m_mz700_mode)
277	269	{
278		if (!mz->m_mz700_ram_lock)
	270	if (!m_mz700_ram_lock)
279	271	{
280	272	/* switch in videoram */
281	273	spc->install_readwrite_bank(0xd000, 0xd7ff, "bank7");
282		memory_set_bankptr(space->machine(), "bank7", videoram);
	274	memory_set_bankptr(machine(), "bank7", videoram);
283	275
284	276	/* switch in colorram */
285	277	spc->install_readwrite_bank(0xd800, 0xdfff, "bank9");
286		memory_set_bankptr(space->machine(), "bank9", mz->m_colorram);
	278	memory_set_bankptr(machine(), "bank9", m_colorram);
287	279
288		mz->m_mz700_ram_vram = TRUE;
	280	m_mz700_ram_vram = TRUE;
289	281
290	282	/* switch in memory mapped i/o devices */
291		if (mz->m_mz700)
	283	if (m_mz700)
292	284	{
293		spc->install_readwrite_handler(0xe000, 0xfff3, 0, 0x1ff0, read8_delegate(FUNC(i8255_device::read), (i8255_device*)mz->m_ppi), write8_delegate(FUNC(i8255_device::write), (i8255_device*)mz->m_ppi));
294		spc->install_legacy_readwrite_handler(*mz->m_pit, 0xe004, 0xfff7, 0, 0x1ff0, FUNC(pit8253_r), FUNC(pit8253_w));
295		spc->install_legacy_readwrite_handler(0xe008, 0xfff8, 0, 0x1ff0, FUNC(mz700_e008_r), FUNC(mz700_e008_w));
	285	spc->install_readwrite_handler(0xe000, 0xfff3, 0, 0x1ff0, read8_delegate(FUNC(i8255_device::read), (i8255_device*)m_ppi), write8_delegate(FUNC(i8255_device::write), (i8255_device*)m_ppi));
	286	spc->install_legacy_readwrite_handler(*m_pit, 0xe004, 0xfff7, 0, 0x1ff0, FUNC(pit8253_r), FUNC(pit8253_w));
	287	spc->install_readwrite_handler(0xe008, 0xfff8, 0, 0x1ff0, read8_delegate(FUNC(mz_state::mz700_e008_r),this), write8_delegate(FUNC(mz_state::mz700_e008_w),this));
296	288	}
297	289	else
298	290	{
299		spc->install_readwrite_handler(0xe000, 0xe003, read8_delegate(FUNC(i8255_device::read), (i8255_device*)mz->m_ppi), write8_delegate(FUNC(i8255_device::write), (i8255_device*)mz->m_ppi));
300		spc->install_legacy_readwrite_handler(*mz->m_pit, 0xe004, 0xe007, FUNC(pit8253_r), FUNC(pit8253_w));
301		spc->install_legacy_readwrite_handler(0xe008, 0xe008, FUNC(mz700_e008_r), FUNC(mz700_e008_w));
	291	spc->install_readwrite_handler(0xe000, 0xe003, read8_delegate(FUNC(i8255_device::read), (i8255_device*)m_ppi), write8_delegate(FUNC(i8255_device::write), (i8255_device*)m_ppi));
	292	spc->install_legacy_readwrite_handler(*m_pit, 0xe004, 0xe007, FUNC(pit8253_r), FUNC(pit8253_w));
	293	spc->install_readwrite_handler(0xe008, 0xe008, read8_delegate(FUNC(mz_state::mz700_e008_r),this), write8_delegate(FUNC(mz_state::mz700_e008_w),this));
302	294	}
303	295	}
304	296	}
305	297	else
306	298	{
307		if (!mz->m_mz800_ram_lock)
	299	if (!m_mz800_ram_lock)
308	300	{
309	301	/* switch in mz800 monitor rom if not locked */
310	302	spc->install_read_bank(0xe000, 0xffff, "bank8");
311	303	spc->nop_write(0xe000, 0xffff);
312		memory_set_bankptr(space->machine(), "bank8", space->machine().region("monitor")->base() + 0x2000);
313		mz->m_mz800_ram_monitor = TRUE;
	304	memory_set_bankptr(machine(), "bank8", machine().region("monitor")->base() + 0x2000);
	305	m_mz800_ram_monitor = TRUE;
314	306	}
315	307	}
316	308	}
317	309
318		WRITE8_HANDLER( mz700_bank_4_w )
	310	WRITE8_MEMBER(mz_state::mz700_bank_4_w)
319	311	{
320		mz_state *state = space->machine().driver_data<mz_state>();
321		UINT8 *videoram = state->m_videoram;
322		address_space *spc = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
323		mz_state *mz = space->machine().driver_data<mz_state>();
	312	UINT8 *videoram = m_videoram;
	313	address_space *spc = machine().device("maincpu")->memory().space(AS_PROGRAM);
324	314
325		if (mz->m_mz700_mode)
	315	if (m_mz700_mode)
326	316	{
327		mz->m_mz700_ram_lock = FALSE;      /* reset lock */
	317	m_mz700_ram_lock = FALSE;      /* reset lock */
328	318	mz700_bank_2_w(space, 0, 0);   /* switch in monitor rom */
329	319	mz700_bank_3_w(space, 0, 0);   /* switch in videoram, colorram, and mmio */
330	320
331	321	/* rest is ram is always ram in mz700 mode */
332	322	spc->install_readwrite_bank(0x1000, 0xcfff, "bank2");
333		memory_set_bankptr(space->machine(), "bank2", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0x1000);
	323	memory_set_bankptr(machine(), "bank2", machine().device<ram_device>(RAM_TAG)->pointer() + 0x1000);
334	324	}
335	325	else
336	326	{
337	327	/* monitor rom and cgrom */
338	328	spc->install_read_bank(0x0000, 0x1fff, "bank1");
339	329	spc->nop_write(0x0000, 0x1fff);
340		memory_set_bankptr(space->machine(), "bank1", space->machine().region("monitor")->base());
	330	memory_set_bankptr(machine(), "bank1", machine().region("monitor")->base());
341	331
342	332	/* ram from 0x2000 to 0x7fff */
343	333	spc->install_readwrite_bank(0x2000, 0x7fff, "bank3");
344		memory_set_bankptr(space->machine(), "bank3", space->machine().device<ram_device>(RAM_TAG)->pointer());
	334	memory_set_bankptr(machine(), "bank3", machine().device<ram_device>(RAM_TAG)->pointer());
345	335
346		if (mz->m_hires_mode)
	336	if (m_hires_mode)
347	337	{
348	338	/* vram from 0x8000 to 0xbfff */
349	339	spc->install_readwrite_bank(0x8000, 0xbfff, "bank4");
350		memory_set_bankptr(space->machine(), "bank4", videoram);
	340	memory_set_bankptr(machine(), "bank4", videoram);
351	341	}
352	342	else
353	343	{
354	344	/* vram from 0x8000 to 0x9fff */
355	345	spc->install_readwrite_bank(0x8000, 0x9fff, "bank4");
356		memory_set_bankptr(space->machine(), "bank4", videoram);
	346	memory_set_bankptr(machine(), "bank4", videoram);
357	347
358	348	/* ram from 0xa000 to 0xbfff */
359	349	spc->install_readwrite_bank(0xa000, 0xbfff, "bank5");
360		memory_set_bankptr(space->machine(), "bank5", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0xa000);
	350	memory_set_bankptr(machine(), "bank5", machine().device<ram_device>(RAM_TAG)->pointer() + 0xa000);
361	351	}
362	352
363	353	/* ram from 0xc000 to 0xdfff */
364	354	spc->install_readwrite_bank(0xc000, 0xdfff, "bank6");
365		memory_set_bankptr(space->machine(), "bank6", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0xc000);
	355	memory_set_bankptr(machine(), "bank6", machine().device<ram_device>(RAM_TAG)->pointer() + 0xc000);
366	356
367	357	/* mz800 monitor rom from 0xe000 to 0xffff */
368	358	spc->install_read_bank(0xe000, 0xffff, "bank8");
369	359	spc->nop_write(0xe000, 0xffff);
370		memory_set_bankptr(space->machine(), "bank8", space->machine().region("monitor")->base() + 0x2000);
371		mz->m_mz800_ram_monitor = TRUE;
	360	memory_set_bankptr(machine(), "bank8", machine().region("monitor")->base() + 0x2000);
	361	m_mz800_ram_monitor = TRUE;
372	362
373		mz->m_mz800_ram_lock = FALSE; /* reset lock? */
	363	m_mz800_ram_lock = FALSE; /* reset lock? */
374	364	}
375	365	}
376	366
377		WRITE8_HANDLER( mz700_bank_5_w )
	367	WRITE8_MEMBER(mz_state::mz700_bank_5_w)
378	368	{
379		address_space *spc = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
380		mz_state *mz = space->machine().driver_data<mz_state>();
	369	address_space *spc = machine().device("maincpu")->memory().space(AS_PROGRAM);
381	370
382		if (mz->m_mz700_mode)
	371	if (m_mz700_mode)
383	372	{
384	373	/* prevent access from 0xd000 to 0xffff */
385		mz->m_mz700_ram_lock = TRUE;
	374	m_mz700_ram_lock = TRUE;
386	375	spc->nop_readwrite(0xd000, 0xffff);
387	376	}
388	377	else
389	378	{
390	379	/* prevent access from 0xe000 to 0xffff */
391		mz->m_mz800_ram_lock = TRUE;
	380	m_mz800_ram_lock = TRUE;
392	381	spc->nop_readwrite(0xe000, 0xffff);
393	382	}
394	383	}
395	384
396		WRITE8_HANDLER( mz700_bank_6_w )
	385	WRITE8_MEMBER(mz_state::mz700_bank_6_w)
397	386	{
398		mz_state *mz = space->machine().driver_data<mz_state>();
399	387
400		if (mz->m_mz700_mode)
	388	if (m_mz700_mode)
401	389	{
402		mz->m_mz700_ram_lock = FALSE;
	390	m_mz700_ram_lock = FALSE;
403	391
404	392	/* restore access */
405		if (mz->m_mz700_ram_vram)
	393	if (m_mz700_ram_vram)
406	394	mz700_bank_3_w(space, 0, 0);
407	395	else
408	396	mz700_bank_1_w(space, 0, 0);
409	397	}
410	398	else
411	399	{
412		mz->m_mz800_ram_lock = FALSE;
	400	m_mz800_ram_lock = FALSE;
413	401
414	402	/* restore access from 0xe000 to 0xffff */
415		if (mz->m_mz800_ram_monitor)
	403	if (m_mz800_ram_monitor)
416	404	mz700_bank_3_w(space, 0, 0);
417	405	else
418	406	mz700_bank_1_w(space, 0, 0);
r14963	r14964
601	589
602	590
603	591	/* port CE */
604		READ8_HANDLER( mz800_crtc_r )
	592	READ8_MEMBER(mz_state::mz800_crtc_r)
605	593	{
606	594	UINT8 data = 0x00;
607		LOG(1,"mz800_crtc_r",("%02X\n",data),space->machine());
	595	LOG(1,"mz800_crtc_r",("%02X\n",data),machine());
608	596	return data;
609	597	}
610	598
611	599
612	600	/* port EA */
613		READ8_HANDLER( mz800_ramdisk_r )
	601	READ8_MEMBER(mz_state::mz800_ramdisk_r)
614	602	{
615		mz_state *state = space->machine().driver_data<mz_state>();
616		UINT8 *mem = space->machine().region("user1")->base();
617		UINT8 data = mem[state->m_mz800_ramaddr];
618		LOG(2,"mz800_ramdisk_r",("[%04X] -> %02X\n", state->m_mz800_ramaddr, data),space->machine());
619		if (state->m_mz800_ramaddr++ == 0)
620		LOG(1,"mz800_ramdisk_r",("address wrap 0000\n"),space->machine());
	603	UINT8 *mem = space.machine().region("user1")->base();
	604	UINT8 data = mem[m_mz800_ramaddr];
	605	LOG(2,"mz800_ramdisk_r",("[%04X] -> %02X\n", m_mz800_ramaddr, data),machine());
	606	if (m_mz800_ramaddr++ == 0)
	607	LOG(1,"mz800_ramdisk_r",("address wrap 0000\n"),machine());
621	608	return data;
622	609	}
623	610
624	611	/* port CC */
625		WRITE8_HANDLER( mz800_write_format_w )
	612	WRITE8_MEMBER(mz_state::mz800_write_format_w)
626	613	{
627		LOG(1,"mz800_write_format_w",("%02X\n", data),space->machine());
	614	LOG(1,"mz800_write_format_w",("%02X\n", data),machine());
628	615	}
629	616
630	617	/* port CD */
631		WRITE8_HANDLER( mz800_read_format_w )
	618	WRITE8_MEMBER(mz_state::mz800_read_format_w)
632	619	{
633		LOG(1,"mz800_read_format_w",("%02X\n", data),space->machine());
	620	LOG(1,"mz800_read_format_w",("%02X\n", data),machine());
634	621	}
635	622
636	623	/* port CE
r14963	r14964
639	626	* bit 1    1: 4bpp/2bpp        0: 2bpp/1bpp
640	627	* bit 0    ???
641	628	*/
642		WRITE8_HANDLER( mz800_display_mode_w )
	629	WRITE8_MEMBER(mz_state::mz800_display_mode_w)
643	630	{
644		mz_state *mz = space->machine().driver_data<mz_state>();
645	631
646		mz->m_mz700_mode = BIT(data, 3);
647		mz->m_hires_mode = BIT(data, 2);
648		mz->m_screen = data & 0x03;
	632	m_mz700_mode = BIT(data, 3);
	633	m_hires_mode = BIT(data, 2);
	634	m_screen = data & 0x03;
649	635
650	636	/* change memory maps if we switched mode */
651		//  if (BIT(data, 3) != mz->m_mz700_mode)
	637	//  if (BIT(data, 3) != m_mz700_mode)
652	638	//  {
653	639	//      logerror("mz800_display_mode_w: switching mode to %s\n", (BIT(data, 3) ? "mz700" : "mz800"));
654		//      mz->m_mz700_mode = BIT(data, 3);
655		//      mz700_bank_4_w(space->machine().device("maincpu")->memory().space(AS_PROGRAM), 0, 0);
	640	//      m_mz700_mode = BIT(data, 3);
	641	//      mz700_bank_4_w(machine().device("maincpu")->memory().&space(AS_PROGRAM), 0, 0);
656	642	//  }
657	643	}
658	644
659	645	/* port CF */
660		WRITE8_HANDLER( mz800_scroll_border_w )
	646	WRITE8_MEMBER(mz_state::mz800_scroll_border_w)
661	647	{
662		LOG(1,"mz800_scroll_border_w",("%02X\n", data),space->machine());
	648	LOG(1,"mz800_scroll_border_w",("%02X\n", data),machine());
663	649	}
664	650
665	651	/* port EA */
666		WRITE8_HANDLER( mz800_ramdisk_w )
	652	WRITE8_MEMBER(mz_state::mz800_ramdisk_w)
667	653	{
668		mz_state *state = space->machine().driver_data<mz_state>();
669		UINT8 *mem = space->machine().region("user1")->base();
670		LOG(2,"mz800_ramdisk_w",("[%04X] <- %02X\n", state->m_mz800_ramaddr, data),space->machine());
671		mem[state->m_mz800_ramaddr] = data;
672		if (state->m_mz800_ramaddr++ == 0)
673		LOG(1,"mz800_ramdisk_w",("address wrap 0000\n"),space->machine());
	654	UINT8 *mem = machine().region("user1")->base();
	655	LOG(2,"mz800_ramdisk_w",("[%04X] <- %02X\n", m_mz800_ramaddr, data),machine());
	656	mem[m_mz800_ramaddr] = data;
	657	if (m_mz800_ramaddr++ == 0)
	658	LOG(1,"mz800_ramdisk_w",("address wrap 0000\n"),machine());
674	659	}
675	660
676	661	/* port EB */
677		WRITE8_HANDLER( mz800_ramaddr_w )
	662	WRITE8_MEMBER(mz_state::mz800_ramaddr_w)
678	663	{
679		mz_state *state = space->machine().driver_data<mz_state>();
680		state->m_mz800_ramaddr = (cpu_get_reg(space->machine().device("maincpu"), Z80_BC) & 0xff00) | (data & 0xff);
681		LOG(1,"mz800_ramaddr_w",("%04X\n", state->m_mz800_ramaddr),space->machine());
	664	m_mz800_ramaddr = (cpu_get_reg(machine().device("maincpu"), Z80_BC) & 0xff00) | (data & 0xff);
	665	LOG(1,"mz800_ramaddr_w",("%04X\n", m_mz800_ramaddr),machine());
682	666	}
683	667
684	668	/* port F0 */
685		WRITE8_HANDLER( mz800_palette_w )
	669	WRITE8_MEMBER(mz_state::mz800_palette_w)
686	670	{
687		mz_state *state = space->machine().driver_data<mz_state>();
688	671	if (data & 0x40)
689	672	{
690		state->m_mz800_palette_bank = data & 3;
691		LOG(1,"mz800_palette_w",("bank: %d\n", state->m_mz800_palette_bank),space->machine());
	673	m_mz800_palette_bank = data & 3;
	674	LOG(1,"mz800_palette_w",("bank: %d\n", m_mz800_palette_bank),machine());
692	675	}
693	676	else
694	677	{
695	678	int idx = (data >> 4) & 3;
696	679	int val = data & 15;
697		LOG(1,"mz800_palette_w",("palette[%d] <- %d\n", idx, val),space->machine());
698		state->m_mz800_palette[idx] = val;
	680	LOG(1,"mz800_palette_w",("palette[%d] <- %d\n", idx, val),machine());
	681	m_mz800_palette[idx] = val;
699	682	}
700	683	}

src/mess/machine/lisa.c

r14963	r14964
147	147	protos
148	148	*/
149	149
150		static READ16_HANDLER ( lisa_IO_r );
151		static WRITE16_HANDLER ( lisa_IO_w );
152	150
153	151
	152
	153
154	154	/*
155	155	Interrupt handling
156	156	*/
r14963	r14964
1260	1260	}
1261	1261	}
1262	1262
1263		READ8_HANDLER ( lisa_fdc_io_r )
	1263	READ8_MEMBER(lisa_state::lisa_fdc_io_r)
1264	1264	{
1265	1265	int answer=0;
1266		device_t *fdc = space->machine().device("fdc");
	1266	device_t *fdc = machine().device("fdc");
1267	1267
1268	1268	switch ((offset & 0x0030) >> 4)
1269	1269	{
r14963	r14964
1272	1272	break;
1273	1273
1274	1274	case 1:   /* TTL glue */
1275		lisa_fdc_ttl_glue_access(space->machine(), offset);
	1275	lisa_fdc_ttl_glue_access(machine(), offset);
1276	1276	answer = 0;   /* ??? */
1277	1277	break;
1278	1278
r14963	r14964
1288	1288	return answer;
1289	1289	}
1290	1290
1291		WRITE8_HANDLER ( lisa_fdc_io_w )
	1291	WRITE8_MEMBER(lisa_state::lisa_fdc_io_w)
1292	1292	{
1293		lisa_state *state = space->machine().driver_data<lisa_state>();
1294		device_t *fdc = space->machine().device("fdc");
	1293	device_t *fdc = machine().device("fdc");
1295	1294
1296	1295	switch ((offset & 0x0030) >> 4)
1297	1296	{
r14963	r14964
1300	1299	break;
1301	1300
1302	1301	case 1:   /* TTL glue */
1303		lisa_fdc_ttl_glue_access(space->machine(), offset);
	1302	lisa_fdc_ttl_glue_access(machine(), offset);
1304	1303	break;
1305	1304
1306	1305	case 2:   /* writes the PWM register */
1307	1306	/* the written value is used to generate the motor speed control signal */
1308	1307	#if 0
1309		if (state->m_features.floppy_hardware == twiggy)
	1308	if (m_features.floppy_hardware == twiggy)
1310	1309	twiggy_set_speed((256-data) * 1.3 /* ??? */ + 237 /* ??? */);
1311	1310	else
1312	1311	#endif
1313		if (state->m_features.floppy_hardware == sony_lisa210)
	1312	if (m_features.floppy_hardware == sony_lisa210)
1314	1313	sony_set_speed(((256-data) * 1.3) + 237);
1315	1314	break;
1316	1315
r14963	r14964
1319	1318	}
1320	1319	}
1321	1320
1322		READ8_HANDLER ( lisa_fdc_r )
	1321	READ8_MEMBER(lisa_state::lisa_fdc_r)
1323	1322	{
1324		lisa_state *state = space->machine().driver_data<lisa_state>();
1325	1323	if (! (offset & 0x1000))
1326	1324	{
1327	1325	if (! (offset & 0x0800))
1328	1326	if (! (offset & 0x0400))
1329		return state->m_fdc_ram[offset & 0x03ff];
	1327	return m_fdc_ram[offset & 0x03ff];
1330	1328	else
1331	1329	return lisa_fdc_io_r(space, offset & 0x03ff);
1332	1330	else
1333	1331	return 0;   /* ??? */
1334	1332	}
1335	1333	else
1336		return state->m_fdc_rom[offset & 0x0fff];
	1334	return m_fdc_rom[offset & 0x0fff];
1337	1335	}
1338	1336
1339		READ8_HANDLER ( lisa210_fdc_r )
	1337	READ8_MEMBER(lisa_state::lisa210_fdc_r)
1340	1338	{
1341		lisa_state *state = space->machine().driver_data<lisa_state>();
1342	1339	if (! (offset & 0x1000))
1343	1340	{
1344	1341	if (! (offset & 0x0400))
1345	1342	if (! (offset & 0x0800))
1346		return state->m_fdc_ram[offset & 0x03ff];
	1343	return m_fdc_ram[offset & 0x03ff];
1347	1344	else
1348	1345	return lisa_fdc_io_r(space, offset & 0x03ff);
1349	1346	else
1350	1347	return 0;   /* ??? */
1351	1348	}
1352	1349	else
1353		return state->m_fdc_rom[offset & 0x0fff];
	1350	return m_fdc_rom[offset & 0x0fff];
1354	1351	}
1355	1352
1356		WRITE8_HANDLER ( lisa_fdc_w )
	1353	WRITE8_MEMBER(lisa_state::lisa_fdc_w)
1357	1354	{
1358		lisa_state *state = space->machine().driver_data<lisa_state>();
1359	1355	if (! (offset & 0x1000))
1360	1356	{
1361	1357	if (! (offset & 0x0800))
1362	1358	{
1363	1359	if (! (offset & 0x0400))
1364		state->m_fdc_ram[offset & 0x03ff] = data;
	1360	m_fdc_ram[offset & 0x03ff] = data;
1365	1361	else
1366	1362	lisa_fdc_io_w(space, offset & 0x03ff, data);
1367	1363	}
1368	1364	}
1369	1365	}
1370	1366
1371		WRITE8_HANDLER ( lisa210_fdc_w )
	1367	WRITE8_MEMBER(lisa_state::lisa210_fdc_w)
1372	1368	{
1373		lisa_state *state = space->machine().driver_data<lisa_state>();
1374	1369	if (! (offset & 0x1000))
1375	1370	{
1376	1371	if (! (offset & 0x0400))
1377	1372	{
1378	1373	if (! (offset & 0x0800))
1379		state->m_fdc_ram[offset & 0x03ff] = data;
	1374	m_fdc_ram[offset & 0x03ff] = data;
1380	1375	else
1381	1376	lisa_fdc_io_w(space, offset & 0x03ff, data);
1382	1377	}
1383	1378	}
1384	1379	}
1385	1380
1386		READ16_HANDLER ( lisa_r )
	1381	READ16_MEMBER(lisa_state::lisa_r)
1387	1382	{
1388		lisa_state *state = space->machine().driver_data<lisa_state>();
1389	1383	int answer=0;
1390	1384
1391	1385	/* segment register set */
1392		int the_seg = state->m_seg;
	1386	int the_seg = m_seg;
1393	1387
1394	1388	/* upper 7 bits -> segment # */
1395	1389	int segment = (offset >> 16) & 0x7f;
1396	1390
1397	1391	/*logerror("read, logical address%lX\n", offset);*/
1398	1392
1399		if (state->m_setup)
	1393	if (m_setup)
1400	1394	{   /* special setup mode */
1401	1395	if (offset & 0x002000)
1402	1396	{
r14963	r14964
1409	1403	/*logerror("read from segment registers (%X:%X) ", the_seg, segment);*/
1410	1404	if (offset & 0x000004)
1411	1405	{   /* sorg register */
1412		answer = state->m_real_mmu_regs[the_seg][segment].sorg;
	1406	answer = m_real_mmu_regs[the_seg][segment].sorg;
1413	1407	/*logerror("sorg, data = %X\n", answer);*/
1414	1408	}
1415	1409	else
1416	1410	{   /* slim register */
1417		answer = state->m_real_mmu_regs[the_seg][segment].slim;
	1411	answer = m_real_mmu_regs[the_seg][segment].slim;
1418	1412	/*logerror("slim, data = %X\n", answer);*/
1419	1413	}
1420	1414	}
1421	1415	else
1422	1416	{   /* system ROMs */
1423		answer = ((UINT16*)state->m_rom_ptr)[(offset & 0x001fff)];
	1417	answer = ((UINT16*)m_rom_ptr)[(offset & 0x001fff)];
1424	1418	/*logerror("dst address in ROM (setup mode)\n");*/
1425	1419	}
1426	1420
r14963	r14964
1428	1422	}
1429	1423	}
1430	1424
1431		if (cpu_get_reg(space->machine().device("maincpu"), M68K_SR) & 0x2000)
	1425	if (cpu_get_reg(machine().device("maincpu"), M68K_SR) & 0x2000)
1432	1426	/* supervisor mode -> force register file 0 */
1433	1427	the_seg = 0;
1434	1428
r14963	r14964
1437	1431	int seg_offset = (offset & 0x00ffff) << 1;
1438	1432
1439	1433	/* add revelant origin -> address */
1440		offs_t address = (state->m_mmu_regs[the_seg][segment].sorg + seg_offset) & 0x1fffff;
	1434	offs_t address = (m_mmu_regs[the_seg][segment].sorg + seg_offset) & 0x1fffff;
1441	1435
1442	1436	/*logerror("read, logical address%lX\n", offset);
1443	1437	logerror("physical address%lX\n", address);*/
1444	1438
1445		switch (state->m_mmu_regs[the_seg][segment].type)
	1439	switch (m_mmu_regs[the_seg][segment].type)
1446	1440	{
1447	1441
1448	1442	case RAM_stack_r:
1449	1443	case RAM_stack_rw:
1450		if (address <= state->m_mmu_regs[the_seg][segment].slim)
	1444	if (address <= m_mmu_regs[the_seg][segment].slim)
1451	1445	{
1452	1446	/* out of segment limits : bus error */
1453	1447
1454	1448	}
1455		answer = *(UINT16 *)(state->m_ram_ptr + address);
	1449	answer = *(UINT16 *)(m_ram_ptr + address);
1456	1450
1457		if (state->m_bad_parity_count && state->m_test_parity
1458		&& (state->m_bad_parity_table[address >> 3] & (0x3 << (address & 0x7))))
	1451	if (m_bad_parity_count && m_test_parity
	1452	&& (m_bad_parity_table[address >> 3] & (0x3 << (address & 0x7))))
1459	1453	{
1460		state->m_mem_err_addr_latch = address >> 5;
1461		set_parity_error_pending(space->machine(), 1);
	1454	m_mem_err_addr_latch = address >> 5;
	1455	set_parity_error_pending(machine(), 1);
1462	1456	}
1463	1457
1464	1458	break;
1465	1459
1466	1460	case RAM_r:
1467	1461	case RAM_rw:
1468		if (address > state->m_mmu_regs[the_seg][segment].slim)
	1462	if (address > m_mmu_regs[the_seg][segment].slim)
1469	1463	{
1470	1464	/* out of segment limits : bus error */
1471	1465
1472	1466	}
1473		answer = *(UINT16 *)(state->m_ram_ptr + address);
	1467	answer = *(UINT16 *)(m_ram_ptr + address);
1474	1468
1475		if (state->m_bad_parity_count && state->m_test_parity
1476		&& (state->m_bad_parity_table[address >> 3] & (0x3 << (address & 0x7))))
	1469	if (m_bad_parity_count && m_test_parity
	1470	&& (m_bad_parity_table[address >> 3] & (0x3 << (address & 0x7))))
1477	1471	{
1478		state->m_mem_err_addr_latch = address >> 5;
1479		set_parity_error_pending(space->machine(), 1);
	1472	m_mem_err_addr_latch = address >> 5;
	1473	set_parity_error_pending(machine(), 1);
1480	1474	}
1481	1475
1482	1476	break;
r14963	r14964
1495	1489
1496	1490	case special_IO:
1497	1491	if (! (address & 0x008000))
1498		answer = *(UINT16 *)(state->m_rom_ptr + (address & 0x003fff));
	1492	answer = *(UINT16 *)(m_rom_ptr + (address & 0x003fff));
1499	1493	else
1500	1494	{   /* read serial number from ROM */
1501	1495	/* this has to be be the least efficient way to read a ROM :-) */
r14963	r14964
1504	1498	/* problem : due to collisions with video, timings of the LISA CPU
1505	1499	are slightly different from timings of a bare 68k */
1506	1500	/* so we use a kludge... */
1507		int time_in_frame = space->machine().primary_screen->vpos();
	1501	int time_in_frame = machine().primary_screen->vpos();
1508	1502
1509	1503	/* the BOOT ROM only reads 56 bits, so there must be some wrap-around for
1510	1504	videoROM_address <= 56 */
r14963	r14964
1519	1513	there are no additionnal margins).
1520	1514	This is caused by the fact that 68k timings are wrong (memory accesses are
1521	1515	interlaced with the video hardware, which is not emulated). */
1522		if (state->m_features.has_mac_xl_video)
	1516	if (m_features.has_mac_xl_video)
1523	1517	{
1524	1518	if ((time_in_frame >= 374) && (time_in_frame <= 392))   /* these values have not been tested */
1525		answer = state->m_videoROM_ptr[state->m_videoROM_address|0x80] << 8;
	1519	answer = m_videoROM_ptr[m_videoROM_address|0x80] << 8;
1526	1520	else
1527		answer = state->m_videoROM_ptr[state->m_videoROM_address] << 8;
	1521	answer = m_videoROM_ptr[m_videoROM_address] << 8;
1528	1522	}
1529	1523	else
1530	1524	{
1531	1525	if ((time_in_frame >= 364) && (time_in_frame <= 375))
1532	1526	{
1533		answer = state->m_videoROM_ptr[state->m_videoROM_address|0x80] << 8;
1534		logerror("reading1 %06X=%04x PC=%06x time=%d\n", address, answer, cpu_get_pc(space->machine().device("maincpu")), time_in_frame);
	1527	answer = m_videoROM_ptr[m_videoROM_address|0x80] << 8;
	1528	logerror("reading1 %06X=%04x PC=%06x time=%d\n", address, answer, cpu_get_pc(machine().device("maincpu")), time_in_frame);
1535	1529	}
1536	1530	else
1537	1531	{
1538		answer = state->m_videoROM_ptr[state->m_videoROM_address] << 8;
1539		logerror("reading2 %06X=%04x PC=%06x time=%d\n", address, answer, cpu_get_pc(space->machine().device("maincpu")), time_in_frame);
	1532	answer = m_videoROM_ptr[m_videoROM_address] << 8;
	1533	logerror("reading2 %06X=%04x PC=%06x time=%d\n", address, answer, cpu_get_pc(machine().device("maincpu")), time_in_frame);
1540	1534	}
1541	1535	}
1542	1536
1543	1537
1544		state->m_videoROM_address = (state->m_videoROM_address + 1) & 0x7f;
1545		if (state->m_videoROM_address == ((state->m_features.has_mac_xl_video) ? 48 : 56)) {
1546		logerror("loop %d\n", state->m_videoROM_address);
1547		state->m_videoROM_address = 0;
	1538	m_videoROM_address = (m_videoROM_address + 1) & 0x7f;
	1539	if (m_videoROM_address == ((m_features.has_mac_xl_video) ? 48 : 56)) {
	1540	logerror("loop %d\n", m_videoROM_address);
	1541	m_videoROM_address = 0;
1548	1542	}
1549	1543
1550	1544	}
r14963	r14964
1558	1552	return answer;
1559	1553	}
1560	1554
1561		WRITE16_HANDLER ( lisa_w )
	1555	WRITE16_MEMBER(lisa_state::lisa_w)
1562	1556	{
1563		lisa_state *state = space->machine().driver_data<lisa_state>();
1564	1557	/* segment register set */
1565		int the_seg = state->m_seg;
	1558	int the_seg = m_seg;
1566	1559
1567	1560	/* upper 7 bits -> segment # */
1568	1561	int segment = (offset >> 16) & 0x7f;
1569	1562
1570	1563
1571		if (state->m_setup)
	1564	if (m_setup)
1572	1565	{
1573	1566	if (offset & 0x002000)
1574	1567	{
r14963	r14964
1582	1575	if (offset & 0x000004)
1583	1576	{   /* sorg register */
1584	1577	logerror("sorg, data = %X\n", data);
1585		state->m_real_mmu_regs[the_seg][segment].sorg = data & 0xFFF;
1586		state->m_mmu_regs[the_seg][segment].sorg = (data & 0x0fff) << 9;
	1578	m_real_mmu_regs[the_seg][segment].sorg = data & 0xFFF;
	1579	m_mmu_regs[the_seg][segment].sorg = (data & 0x0fff) << 9;
1587	1580	}
1588	1581	else
1589	1582	{   /* slim register */
1590	1583	logerror("slim, data = %X\n", data);
1591		state->m_real_mmu_regs[the_seg][segment].slim = data & 0xFFF;
1592		state->m_mmu_regs[the_seg][segment].slim = (~ (data << 9)) & 0x01ffff;
	1584	m_real_mmu_regs[the_seg][segment].slim = data & 0xFFF;
	1585	m_mmu_regs[the_seg][segment].slim = (~ (data << 9)) & 0x01ffff;
1593	1586	switch ((data & 0x0f00) >> 8)
1594	1587	{
1595	1588	case 0x4:
1596	1589	/*logerror("type : RAM stack r\n");*/
1597		state->m_mmu_regs[the_seg][segment].type = RAM_stack_r;
	1590	m_mmu_regs[the_seg][segment].type = RAM_stack_r;
1598	1591	break;
1599	1592	case 0x5:
1600	1593	/*logerror("type : RAM r\n");*/
1601		state->m_mmu_regs[the_seg][segment].type = RAM_r;
	1594	m_mmu_regs[the_seg][segment].type = RAM_r;
1602	1595	break;
1603	1596	case 0x6:
1604	1597	/*logerror("type : RAM stack rw\n");*/
1605		state->m_mmu_regs[the_seg][segment].type = RAM_stack_rw;
	1598	m_mmu_regs[the_seg][segment].type = RAM_stack_rw;
1606	1599	break;
1607	1600	case 0x7:
1608	1601	/*logerror("type : RAM rw\n");*/
1609		state->m_mmu_regs[the_seg][segment].type = RAM_rw;
	1602	m_mmu_regs[the_seg][segment].type = RAM_rw;
1610	1603	break;
1611	1604	case 0x8:
1612	1605	case 0x9:   /* not documented, but used by ROMs (?) */
1613	1606	/*logerror("type : I/O\n");*/
1614		state->m_mmu_regs[the_seg][segment].type = IO;
	1607	m_mmu_regs[the_seg][segment].type = IO;
1615	1608	break;
1616	1609	case 0xC:
1617	1610	/*logerror("type : invalid\n");*/
1618		state->m_mmu_regs[the_seg][segment].type = invalid;
	1611	m_mmu_regs[the_seg][segment].type = invalid;
1619	1612	break;
1620	1613	case 0xF:
1621	1614	logerror("type : special I/O\n");
1622		state->m_mmu_regs[the_seg][segment].type = special_IO;
	1615	m_mmu_regs[the_seg][segment].type = special_IO;
1623	1616	break;
1624	1617	default:   /* "unpredictable results" */
1625	1618	logerror("type : unknown\n");
1626		state->m_mmu_regs[the_seg][segment].type = invalid;
	1619	m_mmu_regs[the_seg][segment].type = invalid;
1627	1620	break;
1628	1621	}
1629	1622	}
r14963	r14964
1636	1629	}
1637	1630	}
1638	1631
1639		if (cpu_get_reg(space->machine().device("maincpu"), M68K_SR) & 0x2000)
	1632	if (cpu_get_reg(machine().device("maincpu"), M68K_SR) & 0x2000)
1640	1633	/* supervisor mode -> force register file 0 */
1641	1634	the_seg = 0;
1642	1635
r14963	r14964
1645	1638	int seg_offset = (offset & 0x00ffff) << 1;
1646	1639
1647	1640	/* add revelant origin -> address */
1648		offs_t address = (state->m_mmu_regs[the_seg][segment].sorg + seg_offset) & 0x1fffff;
	1641	offs_t address = (m_mmu_regs[the_seg][segment].sorg + seg_offset) & 0x1fffff;
1649	1642
1650		switch (state->m_mmu_regs[the_seg][segment].type)
	1643	switch (m_mmu_regs[the_seg][segment].type)
1651	1644	{
1652	1645
1653	1646	case RAM_stack_rw:
1654		if (address <= state->m_mmu_regs[the_seg][segment].slim)
	1647	if (address <= m_mmu_regs[the_seg][segment].slim)
1655	1648	{
1656	1649	/* out of segment limits : bus error */
1657	1650
1658	1651	}
1659		COMBINE_DATA((UINT16 *) (state->m_ram_ptr + address));
1660		if (state->m_diag2)
	1652	COMBINE_DATA((UINT16 *) (m_ram_ptr + address));
	1653	if (m_diag2)
1661	1654	{
1662	1655	if ((ACCESSING_BITS_0_7)
1663		&& ! (state->m_bad_parity_table[address >> 3] & (0x1 << (address & 0x7))))
	1656	&& ! (m_bad_parity_table[address >> 3] & (0x1 << (address & 0x7))))
1664	1657	{
1665		state->m_bad_parity_table[address >> 3] |= 0x1 << (address & 0x7);
1666		state->m_bad_parity_count++;
	1658	m_bad_parity_table[address >> 3] |= 0x1 << (address & 0x7);
	1659	m_bad_parity_count++;
1667	1660	}
1668	1661	if ((ACCESSING_BITS_8_15)
1669		&& ! (state->m_bad_parity_table[address >> 3] & (0x2 << (address & 0x7))))
	1662	&& ! (m_bad_parity_table[address >> 3] & (0x2 << (address & 0x7))))
1670	1663	{
1671		state->m_bad_parity_table[address >> 3] |= 0x2 << (address & 0x7);
1672		state->m_bad_parity_count++;
	1664	m_bad_parity_table[address >> 3] |= 0x2 << (address & 0x7);
	1665	m_bad_parity_count++;
1673	1666	}
1674	1667	}
1675		else if (state->m_bad_parity_table[address >> 3] & (0x3 << (address & 0x7)))
	1668	else if (m_bad_parity_table[address >> 3] & (0x3 << (address & 0x7)))
1676	1669	{
1677	1670	if ((ACCESSING_BITS_0_7)
1678		&& (state->m_bad_parity_table[address >> 3] & (0x1 << (address & 0x7))))
	1671	&& (m_bad_parity_table[address >> 3] & (0x1 << (address & 0x7))))
1679	1672	{
1680		state->m_bad_parity_table[address >> 3] &= ~ (0x1 << (address & 0x7));
1681		state->m_bad_parity_count--;
	1673	m_bad_parity_table[address >> 3] &= ~ (0x1 << (address & 0x7));
	1674	m_bad_parity_count--;
1682	1675	}
1683	1676	if ((ACCESSING_BITS_8_15)
1684		&& (state->m_bad_parity_table[address >> 3] & (0x2 << (address & 0x7))))
	1677	&& (m_bad_parity_table[address >> 3] & (0x2 << (address & 0x7))))
1685	1678	{
1686		state->m_bad_parity_table[address >> 3] &= ~ (0x2 << (address & 0x7));
1687		state->m_bad_parity_count--;
	1679	m_bad_parity_table[address >> 3] &= ~ (0x2 << (address & 0x7));
	1680	m_bad_parity_count--;
1688	1681	}
1689	1682	}
1690	1683	break;
1691	1684
1692	1685	case RAM_rw:
1693		if (address > state->m_mmu_regs[the_seg][segment].slim)
	1686	if (address > m_mmu_regs[the_seg][segment].slim)
1694	1687	{
1695	1688	/* out of segment limits : bus error */
1696	1689
1697	1690	}
1698		COMBINE_DATA((UINT16 *) (state->m_ram_ptr + address));
1699		if (state->m_diag2)
	1691	COMBINE_DATA((UINT16 *) (m_ram_ptr + address));
	1692	if (m_diag2)
1700	1693	{
1701	1694	if ((ACCESSING_BITS_0_7)
1702		&& ! (state->m_bad_parity_table[address >> 3] & (0x1 << (address & 0x7))))
	1695	&& ! (m_bad_parity_table[address >> 3] & (0x1 << (address & 0x7))))
1703	1696	{
1704		state->m_bad_parity_table[address >> 3] |= 0x1 << (address & 0x7);
1705		state->m_bad_parity_count++;
	1697	m_bad_parity_table[address >> 3] |= 0x1 << (address & 0x7);
	1698	m_bad_parity_count++;
1706	1699	}
1707	1700	if ((ACCESSING_BITS_8_15)
1708		&& ! (state->m_bad_parity_table[address >> 3] & (0x2 << (address & 0x7))))
	1701	&& ! (m_bad_parity_table[address >> 3] & (0x2 << (address & 0x7))))
1709	1702	{
1710		state->m_bad_parity_table[address >> 3] |= 0x2 << (address & 0x7);
1711		state->m_bad_parity_count++;
	1703	m_bad_parity_table[address >> 3] |= 0x2 << (address & 0x7);
	1704	m_bad_parity_count++;
1712	1705	}
1713	1706	}
1714		else if (state->m_bad_parity_table[address >> 3] & (0x3 << (address & 0x7)))
	1707	else if (m_bad_parity_table[address >> 3] & (0x3 << (address & 0x7)))
1715	1708	{
1716	1709	if ((ACCESSING_BITS_0_7)
1717		&& (state->m_bad_parity_table[address >> 3] & (0x1 << (address & 0x7))))
	1710	&& (m_bad_parity_table[address >> 3] & (0x1 << (address & 0x7))))
1718	1711	{
1719		state->m_bad_parity_table[address >> 3] &= ~ (0x1 << (address & 0x7));
1720		state->m_bad_parity_count--;
	1712	m_bad_parity_table[address >> 3] &= ~ (0x1 << (address & 0x7));
	1713	m_bad_parity_count--;
1721	1714	}
1722	1715	if ((ACCESSING_BITS_8_15)
1723		&& (state->m_bad_parity_table[address >> 3] & (0x2 << (address & 0x7))))
	1716	&& (m_bad_parity_table[address >> 3] & (0x2 << (address & 0x7))))
1724	1717	{
1725		state->m_bad_parity_table[address >> 3] &= ~ (0x2 << (address & 0x7));
1726		state->m_bad_parity_count--;
	1718	m_bad_parity_table[address >> 3] &= ~ (0x2 << (address & 0x7));
	1719	m_bad_parity_count--;
1727	1720	}
1728	1721	}
1729	1722	break;
r14963	r14964
1828	1821	}
1829	1822	}
1830	1823
1831		static READ16_HANDLER ( lisa_IO_r )
	1824	READ16_MEMBER(lisa_state::lisa_IO_r)
1832	1825	{
1833		lisa_state *state = space->machine().driver_data<lisa_state>();
1834		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
1835		via6522_device *via_1 = space->machine().device<via6522_device>("via6522_1");
	1826	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	1827	via6522_device *via_1 = machine().device<via6522_device>("via6522_1");
1836	1828	int answer=0;
1837	1829
1838	1830	switch ((offset & 0x7000) >> 12)
r14963	r14964
1867	1859	if (! (offset & 0x400))
1868	1860	{
1869	1861	/*if (ACCESSING_BITS_0_7)*/   /* Geez, who cares ? */
1870		answer = state->m_fdc_ram[offset & 0x03ff] & 0xff;   /* right ??? */
	1862	answer = m_fdc_ram[offset & 0x03ff] & 0xff;   /* right ??? */
1871	1863	}
1872	1864	}
1873	1865	else
r14963	r14964
1884	1876	case 2:   /* parallel port */
1885	1877	/* 1 VIA located at 0xD901 */
1886	1878	if (ACCESSING_BITS_0_7)
1887		return via_1->read(*space, (offset >> 2) & 0xf);
	1879	return via_1->read(space, (offset >> 2) & 0xf);
1888	1880	break;
1889	1881
1890	1882	case 3:   /* keyboard/mouse cops via */
1891	1883	/* 1 VIA located at 0xDD81 */
1892	1884	if (ACCESSING_BITS_0_7)
1893		return via_0->read(*space, offset & 0xf);
	1885	return via_0->read(space, offset & 0xf);
1894	1886	break;
1895	1887	}
1896	1888	}
r14963	r14964
1901	1893	switch ((offset & 0x0C00) >> 10)
1902	1894	{
1903	1895	case 0x0:   /* cpu board control */
1904		cpu_board_control_access(space->machine(), offset & 0x03ff);
	1896	cpu_board_control_access(machine(), offset & 0x03ff);
1905	1897	break;
1906	1898
1907	1899	case 0x1:   /* Video Address Latch */
1908		answer = state->m_video_address_latch;
	1900	answer = m_video_address_latch;
1909	1901	break;
1910	1902
1911	1903	case 0x2:   /* Memory Error Address Latch */
1912		answer = state->m_mem_err_addr_latch;
	1904	answer = m_mem_err_addr_latch;
1913	1905	break;
1914	1906
1915	1907	case 0x3:   /* Status Register */
1916	1908	answer = 0;
1917		if (! state->m_parity_error_pending)
	1909	if (! m_parity_error_pending)
1918	1910	answer |= 0x02;
1919		if (state->m_VTIR<=1)
	1911	if (m_VTIR<=1)
1920	1912	// GFE : needs to be in phase with Serial NUM
1921	1913	{
1922		int time_in_frame = space->machine().primary_screen->vpos();
1923		if (state->m_features.has_mac_xl_video)
	1914	int time_in_frame = machine().primary_screen->vpos();
	1915	if (m_features.has_mac_xl_video)
1924	1916	{
1925	1917	if ((time_in_frame >= 374) && (time_in_frame <= 392))   /* these values have not been tested */
1926	1918	{   /* if VSyncing, read ROM 2nd half ? */
1927	1919	}
1928	1920	else
1929	1921	{
1930		state->m_VTIR=0;
	1922	m_VTIR=0;
1931	1923	answer |= 0x04;
1932	1924	}
1933	1925	}
r14963	r14964
1939	1931	}
1940	1932	else
1941	1933	{
1942		state->m_VTIR=0;
	1934	m_VTIR=0;
1943	1935	answer |= 0x04;
1944	1936	}
1945	1937	}
r14963	r14964
1948	1940	else
1949	1941	answer |= 0x04;
1950	1942	/* huh... we need to emulate some other bits */
1951		logerror("read status PC=%x val=%x\n", cpu_get_pc(space->machine().device("maincpu")), answer);
	1943	logerror("read status PC=%x val=%x\n", cpu_get_pc(machine().device("maincpu")), answer);
1952	1944
1953	1945	break;
1954	1946	}
r14963	r14964
1958	1950	return answer;
1959	1951	}
1960	1952
1961		static WRITE16_HANDLER ( lisa_IO_w )
	1953	WRITE16_MEMBER(lisa_state::lisa_IO_w)
1962	1954	{
1963		lisa_state *state = space->machine().driver_data<lisa_state>();
1964		via6522_device *via_0 = space->machine().device<via6522_device>("via6522_0");
1965		via6522_device *via_1 = space->machine().device<via6522_device>("via6522_1");
	1955	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
	1956	via6522_device *via_1 = machine().device<via6522_device>("via6522_1");
1966	1957
1967	1958	switch ((offset & 0x7000) >> 12)
1968	1959	{
r14963	r14964
1997	1988	if (! (offset & 0x0400))
1998	1989	{
1999	1990	if (ACCESSING_BITS_0_7)
2000		state->m_fdc_ram[offset & 0x03ff] = data & 0xff;
	1991	m_fdc_ram[offset & 0x03ff] = data & 0xff;
2001	1992	}
2002	1993	}
2003	1994	else
r14963	r14964
2010	2001
2011	2002	case 2:   /* paralel port */
2012	2003	if (ACCESSING_BITS_0_7)
2013		via_1->write(*space, (offset >> 2) & 0xf, data & 0xff);
	2004	via_1->write(space, (offset >> 2) & 0xf, data & 0xff);
2014	2005	break;
2015	2006
2016	2007	case 3:   /* keyboard/mouse cops via */
2017	2008	if (ACCESSING_BITS_0_7)
2018		via_0->write(*space, offset & 0xf, data & 0xff);
	2009	via_0->write(space, offset & 0xf, data & 0xff);
2019	2010	break;
2020	2011	}
2021	2012	}
r14963	r14964
2026	2017	switch ((offset & 0x0C00) >> 10)
2027	2018	{
2028	2019	case 0x0:   /* cpu board control */
2029		cpu_board_control_access(space->machine(), offset & 0x03ff);
	2020	cpu_board_control_access(machine(), offset & 0x03ff);
2030	2021	break;
2031	2022
2032	2023	case 0x1:   /* Video Address Latch */
2033	2024	/*logerror("video address latch write offs=%X, data=%X\n", offset, data);*/
2034		COMBINE_DATA(& state->m_video_address_latch);
2035		state->m_videoram_ptr = ((UINT16 *)state->m_ram_ptr) + ((state->m_video_address_latch << 6) & 0xfc000);
2036		/*logerror("video address latch %X -> base address %X\n", state->m_video_address_latch,
2037		(state->m_video_address_latch << 7) & 0x1f8000);*/
	2025	COMBINE_DATA(& m_video_address_latch);
	2026	m_videoram_ptr = ((UINT16 *)m_ram_ptr) + ((m_video_address_latch << 6) & 0xfc000);
	2027	/*logerror("video address latch %X -> base address %X\n", m_video_address_latch,
	2028	(m_video_address_latch << 7) & 0x1f8000);*/
2038	2029	break;
2039	2030	}
2040	2031	break;

src/mess/machine/lynx.c

r14963	r14964
826	826	- in divide, the remainder will have 2 possible errors, depending on its actual value (no further
827	827	notes on these errors available) */
828	828
829		static void lynx_divide( lynx_state *state )
	829	void lynx_state::lynx_divide()
830	830	{
831	831	UINT32 left;
832	832	UINT16 right;
r14963	r14964
840	840	Remainder (JK)LM
841	841	*/
842	842
843		left = state->m_suzy.data[MATH_H] | (state->m_suzy.data[MATH_G] << 8) | (state->m_suzy.data[MATH_F] << 16) | (state->m_suzy.data[MATH_E] << 24);
844		right = state->m_suzy.data[MATH_P] | (state->m_suzy.data[MATH_N] << 8);
	843	left = m_suzy.data[MATH_H] | (m_suzy.data[MATH_G] << 8) | (m_suzy.data[MATH_F] << 16) | (m_suzy.data[MATH_E] << 24);
	844	right = m_suzy.data[MATH_P] | (m_suzy.data[MATH_N] << 8);
845	845
846		state->m_suzy.accumulate_overflow = FALSE;
	846	m_suzy.accumulate_overflow = FALSE;
847	847	if (right == 0)
848	848	{
849		state->m_suzy.accumulate_overflow = TRUE;   /* during divisions, this bit is used to detect denominator = 0 */
	849	m_suzy.accumulate_overflow = TRUE;   /* during divisions, this bit is used to detect denominator = 0 */
850	850	res = 0xffffffff;
851	851	mod = 0; //?
852	852	}
r14963	r14964
856	856	mod = left % right;
857	857	}
858	858	//  logerror("coprocessor %8x / %8x = %4x\n", left, right, res);
859		state->m_suzy.data[MATH_D] = res & 0xff;
860		state->m_suzy.data[MATH_C] = res >> 8;
861		state->m_suzy.data[MATH_B] = res >> 16;
862		state->m_suzy.data[MATH_A] = res >> 24;
	859	m_suzy.data[MATH_D] = res & 0xff;
	860	m_suzy.data[MATH_C] = res >> 8;
	861	m_suzy.data[MATH_B] = res >> 16;
	862	m_suzy.data[MATH_A] = res >> 24;
863	863
864		state->m_suzy.data[MATH_M] = mod & 0xff;
865		state->m_suzy.data[MATH_L] = mod >> 8;
866		state->m_suzy.data[MATH_K] = 0; // documentation states the hardware sets these to zero on divides
867		state->m_suzy.data[MATH_J] = 0;
	864	m_suzy.data[MATH_M] = mod & 0xff;
	865	m_suzy.data[MATH_L] = mod >> 8;
	866	m_suzy.data[MATH_K] = 0; // documentation states the hardware sets these to zero on divides
	867	m_suzy.data[MATH_J] = 0;
868	868	}
869	869
870		static void lynx_multiply( lynx_state *state )
	870	void lynx_state::lynx_multiply()
871	871	{
872	872	UINT16 left, right;
873	873	UINT32 res, accu;
r14963	r14964
879	879	EFGH
880	880	Accumulate  JKLM
881	881	*/
882		state->m_suzy.accumulate_overflow = FALSE;
	882	m_suzy.accumulate_overflow = FALSE;
883	883
884		left = state->m_suzy.data[MATH_B] | (state->m_suzy.data[MATH_A] << 8);
885		right = state->m_suzy.data[MATH_D] | (state->m_suzy.data[MATH_C] << 8);
	884	left = m_suzy.data[MATH_B] | (m_suzy.data[MATH_A] << 8);
	885	right = m_suzy.data[MATH_D] | (m_suzy.data[MATH_C] << 8);
886	886
887	887	res = left * right;
888	888
889		if (state->m_suzy.signed_math)
	889	if (m_suzy.signed_math)
890	890	{
891		if (!(state->m_sign_AB + state->m_sign_CD))   /* different signs */
	891	if (!(m_sign_AB + m_sign_CD))   /* different signs */
892	892	res = (res ^ 0xffffffff) + 1;
893	893	}
894	894
895		state->m_suzy.data[MATH_H] = res & 0xff;
896		state->m_suzy.data[MATH_G] = res >> 8;
897		state->m_suzy.data[MATH_F] = res >> 16;
898		state->m_suzy.data[MATH_E] = res >> 24;
	895	m_suzy.data[MATH_H] = res & 0xff;
	896	m_suzy.data[MATH_G] = res >> 8;
	897	m_suzy.data[MATH_F] = res >> 16;
	898	m_suzy.data[MATH_E] = res >> 24;
899	899
900		if (state->m_suzy.accumulate)
	900	if (m_suzy.accumulate)
901	901	{
902		accu = state->m_suzy.data[MATH_M] | state->m_suzy.data[MATH_L] << 8 | state->m_suzy.data[MATH_K] << 16 | state->m_suzy.data[MATH_J] << 24;
	902	accu = m_suzy.data[MATH_M] | m_suzy.data[MATH_L] << 8 | m_suzy.data[MATH_K] << 16 | m_suzy.data[MATH_J] << 24;
903	903	accu += res;
904	904
905	905	if (accu < res)
906		state->m_suzy.accumulate_overflow = TRUE;
	906	m_suzy.accumulate_overflow = TRUE;
907	907
908		state->m_suzy.data[MATH_M] = accu;
909		state->m_suzy.data[MATH_L] = accu >> 8;
910		state->m_suzy.data[MATH_K] = accu >> 16;
911		state->m_suzy.data[MATH_J] = accu >> 24;
	908	m_suzy.data[MATH_M] = accu;
	909	m_suzy.data[MATH_L] = accu >> 8;
	910	m_suzy.data[MATH_K] = accu >> 16;
	911	m_suzy.data[MATH_J] = accu >> 24;
912	912	}
913	913	}
914	914
915		static READ8_HANDLER( suzy_read )
	915	READ8_MEMBER(lynx_state::suzy_read)
916	916	{
917		lynx_state *state = space->machine().driver_data<lynx_state>();
918	917	UINT8 value = 0, input;
919	918
920	919	switch (offset)
921	920	{
922	921	case TILTACUML:
923		return state->m_blitter.tilt_accumulator & 0xff;
	922	return m_blitter.tilt_accumulator & 0xff;
924	923	case TILTACUMH:
925		return state->m_blitter.tilt_accumulator>>8;
	924	return m_blitter.tilt_accumulator>>8;
926	925	case HOFFL:
927		return state->m_blitter.xoff & 0xff;
	926	return m_blitter.xoff & 0xff;
928	927	case HOFFH:
929		return state->m_blitter.xoff>>8;
	928	return m_blitter.xoff>>8;
930	929	case VOFFL:
931		return state->m_blitter.yoff & 0xff;
	930	return m_blitter.yoff & 0xff;
932	931	case VOFFH:
933		return state->m_blitter.yoff>>8;
	932	return m_blitter.yoff>>8;
934	933	case VIDBASL:
935		return state->m_blitter.screen & 0xff;
	934	return m_blitter.screen & 0xff;
936	935	case VIDBASH:
937		return state->m_blitter.screen>>8;
	936	return m_blitter.screen>>8;
938	937	case COLLBASL:
939		return state->m_blitter.colbuf & 0xff;
	938	return m_blitter.colbuf & 0xff;
940	939	case COLLBASH:
941		return state->m_blitter.colbuf>>8;
	940	return m_blitter.colbuf>>8;
942	941	case SCBNEXTL:
943		return state->m_blitter.scb_next & 0xff;
	942	return m_blitter.scb_next & 0xff;
944	943	case SCBNEXTH:
945		return state->m_blitter.scb_next>>8;
	944	return m_blitter.scb_next>>8;
946	945	case SPRDLINEL:
947		return state->m_blitter.bitmap & 0xff;
	946	return m_blitter.bitmap & 0xff;
948	947	case SPRDLINEH:
949		return state->m_blitter.bitmap>>8;
	948	return m_blitter.bitmap>>8;
950	949	case HPOSSTRTL:
951		return state->m_blitter.x_pos & 0xff;
	950	return m_blitter.x_pos & 0xff;
952	951	case HPOSSTRTH:
953		return state->m_blitter.x_pos>>8;
	952	return m_blitter.x_pos>>8;
954	953	case VPOSSTRTL:
955		return state->m_blitter.y_pos & 0xff;
	954	return m_blitter.y_pos & 0xff;
956	955	case VPOSSTRTH:
957		return state->m_blitter.y_pos>>8;
	956	return m_blitter.y_pos>>8;
958	957	case SPRHSIZL:
959		return state->m_blitter.width & 0xff;
	958	return m_blitter.width & 0xff;
960	959	case SPRHSIZH:
961		return state->m_blitter.width>>8;
	960	return m_blitter.width>>8;
962	961	case SPRVSIZL:
963		return state->m_blitter.height & 0xff;
	962	return m_blitter.height & 0xff;
964	963	case SPRVSIZH:
965		return state->m_blitter.height>>8;
	964	return m_blitter.height>>8;
966	965	case STRETCHL:
967		return state->m_blitter.stretch & 0xff;
	966	return m_blitter.stretch & 0xff;
968	967	case STRETCHH:
969		return state->m_blitter.stretch>>8;
	968	return m_blitter.stretch>>8;
970	969	case TILTL:
971		return state->m_blitter.tilt & 0xff;
	970	return m_blitter.tilt & 0xff;
972	971	case TILTH:
973		return state->m_blitter.tilt>>8;
	972	return m_blitter.tilt>>8;
974	973	// case SPRDOFFL:
975	974	// case SPRVPOSL:
976	975	// case COLLOFFL:
977	976	case VSIZACUML:
978		return state->m_blitter.height_accumulator & 0xff;
	977	return m_blitter.height_accumulator & 0xff;
979	978	case VSIZACUMH:
980		return state->m_blitter.height_accumulator>>8;
	979	return m_blitter.height_accumulator>>8;
981	980	case HSIZOFFL:
982		return state->m_blitter.width_offset & 0xff;
	981	return m_blitter.width_offset & 0xff;
983	982	case HSIZOFFH:
984		return state->m_blitter.width_offset>>8;
	983	return m_blitter.width_offset>>8;
985	984	case VSIZOFFL:
986		return state->m_blitter.height_offset & 0xff;
	985	return m_blitter.height_offset & 0xff;
987	986	case VSIZOFFH:
988		return state->m_blitter.height_offset>>8;
	987	return m_blitter.height_offset>>8;
989	988	case SCBADRL:
990		return state->m_blitter.scb & 0xff;
	989	return m_blitter.scb & 0xff;
991	990	case SCBADRH:
992		return state->m_blitter.scb>>8;
	991	return m_blitter.scb>>8;
993	992	//case PROCADRL:
994	993	case SUZYHREV:
995	994	return 0x01; // must not be 0 for correct power up
996	995	case SPRSYS:
997	996	// math busy, last carry, unsafe access, and stop on current sprite bits not implemented.
998		if (state->m_suzy.accumulate_overflow)
	997	if (m_suzy.accumulate_overflow)
999	998	value |= 0x40;
1000		if (state->m_blitter.vstretch)
	999	if (m_blitter.vstretch)
1001	1000	value |= 0x10;
1002		if (state->m_blitter.lefthanded)
	1001	if (m_blitter.lefthanded)
1003	1002	value |= 0x08;
1004		if (state->m_blitter.busy)
	1003	if (m_blitter.busy)
1005	1004	value |= 0x01;
1006	1005	break;
1007	1006	case JOYSTICK:
1008		input = input_port_read(space->machine(), "JOY");
1009		switch (state->m_rotate)
	1007	input = input_port_read(machine(), "JOY");
	1008	switch (m_rotate)
1010	1009	{
1011	1010	case 1:
1012	1011	value = input;
r14963	r14964
1025	1024	if (value & PAD_LEFT) input |= PAD_UP;
1026	1025	break;
1027	1026	}
1028		if (state->m_blitter.lefthanded)
	1027	if (m_blitter.lefthanded)
1029	1028	{
1030	1029	value = input & 0x0f;
1031	1030	if (input & PAD_UP) value |= PAD_DOWN;
r14963	r14964
1037	1036	value = input;
1038	1037	break;
1039	1038	case SWITCHES:
1040		value = input_port_read(space->machine(), "PAUSE");
	1039	value = input_port_read(machine(), "PAUSE");
1041	1040	break;
1042	1041	case RCART:
1043		value = *(space->machine().region("user1")->base() + (state->m_suzy.high * state->m_granularity) + state->m_suzy.low);
1044		state->m_suzy.low = (state->m_suzy.low + 1) & (state->m_granularity - 1);
	1042	value = *(machine().region("user1")->base() + (m_suzy.high * m_granularity) + m_suzy.low);
	1043	m_suzy.low = (m_suzy.low + 1) & (m_granularity - 1);
1045	1044	break;
1046	1045	//case RCART_BANK1: /* we need bank 1 emulation!!! */
1047	1046	case SPRCTL0:
r14963	r14964
1054	1053	value = 0;
1055	1054	break;
1056	1055	default:
1057		value = state->m_suzy.data[offset];
	1056	value = m_suzy.data[offset];
1058	1057	}
1059	1058	//logerror("suzy read %.2x %.2x\n",offset,value);
1060	1059	return value;
1061	1060	}
1062	1061
1063		static WRITE8_HANDLER( suzy_write )
	1062	WRITE8_MEMBER(lynx_state::suzy_write)
1064	1063	{
1065		lynx_state *state = space->machine().driver_data<lynx_state>();
1066		state->m_suzy.data[offset] = data;
	1064	m_suzy.data[offset] = data;
1067	1065	//logerror("suzy write %.2x %.2x\n",offset,data);
1068	1066	/* Additional effects of a write */
1069	1067	/* Even addresses are the LSB. Any CPU write to an LSB in 0x00-0x7f will set the MSB to 0. */
r14963	r14964
1071	1069	F (0x62), H (0x60), K (0x6e) or M (0x6c) will force a '0' to be written to A (0x55),
1072	1070	C (0x53), E (0x63), G (0x61), J (0x6f) or L (0x6d) respectively */
1073	1071	if ((offset < 0x80) && !(offset & 0x01))
1074		state->m_suzy.data[offset + 1] = 0;
	1072	m_suzy.data[offset + 1] = 0;
1075	1073
1076	1074	switch(offset)
1077	1075	{
1078	1076	//case TMPADRL:
1079	1077	//case TMPADRH:
1080	1078	case TILTACUML:
1081		state->m_blitter.tilt_accumulator = data; // upper byte forced to zero see above.
	1079	m_blitter.tilt_accumulator = data; // upper byte forced to zero see above.
1082	1080	break;
1083	1081	case TILTACUMH:
1084		state->m_blitter.tilt_accumulator &= 0xff;
1085		state->m_blitter.tilt_accumulator |= data<<8;
	1082	m_blitter.tilt_accumulator &= 0xff;
	1083	m_blitter.tilt_accumulator |= data<<8;
1086	1084	break;
1087	1085	case HOFFL:
1088		state->m_blitter.xoff = data;
	1086	m_blitter.xoff = data;
1089	1087	break;
1090	1088	case HOFFH:
1091		state->m_blitter.xoff &= 0xff;
1092		state->m_blitter.xoff |= data<<8;
	1089	m_blitter.xoff &= 0xff;
	1090	m_blitter.xoff |= data<<8;
1093	1091	break;
1094	1092	case VOFFL:
1095		state->m_blitter.yoff = data;
	1093	m_blitter.yoff = data;
1096	1094	break;
1097	1095	case VOFFH:
1098		state->m_blitter.yoff &= 0xff;
1099		state->m_blitter.yoff |= data<<8;
	1096	m_blitter.yoff &= 0xff;
	1097	m_blitter.yoff |= data<<8;
1100	1098	break;
1101	1099	case VIDBASL:
1102		state->m_blitter.screen = data;
	1100	m_blitter.screen = data;
1103	1101	break;
1104	1102	case VIDBASH:
1105		state->m_blitter.screen &= 0xff;
1106		state->m_blitter.screen |= data<<8;
	1103	m_blitter.screen &= 0xff;
	1104	m_blitter.screen |= data<<8;
1107	1105	break;
1108	1106	case COLLBASL:
1109		state->m_blitter.colbuf = data;
	1107	m_blitter.colbuf = data;
1110	1108	break;
1111	1109	case COLLBASH:
1112		state->m_blitter.colbuf &= 0xff;
1113		state->m_blitter.colbuf |= data<<8;
	1110	m_blitter.colbuf &= 0xff;
	1111	m_blitter.colbuf |= data<<8;
1114	1112	break;
1115	1113	case SCBNEXTL:
1116		state->m_blitter.scb_next = data;
	1114	m_blitter.scb_next = data;
1117	1115	break;
1118	1116	case SCBNEXTH:
1119		state->m_blitter.scb_next &= 0xff;
1120		state->m_blitter.scb_next |= data<<8;
	1117	m_blitter.scb_next &= 0xff;
	1118	m_blitter.scb_next |= data<<8;
1121	1119	break;
1122	1120	case SPRDLINEL:
1123		state->m_blitter.bitmap = data;
	1121	m_blitter.bitmap = data;
1124	1122	break;
1125	1123	case SPRDLINEH:
1126		state->m_blitter.bitmap &= 0xff;
1127		state->m_blitter.bitmap |= data<<8;
	1124	m_blitter.bitmap &= 0xff;
	1125	m_blitter.bitmap |= data<<8;
1128	1126	break;
1129	1127	case HPOSSTRTL:
1130		state->m_blitter.x_pos = data;
	1128	m_blitter.x_pos = data;
1131	1129	case HPOSSTRTH:
1132		state->m_blitter.x_pos &= 0xff;
1133		state->m_blitter.x_pos |= data<<8;
	1130	m_blitter.x_pos &= 0xff;
	1131	m_blitter.x_pos |= data<<8;
1134	1132	case VPOSSTRTL:
1135		state->m_blitter.y_pos = data;
	1133	m_blitter.y_pos = data;
1136	1134	case VPOSSTRTH:
1137		state->m_blitter.y_pos &= 0xff;
1138		state->m_blitter.y_pos |= data<<8;
	1135	m_blitter.y_pos &= 0xff;
	1136	m_blitter.y_pos |= data<<8;
1139	1137	case SPRHSIZL:
1140		state->m_blitter.width = data;
	1138	m_blitter.width = data;
1141	1139	break;
1142	1140	case SPRHSIZH:
1143		state->m_blitter.width &= 0xff;
1144		state->m_blitter.width |= data<<8;
	1141	m_blitter.width &= 0xff;
	1142	m_blitter.width |= data<<8;
1145	1143	break;
1146	1144	case SPRVSIZL:
1147		state->m_blitter.height = data;
	1145	m_blitter.height = data;
1148	1146	break;
1149	1147	case SPRVSIZH:
1150		state->m_blitter.height &= 0xff;
1151		state->m_blitter.height |= data<<8;
	1148	m_blitter.height &= 0xff;
	1149	m_blitter.height |= data<<8;
1152	1150	break;
1153	1151	case STRETCHL:
1154		state->m_blitter.stretch = data;
	1152	m_blitter.stretch = data;
1155	1153	break;
1156	1154	case STRETCHH:
1157		state->m_blitter.stretch &= 0xff;
1158		state->m_blitter.stretch |= data<<8;
	1155	m_blitter.stretch &= 0xff;
	1156	m_blitter.stretch |= data<<8;
1159	1157	break;
1160	1158	case TILTL:
1161		state->m_blitter.tilt = data;
	1159	m_blitter.tilt = data;
1162	1160	break;
1163	1161	case TILTH:
1164		state->m_blitter.tilt &= 0xff;
1165		state->m_blitter.tilt |= data<<8;
	1162	m_blitter.tilt &= 0xff;
	1163	m_blitter.tilt |= data<<8;
1166	1164	break;
1167	1165	// case SPRDOFFL:
1168	1166	// case SPRVPOSL:
1169	1167	// case COLLOFFL:
1170	1168	case VSIZACUML:
1171		state->m_blitter.height_accumulator = data;
	1169	m_blitter.height_accumulator = data;
1172	1170	break;
1173	1171	case VSIZACUMH:
1174		state->m_blitter.height_accumulator &= 0xff;
1175		state->m_blitter.height_accumulator |= data<<8;
	1172	m_blitter.height_accumulator &= 0xff;
	1173	m_blitter.height_accumulator |= data<<8;
1176	1174	break;
1177	1175	case HSIZOFFL:
1178		state->m_blitter.width_offset = data;
	1176	m_blitter.width_offset = data;
1179	1177	break;
1180	1178	case HSIZOFFH:
1181		state->m_blitter.width_offset &= 0xff;
1182		state->m_blitter.width_offset |= data<<8;
	1179	m_blitter.width_offset &= 0xff;
	1180	m_blitter.width_offset |= data<<8;
1183	1181	break;
1184	1182	case VSIZOFFL:
1185		state->m_blitter.height_offset = data;
	1183	m_blitter.height_offset = data;
1186	1184	break;
1187	1185	case VSIZOFFH:
1188		state->m_blitter.height_offset &= 0xff;
1189		state->m_blitter.height_offset |= data<<8;
	1186	m_blitter.height_offset &= 0xff;
	1187	m_blitter.height_offset |= data<<8;
1190	1188	break;
1191	1189	case SCBADRL:
1192		state->m_blitter.scb = data;
	1190	m_blitter.scb = data;
1193	1191	break;
1194	1192	case SCBADRH:
1195		state->m_blitter.scb &= 0xff;
1196		state->m_blitter.scb |= data<<8;
	1193	m_blitter.scb &= 0xff;
	1194	m_blitter.scb |= data<<8;
1197	1195	break;
1198	1196	//case PROCADRL:
1199	1197
1200	1198	/* Writing to M (0x6c) will also clear the accumulator overflow bit */
1201	1199	case MATH_M:
1202		state->m_suzy.accumulate_overflow = FALSE;
	1200	m_suzy.accumulate_overflow = FALSE;
1203	1201	break;
1204	1202	case MATH_C:
1205	1203	/* If we are going to perform a signed multiplication, we store the sign and convert the number
1206	1204	to an unsigned one */
1207		if (state->m_suzy.signed_math)
	1205	if (m_suzy.signed_math)
1208	1206	{
1209	1207	UINT16 factor, temp;
1210		factor = state->m_suzy.data[MATH_D] | (state->m_suzy.data[MATH_C] << 8);
	1208	factor = m_suzy.data[MATH_D] | (m_suzy.data[MATH_C] << 8);
1211	1209	if ((factor - 1) & 0x8000)      /* here we use -1 to cover the math bugs on the sign of 0 and 0x8000 */
1212	1210	{
1213	1211	temp = (factor ^ 0xffff) + 1;
1214		state->m_sign_CD = - 1;
1215		state->m_suzy.data[MATH_D] = temp & 0xff;
1216		state->m_suzy.data[MATH_C] = temp >> 8;
	1212	m_sign_CD = - 1;
	1213	m_suzy.data[MATH_D] = temp & 0xff;
	1214	m_suzy.data[MATH_C] = temp >> 8;
1217	1215	}
1218	1216	else
1219		state->m_sign_CD = 1;
	1217	m_sign_CD = 1;
1220	1218	}
1221	1219	break;
1222	1220	case MATH_D:
r14963	r14964
1225	1223	Either the sign error in the docs is not as described or writing to the lower byte does update the sign flag.
1226	1224	Here I assume the sign flag gets updated. */
1227	1225	if (data)
1228		state->m_sign_CD = 1;
	1226	m_sign_CD = 1;
1229	1227	break;
1230	1228	/* Writing to A will start a 16 bit multiply */
1231	1229	/* If we are going to perform a signed multiplication, we also store the sign and convert the
1232	1230	number to an unsigned one */
1233	1231	case MATH_A:
1234		if (state->m_suzy.signed_math)
	1232	if (m_suzy.signed_math)
1235	1233	{
1236	1234	UINT16 factor, temp;
1237		factor = state->m_suzy.data[MATH_B] | (state->m_suzy.data[MATH_A] << 8);
	1235	factor = m_suzy.data[MATH_B] | (m_suzy.data[MATH_A] << 8);
1238	1236	if ((factor - 1) & 0x8000)      /* here we use -1 to cover the math bugs on the sign of 0 and 0x8000 */
1239	1237	{
1240	1238	temp = (factor ^ 0xffff) + 1;
1241		state->m_sign_AB = - 1;
1242		state->m_suzy.data[MATH_B] = temp & 0xff;
1243		state->m_suzy.data[MATH_A] = temp >> 8;
	1239	m_sign_AB = - 1;
	1240	m_suzy.data[MATH_B] = temp & 0xff;
	1241	m_suzy.data[MATH_A] = temp >> 8;
1244	1242	}
1245	1243	else
1246		state->m_sign_AB = 1;
	1244	m_sign_AB = 1;
1247	1245	}
1248		lynx_multiply(state);
	1246	lynx_multiply();
1249	1247	break;
1250	1248	/* Writing to E will start a 16 bit divide */
1251	1249	case MATH_E:
1252		lynx_divide(state);
	1250	lynx_divide();
1253	1251	break;
1254	1252	case SPRCTL0:
1255		state->m_blitter.spr_ctl0 = data;
	1253	m_blitter.spr_ctl0 = data;
1256	1254	break;
1257	1255	case SPRCTL1:
1258		state->m_blitter.spr_ctl1 = data;
	1256	m_blitter.spr_ctl1 = data;
1259	1257	break;
1260	1258	case SPRCOLL:
1261		state->m_blitter.spr_coll = data;
	1259	m_blitter.spr_coll = data;
1262	1260	break;
1263	1261	case SUZYBUSEN:
1264	1262	logerror("write to SUSYBUSEN %x \n", data);
1265	1263	break;
1266	1264	case SPRSYS:
1267		state->m_suzy.signed_math = (data & 0x80) ? 1:0;
1268		state->m_suzy.accumulate = (data & 0x40) ? 1:0;
1269		state->m_blitter.no_collide = (data & 0x20) ? 1:0;
1270		state->m_blitter.vstretch = (data & 0x10) ? 1:0;
1271		state->m_blitter.lefthanded = (data & 0x08) ? 1:0;
	1265	m_suzy.signed_math = (data & 0x80) ? 1:0;
	1266	m_suzy.accumulate = (data & 0x40) ? 1:0;
	1267	m_blitter.no_collide = (data & 0x20) ? 1:0;
	1268	m_blitter.vstretch = (data & 0x10) ? 1:0;
	1269	m_blitter.lefthanded = (data & 0x08) ? 1:0;
1272	1270	// unsafe access clear and sprite engine stop request are not enabled
1273	1271	if (data & 0x02) logerror("sprite engine stop request\n");
1274	1272	break;
1275	1273	case SPRGO:
1276		if ((data & 0x01) && state->m_suzy.data[SUZYBUSEN])
	1274	if ((data & 0x01) && m_suzy.data[SUZYBUSEN])
1277	1275	{
1278		//state->m_blitter.time = space->machine().time();
1279		lynx_blitter(space->machine());
	1276	//m_blitter.time = machine().time();
	1277	lynx_blitter(machine());
1280	1278	}
1281	1279	break;
1282	1280	case JOYSTICK:
r14963	r14964
1524	1522	}
1525	1523	}
1526	1524
1527		static UINT8 lynx_timer_read(lynx_state *state, int which, int offset)
	1525	UINT8 lynx_state::lynx_timer_read(int which, int offset)
1528	1526	{
1529	1527	UINT8 value = 0;
1530	1528
1531	1529	switch (offset)
1532	1530	{
1533	1531	case 0:
1534		value = state->m_timer[which].bakup;
	1532	value = m_timer[which].bakup;
1535	1533	break;
1536	1534	case 1:
1537		value = state->m_timer[which].cntrl1;
	1535	value = m_timer[which].cntrl1;
1538	1536	break;
1539	1537	case 2:
1540		if ((state->m_timer[which].cntrl1 & 0x07) == 0x07) // linked timer
	1538	if ((m_timer[which].cntrl1 & 0x07) == 0x07) // linked timer
1541	1539	{
1542		value = state->m_timer[which].counter;
	1540	value = m_timer[which].counter;
1543	1541	}
1544	1542	else
1545	1543	{
1546		if ( state->m_timer[which].timer_active )
	1544	if ( m_timer[which].timer_active )
1547	1545	{
1548		value = (UINT8) (state->m_timer[which].timer->remaining().as_ticks(1000000>>(state->m_timer[which].cntrl1 & 0x07)));
	1546	value = (UINT8) (m_timer[which].timer->remaining().as_ticks(1000000>>(m_timer[which].cntrl1 & 0x07)));
1549	1547	value -= value ? 1 : 0;
1550	1548	}
1551	1549	}
1552	1550	break;
1553	1551
1554	1552	case 3:
1555		value = state->m_timer[which].cntrl2;
	1553	value = m_timer[which].cntrl2;
1556	1554	break;
1557	1555	}
1558	1556	// logerror("timer %d read %x %.2x\n", which, offset, value);
1559	1557	return value;
1560	1558	}
1561	1559
1562		static void lynx_timer_write(lynx_state *state, int which, int offset, UINT8 data)
	1560	void lynx_state::lynx_timer_write(int which, int offset, UINT8 data)
1563	1561	{
1564	1562	//logerror("timer %d write %x %.2x\n", which, offset, data);
1565	1563	attotime t;
1566	1564
1567		if ( state->m_timer[which].timer_active && ((state->m_timer[which].cntrl1 & 0x07) != 0x07))
	1565	if ( m_timer[which].timer_active && ((m_timer[which].cntrl1 & 0x07) != 0x07))
1568	1566	{
1569		state->m_timer[which].counter = (UINT8) (state->m_timer[which].timer->remaining().as_ticks(1000000>>(state->m_timer[which].cntrl1 & 0x07)));
1570		state->m_timer[which].counter -= (state->m_timer[which].counter) ? 1 : 0;
	1567	m_timer[which].counter = (UINT8) (m_timer[which].timer->remaining().as_ticks(1000000>>(m_timer[which].cntrl1 & 0x07)));
	1568	m_timer[which].counter -= (m_timer[which].counter) ? 1 : 0;
1571	1569	}
1572	1570
1573	1571	switch (offset)
1574	1572	{
1575	1573	case 0:
1576		state->m_timer[which].bakup = data;
	1574	m_timer[which].bakup = data;
1577	1575	break;
1578	1576	case 1:
1579		state->m_timer[which].cntrl1 = data;
	1577	m_timer[which].cntrl1 = data;
1580	1578	if (data & 0x40) // reset timer done
1581		state->m_timer[which].cntrl2 &= ~0x08;
	1579	m_timer[which].cntrl2 &= ~0x08;
1582	1580	break;
1583	1581	case 2:
1584		state->m_timer[which].counter = data;
	1582	m_timer[which].counter = data;
1585	1583	break;
1586	1584	case 3:
1587		state->m_timer[which].cntrl2 = (state->m_timer[which].cntrl2 & ~0x08) | (data & 0x08);
	1585	m_timer[which].cntrl2 = (m_timer[which].cntrl2 & ~0x08) | (data & 0x08);
1588	1586	break;
1589	1587	}
1590	1588
1591	1589	/* Update timers */
1592	1590	//if ( offset < 3 )
1593	1591	//{
1594		state->m_timer[which].timer->reset();
1595		state->m_timer[which].timer_active = 0;
1596		if ((state->m_timer[which].cntrl1 & 0x08) && !(state->m_timer[which].cntrl2 & 0x08))      // if enable count
	1592	m_timer[which].timer->reset();
	1593	m_timer[which].timer_active = 0;
	1594	if ((m_timer[which].cntrl1 & 0x08) && !(m_timer[which].cntrl2 & 0x08))      // if enable count
1597	1595	{
1598		if ((state->m_timer[which].cntrl1 & 0x07) != 0x07)  // if not set to link mode
	1596	if ((m_timer[which].cntrl1 & 0x07) != 0x07)  // if not set to link mode
1599	1597	{
1600		t = (attotime::from_hz(lynx_time_factor(state->m_timer[which].cntrl1 & 0x07)) * (state->m_timer[which].counter + 1));
1601		state->m_timer[which].timer->adjust(t, which);
1602		state->m_timer[which].timer_active = 1;
	1598	t = (attotime::from_hz(lynx_time_factor(m_timer[which].cntrl1 & 0x07)) * (m_timer[which].counter + 1));
	1599	m_timer[which].timer->adjust(t, which);
	1600	m_timer[which].timer_active = 1;
1603	1601	}
1604	1602	}
1605	1603	//}
r14963	r14964
1678	1676	return value;
1679	1677	}
1680	1678
1681		static WRITE8_HANDLER(lynx_uart_w)
	1679	WRITE8_MEMBER(lynx_state::lynx_uart_w)
1682	1680	{
1683		lynx_state *state = space->machine().driver_data<lynx_state>();
1684	1681	logerror("uart write %.2x %.2x\n", offset, data);
1685	1682	switch (offset)
1686	1683	{
1687	1684	case 0x8c:
1688		state->m_uart.serctl = data;
	1685	m_uart.serctl = data;
1689	1686	break;
1690	1687
1691	1688	case 0x8d:
1692		if (state->m_uart.sending)
	1689	if (m_uart.sending)
1693	1690	{
1694		state->m_uart.buffer = data;
1695		state->m_uart.buffer_loaded = TRUE;
	1691	m_uart.buffer = data;
	1692	m_uart.buffer_loaded = TRUE;
1696	1693	}
1697	1694	else
1698	1695	{
1699		state->m_uart.sending = TRUE;
1700		state->m_uart.data_to_send = data;
	1696	m_uart.sending = TRUE;
	1697	m_uart.data_to_send = data;
1701	1698	// timing not accurate, baude rate should be calculated from timer 4 backup value and clock rate
1702		space->machine().scheduler().timer_set(attotime::from_usec(11*16), FUNC(lynx_uart_timer));
	1699	machine().scheduler().timer_set(attotime::from_usec(11*16), FUNC(lynx_uart_timer));
1703	1700	}
1704	1701	break;
1705	1702	}
r14963	r14964
1713	1710	****************************************/
1714	1711
1715	1712
1716		static READ8_HANDLER( mikey_read )
	1713	READ8_MEMBER(lynx_state::mikey_read)
1717	1714	{
1718		lynx_state *state = space->machine().driver_data<lynx_state>();
1719	1715	UINT8 direction, value = 0x00;
1720	1716
1721	1717	switch (offset)
r14963	r14964
1728	1724	case 0x14: case 0x15: case 0x16: case 0x17:
1729	1725	case 0x18: case 0x19: case 0x1a: case 0x1b:
1730	1726	case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1731		value = lynx_timer_read(state, offset >> 2, offset & 0x03);
	1727	value = lynx_timer_read(offset >> 2, offset & 0x03);
1732	1728	break;
1733	1729
1734	1730	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
r14963	r14964
1736	1732	case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1737	1733	case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1738	1734	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x50:
1739		value = lynx_audio_read(state->m_audio, offset);
	1735	value = lynx_audio_read(m_audio, offset);
1740	1736	break;
1741	1737
1742	1738	case 0x80:
1743	1739	case 0x81:
1744		value = state->m_mikey.data[0x81]; // both registers access the same interupt status byte
	1740	value = m_mikey.data[0x81]; // both registers access the same interupt status byte
1745	1741	// logerror( "mikey read %.2x %.2x\n", offset, value );
1746	1742	break;
1747	1743
r14963	r14964
1759	1755	break;
1760	1756
1761	1757	case 0x8b:
1762		direction = state->m_mikey.data[0x8a];
1763		value |= (direction & 0x01) ? (state->m_mikey.data[offset] & 0x01) : 0x01;   // External Power input
1764		value |= (direction & 0x02) ? (state->m_mikey.data[offset] & 0x02) : 0x00;   // Cart Address Data output (0 turns cart power on)
1765		value |= (direction & 0x04) ? (state->m_mikey.data[offset] & 0x04) : 0x04;   // noexp input
	1758	direction = m_mikey.data[0x8a];
	1759	value |= (direction & 0x01) ? (m_mikey.data[offset] & 0x01) : 0x01;   // External Power input
	1760	value |= (direction & 0x02) ? (m_mikey.data[offset] & 0x02) : 0x00;   // Cart Address Data output (0 turns cart power on)
	1761	value |= (direction & 0x04) ? (m_mikey.data[offset] & 0x04) : 0x04;   // noexp input
1766	1762	// REST read returns actual rest state anded with rest output bit
1767		value |= (direction & 0x08) ? (((state->m_mikey.data[offset] & 0x08) && (state->m_mikey.vb_rest)) ? 0x00 : 0x08) : 0x00;   // rest output
1768		value |= (direction & 0x10) ? (state->m_mikey.data[offset] & 0x10) : 0x10;   // audin input
	1763	value |= (direction & 0x08) ? (((m_mikey.data[offset] & 0x08) && (m_mikey.vb_rest)) ? 0x00 : 0x08) : 0x00;   // rest output
	1764	value |= (direction & 0x10) ? (m_mikey.data[offset] & 0x10) : 0x10;   // audin input
1769	1765	/* Hack: we disable COMLynx  */
1770	1766	value |= 0x04;
1771	1767	/* B5, B6 & B7 are not used */
r14963	r14964
1773	1769
1774	1770	case 0x8c:
1775	1771	case 0x8d:
1776		value = lynx_uart_r(space, offset);
	1772	value = lynx_uart_r(&space, offset);
1777	1773	break;
1778	1774
1779	1775	default:
1780		value = state->m_mikey.data[offset];
	1776	value = m_mikey.data[offset];
1781	1777	//logerror( "mikey read %.2x %.2x\n", offset, value );
1782	1778	}
1783	1779	return value;
1784	1780	}
1785	1781
1786		static WRITE8_HANDLER( mikey_write )
	1782	WRITE8_MEMBER(lynx_state::mikey_write)
1787	1783	{
1788		lynx_state *state = space->machine().driver_data<lynx_state>();
1789	1784	switch (offset)
1790	1785	{
1791	1786	case 0x00: case 0x01: case 0x02: case 0x03:
r14963	r14964
1796	1791	case 0x14: case 0x15: case 0x16: case 0x17:
1797	1792	case 0x18: case 0x19: case 0x1a: case 0x1b:
1798	1793	case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1799		lynx_timer_write(state, offset >> 2, offset & 3, data);
	1794	lynx_timer_write(offset >> 2, offset & 3, data);
1800	1795	return;
1801	1796
1802	1797	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
r14963	r14964
1804	1799	case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1805	1800	case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1806	1801	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x50:
1807		lynx_audio_write(state->m_audio, offset, data);
	1802	lynx_audio_write(m_audio, offset, data);
1808	1803	return;
1809	1804
1810	1805	case 0x80:
1811		state->m_mikey.data[0x81] &= ~data; // clear interrupt source
	1806	m_mikey.data[0x81] &= ~data; // clear interrupt source
1812	1807	// logerror("mikey write %.2x %.2x\n", offset, data);
1813		if (!state->m_mikey.data[0x81])
1814		cputag_set_input_line(space->machine(), "maincpu", M65SC02_IRQ_LINE, CLEAR_LINE);
	1808	if (!m_mikey.data[0x81])
	1809	cputag_set_input_line(machine(), "maincpu", M65SC02_IRQ_LINE, CLEAR_LINE);
1815	1810	break;
1816	1811
1817	1812	/* Is this correct? */ // Notes say writing to register will result in interupt being triggered.
1818	1813	case 0x81:
1819		state->m_mikey.data[0x81] |= data;
	1814	m_mikey.data[0x81] |= data;
1820	1815	if (data)
1821	1816	{
1822		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_HALT, CLEAR_LINE);
1823		cputag_set_input_line(space->machine(), "maincpu", M65SC02_IRQ_LINE, ASSERT_LINE);
	1817	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_HALT, CLEAR_LINE);
	1818	cputag_set_input_line(machine(), "maincpu", M65SC02_IRQ_LINE, ASSERT_LINE);
1824	1819	logerror("direct write to interupt register\n");
1825	1820	}
1826	1821	break;
1827	1822
1828	1823	case 0x87:
1829		state->m_mikey.data[offset] = data;
	1824	m_mikey.data[offset] = data;
1830	1825	if (data & 0x02)      // Power (1 = on)
1831	1826	{
1832	1827	if (data & 0x01)   // Cart Address Strobe
1833	1828	{
1834		state->m_suzy.high <<= 1;
1835		if (state->m_mikey.data[0x8b] & 0x02)
1836		state->m_suzy.high |= 1;
1837		state->m_suzy.high &= 0xff;
1838		state->m_suzy.low = 0;
	1829	m_suzy.high <<= 1;
	1830	if (m_mikey.data[0x8b] & 0x02)
	1831	m_suzy.high |= 1;
	1832	m_suzy.high &= 0xff;
	1833	m_suzy.low = 0;
1839	1834	}
1840	1835	}
1841	1836	else
1842	1837	{
1843		state->m_suzy.high = 0;
1844		state->m_suzy.low = 0;
	1838	m_suzy.high = 0;
	1839	m_suzy.low = 0;
1845	1840	}
1846	1841	break;
1847	1842
r14963	r14964
1853	1848	case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
1854	1849	case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1855	1850	case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1856		state->m_mikey.data[offset] = data;
	1851	m_mikey.data[offset] = data;
1857	1852
1858	1853	/* RED = 0xb- & 0x0f, GREEN = 0xa- & 0x0f, BLUE = (0xb- & 0xf0) >> 4 */
1859		state->m_palette[offset & 0x0f] = space->machine().pens[
1860		((state->m_mikey.data[0xb0 + (offset & 0x0f)] & 0x0f)) |
1861		((state->m_mikey.data[0xa0 + (offset & 0x0f)] & 0x0f) << 4) |
1862		((state->m_mikey.data[0xb0 + (offset & 0x0f)] & 0xf0) << 4)];
	1854	m_palette[offset & 0x0f] = machine().pens[
	1855	((m_mikey.data[0xb0 + (offset & 0x0f)] & 0x0f)) |
	1856	((m_mikey.data[0xa0 + (offset & 0x0f)] & 0x0f) << 4) |
	1857	((m_mikey.data[0xb0 + (offset & 0x0f)] & 0xf0) << 4)];
1863	1858	break;
1864	1859
1865	1860	/* TODO: properly implement these writes */
1866	1861	case 0x8b:
1867		state->m_mikey.data[offset] = data;
1868		if (state->m_mikey.data[0x8a] & 0x10)
1869		logerror("Trying to enable bank 1 write. %d\n", state->m_mikey.data[offset] & 0x10);
	1862	m_mikey.data[offset] = data;
	1863	if (m_mikey.data[0x8a] & 0x10)
	1864	logerror("Trying to enable bank 1 write. %d\n", m_mikey.data[offset] & 0x10);
1870	1865	break;
1871	1866
1872	1867	//case 0x90: // SDONEACK - Suzy Done Acknowledge
1873	1868	case 0x91: // CPUSLEEP - CPU Bus Request Disable
1874		state->m_mikey.data[offset] = data;
1875		if (!data && state->m_blitter.busy)
	1869	m_mikey.data[offset] = data;
	1870	if (!data && m_blitter.busy)
1876	1871	{
1877		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_HALT, ASSERT_LINE);
	1872	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_HALT, ASSERT_LINE);
1878	1873	/* A write of '0' to this address will reset the CPU bus request flip flop */
1879	1874	}
1880	1875	break;
1881	1876	case 0x94: case 0x95:
1882		state->m_mikey.data[offset]=data;
	1877	m_mikey.data[offset]=data;
1883	1878	break;
1884	1879	case 0x9c: case 0x9d: case 0x9e:
1885		state->m_mikey.data[offset]=data;
	1880	m_mikey.data[offset]=data;
1886	1881	logerror("Mtest%d write: %x\n", offset&0x3, data);
1887	1882	break;
1888	1883
1889	1884	default:
1890		state->m_mikey.data[offset]=data;
	1885	m_mikey.data[offset]=data;
1891	1886	//logerror("mikey write %.2x %.2x\n",offset,data);
1892	1887	break;
1893	1888	}
r14963	r14964
1899	1894
1900	1895	****************************************/
1901	1896
1902		READ8_HANDLER( lynx_memory_config_r )
	1897	READ8_MEMBER(lynx_state::lynx_memory_config_r)
1903	1898	{
1904		lynx_state *state = space->machine().driver_data<lynx_state>();
1905		return state->m_memory_config;
	1899	return m_memory_config;
1906	1900	}
1907	1901
1908		WRITE8_HANDLER( lynx_memory_config_w )
	1902	WRITE8_MEMBER(lynx_state::lynx_memory_config_w)
1909	1903	{
1910		lynx_state *state = space->machine().driver_data<lynx_state>();
1911	1904	/* bit 7: hispeed, uses page mode accesses (4 instead of 5 cycles )
1912	1905	* when these are safe in the cpu */
1913		state->m_memory_config = data;
	1906	m_memory_config = data;
1914	1907
1915	1908	if (data & 1) {
1916		space->install_readwrite_bank(0xfc00, 0xfcff, "bank1");
	1909	space.install_readwrite_bank(0xfc00, 0xfcff, "bank1");
1917	1910	} else {
1918		space->install_legacy_readwrite_handler(0xfc00, 0xfcff, FUNC(suzy_read), FUNC(suzy_write));
	1911	space.install_readwrite_handler(0xfc00, 0xfcff, read8_delegate(FUNC(lynx_state::suzy_read),this), write8_delegate(FUNC(lynx_state::suzy_write),this));
1919	1912	}
1920	1913	if (data & 2) {
1921		space->install_readwrite_bank(0xfd00, 0xfdff, "bank2");
	1914	space.install_readwrite_bank(0xfd00, 0xfdff, "bank2");
1922	1915	} else {
1923		space->install_legacy_readwrite_handler(0xfd00, 0xfdff, FUNC(mikey_read), FUNC(mikey_write));
	1916	space.install_readwrite_handler(0xfd00, 0xfdff, read8_delegate(FUNC(lynx_state::mikey_read),this), write8_delegate(FUNC(lynx_state::mikey_write),this));
1924	1917	}
1925	1918
1926	1919	if (data & 1)
1927		memory_set_bankptr(space->machine(), "bank1", state->m_mem_fc00);
	1920	memory_set_bankptr(machine(), "bank1", m_mem_fc00);
1928	1921	if (data & 2)
1929		memory_set_bankptr(space->machine(), "bank2", state->m_mem_fd00);
1930		memory_set_bank(space->machine(), "bank3", (data & 4) ? 1 : 0);
1931		memory_set_bank(space->machine(), "bank4", (data & 8) ? 1 : 0);
	1922	memory_set_bankptr(machine(), "bank2", m_mem_fd00);
	1923	memory_set_bank(machine(), "bank3", (data & 4) ? 1 : 0);
	1924	memory_set_bank(machine(), "bank4", (data & 8) ? 1 : 0);
1932	1925	}
1933	1926
1934	1927	static void lynx_reset(running_machine &machine)
1935	1928	{
1936	1929	lynx_state *state = machine.driver_data<lynx_state>();
1937		lynx_memory_config_w(machine.device("maincpu")->memory().space(AS_PROGRAM), 0, 0);
	1930	state->lynx_memory_config_w(*machine.device("maincpu")->memory().space(AS_PROGRAM), 0, 0);
1938	1931
1939	1932	cputag_set_input_line(machine, "maincpu", INPUT_LINE_HALT, CLEAR_LINE);
1940	1933	cputag_set_input_line(machine, "maincpu", M65SC02_IRQ_LINE, CLEAR_LINE);
r14963	r14964
1966	1959
1967	1960	static void lynx_postload(lynx_state *state)
1968	1961	{
1969		lynx_memory_config_w( state->machine().device("maincpu")->memory().space(AS_PROGRAM), 0, state->m_memory_config);
	1962	state->lynx_memory_config_w( *state->machine().device("maincpu")->memory().space(AS_PROGRAM), 0, state->m_memory_config);
1970	1963	}
1971	1964
1972	1965	MACHINE_START( lynx )

src/mess/machine/lviv.c

r14963	r14964
145	145
146	146
147	147	/* I/O */
148		READ8_HANDLER ( lviv_io_r )
	148	READ8_MEMBER(lviv_state::lviv_io_r)
149	149	{
150		lviv_state *state = space->machine().driver_data<lviv_state>();
151		if (state->m_startup_mem_map)
	150	if (m_startup_mem_map)
152	151	{
153	152	return 0;   /* ??? */
154	153	}
r14963	r14964
157	156	switch ((offset >> 4) & 0x3)
158	157	{
159	158	case 0:
160		return space->machine().device<i8255_device>("ppi8255_0")->read(*space, offset & 3);
	159	return machine().device<i8255_device>("ppi8255_0")->read(space, offset & 3);
161	160
162	161	case 1:
163		return space->machine().device<i8255_device>("ppi8255_1")->read(*space, offset & 3);
	162	return machine().device<i8255_device>("ppi8255_1")->read(space, offset & 3);
164	163
165	164	case 2:
166	165	case 3:
r14963	r14964
171	170	}
172	171	}
173	172
174		WRITE8_HANDLER ( lviv_io_w )
	173	WRITE8_MEMBER(lviv_state::lviv_io_w)
175	174	{
176		lviv_state *state = space->machine().driver_data<lviv_state>();
177		address_space *cpuspace = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
178		if (state->m_startup_mem_map)
	175	address_space *cpuspace = machine().device("maincpu")->memory().space(AS_PROGRAM);
	176	if (m_startup_mem_map)
179	177	{
180		UINT8 *ram = space->machine().device<ram_device>(RAM_TAG)->pointer();
	178	UINT8 *ram = machine().device<ram_device>(RAM_TAG)->pointer();
181	179
182		state->m_startup_mem_map = 0;
	180	m_startup_mem_map = 0;
183	181
184	182	cpuspace->install_write_bank(0x0000, 0x3fff, "bank1");
185	183	cpuspace->install_write_bank(0x4000, 0x7fff, "bank2");
186	184	cpuspace->install_write_bank(0x8000, 0xbfff, "bank3");
187	185	cpuspace->unmap_write(0xC000, 0xffff);
188	186
189		memory_set_bankptr(space->machine(),"bank1", ram);
190		memory_set_bankptr(space->machine(),"bank2", ram + 0x4000);
191		memory_set_bankptr(space->machine(),"bank3", ram + 0x8000);
192		memory_set_bankptr(space->machine(),"bank4", space->machine().region("maincpu")->base() + 0x010000);
	187	memory_set_bankptr(machine(),"bank1", ram);
	188	memory_set_bankptr(machine(),"bank2", ram + 0x4000);
	189	memory_set_bankptr(machine(),"bank3", ram + 0x8000);
	190	memory_set_bankptr(machine(),"bank4", machine().region("maincpu")->base() + 0x010000);
193	191	}
194	192	else
195	193	{
196	194	switch ((offset >> 4) & 0x3)
197	195	{
198	196	case 0:
199		space->machine().device<i8255_device>("ppi8255_0")->write(*space, offset & 3, data);
	197	machine().device<i8255_device>("ppi8255_0")->write(space, offset & 3, data);
200	198	break;
201	199
202	200	case 1:
203		space->machine().device<i8255_device>("ppi8255_1")->write(*space, offset & 3, data);
	201	machine().device<i8255_device>("ppi8255_1")->write(space, offset & 3, data);
204	202	break;
205	203
206	204	case 2:

src/mess/machine/mbc55x.c

r14963	r14964
116	116	DEVCB_NULL
117	117	};
118	118
119		READ8_HANDLER( pic8259_r )
	119	READ8_MEMBER(mbc55x_state::mbcpic8259_r)
120	120	{
121		mbc55x_state *state = space->machine().driver_data<mbc55x_state>();
122		return pic8259_r(state->m_pic, offset>>1);
	121	return pic8259_r(m_pic, offset>>1);
123	122	}
124	123
125		WRITE8_HANDLER( pic8259_w )
	124	WRITE8_MEMBER(mbc55x_state::mbcpic8259_w)
126	125	{
127		mbc55x_state *state = space->machine().driver_data<mbc55x_state>();
128		pic8259_w(state->m_pic, offset>>1, data);
	126	pic8259_w(m_pic, offset>>1, data);
129	127	}
130	128
131	129	static IRQ_CALLBACK(mbc55x_irq_callback)
r14963	r14964
157	155	}
158	156	};
159	157
160		READ8_HANDLER( pit8253_r )
	158	READ8_MEMBER(mbc55x_state::mbcpit8253_r)
161	159	{
162		mbc55x_state *state = space->machine().driver_data<mbc55x_state>();
163		return pit8253_r(state->m_pit, offset>>1);
	160	return pit8253_r(m_pit, offset>>1);
164	161	}
165	162
166		WRITE8_HANDLER( pit8253_w )
	163	WRITE8_MEMBER(mbc55x_state::mbcpit8253_w)
167	164	{
168		mbc55x_state *state = space->machine().driver_data<mbc55x_state>();
169		pit8253_w(state->m_pit, offset>>1, data);
	165	pit8253_w(m_pit, offset>>1, data);
170	166	}
171	167
172	168	WRITE_LINE_MEMBER( mbc55x_state::pit8253_t2 )
r14963	r14964
189	185	m_vram_page=data;
190	186	}
191	187
192		READ8_HANDLER( mbc55x_disk_r )
	188	READ8_MEMBER(mbc55x_state::mbc55x_disk_r)
193	189	{
194		mbc55x_state *state = space->machine().driver_data<mbc55x_state>();
195		return wd17xx_r(state->m_fdc, offset>>1);
	190	return wd17xx_r(m_fdc, offset>>1);
196	191	}
197	192
198		WRITE8_HANDLER( mbc55x_disk_w )
	193	WRITE8_MEMBER(mbc55x_state::mbc55x_disk_w)
199	194	{
200		mbc55x_state *state = space->machine().driver_data<mbc55x_state>();
201		wd17xx_w(state->m_fdc, offset>>1, data);
	195	wd17xx_w(m_fdc, offset>>1, data);
202	196	}
203	197
204	198	WRITE_LINE_MEMBER( mbc55x_state::mbc55x_fdc_intrq_w )
r14963	r14964
311	305	DEVCB_NULL
312	306	};
313	307
314		READ8_HANDLER( mbc55x_kb_usart_r )
	308	READ8_MEMBER(mbc55x_state::mbc55x_kb_usart_r)
315	309	{
316		mbc55x_state *state = space->machine().driver_data<mbc55x_state>();
317	310	UINT8 result = 0;
318	311	offset>>=1;
319	312
320	313	switch (offset)
321	314	{
322		case 0   : //logerror("%s read kb_uart\n",space->machine().describe_context());
323		result = state->m_kb_uart->data_r(*space,0); break;
	315	case 0   : //logerror("%s read kb_uart\n",machine().describe_context());
	316	result = m_kb_uart->data_r(space,0); break;
324	317
325		case 1   :   result = state->m_kb_uart->status_r(*space,0);
	318	case 1   :   result = m_kb_uart->status_r(space,0);
326	319
327		if (state->m_keyboard.key_special & KEY_BIT_CTRL)   // Parity error used to flag control down
	320	if (m_keyboard.key_special & KEY_BIT_CTRL)   // Parity error used to flag control down
328	321	result |= I8251_STATUS_PARITY_ERROR;
329	322	break;
330	323	}
r14963	r14964
332	325	return result;
333	326	}
334	327
335		WRITE8_HANDLER( mbc55x_kb_usart_w )
	328	WRITE8_MEMBER(mbc55x_state::mbc55x_kb_usart_w)
336	329	{
337		mbc55x_state *state = space->machine().driver_data<mbc55x_state>();
338	330	offset>>=1;
339	331
340	332	switch (offset)
341	333	{
342		case 0   : state->m_kb_uart->data_w(*space, 0, data); break;
343		case 1   : state->m_kb_uart->control_w(*space, 0, data); break;
	334	case 0   : m_kb_uart->data_w(space, 0, data); break;
	335	case 1   : m_kb_uart->control_w(space, 0, data); break;
344	336	}
345	337	}
346	338

src/mess/machine/apple1.c

r14963	r14964
506	506	cassette_device_image(machine)->output(state->m_cassette_output_flipflop ? 1.0 : -1.0);
507	507	}
508	508
509		READ8_HANDLER( apple1_cassette_r )
	509	READ8_MEMBER(apple1_state::apple1_cassette_r)
510	510	{
511		cassette_toggle_output(space->machine());
	511	cassette_toggle_output(machine());
512	512
513	513	if (offset <= 0x7f)
514	514	{
r14963	r14964
517	517	always comes from the corresponding cassette ROM location
518	518	in $C100-$C17F. */
519	519
520		return space->read_byte(0xc100 + offset);
	520	return space.read_byte(0xc100 + offset);
521	521	}
522	522	else
523	523	{
r14963	r14964
534	534	/* (Don't try putting a non-zero "noise threshhold" here,
535	535	because it can cause tape header bits on real cassette
536	536	images to be misread as data bits.) */
537		if (cassette_device_image(space->machine())->input() > 0.0)
538		return space->read_byte(0xc100 + (offset & ~1));
	537	if (cassette_device_image(machine())->input() > 0.0)
	538	return space.read_byte(0xc100 + (offset & ~1));
539	539	else
540		return space->read_byte(0xc100 + offset);
	540	return space.read_byte(0xc100 + offset);
541	541	}
542	542	}
543	543
544		WRITE8_HANDLER( apple1_cassette_w )
	544	WRITE8_MEMBER(apple1_state::apple1_cassette_w)
545	545	{
546	546	/* Writes toggle the output flip-flop in the same way that reads
547	547	do; other than that they have no effect.  Any repeated accesses
r14963	r14964
550	550	However, we still have to handle writes, since they may be done
551	551	by user code. */
552	552
553		cassette_toggle_output(space->machine());
	553	cassette_toggle_output(machine());
554	554	}

src/mess/machine/mtx.c

r14963	r14964
105	105	}
106	106	}
107	107
108		WRITE8_HANDLER( mtx_bankswitch_w )
	108	WRITE8_MEMBER(mtx_state::mtx_bankswitch_w)
109	109	{
110		bankswitch(space->machine(), data);
	110	bankswitch(machine(), data);
111	111	}
112	112
113	113	/*-------------------------------------------------
r14963	r14964
127	127	mtx_sound_latch_w - sound latch write
128	128	-------------------------------------------------*/
129	129
130		WRITE8_HANDLER( mtx_sound_latch_w )
	130	WRITE8_MEMBER(mtx_state::mtx_sound_latch_w)
131	131	{
132		mtx_state *state = space->machine().driver_data<mtx_state>();
133	132
134		state->m_sound_latch = data;
	133	m_sound_latch = data;
135	134	}
136	135
137	136	/*-------------------------------------------------
r14963	r14964
190	189	mtx_sense_w - keyboard sense write
191	190	-------------------------------------------------*/
192	191
193		WRITE8_HANDLER( mtx_sense_w )
	192	WRITE8_MEMBER(mtx_state::mtx_sense_w)
194	193	{
195		mtx_state *state = space->machine().driver_data<mtx_state>();
196	194
197		state->m_key_sense = data;
	195	m_key_sense = data;
198	196	}
199	197
200	198	/*-------------------------------------------------
201	199	mtx_key_lo_r - keyboard low read
202	200	-------------------------------------------------*/
203	201
204		READ8_HANDLER( mtx_key_lo_r )
	202	READ8_MEMBER(mtx_state::mtx_key_lo_r)
205	203	{
206		mtx_state *state = space->machine().driver_data<mtx_state>();
207	204
208	205	UINT8 data = 0xff;
209	206
210		if (!(state->m_key_sense & 0x01)) data &= input_port_read(space->machine(), "ROW0");
211		if (!(state->m_key_sense & 0x02)) data &= input_port_read(space->machine(), "ROW1");
212		if (!(state->m_key_sense & 0x04)) data &= input_port_read(space->machine(), "ROW2");
213		if (!(state->m_key_sense & 0x08)) data &= input_port_read(space->machine(), "ROW3");
214		if (!(state->m_key_sense & 0x10)) data &= input_port_read(space->machine(), "ROW4");
215		if (!(state->m_key_sense & 0x20)) data &= input_port_read(space->machine(), "ROW5");
216		if (!(state->m_key_sense & 0x40)) data &= input_port_read(space->machine(), "ROW6");
217		if (!(state->m_key_sense & 0x80)) data &= input_port_read(space->machine(), "ROW7");
	207	if (!(m_key_sense & 0x01)) data &= input_port_read(machine(), "ROW0");
	208	if (!(m_key_sense & 0x02)) data &= input_port_read(machine(), "ROW1");
	209	if (!(m_key_sense & 0x04)) data &= input_port_read(machine(), "ROW2");
	210	if (!(m_key_sense & 0x08)) data &= input_port_read(machine(), "ROW3");
	211	if (!(m_key_sense & 0x10)) data &= input_port_read(machine(), "ROW4");
	212	if (!(m_key_sense & 0x20)) data &= input_port_read(machine(), "ROW5");
	213	if (!(m_key_sense & 0x40)) data &= input_port_read(machine(), "ROW6");
	214	if (!(m_key_sense & 0x80)) data &= input_port_read(machine(), "ROW7");
218	215
219	216	return data;
220	217	}
r14963	r14964
223	220	mtx_key_lo_r - keyboard high read
224	221	-------------------------------------------------*/
225	222
226		READ8_HANDLER( mtx_key_hi_r )
	223	READ8_MEMBER(mtx_state::mtx_key_hi_r)
227	224	{
228		mtx_state *state = space->machine().driver_data<mtx_state>();
229	225
230		UINT8 data = input_port_read(space->machine(), "country_code");
	226	UINT8 data = input_port_read(machine(), "country_code");
231	227
232		if (!(state->m_key_sense & 0x01)) data &= input_port_read(space->machine(), "ROW0") >> 8;
233		if (!(state->m_key_sense & 0x02)) data &= input_port_read(space->machine(), "ROW1") >> 8;
234		if (!(state->m_key_sense & 0x04)) data &= input_port_read(space->machine(), "ROW2") >> 8;
235		if (!(state->m_key_sense & 0x08)) data &= input_port_read(space->machine(), "ROW3") >> 8;
236		if (!(state->m_key_sense & 0x10)) data &= input_port_read(space->machine(), "ROW4") >> 8;
237		if (!(state->m_key_sense & 0x20)) data &= input_port_read(space->machine(), "ROW5") >> 8;
238		if (!(state->m_key_sense & 0x40)) data &= input_port_read(space->machine(), "ROW6") >> 8;
239		if (!(state->m_key_sense & 0x80)) data &= input_port_read(space->machine(), "ROW7") >> 8;
	228	if (!(m_key_sense & 0x01)) data &= input_port_read(machine(), "ROW0") >> 8;
	229	if (!(m_key_sense & 0x02)) data &= input_port_read(machine(), "ROW1") >> 8;
	230	if (!(m_key_sense & 0x04)) data &= input_port_read(machine(), "ROW2") >> 8;
	231	if (!(m_key_sense & 0x08)) data &= input_port_read(machine(), "ROW3") >> 8;
	232	if (!(m_key_sense & 0x10)) data &= input_port_read(machine(), "ROW4") >> 8;
	233	if (!(m_key_sense & 0x20)) data &= input_port_read(machine(), "ROW5") >> 8;
	234	if (!(m_key_sense & 0x40)) data &= input_port_read(machine(), "ROW6") >> 8;
	235	if (!(m_key_sense & 0x80)) data &= input_port_read(machine(), "ROW7") >> 8;
240	236
241	237	return data;
242	238	}
r14963	r14964
245	241	hrx_address_w - HRX video RAM address
246	242	-------------------------------------------------*/
247	243
248		WRITE8_HANDLER( hrx_address_w )
	244	WRITE8_MEMBER(mtx_state::hrx_address_w)
249	245	{
250	246	if (offset)
251	247	{
r14963	r14964
287	283	hrx_data_r - HRX data read
288	284	-------------------------------------------------*/
289	285
290		READ8_HANDLER( hrx_data_r )
	286	READ8_MEMBER(mtx_state::hrx_data_r)
291	287	{
292	288	return 0;
293	289	}
r14963	r14964
296	292	hrx_data_w - HRX data write
297	293	-------------------------------------------------*/
298	294
299		WRITE8_HANDLER( hrx_data_w )
	295	WRITE8_MEMBER(mtx_state::hrx_data_w)
300	296	{
301	297	}
302	298
r14963	r14964
304	300	hrx_attr_r - HRX attribute read
305	301	-------------------------------------------------*/
306	302
307		READ8_HANDLER( hrx_attr_r )
	303	READ8_MEMBER(mtx_state::hrx_attr_r)
308	304	{
309	305	return 0;
310	306	}
r14963	r14964
313	309	hrx_attr_r - HRX attribute write
314	310	-------------------------------------------------*/
315	311
316		WRITE8_HANDLER( hrx_attr_w )
	312	WRITE8_MEMBER(mtx_state::hrx_attr_w)
317	313	{
318	314	/*
319	315

src/mess/machine/rmnimbus.c

r14963	r14964
854	854	logerror("CPU reset done\n");
855	855	}
856	856
857		READ16_HANDLER( nimbus_i186_internal_port_r )
	857	READ16_MEMBER(rmnimbus_state::nimbus_i186_internal_port_r)
858	858	{
859		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
860	859	int temp, which;
861	860
862	861	switch (offset)
863	862	{
864	863	case 0x11:
865		logerror("%05X:ERROR - read from 80186 EOI\n", cpu_get_pc(&space->device()));
	864	logerror("%05X:ERROR - read from 80186 EOI\n", cpu_get_pc(&space.device()));
866	865	break;
867	866
868	867	case 0x12:
869		if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll\n", cpu_get_pc(&space->device()));
870		if (state->m_i186.intr.poll_status & 0x8000)
871		int_callback(space->machine().device(MAINCPU_TAG), 0);
872		return state->m_i186.intr.poll_status;
	868	if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll\n", cpu_get_pc(&space.device()));
	869	if (m_i186.intr.poll_status & 0x8000)
	870	int_callback(machine().device(MAINCPU_TAG), 0);
	871	return m_i186.intr.poll_status;
873	872
874	873	case 0x13:
875		if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll status\n", cpu_get_pc(&space->device()));
876		return state->m_i186.intr.poll_status;
	874	if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll status\n", cpu_get_pc(&space.device()));
	875	return m_i186.intr.poll_status;
877	876
878	877	case 0x14:
879		if (LOG_PORTS) logerror("%05X:read 80186 interrupt mask\n", cpu_get_pc(&space->device()));
880		temp  = (state->m_i186.intr.timer  >> 3) & 0x01;
881		temp |= (state->m_i186.intr.dma[0] >> 1) & 0x04;
882		temp |= (state->m_i186.intr.dma[1] >> 0) & 0x08;
883		temp |= (state->m_i186.intr.ext[0] << 1) & 0x10;
884		temp |= (state->m_i186.intr.ext[1] << 2) & 0x20;
885		temp |= (state->m_i186.intr.ext[2] << 3) & 0x40;
886		temp |= (state->m_i186.intr.ext[3] << 4) & 0x80;
	878	if (LOG_PORTS) logerror("%05X:read 80186 interrupt mask\n", cpu_get_pc(&space.device()));
	879	temp  = (m_i186.intr.timer  >> 3) & 0x01;
	880	temp |= (m_i186.intr.dma[0] >> 1) & 0x04;
	881	temp |= (m_i186.intr.dma[1] >> 0) & 0x08;
	882	temp |= (m_i186.intr.ext[0] << 1) & 0x10;
	883	temp |= (m_i186.intr.ext[1] << 2) & 0x20;
	884	temp |= (m_i186.intr.ext[2] << 3) & 0x40;
	885	temp |= (m_i186.intr.ext[3] << 4) & 0x80;
887	886	return temp;
888	887
889	888	case 0x15:
890		if (LOG_PORTS) logerror("%05X:read 80186 interrupt priority mask\n", cpu_get_pc(&space->device()));
891		return state->m_i186.intr.priority_mask;
	889	if (LOG_PORTS) logerror("%05X:read 80186 interrupt priority mask\n", cpu_get_pc(&space.device()));
	890	return m_i186.intr.priority_mask;
892	891
893	892	case 0x16:
894		if (LOG_PORTS) logerror("%05X:read 80186 interrupt in-service\n", cpu_get_pc(&space->device()));
895		return state->m_i186.intr.in_service;
	893	if (LOG_PORTS) logerror("%05X:read 80186 interrupt in-service\n", cpu_get_pc(&space.device()));
	894	return m_i186.intr.in_service;
896	895
897	896	case 0x17:
898		if (LOG_PORTS) logerror("%05X:read 80186 interrupt request\n", cpu_get_pc(&space->device()));
899		temp = state->m_i186.intr.request & ~0x0001;
900		if (state->m_i186.intr.status & 0x0007)
	897	if (LOG_PORTS) logerror("%05X:read 80186 interrupt request\n", cpu_get_pc(&space.device()));
	898	temp = m_i186.intr.request & ~0x0001;
	899	if (m_i186.intr.status & 0x0007)
901	900	temp |= 1;
902	901	return temp;
903	902
904	903	case 0x18:
905		if (LOG_PORTS) logerror("%05X:read 80186 interrupt status\n", cpu_get_pc(&space->device()));
906		return state->m_i186.intr.status;
	904	if (LOG_PORTS) logerror("%05X:read 80186 interrupt status\n", cpu_get_pc(&space.device()));
	905	return m_i186.intr.status;
907	906
908	907	case 0x19:
909		if (LOG_PORTS) logerror("%05X:read 80186 timer interrupt control\n", cpu_get_pc(&space->device()));
910		return state->m_i186.intr.timer;
	908	if (LOG_PORTS) logerror("%05X:read 80186 timer interrupt control\n", cpu_get_pc(&space.device()));
	909	return m_i186.intr.timer;
911	910
912	911	case 0x1a:
913		if (LOG_PORTS) logerror("%05X:read 80186 DMA 0 interrupt control\n", cpu_get_pc(&space->device()));
914		return state->m_i186.intr.dma[0];
	912	if (LOG_PORTS) logerror("%05X:read 80186 DMA 0 interrupt control\n", cpu_get_pc(&space.device()));
	913	return m_i186.intr.dma[0];
915	914
916	915	case 0x1b:
917		if (LOG_PORTS) logerror("%05X:read 80186 DMA 1 interrupt control\n", cpu_get_pc(&space->device()));
918		return state->m_i186.intr.dma[1];
	916	if (LOG_PORTS) logerror("%05X:read 80186 DMA 1 interrupt control\n", cpu_get_pc(&space.device()));
	917	return m_i186.intr.dma[1];
919	918
920	919	case 0x1c:
921		if (LOG_PORTS) logerror("%05X:read 80186 INT 0 interrupt control\n", cpu_get_pc(&space->device()));
922		return state->m_i186.intr.ext[0];
	920	if (LOG_PORTS) logerror("%05X:read 80186 INT 0 interrupt control\n", cpu_get_pc(&space.device()));
	921	return m_i186.intr.ext[0];
923	922
924	923	case 0x1d:
925		if (LOG_PORTS) logerror("%05X:read 80186 INT 1 interrupt control\n", cpu_get_pc(&space->device()));
926		return state->m_i186.intr.ext[1];
	924	if (LOG_PORTS) logerror("%05X:read 80186 INT 1 interrupt control\n", cpu_get_pc(&space.device()));
	925	return m_i186.intr.ext[1];
927	926
928	927	case 0x1e:
929		if (LOG_PORTS) logerror("%05X:read 80186 INT 2 interrupt control\n", cpu_get_pc(&space->device()));
930		return state->m_i186.intr.ext[2];
	928	if (LOG_PORTS) logerror("%05X:read 80186 INT 2 interrupt control\n", cpu_get_pc(&space.device()));
	929	return m_i186.intr.ext[2];
931	930
932	931	case 0x1f:
933		if (LOG_PORTS) logerror("%05X:read 80186 INT 3 interrupt control\n", cpu_get_pc(&space->device()));
934		return state->m_i186.intr.ext[3];
	932	if (LOG_PORTS) logerror("%05X:read 80186 INT 3 interrupt control\n", cpu_get_pc(&space.device()));
	933	return m_i186.intr.ext[3];
935	934
936	935	case 0x28:
937	936	case 0x2c:
938	937	case 0x30:
939		if (LOG_PORTS) logerror("%05X:read 80186 Timer %d count\n", cpu_get_pc(&space->device()), (offset - 0x28) / 4);
	938	if (LOG_PORTS) logerror("%05X:read 80186 Timer %d count\n", cpu_get_pc(&space.device()), (offset - 0x28) / 4);
940	939	which = (offset - 0x28) / 4;
941	940	if (!(offset & 1))
942		internal_timer_sync(space->machine(), which);
943		return state->m_i186.timer[which].count;
	941	internal_timer_sync(machine(), which);
	942	return m_i186.timer[which].count;
944	943
945	944	case 0x29:
946	945	case 0x2d:
947	946	case 0x31:
948		if (LOG_PORTS) logerror("%05X:read 80186 Timer %d max A\n", cpu_get_pc(&space->device()), (offset - 0x29) / 4);
	947	if (LOG_PORTS) logerror("%05X:read 80186 Timer %d max A\n", cpu_get_pc(&space.device()), (offset - 0x29) / 4);
949	948	which = (offset - 0x29) / 4;
950		return state->m_i186.timer[which].maxA;
	949	return m_i186.timer[which].maxA;
951	950
952	951	case 0x2a:
953	952	case 0x2e:
954		logerror("%05X:read 80186 Timer %d max B\n", cpu_get_pc(&space->device()), (offset - 0x2a) / 4);
	953	logerror("%05X:read 80186 Timer %d max B\n", cpu_get_pc(&space.device()), (offset - 0x2a) / 4);
955	954	which = (offset - 0x2a) / 4;
956		return state->m_i186.timer[which].maxB;
	955	return m_i186.timer[which].maxB;
957	956
958	957	case 0x2b:
959	958	case 0x2f:
960	959	case 0x33:
961		if (LOG_PORTS) logerror("%05X:read 80186 Timer %d control\n", cpu_get_pc(&space->device()), (offset - 0x2b) / 4);
	960	if (LOG_PORTS) logerror("%05X:read 80186 Timer %d control\n", cpu_get_pc(&space.device()), (offset - 0x2b) / 4);
962	961	which = (offset - 0x2b) / 4;
963		return state->m_i186.timer[which].control;
	962	return m_i186.timer[which].control;
964	963
965	964	case 0x50:
966		if (LOG_PORTS) logerror("%05X:read 80186 upper chip select\n", cpu_get_pc(&space->device()));
967		return state->m_i186.mem.upper;
	965	if (LOG_PORTS) logerror("%05X:read 80186 upper chip select\n", cpu_get_pc(&space.device()));
	966	return m_i186.mem.upper;
968	967
969	968	case 0x51:
970		if (LOG_PORTS) logerror("%05X:read 80186 lower chip select\n", cpu_get_pc(&space->device()));
971		return state->m_i186.mem.lower;
	969	if (LOG_PORTS) logerror("%05X:read 80186 lower chip select\n", cpu_get_pc(&space.device()));
	970	return m_i186.mem.lower;
972	971
973	972	case 0x52:
974		if (LOG_PORTS) logerror("%05X:read 80186 peripheral chip select\n", cpu_get_pc(&space->device()));
975		return state->m_i186.mem.peripheral;
	973	if (LOG_PORTS) logerror("%05X:read 80186 peripheral chip select\n", cpu_get_pc(&space.device()));
	974	return m_i186.mem.peripheral;
976	975
977	976	case 0x53:
978		if (LOG_PORTS) logerror("%05X:read 80186 middle chip select\n", cpu_get_pc(&space->device()));
979		return state->m_i186.mem.middle;
	977	if (LOG_PORTS) logerror("%05X:read 80186 middle chip select\n", cpu_get_pc(&space.device()));
	978	return m_i186.mem.middle;
980	979
981	980	case 0x54:
982		if (LOG_PORTS) logerror("%05X:read 80186 middle P chip select\n", cpu_get_pc(&space->device()));
983		return state->m_i186.mem.middle_size;
	981	if (LOG_PORTS) logerror("%05X:read 80186 middle P chip select\n", cpu_get_pc(&space.device()));
	982	return m_i186.mem.middle_size;
984	983
985	984	case 0x60:
986	985	case 0x68:
987		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower source address\n", cpu_get_pc(&space->device()), (offset - 0x60) / 8);
	986	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower source address\n", cpu_get_pc(&space.device()), (offset - 0x60) / 8);
988	987	which = (offset - 0x60) / 8;
989		return state->m_i186.dma[which].source;
	988	return m_i186.dma[which].source;
990	989
991	990	case 0x61:
992	991	case 0x69:
993		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper source address\n", cpu_get_pc(&space->device()), (offset - 0x61) / 8);
	992	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper source address\n", cpu_get_pc(&space.device()), (offset - 0x61) / 8);
994	993	which = (offset - 0x61) / 8;
995		return state->m_i186.dma[which].source >> 16;
	994	return m_i186.dma[which].source >> 16;
996	995
997	996	case 0x62:
998	997	case 0x6a:
999		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower dest address\n", cpu_get_pc(&space->device()), (offset - 0x62) / 8);
	998	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower dest address\n", cpu_get_pc(&space.device()), (offset - 0x62) / 8);
1000	999	which = (offset - 0x62) / 8;
1001		return state->m_i186.dma[which].dest;
	1000	return m_i186.dma[which].dest;
1002	1001
1003	1002	case 0x63:
1004	1003	case 0x6b:
1005		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper dest address\n", cpu_get_pc(&space->device()), (offset - 0x63) / 8);
	1004	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper dest address\n", cpu_get_pc(&space.device()), (offset - 0x63) / 8);
1006	1005	which = (offset - 0x63) / 8;
1007		return state->m_i186.dma[which].dest >> 16;
	1006	return m_i186.dma[which].dest >> 16;
1008	1007
1009	1008	case 0x64:
1010	1009	case 0x6c:
1011		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d transfer count\n", cpu_get_pc(&space->device()), (offset - 0x64) / 8);
	1010	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d transfer count\n", cpu_get_pc(&space.device()), (offset - 0x64) / 8);
1012	1011	which = (offset - 0x64) / 8;
1013		return state->m_i186.dma[which].count;
	1012	return m_i186.dma[which].count;
1014	1013
1015	1014	case 0x65:
1016	1015	case 0x6d:
1017		if (LOG_PORTS) logerror("%05X:read 80186 DMA%d control\n", cpu_get_pc(&space->device()), (offset - 0x65) / 8);
	1016	if (LOG_PORTS) logerror("%05X:read 80186 DMA%d control\n", cpu_get_pc(&space.device()), (offset - 0x65) / 8);
1018	1017	which = (offset - 0x65) / 8;
1019		return state->m_i186.dma[which].control;
	1018	return m_i186.dma[which].control;
1020	1019
1021	1020	default:
1022		logerror("%05X:read 80186 port %02X\n", cpu_get_pc(&space->device()), offset);
	1021	logerror("%05X:read 80186 port %02X\n", cpu_get_pc(&space.device()), offset);
1023	1022	break;
1024	1023	}
1025	1024	return 0x00;
r14963	r14964
1031	1030	*
1032	1031	*************************************/
1033	1032
1034		WRITE16_HANDLER( nimbus_i186_internal_port_w )
	1033	WRITE16_MEMBER(rmnimbus_state::nimbus_i186_internal_port_w)
1035	1034	{
1036		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
1037	1035	int temp, which, data16 = data;
1038	1036
1039	1037	switch (offset)
1040	1038	{
1041	1039	case 0x11:
1042		if (LOG_PORTS) logerror("%05X:80186 EOI = %04X\n", cpu_get_pc(&space->device()), data16);
1043		handle_eoi(space->machine(),0x8000);
1044		update_interrupt_state(space->machine());
	1040	if (LOG_PORTS) logerror("%05X:80186 EOI = %04X\n", cpu_get_pc(&space.device()), data16);
	1041	handle_eoi(machine(),0x8000);
	1042	update_interrupt_state(machine());
1045	1043	break;
1046	1044
1047	1045	case 0x12:
1048		logerror("%05X:ERROR - write to 80186 interrupt poll = %04X\n", cpu_get_pc(&space->device()), data16);
	1046	logerror("%05X:ERROR - write to 80186 interrupt poll = %04X\n", cpu_get_pc(&space.device()), data16);
1049	1047	break;
1050	1048
1051	1049	case 0x13:
1052		logerror("%05X:ERROR - write to 80186 interrupt poll status = %04X\n", cpu_get_pc(&space->device()), data16);
	1050	logerror("%05X:ERROR - write to 80186 interrupt poll status = %04X\n", cpu_get_pc(&space.device()), data16);
1053	1051	break;
1054	1052
1055	1053	case 0x14:
1056		if (LOG_PORTS) logerror("%05X:80186 interrupt mask = %04X\n", cpu_get_pc(&space->device()), data16);
1057		state->m_i186.intr.timer  = (state->m_i186.intr.timer  & ~0x08) | ((data16 << 3) & 0x08);
1058		state->m_i186.intr.dma[0] = (state->m_i186.intr.dma[0] & ~0x08) | ((data16 << 1) & 0x08);
1059		state->m_i186.intr.dma[1] = (state->m_i186.intr.dma[1] & ~0x08) | ((data16 << 0) & 0x08);
1060		state->m_i186.intr.ext[0] = (state->m_i186.intr.ext[0] & ~0x08) | ((data16 >> 1) & 0x08);
1061		state->m_i186.intr.ext[1] = (state->m_i186.intr.ext[1] & ~0x08) | ((data16 >> 2) & 0x08);
1062		state->m_i186.intr.ext[2] = (state->m_i186.intr.ext[2] & ~0x08) | ((data16 >> 3) & 0x08);
1063		state->m_i186.intr.ext[3] = (state->m_i186.intr.ext[3] & ~0x08) | ((data16 >> 4) & 0x08);
1064		update_interrupt_state(space->machine());
	1054	if (LOG_PORTS) logerror("%05X:80186 interrupt mask = %04X\n", cpu_get_pc(&space.device()), data16);
	1055	m_i186.intr.timer  = (m_i186.intr.timer  & ~0x08) | ((data16 << 3) & 0x08);
	1056	m_i186.intr.dma[0] = (m_i186.intr.dma[0] & ~0x08) | ((data16 << 1) & 0x08);
	1057	m_i186.intr.dma[1] = (m_i186.intr.dma[1] & ~0x08) | ((data16 << 0) & 0x08);
	1058	m_i186.intr.ext[0] = (m_i186.intr.ext[0] & ~0x08) | ((data16 >> 1) & 0x08);
	1059	m_i186.intr.ext[1] = (m_i186.intr.ext[1] & ~0x08) | ((data16 >> 2) & 0x08);
	1060	m_i186.intr.ext[2] = (m_i186.intr.ext[2] & ~0x08) | ((data16 >> 3) & 0x08);
	1061	m_i186.intr.ext[3] = (m_i186.intr.ext[3] & ~0x08) | ((data16 >> 4) & 0x08);
	1062	update_interrupt_state(machine());
1065	1063	break;
1066	1064
1067	1065	case 0x15:
1068		if (LOG_PORTS) logerror("%05X:80186 interrupt priority mask = %04X\n", cpu_get_pc(&space->device()), data16);
1069		state->m_i186.intr.priority_mask = data16 & 0x0007;
1070		update_interrupt_state(space->machine());
	1066	if (LOG_PORTS) logerror("%05X:80186 interrupt priority mask = %04X\n", cpu_get_pc(&space.device()), data16);
	1067	m_i186.intr.priority_mask = data16 & 0x0007;
	1068	update_interrupt_state(machine());
1071	1069	break;
1072	1070
1073	1071	case 0x16:
1074		if (LOG_PORTS) logerror("%05X:80186 interrupt in-service = %04X\n", cpu_get_pc(&space->device()), data16);
1075		state->m_i186.intr.in_service = data16 & 0x00ff;
1076		update_interrupt_state(space->machine());
	1072	if (LOG_PORTS) logerror("%05X:80186 interrupt in-service = %04X\n", cpu_get_pc(&space.device()), data16);
	1073	m_i186.intr.in_service = data16 & 0x00ff;
	1074	update_interrupt_state(machine());
1077	1075	break;
1078	1076
1079	1077	case 0x17:
1080		if (LOG_PORTS) logerror("%05X:80186 interrupt request = %04X\n", cpu_get_pc(&space->device()), data16);
1081		state->m_i186.intr.request = (state->m_i186.intr.request & ~0x00c0) | (data16 & 0x00c0);
1082		update_interrupt_state(space->machine());
	1078	if (LOG_PORTS) logerror("%05X:80186 interrupt request = %04X\n", cpu_get_pc(&space.device()), data16);
	1079	m_i186.intr.request = (m_i186.intr.request & ~0x00c0) | (data16 & 0x00c0);
	1080	update_interrupt_state(machine());
1083	1081	break;
1084	1082
1085	1083	case 0x18:
1086		if (LOG_PORTS) logerror("%05X:WARNING - wrote to 80186 interrupt status = %04X\n", cpu_get_pc(&space->device()), data16);
1087		state->m_i186.intr.status = (state->m_i186.intr.status & ~0x8007) | (data16 & 0x8007);
1088		update_interrupt_state(space->machine());
	1084	if (LOG_PORTS) logerror("%05X:WARNING - wrote to 80186 interrupt status = %04X\n", cpu_get_pc(&space.device()), data16);
	1085	m_i186.intr.status = (m_i186.intr.status & ~0x8007) | (data16 & 0x8007);
	1086	update_interrupt_state(machine());
1089	1087	break;
1090	1088
1091	1089	case 0x19:
1092		if (LOG_PORTS) logerror("%05X:80186 timer interrupt contol = %04X\n", cpu_get_pc(&space->device()), data16);
1093		state->m_i186.intr.timer = data16 & 0x000f;
	1090	if (LOG_PORTS) logerror("%05X:80186 timer interrupt contol = %04X\n", cpu_get_pc(&space.device()), data16);
	1091	m_i186.intr.timer = data16 & 0x000f;
1094	1092	break;
1095	1093
1096	1094	case 0x1a:
1097		if (LOG_PORTS) logerror("%05X:80186 DMA 0 interrupt control = %04X\n", cpu_get_pc(&space->device()), data16);
1098		state->m_i186.intr.dma[0] = data16 & 0x000f;
	1095	if (LOG_PORTS) logerror("%05X:80186 DMA 0 interrupt control = %04X\n", cpu_get_pc(&space.device()), data16);
	1096	m_i186.intr.dma[0] = data16 & 0x000f;
1099	1097	break;
1100	1098
1101	1099	case 0x1b:
1102		if (LOG_PORTS) logerror("%05X:80186 DMA 1 interrupt control = %04X\n", cpu_get_pc(&space->device()), data16);
1103		state->m_i186.intr.dma[1] = data16 & 0x000f;
	1100	if (LOG_PORTS) logerror("%05X:80186 DMA 1 interrupt control = %04X\n", cpu_get_pc(&space.device()), data16);
	1101	m_i186.intr.dma[1] = data16 & 0x000f;
1104	1102	break;
1105	1103
1106	1104	case 0x1c:
1107		if (LOG_PORTS) logerror("%05X:80186 INT 0 interrupt control = %04X\n", cpu_get_pc(&space->device()), data16);
1108		state->m_i186.intr.ext[0] = data16 & 0x007f;
	1105	if (LOG_PORTS) logerror("%05X:80186 INT 0 interrupt control = %04X\n", cpu_get_pc(&space.device()), data16);
	1106	m_i186.intr.ext[0] = data16 & 0x007f;
1109	1107	break;
1110	1108
1111	1109	case 0x1d:
1112		if (LOG_PORTS) logerror("%05X:80186 INT 1 interrupt control = %04X\n", cpu_get_pc(&space->device()), data16);
1113		state->m_i186.intr.ext[1] = data16 & 0x007f;
	1110	if (LOG_PORTS) logerror("%05X:80186 INT 1 interrupt control = %04X\n", cpu_get_pc(&space.device()), data16);
	1111	m_i186.intr.ext[1] = data16 & 0x007f;
1114	1112	break;
1115	1113
1116	1114	case 0x1e:
1117		if (LOG_PORTS) logerror("%05X:80186 INT 2 interrupt control = %04X\n", cpu_get_pc(&space->device()), data16);
1118		state->m_i186.intr.ext[2] = data16 & 0x001f;
	1115	if (LOG_PORTS) logerror("%05X:80186 INT 2 interrupt control = %04X\n", cpu_get_pc(&space.device()), data16);
	1116	m_i186.intr.ext[2] = data16 & 0x001f;
1119	1117	break;
1120	1118
1121	1119	case 0x1f:
1122		if (LOG_PORTS) logerror("%05X:80186 INT 3 interrupt control = %04X\n", cpu_get_pc(&space->device()), data16);
1123		state->m_i186.intr.ext[3] = data16 & 0x001f;
	1120	if (LOG_PORTS) logerror("%05X:80186 INT 3 interrupt control = %04X\n", cpu_get_pc(&space.device()), data16);
	1121	m_i186.intr.ext[3] = data16 & 0x001f;
1124	1122	break;
1125	1123
1126	1124	case 0x28:
1127	1125	case 0x2c:
1128	1126	case 0x30:
1129		if (LOG_PORTS) logerror("%05X:80186 Timer %d count = %04X\n", cpu_get_pc(&space->device()), (offset - 0x28) / 4, data16);
	1127	if (LOG_PORTS) logerror("%05X:80186 Timer %d count = %04X\n", cpu_get_pc(&space.device()), (offset - 0x28) / 4, data16);
1130	1128	which = (offset - 0x28) / 4;
1131		internal_timer_update(space->machine(),which, data16, -1, -1, -1);
	1129	internal_timer_update(machine(),which, data16, -1, -1, -1);
1132	1130	break;
1133	1131
1134	1132	case 0x29:
1135	1133	case 0x2d:
1136	1134	case 0x31:
1137		if (LOG_PORTS) logerror("%05X:80186 Timer %d max A = %04X\n", cpu_get_pc(&space->device()), (offset - 0x29) / 4, data16);
	1135	if (LOG_PORTS) logerror("%05X:80186 Timer %d max A = %04X\n", cpu_get_pc(&space.device()), (offset - 0x29) / 4, data16);
1138	1136	which = (offset - 0x29) / 4;
1139		internal_timer_update(space->machine(),which, -1, data16, -1, -1);
	1137	internal_timer_update(machine(),which, -1, data16, -1, -1);
1140	1138	break;
1141	1139
1142	1140	case 0x2a:
1143	1141	case 0x2e:
1144		if (LOG_PORTS) logerror("%05X:80186 Timer %d max B = %04X\n", cpu_get_pc(&space->device()), (offset - 0x2a) / 4, data16);
	1142	if (LOG_PORTS) logerror("%05X:80186 Timer %d max B = %04X\n", cpu_get_pc(&space.device()), (offset - 0x2a) / 4, data16);
1145	1143	which = (offset - 0x2a) / 4;
1146		internal_timer_update(space->machine(),which, -1, -1, data16, -1);
	1144	internal_timer_update(machine(),which, -1, -1, data16, -1);
1147	1145	break;
1148	1146
1149	1147	case 0x2b:
1150	1148	case 0x2f:
1151	1149	case 0x33:
1152		if (LOG_PORTS) logerror("%05X:80186 Timer %d control = %04X\n", cpu_get_pc(&space->device()), (offset - 0x2b) / 4, data16);
	1150	if (LOG_PORTS) logerror("%05X:80186 Timer %d control = %04X\n", cpu_get_pc(&space.device()), (offset - 0x2b) / 4, data16);
1153	1151	which = (offset - 0x2b) / 4;
1154		internal_timer_update(space->machine(),which, -1, -1, -1, data16);
	1152	internal_timer_update(machine(),which, -1, -1, -1, data16);
1155	1153	break;
1156	1154
1157	1155	case 0x50:
1158		if (LOG_PORTS) logerror("%05X:80186 upper chip select = %04X\n", cpu_get_pc(&space->device()), data16);
1159		state->m_i186.mem.upper = data16 | 0xc038;
	1156	if (LOG_PORTS) logerror("%05X:80186 upper chip select = %04X\n", cpu_get_pc(&space.device()), data16);
	1157	m_i186.mem.upper = data16 | 0xc038;
1160	1158	break;
1161	1159
1162	1160	case 0x51:
1163		if (LOG_PORTS) logerror("%05X:80186 lower chip select = %04X\n", cpu_get_pc(&space->device()), data16);
1164		state->m_i186.mem.lower = (data16 & 0x3fff) | 0x0038; printf("%X",state->m_i186.mem.lower);
	1161	if (LOG_PORTS) logerror("%05X:80186 lower chip select = %04X\n", cpu_get_pc(&space.device()), data16);
	1162	m_i186.mem.lower = (data16 & 0x3fff) | 0x0038; printf("%X",m_i186.mem.lower);
1165	1163	break;
1166	1164
1167	1165	case 0x52:
1168		if (LOG_PORTS) logerror("%05X:80186 peripheral chip select = %04X\n", cpu_get_pc(&space->device()), data16);
1169		state->m_i186.mem.peripheral = data16 | 0x0038;
	1166	if (LOG_PORTS) logerror("%05X:80186 peripheral chip select = %04X\n", cpu_get_pc(&space.device()), data16);
	1167	m_i186.mem.peripheral = data16 | 0x0038;
1170	1168	break;
1171	1169
1172	1170	case 0x53:
1173		if (LOG_PORTS) logerror("%05X:80186 middle chip select = %04X\n", cpu_get_pc(&space->device()), data16);
1174		state->m_i186.mem.middle = data16 | 0x01f8;
	1171	if (LOG_PORTS) logerror("%05X:80186 middle chip select = %04X\n", cpu_get_pc(&space.device()), data16);
	1172	m_i186.mem.middle = data16 | 0x01f8;
1175	1173	break;
1176	1174
1177	1175	case 0x54:
1178		if (LOG_PORTS) logerror("%05X:80186 middle P chip select = %04X\n", cpu_get_pc(&space->device()), data16);
1179		state->m_i186.mem.middle_size = data16 | 0x8038;
	1176	if (LOG_PORTS) logerror("%05X:80186 middle P chip select = %04X\n", cpu_get_pc(&space.device()), data16);
	1177	m_i186.mem.middle_size = data16 | 0x8038;
1180	1178
1181	1179	/* we need to do this at a time when the I86 context is swapped in */
1182	1180	/* this register is generally set once at startup and never again, so it's a good */
1183	1181	/* time to set it up */
1184		device_set_irq_callback(&space->device(), int_callback);
	1182	device_set_irq_callback(&space.device(), int_callback);
1185	1183	break;
1186	1184
1187	1185	case 0x60:
1188	1186	case 0x68:
1189		if (LOG_PORTS) logerror("%05X:80186 DMA%d lower source address = %04X\n", cpu_get_pc(&space->device()), (offset - 0x60) / 8, data16);
	1187	if (LOG_PORTS) logerror("%05X:80186 DMA%d lower source address = %04X\n", cpu_get_pc(&space.device()), (offset - 0x60) / 8, data16);
1190	1188	which = (offset - 0x60) / 8;
1191		state->m_i186.dma[which].source = (state->m_i186.dma[which].source & ~0x0ffff) | (data16 & 0x0ffff);
	1189	m_i186.dma[which].source = (m_i186.dma[which].source & ~0x0ffff) | (data16 & 0x0ffff);
1192	1190	break;
1193	1191
1194	1192	case 0x61:
1195	1193	case 0x69:
1196		if (LOG_PORTS) logerror("%05X:80186 DMA%d upper source address = %04X\n", cpu_get_pc(&space->device()), (offset - 0x61) / 8, data16);
	1194	if (LOG_PORTS) logerror("%05X:80186 DMA%d upper source address = %04X\n", cpu_get_pc(&space.device()), (offset - 0x61) / 8, data16);
1197	1195	which = (offset - 0x61) / 8;
1198		state->m_i186.dma[which].source = (state->m_i186.dma[which].source & ~0xf0000) | ((data16 << 16) & 0xf0000);
	1196	m_i186.dma[which].source = (m_i186.dma[which].source & ~0xf0000) | ((data16 << 16) & 0xf0000);
1199	1197	break;
1200	1198
1201	1199	case 0x62:
1202	1200	case 0x6a:
1203		if (LOG_PORTS) logerror("%05X:80186 DMA%d lower dest address = %04X\n", cpu_get_pc(&space->device()), (offset - 0x62) / 8, data16);
	1201	if (LOG_PORTS) logerror("%05X:80186 DMA%d lower dest address = %04X\n", cpu_get_pc(&space.device()), (offset - 0x62) / 8, data16);
1204	1202	which = (offset - 0x62) / 8;
1205		state->m_i186.dma[which].dest = (state->m_i186.dma[which].dest & ~0x0ffff) | (data16 & 0x0ffff);
	1203	m_i186.dma[which].dest = (m_i186.dma[which].dest & ~0x0ffff) | (data16 & 0x0ffff);
1206	1204	break;
1207	1205
1208	1206	case 0x63:
1209	1207	case 0x6b:
1210		if (LOG_PORTS) logerror("%05X:80186 DMA%d upper dest address = %04X\n", cpu_get_pc(&space->device()), (offset - 0x63) / 8, data16);
	1208	if (LOG_PORTS) logerror("%05X:80186 DMA%d upper dest address = %04X\n", cpu_get_pc(&space.device()), (offset - 0x63) / 8, data16);
1211	1209	which = (offset - 0x63) / 8;
1212		state->m_i186.dma[which].dest = (state->m_i186.dma[which].dest & ~0xf0000) | ((data16 << 16) & 0xf0000);
	1210	m_i186.dma[which].dest = (m_i186.dma[which].dest & ~0xf0000) | ((data16 << 16) & 0xf0000);
1213	1211	break;
1214	1212
1215	1213	case 0x64:
1216	1214	case 0x6c:
1217		if (LOG_PORTS) logerror("%05X:80186 DMA%d transfer count = %04X\n", cpu_get_pc(&space->device()), (offset - 0x64) / 8, data16);
	1215	if (LOG_PORTS) logerror("%05X:80186 DMA%d transfer count = %04X\n", cpu_get_pc(&space.device()), (offset - 0x64) / 8, data16);
1218	1216	which = (offset - 0x64) / 8;
1219		state->m_i186.dma[which].count = data16;
	1217	m_i186.dma[which].count = data16;
1220	1218	break;
1221	1219
1222	1220	case 0x65:
1223	1221	case 0x6d:
1224		if (LOG_PORTS) logerror("%05X:80186 DMA%d control = %04X\n", cpu_get_pc(&space->device()), (offset - 0x65) / 8, data16);
	1222	if (LOG_PORTS) logerror("%05X:80186 DMA%d control = %04X\n", cpu_get_pc(&space.device()), (offset - 0x65) / 8, data16);
1225	1223	which = (offset - 0x65) / 8;
1226		update_dma_control(space->machine(), which, data16);
	1224	update_dma_control(machine(), which, data16);
1227	1225	break;
1228	1226
1229	1227	case 0x7f:
1230		if (LOG_PORTS) logerror("%05X:80186 relocation register = %04X\n", cpu_get_pc(&space->device()), data16);
	1228	if (LOG_PORTS) logerror("%05X:80186 relocation register = %04X\n", cpu_get_pc(&space.device()), data16);
1231	1229
1232	1230	/* we assume here there that this doesn't happen too often */
1233	1231	/* plus, we can't really remove the old memory range, so we also assume that it's */
r14963	r14964
1235	1233	temp = (data16 & 0x0fff) << 8;
1236	1234	if (data16 & 0x1000)
1237	1235	{
1238		space->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM)->install_legacy_read_handler(temp, temp + 0xff, FUNC(nimbus_i186_internal_port_r));
1239		space->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM)->install_legacy_write_handler(temp, temp + 0xff, FUNC(nimbus_i186_internal_port_w));
	1236	machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM)->install_read_handler(temp, temp + 0xff, read16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_r),this));
	1237	machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM)->install_write_handler(temp, temp + 0xff, write16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_w),this));
1240	1238	}
1241	1239	else
1242	1240	{
1243	1241	temp &= 0xffff;
1244		space->machine().device(MAINCPU_TAG)->memory().space(AS_IO)->install_legacy_read_handler(temp, temp + 0xff, FUNC(nimbus_i186_internal_port_r));
1245		space->machine().device(MAINCPU_TAG)->memory().space(AS_IO)->install_legacy_write_handler(temp, temp + 0xff, FUNC(nimbus_i186_internal_port_w));
	1242	machine().device(MAINCPU_TAG)->memory().space(AS_IO)->install_read_handler(temp, temp + 0xff, read16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_r),this));
	1243	machine().device(MAINCPU_TAG)->memory().space(AS_IO)->install_write_handler(temp, temp + 0xff, write16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_w),this));
1246	1244	}
1247	1245	break;
1248	1246
1249	1247	default:
1250		logerror("%05X:80186 port %02X = %04X\n", cpu_get_pc(&space->device()), offset, data16);
	1248	logerror("%05X:80186 port %02X = %04X\n", cpu_get_pc(&space.device()), offset, data16);
1251	1249	break;
1252	1250	}
1253	1251	}
r14963	r14964
2064	2062	}
2065	2063	}
2066	2064
2067		READ8_HANDLER( nimbus_mcu_r )
	2065	READ8_MEMBER(rmnimbus_state::nimbus_mcu_r)
2068	2066	{
2069		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2070		return state->m_mcu_reg080;
	2067	return m_mcu_reg080;
2071	2068	}
2072	2069
2073		WRITE8_HANDLER( nimbus_mcu_w )
	2070	WRITE8_MEMBER(rmnimbus_state::nimbus_mcu_w)
2074	2071	{
2075		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2076		state->m_mcu_reg080=data;
	2072	m_mcu_reg080=data;
2077	2073
2078		nimbus_bank_memory(space->machine());
	2074	nimbus_bank_memory(machine());
2079	2075	}
2080	2076
2081	2077	static void memory_reset(running_machine &machine)
r14963	r14964
2085	2081	nimbus_bank_memory(machine);
2086	2082	}
2087	2083
2088		READ16_HANDLER( nimbus_io_r )
	2084	READ16_MEMBER(rmnimbus_state::nimbus_io_r)
2089	2085	{
2090		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2091		int pc=cpu_get_pc(&space->device());
	2086	int pc=cpu_get_pc(&space.device());
2092	2087
2093		logerror("Nimbus IOR at pc=%08X from %04X mask=%04X, data=%04X\n",pc,(offset*2)+0x30,mem_mask,state->m_IOPorts[offset]);
	2088	logerror("Nimbus IOR at pc=%08X from %04X mask=%04X, data=%04X\n",pc,(offset*2)+0x30,mem_mask,m_IOPorts[offset]);
2094	2089
2095	2090	switch (offset*2)
2096	2091	{
2097		default         : return state->m_IOPorts[offset];
	2092	default         : return m_IOPorts[offset];
2098	2093	}
2099	2094	return 0;
2100	2095	}
2101	2096
2102		WRITE16_HANDLER( nimbus_io_w )
	2097	WRITE16_MEMBER(rmnimbus_state::nimbus_io_w)
2103	2098	{
2104		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2105		int pc=cpu_get_pc(&space->device());
	2099	int pc=cpu_get_pc(&space.device());
2106	2100
2107	2101	logerror("Nimbus IOW at %08X write of %04X to %04X mask=%04X\n",pc,data,(offset*2)+0x30,mem_mask);
2108	2102
2109	2103	switch (offset*2)
2110	2104	{
2111		default         : COMBINE_DATA(&state->m_IOPorts[offset]); break;
	2105	default         : COMBINE_DATA(&m_IOPorts[offset]); break;
2112	2106	}
2113	2107	}
2114	2108
r14963	r14964
2299	2293	7   !REQ from HDD
2300	2294	*/
2301	2295
2302		READ8_HANDLER( nimbus_disk_r )
	2296	READ8_MEMBER(rmnimbus_state::nimbus_disk_r)
2303	2297	{
2304		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2305	2298	int result = 0;
2306		device_t *fdc = space->machine().device(FDC_TAG);
2307		device_t *hdc = space->machine().device(SCSIBUS_TAG);
	2299	device_t *fdc = machine().device(FDC_TAG);
	2300	device_t *hdc = machine().device(SCSIBUS_TAG);
2308	2301
2309		int pc=cpu_get_pc(&space->device());
2310		device_t *drive = space->machine().device(nimbus_wd17xx_interface.floppy_drive_tags[FDC_DRIVE()]);
	2302	int pc=cpu_get_pc(&space.device());
	2303	rmnimbus_state *state = machine().driver_data<rmnimbus_state>();
	2304	device_t *drive = machine().device(nimbus_wd17xx_interface.floppy_drive_tags[FDC_DRIVE()]);
2311	2305
2312	2306	switch(offset*2)
2313	2307	{
r14963	r14964
2325	2319	result = wd17xx_data_r(fdc, 0);
2326	2320	break;
2327	2321	case 0x10 :
2328		state->m_nimbus_drives.reg410_in &= ~FDC_BITS_410;
2329		state->m_nimbus_drives.reg410_in |= (FDC_MOTOR() ? FDC_MOTOR_MASKI : 0x00);
2330		state->m_nimbus_drives.reg410_in |= (floppy_drive_get_flag_state(drive, FLOPPY_DRIVE_INDEX) ? 0x00 : FDC_INDEX_MASK);
2331		state->m_nimbus_drives.reg410_in |= (floppy_drive_get_flag_state(drive, FLOPPY_DRIVE_READY) ? FDC_READY_MASK : 0x00);
	2322	m_nimbus_drives.reg410_in &= ~FDC_BITS_410;
	2323	m_nimbus_drives.reg410_in |= (FDC_MOTOR() ? FDC_MOTOR_MASKI : 0x00);
	2324	m_nimbus_drives.reg410_in |= (floppy_drive_get_flag_state(drive, FLOPPY_DRIVE_INDEX) ? 0x00 : FDC_INDEX_MASK);
	2325	m_nimbus_drives.reg410_in |= (floppy_drive_get_flag_state(drive, FLOPPY_DRIVE_READY) ? FDC_READY_MASK : 0x00);
2332	2326
2333	2327	// Flip inverted bits
2334		result=state->m_nimbus_drives.reg410_in ^ INV_BITS_410;
	2328	result=m_nimbus_drives.reg410_in ^ INV_BITS_410;
2335	2329	break;
2336	2330	case 0x18 :
2337	2331	result = scsi_data_r(hdc);
2338		hdc_post_rw(space->machine());
	2332	hdc_post_rw(machine());
2339	2333	default:
2340	2334	break;
2341	2335	}
r14963	r14964
2368	2362	2   SCSI IRQ Enable
2369	2363	*/
2370	2364
2371		WRITE8_HANDLER( nimbus_disk_w )
	2365	WRITE8_MEMBER(rmnimbus_state::nimbus_disk_w)
2372	2366	{
2373		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2374		device_t *fdc = space->machine().device(FDC_TAG);
2375		device_t *hdc = space->machine().device(SCSIBUS_TAG);
2376		int                 pc=cpu_get_pc(&space->device());
2377		UINT8               reg400_old = state->m_nimbus_drives.reg400;
	2367	device_t *fdc = machine().device(FDC_TAG);
	2368	device_t *hdc = machine().device(SCSIBUS_TAG);
	2369	int                 pc=cpu_get_pc(&space.device());
	2370	UINT8               reg400_old = m_nimbus_drives.reg400;
2378	2371
2379	2372	if(LOG_DISK_FDD && ((offset*2)<=0x10))
2380	2373	logerror("Nimbus FDCW at %05X write of %02X to %04X\n",pc,data,(offset*2)+0x400);
r14963	r14964
2382	2375	if((LOG_DISK_HDD) && (((offset*2)>=0x10) || (offset==0)))
2383	2376	logerror("Nimbus HDCW at %05X write of %02X to %04X\n",pc,data,(offset*2)+0x400);
2384	2377
	2378	rmnimbus_state *state = machine().driver_data<rmnimbus_state>();
2385	2379	switch(offset*2)
2386	2380	{
2387	2381	case 0x00 :
2388		state->m_nimbus_drives.reg400=data;
2389
	2382	m_nimbus_drives.reg400=data;
2390	2383	wd17xx_set_drive(fdc,FDC_DRIVE());
2391	2384	wd17xx_set_side(fdc, FDC_SIDE());
2392	2385
r14963	r14964
2395	2388
2396	2389	// if we enable hdc drq with a pending condition, act on it
2397	2390	if((data & HDC_DRQ_MASK) && (~reg400_old & HDC_DRQ_MASK))
2398		hdc_drq(space->machine());
	2391	hdc_drq(machine());
2399	2392
2400	2393	break;
2401	2394	case 0x08 :
r14963	r14964
2411	2404	wd17xx_data_w(fdc, 0, data);
2412	2405	break;
2413	2406	case 0x10 :
2414		hdc_ctrl_write(space->machine(),data);
	2407	hdc_ctrl_write(machine(),data);
2415	2408	break;
2416	2409
2417	2410	case 0x18 :
2418	2411	scsi_data_w(hdc, data);
2419		hdc_post_rw(space->machine());
	2412	hdc_post_rw(machine());
2420	2413	break;
2421	2414	}
2422	2415	}
r14963	r14964
2544	2537	}
2545	2538	#endif
2546	2539
2547		READ8_HANDLER( nimbus_pc8031_r )
	2540	READ8_MEMBER(rmnimbus_state::nimbus_pc8031_r)
2548	2541	{
2549		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2550		int pc=cpu_get_pc(&space->device());
	2542	int pc=cpu_get_pc(&space.device());
2551	2543	UINT8   result;
2552	2544
2553	2545	switch(offset*2)
2554	2546	{
2555		case 0x00   : result=state->m_ipc_interface.ipc_out;
2556		state->m_ipc_interface.status_in   &= ~IPC_IN_READ_PEND;
2557		state->m_ipc_interface.status_out  &= ~IPC_OUT_BYTE_AVAIL;
	2547	case 0x00   : result=m_ipc_interface.ipc_out;
	2548	m_ipc_interface.status_in   &= ~IPC_IN_READ_PEND;
	2549	m_ipc_interface.status_out  &= ~IPC_OUT_BYTE_AVAIL;
2558	2550	break;
2559	2551
2560		case 0x02   : result=state->m_ipc_interface.status_out;
	2552	case 0x02   : result=m_ipc_interface.status_out;
2561	2553	break;
2562	2554
2563	2555	default : result=0; break;
r14963	r14964
2569	2561	return result;
2570	2562	}
2571	2563
2572		WRITE8_HANDLER( nimbus_pc8031_w )
	2564	WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_w)
2573	2565	{
2574		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2575		int pc=cpu_get_pc(&space->device());
	2566	int pc=cpu_get_pc(&space.device());
2576	2567
2577	2568	switch(offset*2)
2578	2569	{
2579		case 0x00   : state->m_ipc_interface.ipc_in=data;
2580		state->m_ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
2581		state->m_ipc_interface.status_in   &= ~IPC_IN_ADDR;
2582		state->m_ipc_interface.status_out  |= IPC_OUT_READ_PEND;
	2570	case 0x00   : m_ipc_interface.ipc_in=data;
	2571	m_ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
	2572	m_ipc_interface.status_in   &= ~IPC_IN_ADDR;
	2573	m_ipc_interface.status_out  |= IPC_OUT_READ_PEND;
2583	2574	break;
2584	2575
2585		case 0x02   : state->m_ipc_interface.ipc_in=data;
2586		state->m_ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
2587		state->m_ipc_interface.status_in   |= IPC_IN_ADDR;
2588		state->m_ipc_interface.status_out  |= IPC_OUT_READ_PEND;
	2576	case 0x02   : m_ipc_interface.ipc_in=data;
	2577	m_ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
	2578	m_ipc_interface.status_in   |= IPC_IN_ADDR;
	2579	m_ipc_interface.status_out  |= IPC_OUT_READ_PEND;
2589	2580	break;
2590	2581	}
2591	2582
r14963	r14964
2596	2587
2597	2588	/* 8031/8051 Peripheral controler 8031/8051 side */
2598	2589
2599		READ8_HANDLER( nimbus_pc8031_iou_r )
	2590	READ8_MEMBER(rmnimbus_state::nimbus_pc8031_iou_r)
2600	2591	{
2601		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2602		int pc=cpu_get_pc(&space->device());
	2592	int pc=cpu_get_pc(&space.device());
2603	2593	UINT8   result = 0;
2604	2594
2605	2595	switch (offset & 0x01)
2606	2596	{
2607		case 0x00   : result=state->m_ipc_interface.ipc_in;
2608		state->m_ipc_interface.status_out  &= ~IPC_OUT_READ_PEND;
2609		state->m_ipc_interface.status_in   &= ~IPC_IN_BYTE_AVAIL;
	2597	case 0x00   : result=m_ipc_interface.ipc_in;
	2598	m_ipc_interface.status_out  &= ~IPC_OUT_READ_PEND;
	2599	m_ipc_interface.status_in   &= ~IPC_IN_BYTE_AVAIL;
2610	2600	break;
2611	2601
2612		case 0x01   : result=state->m_ipc_interface.status_in;
	2602	case 0x01   : result=m_ipc_interface.status_in;
2613	2603	break;
2614	2604	}
2615	2605
2616		if(((offset==2) || (offset==3)) && (state->m_iou_reg092 & PC8031_INT_ENABLE))
2617		external_int(space->machine(),0,EXTERNAL_INT_PC8031_8C);
	2606	if(((offset==2) || (offset==3)) && (m_iou_reg092 & PC8031_INT_ENABLE))
	2607	external_int(machine(),0,EXTERNAL_INT_PC8031_8C);
2618	2608
2619	2609	if(LOG_PC8031)
2620	2610	logerror("8031: PCIOR %04X read of %04X returns %02X\n",pc,offset,result);
r14963	r14964
2622	2612	return result;
2623	2613	}
2624	2614
2625		WRITE8_HANDLER( nimbus_pc8031_iou_w )
	2615	WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_iou_w)
2626	2616	{
2627		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2628		int pc=cpu_get_pc(&space->device());
	2617	int pc=cpu_get_pc(&space.device());
2629	2618
2630	2619	if(LOG_PC8031)
2631	2620	logerror("8031 PCIOW %04X write of %02X to %04X\n",pc,data,offset);
2632	2621
2633	2622	switch(offset & 0x03)
2634	2623	{
2635		case 0x00   : state->m_ipc_interface.ipc_out=data;
2636		state->m_ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
2637		state->m_ipc_interface.status_out  &= ~IPC_OUT_ADDR;
2638		state->m_ipc_interface.status_in   |= IPC_IN_READ_PEND;
	2624	case 0x00   : m_ipc_interface.ipc_out=data;
	2625	m_ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
	2626	m_ipc_interface.status_out  &= ~IPC_OUT_ADDR;
	2627	m_ipc_interface.status_in   |= IPC_IN_READ_PEND;
2639	2628	break;
2640	2629
2641		case 0x01   : state->m_ipc_interface.ipc_out=data;
2642		state->m_ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
2643		state->m_ipc_interface.status_out   |= IPC_OUT_ADDR;
2644		state->m_ipc_interface.status_in    |= IPC_IN_READ_PEND;
	2630	case 0x01   : m_ipc_interface.ipc_out=data;
	2631	m_ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
	2632	m_ipc_interface.status_out   |= IPC_OUT_ADDR;
	2633	m_ipc_interface.status_in    |= IPC_IN_READ_PEND;
2645	2634	break;
2646	2635
2647		case 0x02   : state->m_ipc_interface.ipc_out=data;
2648		state->m_ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
2649		state->m_ipc_interface.status_out  &= ~IPC_OUT_ADDR;
2650		state->m_ipc_interface.status_in   |= IPC_IN_READ_PEND;
2651		if(state->m_iou_reg092 & PC8031_INT_ENABLE)
2652		external_int(space->machine(),0,EXTERNAL_INT_PC8031_8F);
	2636	case 0x02   : m_ipc_interface.ipc_out=data;
	2637	m_ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
	2638	m_ipc_interface.status_out  &= ~IPC_OUT_ADDR;
	2639	m_ipc_interface.status_in   |= IPC_IN_READ_PEND;
	2640	if(m_iou_reg092 & PC8031_INT_ENABLE)
	2641	external_int(machine(),0,EXTERNAL_INT_PC8031_8F);
2653	2642	break;
2654	2643
2655		case 0x03   : state->m_ipc_interface.ipc_out=data;
2656		//state->m_ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
2657		state->m_ipc_interface.status_out   |= IPC_OUT_ADDR;
2658		state->m_ipc_interface.status_in    |= IPC_IN_READ_PEND;
2659		if(state->m_iou_reg092 & PC8031_INT_ENABLE)
2660		external_int(space->machine(),0,EXTERNAL_INT_PC8031_8E);
	2644	case 0x03   : m_ipc_interface.ipc_out=data;
	2645	//m_ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
	2646	m_ipc_interface.status_out   |= IPC_OUT_ADDR;
	2647	m_ipc_interface.status_in    |= IPC_IN_READ_PEND;
	2648	if(m_iou_reg092 & PC8031_INT_ENABLE)
	2649	external_int(machine(),0,EXTERNAL_INT_PC8031_8E);
2661	2650	break;
2662	2651	}
2663	2652	}
2664	2653
2665		READ8_HANDLER( nimbus_pc8031_port_r )
	2654	READ8_MEMBER(rmnimbus_state::nimbus_pc8031_port_r)
2666	2655	{
2667		device_t *er59256 = space->machine().device(ER59256_TAG);
2668		int pc=cpu_get_pc(&space->device());
	2656	device_t *er59256 = machine().device(ER59256_TAG);
	2657	int pc=cpu_get_pc(&space.device());
2669	2658	UINT8   result = 0;
2670	2659
2671	2660	if(LOG_PC8031_PORT)
r14963	r14964
2679	2668	return result;
2680	2669	}
2681	2670
2682		WRITE8_HANDLER( nimbus_pc8031_port_w )
	2671	WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_port_w)
2683	2672	{
2684		device_t *er59256 = space->machine().device(ER59256_TAG);
2685		int pc=cpu_get_pc(&space->device());
	2673	device_t *er59256 = machine().device(ER59256_TAG);
	2674	int pc=cpu_get_pc(&space.device());
2686	2675
2687	2676	switch (offset)
2688	2677	{
r14963	r14964
2696	2685
2697	2686
2698	2687	/* IO Unit */
2699		READ8_HANDLER( nimbus_iou_r )
	2688	READ8_MEMBER(rmnimbus_state::nimbus_iou_r)
2700	2689	{
2701		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2702		int pc=cpu_get_pc(&space->device());
	2690	int pc=cpu_get_pc(&space.device());
2703	2691	UINT8   result=0;
2704	2692
2705	2693	if(offset==0)
2706	2694	{
2707		result=state->m_iou_reg092;
	2695	result=m_iou_reg092;
2708	2696	}
2709	2697
2710	2698	if(LOG_IOU)
r14963	r14964
2713	2701	return result;
2714	2702	}
2715	2703
2716		WRITE8_HANDLER( nimbus_iou_w )
	2704	WRITE8_MEMBER(rmnimbus_state::nimbus_iou_w)
2717	2705	{
2718		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2719		int pc=cpu_get_pc(&space->device());
2720		device_t *msm5205 = space->machine().device(MSM5205_TAG);
	2706	int pc=cpu_get_pc(&space.device());
	2707	device_t *msm5205 = machine().device(MSM5205_TAG);
2721	2708
2722	2709	if(LOG_IOU)
2723	2710	logerror("Nimbus IOUW %08X write of %02X to %04X\n",pc,data,(offset*2)+0x92);
2724	2711
2725	2712	if(offset==0)
2726	2713	{
2727		state->m_iou_reg092=data;
	2714	m_iou_reg092=data;
2728	2715	msm5205_reset_w(msm5205, (data & MSM5205_INT_ENABLE) ? 0 : 1);
2729	2716	}
2730	2717	}
r14963	r14964
2764	2751	state->m_ay8910_a=0;
2765	2752	}
2766	2753
2767		READ8_HANDLER( nimbus_sound_ay8910_r )
	2754	READ8_MEMBER(rmnimbus_state::nimbus_sound_ay8910_r)
2768	2755	{
2769		device_t *ay8910 = space->machine().device(AY8910_TAG);
	2756	device_t *ay8910 = machine().device(AY8910_TAG);
2770	2757	UINT8   result=0;
2771	2758
2772	2759	if ((offset*2)==0)
r14963	r14964
2775	2762	return result;
2776	2763	}
2777	2764
2778		WRITE8_HANDLER( nimbus_sound_ay8910_w )
	2765	WRITE8_MEMBER(rmnimbus_state::nimbus_sound_ay8910_w)
2779	2766	{
2780		int pc=cpu_get_pc(&space->device());
2781		device_t *ay8910 = space->machine().device(AY8910_TAG);
	2767	int pc=cpu_get_pc(&space.device());
	2768	device_t *ay8910 = machine().device(AY8910_TAG);
2782	2769
2783	2770	if(LOG_SOUND)
2784	2771	logerror("Nimbus SoundW %05X write of %02X to %04X\n",pc,data,(offset*2)+0xE0);
r14963	r14964
2791	2778
2792	2779	}
2793	2780
2794		WRITE8_HANDLER( nimbus_sound_ay8910_porta_w )
	2781	WRITE8_MEMBER(rmnimbus_state::nimbus_sound_ay8910_porta_w)
2795	2782	{
2796		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2797		device_t *msm5205 = space->machine().device(MSM5205_TAG);
	2783	device_t *msm5205 = machine().device(MSM5205_TAG);
2798	2784
2799	2785	msm5205_data_w(msm5205, data);
2800	2786
2801	2787	// Mouse code needs a copy of this.
2802		state->m_ay8910_a=data;
	2788	m_ay8910_a=data;
2803	2789	}
2804	2790
2805		WRITE8_HANDLER( nimbus_sound_ay8910_portb_w )
	2791	WRITE8_MEMBER(rmnimbus_state::nimbus_sound_ay8910_portb_w)
2806	2792	{
2807		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
2808		device_t *msm5205 = space->machine().device(MSM5205_TAG);
	2793	device_t *msm5205 = machine().device(MSM5205_TAG);
2809	2794
2810		if((data & 0x07)!=state->m_last_playmode)
	2795	if((data & 0x07)!=m_last_playmode)
2811	2796	{
2812		state->m_last_playmode=(data & 0x07);
2813		msm5205_playmode_w(msm5205, state->m_last_playmode);
	2797	m_last_playmode=(data & 0x07);
	2798	msm5205_playmode_w(msm5205, m_last_playmode);
2814	2799	}
2815	2800	}
2816	2801
r14963	r14964
2980	2965	state->m_intstate_y=intstate_y;
2981	2966	}
2982	2967
2983		READ8_HANDLER( nimbus_mouse_js_r )
	2968	READ8_MEMBER(rmnimbus_state::nimbus_mouse_js_r)
2984	2969	{
2985		rmnimbus_state *drvstate = space->machine().driver_data<rmnimbus_state>();
2986	2970	/*
2987	2971
2988	2972	bit     description
r14963	r14964
2998	2982
2999	2983	*/
3000	2984	UINT8 result;
3001		//int pc=cpu_get_pc(space->machine().device(MAINCPU_TAG));
	2985	//int pc=cpu_get_pc(machine().device(MAINCPU_TAG));
	2986	_mouse_joy_state *state = &m_nimbus_mouse;
3002	2987
3003		_mouse_joy_state *state = &drvstate->m_nimbus_mouse;
3004
3005		if (input_port_read(space->machine(), "config") & 0x01)
	2988	if (input_port_read(machine(), "config") & 0x01)
3006	2989	{
3007	2990	result=state->m_reg0a4;
3008	2991	//logerror("mouse_js_r: pc=%05X, result=%02X\n",pc,result);
3009	2992	}
3010	2993	else
3011	2994	{
3012		result=input_port_read_safe(space->machine(), JOYSTICK0_TAG, 0xff);
	2995	result=input_port_read_safe(machine(), JOYSTICK0_TAG, 0xff);
3013	2996	}
3014	2997
3015	2998	return result;
3016	2999	}
3017	3000
3018		WRITE8_HANDLER( nimbus_mouse_js_w )
	3001	WRITE8_MEMBER(rmnimbus_state::nimbus_mouse_js_w)
3019	3002	{
3020	3003	}
3021	3004

src/mess/machine/pp01.c

r14963	r14964
13	13	#include "machine/ram.h"
14	14
15	15
16		WRITE8_HANDLER( pp01_video_write_mode_w )
	16	WRITE8_MEMBER(pp01_state::pp01_video_write_mode_w)
17	17	{
18		pp01_state *state = space->machine().driver_data<pp01_state>();
19		state->m_video_write_mode = data & 0x0f;
	18	m_video_write_mode = data & 0x0f;
20	19	}
21	20
22	21	static void pp01_video_w(running_machine &machine,UINT8 block,UINT16 offset,UINT8 data,UINT8 part)
r14963	r14964
55	54	}
56	55	}
57	56
58		static WRITE8_HANDLER (pp01_video_r_1_w)
	57	WRITE8_MEMBER(pp01_state::pp01_video_r_1_w)
59	58	{
60		pp01_video_w(space->machine(),0,offset,data,0);
	59	pp01_video_w(machine(),0,offset,data,0);
61	60	}
62		static WRITE8_HANDLER (pp01_video_g_1_w)
	61	WRITE8_MEMBER(pp01_state::pp01_video_g_1_w)
63	62	{
64		pp01_video_w(space->machine(),1,offset,data,0);
	63	pp01_video_w(machine(),1,offset,data,0);
65	64	}
66		static WRITE8_HANDLER (pp01_video_b_1_w)
	65	WRITE8_MEMBER(pp01_state::pp01_video_b_1_w)
67	66	{
68		pp01_video_w(space->machine(),2,offset,data,0);
	67	pp01_video_w(machine(),2,offset,data,0);
69	68	}
70	69
71		static WRITE8_HANDLER (pp01_video_r_2_w)
	70	WRITE8_MEMBER(pp01_state::pp01_video_r_2_w)
72	71	{
73		pp01_video_w(space->machine(),0,offset,data,1);
	72	pp01_video_w(machine(),0,offset,data,1);
74	73	}
75		static WRITE8_HANDLER (pp01_video_g_2_w)
	74	WRITE8_MEMBER(pp01_state::pp01_video_g_2_w)
76	75	{
77		pp01_video_w(space->machine(),1,offset,data,1);
	76	pp01_video_w(machine(),1,offset,data,1);
78	77	}
79		static WRITE8_HANDLER (pp01_video_b_2_w)
	78	WRITE8_MEMBER(pp01_state::pp01_video_b_2_w)
80	79	{
81		pp01_video_w(space->machine(),2,offset,data,1);
	80	pp01_video_w(machine(),2,offset,data,1);
82	81	}
83	82
84	83
85	84	static void pp01_set_memory(running_machine &machine,UINT8 block, UINT8 data)
86	85	{
	86	pp01_state *state = machine.driver_data<pp01_state>();
87	87	UINT8 *mem = machine.region("maincpu")->base();
88	88	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
89	89	UINT16 startaddr = block*0x1000;
r14963	r14964
96	96	space->install_read_bank (startaddr, endaddr, bank);
97	97	switch(data) {
98	98	case 0xe6 :
99		space->install_legacy_write_handler(startaddr, endaddr, FUNC(pp01_video_r_1_w));
	99	space->install_write_handler(startaddr, endaddr, write8_delegate(FUNC(pp01_state::pp01_video_r_1_w),state));
100	100	break;
101	101	case 0xe7 :
102		space->install_legacy_write_handler(startaddr, endaddr, FUNC(pp01_video_r_2_w));
	102	space->install_write_handler(startaddr, endaddr, write8_delegate(FUNC(pp01_state::pp01_video_r_2_w),state));
103	103	break;
104	104	case 0xea :
105		space->install_legacy_write_handler(startaddr, endaddr, FUNC(pp01_video_g_1_w));
	105	space->install_write_handler(startaddr, endaddr, write8_delegate(FUNC(pp01_state::pp01_video_g_1_w),state));
106	106	break;
107	107	case 0xeb :
108		space->install_legacy_write_handler(startaddr, endaddr, FUNC(pp01_video_g_2_w));
	108	space->install_write_handler(startaddr, endaddr, write8_delegate(FUNC(pp01_state::pp01_video_g_2_w),state));
109	109	break;
110	110	case 0xee :
111		space->install_legacy_write_handler(startaddr, endaddr, FUNC(pp01_video_b_1_w));
	111	space->install_write_handler(startaddr, endaddr, write8_delegate(FUNC(pp01_state::pp01_video_b_1_w),state));
112	112	break;
113	113	case 0xef :
114		space->install_legacy_write_handler(startaddr, endaddr, FUNC(pp01_video_b_2_w));
	114	space->install_write_handler(startaddr, endaddr, write8_delegate(FUNC(pp01_state::pp01_video_b_2_w),state));
115	115	break;
116	116
117	117	default :
r14963	r14964
141	141	}
142	142	}
143	143
144		WRITE8_HANDLER (pp01_mem_block_w)
	144	WRITE8_MEMBER(pp01_state::pp01_mem_block_w)
145	145	{
146		pp01_state *state = space->machine().driver_data<pp01_state>();
147		state->m_memory_block[offset] = data;
148		pp01_set_memory(space->machine(), offset, data);
	146	m_memory_block[offset] = data;
	147	pp01_set_memory(machine(), offset, data);
149	148	}
150	149
151		READ8_HANDLER (pp01_mem_block_r)
	150	READ8_MEMBER(pp01_state::pp01_mem_block_r)
152	151	{
153		pp01_state *state = space->machine().driver_data<pp01_state>();
154		return   state->m_memory_block[offset];
	152	return   m_memory_block[offset];
155	153	}
156	154
157	155	MACHINE_START(pp01)

src/mess/machine/isa_ibm_mfc.c

r14963	r14964
324	324	//  YM-2164
325	325	//-------------------------------------------------
326	326
327		static void ibm_mfc_ym_irq(device_t *device, int state)
	327
	328	WRITE_LINE_MEMBER(isa8_ibm_mfc_device::ibm_mfc_ym_irq)
328	329	{
329		isa8_ibm_mfc_device *mfc = downcast<isa8_ibm_mfc_device *>(device->owner());
330
331		mfc->set_z80_interrupt(Z80_IRQ_YM, state);
	330	set_z80_interrupt(Z80_IRQ_YM, state);
332	331	}
333	332
334	333	static const ym2151_interface ibm_mfc_ym2151_interface =
335	334	{
336		ibm_mfc_ym_irq
	335	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, isa8_ibm_mfc_device, ibm_mfc_ym_irq),
	336	DEVCB_NULL
337	337	};
338	338
339	339

src/mess/machine/isa_ibm_mfc.h

r14963	r14964
54	54	DECLARE_WRITE_LINE_MEMBER( d8253_clk0_out );
55	55	DECLARE_WRITE_LINE_MEMBER( d8253_clk1_out );
56	56	DECLARE_WRITE_LINE_MEMBER( d8253_clk2_out );
	57
	58	DECLARE_WRITE_LINE_MEMBER( ibm_mfc_ym_irq );
57	59
58	60	void                     set_z80_interrupt(int src, int state);
59	61

src/mess/machine/ecb_grip.c

r14963	r14964
749	749	m_video_ram = auto_alloc_array(machine(), UINT8, VIDEORAM_SIZE);
750	750
751	751	// setup GRIP memory banking
752		memory_configure_bank(*this, "videoram", 0, 2, m_video_ram, 0x8000);
753		memory_set_bank(*this, "videoram", 0);
	752	memory_configure_bank(machine(), "videoram", 0, 2, m_video_ram, 0x8000);
	753	memory_set_bank(machine(), "videoram", 0);
754	754
755	755	// allocate keyboard scan timer
756	756	m_kb_timer = timer_alloc();
r14963	r14964
842	842	{
843	843	m_page = BIT(data, 7);
844	844
845		memory_set_bank(*this, "videoram", m_page);
	845	memory_set_bank(machine(), "videoram", m_page);
846	846	}
847	847
848	848

src/mess/machine/pk8020.c

r14963	r14964
18	18	static void pk8020_set_bank(running_machine &machine,UINT8 data);
19	19
20	20
21		static READ8_HANDLER( keyboard_r )
	21	READ8_MEMBER(pk8020_state::keyboard_r)
22	22	{
23	23	static const char *const keynames[] = {
24	24	"LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7",
r14963	r14964
28	28	UINT8 line = 0;
29	29	if (offset & 0x100)  line=8;
30	30
31		if (offset & 0x0001) retVal|=input_port_read(space->machine(),keynames[line]);
	31	if (offset & 0x0001) retVal|=input_port_read(machine(),keynames[line]);
32	32	line++;
33		if (offset & 0x0002) retVal|=input_port_read(space->machine(),keynames[line]);
	33	if (offset & 0x0002) retVal|=input_port_read(machine(),keynames[line]);
34	34	line++;
35		if (offset & 0x0004) retVal|=input_port_read(space->machine(),keynames[line]);
	35	if (offset & 0x0004) retVal|=input_port_read(machine(),keynames[line]);
36	36	line++;
37		if (offset & 0x0008) retVal|=input_port_read(space->machine(),keynames[line]);
	37	if (offset & 0x0008) retVal|=input_port_read(machine(),keynames[line]);
38	38	line++;
39		if (offset & 0x0010) retVal|=input_port_read(space->machine(),keynames[line]);
	39	if (offset & 0x0010) retVal|=input_port_read(machine(),keynames[line]);
40	40	line++;
41		if (offset & 0x0020) retVal|=input_port_read(space->machine(),keynames[line]);
	41	if (offset & 0x0020) retVal|=input_port_read(machine(),keynames[line]);
42	42	line++;
43		if (offset & 0x0040) retVal|=input_port_read(space->machine(),keynames[line]);
	43	if (offset & 0x0040) retVal|=input_port_read(machine(),keynames[line]);
44	44	line++;
45		if (offset & 0x0080) retVal|=input_port_read(space->machine(),keynames[line]);
	45	if (offset & 0x0080) retVal|=input_port_read(machine(),keynames[line]);
46	46	line++;
47	47
48	48	return retVal;
49	49	}
50	50
51		static READ8_HANDLER(sysreg_r)
	51	READ8_MEMBER(pk8020_state::sysreg_r)
52	52	{
53		return space->machine().device<ram_device>(RAM_TAG)->pointer()[offset];
	53	return machine().device<ram_device>(RAM_TAG)->pointer()[offset];
54	54	}
55		static WRITE8_HANDLER(sysreg_w)
	55	WRITE8_MEMBER(pk8020_state::sysreg_w)
56	56	{
57		pk8020_state *state = space->machine().driver_data<pk8020_state>();
58	57	if (BIT(offset,7)==0) {
59		pk8020_set_bank(space->machine(),data >> 2);
	58	pk8020_set_bank(machine(),data >> 2);
60	59	} else if (BIT(offset,6)==0) {
61	60	// Color
62		state->m_color = data;
	61	m_color = data;
63	62	} else if (BIT(offset,2)==0) {
64	63	// Palette set
65	64	UINT8 number = data & 0x0f;
r14963	r14964
68	67	UINT8 r = ((color & 0x04) ? 0xC0 : 0) + i;
69	68	UINT8 g = ((color & 0x02) ? 0xC0 : 0) + i;
70	69	UINT8 b = ((color & 0x01) ? 0xC0 : 0) + i;
71		palette_set_color( space->machine(), number, MAKE_RGB(r,g,b) );
	70	palette_set_color( machine(), number, MAKE_RGB(r,g,b) );
72	71	}
73	72	}
74	73
75		static READ8_HANDLER(text_r)
	74	READ8_MEMBER(pk8020_state::text_r)
76	75	{
77		pk8020_state *state = space->machine().driver_data<pk8020_state>();
78		if (state->m_attr == 3) state->m_text_attr=space->machine().device<ram_device>(RAM_TAG)->pointer()[0x40400+offset];
79		return space->machine().device<ram_device>(RAM_TAG)->pointer()[0x40000+offset];
	76	if (m_attr == 3) m_text_attr=machine().device<ram_device>(RAM_TAG)->pointer()[0x40400+offset];
	77	return machine().device<ram_device>(RAM_TAG)->pointer()[0x40000+offset];
80	78	}
81	79
82		static WRITE8_HANDLER(text_w)
	80	WRITE8_MEMBER(pk8020_state::text_w)
83	81	{
84		pk8020_state *state = space->machine().driver_data<pk8020_state>();
85		UINT8 *ram = space->machine().device<ram_device>(RAM_TAG)->pointer();
	82	UINT8 *ram = machine().device<ram_device>(RAM_TAG)->pointer();
86	83	ram[0x40000+offset] = data;
87		switch (state->m_attr) {
	84	switch (m_attr) {
88	85	case 0: break;
89	86	case 1: ram[0x40400+offset]=0x01;break;
90	87	case 2: ram[0x40400+offset]=0x00;break;
91		case 3: ram[0x40400+offset]=state->m_text_attr;break;
	88	case 3: ram[0x40400+offset]=m_text_attr;break;
92	89	}
93	90	}
94	91
95		static READ8_HANDLER(gzu_r)
	92	READ8_MEMBER(pk8020_state::gzu_r)
96	93	{
97		pk8020_state *state = space->machine().driver_data<pk8020_state>();
98		UINT8 *addr = space->machine().device<ram_device>(RAM_TAG)->pointer() + 0x10000 + (state->m_video_page_access * 0xC000);
	94	UINT8 *addr = machine().device<ram_device>(RAM_TAG)->pointer() + 0x10000 + (m_video_page_access * 0xC000);
99	95	UINT8 p0 = addr[offset];
100	96	UINT8 p1 = addr[offset + 0x4000];
101	97	UINT8 p2 = addr[offset + 0x8000];
102	98	UINT8 retVal = 0;
103		if(state->m_color & 0x80) {
	99	if(m_color & 0x80) {
104	100	// Color mode
105		if (!(state->m_color & 0x10)) {
	101	if (!(m_color & 0x10)) {
106	102	p0 ^= 0xff;
107	103	}
108		if (!(state->m_color & 0x20)) {
	104	if (!(m_color & 0x20)) {
109	105	p1 ^= 0xff;
110	106	}
111		if (!(state->m_color & 0x40)) {
	107	if (!(m_color & 0x40)) {
112	108	p2 ^= 0xff;
113	109	}
114	110	retVal = (p0 & p1 & p2) ^ 0xff;
115	111	} else {
116	112	// Plane mode
117		if (state->m_color & 0x10) {
	113	if (m_color & 0x10) {
118	114	retVal |= p0;
119	115	}
120		if (state->m_color & 0x20) {
	116	if (m_color & 0x20) {
121	117	retVal |= p1;
122	118	}
123		if (state->m_color & 0x40) {
	119	if (m_color & 0x40) {
124	120	retVal |= p2;
125	121	}
126	122	}
127	123	return retVal;
128	124	}
129	125
130		static WRITE8_HANDLER(gzu_w)
	126	WRITE8_MEMBER(pk8020_state::gzu_w)
131	127	{
132		pk8020_state *state = space->machine().driver_data<pk8020_state>();
133		UINT8 *addr = space->machine().device<ram_device>(RAM_TAG)->pointer() + 0x10000 + (state->m_video_page_access * 0xC000);
	128	UINT8 *addr = machine().device<ram_device>(RAM_TAG)->pointer() + 0x10000 + (m_video_page_access * 0xC000);
134	129	UINT8 *plane_0 = addr;
135	130	UINT8 *plane_1 = addr + 0x4000;
136	131	UINT8 *plane_2 = addr + 0x8000;
137	132
138		if(state->m_color & 0x80)
	133	if(m_color & 0x80)
139	134	{
140	135	// Color mode
141		plane_0[offset] = (plane_0[offset] & ~data) | ((state->m_color & 2) ? data : 0);
142		plane_1[offset] = (plane_1[offset] & ~data) | ((state->m_color & 4) ? data : 0);
143		plane_2[offset] = (plane_2[offset] & ~data) | ((state->m_color & 8) ? data : 0);
	136	plane_0[offset] = (plane_0[offset] & ~data) | ((m_color & 2) ? data : 0);
	137	plane_1[offset] = (plane_1[offset] & ~data) | ((m_color & 4) ? data : 0);
	138	plane_2[offset] = (plane_2[offset] & ~data) | ((m_color & 8) ? data : 0);
144	139	} else {
145	140	// Plane mode
146		UINT8 mask = (state->m_color & 1) ? data : 0;
147		if (!(state->m_color & 0x02)) {
	141	UINT8 mask = (m_color & 1) ? data : 0;
	142	if (!(m_color & 0x02)) {
148	143	plane_0[offset] = (plane_0[offset] & ~data) | mask;
149	144	}
150		if (!(state->m_color & 0x04)) {
	145	if (!(m_color & 0x04)) {
151	146	plane_1[offset] = (plane_1[offset] & ~data) | mask;
152	147	}
153		if (!(state->m_color & 0x08)) {
	148	if (!(m_color & 0x08)) {
154	149	plane_2[offset] = (plane_2[offset] & ~data) | mask;
155	150	}
156	151	}
157	152	}
158	153
159		static READ8_HANDLER(devices_r)
	154	READ8_MEMBER(pk8020_state::devices_r)
160	155	{
161		i8255_device *ppi1 = space->machine().device<i8255_device>("ppi8255_1");
162		i8255_device *ppi2 = space->machine().device<i8255_device>("ppi8255_2");
163		i8255_device *ppi3 = space->machine().device<i8255_device>("ppi8255_3");
164		device_t *pit = space->machine().device("pit8253");
165		device_t *pic = space->machine().device("pic8259");
166		i8251_device *rs232 = space->machine().device<i8251_device>("rs232");
167		i8251_device *lan = space->machine().device<i8251_device>("lan");
168		device_t *fdc = space->machine().device("wd1793");
	156	i8255_device *ppi1 = machine().device<i8255_device>("ppi8255_1");
	157	i8255_device *ppi2 = machine().device<i8255_device>("ppi8255_2");
	158	i8255_device *ppi3 = machine().device<i8255_device>("ppi8255_3");
	159	device_t *pit = machine().device("pit8253");
	160	device_t *pic = machine().device("pic8259");
	161	i8251_device *rs232 = machine().device<i8251_device>("rs232");
	162	i8251_device *lan = machine().device<i8251_device>("lan");
	163	device_t *fdc = machine().device("wd1793");
169	164
170	165	switch(offset & 0x38)
171	166	{
172	167	case 0x00: return pit8253_r(pit,offset & 3);
173		case 0x08: return ppi3->read(*space,offset & 3);
	168	case 0x08: return ppi3->read(space,offset & 3);
174	169	case 0x10: switch(offset & 1) {
175		case 0 : return rs232->data_r(*space,0);
176		case 1 : return rs232->status_r(*space,0);
	170	case 0 : return rs232->data_r(space,0);
	171	case 1 : return rs232->status_r(space,0);
177	172	}
178	173	break;
179	174	case 0x18: switch(offset & 3) {
r14963	r14964
184	179	}
185	180	break;
186	181	case 0x20: switch(offset & 1) {
187		case 0 : return lan->data_r(*space,0);
188		case 1 : return lan->status_r(*space,0);
	182	case 0 : return lan->data_r(space,0);
	183	case 1 : return lan->status_r(space,0);
189	184	}
190	185	break;
191	186	case 0x28: return pic8259_r(pic,offset & 1);
192		case 0x30: return ppi2->read(*space,offset & 3);
193		case 0x38: return ppi1->read(*space,offset & 3);
	187	case 0x30: return ppi2->read(space,offset & 3);
	188	case 0x38: return ppi1->read(space,offset & 3);
194	189	}
195	190	return 0xff;
196	191	}
197	192
198		static WRITE8_HANDLER(devices_w)
	193	WRITE8_MEMBER(pk8020_state::devices_w)
199	194	{
200		i8255_device *ppi1 = space->machine().device<i8255_device>("ppi8255_1");
201		i8255_device *ppi2 = space->machine().device<i8255_device>("ppi8255_2");
202		i8255_device *ppi3 = space->machine().device<i8255_device>("ppi8255_3");
203		device_t *pit = space->machine().device("pit8253");
204		device_t *pic = space->machine().device("pic8259");
205		i8251_device *rs232 = space->machine().device<i8251_device>("rs232");
206		i8251_device *lan = space->machine().device<i8251_device>("lan");
207		device_t *fdc = space->machine().device("wd1793");
	195	i8255_device *ppi1 = machine().device<i8255_device>("ppi8255_1");
	196	i8255_device *ppi2 = machine().device<i8255_device>("ppi8255_2");
	197	i8255_device *ppi3 = machine().device<i8255_device>("ppi8255_3");
	198	device_t *pit = machine().device("pit8253");
	199	device_t *pic = machine().device("pic8259");
	200	i8251_device *rs232 = machine().device<i8251_device>("rs232");
	201	i8251_device *lan = machine().device<i8251_device>("lan");
	202	device_t *fdc = machine().device("wd1793");
208	203
209	204	switch(offset & 0x38)
210	205	{
211	206	case 0x00: pit8253_w(pit,offset & 3,data); break;
212		case 0x08: ppi3->write(*space,offset & 3,data); break;
	207	case 0x08: ppi3->write(space,offset & 3,data); break;
213	208	case 0x10: switch(offset & 1) {
214		case 0 : rs232->data_w(*space,0,data); break;
215		case 1 : rs232->control_w(*space,0,data); break;
	209	case 0 : rs232->data_w(space,0,data); break;
	210	case 1 : rs232->control_w(space,0,data); break;
216	211	}
217	212	break;
218	213	case 0x18: switch(offset & 3) {
r14963	r14964
223	218	}
224	219	break;
225	220	case 0x20: switch(offset & 1) {
226		case 0 : lan->data_w(*space,0,data); break;
227		case 1 : lan->control_w(*space,0,data); break;
	221	case 0 : lan->data_w(space,0,data); break;
	222	case 1 : lan->control_w(space,0,data); break;
228	223	}
229	224	break;
230	225	case 0x28: pic8259_w(pic,offset & 1,data);break;
231		case 0x30: ppi2->write(*space,offset & 3,data); break;
232		case 0x38: ppi1->write(*space,offset & 3,data); break;
	226	case 0x30: ppi2->write(space,offset & 3,data); break;
	227	case 0x38: ppi1->write(space,offset & 3,data); break;
233	228	}
234	229	}
235	230
236	231	static void pk8020_set_bank(running_machine &machine,UINT8 data)
237	232	{
	233	pk8020_state *state = machine.driver_data<pk8020_state>();
238	234	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
239	235	UINT8 *mem = machine.region("maincpu")->base();
240	236	UINT8 *ram = machine.device<ram_device>(RAM_TAG)->pointer();
r14963	r14964
248	244	memory_set_bankptr(machine, "bank1", mem + 0x10000);
249	245	memory_set_bankptr(machine, "bank2", ram + 0x0000);
250	246	// Keyboard
251		space->install_legacy_read_handler (0x3800, 0x39ff, FUNC(keyboard_r));
	247	space->install_read_handler (0x3800, 0x39ff, read8_delegate(FUNC(pk8020_state::keyboard_r),state));
252	248	space->install_write_bank(0x3800, 0x39ff, "bank3");
253	249	memory_set_bankptr(machine, "bank3", ram + 0x3800);
254	250	// System reg
255		space->install_legacy_read_handler (0x3a00, 0x3aff, FUNC(sysreg_r));
256		space->install_legacy_write_handler(0x3a00, 0x3aff, FUNC(sysreg_w));
	251	space->install_read_handler (0x3a00, 0x3aff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	252	space->install_write_handler(0x3a00, 0x3aff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
257	253	// Devices
258		space->install_legacy_read_handler (0x3b00, 0x3bff, FUNC(devices_r));
259		space->install_legacy_write_handler(0x3b00, 0x3bff, FUNC(devices_w));
	254	space->install_read_handler (0x3b00, 0x3bff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	255	space->install_write_handler(0x3b00, 0x3bff, write8_delegate(FUNC(pk8020_state::devices_w),state));
260	256	// Text Video Memory
261		space->install_legacy_read_handler (0x3c00, 0x3fff, FUNC(text_r));
262		space->install_legacy_write_handler(0x3c00, 0x3fff, FUNC(text_w));
	257	space->install_read_handler (0x3c00, 0x3fff, read8_delegate(FUNC(pk8020_state::text_r),state));
	258	space->install_write_handler(0x3c00, 0x3fff, write8_delegate(FUNC(pk8020_state::text_w),state));
263	259	// RAM
264	260	space->install_read_bank (0x4000, 0xffff, "bank4");
265	261	space->install_write_bank(0x4000, 0xffff, "bank5");
r14963	r14964
315	311	memory_set_bankptr(machine, "bank3", ram + 0x2000);
316	312	memory_set_bankptr(machine, "bank4", ram + 0x2000);
317	313	// Keyboard
318		space->install_legacy_read_handler (0xf800, 0xf9ff, FUNC(keyboard_r));
	314	space->install_read_handler (0xf800, 0xf9ff, read8_delegate(FUNC(pk8020_state::keyboard_r),state));
319	315	space->install_write_bank(0xf800, 0xf9ff, "bank5");
320	316	memory_set_bankptr(machine, "bank5", ram + 0xf800);
321	317	// System reg
322		space->install_legacy_read_handler (0xfa00, 0xfaff, FUNC(sysreg_r));
323		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(sysreg_w));
	318	space->install_read_handler (0xfa00, 0xfaff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	319	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
324	320	// Devices
325		space->install_legacy_read_handler (0xfb00, 0xfbff, FUNC(devices_r));
326		space->install_legacy_write_handler(0xfb00, 0xfbff, FUNC(devices_w));
	321	space->install_read_handler (0xfb00, 0xfbff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	322	space->install_write_handler(0xfb00, 0xfbff, write8_delegate(FUNC(pk8020_state::devices_w),state));
327	323	// Text Video Memory
328		space->install_legacy_read_handler (0xfc00, 0xffff, FUNC(text_r));
329		space->install_legacy_write_handler(0xfc00, 0xffff, FUNC(text_w));
	324	space->install_read_handler (0xfc00, 0xffff, read8_delegate(FUNC(pk8020_state::text_r),state));
	325	space->install_write_handler(0xfc00, 0xffff, write8_delegate(FUNC(pk8020_state::text_w),state));
330	326	}
331	327	break;
332	328	case 0x06 :
r14963	r14964
342	338	memory_set_bankptr(machine, "bank3", ram + 0x4000);
343	339	memory_set_bankptr(machine, "bank4", ram + 0x4000);
344	340	// Keyboard
345		space->install_legacy_read_handler (0xf800, 0xf9ff, FUNC(keyboard_r));
	341	space->install_read_handler (0xf800, 0xf9ff, read8_delegate(FUNC(pk8020_state::keyboard_r),state));
346	342	space->install_write_bank(0xf800, 0xf9ff, "bank5");
347	343	memory_set_bankptr(machine, "bank5", ram + 0xf800);
348	344	// System reg
349		space->install_legacy_read_handler (0xfa00, 0xfaff, FUNC(sysreg_r));
350		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(sysreg_w));
	345	space->install_read_handler (0xfa00, 0xfaff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	346	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
351	347	// Devices
352		space->install_legacy_read_handler (0xfb00, 0xfbff, FUNC(devices_r));
353		space->install_legacy_write_handler(0xfb00, 0xfbff, FUNC(devices_w));
	348	space->install_read_handler (0xfb00, 0xfbff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	349	space->install_write_handler(0xfb00, 0xfbff, write8_delegate(FUNC(pk8020_state::devices_w),state));
354	350	// Text Video Memory
355		space->install_legacy_read_handler (0xfc00, 0xffff, FUNC(text_r));
356		space->install_legacy_write_handler(0xfc00, 0xffff, FUNC(text_w));
	351	space->install_read_handler (0xfc00, 0xffff, read8_delegate(FUNC(pk8020_state::text_r),state));
	352	space->install_write_handler(0xfc00, 0xffff, write8_delegate(FUNC(pk8020_state::text_w),state));
357	353	}
358	354	break;
359	355	case 0x07 :
r14963	r14964
364	360	memory_set_bankptr(machine, "bank1", ram);
365	361	memory_set_bankptr(machine, "bank2", ram);
366	362	// Keyboard
367		space->install_legacy_read_handler (0xf800, 0xf9ff, FUNC(keyboard_r));
	363	space->install_read_handler (0xf800, 0xf9ff, read8_delegate(FUNC(pk8020_state::keyboard_r),state));
368	364	space->install_write_bank(0xf800, 0xf9ff, "bank3");
369	365	memory_set_bankptr(machine, "bank3", ram + 0xf800);
370	366	// System reg
371		space->install_legacy_read_handler (0xfa00, 0xfaff, FUNC(sysreg_r));
372		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(sysreg_w));
	367	space->install_read_handler (0xfa00, 0xfaff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	368	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
373	369	// Devices
374		space->install_legacy_read_handler (0xfb00, 0xfbff, FUNC(devices_r));
375		space->install_legacy_write_handler(0xfb00, 0xfbff, FUNC(devices_w));
	370	space->install_read_handler (0xfb00, 0xfbff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	371	space->install_write_handler(0xfb00, 0xfbff, write8_delegate(FUNC(pk8020_state::devices_w),state));
376	372	// Text Video Memory
377		space->install_legacy_read_handler (0xfc00, 0xffff, FUNC(text_r));
378		space->install_legacy_write_handler(0xfc00, 0xffff, FUNC(text_w));
	373	space->install_read_handler (0xfc00, 0xffff, read8_delegate(FUNC(pk8020_state::text_r),state));
	374	space->install_write_handler(0xfc00, 0xffff, write8_delegate(FUNC(pk8020_state::text_w),state));
379	375	}
380	376	break;
381	377	case 0x08 :
r14963	r14964
386	382	memory_set_bankptr(machine, "bank1", mem + 0x10000);
387	383	memory_set_bankptr(machine, "bank2", ram + 0x0000);
388	384	// Keyboard
389		space->install_legacy_read_handler (0x3800, 0x39ff, FUNC(keyboard_r));
	385	space->install_read_handler (0x3800, 0x39ff, read8_delegate(FUNC(pk8020_state::keyboard_r),state));
390	386	space->install_write_bank(0x3800, 0x39ff, "bank3");
391	387	memory_set_bankptr(machine, "bank3", ram + 0x3800);
392	388	// System reg
393		space->install_legacy_read_handler (0x3a00, 0x3aff, FUNC(sysreg_r));
394		space->install_legacy_write_handler(0x3a00, 0x3aff, FUNC(sysreg_w));
	389	space->install_read_handler (0x3a00, 0x3aff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	390	space->install_write_handler(0x3a00, 0x3aff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
395	391	// Devices
396		space->install_legacy_read_handler (0x3b00, 0x3bff, FUNC(devices_r));
397		space->install_legacy_write_handler(0x3b00, 0x3bff, FUNC(devices_w));
	392	space->install_read_handler (0x3b00, 0x3bff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	393	space->install_write_handler(0x3b00, 0x3bff, write8_delegate(FUNC(pk8020_state::devices_w),state));
398	394	// Text Video Memory
399		space->install_legacy_read_handler (0x3c00, 0x3fff, FUNC(text_r));
400		space->install_legacy_write_handler(0x3c00, 0x3fff, FUNC(text_w));
	395	space->install_read_handler (0x3c00, 0x3fff, read8_delegate(FUNC(pk8020_state::text_r),state));
	396	space->install_write_handler(0x3c00, 0x3fff, write8_delegate(FUNC(pk8020_state::text_w),state));
401	397	// RAM
402	398	space->install_read_bank (0x4000, 0xbfff, "bank4");
403	399	space->install_write_bank(0x4000, 0xbfff, "bank5");
404	400	memory_set_bankptr(machine, "bank4", ram + 0x4000);
405	401	memory_set_bankptr(machine, "bank5", ram + 0x4000);
406	402	// Video RAM
407		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
408		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	403	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	404	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
409	405
410	406	}
411	407	break;
r14963	r14964
422	418	memory_set_bankptr(machine, "bank3", ram + 0x2000);
423	419	memory_set_bankptr(machine, "bank4", ram + 0x2000);
424	420	// Video RAM
425		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
426		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	421	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	422	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
427	423	}
428	424	break;
429	425	case 0x0A :
r14963	r14964
439	435	memory_set_bankptr(machine, "bank3", ram + 0x4000);
440	436	memory_set_bankptr(machine, "bank4", ram + 0x4000);
441	437	// Video RAM
442		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
443		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	438	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	439	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
444	440	}
445	441	break;
446	442	case 0x0B :
r14963	r14964
451	447	memory_set_bankptr(machine, "bank1", ram + 0x0000);
452	448	memory_set_bankptr(machine, "bank2", ram + 0x0000);
453	449	// Video RAM
454		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
455		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	450	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	451	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
456	452	}
457	453	break;
458	454	case 0x0C :
r14963	r14964
469	465	memory_set_bankptr(machine, "bank3", ram + 0x2000);
470	466	memory_set_bankptr(machine, "bank4", ram + 0x2000);
471	467	// Video RAM
472		space->install_legacy_read_handler (0x4000, 0x7fff, FUNC(gzu_r));
473		space->install_legacy_write_handler(0x4000, 0x7fff, FUNC(gzu_w));
	468	space->install_read_handler (0x4000, 0x7fff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	469	space->install_write_handler(0x4000, 0x7fff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
474	470	// RAM
475	471	space->install_read_bank (0x8000, 0xfdff, "bank5");
476	472	space->install_write_bank(0x8000, 0xfdff, "bank6");
477	473	memory_set_bankptr(machine, "bank5", ram + 0x8000);
478	474	memory_set_bankptr(machine, "bank6", ram + 0x8000);
479	475	// Devices
480		space->install_legacy_read_handler (0xfe00, 0xfeff, FUNC(devices_r));
481		space->install_legacy_write_handler(0xfe00, 0xfeff, FUNC(devices_w));
	476	space->install_read_handler (0xfe00, 0xfeff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	477	space->install_write_handler(0xfe00, 0xfeff, write8_delegate(FUNC(pk8020_state::devices_w),state));
482	478	// System reg
483		space->install_legacy_read_handler (0xff00, 0xffff, FUNC(sysreg_r));
484		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(sysreg_w));
	479	space->install_read_handler (0xff00, 0xffff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	480	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
485	481	}
486	482	break;
487	483	case 0x0E :
r14963	r14964
492	488	memory_set_bankptr(machine, "bank1", mem + 0x10000);
493	489	memory_set_bankptr(machine, "bank2", ram + 0x0000);
494	490	// Video RAM
495		space->install_legacy_read_handler (0x4000, 0x7fff, FUNC(gzu_r));
496		space->install_legacy_write_handler(0x4000, 0x7fff, FUNC(gzu_w));
	491	space->install_read_handler (0x4000, 0x7fff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	492	space->install_write_handler(0x4000, 0x7fff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
497	493	// RAM
498	494	space->install_read_bank (0x8000, 0xfdff, "bank5");
499	495	space->install_write_bank(0x8000, 0xfdff, "bank6");
500	496	memory_set_bankptr(machine, "bank5", ram + 0x8000);
501	497	memory_set_bankptr(machine, "bank6", ram + 0x8000);
502	498	// Devices
503		space->install_legacy_read_handler (0xfe00, 0xfeff, FUNC(devices_r));
504		space->install_legacy_write_handler(0xfe00, 0xfeff, FUNC(devices_w));
	499	space->install_read_handler (0xfe00, 0xfeff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	500	space->install_write_handler(0xfe00, 0xfeff, write8_delegate(FUNC(pk8020_state::devices_w),state));
505	501	// System reg
506		space->install_legacy_read_handler (0xff00, 0xffff, FUNC(sysreg_r));
507		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(sysreg_w));
	502	space->install_read_handler (0xff00, 0xffff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	503	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
508	504	}
509	505	break;
510	506	case 0x0F :
r14963	r14964
515	511	memory_set_bankptr(machine, "bank1", ram + 0x0000);
516	512	memory_set_bankptr(machine, "bank2", ram + 0x0000);
517	513	// Video RAM
518		space->install_legacy_read_handler (0x4000, 0x7fff, FUNC(gzu_r));
519		space->install_legacy_write_handler(0x4000, 0x7fff, FUNC(gzu_w));
	514	space->install_read_handler (0x4000, 0x7fff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	515	space->install_write_handler(0x4000, 0x7fff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
520	516	// RAM
521	517	space->install_read_bank (0x8000, 0xfdff, "bank3");
522	518	space->install_write_bank(0x8000, 0xfdff, "bank4");
523	519	memory_set_bankptr(machine, "bank3", ram + 0x8000);
524	520	memory_set_bankptr(machine, "bank4", ram + 0x8000);
525	521	// Devices
526		space->install_legacy_read_handler (0xfe00, 0xfeff, FUNC(devices_r));
527		space->install_legacy_write_handler(0xfe00, 0xfeff, FUNC(devices_w));
	522	space->install_read_handler (0xfe00, 0xfeff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	523	space->install_write_handler(0xfe00, 0xfeff, write8_delegate(FUNC(pk8020_state::devices_w),state));
528	524	// System reg
529		space->install_legacy_read_handler (0xff00, 0xffff, FUNC(sysreg_r));
530		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(sysreg_w));
	525	space->install_read_handler (0xff00, 0xffff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	526	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
531	527	}
532	528	break;
533	529	case 0x10 :
r14963	r14964
543	539	memory_set_bankptr(machine, "bank3", ram + 0x6000);
544	540	memory_set_bankptr(machine, "bank4", ram + 0x6000);
545	541	// Keyboard
546		space->install_legacy_read_handler (0xf800, 0xf9ff, FUNC(keyboard_r));
	542	space->install_read_handler (0xf800, 0xf9ff, read8_delegate(FUNC(pk8020_state::keyboard_r),state));
547	543	space->install_write_bank(0xf800, 0xf9ff, "bank5");
548	544	memory_set_bankptr(machine, "bank5", ram + 0xf800);
549	545	// System reg
550		space->install_legacy_read_handler (0xfa00, 0xfaff, FUNC(sysreg_r));
551		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(sysreg_w));
	546	space->install_read_handler (0xfa00, 0xfaff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	547	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
552	548	// Devices
553		space->install_legacy_read_handler (0xfb00, 0xfbff, FUNC(devices_r));
554		space->install_legacy_write_handler(0xfb00, 0xfbff, FUNC(devices_w));
	549	space->install_read_handler (0xfb00, 0xfbff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	550	space->install_write_handler(0xfb00, 0xfbff, write8_delegate(FUNC(pk8020_state::devices_w),state));
555	551	// Text Video Memory
556		space->install_legacy_read_handler (0xfc00, 0xffff, FUNC(text_r));
557		space->install_legacy_write_handler(0xfc00, 0xffff, FUNC(text_w));
	552	space->install_read_handler (0xfc00, 0xffff, read8_delegate(FUNC(pk8020_state::text_r),state));
	553	space->install_write_handler(0xfc00, 0xffff, write8_delegate(FUNC(pk8020_state::text_w),state));
558	554	}
559	555	break;
560	556	case 0x11 :
r14963	r14964
570	566	memory_set_bankptr(machine, "bank3", ram + 0x2000);
571	567	memory_set_bankptr(machine, "bank4", ram + 0x2000);
572	568	// Keyboard
573		space->install_legacy_read_handler (0xf800, 0xf9ff, FUNC(keyboard_r));
	569	space->install_read_handler (0xf800, 0xf9ff, read8_delegate(FUNC(pk8020_state::keyboard_r),state));
574	570	space->install_write_bank(0xf800, 0xf9ff, "bank5");
575	571	memory_set_bankptr(machine, "bank5", ram + 0xf800);
576	572	// System reg
577		space->install_legacy_read_handler (0xfa00, 0xfaff, FUNC(sysreg_r));
578		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(sysreg_w));
	573	space->install_read_handler (0xfa00, 0xfaff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	574	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
579	575	// Devices
580		space->install_legacy_read_handler (0xfb00, 0xfbff, FUNC(devices_r));
581		space->install_legacy_write_handler(0xfb00, 0xfbff, FUNC(devices_w));
	576	space->install_read_handler (0xfb00, 0xfbff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	577	space->install_write_handler(0xfb00, 0xfbff, write8_delegate(FUNC(pk8020_state::devices_w),state));
582	578	// Text Video Memory
583		space->install_legacy_read_handler (0xfc00, 0xffff, FUNC(text_r));
584		space->install_legacy_write_handler(0xfc00, 0xffff, FUNC(text_w));
	579	space->install_read_handler (0xfc00, 0xffff, read8_delegate(FUNC(pk8020_state::text_r),state));
	580	space->install_write_handler(0xfc00, 0xffff, write8_delegate(FUNC(pk8020_state::text_w),state));
585	581	}
586	582	break;
587	583	case 0x12 :
r14963	r14964
597	593	memory_set_bankptr(machine, "bank3", ram + 0x4000);
598	594	memory_set_bankptr(machine, "bank4", ram + 0x4000);
599	595	// Keyboard
600		space->install_legacy_read_handler (0xf800, 0xf9ff, FUNC(keyboard_r));
	596	space->install_read_handler (0xf800, 0xf9ff, read8_delegate(FUNC(pk8020_state::keyboard_r),state));
601	597	space->install_write_bank(0xf800, 0xf9ff, "bank5");
602	598	memory_set_bankptr(machine, "bank5", ram + 0xf800);
603	599	// System reg
604		space->install_legacy_read_handler (0xfa00, 0xfaff, FUNC(sysreg_r));
605		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(sysreg_w));
	600	space->install_read_handler (0xfa00, 0xfaff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	601	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
606	602	// Devices
607		space->install_legacy_read_handler (0xfb00, 0xfbff, FUNC(devices_r));
608		space->install_legacy_write_handler(0xfb00, 0xfbff, FUNC(devices_w));
	603	space->install_read_handler (0xfb00, 0xfbff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	604	space->install_write_handler(0xfb00, 0xfbff, write8_delegate(FUNC(pk8020_state::devices_w),state));
609	605	// Text Video Memory
610		space->install_legacy_read_handler (0xfc00, 0xffff, FUNC(text_r));
611		space->install_legacy_write_handler(0xfc00, 0xffff, FUNC(text_w));
	606	space->install_read_handler (0xfc00, 0xffff, read8_delegate(FUNC(pk8020_state::text_r),state));
	607	space->install_write_handler(0xfc00, 0xffff, write8_delegate(FUNC(pk8020_state::text_w),state));
612	608	}
613	609	break;
614	610	case 0x13 :
r14963	r14964
619	615	memory_set_bankptr(machine, "bank1", ram + 0x0000);
620	616	memory_set_bankptr(machine, "bank2", ram + 0x0000);
621	617	// Keyboard
622		space->install_legacy_read_handler (0xf800, 0xf9ff, FUNC(keyboard_r));
	618	space->install_read_handler (0xf800, 0xf9ff, read8_delegate(FUNC(pk8020_state::keyboard_r),state));
623	619	space->install_write_bank(0xf800, 0xf9ff, "bank3");
624	620	memory_set_bankptr(machine, "bank3", ram + 0xf800);
625	621	// System reg
626		space->install_legacy_read_handler (0xfa00, 0xfaff, FUNC(sysreg_r));
627		space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(sysreg_w));
	622	space->install_read_handler (0xfa00, 0xfaff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	623	space->install_write_handler(0xfa00, 0xfaff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
628	624	// Devices
629		space->install_legacy_read_handler (0xfb00, 0xfbff, FUNC(devices_r));
630		space->install_legacy_write_handler(0xfb00, 0xfbff, FUNC(devices_w));
	625	space->install_read_handler (0xfb00, 0xfbff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	626	space->install_write_handler(0xfb00, 0xfbff, write8_delegate(FUNC(pk8020_state::devices_w),state));
631	627	// Text Video Memory
632		space->install_legacy_read_handler (0xfc00, 0xffff, FUNC(text_r));
633		space->install_legacy_write_handler(0xfc00, 0xffff, FUNC(text_w));
	628	space->install_read_handler (0xfc00, 0xffff, read8_delegate(FUNC(pk8020_state::text_r),state));
	629	space->install_write_handler(0xfc00, 0xffff, write8_delegate(FUNC(pk8020_state::text_w),state));
634	630	}
635	631	break;
636	632	case 0x14 :
r14963	r14964
646	642	memory_set_bankptr(machine, "bank3", ram + 0x6000);
647	643	memory_set_bankptr(machine, "bank4", ram + 0x6000);
648	644	// Devices
649		space->install_legacy_read_handler (0xfe00, 0xfeff, FUNC(devices_r));
650		space->install_legacy_write_handler(0xfe00, 0xfeff, FUNC(devices_w));
	645	space->install_read_handler (0xfe00, 0xfeff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	646	space->install_write_handler(0xfe00, 0xfeff, write8_delegate(FUNC(pk8020_state::devices_w),state));
651	647	// System reg
652		space->install_legacy_read_handler (0xff00, 0xffff, FUNC(sysreg_r));
653		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(sysreg_w));
	648	space->install_read_handler (0xff00, 0xffff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	649	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
654	650	}
655	651	break;
656	652	case 0x15 :
r14963	r14964
666	662	memory_set_bankptr(machine, "bank3", ram + 0x2000);
667	663	memory_set_bankptr(machine, "bank4", ram + 0x2000);
668	664	// Devices
669		space->install_legacy_read_handler (0xfe00, 0xfeff, FUNC(devices_r));
670		space->install_legacy_write_handler(0xfe00, 0xfeff, FUNC(devices_w));
	665	space->install_read_handler (0xfe00, 0xfeff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	666	space->install_write_handler(0xfe00, 0xfeff, write8_delegate(FUNC(pk8020_state::devices_w),state));
671	667	// System reg
672		space->install_legacy_read_handler (0xff00, 0xffff, FUNC(sysreg_r));
673		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(sysreg_w));
	668	space->install_read_handler (0xff00, 0xffff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	669	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
674	670	}
675	671	break;
676	672	case 0x16 :
r14963	r14964
686	682	memory_set_bankptr(machine, "bank3", ram + 0x4000);
687	683	memory_set_bankptr(machine, "bank4", ram + 0x4000);
688	684	// Devices
689		space->install_legacy_read_handler (0xfe00, 0xfeff, FUNC(devices_r));
690		space->install_legacy_write_handler(0xfe00, 0xfeff, FUNC(devices_w));
	685	space->install_read_handler (0xfe00, 0xfeff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	686	space->install_write_handler(0xfe00, 0xfeff, write8_delegate(FUNC(pk8020_state::devices_w),state));
691	687	// System reg
692		space->install_legacy_read_handler (0xff00, 0xffff, FUNC(sysreg_r));
693		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(sysreg_w));
	688	space->install_read_handler (0xff00, 0xffff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	689	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
694	690	}
695	691	break;
696	692	case 0x17 :
r14963	r14964
701	697	memory_set_bankptr(machine, "bank1", ram);
702	698	memory_set_bankptr(machine, "bank2", ram);
703	699	// Devices
704		space->install_legacy_read_handler (0xfe00, 0xfeff, FUNC(devices_r));
705		space->install_legacy_write_handler(0xfe00, 0xfeff, FUNC(devices_w));
	700	space->install_read_handler (0xfe00, 0xfeff, read8_delegate(FUNC(pk8020_state::devices_r),state));
	701	space->install_write_handler(0xfe00, 0xfeff, write8_delegate(FUNC(pk8020_state::devices_w),state));
706	702	// System reg
707		space->install_legacy_read_handler (0xff00, 0xffff, FUNC(sysreg_r));
708		space->install_legacy_write_handler(0xff00, 0xffff, FUNC(sysreg_w));
	703	space->install_read_handler (0xff00, 0xffff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	704	space->install_write_handler(0xff00, 0xffff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
709	705	}
710	706	break;
711	707	case 0x18 :
r14963	r14964
721	717	memory_set_bankptr(machine, "bank3", ram + 0x6000);
722	718	memory_set_bankptr(machine, "bank4", ram + 0x6000);
723	719	// System reg
724		space->install_legacy_read_handler (0xbf00, 0xbfff, FUNC(sysreg_r));
725		space->install_legacy_write_handler(0xbf00, 0xbfff, FUNC(sysreg_w));
	720	space->install_read_handler (0xbf00, 0xbfff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	721	space->install_write_handler(0xbf00, 0xbfff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
726	722	// Video RAM
727		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
728		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	723	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	724	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
729	725	}
730	726	break;
731	727	case 0x19 :
r14963	r14964
741	737	memory_set_bankptr(machine, "bank3", ram + 0x2000);
742	738	memory_set_bankptr(machine, "bank4", ram + 0x2000);
743	739	// System reg
744		space->install_legacy_read_handler (0xbf00, 0xbfff, FUNC(sysreg_r));
745		space->install_legacy_write_handler(0xbf00, 0xbfff, FUNC(sysreg_w));
	740	space->install_read_handler (0xbf00, 0xbfff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	741	space->install_write_handler(0xbf00, 0xbfff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
746	742	// Video RAM
747		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
748		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	743	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	744	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
749	745	}
750	746	break;
751	747	case 0x1A :
r14963	r14964
761	757	memory_set_bankptr(machine, "bank3", ram + 0x4000);
762	758	memory_set_bankptr(machine, "bank4", ram + 0x4000);
763	759	// System reg
764		space->install_legacy_read_handler (0xbf00, 0xbfff, FUNC(sysreg_r));
765		space->install_legacy_write_handler(0xbf00, 0xbfff, FUNC(sysreg_w));
	760	space->install_read_handler (0xbf00, 0xbfff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	761	space->install_write_handler(0xbf00, 0xbfff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
766	762	// Video RAM
767		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
768		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	763	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	764	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
769	765	}
770	766	break;
771	767	case 0x1B :
r14963	r14964
776	772	memory_set_bankptr(machine, "bank1", ram);
777	773	memory_set_bankptr(machine, "bank2", ram);
778	774	// System reg
779		space->install_legacy_read_handler (0xbf00, 0xbfff, FUNC(sysreg_r));
780		space->install_legacy_write_handler(0xbf00, 0xbfff, FUNC(sysreg_w));
	775	space->install_read_handler (0xbf00, 0xbfff, read8_delegate(FUNC(pk8020_state::sysreg_r),state));
	776	space->install_write_handler(0xbf00, 0xbfff, write8_delegate(FUNC(pk8020_state::sysreg_w),state));
781	777	// Video RAM
782		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
783		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	778	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	779	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
784	780	}
785	781	break;
786	782	case 0x1C :
r14963	r14964
796	792	memory_set_bankptr(machine, "bank3", ram + 0x6000);
797	793	memory_set_bankptr(machine, "bank4", ram + 0x6000);
798	794	// Video RAM
799		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
800		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	795	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	796	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
801	797	}
802	798	break;
803	799	case 0x1D :
r14963	r14964
813	809	memory_set_bankptr(machine, "bank3", ram + 0x2000);
814	810	memory_set_bankptr(machine, "bank4", ram + 0x2000);
815	811	// Video RAM
816		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
817		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	812	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	813	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
818	814	}
819	815	break;
820	816	case 0x1E :
r14963	r14964
830	826	memory_set_bankptr(machine, "bank3", ram + 0x4000);
831	827	memory_set_bankptr(machine, "bank4", ram + 0x4000);
832	828	// Video RAM
833		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
834		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	829	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	830	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
835	831	}
836	832	break;
837	833	case 0x1F :
r14963	r14964
842	838	memory_set_bankptr(machine, "bank1", ram);
843	839	memory_set_bankptr(machine, "bank2", ram);
844	840	// Video RAM
845		space->install_legacy_read_handler (0xc000, 0xffff, FUNC(gzu_r));
846		space->install_legacy_write_handler(0xc000, 0xffff, FUNC(gzu_w));
	841	space->install_read_handler (0xc000, 0xffff, read8_delegate(FUNC(pk8020_state::gzu_r),state));
	842	space->install_write_handler(0xc000, 0xffff, write8_delegate(FUNC(pk8020_state::gzu_w),state));
847	843	}
848	844	break;
849	845

src/mess/includes/gba.h

r14963	r14964
223	223	int m_flash_battery_load;
224	224
225	225	DIRECT_UPDATE_MEMBER(gba_direct);
	226	DECLARE_READ32_MEMBER(gba_io_r);
	227	DECLARE_WRITE32_MEMBER(gba_io_w);
	228	DECLARE_WRITE32_MEMBER(gba_pram_w);
	229	DECLARE_WRITE32_MEMBER(gba_vram_w);
	230	DECLARE_WRITE32_MEMBER(gba_oam_w);
	231	DECLARE_READ32_MEMBER(gba_bios_r);
	232	DECLARE_READ32_MEMBER(gba_10000000_r);
	233	DECLARE_READ32_MEMBER(sram_r);
	234	DECLARE_WRITE32_MEMBER(sram_w);
	235	DECLARE_READ32_MEMBER(flash_r);
	236	DECLARE_WRITE32_MEMBER(flash_w);
	237	DECLARE_READ32_MEMBER(eeprom_r);
	238	DECLARE_WRITE32_MEMBER(eeprom_w);
226	239	};
227	240
228	241	/*----------- defined in video/gba.c -----------*/

src/mess/includes/fm7.h

r14963	r14964
142	142	fm7_video_t m_video;
143	143	fm7_alu_t m_alu;
144	144	int m_sb_prev;
	145	DECLARE_READ8_MEMBER(fm7_subintf_r);
	146	DECLARE_WRITE8_MEMBER(fm7_subintf_w);
	147	DECLARE_READ8_MEMBER(fm7_sub_busyflag_r);
	148	DECLARE_WRITE8_MEMBER(fm7_sub_busyflag_w);
	149	DECLARE_READ8_MEMBER(fm7_cancel_ack);
	150	DECLARE_READ8_MEMBER(fm7_attn_irq_r);
	151	DECLARE_READ8_MEMBER(fm7_vram_access_r);
	152	DECLARE_WRITE8_MEMBER(fm7_vram_access_w);
	153	DECLARE_READ8_MEMBER(fm7_vram_r);
	154	DECLARE_WRITE8_MEMBER(fm7_vram_w);
	155	DECLARE_WRITE8_MEMBER(fm7_vram_banked_w);
	156	DECLARE_READ8_MEMBER(fm7_vram0_r);
	157	DECLARE_READ8_MEMBER(fm7_vram1_r);
	158	DECLARE_READ8_MEMBER(fm7_vram2_r);
	159	DECLARE_READ8_MEMBER(fm7_vram3_r);
	160	DECLARE_READ8_MEMBER(fm7_vram4_r);
	161	DECLARE_READ8_MEMBER(fm7_vram5_r);
	162	DECLARE_READ8_MEMBER(fm7_vram6_r);
	163	DECLARE_READ8_MEMBER(fm7_vram7_r);
	164	DECLARE_READ8_MEMBER(fm7_vram8_r);
	165	DECLARE_READ8_MEMBER(fm7_vram9_r);
	166	DECLARE_READ8_MEMBER(fm7_vramA_r);
	167	DECLARE_READ8_MEMBER(fm7_vramB_r);
	168	DECLARE_WRITE8_MEMBER(fm7_vram0_w);
	169	DECLARE_WRITE8_MEMBER(fm7_vram1_w);
	170	DECLARE_WRITE8_MEMBER(fm7_vram2_w);
	171	DECLARE_WRITE8_MEMBER(fm7_vram3_w);
	172	DECLARE_WRITE8_MEMBER(fm7_vram4_w);
	173	DECLARE_WRITE8_MEMBER(fm7_vram5_w);
	174	DECLARE_WRITE8_MEMBER(fm7_vram6_w);
	175	DECLARE_WRITE8_MEMBER(fm7_vram7_w);
	176	DECLARE_WRITE8_MEMBER(fm7_vram8_w);
	177	DECLARE_WRITE8_MEMBER(fm7_vram9_w);
	178	DECLARE_WRITE8_MEMBER(fm7_vramA_w);
	179	DECLARE_WRITE8_MEMBER(fm7_vramB_w);
	180	DECLARE_READ8_MEMBER(fm7_crt_r);
	181	DECLARE_WRITE8_MEMBER(fm7_crt_w);
	182	DECLARE_WRITE8_MEMBER(fm7_vram_offset_w);
	183	DECLARE_WRITE8_MEMBER(fm7_multipage_w);
	184	DECLARE_READ8_MEMBER(fm7_palette_r);
	185	DECLARE_WRITE8_MEMBER(fm7_palette_w);
	186	DECLARE_WRITE8_MEMBER(fm77av_analog_palette_w);
	187	DECLARE_READ8_MEMBER(fm77av_video_flags_r);
	188	DECLARE_WRITE8_MEMBER(fm77av_video_flags_w);
	189	DECLARE_READ8_MEMBER(fm77av_sub_modestatus_r);
	190	DECLARE_WRITE8_MEMBER(fm77av_sub_modestatus_w);
	191	DECLARE_WRITE8_MEMBER(fm77av_sub_bank_w);
	192	DECLARE_READ8_MEMBER(fm77av_alu_r);
	193	DECLARE_WRITE8_MEMBER(fm77av_alu_w);
	194	DECLARE_READ8_MEMBER(fm7_sub_ram_ports_banked_r);
	195	DECLARE_WRITE8_MEMBER(fm7_sub_ram_ports_banked_w);
	196	DECLARE_READ8_MEMBER(fm7_console_ram_banked_r);
	197	DECLARE_WRITE8_MEMBER(fm7_console_ram_banked_w);
	198	DECLARE_WRITE8_MEMBER(fm7_irq_mask_w);
	199	DECLARE_READ8_MEMBER(fm7_irq_cause_r);
	200	DECLARE_WRITE8_MEMBER(fm7_beeper_w);
	201	DECLARE_READ8_MEMBER(fm7_sub_beeper_r);
	202	DECLARE_READ8_MEMBER(vector_r);
	203	DECLARE_WRITE8_MEMBER(vector_w);
	204	DECLARE_READ8_MEMBER(fm7_fd04_r);
	205	DECLARE_READ8_MEMBER(fm7_rom_en_r);
	206	DECLARE_WRITE8_MEMBER(fm7_rom_en_w);
	207	DECLARE_WRITE8_MEMBER(fm7_init_en_w);
	208	DECLARE_READ8_MEMBER(fm7_fdc_r);
	209	DECLARE_WRITE8_MEMBER(fm7_fdc_w);
	210	DECLARE_READ8_MEMBER(fm7_keyboard_r);
	211	DECLARE_READ8_MEMBER(fm7_sub_keyboard_r);
	212	DECLARE_READ8_MEMBER(fm77av_key_encoder_r);
	213	DECLARE_WRITE8_MEMBER(fm77av_key_encoder_w);
	214	DECLARE_READ8_MEMBER(fm7_cassette_printer_r);
	215	DECLARE_WRITE8_MEMBER(fm7_cassette_printer_w);
	216	DECLARE_READ8_MEMBER(fm77av_boot_mode_r);
	217	DECLARE_READ8_MEMBER(fm7_psg_select_r);
	218	DECLARE_WRITE8_MEMBER(fm7_psg_select_w);
	219	DECLARE_WRITE8_MEMBER(fm77av_ym_select_w);
	220	DECLARE_READ8_MEMBER(fm7_psg_data_r);
	221	DECLARE_WRITE8_MEMBER(fm7_psg_data_w);
	222	DECLARE_WRITE8_MEMBER(fm77av_bootram_w);
	223	DECLARE_READ8_MEMBER(fm7_main_shared_r);
	224	DECLARE_WRITE8_MEMBER(fm7_main_shared_w);
	225	DECLARE_READ8_MEMBER(fm7_fmirq_r);
	226	DECLARE_READ8_MEMBER(fm7_unknown_r);
	227	DECLARE_READ8_MEMBER(fm7_mmr_r);
	228	DECLARE_WRITE8_MEMBER(fm7_mmr_w);
	229	DECLARE_READ8_MEMBER(fm7_kanji_r);
	230	DECLARE_WRITE8_MEMBER(fm7_kanji_w);
	231	void fm77av_encoder_setup_command();
	232	void fm77av_encoder_handle_command();
145	233	};
146	234
147	235
148	236	/*----------- defined in drivers/fm7.c -----------*/
149	237
150		READ8_HANDLER( fm7_sub_keyboard_r );
151		READ8_HANDLER( fm77av_key_encoder_r );
152		WRITE8_HANDLER( fm77av_key_encoder_w );
153		READ8_HANDLER( fm7_sub_beeper_r );
154	238
155	239
156	240	/*----------- defined in video/fm7.c -----------*/
157	241
158	242	TIMER_CALLBACK( fm77av_vsync );
159	243
160		READ8_HANDLER( fm7_subintf_r );
161		WRITE8_HANDLER( fm7_subintf_w );
162		READ8_HANDLER( fm7_sub_busyflag_r );
163		WRITE8_HANDLER( fm7_sub_busyflag_w );
164		READ8_HANDLER( fm77av_sub_modestatus_r );
165		WRITE8_HANDLER( fm77av_sub_modestatus_w );
166		WRITE8_HANDLER( fm77av_sub_bank_w );
167	244
168		READ8_HANDLER( fm7_cancel_ack );
169		READ8_HANDLER( fm7_attn_irq_r );
170	245
171		READ8_HANDLER( fm7_vram_access_r );
172		WRITE8_HANDLER( fm7_vram_access_w );
173		READ8_HANDLER( fm7_vram_r );
174		WRITE8_HANDLER( fm7_vram_w );
175		READ8_HANDLER( fm7_crt_r );
176		WRITE8_HANDLER( fm7_crt_w );
177		WRITE8_HANDLER( fm7_vram_offset_w );
178		READ8_HANDLER( fm77av_video_flags_r );
179		WRITE8_HANDLER( fm77av_video_flags_w );
180		READ8_HANDLER( fm77av_alu_r );
181		WRITE8_HANDLER( fm77av_alu_w );
182	246
183		WRITE8_HANDLER( fm77av_analog_palette_w );
184		WRITE8_HANDLER( fm7_multipage_w );
185		READ8_HANDLER( fm7_palette_r );
186		WRITE8_HANDLER( fm7_palette_w );
187	247
188		READ8_HANDLER( fm7_vram0_r );
189		READ8_HANDLER( fm7_vram1_r );
190		READ8_HANDLER( fm7_vram2_r );
191		READ8_HANDLER( fm7_vram3_r );
192		READ8_HANDLER( fm7_vram4_r );
193		READ8_HANDLER( fm7_vram5_r );
194		READ8_HANDLER( fm7_vram6_r );
195		READ8_HANDLER( fm7_vram7_r );
196		READ8_HANDLER( fm7_vram8_r );
197		READ8_HANDLER( fm7_vram9_r );
198		READ8_HANDLER( fm7_vramA_r );
199		READ8_HANDLER( fm7_vramB_r );
200		WRITE8_HANDLER( fm7_vram0_w );
201		WRITE8_HANDLER( fm7_vram1_w );
202		WRITE8_HANDLER( fm7_vram2_w );
203		WRITE8_HANDLER( fm7_vram3_w );
204		WRITE8_HANDLER( fm7_vram4_w );
205		WRITE8_HANDLER( fm7_vram5_w );
206		WRITE8_HANDLER( fm7_vram6_w );
207		WRITE8_HANDLER( fm7_vram7_w );
208		WRITE8_HANDLER( fm7_vram8_w );
209		WRITE8_HANDLER( fm7_vram9_w );
210		WRITE8_HANDLER( fm7_vramA_w );
211		WRITE8_HANDLER( fm7_vramB_w );
212	248
213		READ8_HANDLER( fm7_sub_ram_ports_banked_r );
214		WRITE8_HANDLER( fm7_sub_ram_ports_banked_w );
215		READ8_HANDLER( fm7_console_ram_banked_r );
216		WRITE8_HANDLER( fm7_console_ram_banked_w );
217	249
218	250	VIDEO_START( fm7 );
219	251	SCREEN_UPDATE_IND16( fm7 );

src/mess/includes/vtech2.h

r14963	r14964
43	43	int m_row_d;
44	44	int m_laser_bg_mode;
45	45	int m_laser_two_color;
	46	DECLARE_WRITE8_MEMBER(laser_bank_select_w);
	47	DECLARE_WRITE8_MEMBER(laser_fdc_w);
	48	DECLARE_WRITE8_MEMBER(laser_bg_mode_w);
	49	DECLARE_WRITE8_MEMBER(laser_two_color_w);
	50	DECLARE_READ8_MEMBER(laser_fdc_r);
46	51	};
47	52
48	53
r14963	r14964
56	61	DEVICE_IMAGE_LOAD( laser_cart );
57	62	DEVICE_IMAGE_UNLOAD( laser_cart );
58	63
59		extern  READ8_HANDLER ( laser_fdc_r );
60		extern WRITE8_HANDLER ( laser_fdc_w );
61		extern WRITE8_HANDLER ( laser_bank_select_w );
62	64
63	65
64	66	/*----------- defined in video/vtech2.c -----------*/
65	67
66	68	extern VIDEO_START( laser );
67	69	extern SCREEN_UPDATE_IND16( laser );
68		extern WRITE8_HANDLER ( laser_bg_mode_w );
69		extern WRITE8_HANDLER ( laser_two_color_w );
70	70
71	71
72	72	#endif /* VTECH2_H_ */

src/mess/includes/comquest.h

r14963	r14964
20	20	int m_dma_activ;
21	21	int m_state;
22	22	int m_count;
	23	DECLARE_READ8_MEMBER(comquest_read);
	24	DECLARE_WRITE8_MEMBER(comquest_write);
23	25	};
24	26
25	27

src/mess/includes/zx.h

r14963	r14964
46	46	UINT8 m_charline_ptr;
47	47	int m_offs1;
48	48	void zx_ula_bkgnd(UINT8 color);
	49	DECLARE_WRITE8_MEMBER(zx_ram_w);
49	50	};
50	51
51	52

src/mess/includes/z80ne.h

r14963	r14964
80	80	emu_timer *m_cassette_timer;
81	81	cass_data_t m_cass_data;
82	82	wd17xx_state_t m_wd17xx_state;
	83	DECLARE_READ8_MEMBER(lx383_r);
	84	DECLARE_WRITE8_MEMBER(lx383_w);
	85	DECLARE_READ8_MEMBER(lx385_data_r);
	86	DECLARE_READ8_MEMBER(lx385_ctrl_r);
	87	DECLARE_WRITE8_MEMBER(lx385_data_w);
	88	DECLARE_WRITE8_MEMBER(lx385_ctrl_w);
	89	DECLARE_READ8_MEMBER(lx388_data_r);
	90	DECLARE_READ8_MEMBER(lx388_read_field_sync);
83	91	};
84	92
85	93
86	94	/*----------- defined in machine/z80ne.c -----------*/
87	95
88		READ8_HANDLER(lx383_r);
89		WRITE8_HANDLER(lx383_w);
90		READ8_HANDLER(lx385_data_r);
91		WRITE8_HANDLER(lx385_data_w);
92		READ8_HANDLER(lx385_ctrl_r);
93		WRITE8_HANDLER(lx385_ctrl_w);
94	96	READ8_DEVICE_HANDLER(lx388_mc6847_videoram_r);
95		READ8_HANDLER(lx388_data_r);
96		READ8_HANDLER(lx388_read_field_sync);
97	97	READ8_DEVICE_HANDLER(lx390_fdc_r);
98	98	WRITE8_DEVICE_HANDLER(lx390_fdc_w);
99	99	READ8_DEVICE_HANDLER(lx390_reset_bank);

src/mess/includes/apple3.h

r14963	r14964
47	47	UINT8 m_last_n;
48	48	UINT8 *m_char_mem;
49	49	UINT32 *m_hgr_map;
	50	DECLARE_READ8_MEMBER(apple3_c0xx_r);
	51	DECLARE_WRITE8_MEMBER(apple3_c0xx_w);
	52	DECLARE_READ8_MEMBER(apple3_00xx_r);
	53	DECLARE_WRITE8_MEMBER(apple3_00xx_w);
	54	DECLARE_READ8_MEMBER(apple3_indexed_read);
	55	DECLARE_WRITE8_MEMBER(apple3_indexed_write);
	56	UINT8 apple3_profile_r(offs_t offset);
	57	void apple3_profile_w(offs_t offset, UINT8 data);
50	58	};
51	59
52	60
r14963	r14964
60	68	DRIVER_INIT( apple3 );
61	69	INTERRUPT_GEN( apple3_interrupt );
62	70
63		READ8_HANDLER( apple3_00xx_r );
64		WRITE8_HANDLER( apple3_00xx_w );
65	71
66		READ8_HANDLER( apple3_indexed_read );
67		WRITE8_HANDLER( apple3_indexed_write );
68	72
69	73
70	74	/*----------- defined in video/apple3.c -----------*/

src/mess/includes/dai.h

r14963	r14964
26	26	device_t *m_tms5501;
27	27	UINT8 m_keyboard_scan_mask;
28	28	unsigned short m_4_colours_palette[4];
	29	DECLARE_WRITE8_MEMBER(dai_stack_interrupt_circuit_w);
	30	DECLARE_READ8_MEMBER(dai_io_discrete_devices_r);
	31	DECLARE_WRITE8_MEMBER(dai_io_discrete_devices_w);
	32	DECLARE_READ8_MEMBER(dai_amd9511_r);
	33	DECLARE_WRITE8_MEMBER(dai_amd9511_w);
29	34	};
30	35
31	36
r14963	r14964
37	42
38	43	MACHINE_START( dai );
39	44	MACHINE_RESET( dai );
40		READ8_HANDLER( dai_io_discrete_devices_r );
41		WRITE8_HANDLER( dai_io_discrete_devices_w );
42		WRITE8_HANDLER( dai_stack_interrupt_circuit_w );
43		READ8_HANDLER( dai_amd9511_r );
44		WRITE8_HANDLER( dai_amd9511_w );
45	45
46	46
47	47	/*----------- defined in video/dai.c -----------*/

src/mess/includes/nc.h

r14963	r14964
54	54	UINT8 m_type;
55	55	int m_card_size;
56	56	int m_nc200_backlight;
	57	DECLARE_READ8_MEMBER(nc_memory_management_r);
	58	DECLARE_WRITE8_MEMBER(nc_memory_management_w);
	59	DECLARE_WRITE8_MEMBER(nc_irq_mask_w);
	60	DECLARE_WRITE8_MEMBER(nc_irq_status_w);
	61	DECLARE_READ8_MEMBER(nc_irq_status_r);
	62	DECLARE_READ8_MEMBER(nc_key_data_in_r);
	63	DECLARE_WRITE8_MEMBER(nc_sound_w);
	64	DECLARE_WRITE8_MEMBER(nc_uart_control_w);
	65	DECLARE_WRITE8_MEMBER(nc100_display_memory_start_w);
	66	DECLARE_WRITE8_MEMBER(nc100_uart_control_w);
	67	DECLARE_WRITE8_MEMBER(nc100_poweroff_control_w);
	68	DECLARE_READ8_MEMBER(nc100_card_battery_status_r);
	69	DECLARE_WRITE8_MEMBER(nc100_memory_card_wait_state_w);
	70	DECLARE_WRITE8_MEMBER(nc200_display_memory_start_w);
	71	DECLARE_READ8_MEMBER(nc200_card_battery_status_r);
	72	DECLARE_READ8_MEMBER(nc200_printer_status_r);
	73	DECLARE_WRITE8_MEMBER(nc200_uart_control_w);
	74	DECLARE_WRITE8_MEMBER(nc200_memory_card_wait_state_w);
	75	DECLARE_WRITE8_MEMBER(nc200_poweroff_control_w);
57	76	};
58	77
59	78

src/mess/includes/cbmb.h

r14963	r14964
55	55	int m_old_level;
56	56	int m_irq_level;
57	57	int m_font;
	58	DECLARE_WRITE8_MEMBER(cbmb_colorram_w);
58	59	};
59	60
60	61	/*----------- defined in machine/cbmb.c -----------*/
61	62
62	63	extern const mos6526_interface cbmb_cia;
63	64
64		WRITE8_HANDLER ( cbmb_colorram_w );
65	65
66	66	READ8_DEVICE_HANDLER( cbmb_tpi0_port_a_r );
67	67	WRITE8_DEVICE_HANDLER( cbmb_tpi0_port_a_w );

src/mess/includes/nes.h

r14963	r14964
247	247	/* these are used in the mapper 20 handlers */
248	248	int     m_fds_last_side;
249	249	int     m_fds_count;
	250	DECLARE_READ8_MEMBER(nes_IN0_r);
	251	DECLARE_READ8_MEMBER(nes_IN1_r);
	252	DECLARE_WRITE8_MEMBER(nes_IN0_w);
	253	DECLARE_WRITE8_MEMBER(nes_IN1_w);
	254	DECLARE_READ8_MEMBER(nes_fds_r);
	255	DECLARE_WRITE8_MEMBER(nes_fds_w);
	256	DECLARE_WRITE8_MEMBER(nes_vh_sprite_dma_w);
250	257	};
251	258
252	259
253	260	/*----------- defined in machine/nes.c -----------*/
254	261
255		WRITE8_HANDLER ( nes_IN0_w );
256		WRITE8_HANDLER ( nes_IN1_w );
257	262
258	263	/* protos */
259	264
r14963	r14964
267	272
268	273	DRIVER_INIT( famicom );
269	274
270		READ8_HANDLER( nes_IN0_r );
271		READ8_HANDLER( nes_IN1_r );
272	275
273	276	int nes_ppu_vidaccess( device_t *device, int address, int data );
274	277

src/mess/includes/gb.h

r14963	r14964
181	181	void (*update_scanline)( running_machine &machine );
182	182
183	183	bitmap_ind16 m_bitmap;
	184	DECLARE_WRITE8_MEMBER(gb_rom_bank_select_mbc1);
	185	DECLARE_WRITE8_MEMBER(gb_rom_bank_select_mbc2);
	186	DECLARE_WRITE8_MEMBER(gb_rom_bank_select_mbc3);
	187	DECLARE_WRITE8_MEMBER(gb_rom_bank_select_mbc5);
	188	DECLARE_WRITE8_MEMBER(gb_ram_bank_select_mbc6);
	189	DECLARE_WRITE8_MEMBER(gb_rom_bank_select_mbc6_1);
	190	DECLARE_WRITE8_MEMBER(gb_rom_bank_select_mbc6_2);
	191	DECLARE_WRITE8_MEMBER(gb_rom_bank_select_mbc7);
	192	DECLARE_WRITE8_MEMBER(gb_rom_bank_unknown_mbc7);
	193	DECLARE_WRITE8_MEMBER(gb_rom_bank_select_wisdom);
	194	DECLARE_WRITE8_MEMBER(gb_ram_bank_select_mbc1);
	195	DECLARE_WRITE8_MEMBER(gb_ram_bank_select_mbc3);
	196	DECLARE_WRITE8_MEMBER(gb_ram_bank_select_mbc5);
	197	DECLARE_WRITE8_MEMBER(gb_ram_enable);
	198	DECLARE_WRITE8_MEMBER(gb_mem_mode_select_mbc1);
	199	DECLARE_WRITE8_MEMBER(gb_mem_mode_select_mbc3);
	200	DECLARE_WRITE8_MEMBER(gb_ram_tama5);
	201	DECLARE_WRITE8_MEMBER(gb_rom_bank_mmm01_0000_w);
	202	DECLARE_WRITE8_MEMBER(gb_rom_bank_mmm01_2000_w);
	203	DECLARE_WRITE8_MEMBER(gb_rom_bank_mmm01_4000_w);
	204	DECLARE_WRITE8_MEMBER(gb_rom_bank_mmm01_6000_w);
	205	DECLARE_WRITE8_MEMBER(gb_rom_bank_select_mbc1_kor);
	206	DECLARE_WRITE8_MEMBER(gb_ram_bank_select_mbc1_kor);
	207	DECLARE_WRITE8_MEMBER(gb_mem_mode_select_mbc1_kor);
	208	DECLARE_WRITE8_MEMBER(gb_io_w);
	209	DECLARE_WRITE8_MEMBER(gb_io2_w);
	210	DECLARE_WRITE8_MEMBER(sgb_io_w);
	211	DECLARE_READ8_MEMBER(gb_ie_r);
	212	DECLARE_WRITE8_MEMBER(gb_ie_w);
	213	DECLARE_READ8_MEMBER(gb_io_r);
	214	DECLARE_WRITE8_MEMBER(gbc_io2_w);
	215	DECLARE_READ8_MEMBER(gbc_io2_r);
	216	DECLARE_READ8_MEMBER(megaduck_video_r);
	217	DECLARE_WRITE8_MEMBER(megaduck_video_w);
	218	DECLARE_WRITE8_MEMBER(megaduck_sound_w1);
	219	DECLARE_READ8_MEMBER(megaduck_sound_r1);
	220	DECLARE_WRITE8_MEMBER(megaduck_sound_w2);
	221	DECLARE_READ8_MEMBER(megaduck_sound_r2);
	222	DECLARE_WRITE8_MEMBER(megaduck_rom_bank_select_type1);
	223	DECLARE_WRITE8_MEMBER(megaduck_rom_bank_select_type2);
	224	DECLARE_READ8_MEMBER(gb_video_r);
	225	DECLARE_READ8_MEMBER(gb_vram_r);
	226	DECLARE_WRITE8_MEMBER(gb_vram_w);
	227	DECLARE_READ8_MEMBER(gb_oam_r);
	228	DECLARE_WRITE8_MEMBER(gb_oam_w);
	229	DECLARE_WRITE8_MEMBER(gb_video_w);
	230	DECLARE_READ8_MEMBER(gbc_video_r);
	231	DECLARE_WRITE8_MEMBER(gbc_video_w);
184	232	};
185	233
186	234
187	235	/*----------- defined in machine/gb.c -----------*/
188	236
189		WRITE8_HANDLER( gb_ram_enable );
190		WRITE8_HANDLER( gb_io_w );
191		READ8_HANDLER ( gb_io_r );
192		WRITE8_HANDLER( gb_io2_w );
193		READ8_HANDLER( gb_ie_r );
194		WRITE8_HANDLER( gb_ie_w );
195	237	DEVICE_START(gb_cart);
196	238	DEVICE_IMAGE_LOAD(gb_cart);
197	239	INTERRUPT_GEN( gb_scanline_interrupt );
198	240	void gb_timer_callback(lr35902_cpu_device *device, int cycles);
199		WRITE8_HANDLER( gbc_io2_w );
200		READ8_HANDLER( gbc_io2_r );
201	241	MACHINE_START( gb );
202	242	MACHINE_RESET( gb );
203	243	MACHINE_RESET( gbpocket );
r14963	r14964
210	250
211	251	extern MACHINE_START( sgb );
212	252	extern MACHINE_RESET( sgb );
213		extern WRITE8_HANDLER ( sgb_io_w );
214	253
215	254	MACHINE_START( gbc );
216	255	MACHINE_RESET( gbc );
r14963	r14964
220	259	extern DEVICE_IMAGE_LOAD(megaduck_cart);
221	260	extern MACHINE_START( megaduck );
222	261	extern MACHINE_RESET( megaduck );
223		extern  READ8_HANDLER( megaduck_video_r );
224		extern WRITE8_HANDLER( megaduck_video_w );
225		extern WRITE8_HANDLER( megaduck_rom_bank_select_type1 );
226		extern WRITE8_HANDLER( megaduck_rom_bank_select_type2 );
227		extern  READ8_HANDLER( megaduck_sound_r1 );
228		extern WRITE8_HANDLER( megaduck_sound_w1 );
229		extern  READ8_HANDLER( megaduck_sound_r2 );
230		extern WRITE8_HANDLER( megaduck_sound_w2 );
231	262
232	263
233	264	/*----------- defined in video/gb.c -----------*/
234	265
235		READ8_HANDLER( gbc_video_r );
236		WRITE8_HANDLER ( gbc_video_w );
237	266
238		READ8_HANDLER( gb_oam_r );
239		WRITE8_HANDLER( gb_oam_w );
240		READ8_HANDLER( gb_vram_r );
241		WRITE8_HANDLER( gb_vram_w );
242	267
243	268	enum
244	269	{
r14963	r14964
254	279	PALETTE_INIT( gbc );
255	280	PALETTE_INIT( megaduck );
256	281
257		READ8_HANDLER( gb_video_r );
258		WRITE8_HANDLER( gb_video_w );
259	282	MACHINE_START( gb_video );
260	283	MACHINE_START( gbc_video );
261	284	void gb_video_reset( running_machine &machine, int mode );

src/mess/includes/concept.h

r14963	r14964
48	48	UINT8 m_fdc_local_status;
49	49	UINT8 m_fdc_local_command;
50	50	expansion_slot_t m_expansion_slots[4];
	51	DECLARE_READ16_MEMBER(concept_io_r);
	52	DECLARE_WRITE16_MEMBER(concept_io_w);
	53	DECLARE_WRITE8_MEMBER(concept_fdc_reg_w);
	54	DECLARE_READ8_MEMBER(concept_hdc_reg_r);
	55	DECLARE_WRITE8_MEMBER(concept_hdc_reg_w);
51	56	};
52	57
53	58
r14963	r14964
60	65	VIDEO_START(concept);
61	66	SCREEN_UPDATE_IND16(concept);
62	67	INTERRUPT_GEN( concept_interrupt );
63		READ16_HANDLER(concept_io_r);
64		WRITE16_HANDLER(concept_io_w);
65	68
66	69
67	70	#endif /* CONCEPT_H_ */

src/mess/includes/pcw16.h

r14963	r14964
48	48	int m_previous_fdc_int_state;
49	49	int m_colour_palette[16];
50	50	int m_video_control;
	51	DECLARE_WRITE8_MEMBER(pcw16_palette_w);
	52	DECLARE_READ8_MEMBER(pcw16_no_mem_r);
	53	DECLARE_READ8_MEMBER(pcw16_bankhw_r);
	54	DECLARE_WRITE8_MEMBER(pcw16_bankhw_w);
	55	DECLARE_WRITE8_MEMBER(pcw16_video_control_w);
	56	DECLARE_READ8_MEMBER(pcw16_keyboard_data_shift_r);
	57	DECLARE_WRITE8_MEMBER(pcw16_keyboard_data_shift_w);
	58	DECLARE_READ8_MEMBER(pcw16_keyboard_status_r);
	59	DECLARE_WRITE8_MEMBER(pcw16_keyboard_control_w);
	60	DECLARE_READ8_MEMBER(rtc_year_invalid_r);
	61	DECLARE_READ8_MEMBER(rtc_month_r);
	62	DECLARE_READ8_MEMBER(rtc_days_r);
	63	DECLARE_READ8_MEMBER(rtc_hours_r);
	64	DECLARE_READ8_MEMBER(rtc_minutes_r);
	65	DECLARE_READ8_MEMBER(rtc_seconds_r);
	66	DECLARE_READ8_MEMBER(rtc_256ths_seconds_r);
	67	DECLARE_WRITE8_MEMBER(rtc_control_w);
	68	DECLARE_WRITE8_MEMBER(rtc_seconds_w);
	69	DECLARE_WRITE8_MEMBER(rtc_minutes_w);
	70	DECLARE_WRITE8_MEMBER(rtc_hours_w);
	71	DECLARE_WRITE8_MEMBER(rtc_days_w);
	72	DECLARE_WRITE8_MEMBER(rtc_month_w);
	73	DECLARE_WRITE8_MEMBER(rtc_year_w);
	74	DECLARE_READ8_MEMBER(pcw16_system_status_r);
	75	DECLARE_READ8_MEMBER(pcw16_timer_interrupt_counter_r);
	76	DECLARE_WRITE8_MEMBER(pcw16_system_control_w);
	77	DECLARE_WRITE8_MEMBER(pcw16_superio_fdc_datarate_w);
	78	DECLARE_WRITE8_MEMBER(pcw16_superio_fdc_digital_output_register_w);
	79	DECLARE_WRITE8_MEMBER(pcw16_superio_fdc_data_w);
	80	DECLARE_READ8_MEMBER(pcw16_superio_fdc_data_r);
	81	DECLARE_READ8_MEMBER(pcw16_superio_fdc_main_status_register_r);
	82	DECLARE_READ8_MEMBER(pcw16_superio_fdc_digital_input_register_r);
	83	void pcw16_keyboard_init();
	84	void pcw16_keyboard_refresh_outputs();
	85	void pcw16_keyboard_set_clock_state(int state);
	86	void pcw16_keyboard_int(int state);
	87	void pcw16_keyboard_reset();
	88	int pcw16_keyboard_can_transmit();
	89	void pcw16_keyboard_signal_byte_received(int data);
	90	void pcw16_refresh_ints();
	91	void rtc_setup_max_days();
51	92	};
52	93
53	94

src/mess/includes/msx.h

r14963	r14964
115	115	required_device<device_t> m_ym;
116	116	required_device<device_t> m_dac;
117	117	optional_device<rp5c01_device> m_rtc;
	118	DECLARE_READ8_MEMBER(msx_psg_port_a_r);
	119	DECLARE_READ8_MEMBER(msx_psg_port_b_r);
	120	DECLARE_WRITE8_MEMBER(msx_psg_port_a_w);
	121	DECLARE_WRITE8_MEMBER(msx_psg_port_b_w);
118	122	};
119	123
120	124
r14963	r14964
141	145	WRITE8_DEVICE_HANDLER( msx_printer_strobe_w );
142	146	WRITE8_DEVICE_HANDLER( msx_printer_data_w );
143	147
144		WRITE8_HANDLER ( msx_psg_port_a_w );
145		READ8_HANDLER ( msx_psg_port_a_r );
146		WRITE8_HANDLER ( msx_psg_port_b_w );
147		READ8_HANDLER ( msx_psg_port_b_r );
148	148
149	149	#endif /* __MSX_H__ */

src/mess/includes/radio86.h

r14963	r14964
30	30	UINT8 m_romdisk_lsb;
31	31	UINT8 m_romdisk_msb;
32	32	UINT8 m_disk_sel;
	33	DECLARE_READ8_MEMBER(radio_cpu_state_r);
	34	DECLARE_READ8_MEMBER(radio_io_r);
	35	DECLARE_WRITE8_MEMBER(radio_io_w);
	36	DECLARE_WRITE8_MEMBER(radio86_pagesel);
33	37	};
34	38
35	39
r14963	r14964
45	49	extern DRIVER_INIT( radioram );
46	50	extern MACHINE_RESET( radio86 );
47	51
48		extern READ8_HANDLER (radio_cpu_state_r );
49	52
50		extern READ8_HANDLER (radio_io_r );
51		extern WRITE8_HANDLER(radio_io_w );
52	53
53	54	extern const i8255_interface radio86_ppi8255_interface_1;
54	55	extern const i8255_interface radio86_ppi8255_interface_2;
r14963	r14964
62	63	extern const i8275_interface mikrosha_i8275_interface;
63	64	extern const i8275_interface apogee_i8275_interface;
64	65
65		extern WRITE8_HANDLER ( radio86_pagesel );
66	66	extern const i8257_interface radio86_dma;
67	67
68	68

src/mess/includes/mz700.h

r14963	r14964
52	52	UINT16 m_mz800_ramaddr;
53	53	UINT8 m_mz800_palette[4];
54	54	UINT8 m_mz800_palette_bank;
	55	DECLARE_READ8_MEMBER(mz700_e008_r);
	56	DECLARE_WRITE8_MEMBER(mz700_e008_w);
	57	DECLARE_READ8_MEMBER(mz800_bank_0_r);
	58	DECLARE_WRITE8_MEMBER(mz700_bank_0_w);
	59	DECLARE_WRITE8_MEMBER(mz800_bank_0_w);
	60	DECLARE_READ8_MEMBER(mz800_bank_1_r);
	61	DECLARE_WRITE8_MEMBER(mz700_bank_1_w);
	62	DECLARE_WRITE8_MEMBER(mz700_bank_2_w);
	63	DECLARE_WRITE8_MEMBER(mz700_bank_3_w);
	64	DECLARE_WRITE8_MEMBER(mz700_bank_4_w);
	65	DECLARE_WRITE8_MEMBER(mz700_bank_5_w);
	66	DECLARE_WRITE8_MEMBER(mz700_bank_6_w);
	67	DECLARE_READ8_MEMBER(mz800_crtc_r);
	68	DECLARE_WRITE8_MEMBER(mz800_write_format_w);
	69	DECLARE_WRITE8_MEMBER(mz800_read_format_w);
	70	DECLARE_WRITE8_MEMBER(mz800_display_mode_w);
	71	DECLARE_WRITE8_MEMBER(mz800_scroll_border_w);
	72	DECLARE_READ8_MEMBER(mz800_ramdisk_r);
	73	DECLARE_WRITE8_MEMBER(mz800_ramdisk_w);
	74	DECLARE_WRITE8_MEMBER(mz800_ramaddr_w);
	75	DECLARE_WRITE8_MEMBER(mz800_palette_w);
	76	DECLARE_WRITE8_MEMBER(mz800_cgram_w);
55	77	};
56	78
57	79
r14963	r14964
67	89	MACHINE_START( mz700 );
68	90
69	91	/* bank switching */
70		WRITE8_HANDLER( mz700_bank_0_w );
71		WRITE8_HANDLER( mz700_bank_1_w );
72		WRITE8_HANDLER( mz700_bank_2_w );
73		WRITE8_HANDLER( mz700_bank_3_w );
74		WRITE8_HANDLER( mz700_bank_4_w );
75		WRITE8_HANDLER( mz700_bank_5_w );
76		WRITE8_HANDLER( mz700_bank_6_w );
77	92
78	93	/* bankswitching, mz800 only */
79		READ8_HANDLER( mz800_bank_0_r );
80		READ8_HANDLER( mz800_bank_1_r );
81		WRITE8_HANDLER( mz800_bank_0_w );
82	94
83	95
84		READ8_HANDLER( mz800_crtc_r );
85		READ8_HANDLER( mz800_ramdisk_r );
86	96
87		WRITE8_HANDLER( mz800_write_format_w );
88		WRITE8_HANDLER( mz800_read_format_w );
89		WRITE8_HANDLER( mz800_display_mode_w );
90		WRITE8_HANDLER( mz800_scroll_border_w );
91		WRITE8_HANDLER( mz800_ramdisk_w );
92		WRITE8_HANDLER( mz800_ramaddr_w );
93		WRITE8_HANDLER( mz800_palette_w );
94	97
95
96	98	/*----------- defined in video/mz700.c -----------*/
97	99
98	100	PALETTE_INIT( mz700 );
99	101	SCREEN_UPDATE_IND16( mz700 );
100	102	VIDEO_START( mz800 );
101	103	SCREEN_UPDATE_IND16( mz800 );
102		WRITE8_HANDLER( mz800_cgram_w );
103	104
104	105
105	106	#endif /* MZ700_H_ */

src/mess/includes/b2m.h

r14963	r14964
38	38	device_t *m_fdc;
39	39	device_t *m_pic;
40	40	device_t *m_speaker;
	41	DECLARE_READ8_MEMBER(b2m_keyboard_r);
	42	DECLARE_WRITE8_MEMBER(b2m_palette_w);
	43	DECLARE_READ8_MEMBER(b2m_palette_r);
	44	DECLARE_WRITE8_MEMBER(b2m_localmachine_w);
	45	DECLARE_READ8_MEMBER(b2m_localmachine_r);
41	46	};
42	47
43	48	/*----------- defined in machine/b2m.c -----------*/
r14963	r14964
53	58	extern MACHINE_START( b2m );
54	59	extern MACHINE_RESET( b2m );
55	60	extern INTERRUPT_GEN( b2m_vblank_interrupt );
56		extern READ8_HANDLER( b2m_palette_r );
57		extern WRITE8_HANDLER( b2m_palette_w );
58		extern READ8_HANDLER( b2m_localmachine_r );
59		extern WRITE8_HANDLER( b2m_localmachine_w );
60	61
61	62	/*----------- defined in video/b2m.c -----------*/
62	63

src/mess/includes/apollo.h

r14963	r14964
37	37	#define MLOG(x)  { logerror ("%s: ", apollo_cpu_context(machine.device(MAINCPU))); LOG(x) }
38	38	#define MLOG1(x) { if (VERBOSE > 0) MLOG(x) }
39	39	#define MLOG2(x) { if (VERBOSE > 1) MLOG(x) }
40		#define SLOG(x)  { logerror ("%s: ", apollo_cpu_context(&space->device())); LOG(x) }
	40	#define SLOG(x)  { logerror ("%s: ", apollo_cpu_context(&space.device())); LOG(x) }
41	41	#define SLOG1(x) { if (VERBOSE > 0) SLOG(x) }
42	42	#define SLOG2(x) { if (VERBOSE > 1) SLOG(x) }
43	43
r14963	r14964
121	121	device_t *pic8259_master;
122	122	device_t *pic8259_slave;
123	123
	124	DECLARE_WRITE16_MEMBER(apollo_csr_status_register_w);
	125	DECLARE_READ16_MEMBER(apollo_csr_status_register_r);
	126	DECLARE_WRITE16_MEMBER(apollo_csr_control_register_w);
	127	DECLARE_READ16_MEMBER(apollo_csr_control_register_r);
	128	DECLARE_WRITE8_MEMBER(apollo_dma_1_w);
	129	DECLARE_READ8_MEMBER(apollo_dma_1_r);
	130	DECLARE_WRITE8_MEMBER(apollo_dma_2_w);
	131	DECLARE_READ8_MEMBER(apollo_dma_2_r);
	132	DECLARE_WRITE8_MEMBER(apollo_dma_page_register_w);
	133	DECLARE_READ8_MEMBER(apollo_dma_page_register_r);
	134	DECLARE_WRITE16_MEMBER(apollo_address_translation_map_w);
	135	DECLARE_READ16_MEMBER(apollo_address_translation_map_r);
	136	DECLARE_READ8_MEMBER(apollo_dma_read_byte);
	137	DECLARE_WRITE8_MEMBER(apollo_dma_write_byte);
	138	DECLARE_READ8_MEMBER(apollo_dma_read_word);
	139	DECLARE_WRITE8_MEMBER(apollo_dma_write_word);
	140	DECLARE_WRITE8_MEMBER(apollo_rtc_w);
	141	DECLARE_READ8_MEMBER(apollo_rtc_r);
	142	DECLARE_WRITE8_MEMBER(apollo_fdc_w);
	143	DECLARE_READ8_MEMBER(apollo_fdc_r);
	144	DECLARE_WRITE8_MEMBER(cache_control_register_w);
	145	DECLARE_READ8_MEMBER(cache_status_register_r);
	146	DECLARE_WRITE8_MEMBER(task_alias_register_w);
	147	DECLARE_READ8_MEMBER(task_alias_register_r);
	148	DECLARE_WRITE16_MEMBER(apollo_node_id_w);
	149	DECLARE_READ16_MEMBER(apollo_node_id_r);
	150	DECLARE_WRITE16_MEMBER(latch_page_on_parity_error_register_w);
	151	DECLARE_READ16_MEMBER(latch_page_on_parity_error_register_r);
	152	DECLARE_WRITE8_MEMBER(master_req_register_w);
	153	DECLARE_READ8_MEMBER(master_req_register_r);
	154	DECLARE_WRITE16_MEMBER(selective_clear_locations_w);
	155	DECLARE_READ16_MEMBER(selective_clear_locations_r);
	156	DECLARE_READ32_MEMBER(ram_with_parity_r);
	157	DECLARE_WRITE32_MEMBER(ram_with_parity_w);
	158	DECLARE_READ32_MEMBER(apollo_unmapped_r);
	159	DECLARE_WRITE32_MEMBER(apollo_unmapped_w);
	160	DECLARE_WRITE32_MEMBER(apollo_rom_w);
	161	DECLARE_READ16_MEMBER(apollo_atbus_io_r);
	162	DECLARE_WRITE16_MEMBER(apollo_atbus_io_w);
	163	DECLARE_READ32_MEMBER(apollo_atbus_memory_r);
	164	DECLARE_WRITE32_MEMBER(apollo_atbus_memory_w);
	165	DECLARE_WRITE8_MEMBER(dn5500_memory_present_register_w);
	166	DECLARE_READ8_MEMBER(dn5500_memory_present_register_r);
	167	DECLARE_WRITE8_MEMBER(dn5500_11500_w);
	168	DECLARE_READ8_MEMBER(dn5500_11500_r);
	169	DECLARE_WRITE8_MEMBER(dn5500_io_protection_map_w);
	170	DECLARE_READ8_MEMBER(dn5500_io_protection_map_r);
	171	DECLARE_READ32_MEMBER(apollo_f8_r);
	172	DECLARE_WRITE32_MEMBER(apollo_f8_w);
124	173	};
125	174
126	175	MACHINE_CONFIG_EXTERN( apollo );
r14963	r14964
170	219	UINT16 apollo_csr_get_status_register(void);
171	220	void apollo_csr_set_status_register(UINT16 mask, UINT16 data);
172	221
173		WRITE16_HANDLER( apollo_csr_status_register_w );
174		READ16_HANDLER( apollo_csr_status_register_r );
175		WRITE16_HANDLER( apollo_csr_control_register_w );
176		READ16_HANDLER( apollo_csr_control_register_r );
177	222
178	223	/*----------- machine/apollo_dma.c -----------*/
179	224
180		WRITE8_HANDLER(apollo_dma_1_w );
181		READ8_HANDLER( apollo_dma_1_r );
182	225
183		WRITE8_HANDLER(apollo_dma_2_w );
184		READ8_HANDLER( apollo_dma_2_r );
185	226
186		WRITE8_HANDLER(apollo_dma_page_register_w );
187		READ8_HANDLER( apollo_dma_page_register_r );
188	227
189		WRITE16_HANDLER(apollo_address_translation_map_w );
190		READ16_HANDLER( apollo_address_translation_map_r );
191	228
192	229	/*----------- machine/apollo_pic.c -----------*/
193	230
r14963	r14964
206	243
207	244	/*----------- machine/apollo_rtc.c -----------*/
208	245
209		WRITE8_HANDLER( apollo_rtc_w );
210		READ8_HANDLER( apollo_rtc_r );
211	246
212	247	/*----------- machine/apollo_sio.c -----------*/
213	248
r14963	r14964
223	258
224	259	/*----------- machine/apollo_fdc.c -----------*/
225	260
226		READ8_HANDLER(apollo_fdc_r);
227		WRITE8_HANDLER(apollo_fdc_w);
228	261
229	262	/*----------- machine/apollo_eth.c -----------*/
230	263

src/mess/includes/lisa.h

r14963	r14964
139	139	int m_last_my;
140	140	int m_frame_count;
141	141	int m_videoROM_address;
	142	DECLARE_READ8_MEMBER(lisa_fdc_io_r);
	143	DECLARE_WRITE8_MEMBER(lisa_fdc_io_w);
	144	DECLARE_READ8_MEMBER(lisa_fdc_r);
	145	DECLARE_READ8_MEMBER(lisa210_fdc_r);
	146	DECLARE_WRITE8_MEMBER(lisa_fdc_w);
	147	DECLARE_WRITE8_MEMBER(lisa210_fdc_w);
	148	DECLARE_READ16_MEMBER(lisa_r);
	149	DECLARE_WRITE16_MEMBER(lisa_w);
	150	DECLARE_READ16_MEMBER(lisa_IO_r);
	151	DECLARE_WRITE16_MEMBER(lisa_IO_w);
142	152	};
143	153
144	154
r14963	r14964
161	171
162	172	INTERRUPT_GEN( lisa_interrupt );
163	173
164		READ8_HANDLER ( lisa_fdc_io_r );
165		WRITE8_HANDLER ( lisa_fdc_io_w );
166		READ8_HANDLER ( lisa_fdc_r );
167		READ8_HANDLER ( lisa210_fdc_r );
168		WRITE8_HANDLER ( lisa_fdc_w );
169		WRITE8_HANDLER ( lisa210_fdc_w );
170		READ16_HANDLER ( lisa_r );
171		WRITE16_HANDLER ( lisa_w );
172	174
173	175
174	176	#endif /* LISA_H_ */

src/mess/includes/aquarius.h

r14963	r14964
19	19	UINT8 m_scrambler;
20	20	required_shared_ptr<UINT8> m_colorram;
21	21	tilemap_t *m_tilemap;
	22	DECLARE_WRITE8_MEMBER(aquarius_videoram_w);
	23	DECLARE_WRITE8_MEMBER(aquarius_colorram_w);
	24	DECLARE_READ8_MEMBER(cassette_r);
	25	DECLARE_WRITE8_MEMBER(cassette_w);
	26	DECLARE_READ8_MEMBER(vsync_r);
	27	DECLARE_WRITE8_MEMBER(mapper_w);
	28	DECLARE_READ8_MEMBER(printer_r);
	29	DECLARE_WRITE8_MEMBER(printer_w);
	30	DECLARE_READ8_MEMBER(keyboard_r);
	31	DECLARE_WRITE8_MEMBER(scrambler_w);
	32	DECLARE_READ8_MEMBER(cartridge_r);
	33	DECLARE_READ8_MEMBER(floppy_r);
	34	DECLARE_WRITE8_MEMBER(floppy_w);
22	35	};
23	36
24	37
25	38	/*----------- defined in video/aquarius.c -----------*/
26	39
27		WRITE8_HANDLER( aquarius_videoram_w );
28		WRITE8_HANDLER( aquarius_colorram_w );
29	40
30	41	PALETTE_INIT( aquarius );
31	42	VIDEO_START( aquarius );

src/mess/includes/lynx.h

r14963	r14964
126	126	UART m_uart;
127	127	bitmap_ind16 m_bitmap;
128	128	bitmap_ind16 m_bitmap_temp;
	129	DECLARE_READ8_MEMBER(suzy_read);
	130	DECLARE_WRITE8_MEMBER(suzy_write);
	131	DECLARE_WRITE8_MEMBER(lynx_uart_w);
	132	DECLARE_READ8_MEMBER(mikey_read);
	133	DECLARE_WRITE8_MEMBER(mikey_write);
	134	DECLARE_READ8_MEMBER(lynx_memory_config_r);
	135	DECLARE_WRITE8_MEMBER(lynx_memory_config_w);
	136	void lynx_divide();
	137	void lynx_multiply();
	138	UINT8 lynx_timer_read(int which, int offset);
	139	void lynx_timer_write(int which, int offset, UINT8 data);
129	140	};
130	141
131	142
r14963	r14964
134	145	MACHINE_START( lynx );
135	146	MACHINE_RESET( lynx );
136	147
137		READ8_HANDLER( lynx_memory_config_r );
138		WRITE8_HANDLER( lynx_memory_config_w );
139	148	void lynx_timer_count_down(running_machine &machine, int nr);
140	149
141	150	INTERRUPT_GEN( lynx_frame_int );

src/mess/includes/pmd85.h

r14963	r14964
25	25	UINT8 m_model;
26	26	emu_timer * m_cassette_timer;
27	27	void (*update_memory)(running_machine &);
	28	DECLARE_READ8_MEMBER(pmd85_io_r);
	29	DECLARE_WRITE8_MEMBER(pmd85_io_w);
	30	DECLARE_READ8_MEMBER(mato_io_r);
	31	DECLARE_WRITE8_MEMBER(mato_io_w);
28	32	};
29	33
30	34
r14963	r14964
35	39	extern const i8255_interface alfa_ppi8255_interface[3];
36	40	extern const i8255_interface mato_ppi8255_interface;
37	41
38		READ8_HANDLER ( pmd85_io_r );
39		WRITE8_HANDLER ( pmd85_io_w );
40		READ8_HANDLER ( mato_io_r );
41		WRITE8_HANDLER ( mato_io_w );
42	42	DRIVER_INIT ( pmd851 );
43	43	DRIVER_INIT ( pmd852a );
44	44	DRIVER_INIT ( pmd853 );

src/mess/includes/spectrum.h

r14963	r14964
100	100
101	101	UINT8 *m_ram_0000;
102	102	UINT8 m_ram_disabled_by_beta;
	103	DECLARE_WRITE8_MEMBER(spectrum_port_fe_w);
	104	DECLARE_READ8_MEMBER(spectrum_port_fe_r);
	105	DECLARE_READ8_MEMBER(spectrum_port_1f_r);
	106	DECLARE_READ8_MEMBER(spectrum_port_7f_r);
	107	DECLARE_READ8_MEMBER(spectrum_port_df_r);
	108	DECLARE_READ8_MEMBER(spectrum_port_ula_r);
103	109	};
104	110
105	111
r14963	r14964
111	117	MACHINE_CONFIG_EXTERN( spectrum );
112	118	MACHINE_RESET( spectrum );
113	119
114		READ8_HANDLER(spectrum_port_1f_r);
115		READ8_HANDLER(spectrum_port_7f_r);
116		READ8_HANDLER(spectrum_port_df_r);
117		READ8_HANDLER(spectrum_port_fe_r);
118		WRITE8_HANDLER(spectrum_port_fe_w);
119	120
120	121	/*----------- defined in drivers/spec128.c -----------*/
121	122

src/mess/includes/ondra.h

r14963	r14964
16	16	UINT8 m_video_enable;
17	17	UINT8 m_bank1_status;
18	18	UINT8 m_bank2_status;
	19	DECLARE_READ8_MEMBER(ondra_keyboard_r);
	20	DECLARE_WRITE8_MEMBER(ondra_port_03_w);
	21	DECLARE_WRITE8_MEMBER(ondra_port_09_w);
	22	DECLARE_WRITE8_MEMBER(ondra_port_0a_w);
19	23	};
20	24
21	25
r14963	r14964
24	28	extern MACHINE_START( ondra );
25	29	extern MACHINE_RESET( ondra );
26	30
27		extern WRITE8_HANDLER( ondra_port_03_w );
28		extern WRITE8_HANDLER( ondra_port_09_w );
29		extern WRITE8_HANDLER( ondra_port_0a_w );
30	31	/*----------- defined in video/ondra.c -----------*/
31	32
32	33	extern VIDEO_START( ondra );

src/mess/includes/lviv.h

r14963	r14964
20	20	unsigned short m_colortable[1][4];
21	21	UINT8 m_ppi_port_outputs[2][3];
22	22	UINT8 m_startup_mem_map;
	23	DECLARE_READ8_MEMBER(lviv_io_r);
	24	DECLARE_WRITE8_MEMBER(lviv_io_w);
23	25	};
24	26
25	27
r14963	r14964
28	30	extern const i8255_interface lviv_ppi8255_interface_0;
29	31	extern const i8255_interface lviv_ppi8255_interface_1;
30	32
31		READ8_HANDLER ( lviv_io_r );
32		WRITE8_HANDLER ( lviv_io_w );
33	33	MACHINE_RESET( lviv );
34	34	SNAPSHOT_LOAD( lviv );
35	35

src/mess/includes/pcw.h

r14963	r14964
60	60	UINT8 m_printer_p2_prev;
61	61	emu_timer* m_prn_stepper;
62	62	emu_timer* m_prn_pins;
	63	DECLARE_READ8_MEMBER(pcw_keyboard_r);
	64	DECLARE_READ8_MEMBER(pcw_keyboard_data_r);
	65	DECLARE_READ8_MEMBER(pcw_interrupt_counter_r);
	66	DECLARE_WRITE8_MEMBER(pcw_bank_select_w);
	67	DECLARE_WRITE8_MEMBER(pcw_bank_force_selection_w);
	68	DECLARE_WRITE8_MEMBER(pcw_roller_ram_addr_w);
	69	DECLARE_WRITE8_MEMBER(pcw_pointer_table_top_scan_w);
	70	DECLARE_WRITE8_MEMBER(pcw_vdu_video_control_register_w);
	71	DECLARE_WRITE8_MEMBER(pcw_system_control_w);
	72	DECLARE_READ8_MEMBER(pcw_system_status_r);
	73	DECLARE_READ8_MEMBER(pcw_expansion_r);
	74	DECLARE_WRITE8_MEMBER(pcw_expansion_w);
	75	DECLARE_READ8_MEMBER(pcw_fdc_r);
	76	DECLARE_WRITE8_MEMBER(pcw_fdc_w);
	77	DECLARE_WRITE8_MEMBER(pcw_printer_data_w);
	78	DECLARE_WRITE8_MEMBER(pcw_printer_command_w);
	79	DECLARE_READ8_MEMBER(pcw_printer_data_r);
	80	DECLARE_READ8_MEMBER(pcw_printer_status_r);
	81	DECLARE_READ8_MEMBER(mcu_printer_p1_r);
	82	DECLARE_WRITE8_MEMBER(mcu_printer_p1_w);
	83	DECLARE_READ8_MEMBER(mcu_printer_p2_r);
	84	DECLARE_WRITE8_MEMBER(mcu_printer_p2_w);
	85	DECLARE_READ8_MEMBER(mcu_printer_t1_r);
	86	DECLARE_READ8_MEMBER(mcu_printer_t0_r);
	87	DECLARE_READ8_MEMBER(mcu_kb_scan_r);
	88	DECLARE_WRITE8_MEMBER(mcu_kb_scan_w);
	89	DECLARE_READ8_MEMBER(mcu_kb_scan_high_r);
	90	DECLARE_WRITE8_MEMBER(mcu_kb_scan_high_w);
	91	DECLARE_READ8_MEMBER(mcu_kb_data_r);
	92	DECLARE_READ8_MEMBER(mcu_kb_t1_r);
	93	DECLARE_READ8_MEMBER(mcu_kb_t0_r);
	94	DECLARE_READ8_MEMBER(pcw9512_parallel_r);
	95	DECLARE_WRITE8_MEMBER(pcw9512_parallel_w);
	96	void mcu_transmit_serial(UINT8 bit);
63	97	};
64	98
65	99

src/mess/includes/oric.h

r14963	r14964
82	82	unsigned char m_telestrat_via2_port_b_data;
83	83	telestrat_mem_block m_telestrat_blocks[8];
84	84	oric_vh_state m_vh_state;
	85	DECLARE_WRITE8_MEMBER(oric_psg_porta_write);
	86	DECLARE_WRITE8_MEMBER(apple2_v2_interface_w);
	87	DECLARE_READ8_MEMBER(oric_jasmin_r);
	88	DECLARE_WRITE8_MEMBER(oric_jasmin_w);
	89	DECLARE_READ8_MEMBER(oric_microdisc_r);
	90	DECLARE_WRITE8_MEMBER(oric_microdisc_w);
	91	DECLARE_READ8_MEMBER(oric_IO_r);
	92	DECLARE_WRITE8_MEMBER(oric_IO_w);
85	93	};
86	94
87	95
r14963	r14964
93	101
94	102	MACHINE_START( oric );
95	103	MACHINE_RESET( oric );
96		READ8_HANDLER( oric_IO_r );
97		WRITE8_HANDLER( oric_IO_w );
98		READ8_HANDLER( oric_microdisc_r );
99		WRITE8_HANDLER( oric_microdisc_w );
100	104
101		WRITE8_HANDLER(oric_psg_porta_write);
102	105
103	106	/* Telestrat specific */
104	107	MACHINE_START( telestrat );

src/mess/includes/enterp.h

r14963	r14964
24	24	UINT8 keyboard_line;     /* index of keyboard line to read */
25	25	bitmap_ind16 m_bitmap;
26	26	struct _NICK_STATE *nick;
	27	DECLARE_READ8_MEMBER(exdos_card_r);
	28	DECLARE_WRITE8_MEMBER(exdos_card_w);
27	29	};
28	30
29	31

src/mess/includes/orao.h

r14963	r14964
18	18
19	19	required_shared_ptr<UINT8> m_memory;
20	20	required_shared_ptr<UINT8> m_video_ram;
	21	DECLARE_READ8_MEMBER(orao_io_r);
	22	DECLARE_WRITE8_MEMBER(orao_io_w);
21	23	};
22	24
23	25
r14963	r14964
28	30
29	31	extern DRIVER_INIT( orao103 );
30	32
31		extern READ8_HANDLER( orao_io_r );
32		extern WRITE8_HANDLER( orao_io_w );
33	33
34	34
35	35	/*----------- defined in video/orao.c -----------*/

src/mess/includes/mbc55x.h

r14963	r14964
142	142	UINT8      m_vram_page;
143	143
144	144	keyboard_t   m_keyboard;
	145	DECLARE_READ8_MEMBER(mbcpic8259_r);
	146	DECLARE_WRITE8_MEMBER(mbcpic8259_w);
	147	DECLARE_READ8_MEMBER(mbcpit8253_r);
	148	DECLARE_WRITE8_MEMBER(mbcpit8253_w);
	149	DECLARE_READ8_MEMBER(mbc55x_disk_r);
	150	DECLARE_WRITE8_MEMBER(mbc55x_disk_w);
	151	DECLARE_READ8_MEMBER(mbc55x_kb_usart_r);
	152	DECLARE_WRITE8_MEMBER(mbc55x_kb_usart_w);
145	153	};
146	154
147	155	/* IO chips */
r14963	r14964
190	198	#define RAM_BANK_COUNT   15
191	199
192	200
193		READ8_HANDLER(pit8253_r);
194		WRITE8_HANDLER(pit8253_w);
195	201	READ8_HANDLER(ppi8255_r);
196	202	WRITE8_HANDLER(ppi8255_w);
197		READ8_HANDLER(pic8259_r);
198		WRITE8_HANDLER(pic8259_w);
199		READ8_HANDLER(mbc55x_disk_r);
200		WRITE8_HANDLER(mbc55x_disk_w);
201		READ8_HANDLER(mbc55x_kb_usart_r);
202		WRITE8_HANDLER(mbc55x_kb_usart_w);
203	203
204	204	/* Floppy drive interface */
205	205

src/mess/includes/at.h

r14963	r14964
159	159
160	160	UINT8 m_channel_check;
161	161	UINT8 m_nmi_enabled;
	162	DECLARE_READ8_MEMBER(pc_dma_read_byte);
	163	DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
	164	DECLARE_READ8_MEMBER(pc_dma_read_word);
	165	DECLARE_WRITE8_MEMBER(pc_dma_write_word);
162	166	};
163	167
164	168

src/mess/includes/galeb.h

r14963	r14964
16	16	m_video_ram(*this, "video_ram"){ }
17	17
18	18	required_shared_ptr<UINT8> m_video_ram;
	19	DECLARE_READ8_MEMBER(galeb_keyboard_r);
19	20	};
20	21
21	22	/*----------- defined in video/galeb.c -----------*/

src/mess/includes/partner.h

r14963	r14964
19	19
20	20	UINT8 m_mem_page;
21	21	UINT8 m_win_mem_page;
	22	DECLARE_READ8_MEMBER(partner_floppy_r);
	23	DECLARE_WRITE8_MEMBER(partner_floppy_w);
	24	DECLARE_WRITE8_MEMBER(partner_win_memory_page_w);
	25	DECLARE_WRITE8_MEMBER(partner_mem_page_w);
22	26	};
23	27
24	28
r14963	r14964
31	35	extern const i8257_interface partner_dma;
32	36	extern const wd17xx_interface partner_wd17xx_interface;
33	37
34		extern WRITE8_HANDLER (partner_mem_page_w );
35		extern WRITE8_HANDLER (partner_win_memory_page_w);
36	38	#endif /* partner_H_ */

src/mess/includes/electron.h

r14963	r14964
62	62	int m_map4[256];
63	63	int m_map16[256];
64	64	emu_timer *m_scanline_timer;
	65	DECLARE_READ8_MEMBER(electron_read_keyboard);
	66	DECLARE_READ8_MEMBER(electron_jim_r);
	67	DECLARE_WRITE8_MEMBER(electron_jim_w);
	68	DECLARE_READ8_MEMBER(electron_1mhz_r);
	69	DECLARE_WRITE8_MEMBER(electron_1mhz_w);
	70	DECLARE_READ8_MEMBER(electron_ula_r);
	71	DECLARE_WRITE8_MEMBER(electron_ula_w);
	72	void electron_tape_start();
	73	void electron_tape_stop();
65	74	};
66	75
67	76
68	77	/*----------- defined in machine/electron.c -----------*/
69	78
70		READ8_HANDLER( electron_jim_r );
71		WRITE8_HANDLER( electron_jim_w );
72		READ8_HANDLER( electron_1mhz_r );
73		WRITE8_HANDLER( electron_1mhz_w );
74		READ8_HANDLER( electron_ula_r );
75		WRITE8_HANDLER( electron_ula_w );
76	79	MACHINE_START( electron );
77	80
78	81	void electron_interrupt_handler(running_machine &machine, int mode, int interrupt);

src/mess/includes/gp32.h

r14963	r14964
123	123	UINT32 m_s3c240x_spi_regs[0x18/4];
124	124	UINT32 m_s3c240x_mmc_regs[0x40/4];
125	125	bitmap_rgb32 m_bitmap;
	126	DECLARE_READ32_MEMBER(s3c240x_lcd_r);
	127	DECLARE_WRITE32_MEMBER(s3c240x_lcd_w);
	128	DECLARE_READ32_MEMBER(s3c240x_lcd_palette_r);
	129	DECLARE_WRITE32_MEMBER(s3c240x_lcd_palette_w);
	130	DECLARE_READ32_MEMBER(s3c240x_clkpow_r);
	131	DECLARE_WRITE32_MEMBER(s3c240x_clkpow_w);
	132	DECLARE_READ32_MEMBER(s3c240x_irq_r);
	133	DECLARE_WRITE32_MEMBER(s3c240x_irq_w);
	134	DECLARE_READ32_MEMBER(s3c240x_pwm_r);
	135	DECLARE_WRITE32_MEMBER(s3c240x_pwm_w);
	136	DECLARE_READ32_MEMBER(s3c240x_dma_r);
	137	DECLARE_WRITE32_MEMBER(s3c240x_dma_w);
	138	DECLARE_READ32_MEMBER(s3c240x_gpio_r);
	139	DECLARE_WRITE32_MEMBER(s3c240x_gpio_w);
	140	DECLARE_READ32_MEMBER(s3c240x_memcon_r);
	141	DECLARE_WRITE32_MEMBER(s3c240x_memcon_w);
	142	DECLARE_READ32_MEMBER(s3c240x_usb_host_r);
	143	DECLARE_WRITE32_MEMBER(s3c240x_usb_host_w);
	144	DECLARE_READ32_MEMBER(s3c240x_uart_0_r);
	145	DECLARE_WRITE32_MEMBER(s3c240x_uart_0_w);
	146	DECLARE_READ32_MEMBER(s3c240x_uart_1_r);
	147	DECLARE_WRITE32_MEMBER(s3c240x_uart_1_w);
	148	DECLARE_READ32_MEMBER(s3c240x_usb_device_r);
	149	DECLARE_WRITE32_MEMBER(s3c240x_usb_device_w);
	150	DECLARE_READ32_MEMBER(s3c240x_watchdog_r);
	151	DECLARE_WRITE32_MEMBER(s3c240x_watchdog_w);
	152	DECLARE_READ32_MEMBER(s3c240x_iic_r);
	153	DECLARE_WRITE32_MEMBER(s3c240x_iic_w);
	154	DECLARE_READ32_MEMBER(s3c240x_iis_r);
	155	DECLARE_WRITE32_MEMBER(s3c240x_iis_w);
	156	DECLARE_READ32_MEMBER(s3c240x_rtc_r);
	157	DECLARE_WRITE32_MEMBER(s3c240x_rtc_w);
	158	DECLARE_READ32_MEMBER(s3c240x_adc_r);
	159	DECLARE_WRITE32_MEMBER(s3c240x_adc_w);
	160	DECLARE_READ32_MEMBER(s3c240x_spi_r);
	161	DECLARE_WRITE32_MEMBER(s3c240x_spi_w);
	162	DECLARE_READ32_MEMBER(s3c240x_mmc_r);
	163	DECLARE_WRITE32_MEMBER(s3c240x_mmc_w);
126	164	};
127	165
128	166

src/mess/includes/irisha.h

r14963	r14964
18	18	int m_keyboard_mask;
19	19	UINT8 m_keypressed;
20	20	UINT8 m_keyboard_cnt;
	21	DECLARE_READ8_MEMBER(irisha_keyboard_r);
21	22	};
22	23
23	24
r14963	r14964
30	31	extern const struct pit8253_config irisha_pit8253_intf;
31	32	extern const struct pic8259_interface irisha_pic8259_config;
32	33
33		extern READ8_HANDLER (irisha_keyboard_r);
34	34
35	35
36	36	/*----------- defined in video/irisha.c -----------*/

src/mess/includes/apple1.h

r14963	r14964
41	41	terminal_t *m_current_terminal;
42	42	terminal_t *m_terminal;
43	43	int m_blink_on;
	44	DECLARE_READ8_MEMBER(apple1_cassette_r);
	45	DECLARE_WRITE8_MEMBER(apple1_cassette_w);
44	46	};
45	47
46	48
r14963	r14964
52	54	MACHINE_RESET( apple1 );
53	55	SNAPSHOT_LOAD( apple1 );
54	56
55		READ8_HANDLER( apple1_cassette_r );
56		WRITE8_HANDLER( apple1_cassette_w );
57	57
58	58
59	59	/*----------- defined in video/apple1.c -----------*/

src/mess/includes/orion.h

r14963	r14964
34	34	UINT8 m_orionpro_128_page;
35	35	UINT8 m_orionpro_rom2_segment;
36	36	UINT8 m_orionpro_dispatcher;
	37	DECLARE_READ8_MEMBER(orion128_system_r);
	38	DECLARE_WRITE8_MEMBER(orion128_system_w);
	39	DECLARE_READ8_MEMBER(orion128_romdisk_r);
	40	DECLARE_WRITE8_MEMBER(orion128_romdisk_w);
	41	DECLARE_WRITE8_MEMBER(orion128_video_mode_w);
	42	DECLARE_WRITE8_MEMBER(orion128_video_page_w);
	43	DECLARE_WRITE8_MEMBER(orion128_memory_page_w);
	44	DECLARE_WRITE8_MEMBER(orion_disk_control_w);
	45	DECLARE_READ8_MEMBER(orion128_floppy_r);
	46	DECLARE_WRITE8_MEMBER(orion128_floppy_w);
	47	DECLARE_READ8_MEMBER(orionz80_floppy_rtc_r);
	48	DECLARE_WRITE8_MEMBER(orionz80_floppy_rtc_w);
	49	DECLARE_WRITE8_MEMBER(orionz80_sound_w);
	50	DECLARE_WRITE8_MEMBER(orionz80_sound_fe_w);
	51	DECLARE_WRITE8_MEMBER(orionz80_memory_page_w);
	52	DECLARE_WRITE8_MEMBER(orionz80_dispatcher_w);
	53	DECLARE_READ8_MEMBER(orionz80_io_r);
	54	DECLARE_WRITE8_MEMBER(orionz80_io_w);
	55	DECLARE_WRITE8_MEMBER(orionpro_memory_page_w);
	56	DECLARE_READ8_MEMBER(orionpro_io_r);
	57	DECLARE_WRITE8_MEMBER(orionpro_io_w);
37	58	};
38	59
39	60
r14963	r14964
48	69	extern MACHINE_RESET( orionz80 );
49	70	extern INTERRUPT_GEN( orionz80_interrupt );
50	71
51		extern READ8_HANDLER ( orion128_system_r );
52		extern WRITE8_HANDLER ( orion128_system_w );
53		extern READ8_HANDLER ( orion128_romdisk_r );
54		extern WRITE8_HANDLER ( orion128_romdisk_w );
55		extern WRITE8_HANDLER ( orion128_video_mode_w );
56		extern WRITE8_HANDLER ( orion128_memory_page_w );
57		extern WRITE8_HANDLER ( orion128_video_page_w );
58		extern WRITE8_HANDLER ( orionz80_memory_page_w );
59		extern WRITE8_HANDLER ( orionz80_dispatcher_w );
60		extern WRITE8_HANDLER ( orionz80_sound_w );
61		extern READ8_HANDLER ( orion128_floppy_r );
62		extern WRITE8_HANDLER ( orion128_floppy_w );
63		extern READ8_HANDLER ( orionz80_io_r );
64		extern WRITE8_HANDLER ( orionz80_io_w );
65	72
66	73	extern MACHINE_RESET( orionpro );
67		extern READ8_HANDLER ( orionpro_io_r );
68		extern WRITE8_HANDLER ( orionpro_io_w );
69	74
70	75	/*----------- defined in video/orion.c -----------*/
71	76

src/mess/includes/hec2hrp.h

r14963	r14964
114	114	int m_hector_flag_result;
115	115	int m_print;
116	116	UINT8 m_hector_videoram_hrx[0x04000];
	117	DECLARE_READ8_MEMBER(hector_179x_register_r);
	118	DECLARE_WRITE8_MEMBER(hector_179x_register_w);
	119	DECLARE_WRITE8_MEMBER(hector_switch_bank_w);
	120	DECLARE_WRITE8_MEMBER(hector_keyboard_w);
	121	DECLARE_READ8_MEMBER(hector_keyboard_r);
	122	DECLARE_WRITE8_MEMBER(hector_sn_2000_w);
	123	DECLARE_WRITE8_MEMBER(hector_sn_2800_w);
	124	DECLARE_READ8_MEMBER(hector_cassette_r);
	125	DECLARE_WRITE8_MEMBER(hector_sn_3000_w);
	126	DECLARE_WRITE8_MEMBER(hector_color_a_w);
	127	DECLARE_WRITE8_MEMBER(hector_color_b_w);
	128	DECLARE_READ8_MEMBER(hector_io_8255_r);
	129	DECLARE_WRITE8_MEMBER(hector_io_8255_w);
	130	DECLARE_WRITE8_MEMBER(hector_mx40_io_port_w);
	131	DECLARE_WRITE8_MEMBER(hector_mx80_io_port_w);
117	132	};
118	133
119	134	/*----------- defined in machine/hec2hrp.c -----------*/
120	135
121	136	/* Protoype of memory Handler*/
122	137	WRITE8_HANDLER( hector_switch_bank_rom_w );
123		WRITE8_HANDLER( hector_switch_bank_w );
124		READ8_HANDLER( hector_keyboard_r );
125		WRITE8_HANDLER( hector_keyboard_w );
126		WRITE8_HANDLER( hector_sn_2000_w );
127		WRITE8_HANDLER( hector_sn_2800_w );
128		WRITE8_HANDLER( hector_sn_3000_w );
129		READ8_HANDLER( hector_cassette_r );
130		WRITE8_HANDLER( hector_color_a_w );
131		WRITE8_HANDLER( hector_color_b_w );
132	138
133	139	void hector_init( running_machine &machine);
134	140	void hector_reset(running_machine &machine, int hr, int with_D2);
r14963	r14964
136	142
137	143	/* Prototype of I/O Handler*/
138	144	READ8_HANDLER( hector_mx_io_port_r );
139		WRITE8_HANDLER( hector_mx80_io_port_w );
140		WRITE8_HANDLER( hector_mx40_io_port_w );
141		READ8_HANDLER( hector_io_8255_r);
142		WRITE8_HANDLER( hector_io_8255_w);
143		READ8_HANDLER( hector_179x_register_r);
144		WRITE8_HANDLER( hector_179x_register_w);
145	145	/*----------- defined in video/hec2video.c -----------*/
146	146
147	147	void hector_80c(running_machine &machine, bitmap_ind16 &bitmap, UINT8 *page, int ymax, int yram) ;

src/mess/includes/bk.h

r14963	r14964
22	22	UINT16 m_key_pressed;
23	23	UINT16 m_key_irq_vector;
24	24	UINT16 m_drive;
	25	DECLARE_READ16_MEMBER(bk_key_state_r);
	26	DECLARE_READ16_MEMBER(bk_key_code_r);
	27	DECLARE_READ16_MEMBER(bk_vid_scrool_r);
	28	DECLARE_READ16_MEMBER(bk_key_press_r);
	29	DECLARE_WRITE16_MEMBER(bk_key_state_w);
	30	DECLARE_WRITE16_MEMBER(bk_vid_scrool_w);
	31	DECLARE_WRITE16_MEMBER(bk_key_press_w);
	32	DECLARE_READ16_MEMBER(bk_floppy_cmd_r);
	33	DECLARE_WRITE16_MEMBER(bk_floppy_cmd_w);
	34	DECLARE_READ16_MEMBER(bk_floppy_data_r);
	35	DECLARE_WRITE16_MEMBER(bk_floppy_data_w);
25	36	};
26	37
27	38
r14963	r14964
30	41	extern MACHINE_START( bk0010 );
31	42	extern MACHINE_RESET( bk0010 );
32	43
33		extern READ16_HANDLER (bk_key_state_r);
34		extern WRITE16_HANDLER(bk_key_state_w);
35		extern READ16_HANDLER (bk_key_code_r);
36		extern READ16_HANDLER (bk_vid_scrool_r);
37		extern WRITE16_HANDLER(bk_vid_scrool_w);
38		extern READ16_HANDLER (bk_key_press_r);
39		extern WRITE16_HANDLER(bk_key_press_w);
40	44
41		extern READ16_HANDLER (bk_floppy_cmd_r);
42		extern WRITE16_HANDLER(bk_floppy_cmd_w);
43		extern READ16_HANDLER (bk_floppy_data_r);
44		extern WRITE16_HANDLER(bk_floppy_data_w);
45	45
46	46	/*----------- defined in video/bk.c -----------*/
47	47

src/mess/includes/a7800.h

r14963	r14964
53	53	int m_p2_one_button;
54	54
55	55	required_device<cpu_device> m_maincpu;
	56	DECLARE_WRITE8_MEMBER(a7800_RAM0_w);
	57	DECLARE_WRITE8_MEMBER(a7800_cart_w);
	58	DECLARE_READ8_MEMBER(a7800_TIA_r);
	59	DECLARE_WRITE8_MEMBER(a7800_TIA_w);
	60	DECLARE_READ8_MEMBER(a7800_MARIA_r);
	61	DECLARE_WRITE8_MEMBER(a7800_MARIA_w);
56	62	};
57	63
58	64
r14963	r14964
61	67	VIDEO_START( a7800 );
62	68	SCREEN_UPDATE_IND16( a7800 );
63	69	TIMER_DEVICE_CALLBACK( a7800_interrupt );
64		READ8_HANDLER( a7800_MARIA_r );
65		WRITE8_HANDLER( a7800_MARIA_w );
66	70
67	71
68	72	/*----------- defined in machine/a7800.c -----------*/
r14963	r14964
77	81	DEVICE_START( a7800_cart );
78	82	DEVICE_IMAGE_LOAD( a7800_cart );
79	83
80		READ8_HANDLER( a7800_TIA_r );
81		WRITE8_HANDLER( a7800_TIA_w );
82		WRITE8_HANDLER( a7800_RAM0_w );
83		WRITE8_HANDLER( a7800_cart_w );
84	84
85	85	DRIVER_INIT( a7800_ntsc );
86	86	DRIVER_INIT( a7800_pal );

src/mess/includes/nascom1.h

r14963	r14964
38	38	int m_tape_index;
39	39	nascom1_portstat_t m_portstat;
40	40	nascom2_fdc_t m_nascom2_fdc;
	41	DECLARE_READ8_MEMBER(nascom2_fdc_select_r);
	42	DECLARE_WRITE8_MEMBER(nascom2_fdc_select_w);
	43	DECLARE_READ8_MEMBER(nascom2_fdc_status_r);
	44	DECLARE_READ8_MEMBER(nascom1_port_00_r);
	45	DECLARE_WRITE8_MEMBER(nascom1_port_00_w);
	46	DECLARE_READ8_MEMBER(nascom1_port_01_r);
	47	DECLARE_WRITE8_MEMBER(nascom1_port_01_w);
	48	DECLARE_READ8_MEMBER(nascom1_port_02_r);
41	49	};
42	50
43	51
r14963	r14964
50	58	DEVICE_IMAGE_UNLOAD( nascom1_cassette );
51	59	SNAPSHOT_LOAD( nascom1 );
52	60
53		READ8_HANDLER( nascom2_fdc_select_r );
54		WRITE8_HANDLER( nascom2_fdc_select_w );
55		READ8_HANDLER( nascom2_fdc_status_r );
56	61
57		READ8_HANDLER( nascom1_port_00_r );
58		READ8_HANDLER( nascom1_port_01_r );
59		READ8_HANDLER( nascom1_port_02_r );
60		WRITE8_HANDLER( nascom1_port_00_w );
61		WRITE8_HANDLER( nascom1_port_01_w );
62	62
63	63	READ8_DEVICE_HANDLER( nascom1_hd6402_si );
64	64	WRITE8_DEVICE_HANDLER( nascom1_hd6402_so );

src/mess/includes/gmaster.h

r14963	r14964
25	25
26	26	GMASTER_VIDEO m_video;
27	27	GMASTER_MACHINE m_gmachine;
	28	DECLARE_READ8_MEMBER(gmaster_io_r);
	29	DECLARE_WRITE8_MEMBER(gmaster_io_w);
	30	DECLARE_READ8_MEMBER(gmaster_port_r);
	31	DECLARE_WRITE8_MEMBER(gmaster_port_w);
28	32	};
29	33
30	34

src/mess/includes/mtx.h

r14963	r14964
45	45
46	46	/* timers */
47	47	device_t *m_cassette_timer;
	48	DECLARE_WRITE8_MEMBER(mtx_bankswitch_w);
	49	DECLARE_WRITE8_MEMBER(mtx_sound_latch_w);
	50	DECLARE_WRITE8_MEMBER(mtx_sense_w);
	51	DECLARE_READ8_MEMBER(mtx_key_lo_r);
	52	DECLARE_READ8_MEMBER(mtx_key_hi_r);
	53	DECLARE_WRITE8_MEMBER(hrx_address_w);
	54	DECLARE_READ8_MEMBER(hrx_data_r);
	55	DECLARE_WRITE8_MEMBER(hrx_data_w);
	56	DECLARE_READ8_MEMBER(hrx_attr_r);
	57	DECLARE_WRITE8_MEMBER(hrx_attr_w);
48	58	};
49	59
50	60	/*----------- defined in machine/mtx.c -----------*/
r14963	r14964
53	63	MACHINE_RESET( mtx512 );
54	64	SNAPSHOT_LOAD( mtx );
55	65
56		WRITE8_HANDLER( mtx_bankswitch_w );
57	66
58	67	/* Sound */
59	68	READ8_DEVICE_HANDLER( mtx_sound_strobe_r );
60		WRITE8_HANDLER( mtx_sound_latch_w );
61	69
62	70	/* Cassette */
63	71	WRITE8_DEVICE_HANDLER( mtx_cst_w );
r14963	r14964
67	75	READ8_DEVICE_HANDLER( mtx_prt_r );
68	76
69	77	/* Keyboard */
70		WRITE8_HANDLER( mtx_sense_w );
71		READ8_HANDLER( mtx_key_lo_r );
72		READ8_HANDLER( mtx_key_hi_r );
73	78
74	79	/* HRX */
75		WRITE8_HANDLER( hrx_address_w );
76		READ8_HANDLER( hrx_data_r );
77		WRITE8_HANDLER( hrx_data_w );
78		READ8_HANDLER( hrx_attr_r );
79		WRITE8_HANDLER( hrx_attr_w );
80	80
81	81	#endif /* __MTX_H__ */

src/mess/includes/microtan.h

r14963	r14964
42	42	int m_repeat;
43	43	int m_repeater;
44	44	tilemap_t *m_bg_tilemap;
	45	DECLARE_READ8_MEMBER(microtan_sound_r);
	46	DECLARE_WRITE8_MEMBER(microtan_sound_w);
	47	DECLARE_READ8_MEMBER(microtan_bffx_r);
	48	DECLARE_WRITE8_MEMBER(microtan_bffx_w);
	49	DECLARE_WRITE8_MEMBER(microtan_videoram_w);
45	50	};
46	51
47	52
r14963	r14964
58	63
59	64	INTERRUPT_GEN( microtan_interrupt );
60	65
61		READ8_HANDLER ( microtan_bffx_r );
62		READ8_HANDLER ( microtan_sound_r );
63	66
64		WRITE8_HANDLER ( microtan_bffx_w );
65		WRITE8_HANDLER ( microtan_sound_w );
66	67
67
68	68	/*----------- defined in video/microtan.c -----------*/
69	69
70		extern WRITE8_HANDLER ( microtan_videoram_w );
71	70
72	71	extern VIDEO_START( microtan );
73	72	extern SCREEN_UPDATE_IND16( microtan );

src/mess/includes/sapi1.h

r14963	r14964
18	18	UINT8 m_keyboard_mask;
19	19	UINT8 m_refresh_counter;
20	20	UINT8 m_zps3_25;
	21	DECLARE_READ8_MEMBER(sapi1_keyboard_r);
	22	DECLARE_WRITE8_MEMBER(sapi1_keyboard_w);
	23	DECLARE_WRITE8_MEMBER(sapizps3_00_w);
	24	DECLARE_READ8_MEMBER(sapizps3_25_r);
	25	DECLARE_WRITE8_MEMBER(sapizps3_25_w);
21	26	};
22	27
23	28
r14963	r14964
29	34	extern MACHINE_RESET( sapi1 );
30	35	extern MACHINE_RESET( sapizps3 );
31	36
32		extern READ8_HANDLER (sapi1_keyboard_r );
33		extern WRITE8_HANDLER(sapi1_keyboard_w );
34	37
35	38	/*----------- defined in video/sapi1.c -----------*/
36	39

src/mess/includes/einstein.h

r14963	r14964
67	67	UINT8   m_de;
68	68
69	69	static const floppy_format_type floppy_formats[];
	70	DECLARE_WRITE8_MEMBER(einstein_80col_ram_w);
	71	DECLARE_READ8_MEMBER(einstein_80col_ram_r);
	72	DECLARE_READ8_MEMBER(einstein_80col_state_r);
	73	DECLARE_WRITE8_MEMBER(einstein_keyboard_line_write);
	74	DECLARE_READ8_MEMBER(einstein_keyboard_data_read);
	75	DECLARE_WRITE8_MEMBER(einstein_rom_w);
	76	DECLARE_READ8_MEMBER(einstein_kybintmsk_r);
	77	DECLARE_WRITE8_MEMBER(einstein_kybintmsk_w);
	78	DECLARE_WRITE8_MEMBER(einstein_adcintmsk_w);
	79	DECLARE_WRITE8_MEMBER(einstein_fire_int_w);
70	80	};
71	81
72	82

src/mess/includes/mikro80.h

r14963	r14964
21	21	required_shared_ptr<UINT8> m_video_ram;
22	22	int m_keyboard_mask;
23	23	int m_key_mask;
	24	DECLARE_READ8_MEMBER(mikro80_8255_portb_r);
	25	DECLARE_READ8_MEMBER(mikro80_8255_portc_r);
	26	DECLARE_WRITE8_MEMBER(mikro80_8255_porta_w);
	27	DECLARE_WRITE8_MEMBER(mikro80_8255_portc_w);
	28	DECLARE_READ8_MEMBER(mikro80_keyboard_r);
	29	DECLARE_WRITE8_MEMBER(mikro80_keyboard_w);
	30	DECLARE_WRITE8_MEMBER(mikro80_tape_w);
	31	DECLARE_READ8_MEMBER(mikro80_tape_r);
24	32	};
25	33
26	34
r14963	r14964
31	39	extern DRIVER_INIT( mikro80 );
32	40	extern DRIVER_INIT( radio99 );
33	41	extern MACHINE_RESET( mikro80 );
34		extern READ8_HANDLER( mikro80_keyboard_r );
35		extern WRITE8_HANDLER( mikro80_keyboard_w );
36		extern READ8_HANDLER( mikro80_tape_r );
37		extern WRITE8_HANDLER( mikro80_tape_w );
38	42
39		extern READ8_HANDLER (mikro80_8255_portb_r );
40		extern READ8_HANDLER (mikro80_8255_portc_r );
41		extern WRITE8_HANDLER (mikro80_8255_porta_w );
42		extern WRITE8_HANDLER (mikro80_8255_portc_w );
43	43	/*----------- defined in video/mikro80.c -----------*/
44	44
45	45	extern VIDEO_START( mikro80 );

src/mess/includes/amstrad.h

r14963	r14964
112	112	int m_printer_bit8_selected;
113	113	unsigned char m_Psg_FunctionSelected;
114	114	int m_previous_ppi_portc_w;
	115	DECLARE_WRITE8_MEMBER(amstrad_plus_asic_4000_w);
	116	DECLARE_WRITE8_MEMBER(amstrad_plus_asic_6000_w);
	117	DECLARE_READ8_MEMBER(amstrad_plus_asic_4000_r);
	118	DECLARE_READ8_MEMBER(amstrad_plus_asic_6000_r);
	119	DECLARE_WRITE8_MEMBER(aleste_msx_mapper);
	120	DECLARE_READ8_MEMBER(amstrad_cpc_io_r);
	121	DECLARE_WRITE8_MEMBER(amstrad_cpc_io_w);
	122	DECLARE_READ8_MEMBER(amstrad_psg_porta_read);
	123	void amstrad_plus_seqcheck(int data);
115	124	};
116	125
117	126
118	127	/*----------- defined in machine/amstrad.c -----------*/
119	128
120		READ8_HANDLER ( amstrad_cpc_io_r );
121		WRITE8_HANDLER ( amstrad_cpc_io_w );
122	129
123		WRITE8_HANDLER( amstrad_plus_asic_4000_w );
124		WRITE8_HANDLER( amstrad_plus_asic_6000_w );
125		READ8_HANDLER( amstrad_plus_asic_4000_r );
126		READ8_HANDLER( amstrad_plus_asic_6000_r );
127	130
128	131	READ8_DEVICE_HANDLER( amstrad_ppi_porta_r );
129	132	READ8_DEVICE_HANDLER( amstrad_ppi_portb_r );
130	133	WRITE8_DEVICE_HANDLER( amstrad_ppi_porta_w );
131	134	WRITE8_DEVICE_HANDLER( amstrad_ppi_portc_w );
132	135
133		READ8_HANDLER ( amstrad_psg_porta_read );
134	136
135	137	WRITE_LINE_DEVICE_HANDLER( aleste_interrupt );
136	138	WRITE_LINE_DEVICE_HANDLER( cpc_irq_w );

src/mess/includes/rmnimbus.h

r14963	r14964
196	196	UINT16 m_pixel_mask;
197	197	UINT8 m_hs_count;
198	198	UINT32 m_debug_video;
	199	DECLARE_READ16_MEMBER(nimbus_i186_internal_port_r);
	200	DECLARE_WRITE16_MEMBER(nimbus_i186_internal_port_w);
	201	DECLARE_READ8_MEMBER(nimbus_mcu_r);
	202	DECLARE_WRITE8_MEMBER(nimbus_mcu_w);
	203	DECLARE_READ16_MEMBER(nimbus_io_r);
	204	DECLARE_WRITE16_MEMBER(nimbus_io_w);
	205	DECLARE_READ8_MEMBER(nimbus_disk_r);
	206	DECLARE_WRITE8_MEMBER(nimbus_disk_w);
	207	DECLARE_READ8_MEMBER(nimbus_pc8031_r);
	208	DECLARE_WRITE8_MEMBER(nimbus_pc8031_w);
	209	DECLARE_READ8_MEMBER(nimbus_pc8031_iou_r);
	210	DECLARE_WRITE8_MEMBER(nimbus_pc8031_iou_w);
	211	DECLARE_READ8_MEMBER(nimbus_pc8031_port_r);
	212	DECLARE_WRITE8_MEMBER(nimbus_pc8031_port_w);
	213	DECLARE_READ8_MEMBER(nimbus_iou_r);
	214	DECLARE_WRITE8_MEMBER(nimbus_iou_w);
	215	DECLARE_READ8_MEMBER(nimbus_sound_ay8910_r);
	216	DECLARE_WRITE8_MEMBER(nimbus_sound_ay8910_w);
	217	DECLARE_WRITE8_MEMBER(nimbus_sound_ay8910_porta_w);
	218	DECLARE_WRITE8_MEMBER(nimbus_sound_ay8910_portb_w);
	219	DECLARE_READ8_MEMBER(nimbus_mouse_js_r);
	220	DECLARE_WRITE8_MEMBER(nimbus_mouse_js_w);
	221	DECLARE_READ16_MEMBER(nimbus_video_io_r);
	222	DECLARE_WRITE16_MEMBER(nimbus_video_io_w);
199	223	};
200	224
201	225
r14963	r14964
211	235	MACHINE_START(nimbus);
212	236
213	237	/* 80186 Internal */
214		READ16_HANDLER (nimbus_i186_internal_port_r);
215		WRITE16_HANDLER (nimbus_i186_internal_port_w);
216	238
217	239	/* external int priority masks */
218	240
r14963	r14964
246	268	#define BYTE_WORD               0x0001
247	269
248	270	/* Nimbus specific */
249		READ16_HANDLER (nimbus_io_r);
250		WRITE16_HANDLER (nimbus_io_w);
251	271
252	272	/* External int vectors for chained interupts */
253	273	#define EXTERNAL_INT_DISK       0x80
r14963	r14964
275	295	#define HIBLOCK_BASE_MASK   0x08
276	296	#define HIBLOCK_SELECT_MASK 0x10
277	297
278		READ8_HANDLER( nimbus_mcu_r );
279		WRITE8_HANDLER( nimbus_mcu_w );
280	298
281	299
282	300	/* Z80 SIO for keyboard */
r14963	r14964
292	310
293	311	extern const wd17xx_interface nimbus_wd17xx_interface;
294	312
295		READ8_HANDLER( nimbus_disk_r );
296		WRITE8_HANDLER( nimbus_disk_w );
297	313
298	314	#define NO_DRIVE_SELECTED   0xFF
299	315
r14963	r14964
362	378	#define IPC_IN_BYTE_AVAIL   0X02
363	379	#define IPC_IN_READ_PEND    0X04
364	380
365		READ8_HANDLER( nimbus_pc8031_r );
366		WRITE8_HANDLER( nimbus_pc8031_w );
367	381
368		READ8_HANDLER( nimbus_pc8031_iou_r );
369		WRITE8_HANDLER( nimbus_pc8031_iou_w );
370	382
371		READ8_HANDLER( nimbus_pc8031_port_r );
372		WRITE8_HANDLER( nimbus_pc8031_port_w );
373	383
374	384	#define ER59256_TAG             "er59256"
375	385
r14963	r14964
380	390	#define MOUSE_INT_ENABLE        0x08
381	391	#define PC8031_INT_ENABLE       0x10
382	392
383		READ8_HANDLER( nimbus_iou_r );
384		WRITE8_HANDLER( nimbus_iou_w );
385	393
386	394	/* Sound hardware */
387	395
388	396	#define AY8910_TAG              "ay8910"
389	397	#define MONO_TAG                "mono"
390	398
391		READ8_HANDLER( nimbus_sound_ay8910_r );
392		WRITE8_HANDLER( nimbus_sound_ay8910_w );
393	399
394		WRITE8_HANDLER( nimbus_sound_ay8910_porta_w );
395		WRITE8_HANDLER( nimbus_sound_ay8910_portb_w );
396	400
397	401
398	402	#define MSM5205_TAG             "msm5205"
r14963	r14964
413	417	MOUSE_PHASE_NEGATIVE
414	418	};
415	419
416		READ8_HANDLER( nimbus_mouse_js_r );
417		WRITE8_HANDLER( nimbus_mouse_js_w );
418	420
419	421	#define MOUSE_INT_ENABLED(state)     (((state)->m_iou_reg092 & MOUSE_INT_ENABLE) ? 1 : 0)
420	422
r14963	r14964
432	434
433	435	/*----------- defined in video/rmnimbus.c -----------*/
434	436
435		READ16_HANDLER (nimbus_video_io_r);
436		WRITE16_HANDLER (nimbus_video_io_w);
437	437
438	438	VIDEO_START( nimbus );
439	439	SCREEN_VBLANK( nimbus );

src/mess/includes/sms.h

r14963	r14964
130	130	bool m_93c46_enabled;
131	131	UINT8 m_93c46_lines;
132	132	} m_cartridge[MAX_CARTRIDGES];
	133	DECLARE_WRITE8_MEMBER(sms_input_write);
	134	DECLARE_WRITE8_MEMBER(sms_fm_detect_w);
	135	DECLARE_READ8_MEMBER(sms_fm_detect_r);
	136	DECLARE_WRITE8_MEMBER(sms_io_control_w);
	137	DECLARE_READ8_MEMBER(sms_count_r);
	138	DECLARE_READ8_MEMBER(sms_input_port_0_r);
	139	DECLARE_READ8_MEMBER(sms_input_port_1_r);
	140	DECLARE_WRITE8_MEMBER(sms_ym2413_register_port_0_w);
	141	DECLARE_WRITE8_MEMBER(sms_ym2413_data_port_0_w);
	142	DECLARE_READ8_MEMBER(gg_input_port_2_r);
	143	DECLARE_READ8_MEMBER(sms_sscope_r);
	144	DECLARE_WRITE8_MEMBER(sms_sscope_w);
	145	DECLARE_READ8_MEMBER(sms_mapper_r);
	146	DECLARE_WRITE8_MEMBER(sms_tvdraw_axis_w);
	147	DECLARE_READ8_MEMBER(sms_tvdraw_status_r);
	148	DECLARE_READ8_MEMBER(sms_tvdraw_data_r);
	149	DECLARE_WRITE8_MEMBER(sms_93c46_w);
	150	DECLARE_READ8_MEMBER(sms_93c46_r);
	151	DECLARE_WRITE8_MEMBER(sms_mapper_w);
	152	DECLARE_WRITE8_MEMBER(sms_korean_zemina_banksw_w);
	153	DECLARE_WRITE8_MEMBER(sms_codemasters_page0_w);
	154	DECLARE_WRITE8_MEMBER(sms_codemasters_page1_w);
	155	DECLARE_WRITE8_MEMBER(sms_4pak_page0_w);
	156	DECLARE_WRITE8_MEMBER(sms_4pak_page1_w);
	157	DECLARE_WRITE8_MEMBER(sms_4pak_page2_w);
	158	DECLARE_WRITE8_MEMBER(sms_janggun_bank0_w);
	159	DECLARE_WRITE8_MEMBER(sms_janggun_bank1_w);
	160	DECLARE_WRITE8_MEMBER(sms_janggun_bank2_w);
	161	DECLARE_WRITE8_MEMBER(sms_janggun_bank3_w);
	162	DECLARE_WRITE8_MEMBER(sms_bios_w);
	163	DECLARE_WRITE8_MEMBER(sms_cartram2_w);
	164	DECLARE_WRITE8_MEMBER(sms_cartram_w);
	165	DECLARE_WRITE8_MEMBER(gg_sio_w);
	166	DECLARE_READ8_MEMBER(gg_sio_r);
	167	DECLARE_READ8_MEMBER(sms_store_cart_select_r);
	168	DECLARE_WRITE8_MEMBER(sms_store_cart_select_w);
	169	DECLARE_READ8_MEMBER(sms_store_select1);
	170	DECLARE_READ8_MEMBER(sms_store_select2);
	171	DECLARE_READ8_MEMBER(sms_store_control_r);
	172	DECLARE_WRITE8_MEMBER(sms_store_control_w);
133	173	};
134	174
135	175
136	176	/*----------- defined in machine/sms.c -----------*/
137	177
138	178	/* Function prototypes */
139		WRITE8_HANDLER( sms_cartram_w );
140		WRITE8_HANDLER( sms_cartram2_w );
141		WRITE8_HANDLER( sms_fm_detect_w );
142		READ8_HANDLER( sms_fm_detect_r );
143		READ8_HANDLER( sms_input_port_0_r );
144		READ8_HANDLER( sms_input_port_1_r );
145		WRITE8_HANDLER( sms_ym2413_register_port_0_w );
146		WRITE8_HANDLER( sms_ym2413_data_port_0_w );
147		WRITE8_HANDLER( sms_io_control_w );
148		READ8_HANDLER( sms_count_r );
149		WRITE8_HANDLER( sms_sscope_w );
150		READ8_HANDLER( sms_sscope_r );
151		WRITE8_HANDLER( sms_mapper_w );
152		READ8_HANDLER( sms_mapper_r );
153		WRITE8_HANDLER( sms_bios_w );
154		WRITE8_HANDLER( gg_sio_w );
155		READ8_HANDLER( gg_sio_r );
156		READ8_HANDLER( gg_input_port_2_r );
157	179
158	180	INPUT_CHANGED( lgun1_changed );
159	181	INPUT_CHANGED( lgun2_changed );
r14963	r14964
167	189	MACHINE_START( sms );
168	190	MACHINE_RESET( sms );
169	191
170		READ8_HANDLER( sms_store_cart_select_r );
171		WRITE8_HANDLER( sms_store_cart_select_w );
172		READ8_HANDLER( sms_store_select1 );
173		READ8_HANDLER( sms_store_select2 );
174		READ8_HANDLER( sms_store_control_r );
175		WRITE8_HANDLER( sms_store_control_w );
176	192
177	193	#define IO_EXPANSION    (0x80)   /* Expansion slot enable (1= disabled, 0= enabled) */
178	194	#define IO_CARTRIDGE    (0x40)   /* Cartridge slot enable (1= disabled, 0= enabled) */

src/mess/includes/poly88.h

r14963	r14964
27	27	int m_previous_level;
28	28	int m_clk_level;
29	29	int m_clk_level_tape;
	30	DECLARE_WRITE8_MEMBER(poly88_baud_rate_w);
	31	DECLARE_READ8_MEMBER(poly88_keyboard_r);
	32	DECLARE_WRITE8_MEMBER(poly88_intr_w);
30	33	};
31	34
32	35
r14963	r14964
35	38	DRIVER_INIT(poly88);
36	39	MACHINE_RESET(poly88);
37	40	INTERRUPT_GEN( poly88_interrupt );
38		READ8_HANDLER(poly88_keyboard_r);
39		WRITE8_HANDLER(poly88_intr_w);
40		WRITE8_HANDLER(poly88_baud_rate_w);
41	41
42	42	extern const i8251_interface poly88_usart_interface;
43	43

src/mess/includes/llc.h

r14963	r14964
20	20	optional_shared_ptr<UINT8> m_video_ram;
21	21	UINT8 m_s_code;
22	22	UINT8 m_llc1_key_state;
	23	DECLARE_WRITE8_MEMBER(llc2_rom_disable_w);
	24	DECLARE_WRITE8_MEMBER(llc2_basic_enable_w);
23	25	};
24	26
25	27
r14963	r14964
36	38
37	39	extern DRIVER_INIT( llc2 );
38	40	extern MACHINE_RESET( llc2 );
39		extern WRITE8_HANDLER(llc2_rom_disable_w);
40		extern WRITE8_HANDLER(llc2_basic_enable_w);
41	41
42	42	/*----------- defined in video/llc.c -----------*/
43	43

src/mess/includes/samcoupe.h

r14963	r14964
61	61	UINT8 m_mouse_data[9];
62	62	int m_mouse_x, m_mouse_y;
63	63	UINT8 *m_videoram;
	64	DECLARE_WRITE8_MEMBER(samcoupe_ext_mem_w);
	65	DECLARE_READ8_MEMBER(samcoupe_disk_r);
	66	DECLARE_WRITE8_MEMBER(samcoupe_disk_w);
	67	DECLARE_READ8_MEMBER(samcoupe_pen_r);
	68	DECLARE_WRITE8_MEMBER(samcoupe_clut_w);
	69	DECLARE_READ8_MEMBER(samcoupe_status_r);
	70	DECLARE_WRITE8_MEMBER(samcoupe_line_int_w);
	71	DECLARE_READ8_MEMBER(samcoupe_lmpr_r);
	72	DECLARE_WRITE8_MEMBER(samcoupe_lmpr_w);
	73	DECLARE_READ8_MEMBER(samcoupe_hmpr_r);
	74	DECLARE_WRITE8_MEMBER(samcoupe_hmpr_w);
	75	DECLARE_READ8_MEMBER(samcoupe_vmpr_r);
	76	DECLARE_WRITE8_MEMBER(samcoupe_vmpr_w);
	77	DECLARE_READ8_MEMBER(samcoupe_midi_r);
	78	DECLARE_WRITE8_MEMBER(samcoupe_midi_w);
	79	DECLARE_READ8_MEMBER(samcoupe_keyboard_r);
	80	DECLARE_WRITE8_MEMBER(samcoupe_border_w);
	81	DECLARE_READ8_MEMBER(samcoupe_attributes_r);
64	82	};
65	83
66	84
r14963	r14964
74	92	void samcoupe_update_memory(address_space *space);
75	93	UINT8 samcoupe_mouse_r(running_machine &machine);
76	94
77		WRITE8_HANDLER( samcoupe_ext_mem_w );
78	95	MACHINE_START( samcoupe );
79	96	MACHINE_RESET( samcoupe );
80	97

src/mess/includes/pp01.h

r14963	r14964
20	20	UINT8 m_memory_block[16];
21	21	UINT8 m_video_write_mode;
22	22	UINT8 m_key_line;
	23	DECLARE_WRITE8_MEMBER(pp01_video_write_mode_w);
	24	DECLARE_WRITE8_MEMBER(pp01_video_r_1_w);
	25	DECLARE_WRITE8_MEMBER(pp01_video_g_1_w);
	26	DECLARE_WRITE8_MEMBER(pp01_video_b_1_w);
	27	DECLARE_WRITE8_MEMBER(pp01_video_r_2_w);
	28	DECLARE_WRITE8_MEMBER(pp01_video_g_2_w);
	29	DECLARE_WRITE8_MEMBER(pp01_video_b_2_w);
	30	DECLARE_WRITE8_MEMBER(pp01_mem_block_w);
	31	DECLARE_READ8_MEMBER(pp01_mem_block_r);
23	32	};
24	33
25	34
r14963	r14964
28	37	extern const i8255_interface pp01_ppi8255_interface;
29	38	extern MACHINE_START( pp01 );
30	39	extern MACHINE_RESET( pp01 );
31		extern WRITE8_HANDLER (pp01_mem_block_w);
32		extern READ8_HANDLER  (pp01_mem_block_r);
33		extern WRITE8_HANDLER (pp01_video_write_mode_w);
34	40	/*----------- defined in video/pp01.c -----------*/
35	41
36	42	extern VIDEO_START( pp01 );

src/mess/includes/odyssey2.h

r14963	r14964
95	95	sound_stream *m_sh_channel;
96	96	UINT16 m_sh_count;
97	97	//ef9341_t ef9341;
	98	DECLARE_READ8_MEMBER(odyssey2_t0_r);
	99	DECLARE_READ8_MEMBER(odyssey2_bus_r);
	100	DECLARE_WRITE8_MEMBER(odyssey2_bus_w);
	101	DECLARE_READ8_MEMBER(g7400_bus_r);
	102	DECLARE_WRITE8_MEMBER(g7400_bus_w);
	103	DECLARE_READ8_MEMBER(odyssey2_getp1);
	104	DECLARE_WRITE8_MEMBER(odyssey2_putp1);
	105	DECLARE_READ8_MEMBER(odyssey2_getp2);
	106	DECLARE_WRITE8_MEMBER(odyssey2_putp2);
	107	DECLARE_READ8_MEMBER(odyssey2_getbus);
	108	DECLARE_WRITE8_MEMBER(odyssey2_putbus);
	109	DECLARE_READ8_MEMBER(odyssey2_video_r);
	110	DECLARE_WRITE8_MEMBER(odyssey2_video_w);
	111	DECLARE_WRITE8_MEMBER(odyssey2_lum_w);
	112	DECLARE_READ8_MEMBER(odyssey2_t1_r);
98	113	};
99	114
100	115
r14963	r14964
105	120	VIDEO_START( odyssey2 );
106	121	SCREEN_UPDATE_IND16( odyssey2 );
107	122	PALETTE_INIT( odyssey2 );
108		READ8_HANDLER ( odyssey2_t1_r );
109		READ8_HANDLER ( odyssey2_video_r );
110		WRITE8_HANDLER ( odyssey2_video_w );
111		WRITE8_HANDLER ( odyssey2_lum_w );
112	123
113	124	STREAM_UPDATE( odyssey2_sh_update );
114	125
r14963	r14964
123	134	MACHINE_RESET( odyssey2 );
124	135
125	136	/* i/o ports */
126		READ8_HANDLER ( odyssey2_bus_r );
127		WRITE8_HANDLER ( odyssey2_bus_w );
128	137
129		READ8_HANDLER( odyssey2_getp1 );
130		WRITE8_HANDLER ( odyssey2_putp1 );
131	138
132		READ8_HANDLER( odyssey2_getp2 );
133		WRITE8_HANDLER ( odyssey2_putp2 );
134	139
135		READ8_HANDLER( odyssey2_getbus );
136		WRITE8_HANDLER ( odyssey2_putbus );
137	140
138		READ8_HANDLER( odyssey2_t0_r );
139	141	void odyssey2_the_voice_lrq_callback( device_t *device, int state );
140	142
141		READ8_HANDLER ( g7400_bus_r );
142		WRITE8_HANDLER ( g7400_bus_w );
143	143
144	144	int odyssey2_cart_verify(const UINT8 *cartdata, size_t size);
145	145

src/mess/includes/primo.h

r14963	r14964
23	23	UINT16 m_video_memory_base;
24	24	UINT8 m_port_FD;
25	25	int m_nmi;
	26	DECLARE_READ8_MEMBER(primo_be_1_r);
	27	DECLARE_READ8_MEMBER(primo_be_2_r);
	28	DECLARE_WRITE8_MEMBER(primo_ki_1_w);
	29	DECLARE_WRITE8_MEMBER(primo_ki_2_w);
	30	DECLARE_WRITE8_MEMBER(primo_FD_w);
26	31	};
27	32
28	33
29	34	/*----------- defined in machine/primo.c -----------*/
30	35
31		extern READ8_HANDLER ( primo_be_1_r );
32		extern READ8_HANDLER ( primo_be_2_r );
33		extern WRITE8_HANDLER ( primo_ki_1_w );
34		extern WRITE8_HANDLER ( primo_ki_2_w );
35		extern WRITE8_HANDLER ( primo_FD_w );
36	36	extern DRIVER_INIT ( primo32 );
37	37	extern DRIVER_INIT ( primo48 );
38	38	extern DRIVER_INIT ( primo64 );

src/mess/includes/ti85.h

r14963	r14964
57	57	int m_ti_number_of_frames;
58	58	UINT8 * m_frames;
59	59	UINT8 * m_bios;
	60	DECLARE_READ8_MEMBER(ti85_port_0000_r);
	61	DECLARE_READ8_MEMBER(ti8x_keypad_r);
	62	DECLARE_READ8_MEMBER(ti85_port_0006_r);
	63	DECLARE_READ8_MEMBER(ti8x_serial_r);
	64	DECLARE_READ8_MEMBER(ti86_port_0005_r);
	65	DECLARE_READ8_MEMBER(ti83_port_0000_r);
	66	DECLARE_READ8_MEMBER(ti8x_plus_serial_r);
	67	DECLARE_WRITE8_MEMBER(ti81_port_0007_w);
	68	DECLARE_WRITE8_MEMBER(ti85_port_0000_w);
	69	DECLARE_WRITE8_MEMBER(ti8x_keypad_w);
	70	DECLARE_WRITE8_MEMBER(ti85_port_0002_w);
	71	DECLARE_WRITE8_MEMBER(ti85_port_0003_w);
	72	DECLARE_WRITE8_MEMBER(ti85_port_0004_w);
	73	DECLARE_WRITE8_MEMBER(ti85_port_0005_w);
	74	DECLARE_WRITE8_MEMBER(ti85_port_0006_w);
	75	DECLARE_WRITE8_MEMBER(ti8x_serial_w);
	76	DECLARE_WRITE8_MEMBER(ti86_port_0005_w);
	77	DECLARE_WRITE8_MEMBER(ti86_port_0006_w);
	78	DECLARE_WRITE8_MEMBER(ti82_port_0002_w);
	79	DECLARE_WRITE8_MEMBER(ti83_port_0000_w);
	80	DECLARE_WRITE8_MEMBER(ti83_port_0002_w);
	81	DECLARE_WRITE8_MEMBER(ti83_port_0003_w);
	82	DECLARE_WRITE8_MEMBER(ti8x_plus_serial_w);
	83	DECLARE_WRITE8_MEMBER(ti83p_port_0002_w);
	84	DECLARE_WRITE8_MEMBER(ti83p_port_0003_w);
	85	DECLARE_WRITE8_MEMBER(ti83p_port_0004_w);
	86	DECLARE_WRITE8_MEMBER(ti83p_port_0006_w);
	87	DECLARE_WRITE8_MEMBER(ti83p_port_0007_w);
	88	DECLARE_READ8_MEMBER( ti85_port_0002_r );
	89	DECLARE_READ8_MEMBER( ti85_port_0003_r );
	90	DECLARE_READ8_MEMBER( ti85_port_0004_r );
	91	DECLARE_READ8_MEMBER( ti85_port_0005_r );
	92	DECLARE_READ8_MEMBER( ti86_port_0006_r );
	93	DECLARE_READ8_MEMBER( ti82_port_0002_r );
	94	DECLARE_READ8_MEMBER( ti83_port_0002_r );
	95	DECLARE_READ8_MEMBER( ti83_port_0003_r );
	96	DECLARE_READ8_MEMBER( ti83p_port_0002_r );
60	97	};
61	98
62	99
r14963	r14964
72	109
73	110	SNAPSHOT_LOAD( ti8x );
74	111
75		WRITE8_HANDLER( ti81_port_0007_w );
76		READ8_HANDLER( ti85_port_0000_r );
77		READ8_HANDLER( ti8x_keypad_r );
78		READ8_HANDLER( ti85_port_0002_r );
79		READ8_HANDLER( ti85_port_0003_r );
80		READ8_HANDLER( ti85_port_0004_r );
81		READ8_HANDLER( ti85_port_0005_r );
82		READ8_HANDLER( ti85_port_0006_r );
83		READ8_HANDLER( ti8x_serial_r );
84		READ8_HANDLER( ti86_port_0005_r );
85		READ8_HANDLER( ti86_port_0006_r );
86		READ8_HANDLER( ti82_port_0002_r );
87		READ8_HANDLER( ti83_port_0000_r );
88		READ8_HANDLER( ti83_port_0002_r );
89		READ8_HANDLER( ti83_port_0003_r );
90		READ8_HANDLER( ti8x_plus_serial_r );
91		READ8_HANDLER( ti83p_port_0002_r );
92		WRITE8_HANDLER( ti85_port_0000_w );
93		WRITE8_HANDLER( ti8x_keypad_w );
94		WRITE8_HANDLER( ti85_port_0002_w );
95		WRITE8_HANDLER( ti85_port_0003_w );
96		WRITE8_HANDLER( ti85_port_0004_w );
97		WRITE8_HANDLER( ti85_port_0005_w );
98		WRITE8_HANDLER( ti85_port_0006_w );
99		WRITE8_HANDLER( ti8x_serial_w );
100		WRITE8_HANDLER( ti86_port_0005_w );
101		WRITE8_HANDLER( ti86_port_0006_w );
102		WRITE8_HANDLER( ti82_port_0002_w );
103		WRITE8_HANDLER( ti83_port_0000_w );
104		WRITE8_HANDLER( ti83_port_0002_w );
105		WRITE8_HANDLER( ti83_port_0003_w );
106		WRITE8_HANDLER( ti8x_plus_serial_w );
107		WRITE8_HANDLER( ti83p_port_0002_w );
108		WRITE8_HANDLER( ti83p_port_0003_w );
109		WRITE8_HANDLER( ti83p_port_0004_w );
110		WRITE8_HANDLER( ti83p_port_0006_w );
111		WRITE8_HANDLER( ti83p_port_0007_w );
112	112
113	113	/*----------- defined in video/ti85.c -----------*/
114	114

src/mess/includes/svision.h

r14963	r14964
43	43	svision_t m_svision;
44	44	svision_pet_t m_pet;
45	45	tvlink_t m_tvlink;
	46	DECLARE_READ8_MEMBER(svision_r);
	47	DECLARE_WRITE8_MEMBER(svision_w);
	48	DECLARE_READ8_MEMBER(tvlink_r);
	49	DECLARE_WRITE8_MEMBER(tvlink_w);
46	50	};
47	51
48	52

src/mess/includes/svi318.h

r14963	r14964
56	56	UINT8 *m_pcart;
57	57	UINT32 m_pcart_rom_size;
58	58	SVI318_FDC_STRUCT m_fdc;
	59	DECLARE_WRITE8_MEMBER(svi318_ppi_w);
	60	DECLARE_READ8_MEMBER(svi318_psg_port_a_r);
	61	DECLARE_WRITE8_MEMBER(svi318_psg_port_b_w);
	62	DECLARE_WRITE8_MEMBER(svi318_fdc_drive_motor_w);
	63	DECLARE_WRITE8_MEMBER(svi318_fdc_density_side_w);
	64	DECLARE_READ8_MEMBER(svi318_fdc_irqdrq_r);
	65	DECLARE_WRITE8_MEMBER(svi806_ram_enable_w);
	66	DECLARE_WRITE8_MEMBER(svi318_writemem1);
	67	DECLARE_WRITE8_MEMBER(svi318_writemem2);
	68	DECLARE_WRITE8_MEMBER(svi318_writemem3);
	69	DECLARE_WRITE8_MEMBER(svi318_writemem4);
	70	DECLARE_READ8_MEMBER(svi318_io_ext_r);
	71	DECLARE_WRITE8_MEMBER(svi318_io_ext_w);
59	72	};
60	73
61	74
r14963	r14964
74	87	DEVICE_IMAGE_LOAD( svi318_cart );
75	88	DEVICE_IMAGE_UNLOAD( svi318_cart );
76	89
77		WRITE8_HANDLER( svi318_writemem1 );
78		WRITE8_HANDLER( svi318_writemem2 );
79		WRITE8_HANDLER( svi318_writemem3 );
80		WRITE8_HANDLER( svi318_writemem4 );
81	90
82		READ8_HANDLER( svi318_io_ext_r );
83		WRITE8_HANDLER( svi318_io_ext_w );
84	91
85		WRITE8_HANDLER( svi318_ppi_w );
86		WRITE8_HANDLER( svi318_psg_port_b_w );
87		READ8_HANDLER( svi318_psg_port_a_r );
88	92
89	93	int svi318_cassette_present(running_machine &machine, int id);
90	94

src/mess/includes/busicom.h

r14963	r14964
20	20	UINT8 m_timer;
21	21	UINT8 m_printer_line[11][17];
22	22	UINT8 m_printer_line_color[11];
	23	DECLARE_READ8_MEMBER(keyboard_r);
	24	DECLARE_READ8_MEMBER(printer_r);
	25	DECLARE_WRITE8_MEMBER(shifter_w);
	26	DECLARE_WRITE8_MEMBER(printer_w);
	27	DECLARE_WRITE8_MEMBER(status_w);
	28	DECLARE_WRITE8_MEMBER(printer_ctrl_w);
23	29	};
24	30
25	31

src/mess/includes/pc.h

r14963	r14964
41	41	UINT8               m_ppi_data_signal;
42	42	UINT8               m_ppi_shift_register;
43	43	UINT8               m_ppi_shift_enable;
	44	DECLARE_READ8_MEMBER(pc_page_r);
	45	DECLARE_WRITE8_MEMBER(pc_page_w);
	46	DECLARE_READ8_MEMBER(pc_dma_read_byte);
	47	DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
	48	DECLARE_WRITE8_MEMBER(pc_nmi_enable_w);
	49	DECLARE_READ8_MEMBER(pcjr_nmi_enable_r);
	50	DECLARE_WRITE8_MEMBER(ibm5150_kb_set_clock_signal);
	51	DECLARE_WRITE8_MEMBER(ibm5150_kb_set_data_signal);
	52	DECLARE_READ8_MEMBER(input_port_0_r);
	53	DECLARE_READ8_MEMBER(pc_rtc_r);
	54	DECLARE_WRITE8_MEMBER(pc_rtc_w);
	55	DECLARE_WRITE8_MEMBER(pc_EXP_w);
	56	DECLARE_READ8_MEMBER(pc_EXP_r);
	57	DECLARE_READ8_MEMBER(unk_r);
44	58	};
45	59
46	60	/*----------- defined in machine/pc.c -----------*/
r14963	r14964
63	77
64	78	void mess_init_pc_common( running_machine &machine, UINT32 flags, void (*set_keyb_int_func)(running_machine &, int), void (*set_hdc_int_func)(running_machine &,int,int));
65	79
66		WRITE8_HANDLER( pc_nmi_enable_w );
67		READ8_HANDLER( pcjr_nmi_enable_r );
68	80
69		READ8_HANDLER( pc_page_r );
70		WRITE8_HANDLER( pc_page_w );
71	81
72		WRITE8_HANDLER( ibm5150_kb_set_clock_signal );
73		WRITE8_HANDLER( ibm5150_kb_set_data_signal );
74	82
75	83	DRIVER_INIT( ibm5150 );
76	84	DRIVER_INIT( pccga );
r14963	r14964
97	105	TIMER_DEVICE_CALLBACK( pcjr_frame_interrupt );
98	106
99	107
100		READ8_HANDLER( pc_rtc_r );
101		WRITE8_HANDLER( pc_rtc_w );
102	108
103		READ16_HANDLER( pc16le_rtc_r );
104		WRITE16_HANDLER( pc16le_rtc_w );
105	109
106	110	void pc_rtc_init(running_machine &machine);
107	111
108		READ8_HANDLER ( pc_EXP_r );
109		WRITE8_HANDLER ( pc_EXP_w );
110	112
111	113	#endif /* PC_H_ */

src/mess/includes/pecom.h

r14963	r14964
29	29	/* timers */
30	30	emu_timer *m_reset_timer;   /* power on reset timer */
31	31
	32	DECLARE_READ8_MEMBER(pecom_cdp1869_charram_r);
	33	DECLARE_WRITE8_MEMBER(pecom_cdp1869_charram_w);
	34	DECLARE_READ8_MEMBER(pecom_cdp1869_pageram_r);
	35	DECLARE_WRITE8_MEMBER(pecom_cdp1869_pageram_w);
	36	DECLARE_WRITE8_MEMBER(pecom_bank_w);
	37	DECLARE_READ8_MEMBER(pecom_keyboard_r);
	38	DECLARE_WRITE8_MEMBER(pecom_cdp1869_w);
32	39	};
33	40
34	41	/*----------- defined in machine/pecom.c -----------*/
35	42
36	43	extern MACHINE_START( pecom );
37	44	extern MACHINE_RESET( pecom );
38		extern WRITE8_HANDLER( pecom_bank_w );
39		extern READ8_HANDLER (pecom_keyboard_r);
40	45
41	46	extern const cosmac_interface pecom64_cdp1802_config;
42	47
43	48	/* ---------- defined in video/pecom.c ---------- */
44	49
45		WRITE8_HANDLER( pecom_cdp1869_w );
46	50	MACHINE_CONFIG_EXTERN( pecom_video );
47	51
48	52	#endif

src/mess/includes/pce.h

r14963	r14964
121	121	int m_joystick_port_select;
122	122	int m_joystick_data_select;
123	123	UINT8 m_joy_6b_packet[5];
	124	DECLARE_WRITE8_MEMBER(pce_sf2_banking_w);
	125	DECLARE_WRITE8_MEMBER(pce_cartridge_ram_w);
	126	DECLARE_WRITE8_MEMBER(mess_pce_joystick_w);
	127	DECLARE_READ8_MEMBER(mess_pce_joystick_r);
	128	DECLARE_WRITE8_MEMBER(pce_cd_bram_w);
	129	DECLARE_WRITE8_MEMBER(pce_cd_intf_w);
	130	DECLARE_READ8_MEMBER(pce_cd_intf_r);
	131	DECLARE_READ8_MEMBER(pce_cd_acard_r);
	132	DECLARE_WRITE8_MEMBER(pce_cd_acard_w);
	133	DECLARE_READ8_MEMBER(pce_cd_acard_wram_r);
	134	DECLARE_WRITE8_MEMBER(pce_cd_acard_wram_w);
124	135	};
125	136
126	137
127	138	/*----------- defined in machine/pce.c -----------*/
128	139
129	140	DEVICE_IMAGE_LOAD(pce_cart);
130		WRITE8_HANDLER ( mess_pce_joystick_w );
131		READ8_HANDLER ( mess_pce_joystick_r );
132	141
133	142	extern const msm5205_interface pce_cd_msm5205_interface;
134		WRITE8_HANDLER( pce_cd_bram_w );
135		WRITE8_HANDLER( pce_cd_intf_w );
136		READ8_HANDLER( pce_cd_intf_r );
137		WRITE8_HANDLER( pce_cd_acard_w );
138		READ8_HANDLER( pce_cd_acard_r );
139		WRITE8_HANDLER( pce_cd_acard_wram_w );
140		READ8_HANDLER( pce_cd_acard_wram_r );
141	143
142	144	DRIVER_INIT( mess_pce );
143	145	DRIVER_INIT( tg16 );

src/mess/includes/pk8020.h

r14963	r14964
32	32	UINT8 m_portc_data;
33	33	UINT8 m_sound_gate;
34	34	UINT8 m_sound_level;
	35	DECLARE_READ8_MEMBER(keyboard_r);
	36	DECLARE_READ8_MEMBER(sysreg_r);
	37	DECLARE_WRITE8_MEMBER(sysreg_w);
	38	DECLARE_READ8_MEMBER(text_r);
	39	DECLARE_WRITE8_MEMBER(text_w);
	40	DECLARE_READ8_MEMBER(gzu_r);
	41	DECLARE_WRITE8_MEMBER(gzu_w);
	42	DECLARE_READ8_MEMBER(devices_r);
	43	DECLARE_WRITE8_MEMBER(devices_w);
35	44	};
36	45
37	46

src/mess/includes/galaxy.h

r14963	r14964
24	24	UINT32 m_start_addr;
25	25	emu_timer *m_gal_video_timer;
26	26	bitmap_ind16 m_bitmap;
	27	DECLARE_READ8_MEMBER(galaxy_keyboard_r);
	28	DECLARE_WRITE8_MEMBER(galaxy_latch_w);
27	29	};
28	30
29	31
r14963	r14964
33	35	MACHINE_RESET( galaxy );
34	36	INTERRUPT_GEN( galaxy_interrupt );
35	37	SNAPSHOT_LOAD( galaxy );
36		READ8_HANDLER( galaxy_keyboard_r );
37		WRITE8_HANDLER( galaxy_latch_w );
38	38
39	39	MACHINE_RESET( galaxyp );
40	40

src/mess/includes/bbc.h

r14963	r14964
219	219	int *m_videoULA_pallet_lookup;
220	220
221	221	void (*m_draw_function)(running_machine &machine);
	222	DECLARE_WRITE8_MEMBER(bbc_page_selecta_w);
	223	DECLARE_WRITE8_MEMBER(bbc_memorya1_w);
	224	DECLARE_WRITE8_MEMBER(bbc_page_selectb_w);
	225	DECLARE_WRITE8_MEMBER(bbc_memoryb3_w);
	226	DECLARE_WRITE8_MEMBER(bbc_memoryb4_w);
	227	DECLARE_WRITE8_MEMBER(bbc_page_selectbp_w);
	228	DECLARE_WRITE8_MEMBER(bbc_memorybp1_w);
	229	DECLARE_WRITE8_MEMBER(bbc_memorybp2_w);
	230	DECLARE_WRITE8_MEMBER(bbc_memorybp4_w);
	231	DECLARE_WRITE8_MEMBER(bbc_memorybp4_128_w);
	232	DECLARE_WRITE8_MEMBER(bbc_memorybp6_128_w);
	233	DECLARE_READ8_MEMBER(bbcm_ACCCON_read);
	234	DECLARE_WRITE8_MEMBER(bbcm_ACCCON_write);
	235	DECLARE_WRITE8_MEMBER(page_selectbm_w);
	236	DECLARE_WRITE8_MEMBER(bbc_memorybm1_w);
	237	DECLARE_WRITE8_MEMBER(bbc_memorybm2_w);
	238	DECLARE_WRITE8_MEMBER(bbc_memorybm4_w);
	239	DECLARE_WRITE8_MEMBER(bbc_memorybm5_w);
	240	DECLARE_WRITE8_MEMBER(bbc_memorybm7_w);
	241	DECLARE_READ8_MEMBER(bbcm_r);
	242	DECLARE_WRITE8_MEMBER(bbcm_w);
	243	DECLARE_WRITE8_MEMBER(bbc_SerialULA_w);
	244	DECLARE_READ8_MEMBER(bbc_i8271_read);
	245	DECLARE_WRITE8_MEMBER(bbc_i8271_write);
	246	DECLARE_WRITE8_MEMBER(bbc_wd177x_status_w);
	247	DECLARE_READ8_MEMBER(bbc_wd1770_read);
	248	DECLARE_WRITE8_MEMBER(bbc_wd1770_write);
	249	DECLARE_WRITE8_MEMBER(bbc_opus_status_w);
	250	DECLARE_READ8_MEMBER(bbc_opus_read);
	251	DECLARE_WRITE8_MEMBER(bbc_opus_write);
	252	DECLARE_READ8_MEMBER(bbcm_wd1770_read);
	253	DECLARE_WRITE8_MEMBER(bbcm_wd1770_write);
	254	DECLARE_READ8_MEMBER(bbcm_wd1770l_read);
	255	DECLARE_WRITE8_MEMBER(bbcm_wd1770l_write);
	256	DECLARE_READ8_MEMBER(bbc_disc_r);
	257	DECLARE_WRITE8_MEMBER(bbc_disc_w);
	258	DECLARE_WRITE8_MEMBER(bbc_videoULA_w);
	259	DECLARE_WRITE8_MEMBER(bbc_6845_w);
	260	DECLARE_READ8_MEMBER(bbc_6845_r);
	261	DECLARE_READ8_MEMBER(bbc_fe_r);
222	262	};
223	263
224	264
r14963	r14964
247	287	INTERRUPT_GEN( bbcb_keyscan );
248	288	INTERRUPT_GEN( bbcm_keyscan );
249	289
250		WRITE8_HANDLER ( bbc_memorya1_w );
251		WRITE8_HANDLER ( bbc_page_selecta_w );
252	290
253		WRITE8_HANDLER ( bbc_memoryb3_w );
254		WRITE8_HANDLER ( bbc_memoryb4_w );
255		WRITE8_HANDLER ( bbc_page_selectb_w );
256	291
257	292
258		WRITE8_HANDLER ( bbc_memorybp1_w );
259		WRITE8_HANDLER ( bbc_memorybp2_w );
260		WRITE8_HANDLER ( bbc_memorybp4_w );
261		WRITE8_HANDLER ( bbc_memorybp4_128_w );
262		WRITE8_HANDLER ( bbc_memorybp6_128_w );
263		WRITE8_HANDLER ( bbc_page_selectbp_w );
264	293
265	294
266		WRITE8_HANDLER ( bbc_memorybm1_w );
267		WRITE8_HANDLER ( bbc_memorybm2_w );
268		WRITE8_HANDLER ( bbc_memorybm4_w );
269		WRITE8_HANDLER ( bbc_memorybm5_w );
270		WRITE8_HANDLER ( bbc_memorybm7_w );
271		READ8_HANDLER  ( bbcm_r );
272		WRITE8_HANDLER ( bbcm_w );
273		READ8_HANDLER  ( bbcm_ACCCON_read );
274		WRITE8_HANDLER ( bbcm_ACCCON_write );
275	295
276	296
277	297	/* disc support */
278	298
279	299	DEVICE_IMAGE_LOAD ( bbcb_cart );
280	300
281		READ8_HANDLER  ( bbc_disc_r );
282		WRITE8_HANDLER ( bbc_disc_w );
283	301
284		READ8_HANDLER  ( bbc_wd1770_read );
285		WRITE8_HANDLER ( bbc_wd1770_write );
286	302
287		READ8_HANDLER  ( bbc_opus_read );
288		WRITE8_HANDLER ( bbc_opus_write );
289	303
290	304
291		READ8_HANDLER  ( bbcm_wd1770l_read );
292		WRITE8_HANDLER ( bbcm_wd1770l_write );
293		READ8_HANDLER  ( bbcm_wd1770_read );
294		WRITE8_HANDLER ( bbcm_wd1770_write );
295	305
296	306
297	307	/* tape support */
298	308
299		WRITE8_HANDLER ( bbc_SerialULA_w );
300	309
301	310	extern const i8271_interface bbc_i8271_interface;
302	311	extern const uPD7002_interface bbc_uPD7002;
r14963	r14964
315	324	void bbcbp_setvideoshadow(running_machine &machine, int vdusel);
316	325
317	326
318		WRITE8_HANDLER ( bbc_videoULA_w );
319	327
320		WRITE8_HANDLER ( bbc_6845_w );
321		READ8_HANDLER ( bbc_6845_r );
322	328
323	329
324	330	#endif /* BBC_H_ */

src/mess/video/gb.c

r14963	r14964
1295	1295	machine.scheduler().timer_set(machine.device<cpu_device>("maincpu")->cycles_to_attotime(1), FUNC(gb_video_init_vbl));
1296	1296
1297	1297	/* Initialize some video registers */
1298		gb_video_w( space, 0x0, 0x91 );    /* LCDCONT */
1299		gb_video_w( space, 0x7, 0xFC );    /* BGRDPAL */
1300		gb_video_w( space, 0x8, 0xFC );    /* SPR0PAL */
1301		gb_video_w( space, 0x9, 0xFC );    /* SPR1PAL */
	1298	state->gb_video_w( *space, 0x0, 0x91 );    /* LCDCONT */
	1299	state->gb_video_w( *space, 0x7, 0xFC );    /* BGRDPAL */
	1300	state->gb_video_w( *space, 0x8, 0xFC );    /* SPR0PAL */
	1301	state->gb_video_w( *space, 0x9, 0xFC );    /* SPR1PAL */
1302	1302
1303	1303	CURLINE = state->m_lcd.current_line = 0;
1304	1304	LCDSTAT = ( LCDSTAT & 0xF8 ) | 0x05;
r14963	r14964
1973	1973	state->m_lcd.lcd_timer->adjust(machine.device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
1974	1974	}
1975	1975
1976		READ8_HANDLER( gb_video_r )
	1976	READ8_MEMBER(gb_state::gb_video_r)
1977	1977	{
1978		gb_state *state = space->machine().driver_data<gb_state>();
1979		return state->m_lcd.gb_vid_regs[offset];
	1978	return m_lcd.gb_vid_regs[offset];
1980	1979	}
1981	1980
1982		READ8_HANDLER( gb_vram_r )
	1981	READ8_MEMBER(gb_state::gb_vram_r)
1983	1982	{
1984		gb_state *state = space->machine().driver_data<gb_state>();
1985		return ( state->m_lcd.vram_locked == LOCKED ) ? 0xFF : state->m_lcd.gb_vram_ptr[offset];
	1983	return ( m_lcd.vram_locked == LOCKED ) ? 0xFF : m_lcd.gb_vram_ptr[offset];
1986	1984	}
1987	1985
1988		WRITE8_HANDLER( gb_vram_w )
	1986	WRITE8_MEMBER(gb_state::gb_vram_w)
1989	1987	{
1990		gb_state *state = space->machine().driver_data<gb_state>();
1991		if ( state->m_lcd.vram_locked == LOCKED )
	1988	if ( m_lcd.vram_locked == LOCKED )
1992	1989	{
1993	1990	return;
1994	1991	}
1995		state->m_lcd.gb_vram_ptr[offset] = data;
	1992	m_lcd.gb_vram_ptr[offset] = data;
1996	1993	}
1997	1994
1998		READ8_HANDLER( gb_oam_r )
	1995	READ8_MEMBER(gb_state::gb_oam_r)
1999	1996	{
2000		gb_state *state = space->machine().driver_data<gb_state>();
2001		return ( state->m_lcd.oam_locked == LOCKED ) ? 0xFF : state->m_lcd.gb_oam->base()[offset];
	1997	return ( m_lcd.oam_locked == LOCKED ) ? 0xFF : m_lcd.gb_oam->base()[offset];
2002	1998	}
2003	1999
2004		WRITE8_HANDLER( gb_oam_w )
	2000	WRITE8_MEMBER(gb_state::gb_oam_w)
2005	2001	{
2006		gb_state *state = space->machine().driver_data<gb_state>();
2007		if ( state->m_lcd.oam_locked == LOCKED || offset >= 0xa0 )
	2002	if ( m_lcd.oam_locked == LOCKED || offset >= 0xa0 )
2008	2003	{
2009	2004	return;
2010	2005	}
2011		state->m_lcd.gb_oam->base()[offset] = data;
	2006	m_lcd.gb_oam->base()[offset] = data;
2012	2007	}
2013	2008
2014		WRITE8_HANDLER ( gb_video_w )
	2009	WRITE8_MEMBER(gb_state::gb_video_w)
2015	2010	{
2016		gb_state *state = space->machine().driver_data<gb_state>();
	2011	gb_state *state = machine().driver_data<gb_state>();
2017	2012	switch (offset)
2018	2013	{
2019	2014	case 0x00:                  /* LCDC - LCD Control */
2020		state->m_lcd.gb_chrgen = state->m_lcd.gb_vram->base() + ((data & 0x10) ? 0x0000 : 0x0800);
2021		state->m_lcd.gb_tile_no_mod = (data & 0x10) ? 0x00 : 0x80;
2022		state->m_lcd.gb_bgdtab = state->m_lcd.gb_vram->base() + ((data & 0x08) ? 0x1C00 : 0x1800 );
2023		state->m_lcd.gb_wndtab = state->m_lcd.gb_vram->base() + ((data & 0x40) ? 0x1C00 : 0x1800 );
	2015	m_lcd.gb_chrgen = m_lcd.gb_vram->base() + ((data & 0x10) ? 0x0000 : 0x0800);
	2016	m_lcd.gb_tile_no_mod = (data & 0x10) ? 0x00 : 0x80;
	2017	m_lcd.gb_bgdtab = m_lcd.gb_vram->base() + ((data & 0x08) ? 0x1C00 : 0x1800 );
	2018	m_lcd.gb_wndtab = m_lcd.gb_vram->base() + ((data & 0x40) ? 0x1C00 : 0x1800 );
2024	2019	/* if LCD controller is switched off, set STAT and LY to 00 */
2025	2020	if ( ! ( data & 0x80 ) )
2026	2021	{
2027	2022	LCDSTAT &= ~0x03;
2028	2023	CURLINE = 0;
2029		state->m_lcd.oam_locked = UNLOCKED;
2030		state->m_lcd.vram_locked = UNLOCKED;
	2024	m_lcd.oam_locked = UNLOCKED;
	2025	m_lcd.vram_locked = UNLOCKED;
2031	2026	}
2032	2027	/* If LCD is being switched on */
2033	2028	if ( !( LCDCONT & 0x80 ) && ( data & 0x80 ) )
2034	2029	{
2035		gb_lcd_switch_on(space->machine());
	2030	gb_lcd_switch_on(machine());
2036	2031	}
2037	2032	break;
2038	2033	case 0x01:                  /* STAT - LCD Status */
r14963	r14964
2058	2053	- 0x20 -> 0x00/0x08/0x10/0x20/0x40 (mode 2, after m2int) - don't trigger
2059	2054	- 0x20 -> 0x00/0x08/0x10/0x20/0x40 (mode 3, after m2int) - don't trigger
2060	2055	*/
2061		if ( ! state->m_lcd.mode_irq && ( ( state->m_lcd.mode == 1 ) ||
	2056	if ( ! m_lcd.mode_irq && ( ( m_lcd.mode == 1 ) ||
2062	2057	( ( LCDSTAT & 0x40 ) && ! ( data & 0x68 ) ) ||
2063	2058	( ! ( LCDSTAT & 0x40 ) && ( data & 0x40 ) && ( LCDSTAT & 0x04 ) ) ||
2064	2059	( ! ( LCDSTAT & 0x48 ) && ( data & 0x08 ) ) ||
r14963	r14964
2066	2061	( ( LCDSTAT & 0x60 ) == 0x20 && ( data & 0x40 ) )
2067	2062	) )
2068	2063	{
2069		cputag_set_input_line( space->machine(), "maincpu", LCD_INT, ASSERT_LINE );
	2064	cputag_set_input_line( machine(), "maincpu", LCD_INT, ASSERT_LINE );
2070	2065	}
2071	2066	/*
2072	2067	- 0x20 -> 0x08/0x18/0x28/0x48 (mode 0, after m2int) - trigger
2073	2068	- 0x20 -> 0x00/0x10/0x20/0x40 (mode 0, after m2int) - trigger (stat bug)
2074	2069	- 0x00 -> 0xXX (mode 0) - trigger stat bug
2075	2070	*/
2076		if ( state->m_lcd.mode_irq && state->m_lcd.mode == 0 )
	2071	if ( m_lcd.mode_irq && m_lcd.mode == 0 )
2077	2072	{
2078		cputag_set_input_line( space->machine(), "maincpu", LCD_INT, ASSERT_LINE );
	2073	cputag_set_input_line( machine(), "maincpu", LCD_INT, ASSERT_LINE );
2079	2074	}
2080	2075	}
2081	2076	break;
r14963	r14964
2086	2081	{
2087	2082	if ( CURLINE == data )
2088	2083	{
2089		if ( state->m_lcd.state != GB_LCD_STATE_LYXX_M0_INC && state->m_lcd.state != GB_LCD_STATE_LY9X_M1_INC )
	2084	if ( m_lcd.state != GB_LCD_STATE_LYXX_M0_INC && m_lcd.state != GB_LCD_STATE_LY9X_M1_INC )
2090	2085	{
2091	2086	LCDSTAT |= 0x04;
2092	2087	/* Generate lcd interrupt if requested */
2093	2088	if ( LCDSTAT & 0x40 )
2094	2089	{
2095		cputag_set_input_line( space->machine(), "maincpu", LCD_INT, ASSERT_LINE );
	2090	cputag_set_input_line( machine(), "maincpu", LCD_INT, ASSERT_LINE );
2096	2091	}
2097	2092	}
2098	2093	}
2099	2094	else
2100	2095	{
2101	2096	LCDSTAT &= 0xFB;
2102		state->m_lcd.triggering_line_irq = 0;
	2097	m_lcd.triggering_line_irq = 0;
2103	2098	}
2104	2099	}
2105	2100	break;
2106	2101	case 0x06:                  /* DMA - DMA Transfer and Start Address */
2107	2102	{
2108		UINT8 *P = state->m_lcd.gb_oam->base();
	2103	UINT8 *P = m_lcd.gb_oam->base();
2109	2104	offset = (UINT16) data << 8;
2110	2105	for (data = 0; data < 0xA0; data++)
2111		*P++ = space->read_byte(offset++);
	2106	*P++ = space.read_byte(offset++);
2112	2107	}
2113	2108	return;
2114	2109	case 0x07:                  /* BGP - Background Palette */
2115		(*state->update_scanline)(space->machine());
2116		state->m_lcd.gb_bpal[0] = data & 0x3;
2117		state->m_lcd.gb_bpal[1] = (data & 0xC) >> 2;
2118		state->m_lcd.gb_bpal[2] = (data & 0x30) >> 4;
2119		state->m_lcd.gb_bpal[3] = (data & 0xC0) >> 6;
	2110	(*update_scanline)(machine());
	2111	m_lcd.gb_bpal[0] = data & 0x3;
	2112	m_lcd.gb_bpal[1] = (data & 0xC) >> 2;
	2113	m_lcd.gb_bpal[2] = (data & 0x30) >> 4;
	2114	m_lcd.gb_bpal[3] = (data & 0xC0) >> 6;
2120	2115	break;
2121	2116	case 0x08:                  /* OBP0 - Object Palette 0 */
2122		//      (*state->update_scanline)( machine );
2123		state->m_lcd.gb_spal0[0] = data & 0x3;
2124		state->m_lcd.gb_spal0[1] = (data & 0xC) >> 2;
2125		state->m_lcd.gb_spal0[2] = (data & 0x30) >> 4;
2126		state->m_lcd.gb_spal0[3] = (data & 0xC0) >> 6;
	2117	//      (*update_scanline)( machine );
	2118	m_lcd.gb_spal0[0] = data & 0x3;
	2119	m_lcd.gb_spal0[1] = (data & 0xC) >> 2;
	2120	m_lcd.gb_spal0[2] = (data & 0x30) >> 4;
	2121	m_lcd.gb_spal0[3] = (data & 0xC0) >> 6;
2127	2122	break;
2128	2123	case 0x09:                  /* OBP1 - Object Palette 1 */
2129		//      (*state->update_scanline)( machine );
2130		state->m_lcd.gb_spal1[0] = data & 0x3;
2131		state->m_lcd.gb_spal1[1] = (data & 0xC) >> 2;
2132		state->m_lcd.gb_spal1[2] = (data & 0x30) >> 4;
2133		state->m_lcd.gb_spal1[3] = (data & 0xC0) >> 6;
	2124	//      (*update_scanline)( machine );
	2125	m_lcd.gb_spal1[0] = data & 0x3;
	2126	m_lcd.gb_spal1[1] = (data & 0xC) >> 2;
	2127	m_lcd.gb_spal1[2] = (data & 0x30) >> 4;
	2128	m_lcd.gb_spal1[3] = (data & 0xC0) >> 6;
2134	2129	break;
2135	2130	case 0x02:                  /* SCY - Scroll Y */
2136	2131	case 0x03:                  /* SCX - Scroll X */
2137		(*state->update_scanline)(space->machine());
	2132	(*update_scanline)(machine());
2138	2133	case 0x0A:                  /* WY - Window Y position */
2139	2134	case 0x0B:                  /* WX - Window X position */
2140	2135	break;
2141	2136	default:                  /* Unknown register, no change */
2142	2137	return;
2143	2138	}
2144		state->m_lcd.gb_vid_regs[ offset ] = data;
	2139	m_lcd.gb_vid_regs[ offset ] = data;
2145	2140	}
2146	2141
2147		READ8_HANDLER( gbc_video_r )
	2142	READ8_MEMBER(gb_state::gbc_video_r)
2148	2143	{
2149		gb_state *state = space->machine().driver_data<gb_state>();
2150	2144	switch( offset )
2151	2145	{
2152	2146	case 0x11:   /* FF51 */
r14963	r14964
2156	2150	return 0xFF;
2157	2151	case 0x29:   /* FF69 */
2158	2152	case 0x2B:   /* FF6B */
2159		if ( state->m_lcd.pal_locked == LOCKED )
	2153	if ( m_lcd.pal_locked == LOCKED )
2160	2154	{
2161	2155	return 0xFF;
2162	2156	}
2163	2157	break;
2164	2158	}
2165		return state->m_lcd.gb_vid_regs[offset];
	2159	return m_lcd.gb_vid_regs[offset];
2166	2160	}
2167	2161
2168		WRITE8_HANDLER ( gbc_video_w )
	2162	WRITE8_MEMBER(gb_state::gbc_video_w)
2169	2163	{
2170		gb_state *state = space->machine().driver_data<gb_state>();
	2164	gb_state *state = machine().driver_data<gb_state>();
2171	2165	switch( offset )
2172	2166	{
2173	2167	case 0x00:      /* LCDC - LCD Control */
2174		state->m_lcd.gb_chrgen = state->m_lcd.gb_vram->base() + ((data & 0x10) ? 0x0000 : 0x0800);
2175		state->m_lcd.gbc_chrgen = state->m_lcd.gb_vram->base() + ((data & 0x10) ? 0x2000 : 0x2800);
2176		state->m_lcd.gb_tile_no_mod = (data & 0x10) ? 0x00 : 0x80;
2177		state->m_lcd.gb_bgdtab = state->m_lcd.gb_vram->base() + ((data & 0x08) ? 0x1C00 : 0x1800);
2178		state->m_lcd.gbc_bgdtab = state->m_lcd.gb_vram->base() + ((data & 0x08) ? 0x3C00 : 0x3800);
2179		state->m_lcd.gb_wndtab = state->m_lcd.gb_vram->base() + ((data & 0x40) ? 0x1C00 : 0x1800);
2180		state->m_lcd.gbc_wndtab = state->m_lcd.gb_vram->base() + ((data & 0x40) ? 0x3C00 : 0x3800);
	2168	m_lcd.gb_chrgen = m_lcd.gb_vram->base() + ((data & 0x10) ? 0x0000 : 0x0800);
	2169	m_lcd.gbc_chrgen = m_lcd.gb_vram->base() + ((data & 0x10) ? 0x2000 : 0x2800);
	2170	m_lcd.gb_tile_no_mod = (data & 0x10) ? 0x00 : 0x80;
	2171	m_lcd.gb_bgdtab = m_lcd.gb_vram->base() + ((data & 0x08) ? 0x1C00 : 0x1800);
	2172	m_lcd.gbc_bgdtab = m_lcd.gb_vram->base() + ((data & 0x08) ? 0x3C00 : 0x3800);
	2173	m_lcd.gb_wndtab = m_lcd.gb_vram->base() + ((data & 0x40) ? 0x1C00 : 0x1800);
	2174	m_lcd.gbc_wndtab = m_lcd.gb_vram->base() + ((data & 0x40) ? 0x3C00 : 0x3800);
2181	2175	/* if LCD controller is switched off, set STAT to 00 */
2182	2176	if ( ! ( data & 0x80 ) )
2183	2177	{
2184	2178	LCDSTAT &= ~0x03;
2185	2179	CURLINE = 0;
2186		state->m_lcd.oam_locked = UNLOCKED;
2187		state->m_lcd.vram_locked = UNLOCKED;
2188		state->m_lcd.pal_locked = UNLOCKED;
	2180	m_lcd.oam_locked = UNLOCKED;
	2181	m_lcd.vram_locked = UNLOCKED;
	2182	m_lcd.pal_locked = UNLOCKED;
2189	2183	}
2190	2184	/* If LCD is being switched on */
2191	2185	if ( !( LCDCONT & 0x80 ) && ( data & 0x80 ) )
2192	2186	{
2193		gb_lcd_switch_on(space->machine());
	2187	gb_lcd_switch_on(machine());
2194	2188	}
2195	2189	break;
2196	2190	case 0x01:      /* STAT - LCD Status */
r14963	r14964
2200	2194	/*
2201	2195	- 0x20 -> 0x08/0x18/0x28/0x48 (mode 0, after m2int) - trigger
2202	2196	*/
2203		if ( state->m_lcd.mode_irq && state->m_lcd.mode == 0 && ( LCDSTAT & 0x28 ) == 0x20 && ( data & 0x08 ) )
	2197	if ( m_lcd.mode_irq && m_lcd.mode == 0 && ( LCDSTAT & 0x28 ) == 0x20 && ( data & 0x08 ) )
2204	2198	{
2205		cputag_set_input_line( space->machine(), "maincpu", LCD_INT, ASSERT_LINE );
	2199	cputag_set_input_line( machine(), "maincpu", LCD_INT, ASSERT_LINE );
2206	2200	}
2207	2201	/* Check if line irqs are being disabled */
2208	2202	if ( ! ( data & 0x40 ) )
2209	2203	{
2210		state->m_lcd.delayed_line_irq = 0;
	2204	m_lcd.delayed_line_irq = 0;
2211	2205	}
2212	2206	/* Check if line irqs are being enabled */
2213	2207	if ( ! ( LCDSTAT & 0x40 ) && ( data & 0x40 ) )
2214	2208	{
2215	2209	if ( CMPLINE == CURLINE )
2216	2210	{
2217		state->m_lcd.line_irq = 1;
2218		cputag_set_input_line( space->machine(), "maincpu", LCD_INT, ASSERT_LINE );
	2211	m_lcd.line_irq = 1;
	2212	cputag_set_input_line( machine(), "maincpu", LCD_INT, ASSERT_LINE );
2219	2213	}
2220	2214	}
2221	2215	}
r14963	r14964
2223	2217	case 0x05:                      /* LYC */
2224	2218	if ( CMPLINE != data )
2225	2219	{
2226		if ( ( state->m_lcd.state != GB_LCD_STATE_LYXX_M0_PRE_INC && CURLINE == data ) ||
2227		( state->m_lcd.state == GB_LCD_STATE_LYXX_M0_INC && state->m_lcd.triggering_line_irq ) )
	2220	if ( ( m_lcd.state != GB_LCD_STATE_LYXX_M0_PRE_INC && CURLINE == data ) ||
	2221	( m_lcd.state == GB_LCD_STATE_LYXX_M0_INC && m_lcd.triggering_line_irq ) )
2228	2222	{
2229	2223	LCDSTAT |= 0x04;
2230	2224	/* Generate lcd interrupt if requested */
2231	2225	if ( LCDSTAT & 0x40 )
2232	2226	{
2233		cputag_set_input_line( space->machine(), "maincpu", LCD_INT, ASSERT_LINE );
	2227	cputag_set_input_line( machine(), "maincpu", LCD_INT, ASSERT_LINE );
2234	2228	}
2235	2229	}
2236	2230	else
2237	2231	{
2238	2232	LCDSTAT &= 0xFB;
2239		state->m_lcd.triggering_line_irq = 0;
2240		state->m_lcd.cmp_line = data;
	2233	m_lcd.triggering_line_irq = 0;
	2234	m_lcd.cmp_line = data;
2241	2235	}
2242	2236	}
2243	2237	break;
2244	2238	case 0x07:      /* BGP - GB background palette */
2245		(*state->update_scanline)(space->machine());
2246		state->m_lcd.gb_bpal[0] = data & 0x3;
2247		state->m_lcd.gb_bpal[1] = (data & 0xC) >> 2;
2248		state->m_lcd.gb_bpal[2] = (data & 0x30) >> 4;
2249		state->m_lcd.gb_bpal[3] = (data & 0xC0) >> 6;
	2239	(*update_scanline)(machine());
	2240	m_lcd.gb_bpal[0] = data & 0x3;
	2241	m_lcd.gb_bpal[1] = (data & 0xC) >> 2;
	2242	m_lcd.gb_bpal[2] = (data & 0x30) >> 4;
	2243	m_lcd.gb_bpal[3] = (data & 0xC0) >> 6;
2250	2244	break;
2251	2245	case 0x08:      /* OBP0 - GB Object 0 palette */
2252		state->m_lcd.gb_spal0[0] = data & 0x3;
2253		state->m_lcd.gb_spal0[1] = (data & 0xC) >> 2;
2254		state->m_lcd.gb_spal0[2] = (data & 0x30) >> 4;
2255		state->m_lcd.gb_spal0[3] = (data & 0xC0) >> 6;
	2246	m_lcd.gb_spal0[0] = data & 0x3;
	2247	m_lcd.gb_spal0[1] = (data & 0xC) >> 2;
	2248	m_lcd.gb_spal0[2] = (data & 0x30) >> 4;
	2249	m_lcd.gb_spal0[3] = (data & 0xC0) >> 6;
2256	2250	break;
2257	2251	case 0x09:      /* OBP1 - GB Object 1 palette */
2258		state->m_lcd.gb_spal1[0] = data & 0x3;
2259		state->m_lcd.gb_spal1[1] = (data & 0xC) >> 2;
2260		state->m_lcd.gb_spal1[2] = (data & 0x30) >> 4;
2261		state->m_lcd.gb_spal1[3] = (data & 0xC0) >> 6;
	2252	m_lcd.gb_spal1[0] = data & 0x3;
	2253	m_lcd.gb_spal1[1] = (data & 0xC) >> 2;
	2254	m_lcd.gb_spal1[2] = (data & 0x30) >> 4;
	2255	m_lcd.gb_spal1[3] = (data & 0xC0) >> 6;
2262	2256	break;
2263	2257	case 0x0c:      /* Undocumented register involved in selecting gb/gbc mode */
2264	2258	logerror( "Write to undocumented register: %X = %X\n", offset, data );
2265	2259	break;
2266	2260	case 0x0F:      /* VBK - VRAM bank select */
2267		state->m_lcd.gb_vram_ptr = state->m_lcd.gb_vram->base() + ( data & 0x01 ) * 0x2000;
	2261	m_lcd.gb_vram_ptr = m_lcd.gb_vram->base() + ( data & 0x01 ) * 0x2000;
2268	2262	data |= 0xFE;
2269	2263	break;
2270	2264	case 0x11:      /* HDMA1 - HBL General DMA - Source High */
r14963	r14964
2281	2275	case 0x15:      /* HDMA5 - HBL General DMA - Mode, Length */
2282	2276	if( !(data & 0x80) )
2283	2277	{
2284		if( state->m_lcd.hdma_enabled )
	2278	if( m_lcd.hdma_enabled )
2285	2279	{
2286		state->m_lcd.hdma_enabled = 0;
	2280	m_lcd.hdma_enabled = 0;
2287	2281	data = HDMA5 & 0x80;
2288	2282	}
2289	2283	else
2290	2284	{
2291	2285	/* General DMA */
2292		gbc_hdma( space->machine(), ((data & 0x7F) + 1) * 0x10 );
	2286	gbc_hdma( machine(), ((data & 0x7F) + 1) * 0x10 );
2293	2287	//              cpunum_set_reg( 0, LR35902_DMA_CYCLES, 4 + ( ( ( data & 0x7F ) + 1 ) * 32 ) );
2294	2288	data = 0xff;
2295	2289	}
r14963	r14964
2297	2291	else
2298	2292	{
2299	2293	/* H-Blank DMA */
2300		state->m_lcd.hdma_enabled = 1;
	2294	m_lcd.hdma_enabled = 1;
2301	2295	data &= 0x7f;
2302		state->m_lcd.gb_vid_regs[offset] = data;
	2296	m_lcd.gb_vid_regs[offset] = data;
2303	2297	/* Check if HDMA should be immediately performed */
2304		if ( state->m_lcd.hdma_possible )
	2298	if ( m_lcd.hdma_possible )
2305	2299	{
2306		gbc_hdma( space->machine(), 0x10 );
	2300	gbc_hdma( machine(), 0x10 );
2307	2301	//              cpunum_set_reg( 0, LR35902_DMA_CYCLES, 36 );
2308		state->m_lcd.hdma_possible = 0;
	2302	m_lcd.hdma_possible = 0;
2309	2303	}
2310	2304	}
2311	2305	break;
2312	2306	case 0x28:      /* BCPS - Background palette specification */
2313	2307	GBCBCPS = data;
2314	2308	if (data & 0x01)
2315		GBCBCPD = state->m_lcd.cgb_bpal[( data >> 1 ) & 0x1F] >> 8;
	2309	GBCBCPD = m_lcd.cgb_bpal[( data >> 1 ) & 0x1F] >> 8;
2316	2310	else
2317		GBCBCPD = state->m_lcd.cgb_bpal[( data >> 1 ) & 0x1F] & 0xFF;
	2311	GBCBCPD = m_lcd.cgb_bpal[( data >> 1 ) & 0x1F] & 0xFF;
2318	2312	break;
2319	2313	case 0x29:      /* BCPD - background palette data */
2320		if ( state->m_lcd.pal_locked == LOCKED )
	2314	if ( m_lcd.pal_locked == LOCKED )
2321	2315	{
2322	2316	return;
2323	2317	}
2324	2318	GBCBCPD = data;
2325	2319	if (GBCBCPS & 0x01)
2326		state->m_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] = ((data << 8) | (state->m_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] & 0xFF)) & 0x7FFF;
	2320	m_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] = ((data << 8) | (m_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] & 0xFF)) & 0x7FFF;
2327	2321	else
2328		state->m_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] = ((state->m_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] & 0xFF00) | data) & 0x7FFF;
	2322	m_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] = ((m_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] & 0xFF00) | data) & 0x7FFF;
2329	2323	if( GBCBCPS & 0x80 )
2330	2324	{
2331	2325	GBCBCPS++;
r14963	r14964
2335	2329	case 0x2A:      /* OCPS - Object palette specification */
2336	2330	GBCOCPS = data;
2337	2331	if (data & 0x01)
2338		GBCOCPD = state->m_lcd.cgb_spal[( data >> 1 ) & 0x1F] >> 8;
	2332	GBCOCPD = m_lcd.cgb_spal[( data >> 1 ) & 0x1F] >> 8;
2339	2333	else
2340		GBCOCPD = state->m_lcd.cgb_spal[( data >> 1 ) & 0x1F] & 0xFF;
	2334	GBCOCPD = m_lcd.cgb_spal[( data >> 1 ) & 0x1F] & 0xFF;
2341	2335	break;
2342	2336	case 0x2B:      /* OCPD - Object palette data */
2343		if ( state->m_lcd.pal_locked == LOCKED )
	2337	if ( m_lcd.pal_locked == LOCKED )
2344	2338	{
2345	2339	return;
2346	2340	}
2347	2341	GBCOCPD = data;
2348	2342	if (GBCOCPS & 0x01)
2349		state->m_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] = ((data << 8) | (state->m_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] & 0xFF)) & 0x7FFF;
	2343	m_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] = ((data << 8) | (m_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] & 0xFF)) & 0x7FFF;
2350	2344	else
2351		state->m_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] = ((state->m_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] & 0xFF00) | data) & 0x7FFF;
	2345	m_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] = ((m_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] & 0xFF00) | data) & 0x7FFF;
2352	2346	if( GBCOCPS & 0x80 )
2353	2347	{
2354	2348	GBCOCPS++;
r14963	r14964
2362	2356	data = 0xFE | ( data & 0x01 );
2363	2357	if ( data & 0x01 )
2364	2358	{
2365		state->m_lcd.gbc_mode = 0;
	2359	m_lcd.gbc_mode = 0;
2366	2360	}
2367	2361	break;
2368	2362	case 0x32:
r14963	r14964
2386	2380	return;
2387	2381	}
2388	2382
2389		state->m_lcd.gb_vid_regs[offset] = data;
	2383	m_lcd.gb_vid_regs[offset] = data;
2390	2384	}
2391	2385
2392	2386

src/mess/video/mz700.c

r14963	r14964
127	127	CGRAM
128	128	***************************************************************************/
129	129
130		WRITE8_HANDLER( mz800_cgram_w )
	130	WRITE8_MEMBER(mz_state::mz800_cgram_w)
131	131	{
132		mz_state *mz = space->machine().driver_data<mz_state>();
133		mz->m_cgram[offset] = data;
	132	m_cgram[offset] = data;
134	133
135		gfx_element_mark_dirty(space->machine().gfx[0], offset/8);
	134	gfx_element_mark_dirty(machine().gfx[0], offset/8);
136	135	}

src/mess/video/aquarius.c

r14963	r14964
64	64	colortable_entry_set_value(machine.colortable, i, aquarius_palette[i]);
65	65	}
66	66
67		WRITE8_HANDLER( aquarius_videoram_w )
	67	WRITE8_MEMBER(aquarius_state::aquarius_videoram_w)
68	68	{
69		aquarius_state *state = space->machine().driver_data<aquarius_state>();
70		UINT8 *videoram = state->m_videoram;
	69	UINT8 *videoram = m_videoram;
71	70	videoram[offset] = data;
72		state->m_tilemap->mark_tile_dirty(offset);
	71	m_tilemap->mark_tile_dirty(offset);
73	72	}
74	73
75		WRITE8_HANDLER( aquarius_colorram_w )
	74	WRITE8_MEMBER(aquarius_state::aquarius_colorram_w)
76	75	{
77		aquarius_state *state = space->machine().driver_data<aquarius_state>();
78		state->m_colorram[offset] = data;
79		state->m_tilemap->mark_tile_dirty(offset);
	76	m_colorram[offset] = data;
	77	m_tilemap->mark_tile_dirty(offset);
80	78	}
81	79
82	80	static TILE_GET_INFO(aquarius_gettileinfo)

src/mess/video/a7800.c

r14963	r14964
440	440
441	441	/****** MARIA ***************************************/
442	442
443		READ8_HANDLER( a7800_MARIA_r )
	443	READ8_MEMBER(a7800_state::a7800_MARIA_r)
444	444	{
445		a7800_state *state = space->machine().driver_data<a7800_state>();
446		UINT8 *ROM = space->machine().region("maincpu")->base();
	445	UINT8 *ROM = machine().region("maincpu")->base();
447	446	switch (offset)
448	447	{
449	448	case 0x08:
450		return state->m_maria_vblank;
	449	return m_maria_vblank;
451	450
452	451	default:
453	452	logerror("undefined MARIA read %x\n",offset);
r14963	r14964
455	454	}
456	455	}
457	456
458		WRITE8_HANDLER( a7800_MARIA_w )
	457	WRITE8_MEMBER(a7800_state::a7800_MARIA_w)
459	458	{
460		a7800_state *state = space->machine().driver_data<a7800_state>();
461		UINT8 *ROM = space->machine().region("maincpu")->base();
	459	UINT8 *ROM = machine().region("maincpu")->base();
462	460	switch (offset)
463	461	{
464	462	case 0x00:
465		state->m_maria_backcolor = data;
466		// 20030621 ericball added state->m_maria_palette[pal][0] to make kanagroo mode easier
467		state->m_maria_palette[0][0]=state->m_maria_backcolor;
468		state->m_maria_palette[1][0]=state->m_maria_backcolor;
469		state->m_maria_palette[2][0]=state->m_maria_backcolor;
470		state->m_maria_palette[3][0]=state->m_maria_backcolor;
471		state->m_maria_palette[4][0]=state->m_maria_backcolor;
472		state->m_maria_palette[5][0]=state->m_maria_backcolor;
473		state->m_maria_palette[6][0]=state->m_maria_backcolor;
474		state->m_maria_palette[7][0]=state->m_maria_backcolor;
	463	m_maria_backcolor = data;
	464	// 20030621 ericball added m_maria_palette[pal][0] to make kanagroo mode easier
	465	m_maria_palette[0][0]=m_maria_backcolor;
	466	m_maria_palette[1][0]=m_maria_backcolor;
	467	m_maria_palette[2][0]=m_maria_backcolor;
	468	m_maria_palette[3][0]=m_maria_backcolor;
	469	m_maria_palette[4][0]=m_maria_backcolor;
	470	m_maria_palette[5][0]=m_maria_backcolor;
	471	m_maria_palette[6][0]=m_maria_backcolor;
	472	m_maria_palette[7][0]=m_maria_backcolor;
475	473	break;
476	474	case 0x01:
477		state->m_maria_palette[0][1] = data;
	475	m_maria_palette[0][1] = data;
478	476	break;
479	477	case 0x02:
480		state->m_maria_palette[0][2] = data;
	478	m_maria_palette[0][2] = data;
481	479	break;
482	480	case 0x03:
483		state->m_maria_palette[0][3] = data;
	481	m_maria_palette[0][3] = data;
484	482	break;
485	483	case 0x04:
486		device_spin_until_trigger(space->machine().device("maincpu"), TRIGGER_HSYNC);
487		state->m_maria_wsync=1;
	484	device_spin_until_trigger(machine().device("maincpu"), TRIGGER_HSYNC);
	485	m_maria_wsync=1;
488	486	break;
489	487
490	488	case 0x05:
491		state->m_maria_palette[1][1] = data;
	489	m_maria_palette[1][1] = data;
492	490	break;
493	491	case 0x06:
494		state->m_maria_palette[1][2] = data;
	492	m_maria_palette[1][2] = data;
495	493	break;
496	494	case 0x07:
497		state->m_maria_palette[1][3] = data;
	495	m_maria_palette[1][3] = data;
498	496	break;
499	497
500	498	case 0x09:
501		state->m_maria_palette[2][1] = data;
	499	m_maria_palette[2][1] = data;
502	500	break;
503	501	case 0x0A:
504		state->m_maria_palette[2][2] = data;
	502	m_maria_palette[2][2] = data;
505	503	break;
506	504	case 0x0B:
507		state->m_maria_palette[2][3] = data;
	505	m_maria_palette[2][3] = data;
508	506	break;
509	507
510	508	case 0x0D:
511		state->m_maria_palette[3][1] = data;
	509	m_maria_palette[3][1] = data;
512	510	break;
513	511	case 0x0E:
514		state->m_maria_palette[3][2] = data;
	512	m_maria_palette[3][2] = data;
515	513	break;
516	514	case 0x0F:
517		state->m_maria_palette[3][3] = data;
	515	m_maria_palette[3][3] = data;
518	516	break;
519	517
520	518	case 0x11:
521		state->m_maria_palette[4][1] = data;
	519	m_maria_palette[4][1] = data;
522	520	break;
523	521	case 0x12:
524		state->m_maria_palette[4][2] = data;
	522	m_maria_palette[4][2] = data;
525	523	break;
526	524	case 0x13:
527		state->m_maria_palette[4][3] = data;
	525	m_maria_palette[4][3] = data;
528	526	break;
529	527	case 0x14:
530		state->m_maria_charbase = (data << 8);
	528	m_maria_charbase = (data << 8);
531	529	break;
532	530	case 0x15:
533		state->m_maria_palette[5][1] = data;
	531	m_maria_palette[5][1] = data;
534	532	break;
535	533	case 0x16:
536		state->m_maria_palette[5][2] = data;
	534	m_maria_palette[5][2] = data;
537	535	break;
538	536	case 0x17:
539		state->m_maria_palette[5][3] = data;
	537	m_maria_palette[5][3] = data;
540	538	break;
541	539
542	540	case 0x19:
543		state->m_maria_palette[6][1] = data;
	541	m_maria_palette[6][1] = data;
544	542	break;
545	543	case 0x1A:
546		state->m_maria_palette[6][2] = data;
	544	m_maria_palette[6][2] = data;
547	545	break;
548	546	case 0x1B:
549		state->m_maria_palette[6][3] = data;
	547	m_maria_palette[6][3] = data;
550	548	break;
551	549
552	550	case 0x1C:
553	551	/*logerror("MARIA CTRL=%x\n",data);*/
554		state->m_maria_color_kill = data & 0x80;
	552	m_maria_color_kill = data & 0x80;
555	553	if ((data & 0x60) == 0x40)
556		state->m_maria_dmaon = 1;
	554	m_maria_dmaon = 1;
557	555	else
558		state->m_maria_dmaon = state->m_maria_dodma = 0;
	556	m_maria_dmaon = m_maria_dodma = 0;
559	557
560		state->m_maria_cwidth = data & 0x10;
561		state->m_maria_bcntl = data & 0x08;
562		state->m_maria_kangaroo = data & 0x04;
563		state->m_maria_rm = data & 0x03;
	558	m_maria_cwidth = data & 0x10;
	559	m_maria_bcntl = data & 0x08;
	560	m_maria_kangaroo = data & 0x04;
	561	m_maria_rm = data & 0x03;
564	562
565	563	/*logerror( "MARIA CTRL: CK:%d DMA:%d CW:%d BC:%d KM:%d RM:%d\n",
566		state->m_maria_color_kill ? 1 : 0,
	564	m_maria_color_kill ? 1 : 0,
567	565	( data & 0x60 ) >> 5,
568		state->m_maria_cwidth ? 1 : 0,
569		state->m_maria_bcntl ? 1 : 0,
570		state->m_maria_kangaroo ? 1 : 0,
571		state->m_maria_rm );*/
	566	m_maria_cwidth ? 1 : 0,
	567	m_maria_bcntl ? 1 : 0,
	568	m_maria_kangaroo ? 1 : 0,
	569	m_maria_rm );*/
572	570
573	571	break;
574	572	case 0x1D:
575		state->m_maria_palette[7][1] = data;
	573	m_maria_palette[7][1] = data;
576	574	break;
577	575	case 0x1E:
578		state->m_maria_palette[7][2] = data;
	576	m_maria_palette[7][2] = data;
579	577	break;
580	578	case 0x1F:
581		state->m_maria_palette[7][3] = data;
	579	m_maria_palette[7][3] = data;
582	580	break;
583	581	}
584	582	ROM[ 0x20 + offset ] = data;

src/mess/video/microtan.c

r14963	r14964
18	18
19	19
20	20
21		WRITE8_HANDLER( microtan_videoram_w )
	21	WRITE8_MEMBER(microtan_state::microtan_videoram_w)
22	22	{
23		microtan_state *state = space->machine().driver_data<microtan_state>();
24		UINT8 *videoram = state->m_videoram;
25		if ((videoram[offset] != data) || (state->m_chunky_buffer[offset] != state->m_chunky_graphics))
	23	UINT8 *videoram = m_videoram;
	24	if ((videoram[offset] != data) || (m_chunky_buffer[offset] != m_chunky_graphics))
26	25	{
27	26	videoram[offset] = data;
28		state->m_bg_tilemap->mark_tile_dirty(offset);
29		state->m_chunky_buffer[offset] = state->m_chunky_graphics;
	27	m_bg_tilemap->mark_tile_dirty(offset);
	28	m_chunky_buffer[offset] = m_chunky_graphics;
30	29	}
31	30	}
32	31

src/mess/video/rmnimbus.c

r14963	r14964
102	102	to return the values for all of them, it doesn't seem to hurt !
103	103	*/
104	104
105		READ16_HANDLER (nimbus_video_io_r)
	105	READ16_MEMBER(rmnimbus_state::nimbus_video_io_r)
106	106	{
107		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
108		int     pc=cpu_get_pc(&space->device());
	107	rmnimbus_state *state = machine().driver_data<rmnimbus_state>();
	108	int     pc=cpu_get_pc(&space.device());
109	109	UINT16  result;
110	110
111	111	switch (offset)
112	112	{
113		case    reg000  : result=state->m_vidregs[reg000]; break;
114		case    reg002  : result=state->m_vidregs[reg002]; break;
115		case    reg004  : result=state->m_vidregs[reg004]; break;
116		case    reg006  : result=state->m_vidregs[reg006]; break;
117		case    reg008  : result=state->m_vidregs[reg008]; break;
	113	case    reg000  : result=m_vidregs[reg000]; break;
	114	case    reg002  : result=m_vidregs[reg002]; break;
	115	case    reg004  : result=m_vidregs[reg004]; break;
	116	case    reg006  : result=m_vidregs[reg006]; break;
	117	case    reg008  : result=m_vidregs[reg008]; break;
118	118	case    reg00A  : result=read_reg_00A(state); break;
119		case    reg00C  : result=state->m_vidregs[reg00C]; break;
120		case    reg00E  : result=state->m_vidregs[reg00E]; break;
	119	case    reg00C  : result=m_vidregs[reg00C]; break;
	120	case    reg00E  : result=m_vidregs[reg00E]; break;
121	121
122		case    reg010  : result=state->m_vidregs[reg010]; break;
123		case    reg012  : result=state->m_vidregs[reg012]; break;
124		case    reg014  : result=state->m_vidregs[reg014]; break;
125		case    reg016  : result=state->m_vidregs[reg016]; break;
126		case    reg018  : result=state->m_vidregs[reg018]; break;
127		case    reg01A  : result=state->m_vidregs[reg01A]; break;
128		case    reg01C  : result=state->m_vidregs[reg01C]; break;
129		case    reg01E  : result=state->m_vidregs[reg01E]; break;
	122	case    reg010  : result=m_vidregs[reg010]; break;
	123	case    reg012  : result=m_vidregs[reg012]; break;
	124	case    reg014  : result=m_vidregs[reg014]; break;
	125	case    reg016  : result=m_vidregs[reg016]; break;
	126	case    reg018  : result=m_vidregs[reg018]; break;
	127	case    reg01A  : result=m_vidregs[reg01A]; break;
	128	case    reg01C  : result=m_vidregs[reg01C]; break;
	129	case    reg01E  : result=m_vidregs[reg01E]; break;
130	130
131		case    reg020  : result=state->m_vidregs[reg020]; break;
132		case    reg022  : result=state->m_vidregs[reg022]; break;
133		case    reg024  : result=state->m_vidregs[reg024]; break;
134		case    reg026  : result=state->m_vidregs[reg026]; break;
135		case    reg028  : result=state->m_hs_count; break; //result=state->m_vidregs[reg028]; break;
136		case    reg02A  : result=state->m_vidregs[reg02A]; break;
137		case    reg02C  : result=state->m_vidregs[reg02C]; break;
138		case    reg02E  : result=state->m_vidregs[reg02E]; break;
	131	case    reg020  : result=m_vidregs[reg020]; break;
	132	case    reg022  : result=m_vidregs[reg022]; break;
	133	case    reg024  : result=m_vidregs[reg024]; break;
	134	case    reg026  : result=m_vidregs[reg026]; break;
	135	case    reg028  : result=m_hs_count; break; //result=m_vidregs[reg028]; break;
	136	case    reg02A  : result=m_vidregs[reg02A]; break;
	137	case    reg02C  : result=m_vidregs[reg02C]; break;
	138	case    reg02E  : result=m_vidregs[reg02E]; break;
139	139	default         : result=0; break;
140	140	}
141	141
r14963	r14964
263	263
264	264	*/
265	265
266		WRITE16_HANDLER (nimbus_video_io_w)
	266	WRITE16_MEMBER(rmnimbus_state::nimbus_video_io_w)
267	267	{
268		rmnimbus_state *state = space->machine().driver_data<rmnimbus_state>();
269		int pc=cpu_get_pc(&space->device());
	268	rmnimbus_state *state = machine().driver_data<rmnimbus_state>();
	269	int pc=cpu_get_pc(&space.device());
270	270
271	271	if(offset<reg028)
272	272	{
r14963	r14964
279	279
280	280	switch (offset)
281	281	{
282		case    reg000  : state->m_vidregs[reg000]=data; break;
283		case    reg002  : state->m_vidregs[reg002]=data; break;
284		case    reg004  : state->m_vidregs[reg004]=data; write_reg_004(state); break;
285		case    reg006  : state->m_vidregs[reg006]=data; write_reg_006(state); break;
286		case    reg008  : state->m_vidregs[reg008]=data; break;
287		case    reg00A  : state->m_vidregs[reg00A]=data; break;
288		case    reg00C  : state->m_vidregs[reg00C]=data; break;
289		case    reg00E  : state->m_vidregs[reg00E]=data; break;
	282	case    reg000  : m_vidregs[reg000]=data; break;
	283	case    reg002  : m_vidregs[reg002]=data; break;
	284	case    reg004  : m_vidregs[reg004]=data; write_reg_004(state); break;
	285	case    reg006  : m_vidregs[reg006]=data; write_reg_006(state); break;
	286	case    reg008  : m_vidregs[reg008]=data; break;
	287	case    reg00A  : m_vidregs[reg00A]=data; break;
	288	case    reg00C  : m_vidregs[reg00C]=data; break;
	289	case    reg00E  : m_vidregs[reg00E]=data; break;
290	290
291		case    reg010  : state->m_vidregs[reg010]=data; write_reg_010(state); break;
292		case    reg012  : state->m_vidregs[reg012]=data; write_reg_012(state); break;
293		case    reg014  : state->m_vidregs[reg014]=data; write_reg_014(state); break;
294		case    reg016  : state->m_vidregs[reg016]=data; write_reg_016(state); break;
295		case    reg018  : state->m_vidregs[reg018]=data; break;
296		case    reg01A  : state->m_vidregs[reg01A]=data; write_reg_01A(state); break;
297		case    reg01C  : state->m_vidregs[reg01C]=data; write_reg_01C(state);break;
298		case    reg01E  : state->m_vidregs[reg01E]=data; write_reg_01E(state);break;
	291	case    reg010  : m_vidregs[reg010]=data; write_reg_010(state); break;
	292	case    reg012  : m_vidregs[reg012]=data; write_reg_012(state); break;
	293	case    reg014  : m_vidregs[reg014]=data; write_reg_014(state); break;
	294	case    reg016  : m_vidregs[reg016]=data; write_reg_016(state); break;
	295	case    reg018  : m_vidregs[reg018]=data; break;
	296	case    reg01A  : m_vidregs[reg01A]=data; write_reg_01A(state); break;
	297	case    reg01C  : m_vidregs[reg01C]=data; write_reg_01C(state);break;
	298	case    reg01E  : m_vidregs[reg01E]=data; write_reg_01E(state);break;
299	299
300		case    reg020  : state->m_vidregs[reg020]=data; break;
301		case    reg022  : state->m_vidregs[reg022]=data; break;
302		case    reg024  : state->m_vidregs[reg024]=data; break;
303		case    reg026  : state->m_vidregs[reg026]=data; write_reg_026(state); break;
304		case    reg028  : change_palette(space->machine(),0,data,reg028); break;
305		case    reg02A  : change_palette(space->machine(),1,data,reg02A); break;
306		case    reg02C  : change_palette(space->machine(),2,data,reg02C); break;
307		case    reg02E  : change_palette(space->machine(),3,data,reg02E); break;
	300	case    reg020  : m_vidregs[reg020]=data; break;
	301	case    reg022  : m_vidregs[reg022]=data; break;
	302	case    reg024  : m_vidregs[reg024]=data; break;
	303	case    reg026  : m_vidregs[reg026]=data; write_reg_026(state); break;
	304	case    reg028  : change_palette(machine(),0,data,reg028); break;
	305	case    reg02A  : change_palette(machine(),1,data,reg02A); break;
	306	case    reg02C  : change_palette(machine(),2,data,reg02C); break;
	307	case    reg02E  : change_palette(machine(),3,data,reg02E); break;
308	308
309	309	default         : break;
310	310	}

src/mess/video/odyssey2.c

r14963	r14964
142	142	}
143	143	}
144	144
145		READ8_HANDLER( odyssey2_video_r )
	145	READ8_MEMBER(odyssey2_state::odyssey2_video_r)
146	146	{
147		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
148	147	UINT8 data = 0;
149	148
150	149	switch (offset)
151	150	{
152	151	case 0xa1:
153		data = state->m_control_status;
154		state->m_iff = 0;
155		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
156		state->m_control_status &= ~ 0x08;
157		if ( space->machine().primary_screen->hpos() < I824X_START_ACTIVE_SCAN || space->machine().primary_screen->hpos() > I824X_END_ACTIVE_SCAN )
	152	data = m_control_status;
	153	m_iff = 0;
	154	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
	155	m_control_status &= ~ 0x08;
	156	if ( machine().primary_screen->hpos() < I824X_START_ACTIVE_SCAN || machine().primary_screen->hpos() > I824X_END_ACTIVE_SCAN )
158	157	{
159	158	data |= 1;
160	159	}
r14963	r14964
162	161	break;
163	162
164	163	case 0xa2:
165		data = state->m_collision_status;
166		state->m_collision_status = 0;
	164	data = m_collision_status;
	165	m_collision_status = 0;
167	166
168	167	break;
169	168
170	169	case 0xa4:
171	170
172		if ((state->m_o2_vdc.s.control & VDC_CONTROL_REG_STROBE_XY))
173		state->m_y_beam_pos = space->machine().primary_screen->vpos() - state->m_start_vpos;
	171	if ((m_o2_vdc.s.control & VDC_CONTROL_REG_STROBE_XY))
	172	m_y_beam_pos = machine().primary_screen->vpos() - m_start_vpos;
174	173
175		data = state->m_y_beam_pos;
	174	data = m_y_beam_pos;
176	175
177	176	break;
178	177
179	178
180	179	case 0xa5:
181	180
182		if ((state->m_o2_vdc.s.control & VDC_CONTROL_REG_STROBE_XY))
	181	if ((m_o2_vdc.s.control & VDC_CONTROL_REG_STROBE_XY))
183	182	{
184		state->m_x_beam_pos = space->machine().primary_screen->hpos();
185		if ( state->m_x_beam_pos < I824X_START_ACTIVE_SCAN )
	183	m_x_beam_pos = machine().primary_screen->hpos();
	184	if ( m_x_beam_pos < I824X_START_ACTIVE_SCAN )
186	185	{
187		state->m_x_beam_pos = state->m_x_beam_pos - I824X_START_ACTIVE_SCAN + I824X_LINE_CLOCKS;
	186	m_x_beam_pos = m_x_beam_pos - I824X_START_ACTIVE_SCAN + I824X_LINE_CLOCKS;
188	187	}
189	188	else
190	189	{
191		state->m_x_beam_pos = state->m_x_beam_pos - I824X_START_ACTIVE_SCAN;
	190	m_x_beam_pos = m_x_beam_pos - I824X_START_ACTIVE_SCAN;
192	191	}
193	192	}
194	193
195		data = state->m_x_beam_pos;
	194	data = m_x_beam_pos;
196	195
197	196	break;
198	197
199	198	default:
200		data = state->m_o2_vdc.reg[offset];
	199	data = m_o2_vdc.reg[offset];
201	200	}
202	201
203	202	return data;
204	203	}
205	204
206		WRITE8_HANDLER( odyssey2_video_w )
	205	WRITE8_MEMBER(odyssey2_state::odyssey2_video_w)
207	206	{
208		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
209	207	/* Update the sound */
210	208	if( offset >= 0xa7 && offset <= 0xaa )
211		state->m_sh_channel->update();
	209	m_sh_channel->update();
212	210
213	211	if (offset == 0xa0) {
214	212
215	213
216		if (    state->m_o2_vdc.s.control & VDC_CONTROL_REG_STROBE_XY
	214	if (    m_o2_vdc.s.control & VDC_CONTROL_REG_STROBE_XY
217	215	&& !(data & VDC_CONTROL_REG_STROBE_XY))
218	216	{
219	217	/* Toggling strobe bit, tuck away values */
220		state->m_x_beam_pos = space->machine().primary_screen->hpos();
221		if ( state->m_x_beam_pos < I824X_START_ACTIVE_SCAN )
	218	m_x_beam_pos = machine().primary_screen->hpos();
	219	if ( m_x_beam_pos < I824X_START_ACTIVE_SCAN )
222	220	{
223		state->m_x_beam_pos = state->m_x_beam_pos - I824X_START_ACTIVE_SCAN + 228;
	221	m_x_beam_pos = m_x_beam_pos - I824X_START_ACTIVE_SCAN + 228;
224	222	}
225	223	else
226	224	{
227		state->m_x_beam_pos = state->m_x_beam_pos - I824X_START_ACTIVE_SCAN;
	225	m_x_beam_pos = m_x_beam_pos - I824X_START_ACTIVE_SCAN;
228	226	}
229	227
230		state->m_y_beam_pos = space->machine().primary_screen->vpos() - state->m_start_vpos;
	228	m_y_beam_pos = machine().primary_screen->vpos() - m_start_vpos;
231	229	}
232	230	}
233	231
234		state->m_o2_vdc.reg[offset] = data;
	232	m_o2_vdc.reg[offset] = data;
235	233	}
236	234
237		WRITE8_HANDLER ( odyssey2_lum_w )
	235	WRITE8_MEMBER(odyssey2_state::odyssey2_lum_w)
238	236	{
239		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
240		state->m_lum = data;
	237	m_lum = data;
241	238	}
242	239
243		READ8_HANDLER( odyssey2_t1_r )
	240	READ8_MEMBER(odyssey2_state::odyssey2_t1_r)
244	241	{
245		odyssey2_state *state = space->machine().driver_data<odyssey2_state>();
246		if ( space->machine().primary_screen->vpos() > state->m_start_vpos && space->machine().primary_screen->vpos() < state->m_start_vblank )
	242	if ( machine().primary_screen->vpos() > m_start_vpos && machine().primary_screen->vpos() < m_start_vblank )
247	243	{
248		if ( space->machine().primary_screen->hpos() >= I824X_START_ACTIVE_SCAN && space->machine().primary_screen->hpos() < I824X_END_ACTIVE_SCAN )
	244	if ( machine().primary_screen->hpos() >= I824X_START_ACTIVE_SCAN && machine().primary_screen->hpos() < I824X_END_ACTIVE_SCAN )
249	245	{
250	246	return 1;
251	247	}

src/mess/video/pecom.c

r14963	r14964
12	12	#include "cpu/cosmac/cosmac.h"
13	13	#include "includes/pecom.h"
14	14
15		WRITE8_HANDLER( pecom_cdp1869_w )
	15	WRITE8_MEMBER(pecom_state::pecom_cdp1869_w)
16	16	{
17		pecom_state *state = space->machine().driver_data<pecom_state>();
18	17
19		UINT16 ma = state->m_cdp1802->get_memory_address();
	18	UINT16 ma = m_cdp1802->get_memory_address();
20	19
21	20	switch (offset + 3)
22	21	{
23	22	case 3:
24		state->m_cdp1869->out3_w(*space, ma, data);
	23	m_cdp1869->out3_w(space, ma, data);
25	24	break;
26	25
27	26	case 4:
28		state->m_cdp1869->out4_w(*space, ma, data);
	27	m_cdp1869->out4_w(space, ma, data);
29	28	break;
30	29
31	30	case 5:
32		state->m_cdp1869->out5_w(*space, ma, data);
	31	m_cdp1869->out5_w(space, ma, data);
33	32	break;
34	33
35	34	case 6:
36		state->m_cdp1869->out6_w(*space, ma, data);
	35	m_cdp1869->out6_w(space, ma, data);
37	36	break;
38	37
39	38	case 7:
40		state->m_cdp1869->out7_w(*space, ma, data);
	39	m_cdp1869->out7_w(space, ma, data);
41	40	break;
42	41	}
43	42	}

src/mess/video/bbc.c

r14963	r14964
107	107	}
108	108
109	109
110		WRITE8_HANDLER ( bbc_videoULA_w )
	110	WRITE8_MEMBER(bbc_state::bbc_videoULA_w)
111	111	{
112		bbc_state *state = space->machine().driver_data<bbc_state>();
113	112
114	113	// Make sure vpos is never <0 2008-10-11 PHS.
115		int vpos=space->machine().primary_screen->vpos();
	114	int vpos=machine().primary_screen->vpos();
116	115	if(vpos==0)
117		space->machine().primary_screen->update_partial(vpos);
	116	machine().primary_screen->update_partial(vpos);
118	117	else
119		space->machine().primary_screen->update_partial(vpos -1 );
	118	machine().primary_screen->update_partial(vpos -1 );
120	119
121		logerror("setting videoULA %.4x to:%.4x   at :%d \n",data,offset,space->machine().primary_screen->vpos() );
	120	logerror("setting videoULA %.4x to:%.4x   at :%d \n",data,offset,machine().primary_screen->vpos() );
122	121
123	122
124	123	switch (offset&0x01)
r14963	r14964
126	125	// Set the control register in the Video ULA
127	126	case 0:
128	127	{
129		state->m_videoULA_Reg=data;
130		state->m_videoULA_master_cursor_size=    (state->m_videoULA_Reg>>7)&0x01;
131		state->m_videoULA_width_of_cursor=       (state->m_videoULA_Reg>>5)&0x03;
132		state->m_videoULA_6845_clock_rate=       (state->m_videoULA_Reg>>4)&0x01;
133		state->m_videoULA_characters_per_line=   (state->m_videoULA_Reg>>2)&0x03;
134		state->m_videoULA_teletext_normal_select=(state->m_videoULA_Reg>>1)&0x01;
135		state->m_videoULA_flash_colour_select=    state->m_videoULA_Reg    &0x01;
	128	m_videoULA_Reg=data;
	129	m_videoULA_master_cursor_size=    (m_videoULA_Reg>>7)&0x01;
	130	m_videoULA_width_of_cursor=       (m_videoULA_Reg>>5)&0x03;
	131	m_videoULA_6845_clock_rate=       (m_videoULA_Reg>>4)&0x01;
	132	m_videoULA_characters_per_line=   (m_videoULA_Reg>>2)&0x03;
	133	m_videoULA_teletext_normal_select=(m_videoULA_Reg>>1)&0x01;
	134	m_videoULA_flash_colour_select=    m_videoULA_Reg    &0x01;
136	135
137		state->m_videoULA_pallet_lookup=state->m_videoULA_flash_colour_select?state->m_videoULA_pallet0:state->m_videoULA_pallet1;
	136	m_videoULA_pallet_lookup=m_videoULA_flash_colour_select?m_videoULA_pallet0:m_videoULA_pallet1;
138	137
139		state->m_emulation_cursor_size=width_of_cursor_set[state->m_videoULA_width_of_cursor|(state->m_videoULA_master_cursor_size<<2)];
	138	m_emulation_cursor_size=width_of_cursor_set[m_videoULA_width_of_cursor|(m_videoULA_master_cursor_size<<2)];
140	139
141	140	// this is the number of BBC pixels held in each byte
142		if (state->m_videoULA_teletext_normal_select)
	141	if (m_videoULA_teletext_normal_select)
143	142	{
144		state->m_pixels_per_byte=6;
	143	m_pixels_per_byte=6;
145	144	} else {
146		state->m_pixels_per_byte=pixels_per_byte_set[state->m_videoULA_characters_per_line|(state->m_videoULA_6845_clock_rate<<2)];
	145	m_pixels_per_byte=pixels_per_byte_set[m_videoULA_characters_per_line|(m_videoULA_6845_clock_rate<<2)];
147	146	}
148		mc6845_device *mc6845 = state->machine().device<mc6845_device>("mc6845");
149		mc6845->set_hpixels_per_column(state->m_pixels_per_byte);
150		if (state->m_videoULA_6845_clock_rate)
	147	mc6845_device *mc6845 = machine().device<mc6845_device>("mc6845");
	148	mc6845->set_hpixels_per_column(m_pixels_per_byte);
	149	if (m_videoULA_6845_clock_rate)
151	150	mc6845->set_clock(2000000);
152	151	else
153	152	mc6845->set_clock(1000000);
r14963	r14964
157	156	case 1:
158	157	int tpal=(data>>4)&0x0f;
159	158	int tcol=data&0x0f;
160		state->m_videoULA_pallet0[tpal]=tcol;
161		state->m_videoULA_pallet1[tpal]=tcol<8?tcol:tcol^7;
	159	m_videoULA_pallet0[tpal]=tcol;
	160	m_videoULA_pallet1[tpal]=tcol<8?tcol:tcol^7;
162	161	break;
163	162	}
164	163	}
r14963	r14964
302	301	* memory interface to BBC's 6845
303	302	************************************************************************/
304	303
305		WRITE8_HANDLER ( bbc_6845_w )
	304	WRITE8_MEMBER(bbc_state::bbc_6845_w)
306	305	{
307		mc6845_device *mc6845 = space->machine().device<mc6845_device>("mc6845");
	306	mc6845_device *mc6845 = machine().device<mc6845_device>("mc6845");
308	307	switch(offset & 1)
309	308	{
310	309	case 0 :
311		mc6845->address_w(*space,0,data);
	310	mc6845->address_w(space,0,data);
312	311	break;
313	312	case 1 :
314		mc6845->register_w(*space,0,data);
	313	mc6845->register_w(space,0,data);
315	314	break;
316	315	}
317	316	return;
318	317	}
319	318
320		READ8_HANDLER (bbc_6845_r)
	319	READ8_MEMBER(bbc_state::bbc_6845_r)
321	320	{
322	321
323		mc6845_device *mc6845 = space->machine().device<mc6845_device>("mc6845");
	322	mc6845_device *mc6845 = machine().device<mc6845_device>("mc6845");
324	323
325	324	switch (offset&1)
326	325	{
327		case 0: return mc6845->status_r(*space,0); break;
328		case 1: return mc6845->register_r(*space,0); break;
	326	case 0: return mc6845->status_r(space,0); break;
	327	case 1: return mc6845->register_r(space,0); break;
329	328	}
330	329	return 0;
331	330	}
r14963	r14964
581	580
582	581
583	582
584		WRITE8_HANDLER ( bbc_6845_w )
	583	WRITE8_MEMBER(bbc_state::bbc_6845_w)
585	584	{
586		mc6845_device *mc6845 = space->machine().device<mc6845_device>("mc6845");
	585	mc6845_device *mc6845 = machine().device<mc6845_device>("mc6845");
587	586	switch(offset & 1)
588	587	{
589	588	case 0 :
590		mc6845->address_w(*space,0,data);
	589	mc6845->address_w(space,0,data);
591	590	break;
592	591	case 1 :
593		mc6845->register_w(*space,0,data);
	592	mc6845->register_w(space,0,data);
594	593	break;
595	594	}
596	595	return;

src/mess/video/fm7.c

r14963	r14964
20	20	*   bit 6: Sub-CPU cancel IRQ
21	21	*/
22	22
23		READ8_HANDLER( fm7_subintf_r )
	23	READ8_MEMBER(fm7_state::fm7_subintf_r)
24	24	{
25		fm7_state *state = space->machine().driver_data<fm7_state>();
26	25	UINT8 ret = 0x00;
27	26
28		if(state->m_video.sub_busy != 0 || state->m_video.sub_halt != 0)
	27	if(m_video.sub_busy != 0 || m_video.sub_halt != 0)
29	28	ret |= 0x80;
30	29
31	30	ret |= 0x7e;
r14963	r14964
34	33	return ret;
35	34	}
36	35
37		WRITE8_HANDLER( fm7_subintf_w )
	36	WRITE8_MEMBER(fm7_state::fm7_subintf_w)
38	37	{
39		fm7_state *state = space->machine().driver_data<fm7_state>();
40		state->m_video.sub_halt = data & 0x80;
	38	m_video.sub_halt = data & 0x80;
41	39	if(data & 0x80)
42		state->m_video.sub_busy = data & 0x80;
	40	m_video.sub_busy = data & 0x80;
43	41
44		cputag_set_input_line(space->machine(),"sub",INPUT_LINE_HALT,(data & 0x80) ? ASSERT_LINE : CLEAR_LINE);
	42	cputag_set_input_line(machine(),"sub",INPUT_LINE_HALT,(data & 0x80) ? ASSERT_LINE : CLEAR_LINE);
45	43	if(data & 0x40)
46		cputag_set_input_line(space->machine(),"sub",M6809_IRQ_LINE,ASSERT_LINE);
	44	cputag_set_input_line(machine(),"sub",M6809_IRQ_LINE,ASSERT_LINE);
47	45	//popmessage("Sub CPU Interface write: %02x\n",data);
48	46	}
49	47
50		READ8_HANDLER( fm7_sub_busyflag_r )
	48	READ8_MEMBER(fm7_state::fm7_sub_busyflag_r)
51	49	{
52		fm7_state *state = space->machine().driver_data<fm7_state>();
53		if(state->m_video.sub_halt == 0)
54		state->m_video.sub_busy = 0x00;
	50	if(m_video.sub_halt == 0)
	51	m_video.sub_busy = 0x00;
55	52	return 0x00;
56	53	}
57	54
58		WRITE8_HANDLER( fm7_sub_busyflag_w )
	55	WRITE8_MEMBER(fm7_state::fm7_sub_busyflag_w)
59	56	{
60		fm7_state *state = space->machine().driver_data<fm7_state>();
61		state->m_video.sub_busy = 0x80;
	57	m_video.sub_busy = 0x80;
62	58	}
63	59
64	60	/*
65	61	* Sub-CPU port 0xd402
66	62	*   Read-only: Acknowledge Cancel IRQ
67	63	*/
68		READ8_HANDLER( fm7_cancel_ack )
	64	READ8_MEMBER(fm7_state::fm7_cancel_ack)
69	65	{
70		cputag_set_input_line(space->machine(),"sub",M6809_IRQ_LINE,CLEAR_LINE);
	66	cputag_set_input_line(machine(),"sub",M6809_IRQ_LINE,CLEAR_LINE);
71	67	return 0x00;
72	68	}
73	69
74	70	/*
75	71	* Reading from 0xd404 (sub-CPU) causes an "Attention" FIRQ on the main CPU
76	72	*/
77		READ8_HANDLER( fm7_attn_irq_r )
	73	READ8_MEMBER(fm7_state::fm7_attn_irq_r)
78	74	{
79		fm7_state *state = space->machine().driver_data<fm7_state>();
80		state->m_video.attn_irq = 1;
81		cputag_set_input_line(space->machine(),"maincpu",M6809_FIRQ_LINE,ASSERT_LINE);
	75	m_video.attn_irq = 1;
	76	cputag_set_input_line(machine(),"maincpu",M6809_FIRQ_LINE,ASSERT_LINE);
82	77	return 0xff;
83	78	}
84	79
r14963	r14964
88	83	*  On read, enables VRAM access
89	84	*  On write, disables VRAM access
90	85	*/
91		READ8_HANDLER( fm7_vram_access_r )
	86	READ8_MEMBER(fm7_state::fm7_vram_access_r)
92	87	{
93		fm7_state *state = space->machine().driver_data<fm7_state>();
94		state->m_video.vram_access = 1;
	88	m_video.vram_access = 1;
95	89	return 0xff;
96	90	}
97	91
98		WRITE8_HANDLER( fm7_vram_access_w )
	92	WRITE8_MEMBER(fm7_state::fm7_vram_access_w)
99	93	{
100		fm7_state *state = space->machine().driver_data<fm7_state>();
101		state->m_video.vram_access = 0;
	94	m_video.vram_access = 0;
102	95	}
103	96
104	97	static TIMER_CALLBACK( fm77av_alu_task_end )
r14963	r14964
638	631	machine.scheduler().timer_set(attotime::from_usec(byte_count/16), FUNC(fm77av_alu_task_end));
639	632	}
640	633
641		READ8_HANDLER( fm7_vram_r )
	634	READ8_MEMBER(fm7_state::fm7_vram_r)
642	635	{
643		fm7_state *state = space->machine().driver_data<fm7_state>();
644	636	int offs;
645	637	UINT16 page = 0x0000;
646	638
647		if(state->m_video.active_video_page != 0)
	639	if(m_video.active_video_page != 0)
648	640	page = 0xc000;
649	641
650		if(offset < 0x4000 && (state->m_video.multi_page & 0x01))
	642	if(offset < 0x4000 && (m_video.multi_page & 0x01))
651	643	return 0xff;
652		if((offset < 0x8000 && offset >=0x4000) && (state->m_video.multi_page & 0x02))
	644	if((offset < 0x8000 && offset >=0x4000) && (m_video.multi_page & 0x02))
653	645	return 0xff;
654		if((offset < 0xc000 && offset >=0x8000) && (state->m_video.multi_page & 0x04))
	646	if((offset < 0xc000 && offset >=0x8000) && (m_video.multi_page & 0x04))
655	647	return 0xff;
656	648
657		if(state->m_alu.command & 0x80) // ALU active, writes to VRAM even when reading it (go figure)
	649	if(m_alu.command & 0x80) // ALU active, writes to VRAM even when reading it (go figure)
658	650	{
	651	fm7_state *state = machine().driver_data<fm7_state>();
659	652	fm7_alu_function(state, offset+page);
660	653	}
661	654
662		if(state->m_video.modestatus & 0x40)
	655	if(m_video.modestatus & 0x40)
663	656	{
664		if(state->m_video.active_video_page != 0)
665		offs = (offset & 0xe000) | ((offset + state->m_video.vram_offset2) & 0x1fff);
	657	if(m_video.active_video_page != 0)
	658	offs = (offset & 0xe000) | ((offset + m_video.vram_offset2) & 0x1fff);
666	659	else
667		offs = (offset & 0xe000) | ((offset + state->m_video.vram_offset) & 0x1fff);
	660	offs = (offset & 0xe000) | ((offset + m_video.vram_offset) & 0x1fff);
668	661	}
669	662	else
670	663	{
671		if(state->m_video.active_video_page != 0)
672		offs = (offset & 0xc000) | ((offset + state->m_video.vram_offset2) & 0x3fff);
	664	if(m_video.active_video_page != 0)
	665	offs = (offset & 0xc000) | ((offset + m_video.vram_offset2) & 0x3fff);
673	666	else
674		offs = (offset & 0xc000) | ((offset + state->m_video.vram_offset) & 0x3fff);
	667	offs = (offset & 0xc000) | ((offset + m_video.vram_offset) & 0x3fff);
675	668	}
676		return state->m_video_ram[offs + page];
	669	return m_video_ram[offs + page];
677	670	}
678	671
679		WRITE8_HANDLER( fm7_vram_w )
	672	WRITE8_MEMBER(fm7_state::fm7_vram_w)
680	673	{
681		fm7_state *state = space->machine().driver_data<fm7_state>();
682	674	int offs;
683	675	UINT16 page = 0x0000;
684	676
685		if(state->m_video.active_video_page != 0)
	677	if(m_video.active_video_page != 0)
686	678	page = 0xc000;
687	679
688		if(offset < 0x4000 && (state->m_video.multi_page & 0x01))
	680	if(offset < 0x4000 && (m_video.multi_page & 0x01))
689	681	return;
690		if((offset < 0x8000 && offset >=0x4000) && (state->m_video.multi_page & 0x02))
	682	if((offset < 0x8000 && offset >=0x4000) && (m_video.multi_page & 0x02))
691	683	return;
692		if((offset < 0xc000 && offset >=0x8000) && (state->m_video.multi_page & 0x04))
	684	if((offset < 0xc000 && offset >=0x8000) && (m_video.multi_page & 0x04))
693	685	return;
694	686
695		if(state->m_alu.command & 0x80) // ALU active
	687	if(m_alu.command & 0x80) // ALU active
696	688	{
	689	fm7_state *state = machine().driver_data<fm7_state>();
697	690	fm7_alu_function(state, offset+page);
698	691	return;
699	692	}
700	693
701		if(state->m_video.modestatus & 0x40)
	694	if(m_video.modestatus & 0x40)
702	695	{
703		if(state->m_video.active_video_page != 0)
704		offs = (offset & 0xe000) | ((offset + state->m_video.vram_offset2) & 0x1fff);
	696	if(m_video.active_video_page != 0)
	697	offs = (offset & 0xe000) | ((offset + m_video.vram_offset2) & 0x1fff);
705	698	else
706		offs = (offset & 0xe000) | ((offset + state->m_video.vram_offset) & 0x1fff);
	699	offs = (offset & 0xe000) | ((offset + m_video.vram_offset) & 0x1fff);
707	700	}
708	701	else
709	702	{
710		if(state->m_video.active_video_page != 0)
711		offs = (offset & 0xc000) | ((offset + state->m_video.vram_offset2) & 0x3fff);
	703	if(m_video.active_video_page != 0)
	704	offs = (offset & 0xc000) | ((offset + m_video.vram_offset2) & 0x3fff);
712	705	else
713		offs = (offset & 0xc000) | ((offset + state->m_video.vram_offset) & 0x3fff);
	706	offs = (offset & 0xc000) | ((offset + m_video.vram_offset) & 0x3fff);
714	707	}
715		//  if(state->m_video.vram_access != 0)
716		state->m_video_ram[offs+page] = data;
	708	//  if(m_video.vram_access != 0)
	709	m_video_ram[offs+page] = data;
717	710	}
718	711
719	712	// not pretty, but it should work.
720		static WRITE8_HANDLER( fm7_vram_banked_w )
	713	WRITE8_MEMBER(fm7_state::fm7_vram_banked_w)
721	714	{
722		fm7_state *state = space->machine().driver_data<fm7_state>();
723	715	int offs;
724	716	UINT16 page = 0x0000;
725	717
726		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	718	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
727	719	return;
728	720
729		if(state->m_video.active_video_page != 0)
	721	if(m_video.active_video_page != 0)
730	722	page = 0xc000;
731	723
732		if(offset < 0x4000 && (state->m_video.multi_page & 0x01))
	724	if(offset < 0x4000 && (m_video.multi_page & 0x01))
733	725	return;
734		if((offset < 0x8000 && offset >=0x4000) && (state->m_video.multi_page & 0x02))
	726	if((offset < 0x8000 && offset >=0x4000) && (m_video.multi_page & 0x02))
735	727	return;
736		if((offset < 0xc000 && offset >=0x8000) && (state->m_video.multi_page & 0x04))
	728	if((offset < 0xc000 && offset >=0x8000) && (m_video.multi_page & 0x04))
737	729	return;
738	730
739		if(state->m_alu.command & 0x80) // ALU active
	731	if(m_alu.command & 0x80) // ALU active
740	732	{
	733	fm7_state *state = machine().driver_data<fm7_state>();
741	734	fm7_alu_function(state, offset+page);
742	735	return;
743	736	}
744	737
745		if(state->m_video.modestatus & 0x40)
	738	if(m_video.modestatus & 0x40)
746	739	{
747		if(state->m_video.active_video_page != 0)
748		offs = (offset & 0xe000) | ((offset + state->m_video.vram_offset2) & 0x1fff);
	740	if(m_video.active_video_page != 0)
	741	offs = (offset & 0xe000) | ((offset + m_video.vram_offset2) & 0x1fff);
749	742	else
750		offs = (offset & 0xe000) | ((offset + state->m_video.vram_offset) & 0x1fff);
	743	offs = (offset & 0xe000) | ((offset + m_video.vram_offset) & 0x1fff);
751	744	}
752	745	else
753	746	{
754		if(state->m_video.active_video_page != 0)
755		offs = (offset & 0xc000) | ((offset + state->m_video.vram_offset2) & 0x3fff);
	747	if(m_video.active_video_page != 0)
	748	offs = (offset & 0xc000) | ((offset + m_video.vram_offset2) & 0x3fff);
756	749	else
757		offs = (offset & 0xc000) | ((offset + state->m_video.vram_offset) & 0x3fff);
	750	offs = (offset & 0xc000) | ((offset + m_video.vram_offset) & 0x3fff);
758	751	}
759		state->m_video_ram[offs+page] = data;
	752	m_video_ram[offs+page] = data;
760	753	}
761	754
762		READ8_HANDLER( fm7_vram0_r )
	755	READ8_MEMBER(fm7_state::fm7_vram0_r)
763	756	{
764		fm7_state *state = space->machine().driver_data<fm7_state>();
765		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	757	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
766	758	return 0xff;
767	759	return fm7_vram_r(space,offset);
768	760	}
769	761
770		READ8_HANDLER( fm7_vram1_r )
	762	READ8_MEMBER(fm7_state::fm7_vram1_r)
771	763	{
772		fm7_state *state = space->machine().driver_data<fm7_state>();
773		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	764	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
774	765	return 0xff;
775	766	return fm7_vram_r(space,offset+0x1000);
776	767	}
777	768
778		READ8_HANDLER( fm7_vram2_r )
	769	READ8_MEMBER(fm7_state::fm7_vram2_r)
779	770	{
780		fm7_state *state = space->machine().driver_data<fm7_state>();
781		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	771	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
782	772	return 0xff;
783	773	return fm7_vram_r(space,offset+0x2000);
784	774	}
785	775
786		READ8_HANDLER( fm7_vram3_r )
	776	READ8_MEMBER(fm7_state::fm7_vram3_r)
787	777	{
788		fm7_state *state = space->machine().driver_data<fm7_state>();
789		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	778	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
790	779	return 0xff;
791	780	return fm7_vram_r(space,offset+0x3000);
792	781	}
793	782
794		READ8_HANDLER( fm7_vram4_r )
	783	READ8_MEMBER(fm7_state::fm7_vram4_r)
795	784	{
796		fm7_state *state = space->machine().driver_data<fm7_state>();
797		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	785	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
798	786	return 0xff;
799	787	return fm7_vram_r(space,offset+0x4000);
800	788	}
801	789
802		READ8_HANDLER( fm7_vram5_r )
	790	READ8_MEMBER(fm7_state::fm7_vram5_r)
803	791	{
804		fm7_state *state = space->machine().driver_data<fm7_state>();
805		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	792	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
806	793	return 0xff;
807	794	return fm7_vram_r(space,offset+0x5000);
808	795	}
809	796
810		READ8_HANDLER( fm7_vram6_r )
	797	READ8_MEMBER(fm7_state::fm7_vram6_r)
811	798	{
812		fm7_state *state = space->machine().driver_data<fm7_state>();
813		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	799	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
814	800	return 0xff;
815	801	return fm7_vram_r(space,offset+0x6000);
816	802	}
817	803
818		READ8_HANDLER( fm7_vram7_r )
	804	READ8_MEMBER(fm7_state::fm7_vram7_r)
819	805	{
820		fm7_state *state = space->machine().driver_data<fm7_state>();
821		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	806	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
822	807	return 0xff;
823	808	return fm7_vram_r(space,offset+0x7000);
824	809	}
825	810
826		READ8_HANDLER( fm7_vram8_r )
	811	READ8_MEMBER(fm7_state::fm7_vram8_r)
827	812	{
828		fm7_state *state = space->machine().driver_data<fm7_state>();
829		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	813	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
830	814	return 0xff;
831	815	return fm7_vram_r(space,offset+0x8000);
832	816	}
833	817
834		READ8_HANDLER( fm7_vram9_r )
	818	READ8_MEMBER(fm7_state::fm7_vram9_r)
835	819	{
836		fm7_state *state = space->machine().driver_data<fm7_state>();
837		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	820	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
838	821	return 0xff;
839	822	return fm7_vram_r(space,offset+0x9000);
840	823	}
841	824
842		READ8_HANDLER( fm7_vramA_r )
	825	READ8_MEMBER(fm7_state::fm7_vramA_r)
843	826	{
844		fm7_state *state = space->machine().driver_data<fm7_state>();
845		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	827	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
846	828	return 0xff;
847	829	return fm7_vram_r(space,offset+0xa000);
848	830	}
849	831
850		READ8_HANDLER( fm7_vramB_r )
	832	READ8_MEMBER(fm7_state::fm7_vramB_r)
851	833	{
852		fm7_state *state = space->machine().driver_data<fm7_state>();
853		if(!state->m_video.sub_halt)  // no access if sub CPU is not halted.
	834	if(!m_video.sub_halt)  // no access if sub CPU is not halted.
854	835	return 0xff;
855	836	return fm7_vram_r(space,offset+0xb000);
856	837	}
857	838
858		WRITE8_HANDLER( fm7_vram0_w )
	839	WRITE8_MEMBER(fm7_state::fm7_vram0_w)
859	840	{
860	841	fm7_vram_banked_w(space,offset,data);
861	842	}
862	843
863		WRITE8_HANDLER( fm7_vram1_w )
	844	WRITE8_MEMBER(fm7_state::fm7_vram1_w)
864	845	{
865	846	fm7_vram_banked_w(space,offset+0x1000,data);
866	847	}
867	848
868		WRITE8_HANDLER( fm7_vram2_w )
	849	WRITE8_MEMBER(fm7_state::fm7_vram2_w)
869	850	{
870	851	fm7_vram_banked_w(space,offset+0x2000,data);
871	852	}
872	853
873		WRITE8_HANDLER( fm7_vram3_w )
	854	WRITE8_MEMBER(fm7_state::fm7_vram3_w)
874	855	{
875	856	fm7_vram_banked_w(space,offset+0x3000,data);
876	857	}
877	858
878		WRITE8_HANDLER( fm7_vram4_w )
	859	WRITE8_MEMBER(fm7_state::fm7_vram4_w)
879	860	{
880	861	fm7_vram_banked_w(space,offset+0x4000,data);
881	862	}
882	863
883		WRITE8_HANDLER( fm7_vram5_w )
	864	WRITE8_MEMBER(fm7_state::fm7_vram5_w)
884	865	{
885	866	fm7_vram_banked_w(space,offset+0x5000,data);
886	867	}
887	868
888		WRITE8_HANDLER( fm7_vram6_w )
	869	WRITE8_MEMBER(fm7_state::fm7_vram6_w)
889	870	{
890	871	fm7_vram_banked_w(space,offset+0x6000,data);
891	872	}
892	873
893		WRITE8_HANDLER( fm7_vram7_w )
	874	WRITE8_MEMBER(fm7_state::fm7_vram7_w)
894	875	{
895	876	fm7_vram_banked_w(space,offset+0x7000,data);
896	877	}
897	878
898		WRITE8_HANDLER( fm7_vram8_w )
	879	WRITE8_MEMBER(fm7_state::fm7_vram8_w)
899	880	{
900	881	fm7_vram_banked_w(space,offset+0x8000,data);
901	882	}
902	883
903		WRITE8_HANDLER( fm7_vram9_w )
	884	WRITE8_MEMBER(fm7_state::fm7_vram9_w)
904	885	{
905	886	fm7_vram_banked_w(space,offset+0x9000,data);
906	887	}
907	888
908		WRITE8_HANDLER( fm7_vramA_w )
	889	WRITE8_MEMBER(fm7_state::fm7_vramA_w)
909	890	{
910	891	fm7_vram_banked_w(space,offset+0xa000,data);
911	892	}
912	893
913		WRITE8_HANDLER( fm7_vramB_w )
	894	WRITE8_MEMBER(fm7_state::fm7_vramB_w)
914	895	{
915	896	fm7_vram_banked_w(space,offset+0xb000,data);
916	897	}
r14963	r14964
921	902	*  On read, enables the CRT display
922	903	*  On write, disables the CRT display
923	904	*/
924		READ8_HANDLER( fm7_crt_r )
	905	READ8_MEMBER(fm7_state::fm7_crt_r)
925	906	{
926		fm7_state *state = space->machine().driver_data<fm7_state>();
927		state->m_video.crt_enable = 1;
	907	m_video.crt_enable = 1;
928	908	return 0xff;
929	909	}
930	910
931		WRITE8_HANDLER( fm7_crt_w )
	911	WRITE8_MEMBER(fm7_state::fm7_crt_w)
932	912	{
933		fm7_state *state = space->machine().driver_data<fm7_state>();
934		state->m_video.crt_enable = 0;
	913	m_video.crt_enable = 0;
935	914	}
936	915
937	916	/*
r14963	r14964
940	919	*  0xd40e: bits 0-6 - offset in bytes (high byte) (bit 6 is used for 400 line video only)
941	920	*  0xd40f: bits 0-7 - offset in bytes (low byte)
942	921	*/
943		WRITE8_HANDLER( fm7_vram_offset_w )
	922	WRITE8_MEMBER(fm7_state::fm7_vram_offset_w)
944	923	{
945		fm7_state *state = space->machine().driver_data<fm7_state>();
946	924	UINT16 new_offset = 0;
947	925
948	926	switch(offset)
949	927	{
950	928	case 0:
951		if(state->m_video.active_video_page != 0)
952		new_offset = ((data & 0x3f) << 8) | (state->m_video.vram_offset2 & 0x00ff);
	929	if(m_video.active_video_page != 0)
	930	new_offset = ((data & 0x3f) << 8) | (m_video.vram_offset2 & 0x00ff);
953	931	else
954		new_offset = ((data & 0x3f) << 8) | (state->m_video.vram_offset & 0x00ff);
	932	new_offset = ((data & 0x3f) << 8) | (m_video.vram_offset & 0x00ff);
955	933	break;
956	934	case 1:  // low 5 bits are used on FM-77AV and later only
957		if(state->m_type == SYS_FM7)
958		new_offset = (state->m_video.vram_offset & 0xff00) | (data & 0xe0);
	935	if(m_type == SYS_FM7)
	936	new_offset = (m_video.vram_offset & 0xff00) | (data & 0xe0);
959	937	else
960	938	{
961		if(state->m_video.active_video_page != 0)
	939	if(m_video.active_video_page != 0)
962	940	{
963		if(state->m_video.fine_offset != 0)
964		new_offset = (state->m_video.vram_offset2 & 0xff00) | (data & 0xff);
	941	if(m_video.fine_offset != 0)
	942	new_offset = (m_video.vram_offset2 & 0xff00) | (data & 0xff);
965	943	else
966		new_offset = (state->m_video.vram_offset2 & 0xff00) | (data & 0xe0);
	944	new_offset = (m_video.vram_offset2 & 0xff00) | (data & 0xe0);
967	945	}
968	946	else
969	947	{
970		if(state->m_video.fine_offset != 0)
971		new_offset = (state->m_video.vram_offset & 0xff00) | (data & 0xff);
	948	if(m_video.fine_offset != 0)
	949	new_offset = (m_video.vram_offset & 0xff00) | (data & 0xff);
972	950	else
973		new_offset = (state->m_video.vram_offset & 0xff00) | (data & 0xe0);
	951	new_offset = (m_video.vram_offset & 0xff00) | (data & 0xe0);
974	952	}
975	953	}
976	954	break;
977	955	}
978		if(state->m_video.active_video_page != 0)
979		state->m_video.vram_offset2 = new_offset;
	956	if(m_video.active_video_page != 0)
	957	m_video.vram_offset2 = new_offset;
980	958	else
981		state->m_video.vram_offset = new_offset;
	959	m_video.vram_offset = new_offset;
982	960	}
983	961
984	962	/*
r14963	r14964
989	967	*  bits 6-4: VRAM planes to display (G,R,B) (1=disable)
990	968	*  bits 2-0: VRAM CPU access (G,R,B) (1=disable)
991	969	*/
992		WRITE8_HANDLER( fm7_multipage_w )
	970	WRITE8_MEMBER(fm7_state::fm7_multipage_w)
993	971	{
994		fm7_state *state = space->machine().driver_data<fm7_state>();
995		state->m_video.multi_page = data & 0x77;
	972	m_video.multi_page = data & 0x77;
996	973	}
997	974
998	975	/*
r14963	r14964
1003	980	*  bit 1 = Red
1004	981	*  bit 0 = Blue
1005	982	*/
1006		READ8_HANDLER( fm7_palette_r )
	983	READ8_MEMBER(fm7_state::fm7_palette_r)
1007	984	{
1008		fm7_state *state = space->machine().driver_data<fm7_state>();
1009		return state->m_video.fm7_pal[offset];
	985	return m_video.fm7_pal[offset];
1010	986	}
1011	987
1012		WRITE8_HANDLER( fm7_palette_w )
	988	WRITE8_MEMBER(fm7_state::fm7_palette_w)
1013	989	{
1014		fm7_state *state = space->machine().driver_data<fm7_state>();
1015	990	UINT8 r = 0,g = 0,b = 0;
1016	991
1017	992	if(data & 0x04)
r14963	r14964
1021	996	if(data & 0x01)
1022	997	b = 0xff;
1023	998
1024		palette_set_color(space->machine(),offset,MAKE_RGB(r,g,b));
1025		state->m_video.fm7_pal[offset] = data & 0x07;
	999	palette_set_color(machine(),offset,MAKE_RGB(r,g,b));
	1000	m_video.fm7_pal[offset] = data & 0x07;
1026	1001	}
1027	1002
1028	1003	/*
r14963	r14964
1036	1011	*  fd33: red level (4 bits)
1037	1012	*  fd34: green level (4 bits)
1038	1013	*/
1039		WRITE8_HANDLER( fm77av_analog_palette_w )
	1014	WRITE8_MEMBER(fm7_state::fm77av_analog_palette_w)
1040	1015	{
1041		fm7_state *state = space->machine().driver_data<fm7_state>();
1042	1016	int val;
1043	1017
1044	1018	switch(offset)
1045	1019	{
1046	1020	case 0:
1047		val = ((data & 0x0f) << 8) | (state->m_video.fm77av_pal_selected & 0x00ff);
1048		state->m_video.fm77av_pal_selected = val;
	1021	val = ((data & 0x0f) << 8) | (m_video.fm77av_pal_selected & 0x00ff);
	1022	m_video.fm77av_pal_selected = val;
1049	1023	break;
1050	1024	case 1:
1051		val = data | (state->m_video.fm77av_pal_selected & 0x0f00);
1052		state->m_video.fm77av_pal_selected = val;
	1025	val = data | (m_video.fm77av_pal_selected & 0x0f00);
	1026	m_video.fm77av_pal_selected = val;
1053	1027	break;
1054	1028	case 2:
1055		state->m_video.fm77av_pal_b[state->m_video.fm77av_pal_selected] = (data & 0x0f) << 4;
1056		palette_set_color(space->machine(),state->m_video.fm77av_pal_selected+8,
1057		MAKE_RGB(state->m_video.fm77av_pal_r[state->m_video.fm77av_pal_selected],
1058		state->m_video.fm77av_pal_g[state->m_video.fm77av_pal_selected],
1059		state->m_video.fm77av_pal_b[state->m_video.fm77av_pal_selected]));
	1029	m_video.fm77av_pal_b[m_video.fm77av_pal_selected] = (data & 0x0f) << 4;
	1030	palette_set_color(machine(),m_video.fm77av_pal_selected+8,
	1031	MAKE_RGB(m_video.fm77av_pal_r[m_video.fm77av_pal_selected],
	1032	m_video.fm77av_pal_g[m_video.fm77av_pal_selected],
	1033	m_video.fm77av_pal_b[m_video.fm77av_pal_selected]));
1060	1034	break;
1061	1035	case 3:
1062		state->m_video.fm77av_pal_r[state->m_video.fm77av_pal_selected] = (data & 0x0f) << 4;
1063		palette_set_color(space->machine(),state->m_video.fm77av_pal_selected+8,
1064		MAKE_RGB(state->m_video.fm77av_pal_r[state->m_video.fm77av_pal_selected],
1065		state->m_video.fm77av_pal_g[state->m_video.fm77av_pal_selected],
1066		state->m_video.fm77av_pal_b[state->m_video.fm77av_pal_selected]));
	1036	m_video.fm77av_pal_r[m_video.fm77av_pal_selected] = (data & 0x0f) << 4;
	1037	palette_set_color(machine(),m_video.fm77av_pal_selected+8,
	1038	MAKE_RGB(m_video.fm77av_pal_r[m_video.fm77av_pal_selected],
	1039	m_video.fm77av_pal_g[m_video.fm77av_pal_selected],
	1040	m_video.fm77av_pal_b[m_video.fm77av_pal_selected]));
1067	1041	break;
1068	1042	case 4:
1069		state->m_video.fm77av_pal_g[state->m_video.fm77av_pal_selected] = (data & 0x0f) << 4;
1070		palette_set_color(space->machine(),state->m_video.fm77av_pal_selected+8,
1071		MAKE_RGB(state->m_video.fm77av_pal_r[state->m_video.fm77av_pal_selected],
1072		state->m_video.fm77av_pal_g[state->m_video.fm77av_pal_selected],
1073		state->m_video.fm77av_pal_b[state->m_video.fm77av_pal_selected]));
	1043	m_video.fm77av_pal_g[m_video.fm77av_pal_selected] = (data & 0x0f) << 4;
	1044	palette_set_color(machine(),m_video.fm77av_pal_selected+8,
	1045	MAKE_RGB(m_video.fm77av_pal_r[m_video.fm77av_pal_selected],
	1046	m_video.fm77av_pal_g[m_video.fm77av_pal_selected],
	1047	m_video.fm77av_pal_b[m_video.fm77av_pal_selected]));
1074	1048	break;
1075	1049	}
1076	1050	}
r14963	r14964
1090	1064	*             bit 6 - display VRAM page
1091	1065	*             bit 7 - NMI mask register (1=mask)
1092	1066	*/
1093		READ8_HANDLER( fm77av_video_flags_r )
	1067	READ8_MEMBER(fm7_state::fm77av_video_flags_r)
1094	1068	{
1095		fm7_state *state = space->machine().driver_data<fm7_state>();
1096	1069	UINT8 ret = 0xff;
1097	1070
1098		if(space->machine().primary_screen->vblank())
	1071	if(machine().primary_screen->vblank())
1099	1072	ret &= ~0x80;
1100	1073
1101		if(state->m_alu.busy != 0)
	1074	if(m_alu.busy != 0)
1102	1075	ret &= ~0x10;
1103	1076
1104		if(state->m_video.vsync_flag == 0)
	1077	if(m_video.vsync_flag == 0)
1105	1078	ret &= ~0x04;
1106	1079
1107		if(!state->m_video.sub_reset)
	1080	if(!m_video.sub_reset)
1108	1081	ret &= ~0x01;
1109	1082
1110	1083	return ret;
1111	1084	}
1112	1085
1113		WRITE8_HANDLER( fm77av_video_flags_w )
	1086	WRITE8_MEMBER(fm7_state::fm77av_video_flags_w)
1114	1087	{
1115		fm7_state *state = space->machine().driver_data<fm7_state>();
1116		UINT8* RAM = space->machine().region("subsyscg")->base();
	1088	UINT8* RAM = machine().region("subsyscg")->base();
1117	1089
1118		state->m_video.cgrom = data & 0x03;
1119		memory_set_bankptr(space->machine(),"bank20",RAM+(state->m_video.cgrom*0x800));
1120		state->m_video.fine_offset = data & 0x04;
1121		state->m_video.active_video_page = data & 0x20;
1122		state->m_video.display_video_page = data & 0x40;
1123		state->m_video.nmi_mask = data & 0x80;
	1090	m_video.cgrom = data & 0x03;
	1091	memory_set_bankptr(machine(),"bank20",RAM+(m_video.cgrom*0x800));
	1092	m_video.fine_offset = data & 0x04;
	1093	m_video.active_video_page = data & 0x20;
	1094	m_video.display_video_page = data & 0x40;
	1095	m_video.nmi_mask = data & 0x80;
1124	1096	}
1125	1097
1126	1098	/*
r14963	r14964
1130	1102	*  bit 1 (R/O) - DISPTMG status (0=blank)
1131	1103	*  bit 0 (R/O) - VSync status (1=sync?)
1132	1104	*/
1133		READ8_HANDLER( fm77av_sub_modestatus_r )
	1105	READ8_MEMBER(fm7_state::fm77av_sub_modestatus_r)
1134	1106	{
1135		fm7_state *state = space->machine().driver_data<fm7_state>();
1136	1107	UINT8 ret = 0x00;
1137	1108
1138	1109	ret |= 0xbc;
1139		ret |= (state->m_video.modestatus & 0x40);
	1110	ret |= (m_video.modestatus & 0x40);
1140	1111
1141		if(!space->machine().primary_screen->vblank())
	1112	if(!machine().primary_screen->vblank())
1142	1113	ret |= 0x02;
1143	1114
1144		if(state->m_video.vsync_flag != 0)
	1115	if(m_video.vsync_flag != 0)
1145	1116	ret |= 0x01;
1146	1117
1147	1118	return ret;
1148	1119	}
1149	1120
1150		WRITE8_HANDLER( fm77av_sub_modestatus_w )
	1121	WRITE8_MEMBER(fm7_state::fm77av_sub_modestatus_w)
1151	1122	{
1152		fm7_state *state = space->machine().driver_data<fm7_state>();
1153		state->m_video.modestatus = data & 0x40;
	1123	m_video.modestatus = data & 0x40;
1154	1124	if(data & 0x40)
1155	1125	{
1156	1126	rectangle rect(0, 320-1, 0, 200-1);
1157		space->machine().primary_screen->configure(320,200,rect,HZ_TO_ATTOSECONDS(60));
	1127	machine().primary_screen->configure(320,200,rect,HZ_TO_ATTOSECONDS(60));
1158	1128	}
1159	1129	else
1160	1130	{
1161	1131	rectangle rect(0, 640-1, 0, 200-1);
1162		space->machine().primary_screen->configure(640,200,rect,HZ_TO_ATTOSECONDS(60));
	1132	machine().primary_screen->configure(640,200,rect,HZ_TO_ATTOSECONDS(60));
1163	1133	}
1164	1134	}
1165	1135
r14963	r14964
1170	1140	*  bits 1 and 0 select which subsys ROM to be banked into sub CPU space
1171	1141	*  on the FM-77AV40 and later, bit 2 can also selected to bank in sub monitor RAM.
1172	1142	*/
1173		WRITE8_HANDLER( fm77av_sub_bank_w )
	1143	WRITE8_MEMBER(fm7_state::fm77av_sub_bank_w)
1174	1144	{
1175		fm7_state *state = space->machine().driver_data<fm7_state>();
1176		//  UINT8* RAM = space->machine().region("sub")->base();
	1145	//  UINT8* RAM = machine().region("sub")->base();
1177	1146	UINT8* ROM;
1178	1147
1179		if((data & 0x03) == (state->m_sb_prev & 0x03))
	1148	if((data & 0x03) == (m_sb_prev & 0x03))
1180	1149	return;
1181	1150
1182		state->m_video.subrom = data & 0x03;
	1151	m_video.subrom = data & 0x03;
1183	1152	switch (data & 0x03)
1184	1153	{
1185	1154	case 0x00:  // Type C, 640x200 (as used on the FM-7)
1186		ROM = space->machine().region("subsys_c")->base();
1187		//  memory_set_bankptr(space->machine(),20,ROM);
1188		memory_set_bankptr(space->machine(),"bank21",ROM+0x800);
	1155	ROM = machine().region("subsys_c")->base();
	1156	//  memory_set_bankptr(machine(),20,ROM);
	1157	memory_set_bankptr(machine(),"bank21",ROM+0x800);
1189	1158	logerror("VID: Sub ROM Type C selected\n");
1190	1159	break;
1191	1160	case 0x01:  // Type A, 640x200
1192		ROM = space->machine().region("subsys_a")->base();
1193		//  memory_set_bankptr(space->machine(),20,RAM+0xd800);
1194		memory_set_bankptr(space->machine(),"bank21",ROM);
	1161	ROM = machine().region("subsys_a")->base();
	1162	//  memory_set_bankptr(machine(),20,RAM+0xd800);
	1163	memory_set_bankptr(machine(),"bank21",ROM);
1195	1164	logerror("VID: Sub ROM Type A selected\n");
1196	1165	break;
1197	1166	case 0x02:  // Type B, 320x200
1198		ROM = space->machine().region("subsys_b")->base();
1199		//  memory_set_bankptr(space->machine(),20,RAM+0xd800);
1200		memory_set_bankptr(space->machine(),"bank21",ROM);
	1167	ROM = machine().region("subsys_b")->base();
	1168	//  memory_set_bankptr(machine(),20,RAM+0xd800);
	1169	memory_set_bankptr(machine(),"bank21",ROM);
1201	1170	logerror("VID: Sub ROM Type B selected\n");
1202	1171	break;
1203	1172	case 0x03:  // CG Font?
1204		ROM = space->machine().region("subsyscg")->base();
1205		//  memory_set_bankptr(space->machine(),20,RAM+0xd800);
1206		memory_set_bankptr(space->machine(),"bank21",ROM);
	1173	ROM = machine().region("subsyscg")->base();
	1174	//  memory_set_bankptr(machine(),20,RAM+0xd800);
	1175	memory_set_bankptr(machine(),"bank21",ROM);
1207	1176	logerror("VID: Sub ROM CG selected\n");
1208	1177	break;
1209	1178	}
1210	1179	// reset sub CPU, set busy flag, set reset flag
1211		cputag_set_input_line(space->machine(),"sub",INPUT_LINE_RESET,PULSE_LINE);
1212		state->m_video.sub_busy = 0x80;
1213		state->m_video.sub_halt = 0;
1214		state->m_video.sub_reset = 1;
1215		state->m_sb_prev = data;
	1180	cputag_set_input_line(machine(),"sub",INPUT_LINE_RESET,PULSE_LINE);
	1181	m_video.sub_busy = 0x80;
	1182	m_video.sub_halt = 0;
	1183	m_video.sub_reset = 1;
	1184	m_sb_prev = data;
1216	1185	}
1217	1186
1218	1187	/*
r14963	r14964
1243	1212	*  0xd428-29(W): Line X1 (High-Low, X9-X0)
1244	1213	*  0xd42a-2b(W): Line Y1 (High-Low, Y8-Y0)
1245	1214	*/
1246		READ8_HANDLER( fm77av_alu_r )
	1215	READ8_MEMBER(fm7_state::fm77av_alu_r)
1247	1216	{
1248		fm7_state *state = space->machine().driver_data<fm7_state>();
1249	1217	switch(offset)
1250	1218	{
1251	1219	case 0x00:
1252		logerror("ALU: read from command register (%02x)\n",state->m_alu.command);
1253		return state->m_alu.command;
	1220	logerror("ALU: read from command register (%02x)\n",m_alu.command);
	1221	return m_alu.command;
1254	1222	case 0x01:
1255	1223	logerror("ALU: read from logical colour\n");
1256		return state->m_alu.lcolour;
	1224	return m_alu.lcolour;
1257	1225	case 0x02:
1258	1226	logerror("ALU: read from mask register\n");
1259		return state->m_alu.mask;
	1227	return m_alu.mask;
1260	1228	case 0x03:
1261		logerror("ALU: read from compare data register (%02x)\n",state->m_alu.compare_data);
1262		return state->m_alu.compare_data;
	1229	logerror("ALU: read from compare data register (%02x)\n",m_alu.compare_data);
	1230	return m_alu.compare_data;
1263	1231	case 0x0b:
1264	1232	logerror("ALU: read from bank disable register\n");
1265		return 0xf7 | state->m_alu.bank_disable;
	1233	return 0xf7 | m_alu.bank_disable;
1266	1234	default:
1267	1235	logerror("ALU: read from invalid register 0x%02x\n",offset);
1268	1236	return 0xff;
r14963	r14964
1270	1238	return 0xff;
1271	1239	}
1272	1240
1273		WRITE8_HANDLER( fm77av_alu_w )
	1241	WRITE8_MEMBER(fm7_state::fm77av_alu_w)
1274	1242	{
1275		fm7_state *state = space->machine().driver_data<fm7_state>();
1276	1243	UINT16 dat;
1277	1244
1278	1245	switch(offset)
1279	1246	{
1280	1247	case 0x00:
1281		state->m_alu.command = data;
	1248	m_alu.command = data;
1282	1249	logerror("ALU: write to command register - %02x\n",data);
1283	1250	break;
1284	1251	case 0x01:
1285		state->m_alu.lcolour = data & 0x07;
	1252	m_alu.lcolour = data & 0x07;
1286	1253	logerror("ALU: write to logical colour - %02x\n",data);
1287	1254	break;
1288	1255	case 0x02:
1289		state->m_alu.mask = data;
	1256	m_alu.mask = data;
1290	1257	logerror("ALU: write to mask register - %02x\n",data);
1291	1258	break;
1292	1259	case 0x03:
r14963	r14964
1297	1264	case 0x08:
1298	1265	case 0x09:
1299	1266	case 0x0a:
1300		state->m_alu.compare[offset-3] = data;
	1267	m_alu.compare[offset-3] = data;
1301	1268	logerror("ALU: write to compare register %i - %02x\n",offset-3,data);
1302	1269	break;
1303	1270	case 0x0b:
1304		state->m_alu.bank_disable = data & 0x03;
	1271	m_alu.bank_disable = data & 0x03;
1305	1272	//          logerror("ALU: write to bank disable register - %02x\n",data);
1306	1273	break;
1307	1274	case 0x0c:
1308		state->m_alu.tilepaint_b = data;
	1275	m_alu.tilepaint_b = data;
1309	1276	//          logerror("ALU: write to tilepaint (blue) register - %02x\n",data);
1310	1277	break;
1311	1278	case 0x0d:
1312		state->m_alu.tilepaint_r = data;
	1279	m_alu.tilepaint_r = data;
1313	1280	//          logerror("ALU: write to tilepaint (red) register - %02x\n",data);
1314	1281	break;
1315	1282	case 0x0e:
1316		state->m_alu.tilepaint_g = data;
	1283	m_alu.tilepaint_g = data;
1317	1284	//          logerror("ALU: write to tilepaint (green) register - %02x\n",data);
1318	1285	break;
1319	1286	case 0x10:
1320		dat = ((data & 0x1f) << 8) | (state->m_alu.addr_offset & 0x00ff);
1321		state->m_alu.addr_offset = dat;
1322		//          logerror("ALU: write to address offset (high) register - %02x (%04x)\n",data,state->m_alu.addr_offset);
	1287	dat = ((data & 0x1f) << 8) | (m_alu.addr_offset & 0x00ff);
	1288	m_alu.addr_offset = dat;
	1289	//          logerror("ALU: write to address offset (high) register - %02x (%04x)\n",data,m_alu.addr_offset);
1323	1290	break;
1324	1291	case 0x11:
1325		dat = (state->m_alu.addr_offset & 0xff00) | data;
1326		state->m_alu.addr_offset = dat;
1327		//          logerror("ALU: write to address offset (low) register - %02x (%04x)\n",data,state->m_alu.addr_offset);
	1292	dat = (m_alu.addr_offset & 0xff00) | data;
	1293	m_alu.addr_offset = dat;
	1294	//          logerror("ALU: write to address offset (low) register - %02x (%04x)\n",data,m_alu.addr_offset);
1328	1295	break;
1329	1296	case 0x12:
1330		dat = (data << 8) | (state->m_alu.line_style & 0x00ff);
1331		state->m_alu.line_style = dat;
1332		//          logerror("ALU: write to line style (high) register - %02x (%04x)\n",data,state->m_alu.line_style);
	1297	dat = (data << 8) | (m_alu.line_style & 0x00ff);
	1298	m_alu.line_style = dat;
	1299	//          logerror("ALU: write to line style (high) register - %02x (%04x)\n",data,m_alu.line_style);
1333	1300	break;
1334	1301	case 0x13:
1335		dat = (state->m_alu.line_style & 0xff00) | data;
1336		state->m_alu.line_style = dat;
1337		//          logerror("ALU: write to line style (low) register - %02x (%04x)\n",data,state->m_alu.line_style);
	1302	dat = (m_alu.line_style & 0xff00) | data;
	1303	m_alu.line_style = dat;
	1304	//          logerror("ALU: write to line style (low) register - %02x (%04x)\n",data,m_alu.line_style);
1338	1305	break;
1339	1306	case 0x14:
1340		dat = ((data & 0x03) << 8) | (state->m_alu.x0 & 0x00ff);
1341		state->m_alu.x0 = dat;
1342		//          logerror("ALU: write to X0 (high) register - %02x (%04x)\n",data,state->m_alu.x0);
	1307	dat = ((data & 0x03) << 8) | (m_alu.x0 & 0x00ff);
	1308	m_alu.x0 = dat;
	1309	//          logerror("ALU: write to X0 (high) register - %02x (%04x)\n",data,m_alu.x0);
1343	1310	break;
1344	1311	case 0x15:
1345		dat = (state->m_alu.x0 & 0xff00) | data;
1346		state->m_alu.x0 = dat;
1347		//          logerror("ALU: write to X0 (low) register - %02x (%04x)\n",data,state->m_alu.x0);
	1312	dat = (m_alu.x0 & 0xff00) | data;
	1313	m_alu.x0 = dat;
	1314	//          logerror("ALU: write to X0 (low) register - %02x (%04x)\n",data,m_alu.x0);
1348	1315	break;
1349	1316	case 0x16:
1350		dat = ((data & 0x01) << 8) | (state->m_alu.y0 & 0x00ff);
1351		state->m_alu.y0 = dat;
1352		//          logerror("ALU: write to Y0 (high) register - %02x (%04x)\n",data,state->m_alu.y0);
	1317	dat = ((data & 0x01) << 8) | (m_alu.y0 & 0x00ff);
	1318	m_alu.y0 = dat;
	1319	//          logerror("ALU: write to Y0 (high) register - %02x (%04x)\n",data,m_alu.y0);
1353	1320	break;
1354	1321	case 0x17:
1355		dat = (state->m_alu.y0 & 0xff00) | data;
1356		state->m_alu.y0 = dat;
1357		//          logerror("ALU: write to Y0 (low) register - %02x (%04x)\n",data,state->m_alu.y0);
	1322	dat = (m_alu.y0 & 0xff00) | data;
	1323	m_alu.y0 = dat;
	1324	//          logerror("ALU: write to Y0 (low) register - %02x (%04x)\n",data,m_alu.y0);
1358	1325	break;
1359	1326	case 0x18:
1360		dat = ((data & 0x03) << 8) | (state->m_alu.x1 & 0x00ff);
1361		state->m_alu.x1 = dat;
1362		//          logerror("ALU: write to X1 (high) register - %02x (%04x)\n",data,state->m_alu.x1);
	1327	dat = ((data & 0x03) << 8) | (m_alu.x1 & 0x00ff);
	1328	m_alu.x1 = dat;
	1329	//          logerror("ALU: write to X1 (high) register - %02x (%04x)\n",data,m_alu.x1);
1363	1330	break;
1364	1331	case 0x19:
1365		dat = (state->m_alu.x1 & 0xff00) | data;
1366		state->m_alu.x1 = dat;
1367		//          logerror("ALU: write to X1 (low) register - %02x (%04x)\n",data,state->m_alu.x1);
	1332	dat = (m_alu.x1 & 0xff00) | data;
	1333	m_alu.x1 = dat;
	1334	//          logerror("ALU: write to X1 (low) register - %02x (%04x)\n",data,m_alu.x1);
1368	1335	break;
1369	1336	case 0x1a:
1370		dat = ((data & 0x01) << 8) | (state->m_alu.y1 & 0x00ff);
1371		state->m_alu.y1 = dat;
1372		//          logerror("ALU: write to Y1 (high) register - %02x (%04x)\n",data,state->m_alu.y1);
	1337	dat = ((data & 0x01) << 8) | (m_alu.y1 & 0x00ff);
	1338	m_alu.y1 = dat;
	1339	//          logerror("ALU: write to Y1 (high) register - %02x (%04x)\n",data,m_alu.y1);
1373	1340	break;
1374	1341	case 0x1b:
1375		dat = (state->m_alu.y1 & 0xff00) | data;
1376		state->m_alu.y1 = dat;
	1342	dat = (m_alu.y1 & 0xff00) | data;
	1343	m_alu.y1 = dat;
1377	1344	// draw line
1378		fm77av_line_draw(space->machine());
1379		//          logerror("ALU: write to Y1 (low) register - %02x (%04x)\n",data,state->m_alu.y1);
	1345	fm77av_line_draw(machine());
	1346	//          logerror("ALU: write to Y1 (low) register - %02x (%04x)\n",data,m_alu.y1);
1380	1347	break;
1381	1348	default:
1382	1349	logerror("ALU: write 0x%02x to invalid register 0x%02x\n",data,offset);
r14963	r14964
1399	1366	}
1400	1367
1401	1368	// called when banked into main CPU space by the MMR, available only if sub CPU is halted
1402		READ8_HANDLER( fm7_sub_ram_ports_banked_r )
	1369	READ8_MEMBER(fm7_state::fm7_sub_ram_ports_banked_r)
1403	1370	{
1404		fm7_state *state = space->machine().driver_data<fm7_state>();
1405		UINT8* RAM = space->machine().region("maincpu")->base();
	1371	UINT8* RAM = machine().region("maincpu")->base();
1406	1372	UINT8* ROM;
1407	1373
1408		if(!state->m_video.sub_halt)
	1374	if(!m_video.sub_halt)
1409	1375	return 0xff;
1410	1376
1411	1377	if(offset < 0x380)  // work RAM
1412	1378	return RAM[0x1d000+offset];
1413	1379	if(offset >= 0x380 && offset < 0x400) // shared RAM
1414		return state->m_shared_ram[offset-0x380];
	1380	return m_shared_ram[offset-0x380];
1415	1381	if(offset >= 0x500 && offset < 0x800) // work RAM
1416	1382	return RAM[0x1d000+offset];
1417	1383	if(offset > 0x800) // CGROM
1418	1384	{
1419		ROM = space->machine().region("subsyscg")->base();
1420		return ROM[(state->m_video.cgrom*0x800)+(offset-0x800)];
	1385	ROM = machine().region("subsyscg")->base();
	1386	return ROM[(m_video.cgrom*0x800)+(offset-0x800)];
1421	1387	}
1422	1388
1423	1389	if(offset >= 0x410 && offset <= 0x42b)
r14963	r14964
1452	1418	return 0xff;
1453	1419	}
1454	1420
1455		WRITE8_HANDLER( fm7_sub_ram_ports_banked_w )
	1421	WRITE8_MEMBER(fm7_state::fm7_sub_ram_ports_banked_w)
1456	1422	{
1457		fm7_state *state = space->machine().driver_data<fm7_state>();
1458		UINT8* RAM = space->machine().region("maincpu")->base();
	1423	UINT8* RAM = machine().region("maincpu")->base();
1459	1424
1460		if(!state->m_video.sub_halt)
	1425	if(!m_video.sub_halt)
1461	1426	return;
1462	1427
1463	1428	if(offset < 0x380)  // work RAM
r14963	r14964
1467	1432	}
1468	1433	if(offset >= 0x380 && offset < 0x400) // shared RAM
1469	1434	{
1470		state->m_shared_ram[offset-0x380] = data;
	1435	m_shared_ram[offset-0x380] = data;
1471	1436	return;
1472	1437	}
1473	1438	if(offset >= 0x500 && offset < 0x800) // work RAM
r14963	r14964
1509	1474	}
1510	1475	}
1511	1476
1512		READ8_HANDLER( fm7_console_ram_banked_r )
	1477	READ8_MEMBER(fm7_state::fm7_console_ram_banked_r)
1513	1478	{
1514		fm7_state *state = space->machine().driver_data<fm7_state>();
1515		UINT8* RAM = space->machine().region("maincpu")->base();
	1479	UINT8* RAM = machine().region("maincpu")->base();
1516	1480
1517		if(!state->m_video.sub_halt)
	1481	if(!m_video.sub_halt)
1518	1482	return 0xff;
1519	1483
1520	1484	return RAM[0x1c000+offset];
1521	1485	}
1522	1486
1523		WRITE8_HANDLER( fm7_console_ram_banked_w )
	1487	WRITE8_MEMBER(fm7_state::fm7_console_ram_banked_w)
1524	1488	{
1525		fm7_state *state = space->machine().driver_data<fm7_state>();
1526		UINT8* RAM = space->machine().region("maincpu")->base();
	1489	UINT8* RAM = machine().region("maincpu")->base();
1527	1490
1528		if(!state->m_video.sub_halt)
	1491	if(!m_video.sub_halt)
1529	1492	return;
1530	1493
1531	1494	RAM[0x1c000+offset] = data;

src/mess/video/vtech2.c

r14963	r14964
292	292	return 0;
293	293	}
294	294
295		WRITE8_HANDLER( laser_bg_mode_w )
	295	WRITE8_MEMBER(vtech2_state::laser_bg_mode_w)
296	296	{
297		vtech2_state *state = space->machine().driver_data<vtech2_state>();
298		if (state->m_laser_bg_mode != data)
	297	if (m_laser_bg_mode != data)
299	298	{
300		state->m_laser_bg_mode = data;
	299	m_laser_bg_mode = data;
301	300	logerror("laser border:$%X mode:$%X\n", data >> 4, data & 15);
302	301	}
303	302	}
304	303
305		WRITE8_HANDLER( laser_two_color_w )
	304	WRITE8_MEMBER(vtech2_state::laser_two_color_w)
306	305	{
307		vtech2_state *state = space->machine().driver_data<vtech2_state>();
308		if (state->m_laser_two_color != data)
	306	if (m_laser_two_color != data)
309	307	{
310		state->m_laser_two_color = data;
	308	m_laser_two_color = data;
311	309	logerror("laser foreground:$%X background:$%X\n", data >> 4, data & 15);
312	310	}
313	311	}

src/mess/formats/m65_snqk.c

r14963	r14964
289	289	{
290	290	RAM[0xbff0+i] = snapshot_buff[base++];
291	291	if (i < 4)
292		microtan_bffx_w(space, i, RAM[0xbff0+i]);
	292	state->microtan_bffx_w(*space, i, RAM[0xbff0+i]);
293	293	}
294	294
295		microtan_sound_w(space, 0, snapshot_buff[base++]);
	295	state->microtan_sound_w(*space, 0, snapshot_buff[base++]);
296	296	state->m_chunky_graphics = snapshot_buff[base++];
297	297
298	298	/* first set of AY8910 registers */

src/mess/drivers/comquest.c

r14963	r14964
45	45	#include "imagedev/cartslot.h"
46	46
47	47	#ifdef UNUSED_FUNCTION
48		static  READ8_HANDLER(comquest_read)
	48	READ8_MEMBER(comquest_state::comquest_read)
49	49	{
50	50	UINT8 data=0;
51	51	logerror("comquest read %.4x %.2x\n",offset,data);
52	52	return data;
53	53	}
54	54
55		static WRITE8_HANDLER(comquest_write)
	55	WRITE8_MEMBER(comquest_state::comquest_write)
56	56	{
57	57	logerror("comquest read %.4x %.2x\n",offset,data);
58	58	}

src/mess/drivers/apple3.c

r14963	r14964
23	23	#include "devices/appldriv.h"
24	24
25	25	static ADDRESS_MAP_START( apple3_map, AS_PROGRAM, 8, apple3_state )
26		AM_RANGE(0x0000, 0x00FF) AM_READWRITE_LEGACY(apple3_00xx_r, apple3_00xx_w)
	26	AM_RANGE(0x0000, 0x00FF) AM_READWRITE(apple3_00xx_r, apple3_00xx_w)
27	27	AM_RANGE(0x0100, 0x01FF) AM_RAMBANK("bank2")
28	28	AM_RANGE(0x0200, 0x1FFF) AM_RAMBANK("bank3")
29	29	AM_RANGE(0x2000, 0x9FFF) AM_RAMBANK("bank4")
r14963	r14964
36	36	* different memory locations */
37	37	static const m6502_interface apple3_m6502_interface =
38	38	{
39		apple3_indexed_read,   /* read_indexed_func */
40		apple3_indexed_write,   /* write_indexed_func */
41		DEVCB_NULL,            /* port_read_func */
42		DEVCB_NULL            /* port_write_func */
	39	NULL,   /* read_indexed_func */
	40	NULL,   /* write_indexed_func */
	41	DEVCB_DRIVER_MEMBER(apple3_state, apple3_indexed_read),            /* port_read_func */
	42	DEVCB_DRIVER_MEMBER(apple3_state, apple3_indexed_write)            /* port_write_func */
43	43	};
44	44
45	45	static const floppy_interface apple3_floppy_interface =

src/mess/drivers/dai.c

r14963	r14964
77	77	AM_RANGE( 0x0000, 0xbfff) AM_RAMBANK("bank1")
78	78	AM_RANGE( 0xc000, 0xdfff) AM_ROM
79	79	AM_RANGE( 0xe000, 0xefff) AM_ROMBANK("bank2")
80		AM_RANGE( 0xf000, 0xf7ff) AM_WRITE_LEGACY(dai_stack_interrupt_circuit_w )
	80	AM_RANGE( 0xf000, 0xf7ff) AM_WRITE(dai_stack_interrupt_circuit_w )
81	81	AM_RANGE( 0xf800, 0xf8ff) AM_RAM
82		AM_RANGE( 0xfb00, 0xfbff) AM_READWRITE_LEGACY(dai_amd9511_r, dai_amd9511_w )
	82	AM_RANGE( 0xfb00, 0xfbff) AM_READWRITE(dai_amd9511_r, dai_amd9511_w )
83	83	AM_RANGE( 0xfc00, 0xfcff) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r, pit8253_w )
84		AM_RANGE( 0xfd00, 0xfdff) AM_READWRITE_LEGACY(dai_io_discrete_devices_r, dai_io_discrete_devices_w )
	84	AM_RANGE( 0xfd00, 0xfdff) AM_READWRITE(dai_io_discrete_devices_r, dai_io_discrete_devices_w )
85	85	AM_RANGE( 0xfe00, 0xfeff) AM_DEVREADWRITE("ppi8255", i8255_device, read, write)
86	86	AM_RANGE( 0xff00, 0xffff) AM_DEVREADWRITE_LEGACY("tms5501", tms5501_r, tms5501_w )
87	87	ADDRESS_MAP_END

src/mess/drivers/cbmb.c

r14963	r14964
161	161	AM_RANGE(0xf6000, 0xf7fff) AM_ROM
162	162	AM_RANGE(0xf8000, 0xfbfff) AM_ROM AM_SHARE("basic")
163	163	AM_RANGE(0xfd000, 0xfd3ff) AM_RAM AM_SHARE("videoram")      /* videoram */
164		AM_RANGE(0xfd400, 0xfd7ff) AM_RAM_WRITE_LEGACY(cbmb_colorram_w) AM_SHARE("colorram")      /* colorram */
	164	AM_RANGE(0xfd400, 0xfd7ff) AM_RAM_WRITE(cbmb_colorram_w) AM_SHARE("colorram")      /* colorram */
165	165	AM_RANGE(0xfd800, 0xfd8ff) AM_DEVREADWRITE_LEGACY("vic6567", vic2_port_r, vic2_port_w)
166	166	/* disk units */
167	167	AM_RANGE(0xfda00, 0xfdaff) AM_DEVREADWRITE_LEGACY("sid6581", sid6581_r, sid6581_w)

src/mess/drivers/gb.c

r14963	r14964
467	467	AM_RANGE(0x0900, 0x3fff) AM_ROMBANK("bank11")
468	468	AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank1")               /* 8KB/16KB switched ROM bank */
469	469	AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank4")               /* 8KB/16KB switched ROM bank */
470		AM_RANGE(0x8000, 0x9fff) AM_READWRITE_LEGACY(gb_vram_r, gb_vram_w ) /* 8k VRAM */
	470	AM_RANGE(0x8000, 0x9fff) AM_READWRITE(gb_vram_r, gb_vram_w ) /* 8k VRAM */
471	471	AM_RANGE(0xa000, 0xbfff) AM_RAMBANK("bank2")               /* 8k switched RAM bank (cartridge) */
472	472	AM_RANGE(0xc000, 0xfdff) AM_RAM                  /* 8k low RAM, echo RAM */
473		AM_RANGE(0xfe00, 0xfeff) AM_READWRITE_LEGACY(gb_oam_r, gb_oam_w )   /* OAM RAM */
474		AM_RANGE(0xff00, 0xff0f) AM_READWRITE_LEGACY(gb_io_r, gb_io_w )      /* I/O */
	473	AM_RANGE(0xfe00, 0xfeff) AM_READWRITE(gb_oam_r, gb_oam_w )   /* OAM RAM */
	474	AM_RANGE(0xff00, 0xff0f) AM_READWRITE(gb_io_r, gb_io_w )      /* I/O */
475	475	AM_RANGE(0xff10, 0xff26) AM_DEVREADWRITE_LEGACY("custom", gb_sound_r, gb_sound_w )      /* sound registers */
476	476	AM_RANGE(0xff27, 0xff2f) AM_NOP                  /* unused */
477	477	AM_RANGE(0xff30, 0xff3f) AM_DEVREADWRITE_LEGACY("custom", gb_wave_r, gb_wave_w )      /* Wave ram */
478		AM_RANGE(0xff40, 0xff7f) AM_READWRITE_LEGACY(gb_video_r, gb_io2_w)      /* Video controller & BIOS flip-flop */
	478	AM_RANGE(0xff40, 0xff7f) AM_READWRITE(gb_video_r, gb_io2_w)      /* Video controller & BIOS flip-flop */
479	479	AM_RANGE(0xff80, 0xfffe) AM_RAM                  /* High RAM */
480		AM_RANGE(0xffff, 0xffff) AM_READWRITE_LEGACY(gb_ie_r, gb_ie_w )      /* Interrupt enable register */
	480	AM_RANGE(0xffff, 0xffff) AM_READWRITE(gb_ie_r, gb_ie_w )      /* Interrupt enable register */
481	481	ADDRESS_MAP_END
482	482
483	483	static ADDRESS_MAP_START(sgb_map, AS_PROGRAM, 8, gb_state )
r14963	r14964
488	488	AM_RANGE(0x0900, 0x3fff) AM_ROMBANK("bank11")
489	489	AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank1")               /* 8KB/16KB switched ROM bank */
490	490	AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank4")               /* 8KB/16KB switched ROM bank */
491		AM_RANGE(0x8000, 0x9fff) AM_READWRITE_LEGACY(gb_vram_r, gb_vram_w ) /* 8k VRAM */
	491	AM_RANGE(0x8000, 0x9fff) AM_READWRITE(gb_vram_r, gb_vram_w ) /* 8k VRAM */
492	492	AM_RANGE(0xa000, 0xbfff) AM_RAMBANK("bank2")               /* 8k switched RAM bank (cartridge) */
493	493	AM_RANGE(0xc000, 0xfdff) AM_RAM                  /* 8k low RAM, echo RAM */
494		AM_RANGE(0xfe00, 0xfeff) AM_READWRITE_LEGACY(gb_oam_r, gb_oam_w )   /* OAM RAM */
495		AM_RANGE(0xff00, 0xff0f) AM_READWRITE_LEGACY(gb_io_r, sgb_io_w )      /* I/O */
	494	AM_RANGE(0xfe00, 0xfeff) AM_READWRITE(gb_oam_r, gb_oam_w )   /* OAM RAM */
	495	AM_RANGE(0xff00, 0xff0f) AM_READWRITE(gb_io_r, sgb_io_w )      /* I/O */
496	496	AM_RANGE(0xff10, 0xff26) AM_DEVREADWRITE_LEGACY("custom", gb_sound_r, gb_sound_w )      /* sound registers */
497	497	AM_RANGE(0xff27, 0xff2f) AM_NOP                  /* unused */
498	498	AM_RANGE(0xff30, 0xff3f) AM_DEVREADWRITE_LEGACY("custom", gb_wave_r, gb_wave_w )      /* Wave RAM */
499		AM_RANGE(0xff40, 0xff7f) AM_READWRITE_LEGACY(gb_video_r, gb_io2_w )      /* Video controller & BIOS flip-flop */
	499	AM_RANGE(0xff40, 0xff7f) AM_READWRITE(gb_video_r, gb_io2_w )      /* Video controller & BIOS flip-flop */
500	500	AM_RANGE(0xff80, 0xfffe) AM_RAM                  /* High RAM */
501		AM_RANGE(0xffff, 0xffff) AM_READWRITE_LEGACY(gb_ie_r, gb_ie_w )      /* Interrupt enable register */
	501	AM_RANGE(0xffff, 0xffff) AM_READWRITE(gb_ie_r, gb_ie_w )      /* Interrupt enable register */
502	502	ADDRESS_MAP_END
503	503
504	504	static ADDRESS_MAP_START(gbc_map, AS_PROGRAM, 8, gb_state )
r14963	r14964
509	509	AM_RANGE(0x0900, 0x3fff) AM_ROMBANK("bank11")
510	510	AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank1")               /* 8KB/16KB switched ROM bank */
511	511	AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank4")               /* 8KB/16KB switched ROM bank */
512		AM_RANGE(0x8000, 0x9fff) AM_READWRITE_LEGACY(gb_vram_r, gb_vram_w )      /* 8k switched VRAM bank */
	512	AM_RANGE(0x8000, 0x9fff) AM_READWRITE(gb_vram_r, gb_vram_w )      /* 8k switched VRAM bank */
513	513	AM_RANGE(0xa000, 0xbfff) AM_RAMBANK("bank2")               /* 8k switched RAM bank (on cartridge) */
514	514	AM_RANGE(0xc000, 0xcfff) AM_RAM                  /* 4k fixed RAM bank */
515	515	AM_RANGE(0xd000, 0xdfff) AM_RAMBANK("bank3")               /* 4k switched RAM bank */
516	516	AM_RANGE(0xe000, 0xfdff) AM_RAM                  /* echo RAM */
517		AM_RANGE(0xfe00, 0xfeff) AM_READWRITE_LEGACY(gb_oam_r, gb_oam_w )   /* OAM RAM */
518		AM_RANGE(0xff00, 0xff0f) AM_READWRITE_LEGACY(gb_io_r, gb_io_w )      /* I/O */
	517	AM_RANGE(0xfe00, 0xfeff) AM_READWRITE(gb_oam_r, gb_oam_w )   /* OAM RAM */
	518	AM_RANGE(0xff00, 0xff0f) AM_READWRITE(gb_io_r, gb_io_w )      /* I/O */
519	519	AM_RANGE(0xff10, 0xff26) AM_DEVREADWRITE_LEGACY("custom", gb_sound_r, gb_sound_w )      /* sound controller */
520	520	AM_RANGE(0xff27, 0xff2f) AM_NOP                  /* unused */
521	521	AM_RANGE(0xff30, 0xff3f) AM_DEVREADWRITE_LEGACY("custom", gb_wave_r, gb_wave_w )      /* Wave RAM */
522		AM_RANGE(0xff40, 0xff7f) AM_READWRITE_LEGACY(gbc_io2_r, gbc_io2_w )      /* Other I/O and video controller */
	522	AM_RANGE(0xff40, 0xff7f) AM_READWRITE(gbc_io2_r, gbc_io2_w )      /* Other I/O and video controller */
523	523	AM_RANGE(0xff80, 0xfffe) AM_RAM                  /* high RAM */
524		AM_RANGE(0xffff, 0xffff) AM_READWRITE_LEGACY(gb_ie_r, gb_ie_w )      /* Interrupt enable register */
	524	AM_RANGE(0xffff, 0xffff) AM_READWRITE(gb_ie_r, gb_ie_w )      /* Interrupt enable register */
525	525	ADDRESS_MAP_END
526	526
527	527	static ADDRESS_MAP_START(megaduck_map, AS_PROGRAM, 8, gb_state )
528	528	ADDRESS_MAP_UNMAP_HIGH
529	529	AM_RANGE(0x0000, 0x3fff) AM_ROMBANK("bank10")                  /* 16k switched ROM bank */
530	530	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")                  /* 16k switched ROM bank */
531		AM_RANGE(0x8000, 0x9fff) AM_READWRITE_LEGACY(gb_vram_r, gb_vram_w )      /* 8k VRAM */
	531	AM_RANGE(0x8000, 0x9fff) AM_READWRITE(gb_vram_r, gb_vram_w )      /* 8k VRAM */
532	532	AM_RANGE(0xa000, 0xbfff) AM_NOP                     /* unused? */
533	533	AM_RANGE(0xc000, 0xfe9f) AM_RAM                     /* 8k low RAM, echo RAM */
534		AM_RANGE(0xfe00, 0xfeff) AM_READWRITE_LEGACY(gb_oam_r, gb_oam_w )      /* OAM RAM */
535		AM_RANGE(0xff00, 0xff0f) AM_READWRITE_LEGACY(gb_io_r, gb_io_w )         /* I/O */
536		AM_RANGE(0xff10, 0xff1f) AM_READWRITE_LEGACY(megaduck_video_r, megaduck_video_w )   /* video controller */
537		AM_RANGE(0xff20, 0xff2f) AM_READWRITE_LEGACY(megaduck_sound_r1, megaduck_sound_w1)   /* sound controller pt1 */
	534	AM_RANGE(0xfe00, 0xfeff) AM_READWRITE(gb_oam_r, gb_oam_w )      /* OAM RAM */
	535	AM_RANGE(0xff00, 0xff0f) AM_READWRITE(gb_io_r, gb_io_w )         /* I/O */
	536	AM_RANGE(0xff10, 0xff1f) AM_READWRITE(megaduck_video_r, megaduck_video_w )   /* video controller */
	537	AM_RANGE(0xff20, 0xff2f) AM_READWRITE(megaduck_sound_r1, megaduck_sound_w1)   /* sound controller pt1 */
538	538	AM_RANGE(0xff30, 0xff3f) AM_DEVREADWRITE_LEGACY("custom", gb_wave_r, gb_wave_w )         /* wave ram */
539		AM_RANGE(0xff40, 0xff46) AM_READWRITE_LEGACY(megaduck_sound_r2, megaduck_sound_w2)   /* sound controller pt2 */
	539	AM_RANGE(0xff40, 0xff46) AM_READWRITE(megaduck_sound_r2, megaduck_sound_w2)   /* sound controller pt2 */
540	540	AM_RANGE(0xff47, 0xff7f) AM_NOP                     /* unused */
541	541	AM_RANGE(0xff80, 0xfffe) AM_RAM                     /* high RAM */
542		AM_RANGE(0xffff, 0xffff) AM_READWRITE_LEGACY(gb_ie_r, gb_ie_w )         /* interrupt enable register */
	542	AM_RANGE(0xffff, 0xffff) AM_READWRITE(gb_ie_r, gb_ie_w )         /* interrupt enable register */
543	543	ADDRESS_MAP_END
544	544
545	545	static GFXDECODE_START( gb )

src/mess/drivers/glasgow.c

r14963	r14964
80	80	UINT8 m_led7;
81	81	UINT8 m_irq_flag;
82	82	UINT16 m_beeper;
	83	DECLARE_READ16_MEMBER(read_test);
	84	DECLARE_READ16_MEMBER(read_board_amsterd);
83	85	};
84	86
85	87
r14963	r14964
190	192
191	193
192	194	#ifdef UNUSED_FUNCTION
193		READ16_HANDLER(read_test)
	195	READ16_MEMBER(glasgow_state::read_test)
194	196	{
195	197	logerror("read test Offset = %x Data = %x\n  ",offset,data);
196	198	return 0xffff;    // Mephisto need it for working
r14963	r14964
253	255	}
254	256
255	257	#ifdef UNUSED_FUNCTION
256		READ16_HANDLER(read_board_amsterd)
	258	READ16_MEMBER(glasgow_state::read_board_amsterd)
257	259	{
258	260	logerror("read board amsterdam Offset = %x \n  ", offset);
259	261	return 0xffff;

src/mess/drivers/radio86.c

r14963	r14964
31	31
32	32	static ADDRESS_MAP_START( radio86_io , AS_IO, 8, radio86_state )
33	33	ADDRESS_MAP_UNMAP_HIGH
34		AM_RANGE( 0x00, 0xff ) AM_READWRITE_LEGACY(radio_io_r,radio_io_w)
	34	AM_RANGE( 0x00, 0xff ) AM_READWRITE(radio_io_r,radio_io_w)
35	35	ADDRESS_MAP_END
36	36
37	37	static ADDRESS_MAP_START( rk7007_io , AS_IO, 8, radio86_state )
r14963	r14964
57	57	AM_RANGE( 0xf700, 0xf703 ) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
58	58	AM_RANGE( 0xf780, 0xf7bf ) AM_DEVREADWRITE_LEGACY("i8275", i8275_r, i8275_w) // video
59	59	AM_RANGE( 0xf684, 0xf687 ) AM_DEVREADWRITE("ppi8255_2", i8255_device, read, write)
60		AM_RANGE( 0xf688, 0xf688 ) AM_WRITE_LEGACY(radio86_pagesel )
	60	AM_RANGE( 0xf688, 0xf688 ) AM_WRITE(radio86_pagesel )
61	61	AM_RANGE( 0xf800, 0xffff ) AM_DEVWRITE_LEGACY("dma8257", i8257_w)    // DMA
62	62	AM_RANGE( 0xf800, 0xffff ) AM_ROM  // System ROM page 1
63	63	ADDRESS_MAP_END
r14963	r14964
66	66	ADDRESS_MAP_UNMAP_HIGH
67	67	AM_RANGE( 0x0000, 0x0fff ) AM_RAMBANK("bank1") // First bank
68	68	AM_RANGE( 0x1000, 0x3fff ) AM_RAM  // RAM
69		AM_RANGE( 0x4000, 0x7fff ) AM_READ_LEGACY(radio_cpu_state_r)
	69	AM_RANGE( 0x4000, 0x7fff ) AM_READ(radio_cpu_state_r)
70	70	AM_RANGE( 0x8000, 0x8003 ) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write) AM_MIRROR(0x1ffc)
71	71	//AM_RANGE( 0xa000, 0xa003 ) AM_DEVREADWRITE_LEGACY("ppi8255_2", i8255a_r, i8255a_w) AM_MIRROR(0x1ffc)
72	72	AM_RANGE( 0xc000, 0xc001 ) AM_DEVREADWRITE_LEGACY("i8275", i8275_r, i8275_w) AM_MIRROR(0x1ffe) // video

src/mess/drivers/b2m.c

r14963	r14964
35	35	AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r,pit8253_w)
36	36	AM_RANGE(0x04, 0x07) AM_DEVREADWRITE("ppi8255_2", i8255_device, read, write)
37	37	AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
38		AM_RANGE(0x0c, 0x0c) AM_READWRITE_LEGACY(b2m_localmachine_r,b2m_localmachine_w)
39		AM_RANGE(0x10, 0x13) AM_READWRITE_LEGACY(b2m_palette_r,b2m_palette_w)
	38	AM_RANGE(0x0c, 0x0c) AM_READWRITE(b2m_localmachine_r,b2m_localmachine_w)
	39	AM_RANGE(0x10, 0x13) AM_READWRITE(b2m_palette_r,b2m_palette_w)
40	40	AM_RANGE(0x14, 0x15) AM_DEVREADWRITE_LEGACY("pic8259", pic8259_r, pic8259_w )
41	41	AM_RANGE(0x18, 0x18) AM_DEVREADWRITE("uart", i8251_device, data_r, data_w)
42	42	AM_RANGE(0x19, 0x19)  AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)
r14963	r14964
51	51	AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r,pit8253_w)
52	52	AM_RANGE(0x04, 0x07) AM_DEVREADWRITE("ppi8255_3", i8255_device, read, write)
53	53	AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
54		AM_RANGE(0x0c, 0x0c) AM_READWRITE_LEGACY(b2m_localmachine_r,b2m_localmachine_w)
55		AM_RANGE(0x10, 0x13) AM_READWRITE_LEGACY(b2m_palette_r,b2m_palette_w)
	54	AM_RANGE(0x0c, 0x0c) AM_READWRITE(b2m_localmachine_r,b2m_localmachine_w)
	55	AM_RANGE(0x10, 0x13) AM_READWRITE(b2m_palette_r,b2m_palette_w)
56	56	AM_RANGE(0x14, 0x15) AM_DEVREADWRITE_LEGACY("pic8259", pic8259_r, pic8259_w )
57	57	AM_RANGE(0x18, 0x18) AM_DEVREADWRITE("uart", i8251_device, data_r, data_w)
58	58	AM_RANGE(0x19, 0x19) AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)

src/mess/drivers/scorpion.c

r14963	r14964
306	306	AM_RANGE(0x003f, 0x003f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_track_r,betadisk_track_w) AM_MIRROR(0xff00)
307	307	AM_RANGE(0x005f, 0x005f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_sector_r,betadisk_sector_w) AM_MIRROR(0xff00)
308	308	AM_RANGE(0x007f, 0x007f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_data_r,betadisk_data_w) AM_MIRROR(0xff00)
309		AM_RANGE(0x00fe, 0x00fe) AM_READWRITE_LEGACY(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xff00) AM_MASK(0xffff)
	309	AM_RANGE(0x00fe, 0x00fe) AM_READWRITE(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xff00) AM_MASK(0xffff)
310	310	AM_RANGE(0x00ff, 0x00ff) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_state_r, betadisk_param_w) AM_MIRROR(0xff00)
311	311	AM_RANGE(0x4000, 0x4000) AM_WRITE_LEGACY(scorpion_port_7ffd_w)  AM_MIRROR(0x3ffd)
312	312	AM_RANGE(0x8000, 0x8000) AM_DEVWRITE_LEGACY("ay8912", ay8910_data_w) AM_MIRROR(0x3ffd)

src/mess/drivers/pmd85.c

r14963	r14964
183	183	/* I/O ports */
184	184
185	185	static ADDRESS_MAP_START( pmd85_io_map, AS_IO, 8, pmd85_state )
186		AM_RANGE( 0x00, 0xff) AM_READWRITE_LEGACY(pmd85_io_r, pmd85_io_w )
	186	AM_RANGE( 0x00, 0xff) AM_READWRITE(pmd85_io_r, pmd85_io_w )
187	187	ADDRESS_MAP_END
188	188
189	189	static ADDRESS_MAP_START( mato_io_map, AS_IO, 8, pmd85_state )
190		AM_RANGE( 0x00, 0xff) AM_READWRITE_LEGACY(mato_io_r, mato_io_w )
	190	AM_RANGE( 0x00, 0xff) AM_READWRITE(mato_io_r, mato_io_w )
191	191	ADDRESS_MAP_END
192	192
193	193	/* memory w/r functions */

src/mess/drivers/spectrum.c

r14963	r14964
292	292	bit 2-0: border colour
293	293	*/
294	294
295		WRITE8_HANDLER(spectrum_port_fe_w)
	295	WRITE8_MEMBER(spectrum_state::spectrum_port_fe_w)
296	296	{
297		spectrum_state *state = space->machine().driver_data<spectrum_state>();
298		device_t *speaker = space->machine().device(SPEAKER_TAG);
	297	device_t *speaker = machine().device(SPEAKER_TAG);
299	298	unsigned char Changed;
300	299
301		Changed = state->m_port_fe_data^data;
	300	Changed = m_port_fe_data^data;
302	301
303	302	/* border colour changed? */
304	303	if ((Changed & 0x07)!=0)
305	304	{
306	305	/* yes - send event */
307		spectrum_EventList_AddItemOffset(space->machine(), 0x0fe, data & 0x07, space->machine().device<cpu_device>("maincpu")->attotime_to_cycles(space->machine().primary_screen->scan_period() * space->machine().primary_screen->vpos()));
	306	spectrum_EventList_AddItemOffset(machine(), 0x0fe, data & 0x07, machine().device<cpu_device>("maincpu")->attotime_to_cycles(machine().primary_screen->scan_period() * machine().primary_screen->vpos()));
308	307	}
309	308
310	309	if ((Changed & (1<<4))!=0)
r14963	r14964
316	315	if ((Changed & (1<<3))!=0)
317	316	{
318	317	/* write cassette data */
319		space->machine().device<cassette_image_device>(CASSETTE_TAG)->output((data & (1<<3)) ? -1.0 : +1.0);
	318	machine().device<cassette_image_device>(CASSETTE_TAG)->output((data & (1<<3)) ? -1.0 : +1.0);
320	319	}
321	320
322		state->m_port_fe_data = data;
	321	m_port_fe_data = data;
323	322	}
324	323
325	324	DIRECT_UPDATE_HANDLER(spectrum_direct)
r14963	r14964
336	335
337	336	/* KT: more accurate keyboard reading */
338	337	/* DJR: Spectrum+ keys added */
339		READ8_HANDLER(spectrum_port_fe_r)
	338	READ8_MEMBER(spectrum_state::spectrum_port_fe_r)
340	339	{
341	340	int lines = offset >> 8;
342	341	int data = 0xff;
343	342
344		int cs_extra1 = input_port_read_safe(space->machine(), "PLUS0", 0xff) & 0x1f;
345		int cs_extra2 = input_port_read_safe(space->machine(), "PLUS1", 0xff) & 0x1f;
346		int cs_extra3 = input_port_read_safe(space->machine(), "PLUS2", 0xff) & 0x1f;
347		int ss_extra1 = input_port_read_safe(space->machine(), "PLUS3", 0xff) & 0x1f;
348		int ss_extra2 = input_port_read_safe(space->machine(), "PLUS4", 0xff) & 0x1f;
	343	int cs_extra1 = input_port_read_safe(machine(), "PLUS0", 0xff) & 0x1f;
	344	int cs_extra2 = input_port_read_safe(machine(), "PLUS1", 0xff) & 0x1f;
	345	int cs_extra3 = input_port_read_safe(machine(), "PLUS2", 0xff) & 0x1f;
	346	int ss_extra1 = input_port_read_safe(machine(), "PLUS3", 0xff) & 0x1f;
	347	int ss_extra2 = input_port_read_safe(machine(), "PLUS4", 0xff) & 0x1f;
349	348
350	349	/* Caps - V */
351	350	if ((lines & 1) == 0)
352	351	{
353		data &= input_port_read(space->machine(), "LINE0");
	352	data &= input_port_read(machine(), "LINE0");
354	353	/* CAPS for extra keys */
355	354	if (cs_extra1 != 0x1f || cs_extra2 != 0x1f || cs_extra3 != 0x1f)
356	355	data &= ~0x01;
r14963	r14964
358	357
359	358	/* A - G */
360	359	if ((lines & 2) == 0)
361		data &= input_port_read(space->machine(), "LINE1");
	360	data &= input_port_read(machine(), "LINE1");
362	361
363	362	/* Q - T */
364	363	if ((lines & 4) == 0)
365		data &= input_port_read(space->machine(), "LINE2");
	364	data &= input_port_read(machine(), "LINE2");
366	365
367	366	/* 1 - 5 */
368	367	if ((lines & 8) == 0)
369		data &= input_port_read(space->machine(), "LINE3") & cs_extra1;
	368	data &= input_port_read(machine(), "LINE3") & cs_extra1;
370	369
371	370	/* 6 - 0 */
372	371	if ((lines & 16) == 0)
373		data &= input_port_read(space->machine(), "LINE4") & cs_extra2;
	372	data &= input_port_read(machine(), "LINE4") & cs_extra2;
374	373
375	374	/* Y - P */
376	375	if ((lines & 32) == 0)
377		data &= input_port_read(space->machine(), "LINE5") & ss_extra1;
	376	data &= input_port_read(machine(), "LINE5") & ss_extra1;
378	377
379	378	/* H - Enter */
380	379	if ((lines & 64) == 0)
381		data &= input_port_read(space->machine(), "LINE6");
	380	data &= input_port_read(machine(), "LINE6");
382	381
383	382	/* B - Space */
384	383	if ((lines & 128) == 0)
385	384	{
386		data &= input_port_read(space->machine(), "LINE7") & cs_extra3 & ss_extra2;
	385	data &= input_port_read(machine(), "LINE7") & cs_extra3 & ss_extra2;
387	386	/* SYMBOL SHIFT for extra keys */
388	387	if (ss_extra1 != 0x1f || ss_extra2 != 0x1f)
389	388	data &= ~0x02;
r14963	r14964
392	391	data |= (0xe0); /* Set bits 5-7 - as reset above */
393	392
394	393	/* cassette input from wav */
395		if ((space->machine().device<cassette_image_device>(CASSETTE_TAG))->input() > 0.0038 )
	394	if ((machine().device<cassette_image_device>(CASSETTE_TAG))->input() > 0.0038 )
396	395	{
397	396	data &= ~0x40;
398	397	}
399	398
400	399	/* Issue 2 Spectrums default to having bits 5, 6 & 7 set.
401	400	Issue 3 Spectrums default to having bits 5 & 7 set and bit 6 reset. */
402		if (input_port_read(space->machine(), "CONFIG") & 0x80)
	401	if (input_port_read(machine(), "CONFIG") & 0x80)
403	402	data ^= (0x40);
404	403
405	404	return data;
406	405	}
407	406
408	407	/* kempston joystick interface */
409		READ8_HANDLER(spectrum_port_1f_r)
	408	READ8_MEMBER(spectrum_state::spectrum_port_1f_r)
410	409	{
411		return input_port_read(space->machine(), "KEMPSTON") & 0x1f;
	410	return input_port_read(machine(), "KEMPSTON") & 0x1f;
412	411	}
413	412
414	413	/* fuller joystick interface */
415		READ8_HANDLER(spectrum_port_7f_r)
	414	READ8_MEMBER(spectrum_state::spectrum_port_7f_r)
416	415	{
417		return input_port_read(space->machine(), "FULLER") | (0xff^0x8f);
	416	return input_port_read(machine(), "FULLER") | (0xff^0x8f);
418	417	}
419	418
420	419	/* mikrogen joystick interface */
421		READ8_HANDLER(spectrum_port_df_r)
	420	READ8_MEMBER(spectrum_state::spectrum_port_df_r)
422	421	{
423		return input_port_read(space->machine(), "MIKROGEN") | (0xff^0x1f);
	422	return input_port_read(machine(), "MIKROGEN") | (0xff^0x1f);
424	423	}
425	424
426		static READ8_HANDLER ( spectrum_port_ula_r )
	425	READ8_MEMBER(spectrum_state::spectrum_port_ula_r)
427	426	{
428		spectrum_state *state = space->machine().driver_data<spectrum_state>();
429		int vpos = space->machine().primary_screen->vpos();
	427	int vpos = machine().primary_screen->vpos();
430	428
431		return vpos<193 ? state->m_video_ram[(vpos&0xf8)<<2]:0xff;
	429	return vpos<193 ? m_video_ram[(vpos&0xf8)<<2]:0xff;
432	430	}
433	431
434	432	/* Memory Maps */
r14963	r14964
443	441	/* ports are not decoded full.
444	442	The function decodes the ports appropriately */
445	443	static ADDRESS_MAP_START (spectrum_io, AS_IO, 8, spectrum_state )
446		AM_RANGE(0x00, 0x00) AM_READWRITE_LEGACY(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xfffe) AM_MASK(0xffff)
447		AM_RANGE(0x1f, 0x1f) AM_READ_LEGACY(spectrum_port_1f_r) AM_MIRROR(0xff00)
448		AM_RANGE(0x7f, 0x7f) AM_READ_LEGACY(spectrum_port_7f_r) AM_MIRROR(0xff00)
449		AM_RANGE(0xdf, 0xdf) AM_READ_LEGACY(spectrum_port_df_r) AM_MIRROR(0xff00)
450		AM_RANGE(0x01, 0x01) AM_READ_LEGACY(spectrum_port_ula_r) AM_MIRROR(0xfffe)
	444	AM_RANGE(0x00, 0x00) AM_READWRITE(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xfffe) AM_MASK(0xffff)
	445	AM_RANGE(0x1f, 0x1f) AM_READ(spectrum_port_1f_r) AM_MIRROR(0xff00)
	446	AM_RANGE(0x7f, 0x7f) AM_READ(spectrum_port_7f_r) AM_MIRROR(0xff00)
	447	AM_RANGE(0xdf, 0xdf) AM_READ(spectrum_port_df_r) AM_MIRROR(0xff00)
	448	AM_RANGE(0x01, 0x01) AM_READ(spectrum_port_ula_r) AM_MIRROR(0xfffe)
451	449	ADDRESS_MAP_END
452	450
453	451	/* Input ports */

src/mess/drivers/ip22.c

r14963	r14964
108	108	PBUS_DMA_t m_PBUS_DMA;
109	109	UINT32 m_nIntCounter;
110	110	UINT8 m_dma_buffer[4096];
	111	DECLARE_READ32_MEMBER(hpc3_pbus6_r);
	112	DECLARE_WRITE32_MEMBER(hpc3_pbus6_w);
	113	DECLARE_READ32_MEMBER(hpc3_hd_enet_r);
	114	DECLARE_WRITE32_MEMBER(hpc3_hd_enet_w);
	115	DECLARE_READ32_MEMBER(hpc3_hd0_r);
	116	DECLARE_WRITE32_MEMBER(hpc3_hd0_w);
	117	DECLARE_READ32_MEMBER(hpc3_pbus4_r);
	118	DECLARE_WRITE32_MEMBER(hpc3_pbus4_w);
	119	DECLARE_READ32_MEMBER(rtc_r);
	120	DECLARE_WRITE32_MEMBER(rtc_w);
	121	DECLARE_WRITE32_MEMBER(ip22_write_ram);
	122	DECLARE_READ32_MEMBER(hal2_r);
	123	DECLARE_WRITE32_MEMBER(hal2_w);
	124	DECLARE_READ32_MEMBER(hpc3_pbusdma_r);
	125	DECLARE_WRITE32_MEMBER(hpc3_pbusdma_w);
	126	DECLARE_READ32_MEMBER(hpc3_unkpbus0_r);
	127	DECLARE_WRITE32_MEMBER(hpc3_unkpbus0_w);
111	128	};
112	129
113	130
r14963	r14964
216	233	}
217	234	#endif
218	235
219		static READ32_HANDLER( hpc3_pbus6_r )
	236	READ32_MEMBER(ip22_state::hpc3_pbus6_r)
220	237	{
221		ip22_state *state = space->machine().driver_data<ip22_state>();
222		device_t *lpt = space->machine().device("lpt_0");
	238	device_t *lpt = machine().device("lpt_0");
223	239	UINT8 ret8;
224		running_machine &machine = space->machine();
225
226	240	switch( offset )
227	241	{
228	242	case 0x004/4:
r14963	r14964
235	249	return ret8;
236	250	case 0x030/4:
237	251	//verboselog(( machine, 2, "Serial 1 Command Transfer Read, 0x1fbd9830: %02x\n", 0x04 );
238		switch(cpu_get_pc(&space->device()))
	252	switch(cpu_get_pc(&space.device()))
239	253	{
240	254	case 0x9fc1d9e4:   // interpreter (ip244415)
241	255	case 0x9fc1d9e0:   // DRC (ip244415)
r14963	r14964
250	264	//verboselog(( machine, 2, "Serial 2 Command Transfer Read, 0x1fbd9838: %02x\n", 0x04 );
251	265	return 0x00000004;
252	266	case 0x40/4:
253		return kbdc8042_8_r(space, 0);
	267	return kbdc8042_8_r(&space, 0);
254	268	case 0x44/4:
255		return kbdc8042_8_r(space, 4);
	269	return kbdc8042_8_r(&space, 4);
256	270	case 0x58/4:
257	271	return 0x20;   // chip rev 1, board rev 0, "Guinness" (Indy) => 0x01 for "Full House" (Indigo2)
258	272	case 0x80/4:
r14963	r14964
268	282	case 0xa8/4:
269	283	case 0xac/4:
270	284	//      mame_printf_info("INT3: r @ %x mask %08x (PC=%x)\n", offset*4, mem_mask, activecpu_get_pc());
271		return state->m_int3_regs[offset-0x80/4];
	285	return m_int3_regs[offset-0x80/4];
272	286	case 0xb0/4:
273		ret8 = pit8253_r(machine.device("pit8254"), 0);
	287	ret8 = pit8253_r(machine().device("pit8254"), 0);
274	288	//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 0 Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
275	289	return ret8;
276	290	case 0xb4/4:
277		ret8 = pit8253_r(machine.device("pit8254"), 1);
	291	ret8 = pit8253_r(machine().device("pit8254"), 1);
278	292	//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 1 Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
279	293	return ret8;
280	294	case 0xb8/4:
281		ret8 = pit8253_r(machine.device("pit8254"), 2);
	295	ret8 = pit8253_r(machine().device("pit8254"), 2);
282	296	//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 2 Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
283	297	return ret8;
284	298	case 0xbc/4:
285		ret8 = pit8253_r(machine.device("pit8254"), 3);
	299	ret8 = pit8253_r(machine().device("pit8254"), 3);
286	300	//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Control Word Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
287	301	return ret8;
288	302	default:
r14963	r14964
292	306	return 0;
293	307	}
294	308
295		static WRITE32_HANDLER( hpc3_pbus6_w )
	309	WRITE32_MEMBER(ip22_state::hpc3_pbus6_w)
296	310	{
297		ip22_state *state = space->machine().driver_data<ip22_state>();
298		device_t *lpt = space->machine().device("lpt_0");
	311	device_t *lpt = machine().device("lpt_0");
299	312	char cChar;
300		running_machine &machine = space->machine();
301	313
302	314	switch( offset )
303	315	{
304	316	case 0x004/4:
305	317	//verboselog(( machine, 0, "Parallel Control Write: %08x\n", data );
306	318	pc_lpt_control_w(lpt, 0, data ^ 0x0d);
307		//state->m_nIOC_ParCntl = data;
	319	//m_nIOC_ParCntl = data;
308	320	break;
309	321	case 0x030/4:
310	322	if( ( data & 0x000000ff ) >= 0x20 )
r14963	r14964
337	349	}
338	350	break;
339	351	case 0x40/4:
340		kbdc8042_8_w(space, 0, data);
	352	kbdc8042_8_w(&space, 0, data);
341	353	break;
342	354	case 0x44/4:
343		kbdc8042_8_w(space, 4, data);
	355	kbdc8042_8_w(&space, 4, data);
344	356	break;
345	357	case 0x80/4:
346	358	case 0x84/4:
r14963	r14964
353	365	case 0xa0/4:
354	366	case 0xa4/4:
355	367	//      mame_printf_info("INT3: w %x to %x (reg %d) mask %08x (PC=%x)\n", data, offset*4, offset-0x80/4, mem_mask, activecpu_get_pc());
356		state->m_int3_regs[offset-0x80/4] = data;
	368	m_int3_regs[offset-0x80/4] = data;
357	369
358	370	// if no local0 interrupts now, clear the input to the CPU
359		if ((state->m_int3_regs[0] & state->m_int3_regs[1]) == 0)
	371	if ((m_int3_regs[0] & m_int3_regs[1]) == 0)
360	372	{
361		cputag_set_input_line(machine, "maincpu", MIPS3_IRQ0, CLEAR_LINE);
	373	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ0, CLEAR_LINE);
362	374	}
363	375	else
364	376	{
365		cputag_set_input_line(machine, "maincpu", MIPS3_IRQ0, ASSERT_LINE);
	377	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ0, ASSERT_LINE);
366	378	}
367	379
368	380	// if no local1 interrupts now, clear the input to the CPU
369		if ((state->m_int3_regs[2] & state->m_int3_regs[3]) == 0)
	381	if ((m_int3_regs[2] & m_int3_regs[3]) == 0)
370	382	{
371		cputag_set_input_line(machine, "maincpu", MIPS3_IRQ1, CLEAR_LINE);
	383	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ1, CLEAR_LINE);
372	384	}
373	385	else
374	386	{
375		cputag_set_input_line(machine, "maincpu", MIPS3_IRQ1, ASSERT_LINE);
	387	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ1, ASSERT_LINE);
376	388	}
377	389	break;
378	390	case 0xb0/4:
379	391	//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 0 Register Write: 0x%08x (%08x)\n", data, mem_mask );
380		pit8253_w(machine.device("pit8254"), 0, data & 0x000000ff);
	392	pit8253_w(machine().device("pit8254"), 0, data & 0x000000ff);
381	393	return;
382	394	case 0xb4/4:
383	395	//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 1 Register Write: 0x%08x (%08x)\n", data, mem_mask );
384		pit8253_w(machine.device("pit8254"), 1, data & 0x000000ff);
	396	pit8253_w(machine().device("pit8254"), 1, data & 0x000000ff);
385	397	return;
386	398	case 0xb8/4:
387	399	//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 2 Register Write: 0x%08x (%08x)\n", data, mem_mask );
388		pit8253_w(machine.device("pit8254"), 2, data & 0x000000ff);
	400	pit8253_w(machine().device("pit8254"), 2, data & 0x000000ff);
389	401	return;
390	402	case 0xbc/4:
391	403	//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Control Word Register Write: 0x%08x (%08x)\n", data, mem_mask );
392		pit8253_w(machine.device("pit8254"), 3, data & 0x000000ff);
	404	pit8253_w(machine().device("pit8254"), 3, data & 0x000000ff);
393	405	return;
394	406	default:
395	407	//verboselog(( machine, 0, "Unknown HPC PBUS6 Write: 0x%08x: 0x%08x (%08x)\n", 0x1fbd9800 + ( offset << 2 ), data, mem_mask );
r14963	r14964
401	413	//UINT32 nHPC3_hd0_regs[0x20];
402	414	//UINT32 nHPC3_hd1_regs[0x20];
403	415
404		static READ32_HANDLER( hpc3_hd_enet_r )
	416	READ32_MEMBER(ip22_state::hpc3_hd_enet_r)
405	417	{
406		ip22_state *state = space->machine().driver_data<ip22_state>();
407		//running_machine &machine = space->machine();
	418	//running_machine &machine = machine();
408	419
409	420	switch( offset )
410	421	{
411	422	case 0x0004/4:
412		//verboselog((machine, 0, "HPC3 SCSI0DESC Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, state->m_HPC3.nSCSI0Descriptor );
413		return state->m_HPC3.nSCSI0Descriptor;
	423	//verboselog((machine, 0, "HPC3 SCSI0DESC Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, m_HPC3.nSCSI0Descriptor );
	424	return m_HPC3.nSCSI0Descriptor;
414	425	case 0x1004/4:
415		//verboselog((machine, 0, "HPC3 SCSI0DMACTRL Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, state->m_HPC3.nSCSI0DMACtrl );
416		return state->m_HPC3.nSCSI0DMACtrl;
	426	//verboselog((machine, 0, "HPC3 SCSI0DMACTRL Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, m_HPC3.nSCSI0DMACtrl );
	427	return m_HPC3.nSCSI0DMACtrl;
417	428	case 0x4000/4:
418		//verboselog((machine, 2, "HPC3 ENETR CBP Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, state->m_HPC3.nenetr_nbdp );
419		return state->m_HPC3.nenetr_cbp;
	429	//verboselog((machine, 2, "HPC3 ENETR CBP Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, m_HPC3.nenetr_nbdp );
	430	return m_HPC3.nenetr_cbp;
420	431	case 0x4004/4:
421		//verboselog((machine, 2, "HPC3 ENETR NBDP Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, state->m_HPC3.nenetr_nbdp );
422		return state->m_HPC3.nenetr_nbdp;
	432	//verboselog((machine, 2, "HPC3 ENETR NBDP Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, m_HPC3.nenetr_nbdp );
	433	return m_HPC3.nenetr_nbdp;
423	434	default:
424	435	//verboselog((machine, 0, "Unknown HPC3 ENET/HDx Read: %08x (%08x)\n", 0x1fb90000 + ( offset << 2 ), mem_mask );
425	436	return 0;
r14963	r14964
427	438	return 0;
428	439	}
429	440
430		static WRITE32_HANDLER( hpc3_hd_enet_w )
	441	WRITE32_MEMBER(ip22_state::hpc3_hd_enet_w)
431	442	{
432		ip22_state *state = space->machine().driver_data<ip22_state>();
433		//running_machine &machine = space->machine();
	443	//running_machine &machine = machine();
434	444
435	445	switch( offset )
436	446	{
437	447	case 0x0004/4:
438	448	//verboselog((machine, 2, "HPC3 SCSI0DESC Write: %08x\n", data );
439		state->m_HPC3.nSCSI0Descriptor = data;
	449	m_HPC3.nSCSI0Descriptor = data;
440	450	break;
441	451	case 0x1004/4:
442	452	//verboselog((machine, 2, "HPC3 SCSI0DMACTRL Write: %08x\n", data );
443		state->m_HPC3.nSCSI0DMACtrl = data;
	453	m_HPC3.nSCSI0DMACtrl = data;
444	454	break;
445	455	case 0x4000/4:
446	456	//verboselog((machine, 2, "HPC3 ENETR CBP Write: %08x\n", data );
447		state->m_HPC3.nenetr_cbp = data;
	457	m_HPC3.nenetr_cbp = data;
448	458	break;
449	459	case 0x4004/4:
450	460	//verboselog((machine, 2, "HPC3 ENETR NBDP Write: %08x\n", data );
451		state->m_HPC3.nenetr_nbdp = data;
	461	m_HPC3.nenetr_nbdp = data;
452	462	break;
453	463	default:
454	464	//verboselog((machine, 0, "Unknown HPC3 ENET/HDx write: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2 ), mem_mask, data );
r14963	r14964
456	466	}
457	467	}
458	468
459		static READ32_HANDLER( hpc3_hd0_r )
	469	READ32_MEMBER(ip22_state::hpc3_hd0_r)
460	470	{
461		//running_machine &machine = space->machine();
	471	//running_machine &machine = machine();
462	472
463	473	switch( offset )
464	474	{
r14963	r14964
467	477	//      //verboselog((machine, 2, "HPC3 HD0 Status Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, nHPC3_hd0_regs[0x17] );
468	478	if (ACCESSING_BITS_0_7)
469	479	{
470		return wd33c93_r( space, 0 );
	480	return wd33c93_r( &space, 0 );
471	481	}
472	482	else
473	483	{
r14963	r14964
478	488	//      //verboselog((machine, 2, "HPC3 HD0 Register Read: %08x (%08x): %08x\n", 0x1fb90000 + ( offset << 2), mem_mask, nHPC3_hd0_regs[nHPC3_hd0_register] );
479	489	if (ACCESSING_BITS_0_7)
480	490	{
481		return wd33c93_r( space, 1 );
	491	return wd33c93_r( &space, 1 );
482	492	}
483	493	else
484	494	{
485	495	return 0;
486	496	}
487	497	default:
488		//verboselog((machine, 0, "Unknown HPC3 HD0 Read: %08x (%08x) [%x] PC=%x\n", 0x1fbc0000 + ( offset << 2 ), mem_mask, offset, cpu_get_pc(&space->device()) );
	498	//verboselog((machine, 0, "Unknown HPC3 HD0 Read: %08x (%08x) [%x] PC=%x\n", 0x1fbc0000 + ( offset << 2 ), mem_mask, offset, cpu_get_pc(&space.device()) );
489	499	return 0;
490	500	}
491	501	return 0;
492	502	}
493	503
494		static WRITE32_HANDLER( hpc3_hd0_w )
	504	WRITE32_MEMBER(ip22_state::hpc3_hd0_w)
495	505	{
496		//running_machine &machine = space->machine();
	506	//running_machine &machine = machine();
497	507
498	508	switch( offset )
499	509	{
r14963	r14964
502	512	//      //verboselog((machine, 2, "HPC3 HD0 Register Select Write: %08x\n", data );
503	513	if (ACCESSING_BITS_0_7)
504	514	{
505		wd33c93_w( space, 0, data & 0x000000ff );
	515	wd33c93_w( &space, 0, data & 0x000000ff );
506	516	}
507	517	break;
508	518	case 0x0004/4:
r14963	r14964
510	520	//      //verboselog((machine, 2, "HPC3 HD0 Register %d Write: %08x\n", nHPC3_hd0_register, data );
511	521	if (ACCESSING_BITS_0_7)
512	522	{
513		wd33c93_w( space, 1,  data & 0x000000ff );
	523	wd33c93_w( &space, 1,  data & 0x000000ff );
514	524	}
515	525	break;
516	526	default:
r14963	r14964
520	530	}
521	531
522	532
523		static READ32_HANDLER( hpc3_pbus4_r )
	533	READ32_MEMBER(ip22_state::hpc3_pbus4_r)
524	534	{
525		ip22_state *state = space->machine().driver_data<ip22_state>();
526		//running_machine &machine = space->machine();
	535	//running_machine &machine = machine();
527	536
528	537	switch( offset )
529	538	{
530	539	case 0x0004/4:
531		//verboselog((machine, 2, "HPC3 PBUS4 Unknown 0 Read: (%08x): %08x\n", mem_mask, state->m_HPC3.nunk0 );
532		return state->m_HPC3.nunk0;
	540	//verboselog((machine, 2, "HPC3 PBUS4 Unknown 0 Read: (%08x): %08x\n", mem_mask, m_HPC3.nunk0 );
	541	return m_HPC3.nunk0;
533	542	case 0x000c/4:
534		//verboselog((machine, 2, "Interrupt Controller(?) Read: (%08x): %08x\n", mem_mask, state->m_HPC3.nIC_Unk0 );
535		return state->m_HPC3.nIC_Unk0;
	543	//verboselog((machine, 2, "Interrupt Controller(?) Read: (%08x): %08x\n", mem_mask, m_HPC3.nIC_Unk0 );
	544	return m_HPC3.nIC_Unk0;
536	545	case 0x0014/4:
537		//verboselog((machine, 2, "HPC3 PBUS4 Unknown 1 Read: (%08x): %08x\n", mem_mask, state->m_HPC3.nunk1 );
538		return state->m_HPC3.nunk1;
	546	//verboselog((machine, 2, "HPC3 PBUS4 Unknown 1 Read: (%08x): %08x\n", mem_mask, m_HPC3.nunk1 );
	547	return m_HPC3.nunk1;
539	548	default:
540	549	//verboselog((machine, 0, "Unknown HPC3 PBUS4 Read: %08x (%08x)\n", 0x1fbd9000 + ( offset << 2 ), mem_mask );
541	550	return 0;
r14963	r14964
543	552	return 0;
544	553	}
545	554
546		static WRITE32_HANDLER( hpc3_pbus4_w )
	555	WRITE32_MEMBER(ip22_state::hpc3_pbus4_w)
547	556	{
548		ip22_state *state = space->machine().driver_data<ip22_state>();
549		//running_machine &machine = space->machine();
	557	//running_machine &machine = machine();
550	558
551	559	switch( offset )
552	560	{
553	561	case 0x0004/4:
554	562	//verboselog((machine, 2, "HPC3 PBUS4 Unknown 0 Write: %08x (%08x)\n", data, mem_mask );
555		state->m_HPC3.nunk0 = data;
	563	m_HPC3.nunk0 = data;
556	564	break;
557	565	case 0x000c/4:
558	566	//verboselog((machine, 2, "Interrupt Controller(?) Write: (%08x): %08x\n", mem_mask, data );
559		state->m_HPC3.nIC_Unk0 = data;
	567	m_HPC3.nIC_Unk0 = data;
560	568	break;
561	569	case 0x0014/4:
562	570	//verboselog((machine, 2, "HPC3 PBUS4 Unknown 1 Write: %08x (%08x)\n", data, mem_mask );
563		state->m_HPC3.nunk1 = data;
	571	m_HPC3.nunk1 = data;
564	572	break;
565	573	default:
566	574	//verboselog((machine, 0, "Unknown HPC3 PBUS4 Write: %08x (%08x): %08x\n", 0x1fbd9000 + ( offset << 2 ), mem_mask, data );
r14963	r14964
600	608	#define RTC_RAMMSB   state->m_RTC.nRegs[0x51]
601	609	#define RTC_WRITECNT   state->m_RTC.nRegs[0x5e]
602	610
603		static READ32_HANDLER( rtc_r )
	611	READ32_MEMBER(ip22_state::rtc_r)
604	612	{
605		ip22_state *state = space->machine().driver_data<ip22_state>();
606		//running_machine &machine = space->machine();
	613	ip22_state *state = machine().driver_data<ip22_state>();
607	614
608		//  mame_printf_info("RTC_R: offset %x = %x (PC=%x)\n", offset, state->m_RTC.nRegs[offset], activecpu_get_pc());
	615	//  mame_printf_info("RTC_R: offset %x = %x (PC=%x)\n", offset, m_RTC.nRegs[offset], activecpu_get_pc());
609	616
610	617	if( offset <= 0x0d )
611	618	{
r14963	r14964
660	667	}
661	668	if( offset >= 0x0e && offset < 0x40 )
662	669	{
663		return state->m_RTC.nRegs[offset];
	670	return m_RTC.nRegs[offset];
664	671	}
665	672	if( offset >= 0x40 && offset < 0x80 && !( RTC_REGISTERA & 0x10 ) )
666	673	{
667		return state->m_RTC.nUserRAM[offset - 0x40];
	674	return m_RTC.nUserRAM[offset - 0x40];
668	675	}
669	676	if( offset >= 0x40 && offset < 0x80 && ( RTC_REGISTERA & 0x10 ) )
670	677	{
r14963	r14964
719	726	//verboselog((machine, 3, "RTC RAM MSB Read: %02x \n", RTC_RAMMSB );
720	727	return RTC_RAMMSB;
721	728	case 0x0053:
722		return state->m_RTC.nRAM[ ( RTC_RAMMSB << 8 ) | RTC_RAMLSB ];
	729	return m_RTC.nRAM[ ( RTC_RAMMSB << 8 ) | RTC_RAMLSB ];
723	730	case 0x005e:
724	731	return RTC_WRITECNT;
725	732	default:
r14963	r14964
729	736	}
730	737	if( offset >= 0x80 )
731	738	{
732		return state->m_RTC.nUserRAM[ offset - 0x80 ];
	739	return m_RTC.nUserRAM[ offset - 0x80 ];
733	740	}
734	741	return 0;
735	742	}
736	743
737		static WRITE32_HANDLER( rtc_w )
	744	WRITE32_MEMBER(ip22_state::rtc_w)
738	745	{
739		ip22_state *state = space->machine().driver_data<ip22_state>();
740		//running_machine &machine = space->machine();
741
	746	//running_machine &machine = machine();
	747	ip22_state *state = machine().driver_data<ip22_state>();
742	748	RTC_WRITECNT++;
743	749
744	750	//  mame_printf_info("RTC_W: offset %x => %x (PC=%x)\n", data, offset, activecpu_get_pc());
r14963	r14964
808	814	}
809	815	if( offset >= 0x0e && offset < 0x40 )
810	816	{
811		state->m_RTC.nRegs[offset] = data;
	817	m_RTC.nRegs[offset] = data;
812	818	return;
813	819	}
814	820	if( offset >= 0x40 && offset < 0x80 && !( RTC_REGISTERA & 0x10 ) )
815	821	{
816		state->m_RTC.nUserRAM[offset - 0x40] = data;
	822	m_RTC.nUserRAM[offset - 0x40] = data;
817	823	return;
818	824	}
819	825	if( offset >= 0x40 && offset < 0x80 && ( RTC_REGISTERA & 0x10 ) )
r14963	r14964
866	872	RTC_RAMMSB = data;
867	873	break;
868	874	case 0x0053:
869		state->m_RTC.nRAM[ ( RTC_RAMMSB << 8 ) | RTC_RAMLSB ] = data;
	875	m_RTC.nRAM[ ( RTC_RAMMSB << 8 ) | RTC_RAMLSB ] = data;
870	876	break;
871	877	default:
872	878	//verboselog((machine, 3, "Unknown RTC Ext. Reg. Write: %02x: %02x\n", offset, data );
r14963	r14964
875	881	}
876	882	if( offset >= 0x80 )
877	883	{
878		state->m_RTC.nUserRAM[ offset - 0x80 ] = data;
	884	m_RTC.nUserRAM[ offset - 0x80 ] = data;
879	885	}
880	886	}
881	887
882	888	// a bit hackish, but makes the memory detection work properly and allows a big cleanup of the mapping
883		static WRITE32_HANDLER( ip22_write_ram )
	889	WRITE32_MEMBER(ip22_state::ip22_write_ram)
884	890	{
885		ip22_state *state = space->machine().driver_data<ip22_state>();
886	891	// if banks 2 or 3 are enabled, do nothing, we don't support that much memory
887		if (sgi_mc_r(space, 0xc8/4, 0xffffffff) & 0x10001000)
	892	if (sgi_mc_r(&space, 0xc8/4, 0xffffffff) & 0x10001000)
888	893	{
889	894	// a random perturbation so the memory test fails
890	895	data ^= 0xffffffff;
891	896	}
892	897
893	898	// if banks 0 or 1 have 2 subbanks, also kill it, we only want 128 MB
894		if (sgi_mc_r(space, 0xc0/4, 0xffffffff) & 0x40004000)
	899	if (sgi_mc_r(&space, 0xc0/4, 0xffffffff) & 0x40004000)
895	900	{
896	901	// a random perturbation so the memory test fails
897	902	data ^= 0xffffffff;
898	903	}
899		COMBINE_DATA(&state->m_mainram[offset]);
	904	COMBINE_DATA(&m_mainram[offset]);
900	905	}
901	906
902	907
r14963	r14964
912	917	#define H2_ISR_GLOBAL_RESET   0x08
913	918	#define H2_ISR_CODEC_RESET   0x10
914	919
915		static READ32_HANDLER( hal2_r )
	920	READ32_MEMBER(ip22_state::hal2_r)
916	921	{
917		//running_machine &machine = space->machine();
	922	//running_machine &machine = machine();
918	923
919	924	switch( offset )
920	925	{
r14963	r14964
929	934	return 0;
930	935	}
931	936
932		static WRITE32_HANDLER( hal2_w )
	937	WRITE32_MEMBER(ip22_state::hal2_w)
933	938	{
934		ip22_state *state = space->machine().driver_data<ip22_state>();
935		//running_machine &machine = space->machine();
	939	//running_machine &machine = machine();
936	940
937	941	switch( offset )
938	942	{
r14963	r14964
949	953	break;
950	954	case 0x0030/4:
951	955	//verboselog((machine, 0, "HAL2 Indirect Address Register Write: 0x%08x (%08x)\n", data, mem_mask );
952		state->m_HAL2.nIAR = data;
	956	m_HAL2.nIAR = data;
953	957	switch( data & H2_IAR_TYPE )
954	958	{
955	959	case 0x1000:
r14963	r14964
1026	1030	break;
1027	1031	case 0x0040/4:
1028	1032	//verboselog((machine, 0, "HAL2 Indirect Data Register 0 Write: 0x%08x (%08x)\n", data, mem_mask );
1029		state->m_HAL2.nIDR[0] = data;
	1033	m_HAL2.nIDR[0] = data;
1030	1034	return;
1031	1035	case 0x0050/4:
1032	1036	//verboselog((machine, 0, "HAL2 Indirect Data Register 1 Write: 0x%08x (%08x)\n", data, mem_mask );
1033		state->m_HAL2.nIDR[1] = data;
	1037	m_HAL2.nIDR[1] = data;
1034	1038	return;
1035	1039	case 0x0060/4:
1036	1040	//verboselog((machine, 0, "HAL2 Indirect Data Register 2 Write: 0x%08x (%08x)\n", data, mem_mask );
1037		state->m_HAL2.nIDR[2] = data;
	1041	m_HAL2.nIDR[2] = data;
1038	1042	return;
1039	1043	case 0x0070/4:
1040	1044	//verboselog((machine, 0, "HAL2 Indirect Data Register 3 Write: 0x%08x (%08x)\n", data, mem_mask );
1041		state->m_HAL2.nIDR[3] = data;
	1045	m_HAL2.nIDR[3] = data;
1042	1046	return;
1043	1047	}
1044	1048	//verboselog((machine, 0, "Unknown HAL2 write: 0x%08x: 0x%08x (%08x)\n", 0x1fbd8000 + offset*4, data, mem_mask );
r14963	r14964
1097	1101	#endif
1098	1102	}
1099	1103
1100		static READ32_HANDLER( hpc3_pbusdma_r )
	1104	READ32_MEMBER(ip22_state::hpc3_pbusdma_r)
1101	1105	{
1102	1106	//UINT32 channel = offset / (0x2000/4);
1103		//verboselog((space->machine(), 0, "PBUS DMA Channel %d Read: 0x%08x (%08x)\n", channel, 0x1fb80000 + offset*4, mem_mask );
	1107	//verboselog((machine(), 0, "PBUS DMA Channel %d Read: 0x%08x (%08x)\n", channel, 0x1fb80000 + offset*4, mem_mask );
1104	1108	return 0;
1105	1109	}
1106	1110
1107		static WRITE32_HANDLER( hpc3_pbusdma_w )
	1111	WRITE32_MEMBER(ip22_state::hpc3_pbusdma_w)
1108	1112	{
1109		ip22_state *state = space->machine().driver_data<ip22_state>();
1110	1113	UINT32 channel = offset / (0x2000/4);
1111		running_machine &machine = space->machine();
1112	1114
1113	1115	switch( offset & 0x07ff )
1114	1116	{
r14963	r14964
1119	1121	//verboselog((machine, 0, "PBUS DMA Channel %d Descriptor Pointer Write: 0x%08x\n", channel, data );
1120	1122	if( channel == 1 )
1121	1123	{
1122		state->m_PBUS_DMA.nDescPtr = data;
1123		state->m_PBUS_DMA.nCurPtr = state->m_mainram[(state->m_PBUS_DMA.nDescPtr - 0x08000000)/4];
1124		state->m_PBUS_DMA.nWordsLeft = state->m_mainram[(state->m_PBUS_DMA.nDescPtr - 0x08000000)/4+1];
1125		state->m_PBUS_DMA.nNextPtr = state->m_mainram[(state->m_PBUS_DMA.nDescPtr - 0x08000000)/4+2];
1126		//verboselog((machine, 0, "nPBUS_DMA_DescPtr = %08x\n", state->m_PBUS_DMA.nDescPtr );
1127		//verboselog((machine, 0, "nPBUS_DMA_CurPtr = %08x\n", state->m_PBUS_DMA.nCurPtr );
1128		//verboselog((machine, 0, "nPBUS_DMA_WordsLeft = %08x\n", state->m_PBUS_DMA.nWordsLeft );
1129		//verboselog((machine, 0, "nPBUS_DMA_NextPtr = %08x\n", state->m_PBUS_DMA.nNextPtr );
	1124	m_PBUS_DMA.nDescPtr = data;
	1125	m_PBUS_DMA.nCurPtr = m_mainram[(m_PBUS_DMA.nDescPtr - 0x08000000)/4];
	1126	m_PBUS_DMA.nWordsLeft = m_mainram[(m_PBUS_DMA.nDescPtr - 0x08000000)/4+1];
	1127	m_PBUS_DMA.nNextPtr = m_mainram[(m_PBUS_DMA.nDescPtr - 0x08000000)/4+2];
	1128	//verboselog((machine, 0, "nPBUS_DMA_DescPtr = %08x\n", m_PBUS_DMA.nDescPtr );
	1129	//verboselog((machine, 0, "nPBUS_DMA_CurPtr = %08x\n", m_PBUS_DMA.nCurPtr );
	1130	//verboselog((machine, 0, "nPBUS_DMA_WordsLeft = %08x\n", m_PBUS_DMA.nWordsLeft );
	1131	//verboselog((machine, 0, "nPBUS_DMA_NextPtr = %08x\n", m_PBUS_DMA.nNextPtr );
1130	1132	}
1131	1133	return;
1132	1134	case 0x1000/4:
r14963	r14964
1164	1166	//verboselog((machine, 0, "    FIFO End: Rowe %04x\n", ( data & PBUS_CTRL_FIFO_END ) >> 24 );
1165	1167	if( ( data & PBUS_CTRL_DMASTART ) || ( data & PBUS_CTRL_LOAD_EN ) )
1166	1168	{
1167		machine.scheduler().timer_set(attotime::from_hz(44100), FUNC(ip22_dma));
1168		state->m_PBUS_DMA.nActive = 1;
	1169	machine().scheduler().timer_set(attotime::from_hz(44100), FUNC(ip22_dma));
	1170	m_PBUS_DMA.nActive = 1;
1169	1171	}
1170	1172	return;
1171	1173	}
1172	1174	//verboselog((machine, 0, "Unknown PBUS DMA Channel %d Write: 0x%08x: 0x%08x (%08x)\n", channel, 0x1fb80000 + offset*4, data, mem_mask );
1173	1175	}
1174	1176
1175		static READ32_HANDLER( hpc3_unkpbus0_r )
	1177	READ32_MEMBER(ip22_state::hpc3_unkpbus0_r)
1176	1178	{
1177		//ip22_state *state = space->machine().driver_data<ip22_state>();
1178	1179	return 0;
1179		////verboselog((space->machine(), 0, "Unknown PBUS Read: 0x%08x (%08x)\n", 0x1fbc8000 + offset*4, mem_mask );
1180		//return state->m_unkpbus0[offset];
	1180	////verboselog((machine(), 0, "Unknown PBUS Read: 0x%08x (%08x)\n", 0x1fbc8000 + offset*4, mem_mask );
	1181	//return m_unkpbus0[offset];
1181	1182	}
1182	1183
1183		static WRITE32_HANDLER( hpc3_unkpbus0_w )
	1184	WRITE32_MEMBER(ip22_state::hpc3_unkpbus0_w)
1184	1185	{
1185		//ip22_state *state = space->machine().driver_data<ip22_state>();
1186		////verboselog((space->machine(), 0, "Unknown PBUS Write: 0x%08x = 0x%08x (%08x)\n", 0x1fbc8000 + offset*4, data, mem_mask );
1187		//COMBINE_DATA(&state->m_unkpbus0[offset]);
	1186	////verboselog((machine(), 0, "Unknown PBUS Write: 0x%08x = 0x%08x (%08x)\n", 0x1fbc8000 + offset*4, data, mem_mask );
	1187	//COMBINE_DATA(&m_unkpbus0[offset]);
1188	1188	}
1189	1189
1190	1190	static ADDRESS_MAP_START( ip225015_map, AS_PROGRAM, 32, ip22_state )
1191	1191	AM_RANGE( 0x00000000, 0x0007ffff ) AM_RAMBANK( "bank1" )   /* mirror of first 512k of main RAM */
1192		AM_RANGE( 0x08000000, 0x0fffffff ) AM_SHARE("share1") AM_SHARE("mainram") AM_RAM_WRITE_LEGACY(ip22_write_ram)      /* 128 MB of main RAM */
	1192	AM_RANGE( 0x08000000, 0x0fffffff ) AM_SHARE("share1") AM_SHARE("mainram") AM_RAM_WRITE(ip22_write_ram)      /* 128 MB of main RAM */
1193	1193	AM_RANGE( 0x1f0f0000, 0x1f0f1fff ) AM_READWRITE_LEGACY(newport_rex3_r, newport_rex3_w )
1194	1194	AM_RANGE( 0x1fa00000, 0x1fa1ffff ) AM_READWRITE_LEGACY(sgi_mc_r, sgi_mc_w )
1195		AM_RANGE( 0x1fb90000, 0x1fb9ffff ) AM_READWRITE_LEGACY(hpc3_hd_enet_r, hpc3_hd_enet_w )
	1195	AM_RANGE( 0x1fb90000, 0x1fb9ffff ) AM_READWRITE(hpc3_hd_enet_r, hpc3_hd_enet_w )
1196	1196	AM_RANGE( 0x1fbb0000, 0x1fbb0003 ) AM_RAM   /* unknown, but read a lot and discarded */
1197		AM_RANGE( 0x1fbc0000, 0x1fbc7fff ) AM_READWRITE_LEGACY(hpc3_hd0_r, hpc3_hd0_w )
1198		AM_RANGE( 0x1fbc8000, 0x1fbcffff ) AM_READWRITE_LEGACY(hpc3_unkpbus0_r, hpc3_unkpbus0_w ) AM_SHARE("unkpbus0")
1199		AM_RANGE( 0x1fb80000, 0x1fb8ffff ) AM_READWRITE_LEGACY(hpc3_pbusdma_r, hpc3_pbusdma_w )
1200		AM_RANGE( 0x1fbd8000, 0x1fbd83ff ) AM_READWRITE_LEGACY(hal2_r, hal2_w )
	1197	AM_RANGE( 0x1fbc0000, 0x1fbc7fff ) AM_READWRITE(hpc3_hd0_r, hpc3_hd0_w )
	1198	AM_RANGE( 0x1fbc8000, 0x1fbcffff ) AM_READWRITE(hpc3_unkpbus0_r, hpc3_unkpbus0_w ) AM_SHARE("unkpbus0")
	1199	AM_RANGE( 0x1fb80000, 0x1fb8ffff ) AM_READWRITE(hpc3_pbusdma_r, hpc3_pbusdma_w )
	1200	AM_RANGE( 0x1fbd8000, 0x1fbd83ff ) AM_READWRITE(hal2_r, hal2_w )
1201	1201	AM_RANGE( 0x1fbd8400, 0x1fbd87ff ) AM_RAM /* hack */
1202		AM_RANGE( 0x1fbd9000, 0x1fbd93ff ) AM_READWRITE_LEGACY(hpc3_pbus4_r, hpc3_pbus4_w )
1203		AM_RANGE( 0x1fbd9800, 0x1fbd9bff ) AM_READWRITE_LEGACY(hpc3_pbus6_r, hpc3_pbus6_w )
	1202	AM_RANGE( 0x1fbd9000, 0x1fbd93ff ) AM_READWRITE(hpc3_pbus4_r, hpc3_pbus4_w )
	1203	AM_RANGE( 0x1fbd9800, 0x1fbd9bff ) AM_READWRITE(hpc3_pbus6_r, hpc3_pbus6_w )
1204	1204	AM_RANGE( 0x1fbdc000, 0x1fbdc7ff ) AM_RAM
1205	1205	AM_RANGE( 0x1fbdd000, 0x1fbdd3ff ) AM_RAM
1206		AM_RANGE( 0x1fbe0000, 0x1fbe04ff ) AM_READWRITE_LEGACY(rtc_r, rtc_w )
	1206	AM_RANGE( 0x1fbe0000, 0x1fbe04ff ) AM_READWRITE(rtc_r, rtc_w )
1207	1207	AM_RANGE( 0x1fc00000, 0x1fc7ffff ) AM_ROM AM_REGION( "user1", 0 )
1208		AM_RANGE( 0x20000000, 0x27ffffff ) AM_SHARE("share1") AM_RAM_WRITE_LEGACY(ip22_write_ram)
	1208	AM_RANGE( 0x20000000, 0x27ffffff ) AM_SHARE("share1") AM_RAM_WRITE(ip22_write_ram)
1209	1209	ADDRESS_MAP_END
1210	1210
1211	1211

src/mess/drivers/spec128.c

r14963	r14964
235	235	}
236	236
237	237	static ADDRESS_MAP_START (spectrum_128_io, AS_IO, 8, spectrum_state )
238		AM_RANGE(0x0000, 0x0000) AM_READWRITE_LEGACY(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xfffe) AM_MASK(0xffff)
239		AM_RANGE(0x001f, 0x001f) AM_READ_LEGACY(spectrum_port_1f_r) AM_MIRROR(0xff00)
240		AM_RANGE(0x007f, 0x007f) AM_READ_LEGACY(spectrum_port_7f_r) AM_MIRROR(0xff00)
241		AM_RANGE(0x00df, 0x00df) AM_READ_LEGACY(spectrum_port_df_r) AM_MIRROR(0xff00)
	238	AM_RANGE(0x0000, 0x0000) AM_READWRITE(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xfffe) AM_MASK(0xffff)
	239	AM_RANGE(0x001f, 0x001f) AM_READ(spectrum_port_1f_r) AM_MIRROR(0xff00)
	240	AM_RANGE(0x007f, 0x007f) AM_READ(spectrum_port_7f_r) AM_MIRROR(0xff00)
	241	AM_RANGE(0x00df, 0x00df) AM_READ(spectrum_port_df_r) AM_MIRROR(0xff00)
242	242	AM_RANGE(0x4000, 0x4000) AM_WRITE_LEGACY(spectrum_128_port_7ffd_w) AM_MIRROR(0x3ffd)
243	243	AM_RANGE(0x8000, 0x8000) AM_DEVWRITE_LEGACY("ay8912", ay8910_data_w) AM_MIRROR(0x3ffd)
244	244	AM_RANGE(0xc000, 0xc000) AM_DEVREADWRITE_LEGACY("ay8912", ay8910_r, ay8910_address_w) AM_MIRROR(0x3ffd)

src/mess/drivers/a2600.c

r14963	r14964
73	73	DECLARE_DIRECT_UPDATE_MEMBER(modeSS_opbase);
74	74	DECLARE_DIRECT_UPDATE_MEMBER(modeDPC_opbase_handler);
75	75	DECLARE_DIRECT_UPDATE_MEMBER(modeFE_opbase_handler);
	76	DECLARE_READ8_MEMBER(modeF8_switch_r);
	77	DECLARE_READ8_MEMBER(modeFA_switch_r);
	78	DECLARE_READ8_MEMBER(modeF6_switch_r);
	79	DECLARE_READ8_MEMBER(modeF4_switch_r);
	80	DECLARE_READ8_MEMBER(modeE0_switch_r);
	81	DECLARE_READ8_MEMBER(modeE7_switch_r);
	82	DECLARE_READ8_MEMBER(modeE7_RAM_switch_r);
	83	DECLARE_READ8_MEMBER(modeUA_switch_r);
	84	DECLARE_READ8_MEMBER(modeDC_switch_r);
	85	DECLARE_READ8_MEMBER(modeFV_switch_r);
	86	DECLARE_READ8_MEMBER(modeJVP_switch_r);
	87	DECLARE_WRITE8_MEMBER(modeF8_switch_w);
	88	DECLARE_WRITE8_MEMBER(modeFA_switch_w);
	89	DECLARE_WRITE8_MEMBER(modeF6_switch_w);
	90	DECLARE_WRITE8_MEMBER(modeF4_switch_w);
	91	DECLARE_WRITE8_MEMBER(modeE0_switch_w);
	92	DECLARE_WRITE8_MEMBER(modeE7_switch_w);
	93	DECLARE_WRITE8_MEMBER(modeE7_RAM_switch_w);
	94	DECLARE_WRITE8_MEMBER(mode3F_switch_w);
	95	DECLARE_WRITE8_MEMBER(modeUA_switch_w);
	96	DECLARE_WRITE8_MEMBER(modeDC_switch_w);
	97	DECLARE_WRITE8_MEMBER(mode3E_switch_w);
	98	DECLARE_WRITE8_MEMBER(mode3E_RAM_switch_w);
	99	DECLARE_WRITE8_MEMBER(mode3E_RAM_w);
	100	DECLARE_WRITE8_MEMBER(modeFV_switch_w);
	101	DECLARE_WRITE8_MEMBER(modeJVP_switch_w);
	102	DECLARE_READ8_MEMBER(modeSS_r);
	103	DECLARE_READ8_MEMBER(modeDPC_r);
	104	DECLARE_WRITE8_MEMBER(modeDPC_w);
	105	DECLARE_READ8_MEMBER(modeFE_switch_r);
	106	DECLARE_WRITE8_MEMBER(modeFE_switch_w);
	107	DECLARE_READ8_MEMBER(current_bank_r);
	108	DECLARE_READ16_MEMBER(a2600_read_input_port);
	109	DECLARE_READ8_MEMBER(a2600_get_databus_contents);
	110	DECLARE_WRITE16_MEMBER(a2600_tia_vsync_callback);
	111	DECLARE_WRITE16_MEMBER(a2600_tia_vsync_callback_pal);
	112	void modeDPC_check_flag(UINT8 data_fetcher);
	113	void modeDPC_decrement_counter(UINT8 data_fetcher);
76	114	};
77	115
78	116
r14963	r14964
644	682
645	683
646	684	/* These read handlers will return the byte from the new bank */
647		static  READ8_HANDLER(modeF8_switch_r)
	685	READ8_MEMBER(a2600_state::modeF8_switch_r)
648	686	{
649		a2600_state *state = space->machine().driver_data<a2600_state>();
650		modeF8_switch(space->machine(), offset, 0);
651		return state->m_bank_base[1][0xff8 + offset];
	687	modeF8_switch(machine(), offset, 0);
	688	return m_bank_base[1][0xff8 + offset];
652	689	}
653	690
654		static  READ8_HANDLER(modeFA_switch_r)
	691	READ8_MEMBER(a2600_state::modeFA_switch_r)
655	692	{
656		a2600_state *state = space->machine().driver_data<a2600_state>();
657		modeFA_switch(space->machine(), offset, 0);
658		return state->m_bank_base[1][0xff8 + offset];
	693	modeFA_switch(machine(), offset, 0);
	694	return m_bank_base[1][0xff8 + offset];
659	695	}
660	696
661		static  READ8_HANDLER(modeF6_switch_r)
	697	READ8_MEMBER(a2600_state::modeF6_switch_r)
662	698	{
663		a2600_state *state = space->machine().driver_data<a2600_state>();
664		modeF6_switch(space->machine(), offset, 0);
665		return state->m_bank_base[1][0xff6 + offset];
	699	modeF6_switch(machine(), offset, 0);
	700	return m_bank_base[1][0xff6 + offset];
666	701	}
667	702
668		static  READ8_HANDLER(modeF4_switch_r)
	703	READ8_MEMBER(a2600_state::modeF4_switch_r)
669	704	{
670		a2600_state *state = space->machine().driver_data<a2600_state>();
671		modeF4_switch(space->machine(), offset, 0);
672		return state->m_bank_base[1][0xff4 + offset];
	705	modeF4_switch(machine(), offset, 0);
	706	return m_bank_base[1][0xff4 + offset];
673	707	}
674	708
675		static  READ8_HANDLER(modeE0_switch_r)
	709	READ8_MEMBER(a2600_state::modeE0_switch_r)
676	710	{
677		a2600_state *state = space->machine().driver_data<a2600_state>();
678		modeE0_switch(space->machine(), offset, 0);
679		return state->m_bank_base[4][0x3e0 + offset];
	711	modeE0_switch(machine(), offset, 0);
	712	return m_bank_base[4][0x3e0 + offset];
680	713	}
681	714
682		static  READ8_HANDLER(modeE7_switch_r)
	715	READ8_MEMBER(a2600_state::modeE7_switch_r)
683	716	{
684		a2600_state *state = space->machine().driver_data<a2600_state>();
685		modeE7_switch(space->machine(), offset, 0);
686		return state->m_bank_base[1][0xfe0 + offset];
	717	modeE7_switch(machine(), offset, 0);
	718	return m_bank_base[1][0xfe0 + offset];
687	719	}
688	720
689		static  READ8_HANDLER(modeE7_RAM_switch_r)
	721	READ8_MEMBER(a2600_state::modeE7_RAM_switch_r)
690	722	{
691		modeE7_RAM_switch(space->machine(), offset, 0);
	723	modeE7_RAM_switch(machine(), offset, 0);
692	724	return 0;
693	725	}
694	726
695		static  READ8_HANDLER(modeUA_switch_r)
	727	READ8_MEMBER(a2600_state::modeUA_switch_r)
696	728	{
697		modeUA_switch(space->machine(), offset, 0);
	729	modeUA_switch(machine(), offset, 0);
698	730	return 0;
699	731	}
700	732
701		static  READ8_HANDLER(modeDC_switch_r)
	733	READ8_MEMBER(a2600_state::modeDC_switch_r)
702	734	{
703		a2600_state *state = space->machine().driver_data<a2600_state>();
704		modeDC_switch(space->machine(), offset, 0);
705		return state->m_bank_base[1][0xff0 + offset];
	735	modeDC_switch(machine(), offset, 0);
	736	return m_bank_base[1][0xff0 + offset];
706	737	}
707	738
708		static  READ8_HANDLER(modeFV_switch_r)
	739	READ8_MEMBER(a2600_state::modeFV_switch_r)
709	740	{
710		a2600_state *state = space->machine().driver_data<a2600_state>();
711		modeFV_switch(space->machine(), offset, 0);
712		return state->m_bank_base[1][0xfd0 + offset];
	741	modeFV_switch(machine(), offset, 0);
	742	return m_bank_base[1][0xfd0 + offset];
713	743	}
714	744
715		static  READ8_HANDLER(modeJVP_switch_r)
	745	READ8_MEMBER(a2600_state::modeJVP_switch_r)
716	746	{
717		a2600_state *state = space->machine().driver_data<a2600_state>();
718		modeJVP_switch(space->machine(), offset, 0);
719		return state->m_riot_ram[ 0x20 + offset ];
	747	modeJVP_switch(machine(), offset, 0);
	748	return m_riot_ram[ 0x20 + offset ];
720	749	}
721	750
722	751
723		static WRITE8_HANDLER(modeF8_switch_w) { modeF8_switch(space->machine(), offset, data); }
724		static WRITE8_HANDLER(modeFA_switch_w) { modeFA_switch(space->machine(), offset, data); }
725		static WRITE8_HANDLER(modeF6_switch_w) { modeF6_switch(space->machine(), offset, data); }
726		static WRITE8_HANDLER(modeF4_switch_w) { modeF4_switch(space->machine(), offset, data); }
727		static WRITE8_HANDLER(modeE0_switch_w) { modeE0_switch(space->machine(), offset, data); }
728		static WRITE8_HANDLER(modeE7_switch_w) { modeE7_switch(space->machine(), offset, data); }
729		static WRITE8_HANDLER(modeE7_RAM_switch_w) { modeE7_RAM_switch(space->machine(), offset, data); }
730		static WRITE8_HANDLER(mode3F_switch_w) { mode3F_switch(space->machine(), offset, data); }
731		static WRITE8_HANDLER(modeUA_switch_w) { modeUA_switch(space->machine(), offset, data); }
732		static WRITE8_HANDLER(modeDC_switch_w) { modeDC_switch(space->machine(), offset, data); }
733		static WRITE8_HANDLER(mode3E_switch_w) { mode3E_switch(space->machine(), offset, data); }
734		static WRITE8_HANDLER(mode3E_RAM_switch_w) { mode3E_RAM_switch(space->machine(), offset, data); }
735		static WRITE8_HANDLER(mode3E_RAM_w)
	752	WRITE8_MEMBER(a2600_state::modeF8_switch_w){ modeF8_switch(machine(), offset, data); }
	753	WRITE8_MEMBER(a2600_state::modeFA_switch_w){ modeFA_switch(machine(), offset, data); }
	754	WRITE8_MEMBER(a2600_state::modeF6_switch_w){ modeF6_switch(machine(), offset, data); }
	755	WRITE8_MEMBER(a2600_state::modeF4_switch_w){ modeF4_switch(machine(), offset, data); }
	756	WRITE8_MEMBER(a2600_state::modeE0_switch_w){ modeE0_switch(machine(), offset, data); }
	757	WRITE8_MEMBER(a2600_state::modeE7_switch_w){ modeE7_switch(machine(), offset, data); }
	758	WRITE8_MEMBER(a2600_state::modeE7_RAM_switch_w){ modeE7_RAM_switch(machine(), offset, data); }
	759	WRITE8_MEMBER(a2600_state::mode3F_switch_w){ mode3F_switch(machine(), offset, data); }
	760	WRITE8_MEMBER(a2600_state::modeUA_switch_w){ modeUA_switch(machine(), offset, data); }
	761	WRITE8_MEMBER(a2600_state::modeDC_switch_w){ modeDC_switch(machine(), offset, data); }
	762	WRITE8_MEMBER(a2600_state::mode3E_switch_w){ mode3E_switch(machine(), offset, data); }
	763	WRITE8_MEMBER(a2600_state::mode3E_RAM_switch_w){ mode3E_RAM_switch(machine(), offset, data); }
	764	WRITE8_MEMBER(a2600_state::mode3E_RAM_w)
736	765	{
737		a2600_state *state = space->machine().driver_data<a2600_state>();
738		if ( state->m_mode3E_ram_enabled )
	766	if ( m_mode3E_ram_enabled )
739	767	{
740		state->m_ram_base[offset] = data;
	768	m_ram_base[offset] = data;
741	769	}
742	770	}
743		static WRITE8_HANDLER(modeFV_switch_w) { modeFV_switch(space->machine(), offset, data); }
744		static WRITE8_HANDLER(modeJVP_switch_w)
	771	WRITE8_MEMBER(a2600_state::modeFV_switch_w){ modeFV_switch(machine(), offset, data); }
	772	WRITE8_MEMBER(a2600_state::modeJVP_switch_w)
745	773	{
746		a2600_state *state = space->machine().driver_data<a2600_state>();
747		modeJVP_switch(space->machine(), offset, data); state->m_riot_ram[ 0x20 + offset ] = data;
	774	modeJVP_switch(machine(), offset, data); m_riot_ram[ 0x20 + offset ] = data;
748	775	}
749	776
750	777
r14963	r14964
752	779	{
753	780	if ( ( address & 0x1FFF ) >= 0x1FF6 && ( address & 0x1FFF ) <= 0x1FF9 )
754	781	{
755		modeF6_switch_w( machine().device("maincpu")->memory().space(AS_PROGRAM), ( address & 0x1FFF ) - 0x1FF6, 0 );
	782	modeF6_switch_w(*machine().device("maincpu")->memory().space(AS_PROGRAM), ( address & 0x1FFF ) - 0x1FF6, 0 );
756	783	}
757	784	return address;
758	785	}
r14963	r14964
774	801	return address;
775	802	}
776	803
777		static READ8_HANDLER(modeSS_r)
	804	READ8_MEMBER(a2600_state::modeSS_r)
778	805	{
779		a2600_state *state = space->machine().driver_data<a2600_state>();
780		UINT8 data = ( offset & 0x800 ) ? state->m_bank_base[2][offset & 0x7FF] : state->m_bank_base[1][offset];
	806	UINT8 data = ( offset & 0x800 ) ? m_bank_base[2][offset & 0x7FF] : m_bank_base[1][offset];
781	807
782		//logerror("%04X: read from modeSS area offset = %04X\n", cpu_get_pc(space->machine().device("maincpu")), offset);
	808	//logerror("%04X: read from modeSS area offset = %04X\n", cpu_get_pc(machine().device("maincpu")), offset);
783	809	/* Check for control register "write" */
784	810	if ( offset == 0xFF8 )
785	811	{
786		//logerror("%04X: write to modeSS control register data = %02X\n", cpu_get_pc(space->machine().device("maincpu")), state->m_modeSS_byte);
787		state->m_modeSS_write_enabled = state->m_modeSS_byte & 0x02;
788		state->m_modeSS_write_delay = state->m_modeSS_byte >> 5;
789		switch ( state->m_modeSS_byte & 0x1C )
	812	//logerror("%04X: write to modeSS control register data = %02X\n", cpu_get_pc(machine().device("maincpu")), m_modeSS_byte);
	813	m_modeSS_write_enabled = m_modeSS_byte & 0x02;
	814	m_modeSS_write_delay = m_modeSS_byte >> 5;
	815	switch ( m_modeSS_byte & 0x1C )
790	816	{
791	817	case 0x00:
792		state->m_bank_base[1] = state->m_extra_RAM->base() + 2 * 0x800;
793		state->m_bank_base[2] = ( state->m_modeSS_byte & 0x01 ) ? space->machine().region("maincpu")->base() + 0x1800 : space->machine().region("user1")->base();
794		state->m_modeSS_high_ram_enabled = 0;
	818	m_bank_base[1] = m_extra_RAM->base() + 2 * 0x800;
	819	m_bank_base[2] = ( m_modeSS_byte & 0x01 ) ? machine().region("maincpu")->base() + 0x1800 : machine().region("user1")->base();
	820	m_modeSS_high_ram_enabled = 0;
795	821	break;
796	822	case 0x04:
797		state->m_bank_base[1] = state->m_extra_RAM->base();
798		state->m_bank_base[2] = ( state->m_modeSS_byte & 0x01 ) ? space->machine().region("maincpu")->base() + 0x1800 : space->machine().region("user1")->base();
799		state->m_modeSS_high_ram_enabled = 0;
	823	m_bank_base[1] = m_extra_RAM->base();
	824	m_bank_base[2] = ( m_modeSS_byte & 0x01 ) ? machine().region("maincpu")->base() + 0x1800 : machine().region("user1")->base();
	825	m_modeSS_high_ram_enabled = 0;
800	826	break;
801	827	case 0x08:
802		state->m_bank_base[1] = state->m_extra_RAM->base() + 2 * 0x800;
803		state->m_bank_base[2] = state->m_extra_RAM->base();
804		state->m_modeSS_high_ram_enabled = 1;
	828	m_bank_base[1] = m_extra_RAM->base() + 2 * 0x800;
	829	m_bank_base[2] = m_extra_RAM->base();
	830	m_modeSS_high_ram_enabled = 1;
805	831	break;
806	832	case 0x0C:
807		state->m_bank_base[1] = state->m_extra_RAM->base();
808		state->m_bank_base[2] = state->m_extra_RAM->base() + 2 * 0x800;
809		state->m_modeSS_high_ram_enabled = 1;
	833	m_bank_base[1] = m_extra_RAM->base();
	834	m_bank_base[2] = m_extra_RAM->base() + 2 * 0x800;
	835	m_modeSS_high_ram_enabled = 1;
810	836	break;
811	837	case 0x10:
812		state->m_bank_base[1] = state->m_extra_RAM->base() + 2 * 0x800;
813		state->m_bank_base[2] = ( state->m_modeSS_byte & 0x01 ) ? space->machine().region("maincpu")->base() + 0x1800 : space->machine().region("user1")->base();
814		state->m_modeSS_high_ram_enabled = 0;
	838	m_bank_base[1] = m_extra_RAM->base() + 2 * 0x800;
	839	m_bank_base[2] = ( m_modeSS_byte & 0x01 ) ? machine().region("maincpu")->base() + 0x1800 : machine().region("user1")->base();
	840	m_modeSS_high_ram_enabled = 0;
815	841	break;
816	842	case 0x14:
817		state->m_bank_base[1] = state->m_extra_RAM->base() + 0x800;
818		state->m_bank_base[2] = ( state->m_modeSS_byte & 0x01 ) ? space->machine().region("maincpu")->base() + 0x1800 : space->machine().region("user1")->base();
819		state->m_modeSS_high_ram_enabled = 0;
	843	m_bank_base[1] = m_extra_RAM->base() + 0x800;
	844	m_bank_base[2] = ( m_modeSS_byte & 0x01 ) ? machine().region("maincpu")->base() + 0x1800 : machine().region("user1")->base();
	845	m_modeSS_high_ram_enabled = 0;
820	846	break;
821	847	case 0x18:
822		state->m_bank_base[1] = state->m_extra_RAM->base() + 2 * 0x800;
823		state->m_bank_base[2] = state->m_extra_RAM->base() + 0x800;
824		state->m_modeSS_high_ram_enabled = 1;
	848	m_bank_base[1] = m_extra_RAM->base() + 2 * 0x800;
	849	m_bank_base[2] = m_extra_RAM->base() + 0x800;
	850	m_modeSS_high_ram_enabled = 1;
825	851	break;
826	852	case 0x1C:
827		state->m_bank_base[1] = state->m_extra_RAM->base() + 0x800;
828		state->m_bank_base[2] = state->m_extra_RAM->base() + 2 * 0x800;
829		state->m_modeSS_high_ram_enabled = 1;
	853	m_bank_base[1] = m_extra_RAM->base() + 0x800;
	854	m_bank_base[2] = m_extra_RAM->base() + 2 * 0x800;
	855	m_modeSS_high_ram_enabled = 1;
830	856	break;
831	857	}
832		memory_set_bankptr(space->machine(), "bank1", state->m_bank_base[1] );
833		memory_set_bankptr(space->machine(), "bank2", state->m_bank_base[2] );
	858	memory_set_bankptr(machine(), "bank1", m_bank_base[1] );
	859	memory_set_bankptr(machine(), "bank2", m_bank_base[2] );
834	860	}
835	861	else if ( offset == 0xFF9 )
836	862	{
837	863	/* Cassette port read */
838		double tap_val = space->machine().device<cassette_image_device>(CASSETTE_TAG)->input();
839		//logerror("%04X: Cassette port read, tap_val = %f\n", cpu_get_pc(space->machine().device("maincpu")), tap_val);
	864	double tap_val = machine().device<cassette_image_device>(CASSETTE_TAG)->input();
	865	//logerror("%04X: Cassette port read, tap_val = %f\n", cpu_get_pc(machine().device("maincpu")), tap_val);
840	866	if ( tap_val < 0 )
841	867	{
842	868	data = 0x00;
r14963	r14964
849	875	else
850	876	{
851	877	/* Possible RAM write */
852		if ( state->m_modeSS_write_enabled )
	878	if ( m_modeSS_write_enabled )
853	879	{
854		int diff = space->machine().device<cpu_device>("maincpu")->total_cycles() - state->m_modeSS_byte_started;
855		//logerror("%04X: offset = %04X, %d\n", cpu_get_pc(space->machine().device("maincpu")), offset, diff);
856		if ( diff - state->m_modeSS_diff_adjust == 5 )
	880	int diff = machine().device<cpu_device>("maincpu")->total_cycles() - m_modeSS_byte_started;
	881	//logerror("%04X: offset = %04X, %d\n", cpu_get_pc(machine().device("maincpu")), offset, diff);
	882	if ( diff - m_modeSS_diff_adjust == 5 )
857	883	{
858		//logerror("%04X: RAM write offset = %04X, data = %02X\n", cpu_get_pc(space->machine().device("maincpu")), offset, state->m_modeSS_byte );
	884	//logerror("%04X: RAM write offset = %04X, data = %02X\n", cpu_get_pc(machine().device("maincpu")), offset, m_modeSS_byte );
859	885	if ( offset & 0x800 )
860	886	{
861		if ( state->m_modeSS_high_ram_enabled )
	887	if ( m_modeSS_high_ram_enabled )
862	888	{
863		state->m_bank_base[2][offset & 0x7FF] = state->m_modeSS_byte;
864		data = state->m_modeSS_byte;
	889	m_bank_base[2][offset & 0x7FF] = m_modeSS_byte;
	890	data = m_modeSS_byte;
865	891	}
866	892	}
867	893	else
868	894	{
869		state->m_bank_base[1][offset] = state->m_modeSS_byte;
870		data = state->m_modeSS_byte;
	895	m_bank_base[1][offset] = m_modeSS_byte;
	896	data = m_modeSS_byte;
871	897	}
872	898	}
873	899	else if ( offset < 0x0100 )
874	900	{
875		state->m_modeSS_byte = offset;
876		state->m_modeSS_byte_started = space->machine().device<cpu_device>("maincpu")->total_cycles();
	901	m_modeSS_byte = offset;
	902	m_modeSS_byte_started = machine().device<cpu_device>("maincpu")->total_cycles();
877	903	}
878	904	/* Check for dummy read from same address */
879	905	if ( diff == 2 )
880	906	{
881		state->m_modeSS_diff_adjust = 1;
	907	m_modeSS_diff_adjust = 1;
882	908	}
883	909	else
884	910	{
885		state->m_modeSS_diff_adjust = 0;
	911	m_modeSS_diff_adjust = 0;
886	912	}
887	913	}
888	914	else if ( offset < 0x0100 )
889	915	{
890		state->m_modeSS_byte = offset;
891		state->m_modeSS_byte_started = space->machine().device<cpu_device>("maincpu")->total_cycles();
	916	m_modeSS_byte = offset;
	917	m_modeSS_byte_started = machine().device<cpu_device>("maincpu")->total_cycles();
892	918	}
893	919	}
894	920	/* Because the mame core caches opcode data and doesn't perform reads like normal */
895	921	/* we have to put in this little hack here to get Suicide Mission to work. */
896		if ( offset != 0xFF8 && ( cpu_get_pc(space->machine().device("maincpu")) & 0x1FFF ) == 0x1FF8 )
	922	if ( offset != 0xFF8 && ( cpu_get_pc(machine().device("maincpu")) & 0x1FFF ) == 0x1FF8 )
897	923	{
898	924	modeSS_r( space, 0xFF8 );
899	925	}
900	926	return data;
901	927	}
902	928
903		INLINE void modeDPC_check_flag(a2600_state *state, UINT8 data_fetcher)
	929	void a2600_state::modeDPC_check_flag(UINT8 data_fetcher)
904	930	{
905	931	/* Set flag when low counter equals top */
906		if ( state->m_dpc.df[data_fetcher].low == state->m_dpc.df[data_fetcher].top )
	932	if ( m_dpc.df[data_fetcher].low == m_dpc.df[data_fetcher].top )
907	933	{
908		state->m_dpc.df[data_fetcher].flag = 1;
	934	m_dpc.df[data_fetcher].flag = 1;
909	935	}
910	936	/* Reset flag when low counter equals bottom */
911		if ( state->m_dpc.df[data_fetcher].low == state->m_dpc.df[data_fetcher].bottom )
	937	if ( m_dpc.df[data_fetcher].low == m_dpc.df[data_fetcher].bottom )
912	938	{
913		state->m_dpc.df[data_fetcher].flag = 0;
	939	m_dpc.df[data_fetcher].flag = 0;
914	940	}
915	941	}
916	942
917		INLINE void modeDPC_decrement_counter(a2600_state *state, UINT8 data_fetcher)
	943	void a2600_state::modeDPC_decrement_counter(UINT8 data_fetcher)
918	944	{
919		state->m_dpc.df[data_fetcher].low -= 1;
920		if ( state->m_dpc.df[data_fetcher].low == 0xFF )
	945	m_dpc.df[data_fetcher].low -= 1;
	946	if ( m_dpc.df[data_fetcher].low == 0xFF )
921	947	{
922		state->m_dpc.df[data_fetcher].high -= 1;
923		if ( data_fetcher > 4 && state->m_dpc.df[data_fetcher].music_mode )
	948	m_dpc.df[data_fetcher].high -= 1;
	949	if ( data_fetcher > 4 && m_dpc.df[data_fetcher].music_mode )
924	950	{
925		state->m_dpc.df[data_fetcher].low = state->m_dpc.df[data_fetcher].top;
	951	m_dpc.df[data_fetcher].low = m_dpc.df[data_fetcher].top;
926	952	}
927	953	}
928	954
929		modeDPC_check_flag( state, data_fetcher );
	955	modeDPC_check_flag(data_fetcher );
930	956	}
931	957
932	958	static TIMER_CALLBACK(modeDPC_timer_callback)
r14963	r14964
937	963	{
938	964	if ( state->m_dpc.df[data_fetcher].osc_clk )
939	965	{
940		modeDPC_decrement_counter( state, data_fetcher );
	966	state->modeDPC_decrement_counter(data_fetcher );
941	967	}
942	968	}
943	969	}
r14963	r14964
952	978	return address;
953	979	}
954	980
955		static READ8_HANDLER(modeDPC_r)
	981	READ8_MEMBER(a2600_state::modeDPC_r)
956	982	{
957		a2600_state *state = space->machine().driver_data<a2600_state>();
958	983	static const UINT8 dpc_amplitude[8] = { 0x00, 0x04, 0x05, 0x09, 0x06, 0x0A, 0x0B, 0x0F };
959	984	UINT8   data_fetcher = offset & 0x07;
960	985	UINT8   data = 0xFF;
961	986
962		logerror("%04X: Read from DPC offset $%02X\n", cpu_get_pc(space->machine().device("maincpu")), offset);
	987	logerror("%04X: Read from DPC offset $%02X\n", cpu_get_pc(machine().device("maincpu")), offset);
963	988	if ( offset < 0x08 )
964	989	{
965	990	switch( offset & 0x06 )
966	991	{
967	992	case 0x00:      /* Random number generator */
968	993	case 0x02:
969		return state->m_dpc.shift_reg;
	994	return m_dpc.shift_reg;
970	995	case 0x04:      /* Sound value, MOVAMT value AND'd with Draw Line Carry; with Draw Line Add */
971		state->m_dpc.latch_62 = state->m_dpc.latch_64;
	996	m_dpc.latch_62 = m_dpc.latch_64;
972	997	case 0x06:      /* Sound value, MOVAMT value AND'd with Draw Line Carry; without Draw Line Add */
973		state->m_dpc.latch_64 = state->m_dpc.latch_62 + state->m_dpc.df[4].top;
974		state->m_dpc.dlc = ( state->m_dpc.latch_62 + state->m_dpc.df[4].top > 0xFF ) ? 1 : 0;
	998	m_dpc.latch_64 = m_dpc.latch_62 + m_dpc.df[4].top;
	999	m_dpc.dlc = ( m_dpc.latch_62 + m_dpc.df[4].top > 0xFF ) ? 1 : 0;
975	1000	data = 0;
976		if ( state->m_dpc.df[5].music_mode && state->m_dpc.df[5].flag )
	1001	if ( m_dpc.df[5].music_mode && m_dpc.df[5].flag )
977	1002	{
978	1003	data |= 0x01;
979	1004	}
980		if ( state->m_dpc.df[6].music_mode && state->m_dpc.df[6].flag )
	1005	if ( m_dpc.df[6].music_mode && m_dpc.df[6].flag )
981	1006	{
982	1007	data |= 0x02;
983	1008	}
984		if ( state->m_dpc.df[7].music_mode && state->m_dpc.df[7].flag )
	1009	if ( m_dpc.df[7].music_mode && m_dpc.df[7].flag )
985	1010	{
986	1011	data |= 0x04;
987	1012	}
988		return ( state->m_dpc.dlc ? state->m_dpc.movamt & 0xF0 : 0 ) | dpc_amplitude[data];
	1013	return ( m_dpc.dlc ? m_dpc.movamt & 0xF0 : 0 ) | dpc_amplitude[data];
989	1014	}
990	1015	}
991	1016	else
992	1017	{
993		UINT8   display_data = space->machine().region("user1")->base()[0x2000 + ( ~ ( ( state->m_dpc.df[data_fetcher].low | ( state->m_dpc.df[data_fetcher].high << 8 ) ) ) & 0x7FF ) ];
	1018	UINT8   display_data = machine().region("user1")->base()[0x2000 + ( ~ ( ( m_dpc.df[data_fetcher].low | ( m_dpc.df[data_fetcher].high << 8 ) ) ) & 0x7FF ) ];
994	1019
995	1020	switch( offset & 0x38 )
996	1021	{
r14963	r14964
998	1023	data = display_data;
999	1024	break;
1000	1025	case 0x10:         /* display data AND'd w/flag */
1001		data = state->m_dpc.df[data_fetcher].flag ? display_data : 0x00;
	1026	data = m_dpc.df[data_fetcher].flag ? display_data : 0x00;
1002	1027	break;
1003	1028	case 0x18:         /* display data AND'd w/flag, nibbles swapped */
1004		data = state->m_dpc.df[data_fetcher].flag ? BITSWAP8(display_data,3,2,1,0,7,6,5,4) : 0x00;
	1029	data = m_dpc.df[data_fetcher].flag ? BITSWAP8(display_data,3,2,1,0,7,6,5,4) : 0x00;
1005	1030	break;
1006	1031	case 0x20:         /* display data AND'd w/flag, byte reversed */
1007		data = state->m_dpc.df[data_fetcher].flag ? BITSWAP8(display_data,0,1,2,3,4,5,6,7) : 0x00;
	1032	data = m_dpc.df[data_fetcher].flag ? BITSWAP8(display_data,0,1,2,3,4,5,6,7) : 0x00;
1008	1033	break;
1009	1034	case 0x28:         /* display data AND'd w/flag, rotated right */
1010		data = state->m_dpc.df[data_fetcher].flag ? ( display_data >> 1 ) : 0x00;
	1035	data = m_dpc.df[data_fetcher].flag ? ( display_data >> 1 ) : 0x00;
1011	1036	break;
1012	1037	case 0x30:         /* display data AND'd w/flag, rotated left */
1013		data = state->m_dpc.df[data_fetcher].flag ? ( display_data << 1 ) : 0x00;
	1038	data = m_dpc.df[data_fetcher].flag ? ( display_data << 1 ) : 0x00;
1014	1039	break;
1015	1040	case 0x38:         /* flag */
1016		data = state->m_dpc.df[data_fetcher].flag ? 0xFF : 0x00;
	1041	data = m_dpc.df[data_fetcher].flag ? 0xFF : 0x00;
1017	1042	break;
1018	1043	}
1019	1044
1020		if ( data_fetcher < 5 || ! state->m_dpc.df[data_fetcher].osc_clk )
	1045	if ( data_fetcher < 5 || ! m_dpc.df[data_fetcher].osc_clk )
1021	1046	{
1022		modeDPC_decrement_counter( state, data_fetcher );
	1047	modeDPC_decrement_counter(data_fetcher );
1023	1048	}
1024	1049	}
1025	1050	return data;
1026	1051	}
1027	1052
1028		static WRITE8_HANDLER(modeDPC_w)
	1053	WRITE8_MEMBER(a2600_state::modeDPC_w)
1029	1054	{
1030		a2600_state *state = space->machine().driver_data<a2600_state>();
1031	1055	UINT8   data_fetcher = offset & 0x07;
1032	1056
1033	1057	switch( offset & 0x38 )
1034	1058	{
1035	1059	case 0x00:         /* Top count */
1036		state->m_dpc.df[data_fetcher].top = data;
1037		state->m_dpc.df[data_fetcher].flag = 0;
1038		modeDPC_check_flag( state, data_fetcher );
	1060	m_dpc.df[data_fetcher].top = data;
	1061	m_dpc.df[data_fetcher].flag = 0;
	1062	modeDPC_check_flag(data_fetcher );
1039	1063	break;
1040	1064	case 0x08:         /* Bottom count */
1041		state->m_dpc.df[data_fetcher].bottom = data;
1042		modeDPC_check_flag( state, data_fetcher );
	1065	m_dpc.df[data_fetcher].bottom = data;
	1066	modeDPC_check_flag(data_fetcher );
1043	1067	break;
1044	1068	case 0x10:         /* Counter low */
1045		state->m_dpc.df[data_fetcher].low = data;
	1069	m_dpc.df[data_fetcher].low = data;
1046	1070	if ( data_fetcher == 4 )
1047	1071	{
1048		state->m_dpc.latch_64 = data;
	1072	m_dpc.latch_64 = data;
1049	1073	}
1050		if ( data_fetcher > 4 && state->m_dpc.df[data_fetcher].music_mode )
	1074	if ( data_fetcher > 4 && m_dpc.df[data_fetcher].music_mode )
1051	1075	{
1052		state->m_dpc.df[data_fetcher].low = state->m_dpc.df[data_fetcher].top;
	1076	m_dpc.df[data_fetcher].low = m_dpc.df[data_fetcher].top;
1053	1077	}
1054		modeDPC_check_flag( state, data_fetcher );
	1078	modeDPC_check_flag(data_fetcher );
1055	1079	break;
1056	1080	case 0x18:         /* Counter high */
1057		state->m_dpc.df[data_fetcher].high = data;
1058		state->m_dpc.df[data_fetcher].music_mode = data & 0x10;
1059		state->m_dpc.df[data_fetcher].osc_clk = data & 0x20;
1060		if ( data_fetcher > 4 && state->m_dpc.df[data_fetcher].music_mode && state->m_dpc.df[data_fetcher].low == 0xFF )
	1081	m_dpc.df[data_fetcher].high = data;
	1082	m_dpc.df[data_fetcher].music_mode = data & 0x10;
	1083	m_dpc.df[data_fetcher].osc_clk = data & 0x20;
	1084	if ( data_fetcher > 4 && m_dpc.df[data_fetcher].music_mode && m_dpc.df[data_fetcher].low == 0xFF )
1061	1085	{
1062		state->m_dpc.df[data_fetcher].low = state->m_dpc.df[data_fetcher].top;
1063		modeDPC_check_flag( state, data_fetcher );
	1086	m_dpc.df[data_fetcher].low = m_dpc.df[data_fetcher].top;
	1087	modeDPC_check_flag(data_fetcher );
1064	1088	}
1065	1089	break;
1066	1090	case 0x20:         /* Draw line movement value / MOVAMT */
1067		state->m_dpc.movamt = data;
	1091	m_dpc.movamt = data;
1068	1092	break;
1069	1093	case 0x28:         /* Not used */
1070		logerror("%04X: Write to unused DPC register $%02X, data $%02X\n", cpu_get_pc(space->machine().device("maincpu")), offset, data);
	1094	logerror("%04X: Write to unused DPC register $%02X, data $%02X\n", cpu_get_pc(machine().device("maincpu")), offset, data);
1071	1095	break;
1072	1096	case 0x30:         /* Random number generator reset */
1073		state->m_dpc.shift_reg = 0;
	1097	m_dpc.shift_reg = 0;
1074	1098	break;
1075	1099	case 0x38:         /* Not used */
1076		logerror("%04X: Write to unused DPC register $%02X, data $%02X\n", cpu_get_pc(space->machine().device("maincpu")), offset, data);
	1100	logerror("%04X: Write to unused DPC register $%02X, data $%02X\n", cpu_get_pc(machine().device("maincpu")), offset, data);
1077	1101	break;
1078	1102	}
1079	1103	}
r14963	r14964
1122	1146	state->m_FE_old_opbase_handler = space->set_direct_update_handler(direct_update_delegate(FUNC(a2600_state::modeFE_opbase_handler), state));
1123	1147	}
1124	1148
1125		static READ8_HANDLER(modeFE_switch_r)
	1149	READ8_MEMBER(a2600_state::modeFE_switch_r)
1126	1150	{
1127		modeFE_switch(space->machine(),offset, 0 );
1128		return space->read_byte(0xFE );
	1151	modeFE_switch(machine(),offset, 0 );
	1152	return space.read_byte(0xFE );
1129	1153	}
1130	1154
1131		static WRITE8_HANDLER(modeFE_switch_w)
	1155	WRITE8_MEMBER(a2600_state::modeFE_switch_w)
1132	1156	{
1133		space->write_byte(0xFE, data );
1134		modeFE_switch(space->machine(),offset, 0 );
	1157	space.write_byte(0xFE, data );
	1158	modeFE_switch(machine(),offset, 0 );
1135	1159	}
1136	1160
1137		static  READ8_HANDLER(current_bank_r)
	1161	READ8_MEMBER(a2600_state::current_bank_r)
1138	1162	{
1139		a2600_state *state = space->machine().driver_data<a2600_state>();
1140		return state->m_current_bank;
	1163	return m_current_bank;
1141	1164	}
1142	1165
1143	1166	static ADDRESS_MAP_START(a2600_mem, AS_PROGRAM, 8, a2600_state )
1144	1167	ADDRESS_MAP_GLOBAL_MASK(0x1fff)
1145		AM_RANGE(0x0000, 0x007F) AM_MIRROR(0x0F00) AM_READWRITE_LEGACY(tia_r, tia_w)
	1168	AM_RANGE(0x0000, 0x007F) AM_MIRROR(0x0F00) AM_DEVREADWRITE("tia_video", tia_video_device, read, write)
1146	1169	AM_RANGE(0x0080, 0x00FF) AM_MIRROR(0x0D00) AM_RAM AM_SHARE("riot_ram")
1147	1170	AM_RANGE(0x0280, 0x029F) AM_MIRROR(0x0D00) AM_DEVREADWRITE_LEGACY("riot", riot6532_r, riot6532_w)
1148	1171	AM_RANGE(0x1000, 0x1FFF)                   AM_ROMBANK("bank1")
r14963	r14964
1272	1295	}
1273	1296	}
1274	1297
1275		static READ16_HANDLER(a2600_read_input_port)
	1298	READ16_MEMBER(a2600_state::a2600_read_input_port)
1276	1299	{
1277		a2600_state *state = space->machine().driver_data<a2600_state>();
1278	1300	int i;
1279	1301
1280	1302	switch( offset )
1281	1303	{
1282	1304	case 0:   /* Left controller port PIN 5 */
1283		switch ( input_port_read(space->machine(), "CONTROLLERS") / CATEGORY_SELECT )
	1305	switch ( input_port_read(machine(), "CONTROLLERS") / CATEGORY_SELECT )
1284	1306	{
1285	1307	case 0x00:   /* Joystick */
1286	1308	return TIA_INPUT_PORT_ALWAYS_OFF;
1287	1309	case 0x01:   /* Paddle */
1288		return input_port_read(space->machine(), "PADDLE1");
	1310	return input_port_read(machine(), "PADDLE1");
1289	1311	case 0x03:   /* Keypad */
1290	1312	for ( i = 0; i < 4; i++ )
1291	1313	{
1292		if ( ! ( ( state->m_keypad_left_column >> i ) & 0x01 ) )
	1314	if ( ! ( ( m_keypad_left_column >> i ) & 0x01 ) )
1293	1315	{
1294		if ( ( input_port_read(space->machine(), "KEYPAD_L") >> 3*i ) & 0x01 )
	1316	if ( ( input_port_read(machine(), "KEYPAD_L") >> 3*i ) & 0x01 )
1295	1317	{
1296	1318	return TIA_INPUT_PORT_ALWAYS_ON;
1297	1319	}
r14963	r14964
1303	1325	}
1304	1326	return TIA_INPUT_PORT_ALWAYS_ON;
1305	1327	case 0x05:   /* Boostergrip joystick */
1306		return ( input_port_read(space->machine(), "BUTTONS_L") & 0x40 ) ? TIA_INPUT_PORT_ALWAYS_OFF : TIA_INPUT_PORT_ALWAYS_ON;
	1328	return ( input_port_read(machine(), "BUTTONS_L") & 0x40 ) ? TIA_INPUT_PORT_ALWAYS_OFF : TIA_INPUT_PORT_ALWAYS_ON;
1307	1329	default:
1308	1330	return TIA_INPUT_PORT_ALWAYS_OFF;
1309	1331	}
1310	1332	break;
1311	1333	case 1:   /* Right controller port PIN 5 */
1312		switch ( input_port_read(space->machine(), "CONTROLLERS") / CATEGORY_SELECT )
	1334	switch ( input_port_read(machine(), "CONTROLLERS") / CATEGORY_SELECT )
1313	1335	{
1314	1336	case 0x00:   /* Joystick */
1315	1337	return TIA_INPUT_PORT_ALWAYS_OFF;
1316	1338	case 0x01:   /* Paddle */
1317		return input_port_read(space->machine(), "PADDLE3");
	1339	return input_port_read(machine(), "PADDLE3");
1318	1340	case 0x03:   /* Keypad */
1319	1341	for ( i = 0; i < 4; i++ )
1320	1342	{
1321		if ( ! ( ( state->m_keypad_left_column >> i ) & 0x01 ) )
	1343	if ( ! ( ( m_keypad_left_column >> i ) & 0x01 ) )
1322	1344	{
1323		if ( ( input_port_read(space->machine(), "KEYPAD_L") >> 3*i ) & 0x02 )
	1345	if ( ( input_port_read(machine(), "KEYPAD_L") >> 3*i ) & 0x02 )
1324	1346	{
1325	1347	return TIA_INPUT_PORT_ALWAYS_ON;
1326	1348	}
r14963	r14964
1332	1354	}
1333	1355	return TIA_INPUT_PORT_ALWAYS_ON;
1334	1356	case 0x05:   /* Joystick w/Boostergrip */
1335		return ( input_port_read(space->machine(), "BUTTONS_L") & 0x20 ) ? TIA_INPUT_PORT_ALWAYS_OFF : TIA_INPUT_PORT_ALWAYS_ON;
	1357	return ( input_port_read(machine(), "BUTTONS_L") & 0x20 ) ? TIA_INPUT_PORT_ALWAYS_OFF : TIA_INPUT_PORT_ALWAYS_ON;
1336	1358	default:
1337	1359	return TIA_INPUT_PORT_ALWAYS_OFF;
1338	1360	}
1339	1361	break;
1340	1362	case 2:   /* Left controller port PIN 9 */
1341		switch ( input_port_read(space->machine(), "CONTROLLERS") % CATEGORY_SELECT )
	1363	switch ( input_port_read(machine(), "CONTROLLERS") % CATEGORY_SELECT )
1342	1364	{
1343	1365	case 0x00:   /* Joystick */
1344	1366	return TIA_INPUT_PORT_ALWAYS_OFF;
1345	1367	case 0x01:   /* Paddle */
1346		return input_port_read(space->machine(), "PADDLE2");
	1368	return input_port_read(machine(), "PADDLE2");
1347	1369	case 0x03:   /* Keypad */
1348	1370	for ( i = 0; i < 4; i++ )
1349	1371	{
1350		if ( ! ( ( state->m_keypad_right_column >> i ) & 0x01 ) )
	1372	if ( ! ( ( m_keypad_right_column >> i ) & 0x01 ) )
1351	1373	{
1352		if ( ( input_port_read(space->machine(), "KEYPAD_R") >> 3*i ) & 0x01 )
	1374	if ( ( input_port_read(machine(), "KEYPAD_R") >> 3*i ) & 0x01 )
1353	1375	{
1354	1376	return TIA_INPUT_PORT_ALWAYS_ON;
1355	1377	}
r14963	r14964
1361	1383	}
1362	1384	return TIA_INPUT_PORT_ALWAYS_ON;
1363	1385	case 0x05:   /* Joystick w/Boostergrip */
1364		return ( input_port_read(space->machine(), "BUTTONS_R") & 0x40 ) ? TIA_INPUT_PORT_ALWAYS_OFF : TIA_INPUT_PORT_ALWAYS_ON;
	1386	return ( input_port_read(machine(), "BUTTONS_R") & 0x40 ) ? TIA_INPUT_PORT_ALWAYS_OFF : TIA_INPUT_PORT_ALWAYS_ON;
1365	1387	default:
1366	1388	return TIA_INPUT_PORT_ALWAYS_OFF;
1367	1389	}
1368	1390	break;
1369	1391	case 3:   /* Right controller port PIN 9 */
1370		switch ( input_port_read(space->machine(), "CONTROLLERS") % CATEGORY_SELECT )
	1392	switch ( input_port_read(machine(), "CONTROLLERS") % CATEGORY_SELECT )
1371	1393	{
1372	1394	case 0x00:   /* Joystick */
1373	1395	return TIA_INPUT_PORT_ALWAYS_OFF;
1374	1396	case 0x01:   /* Paddle */
1375		return input_port_read(space->machine(), "PADDLE4");
	1397	return input_port_read(machine(), "PADDLE4");
1376	1398	case 0x03:   /* Keypad */
1377	1399	for ( i = 0; i < 4; i++ )
1378	1400	{
1379		if ( ! ( ( state->m_keypad_right_column >> i ) & 0x01 ) )
	1401	if ( ! ( ( m_keypad_right_column >> i ) & 0x01 ) )
1380	1402	{
1381		if ( ( input_port_read(space->machine(), "KEYPAD_R") >> 3*i ) & 0x02 )
	1403	if ( ( input_port_read(machine(), "KEYPAD_R") >> 3*i ) & 0x02 )
1382	1404	{
1383	1405	return TIA_INPUT_PORT_ALWAYS_ON;
1384	1406	}
r14963	r14964
1390	1412	}
1391	1413	return TIA_INPUT_PORT_ALWAYS_ON;
1392	1414	case 0x05:   /* Joystick w/Boostergrip */
1393		return ( input_port_read(space->machine(), "BUTTONS_R") & 0x20 ) ? TIA_INPUT_PORT_ALWAYS_OFF : TIA_INPUT_PORT_ALWAYS_ON;
	1415	return ( input_port_read(machine(), "BUTTONS_R") & 0x20 ) ? TIA_INPUT_PORT_ALWAYS_OFF : TIA_INPUT_PORT_ALWAYS_ON;
1394	1416	default:
1395	1417	return TIA_INPUT_PORT_ALWAYS_OFF;
1396	1418	}
1397	1419	break;
1398	1420	case 4:   /* Left controller port PIN 6 */
1399		switch ( input_port_read(space->machine(), "CONTROLLERS") / CATEGORY_SELECT )
	1421	switch ( input_port_read(machine(), "CONTROLLERS") / CATEGORY_SELECT )
1400	1422	{
1401	1423	case 0x00:   /* Joystick */
1402	1424	case 0x05:   /* Joystick w/Boostergrip */
1403		return input_port_read(space->machine(), "BUTTONS_L");
	1425	return input_port_read(machine(), "BUTTONS_L");
1404	1426	case 0x01:   /* Paddle */
1405	1427	return 0xff;
1406	1428	case 0x02:   /* Driving */
1407		return input_port_read(space->machine(), "BUTTONS_L") << 3;
	1429	return input_port_read(machine(), "BUTTONS_L") << 3;
1408	1430	case 0x03:   /* Keypad */
1409	1431	for ( i = 0; i < 4; i++ )
1410	1432	{
1411		if ( ! ( ( state->m_keypad_left_column >> i ) & 0x01 ) )
	1433	if ( ! ( ( m_keypad_left_column >> i ) & 0x01 ) )
1412	1434	{
1413		if ( ( input_port_read(space->machine(), "KEYPAD_L") >> 3*i ) & 0x04 )
	1435	if ( ( input_port_read(machine(), "KEYPAD_L") >> 3*i ) & 0x04 )
1414	1436	{
1415	1437	return 0xff;
1416	1438	}
r14963	r14964
1422	1444	}
1423	1445	return 0xff;
1424	1446	case 0x06:   /* Trakball CX-22 */
1425		return input_port_read(space->machine(), "BUTTONS_L") << 4;
	1447	return input_port_read(machine(), "BUTTONS_L") << 4;
1426	1448	default:
1427	1449	return 0xff;
1428	1450	}
1429	1451	break;
1430	1452	case 5:   /* Right controller port PIN 6 */
1431		switch ( input_port_read(space->machine(), "CONTROLLERS") % CATEGORY_SELECT )
	1453	switch ( input_port_read(machine(), "CONTROLLERS") % CATEGORY_SELECT )
1432	1454	{
1433	1455	case 0x00:   /* Joystick */
1434	1456	case 0x05:   /* Joystick w/Boostergrip */
1435		return input_port_read(space->machine(), "BUTTONS_R");
	1457	return input_port_read(machine(), "BUTTONS_R");
1436	1458	case 0x01:   /* Paddle */
1437	1459	return 0xff;
1438	1460	case 0x02:   /* Driving */
1439		return input_port_read(space->machine(), "BUTTONS_R") << 3;
	1461	return input_port_read(machine(), "BUTTONS_R") << 3;
1440	1462	case 0x03:   /* Keypad */
1441	1463	for ( i = 0; i < 4; i++ )
1442	1464	{
1443		if ( ! ( ( state->m_keypad_right_column >> i ) & 0x01 ) )
	1465	if ( ! ( ( m_keypad_right_column >> i ) & 0x01 ) )
1444	1466	{
1445		if ( ( input_port_read(space->machine(), "KEYPAD_R") >> 3*i ) & 0x04 )
	1467	if ( ( input_port_read(machine(), "KEYPAD_R") >> 3*i ) & 0x04 )
1446	1468	{
1447	1469	return 0xff;
1448	1470	}
r14963	r14964
1454	1476	}
1455	1477	return 0xff;
1456	1478	case 0x06:   /* Trakball CX-22 */
1457		return input_port_read(space->machine(), "BUTTONS_R") << 4;
	1479	return input_port_read(machine(), "BUTTONS_R") << 4;
1458	1480	default:
1459	1481	return 0xff;
1460	1482	}
r14963	r14964
1471	1493	Q-Bert's Qubes (NTSC,F6) at 0x1594
1472	1494	Berzerk at 0xF093.
1473	1495	*/
1474		static READ8_HANDLER(a2600_get_databus_contents)
	1496	READ8_MEMBER(a2600_state::a2600_get_databus_contents)
1475	1497	{
1476	1498	UINT16   last_address, prev_address;
1477	1499	UINT8   last_byte, prev_byte;
1478	1500
1479		last_address = cpu_get_pc(space->machine().device("maincpu")) - 1;
	1501	last_address = cpu_get_pc(machine().device("maincpu")) - 1;
1480	1502	if ( ! ( last_address & 0x1080 ) )
1481	1503	{
1482	1504	return offset;
1483	1505	}
1484		last_byte = space->read_byte(last_address );
	1506	last_byte = space.read_byte(last_address );
1485	1507	if ( last_byte < 0x80 || last_byte == 0xFF )
1486	1508	{
1487	1509	return last_byte;
r14963	r14964
1491	1513	{
1492	1514	return last_byte;
1493	1515	}
1494		prev_byte = space->read_byte(prev_address );
	1516	prev_byte = space.read_byte(prev_address );
1495	1517	if ( prev_byte == 0xB1 )
1496	1518	{   /* LDA (XX),Y */
1497		return space->read_byte(last_byte + 1 );
	1519	return space.read_byte(last_byte + 1 );
1498	1520	}
1499	1521	return last_byte;
1500	1522	}
r14963	r14964
1508	1530	};
1509	1531	#endif
1510	1532
1511		static WRITE16_HANDLER( a2600_tia_vsync_callback )
	1533	WRITE16_MEMBER(a2600_state::a2600_tia_vsync_callback)
1512	1534	{
1513		a2600_state *state = space->machine().driver_data<a2600_state>();
1514	1535	int i;
1515	1536
1516	1537	for ( i = 0; i < ARRAY_LENGTH(supported_screen_heights); i++ )
1517	1538	{
1518	1539	if ( data >= supported_screen_heights[i] - 3 && data <= supported_screen_heights[i] + 3 )
1519	1540	{
1520		if ( supported_screen_heights[i] != state->m_current_screen_height )
	1541	if ( supported_screen_heights[i] != m_current_screen_height )
1521	1542	{
1522		state->m_current_screen_height = supported_screen_heights[i];
1523		//              machine.primary_screen->configure(228, state->m_current_screen_height, &visarea[i], HZ_TO_ATTOSECONDS( MASTER_CLOCK_NTSC ) * 228 * state->m_current_screen_height );
	1543	m_current_screen_height = supported_screen_heights[i];
	1544	//              machine.primary_screen->configure(228, m_current_screen_height, &visarea[i], HZ_TO_ATTOSECONDS( MASTER_CLOCK_NTSC ) * 228 * m_current_screen_height );
1524	1545	}
1525	1546	}
1526	1547	}
1527	1548	}
1528	1549
1529		static WRITE16_HANDLER( a2600_tia_vsync_callback_pal )
	1550	WRITE16_MEMBER(a2600_state::a2600_tia_vsync_callback_pal)
1530	1551	{
1531		a2600_state *state = space->machine().driver_data<a2600_state>();
1532	1552	int i;
1533	1553
1534	1554	for ( i = 0; i < ARRAY_LENGTH(supported_screen_heights); i++ )
1535	1555	{
1536	1556	if ( data >= supported_screen_heights[i] - 3 && data <= supported_screen_heights[i] + 3 )
1537	1557	{
1538		if ( supported_screen_heights[i] != state->m_current_screen_height )
	1558	if ( supported_screen_heights[i] != m_current_screen_height )
1539	1559	{
1540		state->m_current_screen_height = supported_screen_heights[i];
1541		//              machine.primary_screen->configure(228, state->m_current_screen_height, &visarea[i], HZ_TO_ATTOSECONDS( MASTER_CLOCK_PAL ) * 228 * state->m_current_screen_height );
	1560	m_current_screen_height = supported_screen_heights[i];
	1561	//              machine.primary_screen->configure(228, m_current_screen_height, &visarea[i], HZ_TO_ATTOSECONDS( MASTER_CLOCK_PAL ) * 228 * m_current_screen_height );
1542	1562	}
1543	1563	}
1544	1564	}
1545	1565	}
1546	1566
1547		static const struct tia_interface tia_interface =
	1567	static const tia_interface a2600_tia_interface =
1548	1568	{
1549		a2600_read_input_port,
1550		a2600_get_databus_contents,
1551		a2600_tia_vsync_callback
	1569	DEVCB_NULL,//DEVCB_DRIVER_MEMBER(a2600_state, a2600_read_input_port),
	1570	DEVCB_DRIVER_MEMBER(a2600_state, a2600_get_databus_contents),
	1571	DEVCB_NULL,//DEVCB_DRIVER_MEMBER(a2600_state, a2600_tia_vsync_callback)
1552	1572	};
1553	1573
1554		static const struct tia_interface tia_interface_pal =
	1574	static const tia_interface a2600_tia_interface_pal =
1555	1575	{
1556		a2600_read_input_port,
1557		a2600_get_databus_contents,
1558		a2600_tia_vsync_callback_pal
	1576	DEVCB_NULL,//DEVCB_DRIVER_MEMBER(a2600_state, a2600_read_input_port),
	1577	DEVCB_DRIVER_MEMBER(a2600_state, a2600_get_databus_contents),
	1578	DEVCB_NULL,//DEVCB_DRIVER_MEMBER(a2600_state, a2600_tia_vsync_callback_pal)
1559	1579	};
1560	1580
1561	1581
r14963	r14964
1573	1593	static MACHINE_START( a2600 )
1574	1594	{
1575	1595	common_init(machine);
1576		tia_init( machine, &tia_interface );
1577	1596	}
1578	1597
1579	1598	static MACHINE_START( a2600p )
1580	1599	{
1581	1600	common_init(machine);
1582		tia_init( machine, &tia_interface_pal );
1583	1601	}
1584	1602
1585	1603	#ifdef UNUSED_FUNCTIONS
r14963	r14964
1890	1908
1891	1909	if (state->m_banking_mode == modeDC)
1892	1910	{
1893		space->install_legacy_read_handler(0x1fec, 0x1fec, FUNC(current_bank_r));
	1911	space->install_read_handler(0x1fec, 0x1fec, read8_delegate(FUNC(a2600_state::current_bank_r),state));
1894	1912	}
1895	1913
1896	1914	/* set up bank switch registers */
r14963	r14964
1898	1916	switch (state->m_banking_mode)
1899	1917	{
1900	1918	case modeF8:
1901		space->install_legacy_write_handler(0x1ff8, 0x1ff9, FUNC(modeF8_switch_w));
1902		space->install_legacy_read_handler(0x1ff8, 0x1ff9, FUNC(modeF8_switch_r));
	1919	space->install_write_handler(0x1ff8, 0x1ff9, write8_delegate(FUNC(a2600_state::modeF8_switch_w),state));
	1920	space->install_read_handler(0x1ff8, 0x1ff9, read8_delegate(FUNC(a2600_state::modeF8_switch_r),state));
1903	1921	break;
1904	1922
1905	1923	case modeFA:
1906		space->install_legacy_write_handler(0x1ff8, 0x1ffa, FUNC(modeFA_switch_w));
1907		space->install_legacy_read_handler(0x1ff8, 0x1ffa, FUNC(modeFA_switch_r));
	1924	space->install_write_handler(0x1ff8, 0x1ffa, write8_delegate(FUNC(a2600_state::modeFA_switch_w),state));
	1925	space->install_read_handler(0x1ff8, 0x1ffa, read8_delegate(FUNC(a2600_state::modeFA_switch_r),state));
1908	1926	break;
1909	1927
1910	1928	case modeF6:
1911		space->install_legacy_write_handler(0x1ff6, 0x1ff9, FUNC(modeF6_switch_w));
1912		space->install_legacy_read_handler(0x1ff6, 0x1ff9, FUNC(modeF6_switch_r));
	1929	space->install_write_handler(0x1ff6, 0x1ff9, write8_delegate(FUNC(a2600_state::modeF6_switch_w),state));
	1930	space->install_read_handler(0x1ff6, 0x1ff9, read8_delegate(FUNC(a2600_state::modeF6_switch_r),state));
1913	1931	space->set_direct_update_handler(direct_update_delegate(FUNC(a2600_state::modeF6_opbase), state));
1914	1932	break;
1915	1933
1916	1934	case modeF4:
1917		space->install_legacy_write_handler(0x1ff4, 0x1ffb, FUNC(modeF4_switch_w));
1918		space->install_legacy_read_handler(0x1ff4, 0x1ffb, FUNC(modeF4_switch_r));
	1935	space->install_write_handler(0x1ff4, 0x1ffb, write8_delegate(FUNC(a2600_state::modeF4_switch_w),state));
	1936	space->install_read_handler(0x1ff4, 0x1ffb, read8_delegate(FUNC(a2600_state::modeF4_switch_r),state));
1919	1937	break;
1920	1938
1921	1939	case modeE0:
1922		space->install_legacy_write_handler(0x1fe0, 0x1ff8, FUNC(modeE0_switch_w));
1923		space->install_legacy_read_handler(0x1fe0, 0x1ff8, FUNC(modeE0_switch_r));
	1940	space->install_write_handler(0x1fe0, 0x1ff8, write8_delegate(FUNC(a2600_state::modeE0_switch_w),state));
	1941	space->install_read_handler(0x1fe0, 0x1ff8, read8_delegate(FUNC(a2600_state::modeE0_switch_r),state));
1924	1942	break;
1925	1943
1926	1944	case mode3F:
1927		space->install_legacy_write_handler(0x00, 0x3f, FUNC(mode3F_switch_w));
	1945	space->install_write_handler(0x00, 0x3f, write8_delegate(FUNC(a2600_state::mode3F_switch_w),state));
1928	1946	break;
1929	1947
1930	1948	case modeUA:
1931		space->install_legacy_write_handler(0x200, 0x27f, FUNC(modeUA_switch_w));
1932		space->install_legacy_read_handler(0x200, 0x27f, FUNC(modeUA_switch_r));
	1949	space->install_write_handler(0x200, 0x27f, write8_delegate(FUNC(a2600_state::modeUA_switch_w),state));
	1950	space->install_read_handler(0x200, 0x27f, read8_delegate(FUNC(a2600_state::modeUA_switch_r),state));
1933	1951	break;
1934	1952
1935	1953	case modeE7:
1936		space->install_legacy_write_handler(0x1fe0, 0x1fe7, FUNC(modeE7_switch_w));
1937		space->install_legacy_read_handler(0x1fe0, 0x1fe7, FUNC(modeE7_switch_r));
1938		space->install_legacy_write_handler(0x1fe8, 0x1feb, FUNC(modeE7_RAM_switch_w));
1939		space->install_legacy_read_handler(0x1fe8, 0x1feb, FUNC(modeE7_RAM_switch_r));
	1954	space->install_write_handler(0x1fe0, 0x1fe7, write8_delegate(FUNC(a2600_state::modeE7_switch_w),state));
	1955	space->install_read_handler(0x1fe0, 0x1fe7, read8_delegate(FUNC(a2600_state::modeE7_switch_r),state));
	1956	space->install_write_handler(0x1fe8, 0x1feb, write8_delegate(FUNC(a2600_state::modeE7_RAM_switch_w),state));
	1957	space->install_read_handler(0x1fe8, 0x1feb, read8_delegate(FUNC(a2600_state::modeE7_RAM_switch_r),state));
1940	1958	space->install_readwrite_bank(0x1800, 0x18ff, "bank9");
1941	1959	memory_set_bankptr(machine, "bank9", state->m_extra_RAM->base() + 4 * 256 );
1942	1960	break;
1943	1961
1944	1962	case modeDC:
1945		space->install_legacy_write_handler(0x1ff0, 0x1ff0, FUNC(modeDC_switch_w));
1946		space->install_legacy_read_handler(0x1ff0, 0x1ff0, FUNC(modeDC_switch_r));
	1963	space->install_write_handler(0x1ff0, 0x1ff0, write8_delegate(FUNC(a2600_state::modeDC_switch_w),state));
	1964	space->install_read_handler(0x1ff0, 0x1ff0, read8_delegate(FUNC(a2600_state::modeDC_switch_r),state));
1947	1965	break;
1948	1966
1949	1967	case modeFE:
1950		space->install_legacy_write_handler(0x01fe, 0x01fe, FUNC(modeFE_switch_w));
1951		space->install_legacy_read_handler(0x01fe, 0x01fe, FUNC(modeFE_switch_r));
	1968	space->install_write_handler(0x01fe, 0x01fe, write8_delegate(FUNC(a2600_state::modeFE_switch_w),state));
	1969	space->install_read_handler(0x01fe, 0x01fe, read8_delegate(FUNC(a2600_state::modeFE_switch_r),state));
1952	1970	break;
1953	1971
1954	1972	case mode3E:
1955		space->install_legacy_write_handler(0x3e, 0x3e, FUNC(mode3E_RAM_switch_w));
1956		space->install_legacy_write_handler(0x3f, 0x3f, FUNC(mode3E_switch_w));
1957		space->install_legacy_write_handler(0x1400, 0x15ff, FUNC(mode3E_RAM_w));
	1973	space->install_write_handler(0x3e, 0x3e, write8_delegate(FUNC(a2600_state::mode3E_RAM_switch_w),state));
	1974	space->install_write_handler(0x3f, 0x3f, write8_delegate(FUNC(a2600_state::mode3E_switch_w),state));
	1975	space->install_write_handler(0x1400, 0x15ff, write8_delegate(FUNC(a2600_state::mode3E_RAM_w),state));
1958	1976	break;
1959	1977
1960	1978	case modeSS:
1961		space->install_legacy_read_handler(0x1000, 0x1fff, FUNC(modeSS_r));
	1979	space->install_read_handler(0x1000, 0x1fff, read8_delegate(FUNC(a2600_state::modeSS_r),state));
1962	1980	state->m_bank_base[1] = state->m_extra_RAM->base() + 2 * 0x800;
1963	1981	state->m_bank_base[2] = CART;
1964	1982	memory_set_bankptr(machine, "bank1", state->m_bank_base[1] );
r14963	r14964
1971	1989	break;
1972	1990
1973	1991	case modeFV:
1974		space->install_legacy_write_handler(0x1fd0, 0x1fd0, FUNC(modeFV_switch_w));
1975		space->install_legacy_read_handler(0x1fd0, 0x1fd0, FUNC(modeFV_switch_r));
	1992	space->install_write_handler(0x1fd0, 0x1fd0, write8_delegate(FUNC(a2600_state::modeFV_switch_w),state));
	1993	space->install_read_handler(0x1fd0, 0x1fd0, read8_delegate(FUNC(a2600_state::modeFV_switch_r),state));
1976	1994	break;
1977	1995
1978	1996	case modeDPC:
1979		space->install_legacy_read_handler(0x1000, 0x103f, FUNC(modeDPC_r));
1980		space->install_legacy_write_handler(0x1040, 0x107f, FUNC(modeDPC_w));
1981		space->install_legacy_write_handler(0x1ff8, 0x1ff9, FUNC(modeF8_switch_w));
1982		space->install_legacy_read_handler(0x1ff8, 0x1ff9, FUNC(modeF8_switch_r));
	1997	space->install_read_handler(0x1000, 0x103f, read8_delegate(FUNC(a2600_state::modeDPC_r),state));
	1998	space->install_write_handler(0x1040, 0x107f, write8_delegate(FUNC(a2600_state::modeDPC_w),state));
	1999	space->install_write_handler(0x1ff8, 0x1ff9, write8_delegate(FUNC(a2600_state::modeF8_switch_w),state));
	2000	space->install_read_handler(0x1ff8, 0x1ff9, read8_delegate(FUNC(a2600_state::modeF8_switch_r),state));
1983	2001	space->set_direct_update_handler(direct_update_delegate(FUNC(a2600_state::modeDPC_opbase_handler), state));
1984	2002	{
1985	2003	int   data_fetcher;
r14963	r14964
1999	2017	break;
2000	2018
2001	2019	case modeJVP:
2002		space->install_legacy_read_handler(0x0FA0, 0x0FC0, FUNC(modeJVP_switch_r));
2003		space->install_legacy_write_handler(0x0FA0, 0x0FC0, FUNC(modeJVP_switch_w));
	2020	space->install_read_handler(0x0FA0, 0x0FC0, read8_delegate(FUNC(a2600_state::modeJVP_switch_r),state));
	2021	space->install_write_handler(0x0FA0, 0x0FC0, write8_delegate(FUNC(a2600_state::modeJVP_switch_w),state));
2004	2022	break;
2005	2023	}
2006	2024
r14963	r14964
2218	2236	MCFG_MACHINE_RESET(a2600)
2219	2237
2220	2238	/* video hardware */
	2239	MCFG_TIA_VIDEO_ADD("tia_video", a2600_tia_interface)
	2240
2221	2241	MCFG_SCREEN_ADD("screen", RASTER)
2222	2242	MCFG_SCREEN_RAW_PARAMS( MASTER_CLOCK_NTSC, 228, 26, 26 + 160 + 16, 262, 24 , 24 + 192 + 31 )
2223		MCFG_SCREEN_UPDATE_STATIC(tia)
	2243	MCFG_SCREEN_UPDATE_DEVICE("tia_video", tia_video_device, screen_update)
2224	2244
2225	2245	MCFG_PALETTE_LENGTH( TIA_PALETTE_LENGTH )
2226	2246	MCFG_PALETTE_INIT(tia_NTSC)
2227	2247
2228		MCFG_VIDEO_START(tia)
2229
2230	2248	/* sound hardware */
2231	2249	MCFG_SPEAKER_STANDARD_MONO("mono")
2232	2250	MCFG_SOUND_ADD("tia", TIA, MASTER_CLOCK_NTSC/114)
r14963	r14964
2251	2269	MCFG_MACHINE_RESET(a2600)
2252	2270
2253	2271	/* video hardware */
	2272	MCFG_DEVICE_REMOVE("tia_video")
	2273	MCFG_TIA_VIDEO_ADD("tia_video", a2600_tia_interface_pal)
	2274
2254	2275	MCFG_SCREEN_ADD("screen", RASTER)
2255	2276	MCFG_SCREEN_RAW_PARAMS( MASTER_CLOCK_PAL, 228, 26, 26 + 160 + 16, 312, 32, 32 + 228 + 31 )
2256		MCFG_SCREEN_UPDATE_STATIC(tia)
	2277	MCFG_SCREEN_UPDATE_DEVICE("tia_video", tia_video_device, screen_update)
2257	2278
2258	2279	MCFG_PALETTE_LENGTH( TIA_PALETTE_LENGTH )
2259	2280	MCFG_PALETTE_INIT(tia_PAL)
2260	2281
2261		MCFG_VIDEO_START(tia)
2262
2263	2282	/* sound hardware */
2264	2283	MCFG_SPEAKER_STANDARD_MONO("mono")
2265	2284	MCFG_SOUND_ADD("tia", TIA, MASTER_CLOCK_PAL/114)

src/mess/drivers/pcw.c

r14963	r14964
212	212
213	213
214	214	/* Keyboard is read by the MCU and sent as serial data to the gate array ASIC */
215		static  READ8_HANDLER(pcw_keyboard_r)
	215	READ8_MEMBER(pcw_state::pcw_keyboard_r)
216	216	{
217	217	static const char *const keynames[] = {
218	218	"LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7",
219	219	"LINE8", "LINE9", "LINE10", "LINE11", "LINE12", "LINE13", "LINE14", "LINE15"
220	220	};
221	221
222		return input_port_read(space->machine(), keynames[offset]);
	222	return input_port_read(machine(), keynames[offset]);
223	223	}
224	224
225		static READ8_HANDLER(pcw_keyboard_data_r)
	225	READ8_MEMBER(pcw_state::pcw_keyboard_data_r)
226	226	{
227		pcw_state *state = space->machine().driver_data<pcw_state>();
228		return state->m_mcu_keyboard_data[offset];
	227	return m_mcu_keyboard_data[offset];
229	228	}
230	229
231	230	/* -----------------------------------------------------------------------
r14963	r14964
234	233
235	234	static void pcw_update_read_memory_block(running_machine &machine, int block, int bank)
236	235	{
	236	pcw_state *state = machine.driver_data<pcw_state>();
237	237	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
238	238	char block_name[10];
239	239
r14963	r14964
243	243	{
244	244	/* when upper 16 bytes are accessed use keyboard read
245	245	handler */
246		space->install_legacy_read_handler(
247		block * 0x04000 + 0x3ff0, block * 0x04000 + 0x3fff, FUNC(
248		pcw_keyboard_data_r));
	246	space->install_read_handler(
	247	block * 0x04000 + 0x3ff0, block * 0x04000 + 0x3fff, read8_delegate(FUNC(pcw_state::pcw_keyboard_data_r),state));
249	248	//      LOG(("MEM: read block %i -> bank %i\n",block,bank));
250	249	}
251	250	else
r14963	r14964
357	356	return state->m_interrupt_counter | (input_port_read(machine, "EXTRA") & (0x040 | 0x010)) | (state->m_system_status & 0x20);
358	357	}
359	358
360		static READ8_HANDLER(pcw_interrupt_counter_r)
	359	READ8_MEMBER(pcw_state::pcw_interrupt_counter_r)
361	360	{
362		pcw_state *state = space->machine().driver_data<pcw_state>();
363	361	int data;
364	362
365	363	/* from Jacob Nevins docs */
366	364
367	365	/* get data */
368		data = pcw_get_sys_status(space->machine());
	366	data = pcw_get_sys_status(machine());
369	367	/* clear int counter */
370		state->m_interrupt_counter = 0;
	368	m_interrupt_counter = 0;
371	369	/* check interrupts */
372		pcw_update_irqs(space->machine());
	370	pcw_update_irqs(machine());
373	371	/* return data */
374	372	//LOG(("SYS: IRQ counter read, returning %02x\n",data));
375	373	return data;
376	374	}
377	375
378	376
379		static WRITE8_HANDLER(pcw_bank_select_w)
	377	WRITE8_MEMBER(pcw_state::pcw_bank_select_w)
380	378	{
381		pcw_state *state = space->machine().driver_data<pcw_state>();
382	379	//LOG(("BANK: %2x %x\n",offset, data));
383		state->m_banks[offset] = data;
	380	m_banks[offset] = data;
384	381
385		pcw_update_mem(space->machine(), offset, data);
386		//  popmessage("RAM Banks: %02x %02x %02x %02x Lock:%02x",state->m_banks[0],state->m_banks[1],state->m_banks[2],state->m_banks[3],state->m_bank_force);
	382	pcw_update_mem(machine(), offset, data);
	383	//  popmessage("RAM Banks: %02x %02x %02x %02x Lock:%02x",m_banks[0],m_banks[1],m_banks[2],m_banks[3],m_bank_force);
387	384	}
388	385
389		static WRITE8_HANDLER(pcw_bank_force_selection_w)
	386	WRITE8_MEMBER(pcw_state::pcw_bank_force_selection_w)
390	387	{
391		pcw_state *state = space->machine().driver_data<pcw_state>();
392		state->m_bank_force = data;
	388	m_bank_force = data;
393	389
394		pcw_update_mem(space->machine(), 0, state->m_banks[0]);
395		pcw_update_mem(space->machine(), 1, state->m_banks[1]);
396		pcw_update_mem(space->machine(), 2, state->m_banks[2]);
397		pcw_update_mem(space->machine(), 3, state->m_banks[3]);
	390	pcw_update_mem(machine(), 0, m_banks[0]);
	391	pcw_update_mem(machine(), 1, m_banks[1]);
	392	pcw_update_mem(machine(), 2, m_banks[2]);
	393	pcw_update_mem(machine(), 3, m_banks[3]);
398	394	}
399	395
400	396
401		static WRITE8_HANDLER(pcw_roller_ram_addr_w)
	397	WRITE8_MEMBER(pcw_state::pcw_roller_ram_addr_w)
402	398	{
403		pcw_state *state = space->machine().driver_data<pcw_state>();
404	399	/*
405	400	Address of roller RAM. b7-5: bank (0-7). b4-1: address / 512. */
406	401
407		state->m_roller_ram_addr = (((data>>5) & 0x07)<<14) |
	402	m_roller_ram_addr = (((data>>5) & 0x07)<<14) |
408	403	((data & 0x01f)<<9);
409		LOG(("Roller-RAM: Address set to 0x%05x\n",state->m_roller_ram_addr));
	404	LOG(("Roller-RAM: Address set to 0x%05x\n",m_roller_ram_addr));
410	405	}
411	406
412		static WRITE8_HANDLER(pcw_pointer_table_top_scan_w)
	407	WRITE8_MEMBER(pcw_state::pcw_pointer_table_top_scan_w)
413	408	{
414		pcw_state *state = space->machine().driver_data<pcw_state>();
415		state->m_roller_ram_offset = data;
416		LOG(("Roller-RAM: offset set to 0x%05x\n",state->m_roller_ram_offset));
	409	m_roller_ram_offset = data;
	410	LOG(("Roller-RAM: offset set to 0x%05x\n",m_roller_ram_offset));
417	411	}
418	412
419		static WRITE8_HANDLER(pcw_vdu_video_control_register_w)
	413	WRITE8_MEMBER(pcw_state::pcw_vdu_video_control_register_w)
420	414	{
421		pcw_state *state = space->machine().driver_data<pcw_state>();
422		state->m_vdu_video_control_register = data;
	415	m_vdu_video_control_register = data;
423	416	LOG(("Roller-RAM: control reg set to 0x%02x\n",data));
424	417	}
425	418
426		static WRITE8_HANDLER(pcw_system_control_w)
	419	WRITE8_MEMBER(pcw_state::pcw_system_control_w)
427	420	{
428		pcw_state *state = space->machine().driver_data<pcw_state>();
429		device_t *fdc = space->machine().device("upd765");
430		device_t *speaker = space->machine().device(BEEPER_TAG);
	421	device_t *fdc = machine().device("upd765");
	422	device_t *speaker = machine().device(BEEPER_TAG);
431	423	LOG(("SYSTEM CONTROL: %d\n",data));
432	424
433	425	switch (data)
r14963	r14964
435	427	/* end bootstrap */
436	428	case 0:
437	429	{
438		state->m_boot = 0;
439		pcw_update_mem(space->machine(), 0, state->m_banks[0]);
	430	m_boot = 0;
	431	pcw_update_mem(machine(), 0, m_banks[0]);
440	432	}
441	433	break;
442	434
443	435	/* reboot */
444	436	case 1:
445	437	{
446		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE);
	438	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE);
447	439	popmessage("SYS: Reboot");
448	440	}
449	441	break;
r14963	r14964
451	443	/* connect fdc interrupt to nmi */
452	444	case 2:
453	445	{
454		int fdc_previous_interrupt_code = state->m_fdc_interrupt_code;
	446	int fdc_previous_interrupt_code = m_fdc_interrupt_code;
455	447
456		state->m_fdc_interrupt_code = 0;
	448	m_fdc_interrupt_code = 0;
457	449
458	450	/* previously connected to INT? */
459	451	if (fdc_previous_interrupt_code == 1)
460	452	{
461	453	/* yes */
462	454
463		pcw_update_irqs(space->machine());
	455	pcw_update_irqs(machine());
464	456	}
465	457
466	458	}
r14963	r14964
470	462	/* connect fdc interrupt to interrupt */
471	463	case 3:
472	464	{
473		int fdc_previous_interrupt_code = state->m_fdc_interrupt_code;
	465	int fdc_previous_interrupt_code = m_fdc_interrupt_code;
474	466
475	467	/* connect to INT */
476		state->m_fdc_interrupt_code = 1;
	468	m_fdc_interrupt_code = 1;
477	469
478	470	/* previously connected to NMI? */
479	471	if (fdc_previous_interrupt_code == 0)
r14963	r14964
481	473	/* yes */
482	474
483	475	/* clear nmi interrupt */
484		state->m_nmi_flag = 0;
	476	m_nmi_flag = 0;
485	477	}
486	478
487	479	/* re-issue interrupt */
488		pcw_update_irqs(space->machine());
	480	pcw_update_irqs(machine());
489	481	}
490	482	break;
491	483
r14963	r14964
493	485	/* connect fdc interrupt to neither */
494	486	case 4:
495	487	{
496		int fdc_previous_interrupt_code = state->m_fdc_interrupt_code;
	488	int fdc_previous_interrupt_code = m_fdc_interrupt_code;
497	489
498		state->m_fdc_interrupt_code = 2;
	490	m_fdc_interrupt_code = 2;
499	491
500	492	/* previously connected to NMI or INT? */
501	493	if ((fdc_previous_interrupt_code == 0) || (fdc_previous_interrupt_code == 1))
r14963	r14964
503	495	/* yes */
504	496
505	497	/* Clear NMI */
506		state->m_nmi_flag = 0;
	498	m_nmi_flag = 0;
507	499	}
508		pcw_update_irqs(space->machine());
	500	pcw_update_irqs(machine());
509	501
510	502	}
511	503	break;
r14963	r14964
542	534	/* disc motor on */
543	535	case 9:
544	536	{
545		floppy_mon_w(floppy_get_device(space->machine(), 0), CLEAR_LINE);
546		floppy_mon_w(floppy_get_device(space->machine(), 1), CLEAR_LINE);
547		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), 1,1);
548		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), 1,1);
	537	floppy_mon_w(floppy_get_device(machine(), 0), CLEAR_LINE);
	538	floppy_mon_w(floppy_get_device(machine(), 1), CLEAR_LINE);
	539	floppy_drive_set_ready_state(floppy_get_device(machine(), 0), 1,1);
	540	floppy_drive_set_ready_state(floppy_get_device(machine(), 1), 1,1);
549	541	}
550	542	break;
551	543
552	544	/* disc motor off */
553	545	case 10:
554	546	{
555		floppy_mon_w(floppy_get_device(space->machine(), 0), ASSERT_LINE);
556		floppy_mon_w(floppy_get_device(space->machine(), 1), ASSERT_LINE);
557		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), 0,1);
558		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), 0,1);
	547	floppy_mon_w(floppy_get_device(machine(), 0), ASSERT_LINE);
	548	floppy_mon_w(floppy_get_device(machine(), 1), ASSERT_LINE);
	549	floppy_drive_set_ready_state(floppy_get_device(machine(), 0), 0,1);
	550	floppy_drive_set_ready_state(floppy_get_device(machine(), 1), 0,1);
559	551	}
560	552	break;
561	553
r14963	r14964
576	568	}
577	569	}
578	570
579		static READ8_HANDLER(pcw_system_status_r)
	571	READ8_MEMBER(pcw_state::pcw_system_status_r)
580	572	{
581	573	/* from Jacob Nevins docs */
582		UINT8 ret = pcw_get_sys_status(space->machine());
	574	UINT8 ret = pcw_get_sys_status(machine());
583	575
584	576	return ret;
585	577	}
586	578
587	579	/* read from expansion hardware - additional hardware not part of
588	580	the PCW custom ASIC */
589		static  READ8_HANDLER(pcw_expansion_r)
	581	READ8_MEMBER(pcw_state::pcw_expansion_r)
590	582	{
591	583	logerror("pcw expansion r: %04x\n",offset+0x080);
592	584
r14963	r14964
595	587	case 0x0e0:
596	588	{
597	589	/* spectravideo joystick */
598		if (input_port_read(space->machine(), "EXTRA") & 0x020)
	590	if (input_port_read(machine(), "EXTRA") & 0x020)
599	591	{
600		return input_port_read(space->machine(), "SPECTRAVIDEO");
	592	return input_port_read(machine(), "SPECTRAVIDEO");
601	593	}
602	594	else
603	595	{
r14963	r14964
609	601	{
610	602
611	603	/* kempston joystick */
612		return input_port_read(space->machine(), "KEMPSTON");
	604	return input_port_read(machine(), "KEMPSTON");
613	605	}
614	606
615	607	case 0x0e1:
r14963	r14964
637	629
638	630	/* write to expansion hardware - additional hardware not part of
639	631	the PCW custom ASIC */
640		static WRITE8_HANDLER(pcw_expansion_w)
	632	WRITE8_MEMBER(pcw_state::pcw_expansion_w)
641	633	{
642	634	logerror("pcw expansion w: %04x %02x\n",offset+0x080, data);
643	635	}
644	636
645		static READ8_HANDLER(pcw_fdc_r)
	637	READ8_MEMBER(pcw_state::pcw_fdc_r)
646	638	{
647		device_t *fdc = space->machine().device("upd765");
	639	device_t *fdc = machine().device("upd765");
648	640	/* from Jacob Nevins docs. FDC I/O is not fully decoded */
649	641	if (offset & 1)
650	642	{
r14963	r14964
654	646	return upd765_status_r(fdc, 0);
655	647	}
656	648
657		static WRITE8_HANDLER(pcw_fdc_w)
	649	WRITE8_MEMBER(pcw_state::pcw_fdc_w)
658	650	{
659		device_t *fdc = space->machine().device("upd765");
	651	device_t *fdc = machine().device("upd765");
660	652	/* from Jacob Nevins docs. FDC I/O is not fully decoded */
661	653	if (offset & 1)
662	654	{
r14963	r14964
681	673	//      state->m_printer_headpos++;
682	674	}
683	675
684		static WRITE8_HANDLER(pcw_printer_data_w)
	676	WRITE8_MEMBER(pcw_state::pcw_printer_data_w)
685	677	{
686		pcw_state *state = space->machine().driver_data<pcw_state>();
687		state->m_printer_data = data;
688		upi41_master_w(space->machine().device("printer_mcu"),0,data);
	678	m_printer_data = data;
	679	upi41_master_w(machine().device("printer_mcu"),0,data);
689	680	logerror("PRN [0xFC]: Sent command %02x\n",data);
690	681	}
691	682
692		static WRITE8_HANDLER(pcw_printer_command_w)
	683	WRITE8_MEMBER(pcw_state::pcw_printer_command_w)
693	684	{
694		pcw_state *state = space->machine().driver_data<pcw_state>();
695		state->m_printer_command = data;
696		upi41_master_w(space->machine().device("printer_mcu"),1,data);
	685	m_printer_command = data;
	686	upi41_master_w(machine().device("printer_mcu"),1,data);
697	687	logerror("PRN [0xFD]: Sent command %02x\n",data);
698	688	}
699	689
r14963	r14964
704	694	// 3 = bad command
705	695	// 5 = print error
706	696	// anything else = no printer
707		static  READ8_HANDLER(pcw_printer_data_r)
	697	READ8_MEMBER(pcw_state::pcw_printer_data_r)
708	698	{
709		return upi41_master_r(space->machine().device("printer_mcu"),0);
	699	return upi41_master_r(machine().device("printer_mcu"),0);
710	700	}
711	701
712	702	// printer status
r14963	r14964
718	708	// bit 2 - paper is present
719	709	// bit 1 - busy
720	710	// bit 0 - controller fault
721		static  READ8_HANDLER(pcw_printer_status_r)
	711	READ8_MEMBER(pcw_state::pcw_printer_status_r)
722	712	{
723		return upi41_master_r(space->machine().device("printer_mcu"),1);
	713	return upi41_master_r(machine().device("printer_mcu"),1);
724	714	}
725	715
726	716	/* MCU handlers */
r14963	r14964
809	799	state->m_printer_p2 |= 0x40;
810	800	}
811	801
812		static READ8_HANDLER(mcu_printer_p1_r)
	802	READ8_MEMBER(pcw_state::mcu_printer_p1_r)
813	803	{
814		pcw_state *state = space->machine().driver_data<pcw_state>();
815	804	//  logerror("PRN: MCU reading data from P1\n");
816		return state->m_printer_pins & 0x00ff;
	805	return m_printer_pins & 0x00ff;
817	806	}
818	807
819		static WRITE8_HANDLER(mcu_printer_p1_w)
	808	WRITE8_MEMBER(pcw_state::mcu_printer_p1_w)
820	809	{
821		pcw_state *state = space->machine().driver_data<pcw_state>();
822		state->m_printer_pins = (state->m_printer_pins & 0x0100) | data;
823		//popmessage("PRN: Print head position = %i",state->m_printer_headpos);
824		logerror("PRN: MCU writing %02x to P1 [%03x/%03x]\n",data,state->m_printer_pins,~state->m_printer_pins & 0x1ff);
	810	m_printer_pins = (m_printer_pins & 0x0100) | data;
	811	//popmessage("PRN: Print head position = %i",m_printer_headpos);
	812	logerror("PRN: MCU writing %02x to P1 [%03x/%03x]\n",data,m_printer_pins,~m_printer_pins & 0x1ff);
825	813	}
826	814
827		static READ8_HANDLER(mcu_printer_p2_r)
	815	READ8_MEMBER(pcw_state::mcu_printer_p2_r)
828	816	{
829	817	UINT8 ret = 0x00;
830		pcw_state *state = space->machine().driver_data<pcw_state>();
831	818	//  logerror("PRN: MCU reading data from P2\n");
832	819	ret |= 0x80;  // make sure bail bar is in
833		ret |= (state->m_printer_p2 & 0x70);
834		ret |= (state->m_printer_pins & 0x100) ? 0x01 : 0x00;  // ninth pin
	820	ret |= (m_printer_p2 & 0x70);
	821	ret |= (m_printer_pins & 0x100) ? 0x01 : 0x00;  // ninth pin
835	822	ret |= 0x0e;
836	823	return ret;
837	824	}
838	825
839		static WRITE8_HANDLER(mcu_printer_p2_w)
	826	WRITE8_MEMBER(pcw_state::mcu_printer_p2_w)
840	827	{
841		pcw_state *state = space->machine().driver_data<pcw_state>();
842	828
843	829	//logerror("PRN: MCU writing %02x to P2\n",data);
844		state->m_printer_p2 = data & 0x70;
	830	m_printer_p2 = data & 0x70;
845	831
846	832	// handle shift/store
847		state->m_printer_serial = data & 0x04;  // data
	833	m_printer_serial = data & 0x04;  // data
848	834	if((data & 0x02) != 0)  // clock
849	835	{
850		state->m_printer_shift <<= 1;
851		if(state->m_printer_serial == 0)
852		state->m_printer_shift &= ~0x01;
	836	m_printer_shift <<= 1;
	837	if(m_printer_serial == 0)
	838	m_printer_shift &= ~0x01;
853	839	else
854		state->m_printer_shift |= 0x01;
	840	m_printer_shift |= 0x01;
855	841	}
856	842	if((data & 0x08) != 0)  // strobe
857	843	{
858		logerror("Strobe active [%02x]\n",state->m_printer_shift);
859		state->m_printer_shift_output = state->m_printer_shift;
860		state->m_prn_stepper->adjust(PERIOD_OF_555_MONOSTABLE(22000,0.00000001));
	844	logerror("Strobe active [%02x]\n",m_printer_shift);
	845	m_printer_shift_output = m_printer_shift;
	846	m_prn_stepper->adjust(PERIOD_OF_555_MONOSTABLE(22000,0.00000001));
861	847	}
862	848
863	849	if(data & 0x40)
864		state->m_prn_pins->adjust(PERIOD_OF_555_MONOSTABLE(22000,0.0000000068));
	850	m_prn_pins->adjust(PERIOD_OF_555_MONOSTABLE(22000,0.0000000068));
865	851
866	852	if(data & 0x01)
867		state->m_printer_pins |= 0x0100;
	853	m_printer_pins |= 0x0100;
868	854	else
869		state->m_printer_pins &= ~0x0100;
870		state->m_printer_p2_prev = data;
	855	m_printer_pins &= ~0x0100;
	856	m_printer_p2_prev = data;
871	857	}
872	858
873	859	// Paper sensor
874		static READ8_HANDLER(mcu_printer_t1_r)
	860	READ8_MEMBER(pcw_state::mcu_printer_t1_r)
875	861	{
876	862	return 1;
877	863	}
878	864
879	865	// Print head location (0 if at left margin, otherwise 1)
880		static READ8_HANDLER(mcu_printer_t0_r)
	866	READ8_MEMBER(pcw_state::mcu_printer_t0_r)
881	867	{
882		pcw_state *state = space->machine().driver_data<pcw_state>();
883	868
884		if(state->m_printer_headpos == 0)
	869	if(m_printer_headpos == 0)
885	870	return 0;
886	871	else
887	872	return 1;
r14963	r14964
894	879	*       bit 1: keyboard serial clock
895	880	*       bit 0: keyboard serial data
896	881	*/
897		static void mcu_transmit_serial(pcw_state *state, UINT8 bit)
	882	void pcw_state::mcu_transmit_serial(UINT8 bit)
898	883	{
899	884	int seq;
900	885
901	886	/* Keyboard data is sent in serial from the MCU through the keyboard port, to the ASIC
902	887	Sends a string of 12-bit sequences, first 4 bits are the RAM location (from &3ff0),
903	888	then 8 bits for the data to be written there. */
904		seq = state->m_mcu_transmit_count % 12;
	889	seq = m_mcu_transmit_count % 12;
905	890	if(seq < 4)
906	891	{
907	892	if(bit == 0)
908		state->m_mcu_selected &= ~(8 >> seq);
	893	m_mcu_selected &= ~(8 >> seq);
909	894	else
910		state->m_mcu_selected |= (8 >> seq);
	895	m_mcu_selected |= (8 >> seq);
911	896	}
912	897	else
913	898	{
914	899	seq -= 4;
915	900	if(bit == 0)
916		state->m_mcu_buffer &= ~(128 >> seq);
	901	m_mcu_buffer &= ~(128 >> seq);
917	902	else
918		state->m_mcu_buffer |= (128 >> seq);
	903	m_mcu_buffer |= (128 >> seq);
919	904	}
920		state->m_mcu_transmit_count++;
921		if(state->m_mcu_transmit_count >= 12)
	905	m_mcu_transmit_count++;
	906	if(m_mcu_transmit_count >= 12)
922	907	{
923		state->m_mcu_keyboard_data[state->m_mcu_selected] = state->m_mcu_buffer;
924		state->m_mcu_transmit_count = 0;
	908	m_mcu_keyboard_data[m_mcu_selected] = m_mcu_buffer;
	909	m_mcu_transmit_count = 0;
925	910	}
926	911	}
927	912
928		static READ8_HANDLER(mcu_kb_scan_r)
	913	READ8_MEMBER(pcw_state::mcu_kb_scan_r)
929	914	{
930		pcw_state *state = space->machine().driver_data<pcw_state>();
931		return state->m_kb_scan_row & 0xff;
	915	return m_kb_scan_row & 0xff;
932	916	}
933	917
934		static WRITE8_HANDLER(mcu_kb_scan_w)
	918	WRITE8_MEMBER(pcw_state::mcu_kb_scan_w)
935	919	{
936		pcw_state *state = space->machine().driver_data<pcw_state>();
937		state->m_kb_scan_row = (state->m_kb_scan_row & 0xff00) | data;
	920	m_kb_scan_row = (m_kb_scan_row & 0xff00) | data;
938	921	}
939	922
940		static READ8_HANDLER(mcu_kb_scan_high_r)
	923	READ8_MEMBER(pcw_state::mcu_kb_scan_high_r)
941	924	{
942		pcw_state *state = space->machine().driver_data<pcw_state>();
943		return (state->m_kb_scan_row & 0xff00) >> 8;
	925	return (m_kb_scan_row & 0xff00) >> 8;
944	926	}
945	927
946		static WRITE8_HANDLER(mcu_kb_scan_high_w)
	928	WRITE8_MEMBER(pcw_state::mcu_kb_scan_high_w)
947	929	{
948		pcw_state *state = space->machine().driver_data<pcw_state>();
949		if((state->m_mcu_prev & 0x02) && !(data & 0x02))  // bit is transmitted on high-to-low clock transition
	930	if((m_mcu_prev & 0x02) && !(data & 0x02))  // bit is transmitted on high-to-low clock transition
950	931	{
951		mcu_transmit_serial(state, data & 0x01);
952		state->m_mcu_transmit_reset_seq = 0;
	932	mcu_transmit_serial(data & 0x01);
	933	m_mcu_transmit_reset_seq = 0;
953	934	}
954	935
955		if((state->m_mcu_prev & 0x01) != (data & 0x01))  // two high->low transitions on the data pin signals the beginning of a new transfer
	936	if((m_mcu_prev & 0x01) != (data & 0x01))  // two high->low transitions on the data pin signals the beginning of a new transfer
956	937	{
957		state->m_mcu_transmit_reset_seq++;
958		if(state->m_mcu_transmit_reset_seq > 3)
959		state->m_mcu_transmit_count = 0;
	938	m_mcu_transmit_reset_seq++;
	939	if(m_mcu_transmit_reset_seq > 3)
	940	m_mcu_transmit_count = 0;
960	941	}
961	942
962		state->m_kb_scan_row = (state->m_kb_scan_row & 0x00ff) | ((data & 0xff) << 8);
963		state->m_mcu_prev = data;
	943	m_kb_scan_row = (m_kb_scan_row & 0x00ff) | ((data & 0xff) << 8);
	944	m_mcu_prev = data;
964	945	}
965	946
966		static READ8_HANDLER(mcu_kb_data_r)
	947	READ8_MEMBER(pcw_state::mcu_kb_data_r)
967	948	{
968		pcw_state *state = space->machine().driver_data<pcw_state>();
969		UINT16 scan_bits = ((state->m_kb_scan_row & 0xf000) >> 4) | (state->m_kb_scan_row & 0xff);
	949	UINT16 scan_bits = ((m_kb_scan_row & 0xf000) >> 4) | (m_kb_scan_row & 0xff);
970	950	int x;
971	951
972	952	for(x=0;x<12;x++)
r14963	r14964
979	959	return 0xff;
980	960	}
981	961
982		static READ8_HANDLER(mcu_kb_t1_r)
	962	READ8_MEMBER(pcw_state::mcu_kb_t1_r)
983	963	{
984	964	return 1;
985	965	}
986	966
987		static READ8_HANDLER(mcu_kb_t0_r)
	967	READ8_MEMBER(pcw_state::mcu_kb_t0_r)
988	968	{
989	969	return 0;
990	970	}
991	971
992	972	/* TODO: Implement parallel port! */
993		static  READ8_HANDLER(pcw9512_parallel_r)
	973	READ8_MEMBER(pcw_state::pcw9512_parallel_r)
994	974	{
995	975	if (offset==1)
996	976	{
r14963	r14964
1002	982	}
1003	983
1004	984	/* TODO: Implement parallel port! */
1005		static WRITE8_HANDLER(pcw9512_parallel_w)
	985	WRITE8_MEMBER(pcw_state::pcw9512_parallel_w)
1006	986	{
1007	987	logerror("pcw9512 parallel w: offs: %04x data: %02x\n",offset,data);
1008	988	}
1009	989
1010	990	static ADDRESS_MAP_START(pcw_io, AS_IO, 8, pcw_state )
1011	991	ADDRESS_MAP_GLOBAL_MASK(0xff)
1012		AM_RANGE(0x000, 0x07f) AM_READWRITE_LEGACY(pcw_fdc_r,               pcw_fdc_w)
1013		AM_RANGE(0x080, 0x0ef) AM_READWRITE_LEGACY(pcw_expansion_r,         pcw_expansion_w)
1014		AM_RANGE(0x0f0, 0x0f3) AM_WRITE_LEGACY(                        pcw_bank_select_w)
1015		AM_RANGE(0x0f4, 0x0f4) AM_READWRITE_LEGACY(pcw_interrupt_counter_r,   pcw_bank_force_selection_w)
1016		AM_RANGE(0x0f5, 0x0f5) AM_WRITE_LEGACY(                        pcw_roller_ram_addr_w)
1017		AM_RANGE(0x0f6, 0x0f6) AM_WRITE_LEGACY(                        pcw_pointer_table_top_scan_w)
1018		AM_RANGE(0x0f7, 0x0f7) AM_WRITE_LEGACY(                        pcw_vdu_video_control_register_w)
1019		AM_RANGE(0x0f8, 0x0f8) AM_READWRITE_LEGACY(pcw_system_status_r,      pcw_system_control_w)
1020		AM_RANGE(0x0fc, 0x0fc) AM_READWRITE_LEGACY(pcw_printer_data_r,         pcw_printer_data_w)
1021		AM_RANGE(0x0fd, 0x0fd) AM_READWRITE_LEGACY(pcw_printer_status_r,      pcw_printer_command_w)
	992	AM_RANGE(0x000, 0x07f) AM_READWRITE(pcw_fdc_r,               pcw_fdc_w)
	993	AM_RANGE(0x080, 0x0ef) AM_READWRITE(pcw_expansion_r,         pcw_expansion_w)
	994	AM_RANGE(0x0f0, 0x0f3) AM_WRITE(                        pcw_bank_select_w)
	995	AM_RANGE(0x0f4, 0x0f4) AM_READWRITE(pcw_interrupt_counter_r,   pcw_bank_force_selection_w)
	996	AM_RANGE(0x0f5, 0x0f5) AM_WRITE(                        pcw_roller_ram_addr_w)
	997	AM_RANGE(0x0f6, 0x0f6) AM_WRITE(                        pcw_pointer_table_top_scan_w)
	998	AM_RANGE(0x0f7, 0x0f7) AM_WRITE(                        pcw_vdu_video_control_register_w)
	999	AM_RANGE(0x0f8, 0x0f8) AM_READWRITE(pcw_system_status_r,      pcw_system_control_w)
	1000	AM_RANGE(0x0fc, 0x0fc) AM_READWRITE(pcw_printer_data_r,         pcw_printer_data_w)
	1001	AM_RANGE(0x0fd, 0x0fd) AM_READWRITE(pcw_printer_status_r,      pcw_printer_command_w)
1022	1002	ADDRESS_MAP_END
1023	1003
1024	1004
1025	1005
1026	1006	static ADDRESS_MAP_START(pcw9512_io, AS_IO, 8, pcw_state )
1027	1007	ADDRESS_MAP_GLOBAL_MASK(0xff)
1028		AM_RANGE(0x000, 0x07f) AM_READWRITE_LEGACY(pcw_fdc_r,               pcw_fdc_w)
1029		AM_RANGE(0x080, 0x0ef) AM_READWRITE_LEGACY(pcw_expansion_r,         pcw_expansion_w)
1030		AM_RANGE(0x0f0, 0x0f3) AM_WRITE_LEGACY(                        pcw_bank_select_w)
1031		AM_RANGE(0x0f4, 0x0f4) AM_READWRITE_LEGACY(pcw_interrupt_counter_r,   pcw_bank_force_selection_w)
1032		AM_RANGE(0x0f5, 0x0f5) AM_WRITE_LEGACY(                        pcw_roller_ram_addr_w)
1033		AM_RANGE(0x0f6, 0x0f6) AM_WRITE_LEGACY(                        pcw_pointer_table_top_scan_w)
1034		AM_RANGE(0x0f7, 0x0f7) AM_WRITE_LEGACY(                        pcw_vdu_video_control_register_w)
1035		AM_RANGE(0x0f8, 0x0f8) AM_READWRITE_LEGACY(pcw_system_status_r,      pcw_system_control_w)
1036		AM_RANGE(0x0fc, 0x0fd) AM_READWRITE_LEGACY(pcw9512_parallel_r,         pcw9512_parallel_w)
	1008	AM_RANGE(0x000, 0x07f) AM_READWRITE(pcw_fdc_r,               pcw_fdc_w)
	1009	AM_RANGE(0x080, 0x0ef) AM_READWRITE(pcw_expansion_r,         pcw_expansion_w)
	1010	AM_RANGE(0x0f0, 0x0f3) AM_WRITE(                        pcw_bank_select_w)
	1011	AM_RANGE(0x0f4, 0x0f4) AM_READWRITE(pcw_interrupt_counter_r,   pcw_bank_force_selection_w)
	1012	AM_RANGE(0x0f5, 0x0f5) AM_WRITE(                        pcw_roller_ram_addr_w)
	1013	AM_RANGE(0x0f6, 0x0f6) AM_WRITE(                        pcw_pointer_table_top_scan_w)
	1014	AM_RANGE(0x0f7, 0x0f7) AM_WRITE(                        pcw_vdu_video_control_register_w)
	1015	AM_RANGE(0x0f8, 0x0f8) AM_READWRITE(pcw_system_status_r,      pcw_system_control_w)
	1016	AM_RANGE(0x0fc, 0x0fd) AM_READWRITE(pcw9512_parallel_r,         pcw9512_parallel_w)
1037	1017	ADDRESS_MAP_END
1038	1018
1039	1019	/* i8041 MCU */
1040	1020	static ADDRESS_MAP_START(pcw_printer_io, AS_IO, 8, pcw_state )
1041		AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_READWRITE_LEGACY(mcu_printer_p2_r,mcu_printer_p2_w)
1042		AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_READWRITE_LEGACY(mcu_printer_p1_r, mcu_printer_p1_w)
1043		AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ_LEGACY(mcu_printer_t1_r)
1044		AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ_LEGACY(mcu_printer_t0_r)
	1021	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_READWRITE(mcu_printer_p2_r,mcu_printer_p2_w)
	1022	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_READWRITE(mcu_printer_p1_r, mcu_printer_p1_w)
	1023	AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ(mcu_printer_t1_r)
	1024	AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ(mcu_printer_t0_r)
1045	1025	ADDRESS_MAP_END
1046	1026
1047	1027	static ADDRESS_MAP_START(pcw_keyboard_io, AS_IO, 8, pcw_state )
1048		AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_READWRITE_LEGACY(mcu_kb_scan_r,mcu_kb_scan_w)
1049		AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_READWRITE_LEGACY(mcu_kb_scan_high_r,mcu_kb_scan_high_w)
1050		AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ_LEGACY(mcu_kb_t1_r)
1051		AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ_LEGACY(mcu_kb_t0_r)
1052		AM_RANGE(MCS48_PORT_BUS, MCS48_PORT_BUS) AM_READ_LEGACY(mcu_kb_data_r)
	1028	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_READWRITE(mcu_kb_scan_r,mcu_kb_scan_w)
	1029	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_READWRITE(mcu_kb_scan_high_r,mcu_kb_scan_high_w)
	1030	AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ(mcu_kb_t1_r)
	1031	AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ(mcu_kb_t0_r)
	1032	AM_RANGE(MCS48_PORT_BUS, MCS48_PORT_BUS) AM_READ(mcu_kb_data_r)
1053	1033	ADDRESS_MAP_END
1054	1034
1055	1035

src/mess/drivers/oric.c

r14963	r14964
69	69	static ADDRESS_MAP_START(telestrat_mem, AS_PROGRAM, 8, oric_state )
70	70	AM_RANGE( 0x0000, 0x02ff) AM_RAM
71	71	AM_RANGE( 0x0300, 0x030f) AM_DEVREADWRITE("via6522_0", via6522_device, read, write)
72		AM_RANGE( 0x0310, 0x031b) AM_READWRITE_LEGACY(oric_microdisc_r, oric_microdisc_w )
	72	AM_RANGE( 0x0310, 0x031b) AM_READWRITE(oric_microdisc_r, oric_microdisc_w )
73	73	AM_RANGE( 0x031c, 0x031f) AM_DEVREADWRITE("acia",  acia6551_device, read, write)
74	74	AM_RANGE( 0x0320, 0x032f) AM_DEVREADWRITE("via6522_1", via6522_device, read, write)
75	75	AM_RANGE( 0x0400, 0xbfff) AM_RAM
r14963	r14964
339	339	AY8910_DEFAULT_LOADS,
340	340	DEVCB_NULL,
341	341	DEVCB_NULL,
342		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, oric_psg_porta_write),
	342	DEVCB_DRIVER_MEMBER(oric_state, oric_psg_porta_write),
343	343	DEVCB_NULL,
344	344	};
345	345

src/mess/drivers/orao.c

r14963	r14964
22	22	static ADDRESS_MAP_START(orao_mem, AS_PROGRAM, 8, orao_state )
23	23	AM_RANGE( 0x0000, 0x5fff ) AM_RAM AM_SHARE("memory")
24	24	AM_RANGE( 0x6000, 0x7fff ) AM_RAM AM_SHARE("video_ram") // video ram
25		AM_RANGE( 0x8000, 0x9fff ) AM_READWRITE_LEGACY(orao_io_r, orao_io_w )
	25	AM_RANGE( 0x8000, 0x9fff ) AM_READWRITE(orao_io_r, orao_io_w )
26	26	AM_RANGE( 0xa000, 0xafff ) AM_RAM  // extension
27	27	AM_RANGE( 0xb000, 0xbfff ) AM_RAM  // DOS
28	28	AM_RANGE( 0xc000, 0xdfff ) AM_ROM

src/mess/drivers/galeb.c

r14963	r14964
22	22
23	23	static WRITE8_DEVICE_HANDLER( galeb_dac_data_w ) { dac_data_w(device, data); }
24	24
25		static READ8_HANDLER( galeb_keyboard_r )
	25	READ8_MEMBER(galeb_state::galeb_keyboard_r)
26	26	{
27	27	static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7" };
28	28
29		return input_port_read(space->machine(), keynames[offset]);
	29	return input_port_read(machine(), keynames[offset]);
30	30	}
31	31
32	32	/* Address maps */
33	33	static ADDRESS_MAP_START(galeb_mem, AS_PROGRAM, 8, galeb_state )
34	34	AM_RANGE( 0x0000, 0x1fff ) AM_RAM  // RAM
35		AM_RANGE( 0xbfe0, 0xbfe7 ) AM_READ_LEGACY(galeb_keyboard_r )
	35	AM_RANGE( 0xbfe0, 0xbfe7 ) AM_READ(galeb_keyboard_r )
36	36	AM_RANGE( 0xbfe0, 0xbfe0 ) AM_DEVWRITE_LEGACY("dac", galeb_dac_data_w )
37	37	AM_RANGE( 0xb000, 0xb3ff ) AM_RAM  AM_SHARE("video_ram") // video ram
38	38	AM_RANGE( 0xc000, 0xc7ff ) AM_ROM  // BASIC 01 ROM

src/mess/drivers/electron.c

r14963	r14964
50	50	AM_RANGE(0x0000, 0x7fff) AM_RAM AM_REGION("maincpu",  0x00000)   /* 32KB of RAM */
51	51	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank2")                        /* Banked ROM pages */
52	52	AM_RANGE(0xc000, 0xfbff) AM_ROM AM_REGION("user1", 0x40000)   /* OS ROM */
53		AM_RANGE(0xfc00, 0xfcff) AM_READWRITE_LEGACY(electron_jim_r, electron_jim_w )         /* JIM pages */
54		AM_RANGE(0xfd00, 0xfdff) AM_READWRITE_LEGACY(electron_1mhz_r, electron_1mhz_w )      /* 1 MHz bus */
55		AM_RANGE(0xfe00, 0xfeff) AM_READWRITE_LEGACY(electron_ula_r, electron_ula_w )         /* Electron ULA */
	53	AM_RANGE(0xfc00, 0xfcff) AM_READWRITE(electron_jim_r, electron_jim_w )         /* JIM pages */
	54	AM_RANGE(0xfd00, 0xfdff) AM_READWRITE(electron_1mhz_r, electron_1mhz_w )      /* 1 MHz bus */
	55	AM_RANGE(0xfe00, 0xfeff) AM_READWRITE(electron_ula_r, electron_ula_w )         /* Electron ULA */
56	56	AM_RANGE(0xff00, 0xffff) AM_ROM AM_REGION("user1", 0x43f00)   /* OS ROM continued */
57	57	ADDRESS_MAP_END
58	58

src/mess/drivers/mikrosha.c

r14963	r14964
32	32	static ADDRESS_MAP_START(mikrosha_mem, AS_PROGRAM, 8, mikrosha_state )
33	33	AM_RANGE( 0x0000, 0x0fff ) AM_RAMBANK("bank1") // First bank
34	34	AM_RANGE( 0x1000, 0x7fff ) AM_RAM // RAM
35		AM_RANGE( 0x8000, 0xbfff ) AM_READ_LEGACY(radio_cpu_state_r) // Not connected
	35	AM_RANGE( 0x8000, 0xbfff ) AM_READ(radio_cpu_state_r) // Not connected
36	36	AM_RANGE( 0xc000, 0xc003 ) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write) AM_MIRROR(0x07fc)
37	37	AM_RANGE( 0xc800, 0xc803 ) AM_DEVREADWRITE("ppi8255_2", i8255_device, read, write) AM_MIRROR(0x07fc)
38	38	AM_RANGE( 0xd000, 0xd001 ) AM_DEVREADWRITE_LEGACY("i8275", i8275_r, i8275_w) AM_MIRROR(0x07fe) // video
39	39	AM_RANGE( 0xd800, 0xd803 ) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r,pit8253_w) AM_MIRROR(0x07fc) // Timer
40		AM_RANGE( 0xe000, 0xf7ff ) AM_READ_LEGACY(radio_cpu_state_r) // Not connected
	40	AM_RANGE( 0xe000, 0xf7ff ) AM_READ(radio_cpu_state_r) // Not connected
41	41	AM_RANGE( 0xf800, 0xffff ) AM_DEVWRITE_LEGACY("dma8257", i8257_w)    // DMA
42	42	AM_RANGE( 0xf800, 0xffff ) AM_ROM  // System ROM
43	43	ADDRESS_MAP_END
44	44
45	45	static ADDRESS_MAP_START( mikrosha_io , AS_IO, 8, mikrosha_state )
46	46	ADDRESS_MAP_UNMAP_HIGH
47		AM_RANGE( 0x00, 0xff ) AM_READWRITE_LEGACY(radio_io_r,radio_io_w)
	47	AM_RANGE( 0x00, 0xff ) AM_READWRITE(radio_io_r,radio_io_w)
48	48	ADDRESS_MAP_END
49	49
50	50	/* Input ports */

src/mess/drivers/irisha.c

r14963	r14964
22	22	ADDRESS_MAP_END
23	23
24	24	static ADDRESS_MAP_START( irisha_io , AS_IO, 8, irisha_state )
25		AM_RANGE( 0x04, 0x05) AM_READ_LEGACY(irisha_keyboard_r)
	25	AM_RANGE( 0x04, 0x05) AM_READ(irisha_keyboard_r)
26	26	AM_RANGE( 0x06, 0x06) AM_DEVREADWRITE("uart",i8251_device, data_r, data_w)
27	27	AM_RANGE( 0x07, 0x07) AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)
28	28	AM_RANGE( 0x08, 0x0B) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r, pit8253_w )

src/mess/drivers/orion.c

r14963	r14964
30	30	static ADDRESS_MAP_START(orion128_mem, AS_PROGRAM, 8, orion_state )
31	31	AM_RANGE( 0x0000, 0xefff ) AM_RAMBANK("bank1")
32	32	AM_RANGE( 0xf000, 0xf3ff ) AM_RAMBANK("bank2")
33		AM_RANGE( 0xf400, 0xf4ff ) AM_READWRITE_LEGACY(orion128_system_r,orion128_system_w)  // Keyboard and cassette
34		AM_RANGE( 0xf500, 0xf5ff ) AM_READWRITE_LEGACY(orion128_romdisk_r,orion128_romdisk_w)
35		AM_RANGE( 0xf700, 0xf7ff ) AM_READWRITE_LEGACY(orion128_floppy_r,orion128_floppy_w)
	33	AM_RANGE( 0xf400, 0xf4ff ) AM_READWRITE(orion128_system_r,orion128_system_w)  // Keyboard and cassette
	34	AM_RANGE( 0xf500, 0xf5ff ) AM_READWRITE(orion128_romdisk_r,orion128_romdisk_w)
	35	AM_RANGE( 0xf700, 0xf7ff ) AM_READWRITE(orion128_floppy_r,orion128_floppy_w)
36	36	AM_RANGE( 0xf800, 0xffff ) AM_ROM
37		AM_RANGE( 0xf800, 0xf8ff ) AM_WRITE_LEGACY(orion128_video_mode_w)
38		AM_RANGE( 0xf900, 0xf9ff ) AM_WRITE_LEGACY(orion128_memory_page_w)
39		AM_RANGE( 0xfa00, 0xfaff ) AM_WRITE_LEGACY(orion128_video_page_w)
	37	AM_RANGE( 0xf800, 0xf8ff ) AM_WRITE(orion128_video_mode_w)
	38	AM_RANGE( 0xf900, 0xf9ff ) AM_WRITE(orion128_memory_page_w)
	39	AM_RANGE( 0xfa00, 0xfaff ) AM_WRITE(orion128_video_page_w)
40	40	ADDRESS_MAP_END
41	41
42	42	/* Orion Z80 Card II */
43	43	static ADDRESS_MAP_START( orion128_io , AS_IO, 8, orion_state )
44	44	ADDRESS_MAP_GLOBAL_MASK(0xff)
45	45	ADDRESS_MAP_UNMAP_HIGH
46		AM_RANGE( 0xf8, 0xf8) AM_WRITE_LEGACY(orion128_video_mode_w )
47		AM_RANGE( 0xf9, 0xf9) AM_WRITE_LEGACY(orion128_memory_page_w )
48		AM_RANGE( 0xfa, 0xfa) AM_WRITE_LEGACY(orion128_video_page_w )
	46	AM_RANGE( 0xf8, 0xf8) AM_WRITE(orion128_video_mode_w )
	47	AM_RANGE( 0xf9, 0xf9) AM_WRITE(orion128_memory_page_w )
	48	AM_RANGE( 0xfa, 0xfa) AM_WRITE(orion128_video_page_w )
49	49	ADDRESS_MAP_END
50	50
51	51	static ADDRESS_MAP_START(orionz80_mem, AS_PROGRAM, 8, orion_state )
r14963	r14964
59	59
60	60	/* Orion Pro */
61	61	static ADDRESS_MAP_START( orionz80_io , AS_IO, 8, orion_state )
62		AM_RANGE( 0x0000, 0xffff) AM_READWRITE_LEGACY(orionz80_io_r, orionz80_io_w )
	62	AM_RANGE( 0x0000, 0xffff) AM_READWRITE(orionz80_io_r, orionz80_io_w )
63	63	ADDRESS_MAP_END
64	64
65	65	static ADDRESS_MAP_START(orionpro_mem, AS_PROGRAM, 8, orion_state )
r14963	r14964
75	75	ADDRESS_MAP_END
76	76
77	77	static ADDRESS_MAP_START( orionpro_io , AS_IO, 8, orion_state )
78		AM_RANGE( 0x0000, 0xffff) AM_READWRITE_LEGACY(orionpro_io_r, orionpro_io_w )
	78	AM_RANGE( 0x0000, 0xffff) AM_READWRITE(orionpro_io_r, orionpro_io_w )
79	79	ADDRESS_MAP_END
80	80
81	81	static const cassette_interface orion_cassette_interface =

src/mess/drivers/bk.c

r14963	r14964
23	23	AM_RANGE( 0xa000, 0xbfff ) AM_ROM  // ROM
24	24	AM_RANGE( 0xc000, 0xdfff ) AM_ROM  // ROM
25	25	AM_RANGE( 0xe000, 0xfeff ) AM_ROM  // ROM
26		AM_RANGE( 0xffb0, 0xffb1 ) AM_READWRITE_LEGACY(bk_key_state_r,bk_key_state_w)
27		AM_RANGE( 0xffb2, 0xffb3 ) AM_READ_LEGACY(bk_key_code_r)
28		AM_RANGE( 0xffb4, 0xffb5 ) AM_READWRITE_LEGACY(bk_vid_scrool_r,bk_vid_scrool_w)
29		AM_RANGE( 0xffce, 0xffcf ) AM_READWRITE_LEGACY(bk_key_press_r,bk_key_press_w)
	26	AM_RANGE( 0xffb0, 0xffb1 ) AM_READWRITE(bk_key_state_r,bk_key_state_w)
	27	AM_RANGE( 0xffb2, 0xffb3 ) AM_READ(bk_key_code_r)
	28	AM_RANGE( 0xffb4, 0xffb5 ) AM_READWRITE(bk_vid_scrool_r,bk_vid_scrool_w)
	29	AM_RANGE( 0xffce, 0xffcf ) AM_READWRITE(bk_key_press_r,bk_key_press_w)
30	30	ADDRESS_MAP_END
31	31
32	32	static ADDRESS_MAP_START(bk0010fd_mem, AS_PROGRAM, 16, bk_state )
r14963	r14964
36	36	AM_RANGE( 0x8000, 0x9fff ) AM_ROM  // ROM
37	37	AM_RANGE( 0xa000, 0xdfff ) AM_RAM  // RAM
38	38	AM_RANGE( 0xe000, 0xfdff ) AM_ROM  // ROM
39		AM_RANGE( 0xfe58, 0xfe59 ) AM_READWRITE_LEGACY(bk_floppy_cmd_r,bk_floppy_cmd_w)
40		AM_RANGE( 0xfe5a, 0xfe5b ) AM_READWRITE_LEGACY(bk_floppy_data_r,bk_floppy_data_w)
41		AM_RANGE( 0xffb0, 0xffb1 ) AM_READWRITE_LEGACY(bk_key_state_r,bk_key_state_w)
42		AM_RANGE( 0xffb2, 0xffb3 ) AM_READ_LEGACY(bk_key_code_r)
43		AM_RANGE( 0xffb4, 0xffb5 ) AM_READWRITE_LEGACY(bk_vid_scrool_r,bk_vid_scrool_w)
44		AM_RANGE( 0xffce, 0xffcf ) AM_READWRITE_LEGACY(bk_key_press_r,bk_key_press_w)
	39	AM_RANGE( 0xfe58, 0xfe59 ) AM_READWRITE(bk_floppy_cmd_r,bk_floppy_cmd_w)
	40	AM_RANGE( 0xfe5a, 0xfe5b ) AM_READWRITE(bk_floppy_data_r,bk_floppy_data_w)
	41	AM_RANGE( 0xffb0, 0xffb1 ) AM_READWRITE(bk_key_state_r,bk_key_state_w)
	42	AM_RANGE( 0xffb2, 0xffb3 ) AM_READ(bk_key_code_r)
	43	AM_RANGE( 0xffb4, 0xffb5 ) AM_READWRITE(bk_vid_scrool_r,bk_vid_scrool_w)
	44	AM_RANGE( 0xffce, 0xffcf ) AM_READWRITE(bk_key_press_r,bk_key_press_w)
45	45	ADDRESS_MAP_END
46	46
47	47	/* Input ports */

src/mess/drivers/a7800.c

r14963	r14964
30	30	***************************************************************************/
31	31
32	32	static ADDRESS_MAP_START( a7800_mem, AS_PROGRAM, 8, a7800_state )
33		AM_RANGE(0x0000, 0x001f) AM_MIRROR(0x300) AM_READWRITE_LEGACY(a7800_TIA_r, a7800_TIA_w)
34		AM_RANGE(0x0020, 0x003f) AM_MIRROR(0x300) AM_READWRITE_LEGACY(a7800_MARIA_r, a7800_MARIA_w)
35		AM_RANGE(0x0040, 0x00ff) AM_READ_BANK("bank5") AM_WRITE_LEGACY(a7800_RAM0_w)   /* RAM (6116 block 0) */
	33	AM_RANGE(0x0000, 0x001f) AM_MIRROR(0x300) AM_READWRITE(a7800_TIA_r, a7800_TIA_w)
	34	AM_RANGE(0x0020, 0x003f) AM_MIRROR(0x300) AM_READWRITE(a7800_MARIA_r, a7800_MARIA_w)
	35	AM_RANGE(0x0040, 0x00ff) AM_READ_BANK("bank5") AM_WRITE(a7800_RAM0_w)   /* RAM (6116 block 0) */
36	36	AM_RANGE(0x0140, 0x01ff) AM_RAMBANK("bank6")   /* RAM (6116 block 1) */
37	37	AM_RANGE(0x0280, 0x02ff) AM_DEVREADWRITE_LEGACY("riot", riot6532_r, riot6532_w)
38	38	AM_RANGE(0x0480, 0x04ff) AM_MIRROR(0x100) AM_RAM   /* RIOT RAM */
r14963	r14964
45	45	AM_RANGE(0xa000, 0xbfff) AM_ROMBANK("bank3")                  /* sc + ac */
46	46	AM_RANGE(0xc000, 0xdfff) AM_ROMBANK("bank4")                  /* ac */
47	47	AM_RANGE(0xe000, 0xffff) AM_ROM
48		AM_RANGE(0x4000, 0xffff) AM_WRITE_LEGACY(a7800_cart_w)
	48	AM_RANGE(0x4000, 0xffff) AM_WRITE(a7800_cart_w)
49	49	ADDRESS_MAP_END
50	50
51	51

src/mess/drivers/nascom1.c

r14963	r14964
86	86
87	87	static ADDRESS_MAP_START( nascom1_io, AS_IO, 8, nascom1_state )
88	88	ADDRESS_MAP_GLOBAL_MASK(0x0F)
89		AM_RANGE(0x00, 0x00) AM_READWRITE_LEGACY(nascom1_port_00_r, nascom1_port_00_w)
90		AM_RANGE(0x01, 0x01) AM_READWRITE_LEGACY(nascom1_port_01_r, nascom1_port_01_w)
91		AM_RANGE(0x02, 0x02) AM_READ_LEGACY(nascom1_port_02_r)
	89	AM_RANGE(0x00, 0x00) AM_READWRITE(nascom1_port_00_r, nascom1_port_00_w)
	90	AM_RANGE(0x01, 0x01) AM_READWRITE(nascom1_port_01_r, nascom1_port_01_w)
	91	AM_RANGE(0x02, 0x02) AM_READ(nascom1_port_02_r)
92	92	AM_RANGE(0x04, 0x07) AM_DEVREADWRITE_LEGACY("z80pio", z80pio_cd_ba_r, z80pio_cd_ba_w )
93	93	ADDRESS_MAP_END
94	94
95	95
96	96	static ADDRESS_MAP_START( nascom2_io, AS_IO, 8, nascom1_state )
97	97	ADDRESS_MAP_GLOBAL_MASK(0xff)
98		AM_RANGE(0x00, 0x00) AM_READWRITE_LEGACY(nascom1_port_00_r, nascom1_port_00_w)
99		AM_RANGE(0x01, 0x01) AM_READWRITE_LEGACY(nascom1_port_01_r, nascom1_port_01_w)
100		AM_RANGE(0x02, 0x02) AM_READ_LEGACY(nascom1_port_02_r)
	98	AM_RANGE(0x00, 0x00) AM_READWRITE(nascom1_port_00_r, nascom1_port_00_w)
	99	AM_RANGE(0x01, 0x01) AM_READWRITE(nascom1_port_01_r, nascom1_port_01_w)
	100	AM_RANGE(0x02, 0x02) AM_READ(nascom1_port_02_r)
101	101	AM_RANGE(0x04, 0x07) AM_DEVREADWRITE_LEGACY("z80pio", z80pio_cd_ba_r, z80pio_cd_ba_w )
102	102	AM_RANGE(0xe0, 0xe3) AM_DEVREADWRITE_LEGACY("wd1793", wd17xx_r, wd17xx_w)
103		AM_RANGE(0xe4, 0xe4) AM_READWRITE_LEGACY(nascom2_fdc_select_r, nascom2_fdc_select_w)
104		AM_RANGE(0xe5, 0xe5) AM_READ_LEGACY(nascom2_fdc_status_r)
	103	AM_RANGE(0xe4, 0xe4) AM_READWRITE(nascom2_fdc_select_r, nascom2_fdc_select_w)
	104	AM_RANGE(0xe5, 0xe5) AM_READ(nascom2_fdc_status_r)
105	105	ADDRESS_MAP_END
106	106
107	107

src/mess/drivers/gmaster.c

r14963	r14964
12	12	#define MAIN_XTAL   12000000
13	13
14	14
15		static READ8_HANDLER( gmaster_io_r )
	15	READ8_MEMBER(gmaster_state::gmaster_io_r)
16	16	{
17		gmaster_state *state = space->machine().driver_data<gmaster_state>();
18	17	UINT8 data = 0;
19		if (state->m_gmachine.ports[2] & 1)
	18	if (m_gmachine.ports[2] & 1)
20	19	{
21		data = space->machine().region("maincpu")->base()[0x4000 + offset];
22		logerror("%.4x external memory %.4x read %.2x\n", (int)cpu_get_reg(&space->device(), CPUINFO_INT_PC), 0x4000 + offset, data);
	20	data = machine().region("maincpu")->base()[0x4000 + offset];
	21	logerror("%.4x external memory %.4x read %.2x\n", (int)cpu_get_reg(&space.device(), CPUINFO_INT_PC), 0x4000 + offset, data);
23	22	}
24	23	else
25	24	{
26	25	switch (offset)
27	26	{
28	27	case 1:
29		data=state->m_video.pixels[state->m_video.y][state->m_video.x];
30		logerror("%.4x lcd x:%.2x y:%.2x %.4x read %.2x\n", (int)cpu_get_reg(&space->device(), CPUINFO_INT_PC), state->m_video.x, state->m_video.y, 0x4000 + offset, data);
31		if (!(state->m_video.mode) && state->m_video.delayed)
32		state->m_video.x++;
33		state->m_video.delayed = TRUE;
	28	data=m_video.pixels[m_video.y][m_video.x];
	29	logerror("%.4x lcd x:%.2x y:%.2x %.4x read %.2x\n", (int)cpu_get_reg(&space.device(), CPUINFO_INT_PC), m_video.x, m_video.y, 0x4000 + offset, data);
	30	if (!(m_video.mode) && m_video.delayed)
	31	m_video.x++;
	32	m_video.delayed = TRUE;
34	33	break;
35	34	default:
36		logerror("%.4x memory %.4x read %.2x\n", (int)cpu_get_reg(&space->device(), CPUINFO_INT_PC), 0x4000 + offset, data);
	35	logerror("%.4x memory %.4x read %.2x\n", (int)cpu_get_reg(&space.device(), CPUINFO_INT_PC), 0x4000 + offset, data);
37	36	}
38	37	}
39	38	return data;
40	39	}
41	40
42		#define BLITTER_Y ((state->m_gmachine.ports[2]&4)|(state->m_video.data[0]&3))
	41	#define BLITTER_Y ((m_gmachine.ports[2]&4)|(m_video.data[0]&3))
43	42
44		static WRITE8_HANDLER( gmaster_io_w )
	43	WRITE8_MEMBER(gmaster_state::gmaster_io_w)
45	44	{
46		gmaster_state *state = space->machine().driver_data<gmaster_state>();
47		if (state->m_gmachine.ports[2] & 1)
	45	if (m_gmachine.ports[2] & 1)
48	46	{
49		space->machine().region("maincpu")->base()[0x4000 + offset] = data;
50		logerror("%.4x external memory %.4x written %.2x\n", (int)cpu_get_reg(&space->device(), CPUINFO_INT_PC), 0x4000 + offset, data);
	47	machine().region("maincpu")->base()[0x4000 + offset] = data;
	48	logerror("%.4x external memory %.4x written %.2x\n", (int)cpu_get_reg(&space.device(), CPUINFO_INT_PC), 0x4000 + offset, data);
51	49	}
52	50	else
53	51	{
54	52	switch (offset)
55	53	{
56	54	case 0:
57		state->m_video.delayed=FALSE;
58		logerror("%.4x lcd %.4x written %.2x\n", (int)cpu_get_reg(&space->device(), CPUINFO_INT_PC), 0x4000 + offset, data);
	55	m_video.delayed=FALSE;
	56	logerror("%.4x lcd %.4x written %.2x\n", (int)cpu_get_reg(&space.device(), CPUINFO_INT_PC), 0x4000 + offset, data);
59	57	// e2 af a4 a0 a9 falling block init for both halves
60	58	if ((data & 0xfc) == 0xb8)
61	59	{
62		state->m_video.index = 0;
63		state->m_video.data[state->m_video.index] = data;
64		state->m_video.y = BLITTER_Y;
	60	m_video.index = 0;
	61	m_video.data[m_video.index] = data;
	62	m_video.y = BLITTER_Y;
65	63	}
66	64	else if ((data & 0xc0) == 0)
67	65	{
68		state->m_video.x = data;
	66	m_video.x = data;
69	67	}
70	68	else if ((data & 0xf0) == 0xe0)
71	69	{
72		state->m_video.mode = (data & 0xe) ? FALSE : TRUE;
	70	m_video.mode = (data & 0xe) ? FALSE : TRUE;
73	71	}
74		state->m_video.data[state->m_video.index] = data;
75		state->m_video.index = (state->m_video.index + 1) & 7;
	72	m_video.data[m_video.index] = data;
	73	m_video.index = (m_video.index + 1) & 7;
76	74	break;
77	75	case 1:
78		state->m_video.delayed = FALSE;
79		if (state->m_video.x < ARRAY_LENGTH(state->m_video.pixels[0])) // continental galaxy flutlicht
80		state->m_video.pixels[state->m_video.y][state->m_video.x] = data;
	76	m_video.delayed = FALSE;
	77	if (m_video.x < ARRAY_LENGTH(m_video.pixels[0])) // continental galaxy flutlicht
	78	m_video.pixels[m_video.y][m_video.x] = data;
81	79	logerror("%.4x lcd x:%.2x y:%.2x %.4x written %.2x\n",
82		(int)cpu_get_reg(&space->device(), CPUINFO_INT_PC), state->m_video.x, state->m_video.y, 0x4000 + offset, data);
83		state->m_video.x++;
	80	(int)cpu_get_reg(&space.device(), CPUINFO_INT_PC), m_video.x, m_video.y, 0x4000 + offset, data);
	81	m_video.x++;
84	82	/* 02 b8 1a
85	83	02 bb 1a
86	84	02 bb 22
r14963	r14964
97	95	*/
98	96	break;
99	97	default:
100		logerror("%.4x memory %.4x written %.2x\n", (int)cpu_get_reg(&space->device(), CPUINFO_INT_PC), 0x4000 + offset, data);
	98	logerror("%.4x memory %.4x written %.2x\n", (int)cpu_get_reg(&space.device(), CPUINFO_INT_PC), 0x4000 + offset, data);
101	99	}
102	100	}
103	101	}
104	102
105		static READ8_HANDLER( gmaster_port_r )
	103	READ8_MEMBER(gmaster_state::gmaster_port_r)
106	104	{
107		//gmaster_state *state = space->machine().driver_data<gmaster_state>();
108		//  UINT8 data = state->m_gmachine.ports[offset];
	105	//  UINT8 data = m_gmachine.ports[offset];
109	106	UINT8 data = 0xff;
110	107	switch (offset)
111	108	{
112	109	case UPD7810_PORTA:
113		data = input_port_read(space->machine(), "JOY");
	110	data = input_port_read(machine(), "JOY");
114	111	break;
115	112	default:
116		logerror("%.4x port %d read %.2x\n", (int)cpu_get_reg(&space->device(), CPUINFO_INT_PC), offset, data);
	113	logerror("%.4x port %d read %.2x\n", (int)cpu_get_reg(&space.device(), CPUINFO_INT_PC), offset, data);
117	114	}
118	115	return data;
119	116	}
120	117
121		static WRITE8_HANDLER( gmaster_port_w )
	118	WRITE8_MEMBER(gmaster_state::gmaster_port_w)
122	119	{
123		gmaster_state *state = space->machine().driver_data<gmaster_state>();
124		state->m_gmachine.ports[offset] = data;
125		logerror("%.4x port %d written %.2x\n", (int)cpu_get_reg(&space->device(), CPUINFO_INT_PC), offset, data);
	120	m_gmachine.ports[offset] = data;
	121	logerror("%.4x port %d written %.2x\n", (int)cpu_get_reg(&space.device(), CPUINFO_INT_PC), offset, data);
126	122	switch (offset)
127	123	{
128	124	case UPD7810_PORTC:
129		state->m_video.y = BLITTER_Y;
	125	m_video.y = BLITTER_Y;
130	126	break;
131	127	}
132	128	}
133	129
134	130	static ADDRESS_MAP_START( gmaster_mem, AS_PROGRAM, 8, gmaster_state )
135	131	AM_RANGE(0x0000, 0x3fff) AM_ROM
136		AM_RANGE( 0x4000, 0x7fff) AM_READWRITE_LEGACY(gmaster_io_r, gmaster_io_w)
	132	AM_RANGE( 0x4000, 0x7fff) AM_READWRITE(gmaster_io_r, gmaster_io_w)
137	133	AM_RANGE(0x8000, 0xfeff) AM_ROM
138	134	AM_RANGE(0xff00, 0xffff) AM_RAM
139	135	ADDRESS_MAP_END
140	136
141	137	static ADDRESS_MAP_START(gmaster_io, AS_IO, 8, gmaster_state )
142		AM_RANGE(UPD7810_PORTA, UPD7810_PORTF) AM_READWRITE_LEGACY(gmaster_port_r, gmaster_port_w )
	138	AM_RANGE(UPD7810_PORTA, UPD7810_PORTF) AM_READWRITE(gmaster_port_r, gmaster_port_w )
143	139	ADDRESS_MAP_END
144	140
145	141	static INPUT_PORTS_START( gmaster )

src/mess/drivers/microtan.c

r14963	r14964
54	54
55	55	static ADDRESS_MAP_START( microtan_map, AS_PROGRAM, 8, microtan_state )
56	56	AM_RANGE(0x0000, 0x01ff) AM_RAM
57		AM_RANGE(0x0200, 0x03ff) AM_RAM_WRITE_LEGACY(microtan_videoram_w) AM_SHARE("videoram")
	57	AM_RANGE(0x0200, 0x03ff) AM_RAM_WRITE(microtan_videoram_w) AM_SHARE("videoram")
58	58	AM_RANGE(0xbc00, 0xbc00) AM_DEVWRITE_LEGACY("ay8910.1", ay8910_address_w)
59	59	AM_RANGE(0xbc01, 0xbc01) AM_DEVREADWRITE_LEGACY("ay8910.1", ay8910_r, ay8910_data_w)
60	60	AM_RANGE(0xbc02, 0xbc02) AM_DEVWRITE_LEGACY("ay8910.2", ay8910_address_w)
r14963	r14964
62	62	AM_RANGE(0xbfc0, 0xbfcf) AM_DEVREADWRITE("via6522_0", via6522_device, read, write)
63	63	AM_RANGE(0xbfd0, 0xbfd3) AM_DEVREADWRITE("acia", acia6551_device, read, write)
64	64	AM_RANGE(0xbfe0, 0xbfef) AM_DEVREADWRITE("via6522_1", via6522_device, read, write)
65		AM_RANGE(0xbff0, 0xbfff) AM_READWRITE_LEGACY(microtan_bffx_r, microtan_bffx_w)
	65	AM_RANGE(0xbff0, 0xbfff) AM_READWRITE(microtan_bffx_r, microtan_bffx_w)
66	66	AM_RANGE(0xc000, 0xe7ff) AM_ROM
67	67	AM_RANGE(0xf000, 0xffff) AM_ROM
68	68	ADDRESS_MAP_END

src/mess/drivers/sapi1.c

r14963	r14964
22	22
23	23
24	24	/* switch out the rom shadow */
25		static WRITE8_HANDLER( sapizps3_00_w )
	25	WRITE8_MEMBER(sapi1_state::sapizps3_00_w)
26	26	{
27		memory_set_bank(space->machine(), "bank1", 0);
	27	memory_set_bank(machine(), "bank1", 0);
28	28	}
29	29
30	30	/* to stop execution in random ram */
31		static READ8_HANDLER( sapizps3_25_r )
	31	READ8_MEMBER(sapi1_state::sapizps3_25_r)
32	32	{
33		sapi1_state *state = space->machine().driver_data<sapi1_state>();
34		return state->m_zps3_25;
	33	return m_zps3_25;
35	34	}
36	35
37		static WRITE8_HANDLER( sapizps3_25_w )
	36	WRITE8_MEMBER(sapi1_state::sapizps3_25_w)
38	37	{
39		sapi1_state *state = space->machine().driver_data<sapi1_state>();
40		state->m_zps3_25 = data & 0xfc; //??
	38	m_zps3_25 = data & 0xfc; //??
41	39	}
42	40
43	41
r14963	r14964
48	46	AM_RANGE(0x0000, 0x0fff) AM_ROM
49	47	AM_RANGE(0x1000, 0x1fff) AM_ROM // Extension ROM
50	48	AM_RANGE(0x2000, 0x23ff) AM_RAM
51		AM_RANGE(0x2400, 0x27ff) AM_READWRITE_LEGACY(sapi1_keyboard_r, sapi1_keyboard_w) // PORT 0 - keyboard
	49	AM_RANGE(0x2400, 0x27ff) AM_READWRITE(sapi1_keyboard_r, sapi1_keyboard_w) // PORT 0 - keyboard
52	50	//AM_RANGE(0x2800, 0x2bff) AM_NOP // PORT 1
53	51	//AM_RANGE(0x2c00, 0x2fff) AM_NOP // PORT 2
54	52	//AM_RANGE(0x3000, 0x33ff) AM_NOP // 3214
r14963	r14964
73	71	static ADDRESS_MAP_START( sapizps3_io, AS_IO, 8, sapi1_state )
74	72	ADDRESS_MAP_UNMAP_HIGH
75	73	ADDRESS_MAP_GLOBAL_MASK(0xff)
76		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(sapizps3_00_w)
77		AM_RANGE(0x25, 0x25) AM_READWRITE_LEGACY(sapizps3_25_r,sapizps3_25_w)
	74	AM_RANGE(0x00, 0x00) AM_WRITE(sapizps3_00_w)
	75	AM_RANGE(0x25, 0x25) AM_READWRITE(sapizps3_25_r,sapizps3_25_w)
78	76	ADDRESS_MAP_END
79	77
80	78	/* Input ports */

src/mess/drivers/einstein.c

r14963	r14964
90	90	* upper 8 bits define the offset in the row,
91	91	* data bits define data to write
92	92	*/
93		static WRITE8_HANDLER( einstein_80col_ram_w )
	93	WRITE8_MEMBER(einstein_state::einstein_80col_ram_w)
94	94	{
95		einstein_state *einstein = space->machine().driver_data<einstein_state>();
96		einstein->m_crtc_ram[((offset & 0x07) << 8) | ((offset >> 8) & 0xff)] = data;
	95	m_crtc_ram[((offset & 0x07) << 8) | ((offset >> 8) & 0xff)] = data;
97	96	}
98	97
99		static READ8_HANDLER( einstein_80col_ram_r )
	98	READ8_MEMBER(einstein_state::einstein_80col_ram_r)
100	99	{
101		einstein_state *einstein = space->machine().driver_data<einstein_state>();
102		return einstein->m_crtc_ram[((offset & 0x07) << 8) | ((offset >> 8) & 0xff)];
	100	return m_crtc_ram[((offset & 0x07) << 8) | ((offset >> 8) & 0xff)];
103	101	}
104	102
105	103	/* TODO: Verify implementation */
r14963	r14964
145	143	* bit 2 - Jumper M002 0 = 50Hz, 1 = 60Hz
146	144	* bit 3 - Jumper M001 0 = ???, 1=??? perminently wired high on both the boards I have seen - PHS.
147	145	*/
148		static READ8_HANDLER( einstein_80col_state_r )
	146	READ8_MEMBER(einstein_state::einstein_80col_state_r)
149	147	{
150		einstein_state *einstein = space->machine().driver_data<einstein_state>();
151	148	UINT8 result = 0;
152	149
153		result |= einstein->m_de;
154		result |= input_port_read(space->machine(), "80column_dips") & 0x06;
	150	result |= m_de;
	151	result |= input_port_read(machine(), "80column_dips") & 0x06;
155	152
156	153	return result;
157	154	}
r14963	r14964
212	209	}
213	210	}
214	211
215		static WRITE8_HANDLER( einstein_keyboard_line_write )
	212	WRITE8_MEMBER(einstein_state::einstein_keyboard_line_write)
216	213	{
217		einstein_state *einstein = space->machine().driver_data<einstein_state>();
218	214
219	215	if (VERBOSE_KEYBOARD)
220	216	logerror("einstein_keyboard_line_write: %02x\n", data);
221	217
222		einstein->m_keyboard_line = data;
	218	m_keyboard_line = data;
223	219
224	220	/* re-scan the keyboard */
225		einstein_scan_keyboard(space->machine());
	221	einstein_scan_keyboard(machine());
226	222	}
227	223
228		static READ8_HANDLER( einstein_keyboard_data_read )
	224	READ8_MEMBER(einstein_state::einstein_keyboard_data_read)
229	225	{
230		einstein_state *einstein = space->machine().driver_data<einstein_state>();
231	226
232	227	/* re-scan the keyboard */
233		einstein_scan_keyboard(space->machine());
	228	einstein_scan_keyboard(machine());
234	229
235	230	if (VERBOSE_KEYBOARD)
236		logerror("einstein_keyboard_data_read: %02x\n", einstein->m_keyboard_data);
	231	logerror("einstein_keyboard_data_read: %02x\n", m_keyboard_data);
237	232
238		return einstein->m_keyboard_data;
	233	return m_keyboard_data;
239	234	}
240	235
241	236
r14963	r14964
316	311	}
317	312
318	313	/* writing to this port is a simple trigger, and switches between RAM and ROM */
319		static WRITE8_HANDLER( einstein_rom_w )
	314	WRITE8_MEMBER(einstein_state::einstein_rom_w)
320	315	{
321		einstein_state *einstein = space->machine().driver_data<einstein_state>();
322		einstein->m_rom_enabled ^= 1;
323		einstein_page_rom(space->machine());
	316	m_rom_enabled ^= 1;
	317	einstein_page_rom(machine());
324	318	}
325	319
326	320
r14963	r14964
328	322	INTERRUPTS
329	323	***************************************************************************/
330	324
331		static READ8_HANDLER( einstein_kybintmsk_r )
	325	READ8_MEMBER(einstein_state::einstein_kybintmsk_r)
332	326	{
333		centronics_device *centronics = space->machine().device<centronics_device>("centronics");
334		einstein_state *einstein = space->machine().driver_data<einstein_state>();
	327	centronics_device *centronics = machine().device<centronics_device>("centronics");
335	328	UINT8 data = 0;
336	329
337	330	/* clear key int. a read of this I/O port will do this or a reset */
338		einstein->m_interrupt &= ~EINSTEIN_KEY_INT;
	331	m_interrupt &= ~EINSTEIN_KEY_INT;
339	332
340	333	/* bit 0 and 1: fire buttons on the joysticks */
341		data |= input_port_read(space->machine(), "BUTTONS");
	334	data |= input_port_read(machine(), "BUTTONS");
342	335
343	336	/* bit 2 to 4: printer status */
344	337	data |= centronics->busy_r() << 2;
r14963	r14964
346	339	data |= centronics->fault_r() << 4;
347	340
348	341	/* bit 5 to 7: graph, control and shift key */
349		data |= input_port_read(space->machine(), "EXTRA");
	342	data |= input_port_read(machine(), "EXTRA");
350	343
351	344	if(VERBOSE_KEYBOARD)
352		logerror("%s: einstein_kybintmsk_r %02x\n", space->machine().describe_context(), data);
	345	logerror("%s: einstein_kybintmsk_r %02x\n", machine().describe_context(), data);
353	346
354	347	return data;
355	348	}
356	349
357		static WRITE8_HANDLER( einstein_kybintmsk_w )
	350	WRITE8_MEMBER(einstein_state::einstein_kybintmsk_w)
358	351	{
359		einstein_state *einstein = space->machine().driver_data<einstein_state>();
360	352
361		logerror("%s: einstein_kybintmsk_w %02x\n", space->machine().describe_context(), data);
	353	logerror("%s: einstein_kybintmsk_w %02x\n", machine().describe_context(), data);
362	354
363	355	/* set mask from bit 0 */
364	356	if (data & 0x01)
365	357	{
366	358	logerror("key int is disabled\n");
367		einstein->m_interrupt_mask &= ~EINSTEIN_KEY_INT;
	359	m_interrupt_mask &= ~EINSTEIN_KEY_INT;
368	360	}
369	361	else
370	362	{
371	363	logerror("key int is enabled\n");
372		einstein->m_interrupt_mask |= EINSTEIN_KEY_INT;
	364	m_interrupt_mask |= EINSTEIN_KEY_INT;
373	365	}
374	366	}
375	367
376	368	/* writing to this I/O port sets the state of the mask; D0 is used */
377	369	/* writing 0 enables the /ADC interrupt */
378		static WRITE8_HANDLER( einstein_adcintmsk_w )
	370	WRITE8_MEMBER(einstein_state::einstein_adcintmsk_w)
379	371	{
380		einstein_state *einstein = space->machine().driver_data<einstein_state>();
381	372
382		logerror("%s: einstein_adcintmsk_w %02x\n", space->machine().describe_context(), data);
	373	logerror("%s: einstein_adcintmsk_w %02x\n", machine().describe_context(), data);
383	374
384	375	if (data & 0x01)
385	376	{
386	377	logerror("adc int is disabled\n");
387		einstein->m_interrupt_mask &= ~EINSTEIN_ADC_INT;
	378	m_interrupt_mask &= ~EINSTEIN_ADC_INT;
388	379	}
389	380	else
390	381	{
391	382	logerror("adc int is enabled\n");
392		einstein->m_interrupt_mask |= EINSTEIN_ADC_INT;
	383	m_interrupt_mask |= EINSTEIN_ADC_INT;
393	384	}
394	385	}
395	386
396	387	/* writing to this I/O port sets the state of the mask; D0 is used */
397	388	/* writing 0 enables the /FIRE interrupt */
398		static WRITE8_HANDLER( einstein_fire_int_w )
	389	WRITE8_MEMBER(einstein_state::einstein_fire_int_w)
399	390	{
400		einstein_state *einstein = space->machine().driver_data<einstein_state>();
401	391
402		logerror("%s: einstein_fire_int_w %02x\n", space->machine().describe_context(), data);
	392	logerror("%s: einstein_fire_int_w %02x\n", machine().describe_context(), data);
403	393
404	394	if (data & 0x01)
405	395	{
406	396	logerror("fire int is disabled\n");
407		einstein->m_interrupt_mask &= ~EINSTEIN_FIRE_INT;
	397	m_interrupt_mask &= ~EINSTEIN_FIRE_INT;
408	398	}
409	399	else
410	400	{
411	401	logerror("fire int is enabled\n");
412		einstein->m_interrupt_mask |= EINSTEIN_FIRE_INT;
	402	m_interrupt_mask |= EINSTEIN_FIRE_INT;
413	403	}
414	404	}
415	405
r14963	r14964
538	528	/* block 3, wd1770 floppy controller */
539	529	AM_RANGE(0x18, 0x1b) AM_MIRROR(0xff04) AM_DEVREADWRITE(IC_I042, wd177x_t, read, write)
540	530	/* block 4, internal controls */
541		AM_RANGE(0x20, 0x20) AM_MIRROR(0xff00) AM_READWRITE_LEGACY(einstein_kybintmsk_r, einstein_kybintmsk_w)
542		AM_RANGE(0x21, 0x21) AM_MIRROR(0xff00) AM_WRITE_LEGACY(einstein_adcintmsk_w)
	531	AM_RANGE(0x20, 0x20) AM_MIRROR(0xff00) AM_READWRITE(einstein_kybintmsk_r, einstein_kybintmsk_w)
	532	AM_RANGE(0x21, 0x21) AM_MIRROR(0xff00) AM_WRITE(einstein_adcintmsk_w)
543	533	AM_RANGE(0x23, 0x23) AM_MIRROR(0xff00) AM_DEVWRITE_LEGACY(IC_I042, einstein_drsel_w)
544		AM_RANGE(0x24, 0x24) AM_MIRROR(0xff00) AM_WRITE_LEGACY(einstein_rom_w)
545		AM_RANGE(0x25, 0x25) AM_MIRROR(0xff00) AM_WRITE_LEGACY(einstein_fire_int_w)
	534	AM_RANGE(0x24, 0x24) AM_MIRROR(0xff00) AM_WRITE(einstein_rom_w)
	535	AM_RANGE(0x25, 0x25) AM_MIRROR(0xff00) AM_WRITE(einstein_fire_int_w)
546	536	/* block 5, z80ctc */
547	537	AM_RANGE(0x28, 0x2b) AM_MIRROR(0xff04) AM_DEVREADWRITE_LEGACY(IC_I058, z80ctc_r, z80ctc_w)
548	538	/* block 6, z80pio */
r14963	r14964
555	545
556	546	static ADDRESS_MAP_START( einstein2_io, AS_IO, 8, einstein_state )
557	547	AM_IMPORT_FROM(einstein_io)
558		AM_RANGE(0x40, 0x47) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE_LEGACY(einstein_80col_ram_r, einstein_80col_ram_w)
	548	AM_RANGE(0x40, 0x47) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE(einstein_80col_ram_r, einstein_80col_ram_w)
559	549	AM_RANGE(0x48, 0x48) AM_MIRROR(0xff00) AM_DEVWRITE("crtc", mc6845_device, address_w)
560	550	AM_RANGE(0x49, 0x49) AM_MIRROR(0xff00) AM_DEVWRITE("crtc", mc6845_device, register_w)
561		AM_RANGE(0x4c, 0x4c) AM_MIRROR(0xff00) AM_READ_LEGACY(einstein_80col_state_r)
	551	AM_RANGE(0x4c, 0x4c) AM_MIRROR(0xff00) AM_READ(einstein_80col_state_r)
562	552	ADDRESS_MAP_END
563	553
564	554
r14963	r14964
734	724	AY8910_LEGACY_OUTPUT,
735	725	AY8910_DEFAULT_LOADS,
736	726	DEVCB_NULL,
737		DEVCB_MEMORY_HANDLER(IC_I001, PROGRAM, einstein_keyboard_data_read),
738		DEVCB_MEMORY_HANDLER(IC_I001, PROGRAM, einstein_keyboard_line_write),
	727	DEVCB_DRIVER_MEMBER(einstein_state, einstein_keyboard_data_read),
	728	DEVCB_DRIVER_MEMBER(einstein_state, einstein_keyboard_line_write),
739	729	DEVCB_NULL
740	730	};
741	731

src/mess/drivers/ti99_2.c

r14963	r14964
95	95	int m_KeyRow;
96	96	DECLARE_WRITE8_MEMBER(ti99_2_write_kbd);
97	97	DECLARE_WRITE8_MEMBER(ti99_2_write_misc_cru);
	98	DECLARE_READ8_MEMBER(ti99_2_read_kbd);
	99	DECLARE_READ8_MEMBER(ti99_2_read_misc_cru);
98	100	};
99	101
100	102
r14963	r14964
267	269	}
268	270
269	271	/* read keys in the current row */
270		static  READ8_HANDLER ( ti99_2_read_kbd )
	272	READ8_MEMBER(ti99_2_state::ti99_2_read_kbd)
271	273	{
272		ti99_2_state *state = space->machine().driver_data<ti99_2_state>();
273	274	static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7" };
274	275
275		return input_port_read(space->machine(), keynames[state->m_KeyRow]);
	276	return input_port_read(machine(), keynames[m_KeyRow]);
276	277	}
277	278
278		static  READ8_HANDLER ( ti99_2_read_misc_cru )
	279	READ8_MEMBER(ti99_2_state::ti99_2_read_misc_cru)
279	280	{
280	281	return 0;
281	282	}
282	283
283	284	static ADDRESS_MAP_START(ti99_2_io, AS_IO, 8, ti99_2_state )
284		AM_RANGE(0x0E00, 0x0E7f) AM_READ_LEGACY(ti99_2_read_kbd)
285		AM_RANGE(0x0E80, 0x0Eff) AM_READ_LEGACY(ti99_2_read_misc_cru)
	285	AM_RANGE(0x0E00, 0x0E7f) AM_READ(ti99_2_read_kbd)
	286	AM_RANGE(0x0E80, 0x0Eff) AM_READ(ti99_2_read_misc_cru)
286	287	AM_RANGE(0x7000, 0x73ff) AM_WRITE(ti99_2_write_kbd)
287	288	AM_RANGE(0x7400, 0x77ff) AM_WRITE(ti99_2_write_misc_cru)
288	289	ADDRESS_MAP_END

src/mess/drivers/amstrad.c

r14963	r14964
179	179	are not fully decoded by the CPC h/w. Doing it this way means
180	180	I can decode it myself and a lot of  software should work */
181	181	static ADDRESS_MAP_START(amstrad_io, AS_IO, 8, amstrad_state )
182		AM_RANGE(0x0000, 0xffff) AM_READWRITE_LEGACY(amstrad_cpc_io_r, amstrad_cpc_io_w )
	182	AM_RANGE(0x0000, 0xffff) AM_READWRITE(amstrad_cpc_io_r, amstrad_cpc_io_w )
183	183	ADDRESS_MAP_END
184	184
185	185
r14963	r14964
773	773	{
774	774	AY8910_LEGACY_OUTPUT,
775	775	AY8910_DEFAULT_LOADS,
776		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, amstrad_psg_porta_read),   /* portA read */
777		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, amstrad_psg_porta_read),   /* portB read */
	776	DEVCB_DRIVER_MEMBER(amstrad_state, amstrad_psg_porta_read),   /* portA read */
	777	DEVCB_DRIVER_MEMBER(amstrad_state, amstrad_psg_porta_read),   /* portB read */
778	778	DEVCB_NULL,               /* portA write */
779	779	DEVCB_NULL               /* portB write */
780	780	};

src/mess/drivers/ng_aes.c

r14963	r14964
61	61
62	62	UINT8 *m_memcard_data;
63	63	neocd_ctrl_t m_neocd_ctrl;
	64	DECLARE_WRITE8_MEMBER(audio_cpu_clear_nmi_w);
	65	DECLARE_WRITE16_MEMBER(io_control_w);
	66	DECLARE_WRITE16_MEMBER(save_ram_w);
	67	DECLARE_READ16_MEMBER(memcard_r);
	68	DECLARE_WRITE16_MEMBER(memcard_w);
	69	DECLARE_READ16_MEMBER(neocd_memcard_r);
	70	DECLARE_WRITE16_MEMBER(neocd_memcard_w);
	71	DECLARE_WRITE16_MEMBER(audio_command_w);
	72	DECLARE_READ8_MEMBER(audio_command_r);
	73	DECLARE_WRITE8_MEMBER(audio_result_w);
	74	DECLARE_WRITE16_MEMBER(main_cpu_bank_select_w);
	75	DECLARE_READ8_MEMBER(audio_cpu_bank_select_f000_f7ff_r);
	76	DECLARE_READ8_MEMBER(audio_cpu_bank_select_e000_efff_r);
	77	DECLARE_READ8_MEMBER(audio_cpu_bank_select_c000_dfff_r);
	78	DECLARE_READ8_MEMBER(audio_cpu_bank_select_8000_bfff_r);
	79	DECLARE_WRITE16_MEMBER(system_control_w);
	80	DECLARE_READ16_MEMBER(neocd_control_r);
	81	DECLARE_WRITE16_MEMBER(neocd_control_w);
	82	DECLARE_READ16_MEMBER(neocd_transfer_r);
	83	DECLARE_WRITE16_MEMBER(neocd_transfer_w);
	84	DECLARE_READ16_MEMBER(aes_in0_r);
	85	DECLARE_READ16_MEMBER(aes_in1_r);
	86	DECLARE_READ16_MEMBER(aes_in2_r);
64	87	};
65	88
66	89
r14963	r14964
232	255	}
233	256
234	257
235		static WRITE8_HANDLER( audio_cpu_clear_nmi_w )
	258	WRITE8_MEMBER(ng_aes_state::audio_cpu_clear_nmi_w)
236	259	{
237		neogeo_state *state = space->machine().driver_data<neogeo_state>();
238		device_set_input_line(state->m_audiocpu, INPUT_LINE_NMI, CLEAR_LINE);
	260	device_set_input_line(m_audiocpu, INPUT_LINE_NMI, CLEAR_LINE);
239	261	}
240	262
241	263
r14963	r14964
293	315
294	316	#endif
295	317
296		static WRITE16_HANDLER( io_control_w )
	318	WRITE16_MEMBER(ng_aes_state::io_control_w)
297	319	{
298		neogeo_state *state = space->machine().driver_data<neogeo_state>();
299	320	switch (offset)
300	321	{
301		case 0x00: select_controller(space->machine(), data & 0x00ff); break;
302		//  case 0x18: set_output_latch(space->machine(), data & 0x00ff); break;
303		//  case 0x20: set_output_data(space->machine(), data & 0x00ff); break;
304		case 0x28: upd4990a_control_16_w(state->m_upd4990a, 0, data, mem_mask); break;
	322	case 0x00: select_controller(machine(), data & 0x00ff); break;
	323	//  case 0x18: set_output_latch(machine(), data & 0x00ff); break;
	324	//  case 0x20: set_output_data(machine(), data & 0x00ff); break;
	325	case 0x28: upd4990a_control_16_w(m_upd4990a, 0, data, mem_mask); break;
305	326	//  case 0x30: break; // coin counters
306	327	//  case 0x31: break; // coin counters
307	328	//  case 0x32: break; // coin lockout
308	329	//  case 0x33: break; // coui lockout
309	330
310	331	default:
311		logerror("PC: %x  Unmapped I/O control write.  Offset: %x  Data: %x\n", cpu_get_pc(&space->device()), offset, data);
	332	logerror("PC: %x  Unmapped I/O control write.  Offset: %x  Data: %x\n", cpu_get_pc(&space.device()), offset, data);
312	333	break;
313	334	}
314	335	}
r14963	r14964
384	405	}
385	406
386	407
387		static WRITE16_HANDLER( save_ram_w )
	408	WRITE16_MEMBER(ng_aes_state::save_ram_w)
388	409	{
389		neogeo_state *state = space->machine().driver_data<neogeo_state>();
390	410
391		if (state->m_save_ram_unlocked)
	411	if (m_save_ram_unlocked)
392	412	COMBINE_DATA(&save_ram[offset]);
393	413	}
394	414	#endif
r14963	r14964
412	432	return (memcard_present(field.machine()) == -1) ? 0x07 : 0x00;
413	433	}
414	434
415		static READ16_HANDLER( memcard_r )
	435	READ16_MEMBER(ng_aes_state::memcard_r)
416	436	{
417		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
418	437	UINT16 ret;
419	438
420		if (memcard_present(space->machine()) != -1)
421		ret = state->m_memcard_data[offset] | 0xff00;
	439	if (memcard_present(machine()) != -1)
	440	ret = m_memcard_data[offset] | 0xff00;
422	441	else
423	442	ret = 0xffff;
424	443
r14963	r14964
426	445	}
427	446
428	447
429		static WRITE16_HANDLER( memcard_w )
	448	WRITE16_MEMBER(ng_aes_state::memcard_w)
430	449	{
431		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
432	450	if (ACCESSING_BITS_0_7)
433	451	{
434		if (memcard_present(space->machine()) != -1)
435		state->m_memcard_data[offset] = data;
	452	if (memcard_present(machine()) != -1)
	453	m_memcard_data[offset] = data;
436	454	}
437	455	}
438	456
439	457	/* The NeoCD has an 8kB internal memory card, instead of memcard slots like the MVS and AES */
440		static READ16_HANDLER( neocd_memcard_r )
	458	READ16_MEMBER(ng_aes_state::neocd_memcard_r)
441	459	{
442		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
443		return state->m_memcard_data[offset] | 0xff00;
	460	return m_memcard_data[offset] | 0xff00;
444	461	}
445	462
446	463
447		static WRITE16_HANDLER( neocd_memcard_w )
	464	WRITE16_MEMBER(ng_aes_state::neocd_memcard_w)
448	465	{
449		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
450	466	if (ACCESSING_BITS_0_7)
451	467	{
452		state->m_memcard_data[offset] = data;
	468	m_memcard_data[offset] = data;
453	469	}
454	470	}
455	471
r14963	r14964
481	497	*
482	498	*************************************/
483	499
484		static WRITE16_HANDLER( audio_command_w )
	500	WRITE16_MEMBER(ng_aes_state::audio_command_w)
485	501	{
486		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
487	502	/* accessing the LSB only is not mapped */
488	503	if (mem_mask != 0x00ff)
489	504	{
490		state->soundlatch_byte_w(*space, 0, data >> 8);
	505	soundlatch_byte_w(space, 0, data >> 8);
491	506
492		audio_cpu_assert_nmi(space->machine());
	507	audio_cpu_assert_nmi(machine());
493	508
494	509	/* boost the interleave to let the audio CPU read the command */
495		space->machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(50));
	510	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(50));
496	511
497		if (LOG_CPU_COMM) logerror("MAIN CPU PC %06x: audio_command_w %04x - %04x\n", cpu_get_pc(&space->device()), data, mem_mask);
	512	if (LOG_CPU_COMM) logerror("MAIN CPU PC %06x: audio_command_w %04x - %04x\n", cpu_get_pc(&space.device()), data, mem_mask);
498	513	}
499	514	}
500	515
501	516
502		static READ8_HANDLER( audio_command_r )
	517	READ8_MEMBER(ng_aes_state::audio_command_r)
503	518	{
504		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
505		UINT8 ret = state->soundlatch_byte_r(*space, 0);
	519	UINT8 ret = soundlatch_byte_r(space, 0);
506	520
507		if (LOG_CPU_COMM) logerror(" AUD CPU PC   %04x: audio_command_r %02x\n", cpu_get_pc(&space->device()), ret);
	521	if (LOG_CPU_COMM) logerror(" AUD CPU PC   %04x: audio_command_r %02x\n", cpu_get_pc(&space.device()), ret);
508	522
509	523	/* this is a guess */
510	524	audio_cpu_clear_nmi_w(space, 0, 0);
r14963	r14964
513	527	}
514	528
515	529
516		static WRITE8_HANDLER( audio_result_w )
	530	WRITE8_MEMBER(ng_aes_state::audio_result_w)
517	531	{
518		neogeo_state *state = space->machine().driver_data<neogeo_state>();
519	532
520		if (LOG_CPU_COMM && (state->m_audio_result != data)) logerror(" AUD CPU PC   %04x: audio_result_w %02x\n", cpu_get_pc(&space->device()), data);
	533	if (LOG_CPU_COMM && (m_audio_result != data)) logerror(" AUD CPU PC   %04x: audio_result_w %02x\n", cpu_get_pc(&space.device()), data);
521	534
522		state->m_audio_result = data;
	535	m_audio_result = data;
523	536	}
524	537
525	538
r14963	r14964
565	578
566	579
567	580
568		static WRITE16_HANDLER( main_cpu_bank_select_w )
	581	WRITE16_MEMBER(ng_aes_state::main_cpu_bank_select_w)
569	582	{
570	583	UINT32 bank_address;
571		UINT32 len = space->machine().region("maincpu")->bytes();
	584	UINT32 len = machine().region("maincpu")->bytes();
572	585
573	586	if ((len <= 0x100000) && (data & 0x07))
574		logerror("PC %06x: warning: bankswitch to %02x but no banks available\n", cpu_get_pc(&space->device()), data);
	587	logerror("PC %06x: warning: bankswitch to %02x but no banks available\n", cpu_get_pc(&space.device()), data);
575	588	else
576	589	{
577	590	bank_address = ((data & 0x07) + 1) * 0x100000;
578	591
579	592	if (bank_address >= len)
580	593	{
581		logerror("PC %06x: warning: bankswitch to empty bank %02x\n", cpu_get_pc(&space->device()), data);
	594	logerror("PC %06x: warning: bankswitch to empty bank %02x\n", cpu_get_pc(&space.device()), data);
582	595	bank_address = 0x100000;
583	596	}
584	597
585		neogeo_set_main_cpu_bank_address(space, bank_address);
	598	neogeo_set_main_cpu_bank_address(&space, bank_address);
586	599	}
587	600	}
588	601
r14963	r14964
632	645	}
633	646
634	647
635		static READ8_HANDLER( audio_cpu_bank_select_f000_f7ff_r )
	648	READ8_MEMBER(ng_aes_state::audio_cpu_bank_select_f000_f7ff_r)
636	649	{
637		audio_cpu_bank_select(space, 0, offset >> 8);
	650	audio_cpu_bank_select(&space, 0, offset >> 8);
638	651
639	652	return 0;
640	653	}
641	654
642	655
643		static READ8_HANDLER( audio_cpu_bank_select_e000_efff_r )
	656	READ8_MEMBER(ng_aes_state::audio_cpu_bank_select_e000_efff_r)
644	657	{
645		audio_cpu_bank_select(space, 1, offset >> 8);
	658	audio_cpu_bank_select(&space, 1, offset >> 8);
646	659
647	660	return 0;
648	661	}
649	662
650	663
651		static READ8_HANDLER( audio_cpu_bank_select_c000_dfff_r )
	664	READ8_MEMBER(ng_aes_state::audio_cpu_bank_select_c000_dfff_r)
652	665	{
653		audio_cpu_bank_select(space, 2, offset >> 8);
	666	audio_cpu_bank_select(&space, 2, offset >> 8);
654	667
655	668	return 0;
656	669	}
657	670
658	671
659		static READ8_HANDLER( audio_cpu_bank_select_8000_bfff_r )
	672	READ8_MEMBER(ng_aes_state::audio_cpu_bank_select_8000_bfff_r)
660	673	{
661		audio_cpu_bank_select(space, 3, offset >> 8);
	674	audio_cpu_bank_select(&space, 3, offset >> 8);
662	675
663	676	return 0;
664	677	}
r14963	r14964
741	754	*
742	755	*************************************/
743	756
744		static WRITE16_HANDLER( system_control_w )
	757	WRITE16_MEMBER(ng_aes_state::system_control_w)
745	758	{
746	759	if (ACCESSING_BITS_0_7)
747	760	{
r14963	r14964
750	763	switch (offset & 0x07)
751	764	{
752	765	default:
753		case 0x00: neogeo_set_screen_dark(space->machine(), bit); break;
754		case 0x01: set_main_cpu_vector_table_source(space->machine(), bit);
755		set_audio_cpu_rom_source(space, bit); /* this is a guess */
	766	case 0x00: neogeo_set_screen_dark(machine(), bit); break;
	767	case 0x01: set_main_cpu_vector_table_source(machine(), bit);
	768	set_audio_cpu_rom_source(&space, bit); /* this is a guess */
756	769	break;
757		case 0x05: neogeo_set_fixed_layer_source(space->machine(), bit); break;
758		//      case 0x06: set_save_ram_unlock(space->machine(), bit); break;
759		case 0x07: neogeo_set_palette_bank(space->machine(), bit); break;
	770	case 0x05: neogeo_set_fixed_layer_source(machine(), bit); break;
	771	//      case 0x06: set_save_ram_unlock(machine(), bit); break;
	772	case 0x07: neogeo_set_palette_bank(machine(), bit); break;
760	773
761	774	case 0x02: /* unknown - HC32 middle pin 1 */
762	775	case 0x03: /* unknown - uPD4990 pin ? */
763	776	case 0x04: /* unknown - HC32 middle pin 10 */
764		logerror("PC: %x  Unmapped system control write.  Offset: %x  Data: %x\n", cpu_get_pc(&space->device()), offset & 0x07, bit);
	777	logerror("PC: %x  Unmapped system control write.  Offset: %x  Data: %x\n", cpu_get_pc(&space.device()), offset & 0x07, bit);
765	778	break;
766	779	}
767	780
768		if (LOG_VIDEO_SYSTEM && ((offset & 0x07) != 0x06)) logerror("PC: %x  System control write.  Offset: %x  Data: %x\n", cpu_get_pc(&space->device()), offset & 0x07, bit);
	781	if (LOG_VIDEO_SYSTEM && ((offset & 0x07) != 0x06)) logerror("PC: %x  System control write.  Offset: %x  Data: %x\n", cpu_get_pc(&space.device()), offset & 0x07, bit);
769	782	}
770	783	}
771	784
r14963	r14964
856	869	}
857	870	}
858	871
859		static READ16_HANDLER( neocd_control_r )
	872	READ16_MEMBER(ng_aes_state::neocd_control_r)
860	873	{
861		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
862	874
863	875	switch(offset)
864	876	{
865	877	case 0x64/2: // source address, high word
866		return (state->m_neocd_ctrl.addr_source >> 16) & 0xffff;
	878	return (m_neocd_ctrl.addr_source >> 16) & 0xffff;
867	879	case 0x66/2: // source address, low word
868		return state->m_neocd_ctrl.addr_source & 0xffff;
	880	return m_neocd_ctrl.addr_source & 0xffff;
869	881	case 0x68/2: // target address, high word
870		return (state->m_neocd_ctrl.addr_target >> 16) & 0xffff;
	882	return (m_neocd_ctrl.addr_target >> 16) & 0xffff;
871	883	case 0x6a/2: // target address, low word
872		return state->m_neocd_ctrl.addr_target & 0xffff;
	884	return m_neocd_ctrl.addr_target & 0xffff;
873	885	case 0x6c/2: // fill word
874		return state->m_neocd_ctrl.fill_word;
	886	return m_neocd_ctrl.fill_word;
875	887	case 0x70/2: // word count
876		return (state->m_neocd_ctrl.word_count >> 16) & 0xffff;
	888	return (m_neocd_ctrl.word_count >> 16) & 0xffff;
877	889	case 0x72/2:
878		return state->m_neocd_ctrl.word_count & 0xffff;
	890	return m_neocd_ctrl.word_count & 0xffff;
879	891	case 0x7e/2:  // DMA parameters
880	892	case 0x80/2:
881	893	case 0x82/2:
r14963	r14964
885	897	case 0x8a/2:
886	898	case 0x8c/2:
887	899	case 0x8e/2:
888		return state->m_neocd_ctrl.dma_mode[offset-(0x7e/2)];
	900	return m_neocd_ctrl.dma_mode[offset-(0x7e/2)];
889	901	break;
890	902	case 0x105/2:
891		return state->m_neocd_ctrl.area_sel;
	903	return m_neocd_ctrl.area_sel;
892	904	case 0x11c/2:
893	905	logerror("CTRL: Read region code.\n");
894	906	return 0x0600;  // we'll just force USA region for now
895	907	case 0x1a0/2:
896		return state->m_neocd_ctrl.spr_bank_sel;
	908	return m_neocd_ctrl.spr_bank_sel;
897	909	break;
898	910	case 0x1a2/2:
899		return state->m_neocd_ctrl.pcm_bank_sel;
	911	return m_neocd_ctrl.pcm_bank_sel;
900	912	break;
901	913	default:
902	914	logerror("CTRL: Read offset %04x\n",offset);
r14963	r14964
905	917	return 0;
906	918	}
907	919
908		static WRITE16_HANDLER( neocd_control_w )
	920	WRITE16_MEMBER(ng_aes_state::neocd_control_w)
909	921	{
910		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
911	922	switch(offset)
912	923	{
913	924	case 0x60/2: // Start DMA transfer
914	925	if((data & 0xff) == 0x40)
915		neocd_do_dma(space);
	926	neocd_do_dma(&space);
916	927	break;
917	928	case 0x64/2: // source address, high word
918		state->m_neocd_ctrl.addr_source = (state->m_neocd_ctrl.addr_source & 0x0000ffff) | (data << 16);
919		logerror("CTRL: Set source address to %08x\n",state->m_neocd_ctrl.addr_source);
	929	m_neocd_ctrl.addr_source = (m_neocd_ctrl.addr_source & 0x0000ffff) | (data << 16);
	930	logerror("CTRL: Set source address to %08x\n",m_neocd_ctrl.addr_source);
920	931	break;
921	932	case 0x66/2: // source address, low word
922		state->m_neocd_ctrl.addr_source = (state->m_neocd_ctrl.addr_source & 0xffff0000) | data;
923		logerror("CTRL: Set source address to %08x\n",state->m_neocd_ctrl.addr_source);
	933	m_neocd_ctrl.addr_source = (m_neocd_ctrl.addr_source & 0xffff0000) | data;
	934	logerror("CTRL: Set source address to %08x\n",m_neocd_ctrl.addr_source);
924	935	break;
925	936	case 0x68/2: // target address, high word
926		state->m_neocd_ctrl.addr_target = (state->m_neocd_ctrl.addr_target & 0x0000ffff) | (data << 16);
927		logerror("CTRL: Set target address to %08x\n",state->m_neocd_ctrl.addr_target);
	937	m_neocd_ctrl.addr_target = (m_neocd_ctrl.addr_target & 0x0000ffff) | (data << 16);
	938	logerror("CTRL: Set target address to %08x\n",m_neocd_ctrl.addr_target);
928	939	break;
929	940	case 0x6a/2: // target address, low word
930		state->m_neocd_ctrl.addr_target = (state->m_neocd_ctrl.addr_target & 0xffff0000) | data;
931		logerror("CTRL: Set target address to %08x\n",state->m_neocd_ctrl.addr_target);
	941	m_neocd_ctrl.addr_target = (m_neocd_ctrl.addr_target & 0xffff0000) | data;
	942	logerror("CTRL: Set target address to %08x\n",m_neocd_ctrl.addr_target);
932	943	break;
933	944	case 0x6c/2: // fill word
934		state->m_neocd_ctrl.fill_word = data;
	945	m_neocd_ctrl.fill_word = data;
935	946	logerror("CTRL: Set fill word to %04x\n",data);
936	947	break;
937	948	case 0x70/2: // word count
938		state->m_neocd_ctrl.word_count = (state->m_neocd_ctrl.word_count & 0x0000ffff) | (data << 16);
939		logerror("CTRL: Set word count to %i\n",state->m_neocd_ctrl.word_count);
	949	m_neocd_ctrl.word_count = (m_neocd_ctrl.word_count & 0x0000ffff) | (data << 16);
	950	logerror("CTRL: Set word count to %i\n",m_neocd_ctrl.word_count);
940	951	break;
941	952	case 0x72/2: // word count (low word)
942		state->m_neocd_ctrl.word_count = (state->m_neocd_ctrl.word_count & 0xffff0000) | data;
943		logerror("CTRL: Set word count to %i\n",state->m_neocd_ctrl.word_count);
	953	m_neocd_ctrl.word_count = (m_neocd_ctrl.word_count & 0xffff0000) | data;
	954	logerror("CTRL: Set word count to %i\n",m_neocd_ctrl.word_count);
944	955	break;
945	956	case 0x7e/2:  // DMA parameters
946	957	case 0x80/2:
r14963	r14964
951	962	case 0x8a/2:
952	963	case 0x8c/2:
953	964	case 0x8e/2:
954		state->m_neocd_ctrl.dma_mode[offset-(0x7e/2)] = data;
	965	m_neocd_ctrl.dma_mode[offset-(0x7e/2)] = data;
955	966	logerror("CTRL: DMA parameter %i set to %04x\n",offset-(0x7e/2),data);
956	967	break;
957	968	case 0x104/2:
958		state->m_neocd_ctrl.area_sel = data & 0x00ff;
	969	m_neocd_ctrl.area_sel = data & 0x00ff;
959	970	logerror("CTRL: 0xExxxxx set to area %i\n",data & 0xff);
960	971	break;
961	972	case 0x140/2:  // end sprite transfer
962		video_reset_neogeo(space->machine());
	973	video_reset_neogeo(machine());
963	974	break;
964	975	case 0x142/2:  // end PCM transfer
965	976	break;
966	977	case 0x146/2:  // end Z80 transfer
967		cputag_set_input_line(space->machine(),"audiocpu",INPUT_LINE_RESET,PULSE_LINE);
	978	cputag_set_input_line(machine(),"audiocpu",INPUT_LINE_RESET,PULSE_LINE);
968	979	break;
969	980	case 0x148/2:  // end FIX transfer
970		video_reset_neogeo(space->machine());
	981	video_reset_neogeo(machine());
971	982	break;
972	983	case 0x1a0/2:
973		state->m_neocd_ctrl.spr_bank_sel = data & 0xff;
	984	m_neocd_ctrl.spr_bank_sel = data & 0xff;
974	985	logerror("CTRL: Sprite area set to bank %i\n",data & 0xff);
975	986	break;
976	987	case 0x1a2/2:
977		state->m_neocd_ctrl.pcm_bank_sel = data & 0xff;
	988	m_neocd_ctrl.pcm_bank_sel = data & 0xff;
978	989	logerror("CTRL: PCM area set to bank %i\n",data & 0xff);
979	990	break;
980	991	default:
r14963	r14964
987	998	*  When the Z80 space is banked in to 0xe00000, only the low byte of each word is used
988	999	*/
989	1000
990		static READ16_HANDLER(neocd_transfer_r)
	1001	READ16_MEMBER(ng_aes_state::neocd_transfer_r)
991	1002	{
992		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
993	1003	UINT16 ret = 0x0000;
994		UINT8* Z80 = space->machine().region("audiocpu")->base();
995		UINT8* PCM = space->machine().region("ymsnd")->base();
996		UINT8* FIX = space->machine().region("fixed")->base();
997		UINT16* SPR = (UINT16*)(*space->machine().region("sprites"));
	1004	UINT8* Z80 = machine().region("audiocpu")->base();
	1005	UINT8* PCM = machine().region("ymsnd")->base();
	1006	UINT8* FIX = machine().region("fixed")->base();
	1007	UINT16* SPR = (UINT16*)(*machine().region("sprites"));
998	1008
999		switch(state->m_neocd_ctrl.area_sel)
	1009	switch(m_neocd_ctrl.area_sel)
1000	1010	{
1001	1011	case NEOCD_AREA_AUDIO:
1002	1012	ret = Z80[offset & 0xffff] | 0xff00;
1003	1013	break;
1004	1014	case NEOCD_AREA_PCM:
1005		ret = PCM[offset + (0x100000*state->m_neocd_ctrl.pcm_bank_sel)] | 0xff00;
	1015	ret = PCM[offset + (0x100000*m_neocd_ctrl.pcm_bank_sel)] | 0xff00;
1006	1016	break;
1007	1017	case NEOCD_AREA_SPR:
1008		ret = SPR[offset + (0x80000*state->m_neocd_ctrl.spr_bank_sel)];
	1018	ret = SPR[offset + (0x80000*m_neocd_ctrl.spr_bank_sel)];
1009	1019	break;
1010	1020	case NEOCD_AREA_FIX:
1011	1021	ret = FIX[offset & 0x1ffff] | 0xff00;
r14963	r14964
1015	1025	return ret;
1016	1026	}
1017	1027
1018		static WRITE16_HANDLER(neocd_transfer_w)
	1028	WRITE16_MEMBER(ng_aes_state::neocd_transfer_w)
1019	1029	{
1020		ng_aes_state *state = space->machine().driver_data<ng_aes_state>();
1021		UINT8* Z80 = space->machine().region("audiocpu")->base();
1022		UINT8* PCM = space->machine().region("ymsnd")->base();
1023		UINT8* FIX = space->machine().region("fixed")->base();
1024		UINT16* SPR = (UINT16*)(*space->machine().region("sprites"));
	1030	UINT8* Z80 = machine().region("audiocpu")->base();
	1031	UINT8* PCM = machine().region("ymsnd")->base();
	1032	UINT8* FIX = machine().region("fixed")->base();
	1033	UINT16* SPR = (UINT16*)(*machine().region("sprites"));
1025	1034
1026		switch(state->m_neocd_ctrl.area_sel)
	1035	switch(m_neocd_ctrl.area_sel)
1027	1036	{
1028	1037	case NEOCD_AREA_AUDIO:
1029	1038	Z80[offset & 0xffff] = data & 0xff;
1030	1039	break;
1031	1040	case NEOCD_AREA_PCM:
1032		PCM[offset + (0x100000*state->m_neocd_ctrl.pcm_bank_sel)] = data & 0xff;
	1041	PCM[offset + (0x100000*m_neocd_ctrl.pcm_bank_sel)] = data & 0xff;
1033	1042	break;
1034	1043	case NEOCD_AREA_SPR:
1035		COMBINE_DATA(SPR+(offset + (0x80000*state->m_neocd_ctrl.spr_bank_sel)));
	1044	COMBINE_DATA(SPR+(offset + (0x80000*m_neocd_ctrl.spr_bank_sel)));
1036	1045	break;
1037	1046	case NEOCD_AREA_FIX:
1038	1047	FIX[offset & 0x1ffff] = data & 0xff;
r14963	r14964
1045	1054	* Handling selectable controller types
1046	1055	*/
1047	1056
1048		static READ16_HANDLER( aes_in0_r )
	1057	READ16_MEMBER(ng_aes_state::aes_in0_r)
1049	1058	{
1050		neogeo_state *state = space->machine().driver_data<neogeo_state>();
1051	1059	UINT32 ret = 0xffff;
1052		UINT32 ctrl = input_port_read(space->machine(),"CTRLSEL");
	1060	UINT32 ctrl = input_port_read(machine(),"CTRLSEL");
1053	1061
1054	1062	switch(ctrl & 0x0f)
1055	1063	{
r14963	r14964
1057	1065	ret = 0xffff;
1058	1066	break;
1059	1067	case 0x01:
1060		ret = input_port_read(space->machine(),"IN0");
	1068	ret = input_port_read(machine(),"IN0");
1061	1069	break;
1062	1070	case 0x02:
1063		switch (state->m_controller_select)
	1071	switch (m_controller_select)
1064	1072	{
1065		case 0x09: ret = input_port_read(space->machine(), "MJ01_P1"); break;
1066		case 0x12: ret = input_port_read(space->machine(), "MJ02_P1"); break;
1067		case 0x1b: ret = input_port_read(space->machine(), "MJ03_P1"); break; /* player 1 normal inputs? */
1068		case 0x24: ret = input_port_read(space->machine(), "MJ04_P1"); break;
	1073	case 0x09: ret = input_port_read(machine(), "MJ01_P1"); break;
	1074	case 0x12: ret = input_port_read(machine(), "MJ02_P1"); break;
	1075	case 0x1b: ret = input_port_read(machine(), "MJ03_P1"); break; /* player 1 normal inputs? */
	1076	case 0x24: ret = input_port_read(machine(), "MJ04_P1"); break;
1069	1077	default:
1070		ret = input_port_read(space->machine(),"IN0");
	1078	ret = input_port_read(machine(),"IN0");
1071	1079	break;
1072	1080	}
1073	1081	break;
r14963	r14964
1076	1084	return ret;
1077	1085	}
1078	1086
1079		static READ16_HANDLER( aes_in1_r )
	1087	READ16_MEMBER(ng_aes_state::aes_in1_r)
1080	1088	{
1081		neogeo_state *state = space->machine().driver_data<neogeo_state>();
1082	1089	UINT32 ret = 0xffff;
1083		UINT32 ctrl = input_port_read(space->machine(),"CTRLSEL");
	1090	UINT32 ctrl = input_port_read(machine(),"CTRLSEL");
1084	1091
1085	1092	switch(ctrl & 0xf0)
1086	1093	{
r14963	r14964
1088	1095	ret = 0xffff;
1089	1096	break;
1090	1097	case 0x10:
1091		ret = input_port_read(space->machine(),"IN1");
	1098	ret = input_port_read(machine(),"IN1");
1092	1099	break;
1093	1100	case 0x20:
1094		switch (state->m_controller_select)
	1101	switch (m_controller_select)
1095	1102	{
1096		case 0x09: ret = input_port_read(space->machine(), "MJ01_P2"); break;
1097		case 0x12: ret = input_port_read(space->machine(), "MJ02_P2"); break;
1098		case 0x1b: ret = input_port_read(space->machine(), "MJ03_P2"); break; /* player 2 normal inputs? */
1099		case 0x24: ret = input_port_read(space->machine(), "MJ04_P2"); break;
	1103	case 0x09: ret = input_port_read(machine(), "MJ01_P2"); break;
	1104	case 0x12: ret = input_port_read(machine(), "MJ02_P2"); break;
	1105	case 0x1b: ret = input_port_read(machine(), "MJ03_P2"); break; /* player 2 normal inputs? */
	1106	case 0x24: ret = input_port_read(machine(), "MJ04_P2"); break;
1100	1107	default:
1101		ret = input_port_read(space->machine(),"IN1");
	1108	ret = input_port_read(machine(),"IN1");
1102	1109	break;
1103	1110	}
1104	1111	break;
r14963	r14964
1108	1115	}
1109	1116
1110	1117
1111		static READ16_HANDLER(aes_in2_r)
	1118	READ16_MEMBER(ng_aes_state::aes_in2_r)
1112	1119	{
1113		UINT32 in2 = input_port_read(space->machine(),"IN2");
	1120	UINT32 in2 = input_port_read(machine(),"IN2");
1114	1121	UINT32 ret = in2;
1115		UINT32 sel = input_port_read(space->machine(),"CTRLSEL");
1116		neogeo_state *state = space->machine().driver_data<neogeo_state>();
	1122	UINT32 sel = input_port_read(machine(),"CTRLSEL");
1117	1123
1118		if((sel & 0x02) && (state->m_controller_select == 0x24))
	1124	if((sel & 0x02) && (m_controller_select == 0x24))
1119	1125	ret ^= 0x0200;
1120	1126
1121		if((sel & 0x20) && (state->m_controller_select == 0x24))
	1127	if((sel & 0x20) && (m_controller_select == 0x24))
1122	1128	ret ^= 0x0800;
1123	1129
1124	1130	return ret;
r14963	r14964
1248	1254
1249	1255	/* reset system control registers */
1250	1256	for (offs = 0; offs < 8; offs++)
1251		system_control_w(space, offs, 0, 0x00ff);
	1257	state->system_control_w(*space, offs, 0, 0x00ff);
1252	1258
1253	1259	machine.device("maincpu")->reset();
1254	1260
r14963	r14964
1279	1285	AM_RANGE(0x100000, 0x10ffff) AM_MIRROR(0x0f0000) AM_RAM
1280	1286	/* some games have protection devices in the 0x200000 region, it appears to map to cart space, not surprising, the ROM is read here too */
1281	1287	AM_RANGE(0x200000, 0x2fffff) AM_ROMBANK(NEOGEO_BANK_CARTRIDGE)
1282		AM_RANGE(0x2ffff0, 0x2fffff) AM_WRITE_LEGACY(main_cpu_bank_select_w)
1283		AM_RANGE(0x300000, 0x300001) AM_MIRROR(0x01ff7e) AM_READ_LEGACY(aes_in0_r)
	1288	AM_RANGE(0x2ffff0, 0x2fffff) AM_WRITE(main_cpu_bank_select_w)
	1289	AM_RANGE(0x300000, 0x300001) AM_MIRROR(0x01ff7e) AM_READ(aes_in0_r)
1284	1290	AM_RANGE(0x300080, 0x300081) AM_MIRROR(0x01ff7e) AM_READ_PORT("IN4")
1285	1291	AM_RANGE(0x300000, 0x300001) AM_MIRROR(0x01ffe0) AM_READ(neogeo_unmapped_r) AM_WRITENOP   // AES has no watchdog
1286		AM_RANGE(0x320000, 0x320001) AM_MIRROR(0x01fffe) AM_READ_PORT("IN3") AM_WRITE_LEGACY(audio_command_w)
1287		AM_RANGE(0x340000, 0x340001) AM_MIRROR(0x01fffe) AM_READ_LEGACY(aes_in1_r)
	1292	AM_RANGE(0x320000, 0x320001) AM_MIRROR(0x01fffe) AM_READ_PORT("IN3") AM_WRITE(audio_command_w)
	1293	AM_RANGE(0x340000, 0x340001) AM_MIRROR(0x01fffe) AM_READ(aes_in1_r)
1288	1294	AM_RANGE(0x360000, 0x37ffff) AM_READ(neogeo_unmapped_r)
1289		AM_RANGE(0x380000, 0x380001) AM_MIRROR(0x01fffe) AM_READ_LEGACY(aes_in2_r)
1290		AM_RANGE(0x380000, 0x38007f) AM_MIRROR(0x01ff80) AM_WRITE_LEGACY(io_control_w)
1291		AM_RANGE(0x3a0000, 0x3a001f) AM_MIRROR(0x01ffe0) AM_READ(neogeo_unmapped_r) AM_WRITE_LEGACY(system_control_w)
	1295	AM_RANGE(0x380000, 0x380001) AM_MIRROR(0x01fffe) AM_READ(aes_in2_r)
	1296	AM_RANGE(0x380000, 0x38007f) AM_MIRROR(0x01ff80) AM_WRITE(io_control_w)
	1297	AM_RANGE(0x3a0000, 0x3a001f) AM_MIRROR(0x01ffe0) AM_READ(neogeo_unmapped_r) AM_WRITE(system_control_w)
1292	1298	AM_RANGE(0x3c0000, 0x3c0007) AM_MIRROR(0x01fff8) AM_READ(neogeo_video_register_r)
1293	1299	AM_RANGE(0x3c0000, 0x3c000f) AM_MIRROR(0x01fff0) AM_WRITE(neogeo_video_register_w)
1294	1300	AM_RANGE(0x3e0000, 0x3fffff) AM_READ(neogeo_unmapped_r)
1295	1301	AM_RANGE(0x400000, 0x401fff) AM_MIRROR(0x3fe000) AM_READWRITE(neogeo_paletteram_r, neogeo_paletteram_w)
1296		AM_RANGE(0x800000, 0x800fff) AM_READWRITE_LEGACY(memcard_r, memcard_w)
	1302	AM_RANGE(0x800000, 0x800fff) AM_READWRITE(memcard_r, memcard_w)
1297	1303	AM_RANGE(0xc00000, 0xc1ffff) AM_MIRROR(0x0e0000) AM_ROMBANK(NEOGEO_BANK_BIOS)
1298		AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE_LEGACY(save_ram_w) AM_BASE_LEGACY(&save_ram)
	1304	AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_BASE_LEGACY(&save_ram)
1299	1305	AM_RANGE(0xe00000, 0xffffff) AM_READ(neogeo_unmapped_r)
1300	1306	ADDRESS_MAP_END
1301	1307
r14963	r14964
1305	1311	AM_RANGE(0x100000, 0x10ffff) AM_MIRROR(0x0f0000) AM_RAM AM_BASE_LEGACY(&neocd_work_ram)
1306	1312	/* some games have protection devices in the 0x200000 region, it appears to map to cart space, not surprising, the ROM is read here too */
1307	1313	AM_RANGE(0x200000, 0x2fffff) AM_ROMBANK(NEOGEO_BANK_CARTRIDGE)
1308		AM_RANGE(0x2ffff0, 0x2fffff) AM_WRITE_LEGACY(main_cpu_bank_select_w)
1309		AM_RANGE(0x300000, 0x300001) AM_MIRROR(0x01ff7e) AM_READ_LEGACY(aes_in0_r)
	1314	AM_RANGE(0x2ffff0, 0x2fffff) AM_WRITE(main_cpu_bank_select_w)
	1315	AM_RANGE(0x300000, 0x300001) AM_MIRROR(0x01ff7e) AM_READ(aes_in0_r)
1310	1316	AM_RANGE(0x300080, 0x300081) AM_MIRROR(0x01ff7e) AM_READ_PORT("IN4")
1311	1317	AM_RANGE(0x300000, 0x300001) AM_MIRROR(0x01ffe0) AM_READ(neogeo_unmapped_r) AM_WRITENOP   // AES has no watchdog
1312		AM_RANGE(0x320000, 0x320001) AM_MIRROR(0x01fffe) AM_READ_PORT("IN3") AM_WRITE_LEGACY(audio_command_w)
1313		AM_RANGE(0x340000, 0x340001) AM_MIRROR(0x01fffe) AM_READ_LEGACY(aes_in1_r)
	1318	AM_RANGE(0x320000, 0x320001) AM_MIRROR(0x01fffe) AM_READ_PORT("IN3") AM_WRITE(audio_command_w)
	1319	AM_RANGE(0x340000, 0x340001) AM_MIRROR(0x01fffe) AM_READ(aes_in1_r)
1314	1320	AM_RANGE(0x360000, 0x37ffff) AM_READ(neogeo_unmapped_r)
1315		AM_RANGE(0x380000, 0x380001) AM_MIRROR(0x01fffe) AM_READ_LEGACY(aes_in2_r)
1316		AM_RANGE(0x380000, 0x38007f) AM_MIRROR(0x01ff80) AM_WRITE_LEGACY(io_control_w)
1317		AM_RANGE(0x3a0000, 0x3a001f) AM_MIRROR(0x01ffe0) AM_READ(neogeo_unmapped_r) AM_WRITE_LEGACY(system_control_w)
	1321	AM_RANGE(0x380000, 0x380001) AM_MIRROR(0x01fffe) AM_READ(aes_in2_r)
	1322	AM_RANGE(0x380000, 0x38007f) AM_MIRROR(0x01ff80) AM_WRITE(io_control_w)
	1323	AM_RANGE(0x3a0000, 0x3a001f) AM_MIRROR(0x01ffe0) AM_READ(neogeo_unmapped_r) AM_WRITE(system_control_w)
1318	1324	AM_RANGE(0x3c0000, 0x3c0007) AM_MIRROR(0x01fff8) AM_READ(neogeo_video_register_r)
1319	1325	AM_RANGE(0x3c0000, 0x3c000f) AM_MIRROR(0x01fff0) AM_WRITE(neogeo_video_register_w)
1320	1326	AM_RANGE(0x3e0000, 0x3fffff) AM_READ(neogeo_unmapped_r)
1321	1327	AM_RANGE(0x400000, 0x401fff) AM_MIRROR(0x3fe000) AM_READWRITE(neogeo_paletteram_r, neogeo_paletteram_w)
1322		AM_RANGE(0x800000, 0x803fff) AM_READWRITE_LEGACY(neocd_memcard_r, neocd_memcard_w)
	1328	AM_RANGE(0x800000, 0x803fff) AM_READWRITE(neocd_memcard_r, neocd_memcard_w)
1323	1329	AM_RANGE(0xc00000, 0xcfffff) AM_ROMBANK(NEOGEO_BANK_BIOS)
1324		AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE_LEGACY(save_ram_w) AM_BASE_LEGACY(&save_ram)
1325		AM_RANGE(0xe00000, 0xefffff) AM_READWRITE_LEGACY(neocd_transfer_r,neocd_transfer_w)
	1330	AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_BASE_LEGACY(&save_ram)
	1331	AM_RANGE(0xe00000, 0xefffff) AM_READWRITE(neocd_transfer_r,neocd_transfer_w)
1326	1332	AM_RANGE(0xf00000, 0xfeffff) AM_READ(neogeo_unmapped_r)
1327		AM_RANGE(0xff0000, 0xff01ff) AM_READWRITE_LEGACY(neocd_control_r, neocd_control_w) // CDROM / DMA
	1333	AM_RANGE(0xff0000, 0xff01ff) AM_READWRITE(neocd_control_r, neocd_control_w) // CDROM / DMA
1328	1334	AM_RANGE(0xff0200, 0xffffff) AM_READ(neogeo_unmapped_r)
1329	1335	ADDRESS_MAP_END
1330	1336
r14963	r14964
1353	1359	*************************************/
1354	1360
1355	1361	static ADDRESS_MAP_START( audio_io_map, AS_IO, 8, ng_aes_state )
1356		/*AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READWRITE_LEGACY(audio_command_r, audio_cpu_clear_nmi_w);*/  /* may not and NMI clear */
1357		AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READ_LEGACY(audio_command_r)
	1362	/*AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READWRITE(audio_command_r, audio_cpu_clear_nmi_w);*/  /* may not and NMI clear */
	1363	AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READ(audio_command_r)
1358	1364	AM_RANGE(0x04, 0x07) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY("ymsnd", ym2610_r, ym2610_w)
1359	1365	AM_RANGE(0x08, 0x08) AM_MIRROR(0xff00) /* write - NMI enable / acknowledge? (the data written doesn't matter) */
1360		AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ_LEGACY(audio_cpu_bank_select_f000_f7ff_r)
1361		AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ_LEGACY(audio_cpu_bank_select_e000_efff_r)
1362		AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ_LEGACY(audio_cpu_bank_select_c000_dfff_r)
1363		AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ_LEGACY(audio_cpu_bank_select_8000_bfff_r)
1364		AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff00) AM_WRITE_LEGACY(audio_result_w)
	1366	AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_f000_f7ff_r)
	1367	AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_e000_efff_r)
	1368	AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_c000_dfff_r)
	1369	AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_8000_bfff_r)
	1370	AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff00) AM_WRITE(audio_result_w)
1365	1371	AM_RANGE(0x18, 0x18) AM_MIRROR(0xff00) /* write - NMI disable? (the data written doesn't matter) */
1366	1372	ADDRESS_MAP_END
1367	1373

src/mess/drivers/sms.c

r14963	r14964
79	79	AM_RANGE(0x2000, 0x3fff) AM_ROMBANK("bank7")               /* switchable rom bank */
80	80	AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank3")               /* switchable rom bank */
81	81	AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank4")               /* switchable rom bank */
82		AM_RANGE(0x8000, 0x9fff) AM_READ_BANK("bank5") AM_WRITE_LEGACY(sms_cartram_w)   /* ROM bank / on-cart RAM */
83		AM_RANGE(0xa000, 0xbfff) AM_READ_BANK("bank6") AM_WRITE_LEGACY(sms_cartram2_w)   /* ROM bank / on-cart RAM */
	82	AM_RANGE(0x8000, 0x9fff) AM_READ_BANK("bank5") AM_WRITE(sms_cartram_w)   /* ROM bank / on-cart RAM */
	83	AM_RANGE(0xa000, 0xbfff) AM_READ_BANK("bank6") AM_WRITE(sms_cartram2_w)   /* ROM bank / on-cart RAM */
84	84	AM_RANGE(0xc000, 0xdff7) AM_MIRROR(0x2000) AM_RAM         /* RAM (mirror at 0xE000) */
85	85	AM_RANGE(0xdff8, 0xdfff) AM_RAM                  /* RAM "underneath" frame registers */
86		AM_RANGE(0xfff8, 0xfffb) AM_READWRITE_LEGACY(sms_sscope_r, sms_sscope_w)   /* 3-D glasses */
87		AM_RANGE(0xfffc, 0xffff) AM_READWRITE_LEGACY(sms_mapper_r, sms_mapper_w)   /* Bankswitch control */
	86	AM_RANGE(0xfff8, 0xfffb) AM_READWRITE(sms_sscope_r, sms_sscope_w)   /* 3-D glasses */
	87	AM_RANGE(0xfffc, 0xffff) AM_READWRITE(sms_mapper_r, sms_mapper_w)   /* Bankswitch control */
88	88	ADDRESS_MAP_END
89	89
90	90	static ADDRESS_MAP_START( sms_mem, AS_PROGRAM, 8, sms_state )
r14963	r14964
93	93	AM_RANGE(0x2000, 0x3fff) AM_ROMBANK("bank7")               /* switchable rom bank */
94	94	AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank3")               /* switchable rom bank */
95	95	AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank4")               /* switchable rom bank */
96		AM_RANGE(0x8000, 0x9fff) AM_READ_BANK("bank5") AM_WRITE_LEGACY(sms_cartram_w)   /* ROM bank / on-cart RAM */
97		AM_RANGE(0xa000, 0xbfff) AM_READ_BANK("bank6") AM_WRITE_LEGACY(sms_cartram2_w)   /* ROM bank / on-cart RAM */
	96	AM_RANGE(0x8000, 0x9fff) AM_READ_BANK("bank5") AM_WRITE(sms_cartram_w)   /* ROM bank / on-cart RAM */
	97	AM_RANGE(0xa000, 0xbfff) AM_READ_BANK("bank6") AM_WRITE(sms_cartram2_w)   /* ROM bank / on-cart RAM */
98	98	AM_RANGE(0xc000, 0xdffb) AM_MIRROR(0x2000) AM_RAM         /* RAM (mirror at 0xE000) */
99	99	AM_RANGE(0xdffc, 0xdfff) AM_RAM                  /* RAM "underneath" frame registers */
100		AM_RANGE(0xfffc, 0xffff) AM_READWRITE_LEGACY(sms_mapper_r, sms_mapper_w)   /* Bankswitch control */
	100	AM_RANGE(0xfffc, 0xffff) AM_READWRITE(sms_mapper_r, sms_mapper_w)   /* Bankswitch control */
101	101	ADDRESS_MAP_END
102	102
103	103	static ADDRESS_MAP_START( sms_store_mem, AS_PROGRAM, 8, sms_state )
104	104	AM_RANGE(0x0000, 0x3fff) AM_ROM                  /* BIOS */
105	105	AM_RANGE(0x4000, 0x47ff) AM_RAM                  /* RAM */
106	106	AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank10")               /* Cartridge/card peek area */
107		AM_RANGE(0x8000, 0x8000) AM_READWRITE_LEGACY(sms_store_control_r, sms_store_control_w)   /* Control */
108		AM_RANGE(0xc000, 0xc000) AM_READWRITE_LEGACY(sms_store_cart_select_r, sms_store_cart_select_w)   /* cartridge/card slot selector */
109		AM_RANGE(0xd800, 0xd800) AM_READ_LEGACY(sms_store_select1)         /* Game selector port #1 */
110		AM_RANGE(0xdc00, 0xdc00) AM_READ_LEGACY(sms_store_select2)         /* Game selector port #2 */
	107	AM_RANGE(0x8000, 0x8000) AM_READWRITE(sms_store_control_r, sms_store_control_w)   /* Control */
	108	AM_RANGE(0xc000, 0xc000) AM_READWRITE(sms_store_cart_select_r, sms_store_cart_select_w)   /* cartridge/card slot selector */
	109	AM_RANGE(0xd800, 0xd800) AM_READ(sms_store_select1)         /* Game selector port #1 */
	110	AM_RANGE(0xdc00, 0xdc00) AM_READ(sms_store_select2)         /* Game selector port #2 */
111	111	ADDRESS_MAP_END
112	112
113	113	static ADDRESS_MAP_START( sms_io, AS_IO, 8, sms_state )
114	114	ADDRESS_MAP_GLOBAL_MASK(0xff)
115	115	ADDRESS_MAP_UNMAP_HIGH
116		AM_RANGE(0x00, 0x00) AM_MIRROR(0x3e) AM_WRITE_LEGACY(sms_bios_w)
117		AM_RANGE(0x01, 0x01) AM_MIRROR(0x3e) AM_WRITE_LEGACY(sms_io_control_w)
118		AM_RANGE(0x40, 0x7f)                 AM_READ_LEGACY(sms_count_r)
	116	AM_RANGE(0x00, 0x00) AM_MIRROR(0x3e) AM_WRITE(sms_bios_w)
	117	AM_RANGE(0x01, 0x01) AM_MIRROR(0x3e) AM_WRITE(sms_io_control_w)
	118	AM_RANGE(0x40, 0x7f)                 AM_READ(sms_count_r)
119	119	AM_RANGE(0x40, 0x7f)                 AM_DEVWRITE_LEGACY("segapsg", sn76496_w)
120	120	AM_RANGE(0x80, 0x80) AM_MIRROR(0x3e) AM_DEVREADWRITE("sms_vdp", sega315_5124_device, vram_read, vram_write)
121	121	AM_RANGE(0x81, 0x81) AM_MIRROR(0x3e) AM_DEVREADWRITE("sms_vdp", sega315_5124_device, register_read, register_write)
122		AM_RANGE(0xc0, 0xc0) AM_MIRROR(0x1e) AM_READ_LEGACY(sms_input_port_0_r)
123		AM_RANGE(0xc1, 0xc1) AM_MIRROR(0x1e) AM_READ_LEGACY(sms_input_port_1_r)
124		AM_RANGE(0xe0, 0xe0) AM_MIRROR(0x0e) AM_READ_LEGACY(sms_input_port_0_r)
125		AM_RANGE(0xe1, 0xe1) AM_MIRROR(0x0e) AM_READ_LEGACY(sms_input_port_1_r)
126		AM_RANGE(0xf0, 0xf0)                 AM_READWRITE_LEGACY(sms_input_port_0_r, sms_ym2413_register_port_0_w)
127		AM_RANGE(0xf1, 0xf1)                 AM_READWRITE_LEGACY(sms_input_port_1_r, sms_ym2413_data_port_0_w)
128		AM_RANGE(0xf2, 0xf2)                 AM_READWRITE_LEGACY(sms_fm_detect_r, sms_fm_detect_w)
129		AM_RANGE(0xf3, 0xf3)                 AM_READ_LEGACY(sms_input_port_1_r)
130		AM_RANGE(0xf4, 0xf4) AM_MIRROR(0x02) AM_READ_LEGACY(sms_input_port_0_r)
131		AM_RANGE(0xf5, 0xf5) AM_MIRROR(0x02) AM_READ_LEGACY(sms_input_port_1_r)
132		AM_RANGE(0xf8, 0xf8) AM_MIRROR(0x06) AM_READ_LEGACY(sms_input_port_0_r)
133		AM_RANGE(0xf9, 0xf9) AM_MIRROR(0x06) AM_READ_LEGACY(sms_input_port_1_r)
	122	AM_RANGE(0xc0, 0xc0) AM_MIRROR(0x1e) AM_READ(sms_input_port_0_r)
	123	AM_RANGE(0xc1, 0xc1) AM_MIRROR(0x1e) AM_READ(sms_input_port_1_r)
	124	AM_RANGE(0xe0, 0xe0) AM_MIRROR(0x0e) AM_READ(sms_input_port_0_r)
	125	AM_RANGE(0xe1, 0xe1) AM_MIRROR(0x0e) AM_READ(sms_input_port_1_r)
	126	AM_RANGE(0xf0, 0xf0)                 AM_READWRITE(sms_input_port_0_r, sms_ym2413_register_port_0_w)
	127	AM_RANGE(0xf1, 0xf1)                 AM_READWRITE(sms_input_port_1_r, sms_ym2413_data_port_0_w)
	128	AM_RANGE(0xf2, 0xf2)                 AM_READWRITE(sms_fm_detect_r, sms_fm_detect_w)
	129	AM_RANGE(0xf3, 0xf3)                 AM_READ(sms_input_port_1_r)
	130	AM_RANGE(0xf4, 0xf4) AM_MIRROR(0x02) AM_READ(sms_input_port_0_r)
	131	AM_RANGE(0xf5, 0xf5) AM_MIRROR(0x02) AM_READ(sms_input_port_1_r)
	132	AM_RANGE(0xf8, 0xf8) AM_MIRROR(0x06) AM_READ(sms_input_port_0_r)
	133	AM_RANGE(0xf9, 0xf9) AM_MIRROR(0x06) AM_READ(sms_input_port_1_r)
134	134	ADDRESS_MAP_END
135	135
136	136	static ADDRESS_MAP_START( gg_io, AS_IO, 8, sms_state )
137	137	ADDRESS_MAP_GLOBAL_MASK(0xff)
138	138	ADDRESS_MAP_UNMAP_HIGH
139		AM_RANGE(0x00, 0x00)                 AM_READ_LEGACY(gg_input_port_2_r)
140		AM_RANGE(0x01, 0x05)                 AM_READWRITE_LEGACY(gg_sio_r, gg_sio_w)
	139	AM_RANGE(0x00, 0x00)                 AM_READ(gg_input_port_2_r)
	140	AM_RANGE(0x01, 0x05)                 AM_READWRITE(gg_sio_r, gg_sio_w)
141	141	AM_RANGE(0x06, 0x06)                 AM_DEVWRITE_LEGACY("gamegear", sn76496_stereo_w)
142		AM_RANGE(0x07, 0x07)                 AM_WRITE_LEGACY(sms_io_control_w)
143		AM_RANGE(0x08, 0x08) AM_MIRROR(0x06) AM_WRITE_LEGACY(sms_bios_w)
144		AM_RANGE(0x09, 0x09) AM_MIRROR(0x06) AM_WRITE_LEGACY(sms_io_control_w)
145		AM_RANGE(0x10, 0x10) AM_MIRROR(0x0e) AM_WRITE_LEGACY(sms_bios_w)
146		AM_RANGE(0x11, 0x11) AM_MIRROR(0x0e) AM_WRITE_LEGACY(sms_io_control_w)
147		AM_RANGE(0x20, 0x20) AM_MIRROR(0x1e) AM_WRITE_LEGACY(sms_bios_w)
148		AM_RANGE(0x21, 0x21) AM_MIRROR(0x1e) AM_WRITE_LEGACY(sms_io_control_w)
149		AM_RANGE(0x40, 0x7f)                 AM_READ_LEGACY(sms_count_r)
	142	AM_RANGE(0x07, 0x07)                 AM_WRITE(sms_io_control_w)
	143	AM_RANGE(0x08, 0x08) AM_MIRROR(0x06) AM_WRITE(sms_bios_w)
	144	AM_RANGE(0x09, 0x09) AM_MIRROR(0x06) AM_WRITE(sms_io_control_w)
	145	AM_RANGE(0x10, 0x10) AM_MIRROR(0x0e) AM_WRITE(sms_bios_w)
	146	AM_RANGE(0x11, 0x11) AM_MIRROR(0x0e) AM_WRITE(sms_io_control_w)
	147	AM_RANGE(0x20, 0x20) AM_MIRROR(0x1e) AM_WRITE(sms_bios_w)
	148	AM_RANGE(0x21, 0x21) AM_MIRROR(0x1e) AM_WRITE(sms_io_control_w)
	149	AM_RANGE(0x40, 0x7f)                 AM_READ(sms_count_r)
150	150	AM_RANGE(0x40, 0x7f)                 AM_DEVWRITE_LEGACY("gamegear", sn76496_w)
151	151	AM_RANGE(0x80, 0x80) AM_MIRROR(0x3e) AM_DEVREADWRITE("sms_vdp", sega315_5124_device, vram_read, vram_write)
152	152	AM_RANGE(0x81, 0x81) AM_MIRROR(0x3e) AM_DEVREADWRITE("sms_vdp", sega315_5124_device, register_read, register_write)

src/mess/drivers/poly88.c

r14963	r14964
28	28	ADDRESS_MAP_GLOBAL_MASK(0xff)
29	29	AM_RANGE(0x00, 0x00) AM_DEVREADWRITE("uart", i8251_device, data_r, data_w)
30	30	AM_RANGE(0x01, 0x01) AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)
31		AM_RANGE(0x04, 0x04) AM_WRITE_LEGACY(poly88_baud_rate_w)
32		AM_RANGE(0x08, 0x08) AM_WRITE_LEGACY(poly88_intr_w)
33		AM_RANGE(0xf8, 0xf8) AM_READ_LEGACY(poly88_keyboard_r)
	31	AM_RANGE(0x04, 0x04) AM_WRITE(poly88_baud_rate_w)
	32	AM_RANGE(0x08, 0x08) AM_WRITE(poly88_intr_w)
	33	AM_RANGE(0xf8, 0xf8) AM_READ(poly88_keyboard_r)
34	34	ADDRESS_MAP_END
35	35
36	36	static ADDRESS_MAP_START(poly8813_mem, AS_PROGRAM, 8, poly88_state )

src/mess/drivers/psx.c

r14963	r14964
49	49	UINT8 m_cd_io_status;
50	50	UINT8 m_cd_param[8];
51	51	UINT8 m_cd_result[8];
	52	DECLARE_READ8_MEMBER(psx_cd_r);
	53	DECLARE_WRITE8_MEMBER(psx_cd_w);
52	54	};
53	55
54	56
r14963	r14964
670	672	printf("cd_dma_write?!: addr %x, size %x\n", n_address, n_size);
671	673	}
672	674
673		static READ8_HANDLER( psx_cd_r )
	675	READ8_MEMBER(psx1_state::psx_cd_r)
674	676	{
675		psxcd_device *psxcd = space->machine().device<psxcd_device>(PSXCD_TAG);
	677	psxcd_device *psxcd = machine().device<psxcd_device>(PSXCD_TAG);
676	678
677	679	return psxcd->read_byte(offset);
678	680	}
679	681
680		static WRITE8_HANDLER( psx_cd_w )
	682	WRITE8_MEMBER(psx1_state::psx_cd_w)
681	683	{
682		psxcd_device *psxcd = space->machine().device<psxcd_device>(PSXCD_TAG);
	684	psxcd_device *psxcd = machine().device<psxcd_device>(PSXCD_TAG);
683	685
684	686	psxcd->write_byte(offset, data);
685	687	}
686	688
687	689	static ADDRESS_MAP_START( psx_map, AS_PROGRAM, 32, psx1_state )
688	690	AM_RANGE(0x00000000, 0x001fffff) AM_RAM   AM_SHARE("share1") /* ram */
689		AM_RANGE(0x1f801800, 0x1f801803) AM_READWRITE8_LEGACY(psx_cd_r, psx_cd_w, 0xffffffff)
	691	AM_RANGE(0x1f801800, 0x1f801803) AM_READWRITE8(psx_cd_r, psx_cd_w, 0xffffffff)
690	692	AM_RANGE(0x1fc00000, 0x1fc7ffff) AM_ROM AM_SHARE("share2") AM_REGION("user1", 0) /* bios */
691	693	AM_RANGE(0x80000000, 0x801fffff) AM_RAM AM_SHARE("share1") /* ram mirror */
692	694	AM_RANGE(0x80600000, 0x807fffff) AM_RAM AM_SHARE("share1") /* ram mirror */

src/mess/drivers/llc.c

r14963	r14964
42	42	static ADDRESS_MAP_START( llc2_io, AS_IO, 8, llc_state )
43	43	ADDRESS_MAP_GLOBAL_MASK(0xff)
44	44	ADDRESS_MAP_UNMAP_HIGH
45		AM_RANGE(0xE0, 0xE3) AM_WRITE_LEGACY(llc2_rom_disable_w)
	45	AM_RANGE(0xE0, 0xE3) AM_WRITE(llc2_rom_disable_w)
46	46	AM_RANGE(0xE8, 0xEB) AM_DEVREADWRITE_LEGACY("z80pio", z80pio_cd_ba_r, z80pio_cd_ba_w)
47		AM_RANGE(0xEC, 0xEC) AM_WRITE_LEGACY(llc2_basic_enable_w)
	47	AM_RANGE(0xEC, 0xEC) AM_WRITE(llc2_basic_enable_w)
48	48	AM_RANGE(0xF8, 0xFB) AM_DEVREADWRITE_LEGACY("z80ctc", z80ctc_r, z80ctc_w)
49	49	ADDRESS_MAP_END
50	50

src/mess/drivers/samcoupe.c

r14963	r14964
60	60	I/O PORTS
61	61	***************************************************************************/
62	62
63		static READ8_HANDLER( samcoupe_disk_r )
	63	READ8_MEMBER(samcoupe_state::samcoupe_disk_r)
64	64	{
65		wd1772_t *fdc = space->machine().device<wd1772_t>("wd1772");
	65	wd1772_t *fdc = machine().device<wd1772_t>("wd1772");
66	66
67	67	/* drive and side is encoded into bit 5 and 3 */
68		floppy_connector *con = space->machine().device<floppy_connector>(BIT(offset, 4) ? "fd1" : "fd0");
	68	floppy_connector *con = machine().device<floppy_connector>(BIT(offset, 4) ? "fd1" : "fd0");
69	69	floppy_image_device *floppy = con ? con->get_device() : 0;
70	70
71	71	if(floppy)
r14963	r14964
84	84	return 0xff;
85	85	}
86	86
87		static WRITE8_HANDLER( samcoupe_disk_w )
	87	WRITE8_MEMBER(samcoupe_state::samcoupe_disk_w)
88	88	{
89		wd1772_t *fdc = space->machine().device<wd1772_t>("wd1772");
	89	wd1772_t *fdc = machine().device<wd1772_t>("wd1772");
90	90
91	91	/* drive and side is encoded into bit 5 and 3 */
92		floppy_connector *con = space->machine().device<floppy_connector>(BIT(offset, 4) ? "fd1" : "fd0");
	92	floppy_connector *con = machine().device<floppy_connector>(BIT(offset, 4) ? "fd1" : "fd0");
93	93	floppy_image_device *floppy = con ? con->get_device() : 0;
94	94
95	95	if(floppy)
r14963	r14964
106	106	}
107	107	}
108	108
109		static READ8_HANDLER( samcoupe_pen_r )
	109	READ8_MEMBER(samcoupe_state::samcoupe_pen_r)
110	110	{
111		screen_device *scr = space->machine().primary_screen;
	111	screen_device *scr = machine().primary_screen;
112	112	UINT8 data;
113	113
114	114	if (offset & 0x100)
r14963	r14964
130	130	return data;
131	131	}
132	132
133		static WRITE8_HANDLER( samcoupe_clut_w )
	133	WRITE8_MEMBER(samcoupe_state::samcoupe_clut_w)
134	134	{
135		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
136		state->m_clut[(offset >> 8) & 0x0f] = data & 0x7f;
	135	m_clut[(offset >> 8) & 0x0f] = data & 0x7f;
137	136	}
138	137
139		static READ8_HANDLER( samcoupe_status_r )
	138	READ8_MEMBER(samcoupe_state::samcoupe_status_r)
140	139	{
141		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
142	140	UINT8 data = 0xe0;
143	141
144	142	/* bit 5-7, keyboard input */
145		if (!BIT(offset,  8)) data &= input_port_read(space->machine(), "keyboard_row_fe") & 0xe0;
146		if (!BIT(offset,  9)) data &= input_port_read(space->machine(), "keyboard_row_fd") & 0xe0;
147		if (!BIT(offset, 10)) data &= input_port_read(space->machine(), "keyboard_row_fb") & 0xe0;
148		if (!BIT(offset, 11)) data &= input_port_read(space->machine(), "keyboard_row_f7") & 0xe0;
149		if (!BIT(offset, 12)) data &= input_port_read(space->machine(), "keyboard_row_ef") & 0xe0;
150		if (!BIT(offset, 13)) data &= input_port_read(space->machine(), "keyboard_row_df") & 0xe0;
151		if (!BIT(offset, 14)) data &= input_port_read(space->machine(), "keyboard_row_bf") & 0xe0;
152		if (!BIT(offset, 15)) data &= input_port_read(space->machine(), "keyboard_row_7f") & 0xe0;
	143	if (!BIT(offset,  8)) data &= input_port_read(machine(), "keyboard_row_fe") & 0xe0;
	144	if (!BIT(offset,  9)) data &= input_port_read(machine(), "keyboard_row_fd") & 0xe0;
	145	if (!BIT(offset, 10)) data &= input_port_read(machine(), "keyboard_row_fb") & 0xe0;
	146	if (!BIT(offset, 11)) data &= input_port_read(machine(), "keyboard_row_f7") & 0xe0;
	147	if (!BIT(offset, 12)) data &= input_port_read(machine(), "keyboard_row_ef") & 0xe0;
	148	if (!BIT(offset, 13)) data &= input_port_read(machine(), "keyboard_row_df") & 0xe0;
	149	if (!BIT(offset, 14)) data &= input_port_read(machine(), "keyboard_row_bf") & 0xe0;
	150	if (!BIT(offset, 15)) data &= input_port_read(machine(), "keyboard_row_7f") & 0xe0;
153	151
154	152	/* bit 0-4, interrupt source */
155		data |= state->m_status;
	153	data |= m_status;
156	154
157	155	return data;
158	156	}
159	157
160		static WRITE8_HANDLER( samcoupe_line_int_w )
	158	WRITE8_MEMBER(samcoupe_state::samcoupe_line_int_w)
161	159	{
162		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
163		state->m_line_int = data;
	160	m_line_int = data;
164	161	}
165	162
166		static READ8_HANDLER( samcoupe_lmpr_r )
	163	READ8_MEMBER(samcoupe_state::samcoupe_lmpr_r)
167	164	{
168		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
169		return state->m_lmpr;
	165	return m_lmpr;
170	166	}
171	167
172		static WRITE8_HANDLER( samcoupe_lmpr_w )
	168	WRITE8_MEMBER(samcoupe_state::samcoupe_lmpr_w)
173	169	{
174		address_space *space_program = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
175		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
	170	address_space *space_program = machine().device("maincpu")->memory().space(AS_PROGRAM);
176	171
177		state->m_lmpr = data;
	172	m_lmpr = data;
178	173	samcoupe_update_memory(space_program);
179	174	}
180	175
181		static READ8_HANDLER( samcoupe_hmpr_r )
	176	READ8_MEMBER(samcoupe_state::samcoupe_hmpr_r)
182	177	{
183		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
184		return state->m_hmpr;
	178	return m_hmpr;
185	179	}
186	180
187		static WRITE8_HANDLER( samcoupe_hmpr_w )
	181	WRITE8_MEMBER(samcoupe_state::samcoupe_hmpr_w)
188	182	{
189		address_space *space_program = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
190		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
	183	address_space *space_program = machine().device("maincpu")->memory().space(AS_PROGRAM);
191	184
192		state->m_hmpr = data;
	185	m_hmpr = data;
193	186	samcoupe_update_memory(space_program);
194	187	}
195	188
196		static READ8_HANDLER( samcoupe_vmpr_r )
	189	READ8_MEMBER(samcoupe_state::samcoupe_vmpr_r)
197	190	{
198		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
199		return state->m_vmpr;
	191	return m_vmpr;
200	192	}
201	193
202		static WRITE8_HANDLER( samcoupe_vmpr_w )
	194	WRITE8_MEMBER(samcoupe_state::samcoupe_vmpr_w)
203	195	{
204		address_space *space_program = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
205		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
	196	address_space *space_program = machine().device("maincpu")->memory().space(AS_PROGRAM);
206	197
207		state->m_vmpr = data;
	198	m_vmpr = data;
208	199	samcoupe_update_memory(space_program);
209	200	}
210	201
211		static READ8_HANDLER( samcoupe_midi_r )
	202	READ8_MEMBER(samcoupe_state::samcoupe_midi_r)
212	203	{
213		logerror("%s: read from midi port\n", space->machine().describe_context());
	204	logerror("%s: read from midi port\n", machine().describe_context());
214	205	return 0xff;
215	206	}
216	207
217		static WRITE8_HANDLER( samcoupe_midi_w )
	208	WRITE8_MEMBER(samcoupe_state::samcoupe_midi_w)
218	209	{
219		logerror("%s: write to midi port: 0x%02x\n", space->machine().describe_context(), data);
	210	logerror("%s: write to midi port: 0x%02x\n", machine().describe_context(), data);
220	211	}
221	212
222		static READ8_HANDLER( samcoupe_keyboard_r )
	213	READ8_MEMBER(samcoupe_state::samcoupe_keyboard_r)
223	214	{
224		cassette_image_device *cassette = space->machine().device<cassette_image_device>(CASSETTE_TAG);
	215	cassette_image_device *cassette = machine().device<cassette_image_device>(CASSETTE_TAG);
225	216	UINT8 data = 0x1f;
226	217
227	218	/* bit 0-4, keyboard input */
228		if (!BIT(offset,  8)) data &= input_port_read(space->machine(), "keyboard_row_fe") & 0x1f;
229		if (!BIT(offset,  9)) data &= input_port_read(space->machine(), "keyboard_row_fd") & 0x1f;
230		if (!BIT(offset, 10)) data &= input_port_read(space->machine(), "keyboard_row_fb") & 0x1f;
231		if (!BIT(offset, 11)) data &= input_port_read(space->machine(), "keyboard_row_f7") & 0x1f;
232		if (!BIT(offset, 12)) data &= input_port_read(space->machine(), "keyboard_row_ef") & 0x1f;
233		if (!BIT(offset, 13)) data &= input_port_read(space->machine(), "keyboard_row_df") & 0x1f;
234		if (!BIT(offset, 14)) data &= input_port_read(space->machine(), "keyboard_row_bf") & 0x1f;
235		if (!BIT(offset, 15)) data &= input_port_read(space->machine(), "keyboard_row_7f") & 0x1f;
	219	if (!BIT(offset,  8)) data &= input_port_read(machine(), "keyboard_row_fe") & 0x1f;
	220	if (!BIT(offset,  9)) data &= input_port_read(machine(), "keyboard_row_fd") & 0x1f;
	221	if (!BIT(offset, 10)) data &= input_port_read(machine(), "keyboard_row_fb") & 0x1f;
	222	if (!BIT(offset, 11)) data &= input_port_read(machine(), "keyboard_row_f7") & 0x1f;
	223	if (!BIT(offset, 12)) data &= input_port_read(machine(), "keyboard_row_ef") & 0x1f;
	224	if (!BIT(offset, 13)) data &= input_port_read(machine(), "keyboard_row_df") & 0x1f;
	225	if (!BIT(offset, 14)) data &= input_port_read(machine(), "keyboard_row_bf") & 0x1f;
	226	if (!BIT(offset, 15)) data &= input_port_read(machine(), "keyboard_row_7f") & 0x1f;
236	227
237	228	if (offset == 0xff00)
238	229	{
239		data &= input_port_read(space->machine(), "keyboard_row_ff") & 0x1f;
	230	data &= input_port_read(machine(), "keyboard_row_ff") & 0x1f;
240	231
241	232	/* if no key has been pressed, return the mouse state */
242	233	if (data == 0x1f)
243		data = samcoupe_mouse_r(space->machine());
	234	data = samcoupe_mouse_r(machine());
244	235	}
245	236
246	237	/* bit 5, lightpen strobe */
r14963	r14964
255	246	return data;
256	247	}
257	248
258		static WRITE8_HANDLER( samcoupe_border_w )
	249	WRITE8_MEMBER(samcoupe_state::samcoupe_border_w)
259	250	{
260		cassette_image_device *cassette = space->machine().device<cassette_image_device>(CASSETTE_TAG);
261		device_t *speaker = space->machine().device(SPEAKER_TAG);
262		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
	251	cassette_image_device *cassette = machine().device<cassette_image_device>(CASSETTE_TAG);
	252	device_t *speaker = machine().device(SPEAKER_TAG);
263	253
264		state->m_border = data;
	254	m_border = data;
265	255
266	256	/* bit 3, cassette output */
267	257	cassette->output( BIT(data, 3) ? -1.0 : +1.0);
r14963	r14964
270	260	speaker_level_w(speaker, BIT(data, 4));
271	261	}
272	262
273		static READ8_HANDLER( samcoupe_attributes_r )
	263	READ8_MEMBER(samcoupe_state::samcoupe_attributes_r)
274	264	{
275		samcoupe_state *state = space->machine().driver_data<samcoupe_state>();
276		return state->m_attribute;
	265	return m_attribute;
277	266	}
278	267
279	268	static READ8_DEVICE_HANDLER( samcoupe_lpt1_busy_r )
r14963	r14964
313	302	ADDRESS_MAP_END
314	303
315	304	static ADDRESS_MAP_START( samcoupe_io, AS_IO, 8, samcoupe_state )
316		AM_RANGE(0x0080, 0x0081) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_WRITE_LEGACY(samcoupe_ext_mem_w)
317		AM_RANGE(0x00e0, 0x00e7) AM_MIRROR(0xff10) AM_MASK(0xffff) AM_READWRITE_LEGACY(samcoupe_disk_r, samcoupe_disk_w)
	305	AM_RANGE(0x0080, 0x0081) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_WRITE(samcoupe_ext_mem_w)
	306	AM_RANGE(0x00e0, 0x00e7) AM_MIRROR(0xff10) AM_MASK(0xffff) AM_READWRITE(samcoupe_disk_r, samcoupe_disk_w)
318	307	AM_RANGE(0x00e8, 0x00e8) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_DEVWRITE("lpt1", centronics_device, write)
319	308	AM_RANGE(0x00e9, 0x00e9) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_DEVREADWRITE_LEGACY("lpt1", samcoupe_lpt1_busy_r, samcoupe_lpt1_strobe_w)
320	309	AM_RANGE(0x00ea, 0x00ea) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_DEVWRITE("lpt2", centronics_device, write)
321	310	AM_RANGE(0x00eb, 0x00eb) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_DEVREADWRITE_LEGACY("lpt2", samcoupe_lpt2_busy_r, samcoupe_lpt2_strobe_w)
322		AM_RANGE(0x00f8, 0x00f8) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE_LEGACY(samcoupe_pen_r, samcoupe_clut_w)
323		AM_RANGE(0x00f9, 0x00f9) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE_LEGACY(samcoupe_status_r, samcoupe_line_int_w)
324		AM_RANGE(0x00fa, 0x00fa) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE_LEGACY(samcoupe_lmpr_r, samcoupe_lmpr_w)
325		AM_RANGE(0x00fb, 0x00fb) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE_LEGACY(samcoupe_hmpr_r, samcoupe_hmpr_w)
326		AM_RANGE(0x00fc, 0x00fc) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE_LEGACY(samcoupe_vmpr_r, samcoupe_vmpr_w)
327		AM_RANGE(0x00fd, 0x00fd) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE_LEGACY(samcoupe_midi_r, samcoupe_midi_w)
328		AM_RANGE(0x00fe, 0x00fe) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE_LEGACY(samcoupe_keyboard_r, samcoupe_border_w)
329		AM_RANGE(0x00ff, 0x00ff) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READ_LEGACY(samcoupe_attributes_r)
	311	AM_RANGE(0x00f8, 0x00f8) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE(samcoupe_pen_r, samcoupe_clut_w)
	312	AM_RANGE(0x00f9, 0x00f9) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE(samcoupe_status_r, samcoupe_line_int_w)
	313	AM_RANGE(0x00fa, 0x00fa) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE(samcoupe_lmpr_r, samcoupe_lmpr_w)
	314	AM_RANGE(0x00fb, 0x00fb) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE(samcoupe_hmpr_r, samcoupe_hmpr_w)
	315	AM_RANGE(0x00fc, 0x00fc) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE(samcoupe_vmpr_r, samcoupe_vmpr_w)
	316	AM_RANGE(0x00fd, 0x00fd) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE(samcoupe_midi_r, samcoupe_midi_w)
	317	AM_RANGE(0x00fe, 0x00fe) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READWRITE(samcoupe_keyboard_r, samcoupe_border_w)
	318	AM_RANGE(0x00ff, 0x00ff) AM_MIRROR(0xff00) AM_MASK(0xffff) AM_READ(samcoupe_attributes_r)
330	319	AM_RANGE(0x00ff, 0x00ff) AM_MIRROR(0xfe00) AM_MASK(0xffff) AM_DEVWRITE_LEGACY("saa1099", saa1099_data_w)
331	320	AM_RANGE(0x01ff, 0x01ff) AM_MIRROR(0xfe00) AM_MASK(0xffff) AM_DEVWRITE_LEGACY("saa1099", saa1099_control_w)
332	321	ADDRESS_MAP_END

src/mess/drivers/odyssey2.c

r14963	r14964
22	22	ADDRESS_MAP_END
23	23
24	24	static ADDRESS_MAP_START( odyssey2_io , AS_IO, 8, odyssey2_state )
25		AM_RANGE( 0x00,       0xff)      AM_READWRITE_LEGACY(odyssey2_bus_r, odyssey2_bus_w)
26		AM_RANGE( MCS48_PORT_P1,   MCS48_PORT_P1)   AM_READWRITE_LEGACY(odyssey2_getp1, odyssey2_putp1 )
27		AM_RANGE( MCS48_PORT_P2,   MCS48_PORT_P2)   AM_READWRITE_LEGACY(odyssey2_getp2, odyssey2_putp2 )
28		AM_RANGE( MCS48_PORT_BUS,   MCS48_PORT_BUS)   AM_READWRITE_LEGACY(odyssey2_getbus, odyssey2_putbus )
29		AM_RANGE( MCS48_PORT_T0,   MCS48_PORT_T0)  AM_READ_LEGACY(odyssey2_t0_r )
30		AM_RANGE( MCS48_PORT_T1,   MCS48_PORT_T1)   AM_READ_LEGACY(odyssey2_t1_r )
	25	AM_RANGE( 0x00,       0xff)      AM_READWRITE(odyssey2_bus_r, odyssey2_bus_w)
	26	AM_RANGE( MCS48_PORT_P1,   MCS48_PORT_P1)   AM_READWRITE(odyssey2_getp1, odyssey2_putp1 )
	27	AM_RANGE( MCS48_PORT_P2,   MCS48_PORT_P2)   AM_READWRITE(odyssey2_getp2, odyssey2_putp2 )
	28	AM_RANGE( MCS48_PORT_BUS,   MCS48_PORT_BUS)   AM_READWRITE(odyssey2_getbus, odyssey2_putbus )
	29	AM_RANGE( MCS48_PORT_T0,   MCS48_PORT_T0)  AM_READ(odyssey2_t0_r )
	30	AM_RANGE( MCS48_PORT_T1,   MCS48_PORT_T1)   AM_READ(odyssey2_t1_r )
31	31	ADDRESS_MAP_END
32	32
33	33	static ADDRESS_MAP_START( g7400_io , AS_IO, 8, odyssey2_state )
34		AM_RANGE( 0x00,      0xff)      AM_READWRITE_LEGACY(g7400_bus_r, g7400_bus_w)
35		AM_RANGE( MCS48_PORT_P1,   MCS48_PORT_P1)  AM_READWRITE_LEGACY(odyssey2_getp1, odyssey2_putp1 )
36		AM_RANGE( MCS48_PORT_P2,   MCS48_PORT_P2)  AM_READWRITE_LEGACY(odyssey2_getp2, odyssey2_putp2 )
37		AM_RANGE( MCS48_PORT_BUS,   MCS48_PORT_BUS) AM_READWRITE_LEGACY(odyssey2_getbus, odyssey2_putbus )
38		AM_RANGE( MCS48_PORT_T0,   MCS48_PORT_T0)  AM_READ_LEGACY(odyssey2_t0_r )
39		AM_RANGE( MCS48_PORT_T1,   MCS48_PORT_T1)  AM_READ_LEGACY(odyssey2_t1_r )
	34	AM_RANGE( 0x00,      0xff)      AM_READWRITE(g7400_bus_r, g7400_bus_w)
	35	AM_RANGE( MCS48_PORT_P1,   MCS48_PORT_P1)  AM_READWRITE(odyssey2_getp1, odyssey2_putp1 )
	36	AM_RANGE( MCS48_PORT_P2,   MCS48_PORT_P2)  AM_READWRITE(odyssey2_getp2, odyssey2_putp2 )
	37	AM_RANGE( MCS48_PORT_BUS,   MCS48_PORT_BUS) AM_READWRITE(odyssey2_getbus, odyssey2_putbus )
	38	AM_RANGE( MCS48_PORT_T0,   MCS48_PORT_T0)  AM_READ(odyssey2_t0_r )
	39	AM_RANGE( MCS48_PORT_T1,   MCS48_PORT_T1)  AM_READ(odyssey2_t1_r )
40	40	ADDRESS_MAP_END
41	41
42	42	static INPUT_PORTS_START( odyssey2 )

src/mess/drivers/atm.c

r14963	r14964
109	109	AM_RANGE(0x003f, 0x003f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_track_r,betadisk_track_w) AM_MIRROR(0xff00)
110	110	AM_RANGE(0x005f, 0x005f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_sector_r,betadisk_sector_w) AM_MIRROR(0xff00)
111	111	AM_RANGE(0x007f, 0x007f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_data_r,betadisk_data_w) AM_MIRROR(0xff00)
112		AM_RANGE(0x00fe, 0x00fe) AM_READWRITE_LEGACY(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xff00) AM_MASK(0xffff)
	112	AM_RANGE(0x00fe, 0x00fe) AM_READWRITE(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xff00) AM_MASK(0xffff)
113	113	AM_RANGE(0x00ff, 0x00ff) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_state_r, betadisk_param_w) AM_MIRROR(0xff00)
114	114	AM_RANGE(0x4000, 0x4000) AM_WRITE(atm_port_7ffd_w)  AM_MIRROR(0x3ffd)
115	115	AM_RANGE(0x8000, 0x8000) AM_DEVWRITE_LEGACY("ay8912", ay8910_data_w) AM_MIRROR(0x3ffd)

src/mess/drivers/primo.c

r14963	r14964
118	118
119	119	static ADDRESS_MAP_START( primoa_port, AS_IO, 8, primo_state )
120	120	ADDRESS_MAP_GLOBAL_MASK(0xff)
121		AM_RANGE( 0x00, 0x3f ) AM_READWRITE_LEGACY(primo_be_1_r, primo_ki_1_w )
122		AM_RANGE( 0xfd, 0xfd ) AM_WRITE_LEGACY(primo_FD_w )
	121	AM_RANGE( 0x00, 0x3f ) AM_READWRITE(primo_be_1_r, primo_ki_1_w )
	122	AM_RANGE( 0xfd, 0xfd ) AM_WRITE(primo_FD_w )
123	123	ADDRESS_MAP_END
124	124
125	125	static ADDRESS_MAP_START( primob_port, AS_IO, 8, primo_state )
126	126	ADDRESS_MAP_GLOBAL_MASK(0xff)
127		AM_RANGE( 0x00, 0x3f ) AM_READWRITE_LEGACY(primo_be_1_r, primo_ki_1_w )
128		AM_RANGE( 0x40, 0x7f ) AM_READWRITE_LEGACY(primo_be_2_r, primo_ki_2_w )
129		AM_RANGE( 0xfd, 0xfd ) AM_WRITE_LEGACY(primo_FD_w )
	127	AM_RANGE( 0x00, 0x3f ) AM_READWRITE(primo_be_1_r, primo_ki_1_w )
	128	AM_RANGE( 0x40, 0x7f ) AM_READWRITE(primo_be_2_r, primo_ki_2_w )
	129	AM_RANGE( 0xfd, 0xfd ) AM_WRITE(primo_FD_w )
130	130	ADDRESS_MAP_END
131	131
132	132	static ADDRESS_MAP_START( primo32_mem, AS_PROGRAM, 8, primo_state )

src/mess/drivers/ti85.c

r14963	r14964
195	195
196	196	static ADDRESS_MAP_START( ti81_io, AS_IO, 8, ti85_state )
197	197	ADDRESS_MAP_GLOBAL_MASK(0xff)
198		AM_RANGE(0x0000, 0x0000) AM_READWRITE_LEGACY(ti85_port_0000_r, ti85_port_0000_w )
199		AM_RANGE(0x0001, 0x0001) AM_READWRITE_LEGACY(ti8x_keypad_r, ti8x_keypad_w )
200		AM_RANGE(0x0002, 0x0002) AM_READWRITE_LEGACY(ti85_port_0002_r, ti85_port_0002_w )
201		AM_RANGE(0x0003, 0x0003) AM_READWRITE_LEGACY(ti85_port_0003_r, ti85_port_0003_w )
202		AM_RANGE(0x0004, 0x0004) AM_READWRITE_LEGACY(ti85_port_0004_r, ti85_port_0004_w )
203		AM_RANGE(0x0005, 0x0005) AM_READWRITE_LEGACY(ti85_port_0005_r, ti85_port_0005_w )
204		AM_RANGE(0x0007, 0x0007) AM_WRITE_LEGACY(ti81_port_0007_w)
	198	AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti85_port_0000_r, ti85_port_0000_w )
	199	AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
	200	AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti85_port_0002_r, ti85_port_0002_w )
	201	AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti85_port_0003_r, ti85_port_0003_w )
	202	AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti85_port_0004_r, ti85_port_0004_w )
	203	AM_RANGE(0x0005, 0x0005) AM_READWRITE(ti85_port_0005_r, ti85_port_0005_w )
	204	AM_RANGE(0x0007, 0x0007) AM_WRITE(ti81_port_0007_w)
205	205	ADDRESS_MAP_END
206	206
207	207	static ADDRESS_MAP_START( ti85_io, AS_IO, 8, ti85_state )
208	208	ADDRESS_MAP_GLOBAL_MASK(0xff)
209		AM_RANGE(0x0000, 0x0000) AM_READWRITE_LEGACY(ti85_port_0000_r, ti85_port_0000_w )
210		AM_RANGE(0x0001, 0x0001) AM_READWRITE_LEGACY(ti8x_keypad_r, ti8x_keypad_w )
211		AM_RANGE(0x0002, 0x0002) AM_READWRITE_LEGACY(ti85_port_0002_r, ti85_port_0002_w )
212		AM_RANGE(0x0003, 0x0003) AM_READWRITE_LEGACY(ti85_port_0003_r, ti85_port_0003_w )
213		AM_RANGE(0x0004, 0x0004) AM_READWRITE_LEGACY(ti85_port_0004_r, ti85_port_0004_w )
214		AM_RANGE(0x0005, 0x0005) AM_READWRITE_LEGACY(ti85_port_0005_r, ti85_port_0005_w )
215		AM_RANGE(0x0006, 0x0006) AM_READWRITE_LEGACY(ti85_port_0006_r, ti85_port_0006_w )
216		AM_RANGE(0x0007, 0x0007) AM_READWRITE_LEGACY(ti8x_serial_r, ti8x_serial_w )
	209	AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti85_port_0000_r, ti85_port_0000_w )
	210	AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
	211	AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti85_port_0002_r, ti85_port_0002_w )
	212	AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti85_port_0003_r, ti85_port_0003_w )
	213	AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti85_port_0004_r, ti85_port_0004_w )
	214	AM_RANGE(0x0005, 0x0005) AM_READWRITE(ti85_port_0005_r, ti85_port_0005_w )
	215	AM_RANGE(0x0006, 0x0006) AM_READWRITE(ti85_port_0006_r, ti85_port_0006_w )
	216	AM_RANGE(0x0007, 0x0007) AM_READWRITE(ti8x_serial_r, ti8x_serial_w )
217	217	ADDRESS_MAP_END
218	218
219	219	static ADDRESS_MAP_START( ti82_io, AS_IO, 8, ti85_state )
220	220	ADDRESS_MAP_GLOBAL_MASK(0xff)
221		AM_RANGE(0x0000, 0x0000) AM_READWRITE_LEGACY(ti8x_serial_r, ti8x_serial_w )
222		AM_RANGE(0x0001, 0x0001) AM_READWRITE_LEGACY(ti8x_keypad_r, ti8x_keypad_w )
223		AM_RANGE(0x0002, 0x0002) AM_READWRITE_LEGACY(ti82_port_0002_r, ti82_port_0002_w )
224		AM_RANGE(0x0003, 0x0003) AM_READWRITE_LEGACY(ti85_port_0003_r, ti85_port_0003_w )
225		AM_RANGE(0x0004, 0x0004) AM_READWRITE_LEGACY(ti85_port_0004_r, ti85_port_0004_w )
	221	AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti8x_serial_r, ti8x_serial_w )
	222	AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
	223	AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti82_port_0002_r, ti82_port_0002_w )
	224	AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti85_port_0003_r, ti85_port_0003_w )
	225	AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti85_port_0004_r, ti85_port_0004_w )
226	226	AM_RANGE(0x0010, 0x0010) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
227	227	AM_RANGE(0x0011, 0x0011) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
228	228	ADDRESS_MAP_END
229	229
230	230	static ADDRESS_MAP_START( ti81v2_io, AS_IO, 8, ti85_state )
231	231	ADDRESS_MAP_GLOBAL_MASK(0xff)
232		AM_RANGE(0x0001, 0x0001) AM_READWRITE_LEGACY(ti8x_keypad_r, ti8x_keypad_w )
233		AM_RANGE(0x0002, 0x0002) AM_READWRITE_LEGACY(ti82_port_0002_r, ti82_port_0002_w )
234		AM_RANGE(0x0003, 0x0003) AM_READWRITE_LEGACY(ti85_port_0003_r, ti85_port_0003_w )
235		AM_RANGE(0x0004, 0x0004) AM_READWRITE_LEGACY(ti85_port_0004_r, ti85_port_0004_w )
	232	AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
	233	AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti82_port_0002_r, ti82_port_0002_w )
	234	AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti85_port_0003_r, ti85_port_0003_w )
	235	AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti85_port_0004_r, ti85_port_0004_w )
236	236	AM_RANGE(0x0010, 0x0010) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
237	237	AM_RANGE(0x0011, 0x0011) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
238	238	ADDRESS_MAP_END
239	239
240	240	static ADDRESS_MAP_START( ti83_io, AS_IO, 8, ti85_state )
241	241	ADDRESS_MAP_GLOBAL_MASK(0xff)
242		AM_RANGE(0x0000, 0x0000) AM_READWRITE_LEGACY(ti83_port_0000_r, ti83_port_0000_w )   //TODO
243		AM_RANGE(0x0001, 0x0001) AM_READWRITE_LEGACY(ti8x_keypad_r, ti8x_keypad_w )
244		AM_RANGE(0x0002, 0x0002) AM_READWRITE_LEGACY(ti83_port_0002_r, ti83_port_0002_w )
245		AM_RANGE(0x0003, 0x0003) AM_READWRITE_LEGACY(ti83_port_0003_r, ti83_port_0003_w )
246		AM_RANGE(0x0004, 0x0004) AM_READWRITE_LEGACY(ti85_port_0004_r, ti85_port_0004_w )
	242	AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti83_port_0000_r, ti83_port_0000_w )   //TODO
	243	AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
	244	AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti83_port_0002_r, ti83_port_0002_w )
	245	AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti83_port_0003_r, ti83_port_0003_w )
	246	AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti85_port_0004_r, ti85_port_0004_w )
247	247	AM_RANGE(0x0010, 0x0010) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
248	248	AM_RANGE(0x0011, 0x0011) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
249	249	AM_RANGE(0x0014, 0x0014) AM_READ_PORT( "BATTERY" )
r14963	r14964
251	251
252	252	static ADDRESS_MAP_START( ti83p_io, AS_IO, 8, ti85_state )
253	253	ADDRESS_MAP_GLOBAL_MASK(0xff)
254		AM_RANGE(0x0000, 0x0000) AM_READWRITE_LEGACY(ti8x_plus_serial_r, ti8x_plus_serial_w)
255		AM_RANGE(0x0001, 0x0001) AM_READWRITE_LEGACY(ti8x_keypad_r, ti8x_keypad_w )
256		AM_RANGE(0x0002, 0x0002) AM_READWRITE_LEGACY(ti83p_port_0002_r, ti83p_port_0002_w )
257		AM_RANGE(0x0003, 0x0003) AM_READWRITE_LEGACY(ti83_port_0003_r, ti83p_port_0003_w )
258		AM_RANGE(0x0004, 0x0004) AM_READWRITE_LEGACY(ti83_port_0003_r, ti83p_port_0004_w )
259		AM_RANGE(0x0006, 0x0006) AM_READWRITE_LEGACY(ti86_port_0005_r, ti83p_port_0006_w )
260		AM_RANGE(0x0007, 0x0007) AM_READWRITE_LEGACY(ti86_port_0006_r, ti83p_port_0007_w )
	254	AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti8x_plus_serial_r, ti8x_plus_serial_w)
	255	AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
	256	AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti83p_port_0002_r, ti83p_port_0002_w )
	257	AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti83_port_0003_r, ti83p_port_0003_w )
	258	AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti83_port_0003_r, ti83p_port_0004_w )
	259	AM_RANGE(0x0006, 0x0006) AM_READWRITE(ti86_port_0005_r, ti83p_port_0006_w )
	260	AM_RANGE(0x0007, 0x0007) AM_READWRITE(ti86_port_0006_r, ti83p_port_0007_w )
261	261	AM_RANGE(0x0010, 0x0010) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
262	262	AM_RANGE(0x0011, 0x0011) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
263	263	ADDRESS_MAP_END
264	264
265	265	static ADDRESS_MAP_START( ti86_io, AS_IO, 8, ti85_state )
266	266	ADDRESS_MAP_GLOBAL_MASK(0xff)
267		AM_RANGE(0x0000, 0x0000) AM_READWRITE_LEGACY(ti85_port_0000_r, ti85_port_0000_w )
268		AM_RANGE(0x0001, 0x0001) AM_READWRITE_LEGACY(ti8x_keypad_r, ti8x_keypad_w )
269		AM_RANGE(0x0002, 0x0002) AM_READWRITE_LEGACY(ti85_port_0002_r, ti85_port_0002_w )
270		AM_RANGE(0x0003, 0x0003) AM_READWRITE_LEGACY(ti85_port_0003_r, ti85_port_0003_w )
271		AM_RANGE(0x0004, 0x0004) AM_READWRITE_LEGACY(ti85_port_0006_r, ti85_port_0006_w )
272		AM_RANGE(0x0005, 0x0005) AM_READWRITE_LEGACY(ti86_port_0005_r, ti86_port_0005_w )
273		AM_RANGE(0x0006, 0x0006) AM_READWRITE_LEGACY(ti86_port_0006_r, ti86_port_0006_w )
274		AM_RANGE(0x0007, 0x0007) AM_READWRITE_LEGACY(ti8x_serial_r, ti8x_serial_w )
	267	AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti85_port_0000_r, ti85_port_0000_w )
	268	AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
	269	AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti85_port_0002_r, ti85_port_0002_w )
	270	AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti85_port_0003_r, ti85_port_0003_w )
	271	AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti85_port_0006_r, ti85_port_0006_w )
	272	AM_RANGE(0x0005, 0x0005) AM_READWRITE(ti86_port_0005_r, ti86_port_0005_w )
	273	AM_RANGE(0x0006, 0x0006) AM_READWRITE(ti86_port_0006_r, ti86_port_0006_w )
	274	AM_RANGE(0x0007, 0x0007) AM_READWRITE(ti8x_serial_r, ti8x_serial_w )
275	275	ADDRESS_MAP_END
276	276
277	277	/* memory w/r functions */

src/mess/drivers/svi318.c

r14963	r14964
29	29	#include "rendlay.h"
30	30
31	31	static ADDRESS_MAP_START( svi318_mem, AS_PROGRAM, 8, svi318_state )
32		AM_RANGE( 0x0000, 0x7fff) AM_READ_BANK("bank1") AM_WRITE_LEGACY(svi318_writemem1 )
33		AM_RANGE( 0x8000, 0xbfff) AM_READ_BANK("bank2") AM_WRITE_LEGACY(svi318_writemem2 )
34		AM_RANGE( 0xc000, 0xffff) AM_READ_BANK("bank3") AM_WRITE_LEGACY(svi318_writemem3 )
	32	AM_RANGE( 0x0000, 0x7fff) AM_READ_BANK("bank1") AM_WRITE(svi318_writemem1 )
	33	AM_RANGE( 0x8000, 0xbfff) AM_READ_BANK("bank2") AM_WRITE(svi318_writemem2 )
	34	AM_RANGE( 0xc000, 0xffff) AM_READ_BANK("bank3") AM_WRITE(svi318_writemem3 )
35	35	ADDRESS_MAP_END
36	36
37	37	static ADDRESS_MAP_START( svi328_806_mem, AS_PROGRAM, 8, svi318_state )
38		AM_RANGE( 0x0000, 0x7fff) AM_READ_BANK("bank1") AM_WRITE_LEGACY(svi318_writemem1 )
39		AM_RANGE( 0x8000, 0xbfff) AM_READ_BANK("bank2") AM_WRITE_LEGACY(svi318_writemem2 )
40		AM_RANGE( 0xc000, 0xefff) AM_READ_BANK("bank3") AM_WRITE_LEGACY(svi318_writemem3 )
41		AM_RANGE( 0xf000, 0xffff) AM_READ_BANK("bank4") AM_WRITE_LEGACY(svi318_writemem4 )
	38	AM_RANGE( 0x0000, 0x7fff) AM_READ_BANK("bank1") AM_WRITE(svi318_writemem1 )
	39	AM_RANGE( 0x8000, 0xbfff) AM_READ_BANK("bank2") AM_WRITE(svi318_writemem2 )
	40	AM_RANGE( 0xc000, 0xefff) AM_READ_BANK("bank3") AM_WRITE(svi318_writemem3 )
	41	AM_RANGE( 0xf000, 0xffff) AM_READ_BANK("bank4") AM_WRITE(svi318_writemem4 )
42	42	ADDRESS_MAP_END
43	43
44	44	static ADDRESS_MAP_START( svi318_io, AS_IO, 8, svi318_state )
45	45	ADDRESS_MAP_UNMAP_HIGH
46	46	ADDRESS_MAP_GLOBAL_MASK(0xff)
47		AM_RANGE( 0x00, 0x38) AM_READWRITE_LEGACY(svi318_io_ext_r, svi318_io_ext_w )
	47	AM_RANGE( 0x00, 0x38) AM_READWRITE(svi318_io_ext_r, svi318_io_ext_w )
48	48	AM_RANGE( 0x80, 0x80) AM_DEVWRITE( "tms9928a", tms9928a_device, vram_write )
49	49	AM_RANGE( 0x81, 0x81) AM_DEVWRITE( "tms9928a", tms9928a_device, register_write )
50	50	AM_RANGE( 0x84, 0x84) AM_DEVREAD( "tms9928a", tms9928a_device, vram_read )
r14963	r14964
52	52	AM_RANGE( 0x88, 0x88) AM_DEVWRITE_LEGACY("ay8910", ay8910_address_w )
53	53	AM_RANGE( 0x8c, 0x8c) AM_DEVWRITE_LEGACY("ay8910", ay8910_data_w )
54	54	AM_RANGE( 0x90, 0x90) AM_DEVREAD_LEGACY("ay8910", ay8910_r )
55		AM_RANGE( 0x96, 0x97) AM_WRITE_LEGACY(svi318_ppi_w)
	55	AM_RANGE( 0x96, 0x97) AM_WRITE(svi318_ppi_w)
56	56	AM_RANGE( 0x98, 0x9a) AM_DEVREAD("ppi8255", i8255_device, read)
57	57	ADDRESS_MAP_END
58	58
59	59	static ADDRESS_MAP_START( svi328_806_io, AS_IO, 8, svi318_state )
60	60	ADDRESS_MAP_UNMAP_HIGH
61	61	ADDRESS_MAP_GLOBAL_MASK(0xff)
62		AM_RANGE( 0x00, 0x58) AM_READWRITE_LEGACY(svi318_io_ext_r, svi318_io_ext_w )
	62	AM_RANGE( 0x00, 0x58) AM_READWRITE(svi318_io_ext_r, svi318_io_ext_w )
63	63	AM_RANGE( 0x80, 0x80) AM_DEVWRITE( "tms9928a", tms9928a_device, vram_write )
64	64	AM_RANGE( 0x81, 0x81) AM_DEVWRITE( "tms9928a", tms9928a_device, register_write )
65	65	AM_RANGE( 0x84, 0x84) AM_DEVREAD( "tms9928a", tms9928a_device, vram_read )
r14963	r14964
67	67	AM_RANGE( 0x88, 0x88) AM_DEVWRITE_LEGACY("ay8910", ay8910_address_w )
68	68	AM_RANGE( 0x8c, 0x8c) AM_DEVWRITE_LEGACY("ay8910", ay8910_data_w )
69	69	AM_RANGE( 0x90, 0x90) AM_DEVREAD_LEGACY("ay8910", ay8910_r )
70		AM_RANGE( 0x96, 0x97) AM_WRITE_LEGACY(svi318_ppi_w)
	70	AM_RANGE( 0x96, 0x97) AM_WRITE(svi318_ppi_w)
71	71	AM_RANGE( 0x98, 0x9a) AM_DEVREAD("ppi8255", i8255_device, read)
72	72	ADDRESS_MAP_END
73	73
r14963	r14964
254	254	{
255	255	AY8910_LEGACY_OUTPUT,
256	256	AY8910_DEFAULT_LOADS,
257		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, svi318_psg_port_a_r),
	257	DEVCB_DRIVER_MEMBER(svi318_state, svi318_psg_port_a_r),
258	258	DEVCB_NULL,
259	259	DEVCB_NULL,
260		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, svi318_psg_port_b_w)
	260	DEVCB_DRIVER_MEMBER(svi318_state, svi318_psg_port_b_w)
261	261	};
262	262
263	263	static WRITE_LINE_DEVICE_HANDLER(vdp_interrupt)

src/mess/drivers/amstr_pc.c

r14963	r14964
88	88	AM_RANGE(0x0070, 0x0071) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0xffff)
89	89	AM_RANGE(0x0078, 0x0079) AM_READWRITE_LEGACY(pc1640_16le_mouse_x_r,         pc1640_16le_mouse_x_w)
90	90	AM_RANGE(0x007a, 0x007b) AM_READWRITE_LEGACY(pc1640_16le_mouse_y_r,         pc1640_16le_mouse_y_w)
91		AM_RANGE(0x0080, 0x0087) AM_READWRITE8_LEGACY(pc_page_r,               pc_page_w, 0xffff)
	91	AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r,               pc_page_w, 0xffff)
92	92	AM_RANGE(0x0200, 0x0207) AM_READWRITE_LEGACY(pc16le_JOY_r,               pc16le_JOY_w)
93	93	AM_RANGE(0x0278, 0x027b) AM_READ_LEGACY(pc200_16le_port278_r) AM_DEVWRITE8_LEGACY("lpt_2", pc_lpt_w, 0x00ff)
94	94	AM_RANGE(0x02e8, 0x02ef) AM_DEVREADWRITE8("ins8250_3", ins8250_device, ins8250_r, ins8250_w, 0xffff)
r14963	r14964
116	116	AM_RANGE(0x0060, 0x0065) AM_READWRITE_LEGACY(pc1640_16le_port60_r,         pc1640_16le_port60_w)
117	117	AM_RANGE(0x0078, 0x0079) AM_READWRITE_LEGACY(pc1640_16le_mouse_x_r,         pc1640_16le_mouse_x_w)
118	118	AM_RANGE(0x007a, 0x007b) AM_READWRITE_LEGACY(pc1640_16le_mouse_y_r,         pc1640_16le_mouse_y_w)
119		AM_RANGE(0x0080, 0x0087) AM_READWRITE8_LEGACY(pc_page_r,               pc_page_w, 0xffff)
	119	AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r,               pc_page_w, 0xffff)
120	120	AM_RANGE(0x0200, 0x0207) AM_READWRITE_LEGACY(pc16le_JOY_r,               pc16le_JOY_w)
121	121	AM_RANGE(0x0278, 0x027b) AM_READ_LEGACY(pc200_16le_port278_r) AM_DEVWRITE8_LEGACY("lpt_2", pc_lpt_w, 0x00ff)
122	122	AM_RANGE(0x02e8, 0x02ef) AM_DEVREADWRITE8("ins8250_3", ins8250_device, ins8250_r,  ins8250_w, 0xffff)

src/mess/drivers/interact.c

r14963	r14964
77	77	ADDRESS_MAP_UNMAP_HIGH
78	78	/* Hardware address mapping*/
79	79	/*  AM_RANGE(0x0800,0x0808) AM_WRITE_LEGACY(hector_switch_bank_w)// Bank management not udsed in BR machine*/
80		AM_RANGE(0x1000,0x1000) AM_WRITE_LEGACY(hector_color_a_w)  /* Color c0/c1*/
81		AM_RANGE(0x1800,0x1800) AM_WRITE_LEGACY(hector_color_b_w)  /* Color c2/c3*/
82		AM_RANGE(0x2000,0x2003) AM_WRITE_LEGACY(hector_sn_2000_w)  /* Sound*/
83		AM_RANGE(0x2800,0x2803) AM_WRITE_LEGACY(hector_sn_2800_w)  /* Sound*/
84		AM_RANGE(0x3000,0x3000) AM_READWRITE_LEGACY(hector_cassette_r, hector_sn_3000_w)/* Write necessary*/
85		AM_RANGE(0x3800,0x3807) AM_READWRITE_LEGACY(hector_keyboard_r, hector_keyboard_w)  /* Keyboard*/
	80	AM_RANGE(0x1000,0x1000) AM_WRITE(hector_color_a_w)  /* Color c0/c1*/
	81	AM_RANGE(0x1800,0x1800) AM_WRITE(hector_color_b_w)  /* Color c2/c3*/
	82	AM_RANGE(0x2000,0x2003) AM_WRITE(hector_sn_2000_w)  /* Sound*/
	83	AM_RANGE(0x2800,0x2803) AM_WRITE(hector_sn_2800_w)  /* Sound*/
	84	AM_RANGE(0x3000,0x3000) AM_READWRITE(hector_cassette_r, hector_sn_3000_w)/* Write necessary*/
	85	AM_RANGE(0x3800,0x3807) AM_READWRITE(hector_keyboard_r, hector_keyboard_w)  /* Keyboard*/
86	86
87	87	/* Main ROM page*/
88	88	AM_RANGE(0x0000,0x3fff) AM_ROM  /*BANK(2)*/

src/mess/drivers/galaxy.c

r14963	r14964
41	41
42	42	static ADDRESS_MAP_START (galaxy_mem, AS_PROGRAM, 8, galaxy_state )
43	43	AM_RANGE(0x0000, 0x0fff) AM_ROM
44		AM_RANGE(0x2000, 0x2037) AM_MIRROR(0x07c0) AM_READ_LEGACY(galaxy_keyboard_r )
45		AM_RANGE(0x2038, 0x203f) AM_MIRROR(0x07c0) AM_WRITE_LEGACY(galaxy_latch_w )
	44	AM_RANGE(0x2000, 0x2037) AM_MIRROR(0x07c0) AM_READ(galaxy_keyboard_r )
	45	AM_RANGE(0x2038, 0x203f) AM_MIRROR(0x07c0) AM_WRITE(galaxy_latch_w )
46	46	ADDRESS_MAP_END
47	47
48	48	static ADDRESS_MAP_START (galaxyp_mem, AS_PROGRAM, 8, galaxy_state )
49	49	AM_RANGE(0x0000, 0x0fff) AM_ROM // ROM A
50	50	AM_RANGE(0x1000, 0x1fff) AM_ROM // ROM B
51		AM_RANGE(0x2000, 0x2037) AM_MIRROR(0x07c0) AM_READ_LEGACY(galaxy_keyboard_r )
52		AM_RANGE(0x2038, 0x203f) AM_MIRROR(0x07c0) AM_WRITE_LEGACY(galaxy_latch_w )
	51	AM_RANGE(0x2000, 0x2037) AM_MIRROR(0x07c0) AM_READ(galaxy_keyboard_r )
	52	AM_RANGE(0x2038, 0x203f) AM_MIRROR(0x07c0) AM_WRITE(galaxy_latch_w )
53	53	AM_RANGE(0xe000, 0xefff) AM_ROM // ROM C
54	54	AM_RANGE(0xf000, 0xffff) AM_ROM // ROM D
55	55	ADDRESS_MAP_END

src/mess/drivers/fm7.c

r14963	r14964
199	199	*   bit 7 - SYNDET
200	200	*
201	201	*/
202		static WRITE8_HANDLER( fm7_irq_mask_w )
	202	WRITE8_MEMBER(fm7_state::fm7_irq_mask_w)
203	203	{
204		fm7_state *state = space->machine().driver_data<fm7_state>();
205		state->m_irq_mask = data;
206		logerror("IRQ mask set: 0x%02x\n",state->m_irq_mask);
	204	m_irq_mask = data;
	205	logerror("IRQ mask set: 0x%02x\n",m_irq_mask);
207	206	}
208	207
209	208	/*
r14963	r14964
219	218	*   bit 6 - buzzer on for 205ms
220	219	*   bit 7 - buzzer on/off
221	220	*/
222		static READ8_HANDLER( fm7_irq_cause_r )
	221	READ8_MEMBER(fm7_state::fm7_irq_cause_r)
223	222	{
224		fm7_state *state = space->machine().driver_data<fm7_state>();
225		UINT8 ret = ~state->m_irq_flags;
	223	UINT8 ret = ~m_irq_flags;
226	224
227	225	// Timer and Printer IRQ flags are cleared when this port is read
228	226	// Keyboard IRQ flag is cleared when the scancode is read from
229	227	// either keyboard data port (main CPU 0xfd01 or sub CPU 0xd401)
230		if(state->m_irq_flags & 0x04)
231		main_irq_clear_flag(space->machine(),IRQ_FLAG_TIMER);
232		if(state->m_irq_flags & 0x02)
233		main_irq_clear_flag(space->machine(),IRQ_FLAG_PRINTER);
	228	if(m_irq_flags & 0x04)
	229	main_irq_clear_flag(machine(),IRQ_FLAG_TIMER);
	230	if(m_irq_flags & 0x02)
	231	main_irq_clear_flag(machine(),IRQ_FLAG_PRINTER);
234	232
235	233	logerror("IRQ flags read: 0x%02x\n",ret);
236	234	return ret;
r14963	r14964
242	240	logerror("timed beeper off\n");
243	241	}
244	242
245		static WRITE8_HANDLER( fm7_beeper_w )
	243	WRITE8_MEMBER(fm7_state::fm7_beeper_w)
246	244	{
247		fm7_state *state = space->machine().driver_data<fm7_state>();
248		state->m_speaker_active = data & 0x01;
	245	m_speaker_active = data & 0x01;
249	246
250		if(!state->m_speaker_active)  // speaker not active, disable all beeper sound
	247	if(!m_speaker_active)  // speaker not active, disable all beeper sound
251	248	{
252		beep_set_state(space->machine().device(BEEPER_TAG),0);
	249	beep_set_state(machine().device(BEEPER_TAG),0);
253	250	return;
254	251	}
255	252
256	253	if(data & 0x80)
257	254	{
258		if(state->m_speaker_active)
259		beep_set_state(space->machine().device(BEEPER_TAG),1);
	255	if(m_speaker_active)
	256	beep_set_state(machine().device(BEEPER_TAG),1);
260	257	}
261	258	else
262		beep_set_state(space->machine().device(BEEPER_TAG),0);
	259	beep_set_state(machine().device(BEEPER_TAG),0);
263	260
264	261	if(data & 0x40)
265	262	{
266		if(state->m_speaker_active)
	263	if(m_speaker_active)
267	264	{
268		beep_set_state(space->machine().device(BEEPER_TAG),1);
	265	beep_set_state(machine().device(BEEPER_TAG),1);
269	266	logerror("timed beeper on\n");
270		space->machine().scheduler().timer_set(attotime::from_msec(205), FUNC(fm7_beeper_off));
	267	machine().scheduler().timer_set(attotime::from_msec(205), FUNC(fm7_beeper_off));
271	268	}
272	269	}
273	270	logerror("beeper state: %02x\n",data);
r14963	r14964
278	275	*  Sub CPU: port 0xd403 (read-only)
279	276	*  On read: timed buzzer sound
280	277	*/
281		READ8_HANDLER( fm7_sub_beeper_r )
	278	READ8_MEMBER(fm7_state::fm7_sub_beeper_r)
282	279	{
283		fm7_state *state = space->machine().driver_data<fm7_state>();
284		if(state->m_speaker_active)
	280	if(m_speaker_active)
285	281	{
286		beep_set_state(space->machine().device(BEEPER_TAG),1);
	282	beep_set_state(machine().device(BEEPER_TAG),1);
287	283	logerror("timed beeper on\n");
288		space->machine().scheduler().timer_set(attotime::from_msec(205), FUNC(fm7_beeper_off));
	284	machine().scheduler().timer_set(attotime::from_msec(205), FUNC(fm7_beeper_off));
289	285	}
290	286	return 0xff;
291	287	}
292	288
293		static READ8_HANDLER( vector_r )
	289	READ8_MEMBER(fm7_state::vector_r)
294	290	{
295		fm7_state *state = space->machine().driver_data<fm7_state>();
296		UINT8* RAM = space->machine().region("maincpu")->base();
297		UINT8* ROM = space->machine().region("init")->base();
	291	UINT8* RAM = machine().region("maincpu")->base();
	292	UINT8* ROM = machine().region("init")->base();
298	293
299		if(state->m_init_rom_en)
	294	if(m_init_rom_en)
300	295	return ROM[0x1ff0+offset];
301	296	else
302	297	{
303		if(state->m_type == SYS_FM7)
	298	if(m_type == SYS_FM7)
304	299	return RAM[0xfff0+offset];
305	300	else
306	301	return RAM[0x3fff0+offset];
307	302	}
308	303	}
309	304
310		static WRITE8_HANDLER( vector_w )
	305	WRITE8_MEMBER(fm7_state::vector_w)
311	306	{
312		fm7_state *state = space->machine().driver_data<fm7_state>();
313		UINT8* RAM = space->machine().region("maincpu")->base();
	307	UINT8* RAM = machine().region("maincpu")->base();
314	308
315		if(state->m_type == SYS_FM7)
	309	if(m_type == SYS_FM7)
316	310	RAM[0xfff0+offset] = data;
317	311	else
318	312	RAM[0x3fff0+offset] = data;
r14963	r14964
324	318	*  bit 0 - attention IRQ active, clears flag when read.
325	319	*  bit 1 - break key active
326	320	*/
327		static READ8_HANDLER( fm7_fd04_r )
	321	READ8_MEMBER(fm7_state::fm7_fd04_r)
328	322	{
329		fm7_state *state = space->machine().driver_data<fm7_state>();
330	323	UINT8 ret = 0xff;
331	324
332		if(state->m_video.attn_irq != 0)
	325	if(m_video.attn_irq != 0)
333	326	{
334	327	ret &= ~0x01;
335		state->m_video.attn_irq = 0;
	328	m_video.attn_irq = 0;
336	329	}
337		if(state->m_break_flag != 0)
	330	if(m_break_flag != 0)
338	331	{
339	332	ret &= ~0x02;
340	333	}
r14963	r14964
347	340	*  On read, enables BASIC ROM at 0x8000 (default)
348	341	*  On write, disables BASIC ROM, enables RAM (if more than 32kB)
349	342	*/
350		static READ8_HANDLER( fm7_rom_en_r )
	343	READ8_MEMBER(fm7_state::fm7_rom_en_r)
351	344	{
352		fm7_state *state = space->machine().driver_data<fm7_state>();
353		UINT8* RAM = space->machine().region("maincpu")->base();
	345	UINT8* RAM = machine().region("maincpu")->base();
354	346
355		state->m_basic_rom_en = 1;
356		if(state->m_type == SYS_FM7)
	347	m_basic_rom_en = 1;
	348	if(m_type == SYS_FM7)
357	349	{
358		space->install_read_bank(0x8000,0xfbff,"bank1");
359		space->nop_write(0x8000,0xfbff);
360		memory_set_bankptr(space->machine(),"bank1",RAM+0x38000);
	350	space.install_read_bank(0x8000,0xfbff,"bank1");
	351	space.nop_write(0x8000,0xfbff);
	352	memory_set_bankptr(machine(),"bank1",RAM+0x38000);
361	353	}
362	354	else
363		fm7_mmr_refresh(space);
	355	fm7_mmr_refresh(&space);
364	356	logerror("BASIC ROM enabled\n");
365	357	return 0x00;
366	358	}
367	359
368		static WRITE8_HANDLER( fm7_rom_en_w )
	360	WRITE8_MEMBER(fm7_state::fm7_rom_en_w)
369	361	{
370		fm7_state *state = space->machine().driver_data<fm7_state>();
371		UINT8* RAM = space->machine().region("maincpu")->base();
	362	UINT8* RAM = machine().region("maincpu")->base();
372	363
373		state->m_basic_rom_en = 0;
374		if(state->m_type == SYS_FM7)
	364	m_basic_rom_en = 0;
	365	if(m_type == SYS_FM7)
375	366	{
376		space->install_readwrite_bank(0x8000,0xfbff,"bank1");
377		memory_set_bankptr(space->machine(),"bank1",RAM+0x8000);
	367	space.install_readwrite_bank(0x8000,0xfbff,"bank1");
	368	memory_set_bankptr(machine(),"bank1",RAM+0x8000);
378	369	}
379	370	else
380		fm7_mmr_refresh(space);
	371	fm7_mmr_refresh(&space);
381	372	logerror("BASIC ROM disabled\n");
382	373	}
383	374
r14963	r14964
387	378	*  Port is write-only.  Initiate ROM is on by default.
388	379	*
389	380	*/
390		static WRITE8_HANDLER( fm7_init_en_w )
	381	WRITE8_MEMBER(fm7_state::fm7_init_en_w)
391	382	{
392		fm7_state *state = space->machine().driver_data<fm7_state>();
393	383	if(data & 0x02)
394	384	{
395		state->m_init_rom_en = 0;
396		fm7_mmr_refresh(space);
	385	m_init_rom_en = 0;
	386	fm7_mmr_refresh(&space);
397	387	}
398	388	else
399	389	{
400		state->m_init_rom_en = 1;
401		fm7_mmr_refresh(space);
	390	m_init_rom_en = 1;
	391	fm7_mmr_refresh(&space);
402	392	}
403	393	}
404	394
r14963	r14964
418	408	drvstate->m_fdc_drq_flag = state;
419	409	}
420	410
421		static READ8_HANDLER( fm7_fdc_r )
	411	READ8_MEMBER(fm7_state::fm7_fdc_r)
422	412	{
423		fm7_state *state = space->machine().driver_data<fm7_state>();
424		device_t* dev = space->machine().device("fdc");
	413	device_t* dev = machine().device("fdc");
425	414	UINT8 ret = 0;
426	415
427	416	switch(offset)
r14963	r14964
435	424	case 3:
436	425	return wd17xx_data_r(dev,offset);
437	426	case 4:
438		return state->m_fdc_side | 0xfe;
	427	return m_fdc_side | 0xfe;
439	428	case 5:
440		return state->m_fdc_drive;
	429	return m_fdc_drive;
441	430	case 6:
442	431	// FM-7 always returns 0xff for this register
443	432	return 0xff;
444	433	case 7:
445		if(state->m_fdc_irq_flag != 0)
	434	if(m_fdc_irq_flag != 0)
446	435	ret |= 0x40;
447		if(state->m_fdc_drq_flag != 0)
	436	if(m_fdc_drq_flag != 0)
448	437	ret |= 0x80;
449	438	return ret;
450	439	}
r14963	r14964
453	442	return 0x00;
454	443	}
455	444
456		static WRITE8_HANDLER( fm7_fdc_w )
	445	WRITE8_MEMBER(fm7_state::fm7_fdc_w)
457	446	{
458		fm7_state *state = space->machine().driver_data<fm7_state>();
459		device_t* dev = space->machine().device("fdc");
	447	device_t* dev = machine().device("fdc");
460	448	switch(offset)
461	449	{
462	450	case 0:
r14963	r14964
472	460	wd17xx_data_w(dev,offset,data);
473	461	break;
474	462	case 4:
475		state->m_fdc_side = data & 0x01;
	463	m_fdc_side = data & 0x01;
476	464	wd17xx_set_side(dev,data & 0x01);
477	465	logerror("FDC: wrote %02x to 0x%04x (side)\n",data,offset+0xfd18);
478	466	break;
479	467	case 5:
480		state->m_fdc_drive = data;
	468	m_fdc_drive = data;
481	469	if((data & 0x03) > 0x01)
482	470	{
483		state->m_fdc_drive = 0;
	471	m_fdc_drive = 0;
484	472	}
485	473	else
486	474	{
487	475	wd17xx_set_drive(dev,data & 0x03);
488		floppy_mon_w(floppy_get_device(space->machine(), data & 0x03), !BIT(data, 7));
489		floppy_drive_set_ready_state(floppy_get_device(space->machine(), data & 0x03), data & 0x80,0);
	476	floppy_mon_w(floppy_get_device(machine(), data & 0x03), !BIT(data, 7));
	477	floppy_drive_set_ready_state(floppy_get_device(machine(), data & 0x03), data & 0x80,0);
490	478	logerror("FDC: wrote %02x to 0x%04x (drive)\n",data,offset+0xfd18);
491	479	}
492	480	break;
r14963	r14964
510	498	*  CPU clock speed in bit 0 (0 = 1.2MHz, 1 = 2MHz)
511	499	*  Clears keyboard IRQ flag
512	500	*/
513		static READ8_HANDLER( fm7_keyboard_r )
	501	READ8_MEMBER(fm7_state::fm7_keyboard_r)
514	502	{
515		fm7_state *state = space->machine().driver_data<fm7_state>();
516	503	UINT8 ret;
517	504	switch(offset)
518	505	{
519	506	case 0:
520		ret = (state->m_current_scancode >> 1) & 0x80;
	507	ret = (m_current_scancode >> 1) & 0x80;
521	508	ret |= 0x01; // 1 = 2MHz, 0 = 1.2MHz
522	509	return ret;
523	510	case 1:
524		main_irq_clear_flag(space->machine(),IRQ_FLAG_KEY);
525		return state->m_current_scancode & 0xff;
	511	main_irq_clear_flag(machine(),IRQ_FLAG_KEY);
	512	return m_current_scancode & 0xff;
526	513	default:
527	514	return 0x00;
528	515	}
529	516	}
530	517
531		READ8_HANDLER( fm7_sub_keyboard_r )
	518	READ8_MEMBER(fm7_state::fm7_sub_keyboard_r)
532	519	{
533		fm7_state *state = space->machine().driver_data<fm7_state>();
534	520	UINT8 ret;
535	521	switch(offset)
536	522	{
537	523	case 0:
538		ret = (state->m_current_scancode >> 1) & 0x80;
	524	ret = (m_current_scancode >> 1) & 0x80;
539	525	return ret;
540	526	case 1:
541		main_irq_clear_flag(space->machine(),IRQ_FLAG_KEY);
542		return state->m_current_scancode & 0xff;
	527	main_irq_clear_flag(machine(),IRQ_FLAG_KEY);
	528	return m_current_scancode & 0xff;
543	529	default:
544	530	return 0x00;
545	531	}
r14963	r14964
570	556	*
571	557	*  ACK is received after 5us.
572	558	*/
573		READ8_HANDLER( fm77av_key_encoder_r )
	559	READ8_MEMBER(fm7_state::fm77av_key_encoder_r)
574	560	{
575		fm7_state *state = space->machine().driver_data<fm7_state>();
576	561	UINT8 ret = 0xff;
577	562	switch(offset)
578	563	{
579	564	case 0x00:  // data register
580		if(state->m_encoder.rx_count > 0)
	565	if(m_encoder.rx_count > 0)
581	566	{
582		ret = state->m_encoder.buffer[state->m_encoder.position];
583		state->m_encoder.position++;
584		state->m_encoder.rx_count--;
585		state->m_encoder.latch = 0;
	567	ret = m_encoder.buffer[m_encoder.position];
	568	m_encoder.position++;
	569	m_encoder.rx_count--;
	570	m_encoder.latch = 0;
586	571	}
587		if(state->m_encoder.rx_count > 0)
588		state->m_encoder.latch = 1;  // more data to receive
	572	if(m_encoder.rx_count > 0)
	573	m_encoder.latch = 1;  // more data to receive
589	574	break;
590	575	case 0x01:  // status register
591		if(state->m_encoder.latch != 0)
	576	if(m_encoder.latch != 0)
592	577	ret &= ~0x80;
593		if(state->m_encoder.ack == 0)
	578	if(m_encoder.ack == 0)
594	579	ret &= ~0x01;
595	580	break;
596	581	}
r14963	r14964
598	583	return ret;
599	584	}
600	585
601		static void fm77av_encoder_setup_command(fm7_state *state)
	586	void fm7_state::fm77av_encoder_setup_command()
602	587	{
603		switch(state->m_encoder.buffer[0])
	588	switch(m_encoder.buffer[0])
604	589	{
605	590	case 0:  // set scancode format
606		state->m_encoder.tx_count = 2;
	591	m_encoder.tx_count = 2;
607	592	break;
608	593	case 1:  // get scancode format
609		state->m_encoder.tx_count = 1;
	594	m_encoder.tx_count = 1;
610	595	break;
611	596	case 2:  // set LED
612		state->m_encoder.tx_count = 2;
	597	m_encoder.tx_count = 2;
613	598	break;
614	599	case 3:  // get LED
615		state->m_encoder.tx_count = 1;
	600	m_encoder.tx_count = 1;
616	601	break;
617	602	case 4:  // enable repeat
618		state->m_encoder.tx_count = 2;
	603	m_encoder.tx_count = 2;
619	604	break;
620	605	case 5:  // set repeat rate
621		state->m_encoder.tx_count = 3;
	606	m_encoder.tx_count = 3;
622	607	break;
623	608	case 0x80:  // get/set RTC (at least two bytes, 9 if byte two = 0x01)
624		state->m_encoder.tx_count = 2;
	609	m_encoder.tx_count = 2;
625	610	break;
626	611	case 0x81:  // digitise
627		state->m_encoder.tx_count = 2;
	612	m_encoder.tx_count = 2;
628	613	break;
629	614	case 0x82:  // set screen mode
630		state->m_encoder.tx_count = 2;
	615	m_encoder.tx_count = 2;
631	616	break;
632	617	case 0x83:  // get screen mode
633		state->m_encoder.tx_count = 1;
	618	m_encoder.tx_count = 1;
634	619	break;
635	620	case 0x84:  // set monitor brightness
636		state->m_encoder.tx_count = 2;
	621	m_encoder.tx_count = 2;
637	622	break;
638	623	default:
639		state->m_encoder.tx_count = 0;
640		state->m_encoder.rx_count = 0;
641		state->m_encoder.position = 0;
642		logerror("ENC: Unknown command 0x%02x sent, ignoring\n",state->m_encoder.buffer[0]);
	624	m_encoder.tx_count = 0;
	625	m_encoder.rx_count = 0;
	626	m_encoder.position = 0;
	627	logerror("ENC: Unknown command 0x%02x sent, ignoring\n",m_encoder.buffer[0]);
643	628	}
644	629	}
645	630
r14963	r14964
649	634	state->m_encoder.ack = 1;
650	635	}
651	636
652		static void fm77av_encoder_handle_command(fm7_state *state)
	637	void fm7_state::fm77av_encoder_handle_command()
653	638	{
654		switch(state->m_encoder.buffer[0])
	639	switch(m_encoder.buffer[0])
655	640	{
656	641	case 0:  // set keyboard scancode mode
657		state->m_key_scan_mode = state->m_encoder.buffer[1];
658		state->m_encoder.rx_count = 0;
659		logerror("ENC: Keyboard set to mode %i\n",state->m_encoder.buffer[1]);
	642	m_key_scan_mode = m_encoder.buffer[1];
	643	m_encoder.rx_count = 0;
	644	logerror("ENC: Keyboard set to mode %i\n",m_encoder.buffer[1]);
660	645	break;
661	646	case 1:  // get keyboard scancode mode
662		state->m_encoder.buffer[0] = state->m_key_scan_mode;
663		state->m_encoder.rx_count = 1;
664		logerror("ENC: Command %02x received\n",state->m_encoder.buffer[0]);
	647	m_encoder.buffer[0] = m_key_scan_mode;
	648	m_encoder.rx_count = 1;
	649	logerror("ENC: Command %02x received\n",m_encoder.buffer[0]);
665	650	break;
666	651	case 2:  // set LEDs
667		state->m_encoder.rx_count = 0;
668		logerror("ENC: Command %02x received\n",state->m_encoder.buffer[0]);
	652	m_encoder.rx_count = 0;
	653	logerror("ENC: Command %02x received\n",m_encoder.buffer[0]);
669	654	break;
670	655	case 3:  // get LEDs
671		state->m_encoder.rx_count = 1;
672		logerror("ENC: Command %02x received\n",state->m_encoder.buffer[0]);
	656	m_encoder.rx_count = 1;
	657	logerror("ENC: Command %02x received\n",m_encoder.buffer[0]);
673	658	break;
674	659	case 4:  // enable key repeat
675		state->m_encoder.rx_count = 0;
676		logerror("ENC: Command %02x received\n",state->m_encoder.buffer[0]);
	660	m_encoder.rx_count = 0;
	661	logerror("ENC: Command %02x received\n",m_encoder.buffer[0]);
677	662	break;
678	663	case 5:  // set key repeat rate
679		state->m_key_repeat = state->m_encoder.buffer[2] * 10;
680		state->m_key_delay = state->m_encoder.buffer[1] * 10;
681		state->m_encoder.rx_count = 0;
682		logerror("ENC: Keyboard repeat rate set to %i/%i\n",state->m_encoder.buffer[1],state->m_encoder.buffer[2]);
	664	m_key_repeat = m_encoder.buffer[2] * 10;
	665	m_key_delay = m_encoder.buffer[1] * 10;
	666	m_encoder.rx_count = 0;
	667	logerror("ENC: Keyboard repeat rate set to %i/%i\n",m_encoder.buffer[1],m_encoder.buffer[2]);
683	668	break;
684	669	case 0x80:  // get/set RTC
685		if(state->m_encoder.buffer[1] == 0x01)
686		state->m_encoder.rx_count = 0;
	670	if(m_encoder.buffer[1] == 0x01)
	671	m_encoder.rx_count = 0;
687	672	else
688		state->m_encoder.rx_count = 7;
689		logerror("ENC: Command %02x %02x received\n",state->m_encoder.buffer[0],state->m_encoder.buffer[1]);
	673	m_encoder.rx_count = 7;
	674	logerror("ENC: Command %02x %02x received\n",m_encoder.buffer[0],m_encoder.buffer[1]);
690	675	break;
691	676	case 0x81:  // digitise
692		state->m_encoder.rx_count = 0;
693		logerror("ENC: Command %02x received\n",state->m_encoder.buffer[0]);
	677	m_encoder.rx_count = 0;
	678	logerror("ENC: Command %02x received\n",m_encoder.buffer[0]);
694	679	break;
695	680	case 0x82:  // set screen mode
696		state->m_encoder.rx_count = 0;
697		logerror("ENC: Command %02x received\n",state->m_encoder.buffer[0]);
	681	m_encoder.rx_count = 0;
	682	logerror("ENC: Command %02x received\n",m_encoder.buffer[0]);
698	683	break;
699	684	case 0x83:  // get screen mode
700		state->m_encoder.rx_count = 1;
701		logerror("ENC: Command %02x received\n",state->m_encoder.buffer[0]);
	685	m_encoder.rx_count = 1;
	686	logerror("ENC: Command %02x received\n",m_encoder.buffer[0]);
702	687	break;
703	688	case 0x84:  // set monitor brightness
704		state->m_encoder.rx_count = 0;
705		logerror("ENC: Command %02x received\n",state->m_encoder.buffer[0]);
	689	m_encoder.rx_count = 0;
	690	logerror("ENC: Command %02x received\n",m_encoder.buffer[0]);
706	691	break;
707	692	}
708		state->m_encoder.position = 0;
	693	m_encoder.position = 0;
709	694	}
710	695
711		WRITE8_HANDLER( fm77av_key_encoder_w )
	696	WRITE8_MEMBER(fm7_state::fm77av_key_encoder_w)
712	697	{
713		fm7_state *state = space->machine().driver_data<fm7_state>();
714		state->m_encoder.ack = 0;
	698	m_encoder.ack = 0;
715	699	if(offset == 0) // data register
716	700	{
717		if(state->m_encoder.position == 0)  // first byte
	701	if(m_encoder.position == 0)  // first byte
718	702	{
719		fm77av_encoder_setup_command(state);
	703	fm77av_encoder_setup_command();
720	704	}
721		if(state->m_encoder.position == 1)  // second byte
	705	if(m_encoder.position == 1)  // second byte
722	706	{
723		if(state->m_encoder.buffer[0] == 0x80 || state->m_encoder.buffer[1] == 0x01)
	707	if(m_encoder.buffer[0] == 0x80 || m_encoder.buffer[1] == 0x01)
724	708	{
725		state->m_encoder.tx_count = 8; // 80 01 command is 9 bytes
	709	m_encoder.tx_count = 8; // 80 01 command is 9 bytes
726	710	}
727	711	}
728		state->m_encoder.buffer[state->m_encoder.position] = data;
729		state->m_encoder.position++;
730		state->m_encoder.tx_count--;
731		if(state->m_encoder.tx_count == 0)  // last byte
732		fm77av_encoder_handle_command(state);
	712	m_encoder.buffer[m_encoder.position] = data;
	713	m_encoder.position++;
	714	m_encoder.tx_count--;
	715	if(m_encoder.tx_count == 0)  // last byte
	716	fm77av_encoder_handle_command();
733	717
734	718	// wait 5us to set ACK flag
735		space->machine().scheduler().timer_set(attotime::from_usec(5), FUNC(fm77av_encoder_ack));
	719	machine().scheduler().timer_set(attotime::from_usec(5), FUNC(fm77av_encoder_ack));
736	720
737		//logerror("ENC: write 0x%02x to data register, moved to pos %i\n",data,state->m_encoder.position);
	721	//logerror("ENC: write 0x%02x to data register, moved to pos %i\n",data,m_encoder.position);
738	722	}
739	723	}
740	724
741		static READ8_HANDLER( fm7_cassette_printer_r )
	725	READ8_MEMBER(fm7_state::fm7_cassette_printer_r)
742	726	{
743	727	// bit 7: cassette input
744	728	// bit 5: printer DET2
r14963	r14964
748	732	// bit 1: printer error
749	733	// bit 0: printer busy
750	734	UINT8 ret = 0x00;
751		double data = (space->machine().device<cassette_image_device>(CASSETTE_TAG)->input());
752		centronics_device* centronics = space->machine().device<centronics_device>("lpt");
	735	double data = (machine().device<cassette_image_device>(CASSETTE_TAG)->input());
	736	centronics_device* centronics = machine().device<centronics_device>("lpt");
753	737	UINT8 pdata;
754	738	int x;
755	739
756	740	if(data > 0.03)
757	741	ret |= 0x80;
758	742
759		if(space->machine().device<cassette_image_device>(CASSETTE_TAG)->get_state() & CASSETTE_MOTOR_DISABLED)
	743	if(machine().device<cassette_image_device>(CASSETTE_TAG)->get_state() & CASSETTE_MOTOR_DISABLED)
760	744	ret |= 0x80;  // cassette input is high when not in use.
761	745
762	746	ret |= 0x70;
763	747
764		if(input_port_read(space->machine(),"config") & 0x01)
	748	if(input_port_read(machine(),"config") & 0x01)
765	749	{
766	750	ret |= 0x0f;
767		pdata = centronics->read(*space, 0);
	751	pdata = centronics->read(space, 0);
768	752	for(x=0;x<6;x++)
769	753	{
770	754	if(~pdata & (1<<x))
771		if(input_port_read(space->machine(),"lptjoy") & (1 << x))
	755	if(input_port_read(machine(),"lptjoy") & (1 << x))
772	756	ret &= ~0x08;
773	757	}
774	758	}
775	759	else
776	760	{
777		device_image_interface *image = dynamic_cast<device_image_interface *>(space->machine().device("lpt:printer:printer"));
	761	device_image_interface *image = dynamic_cast<device_image_interface *>(machine().device("lpt:printer:printer"));
778	762	if(image->exists())
779	763	{
780	764	if(centronics->pe_r())
r14963	r14964
792	776	return ret;
793	777	}
794	778
795		static WRITE8_HANDLER( fm7_cassette_printer_w )
	779	WRITE8_MEMBER(fm7_state::fm7_cassette_printer_w)
796	780	{
797		fm7_state *state = space->machine().driver_data<fm7_state>();
798		centronics_device* centronics = space->machine().device<centronics_device>("lpt");
	781	centronics_device* centronics = machine().device<centronics_device>("lpt");
799	782	switch(offset)
800	783	{
801	784	case 0:
r14963	r14964
803	786	// bit 6: printer strobe
804	787	// bit 1: cassette motor
805	788	// bit 0: cassette output
806		if((data & 0x01) != (state->m_cp_prev & 0x01))
807		space->machine().device<cassette_image_device>(CASSETTE_TAG)->output((data & 0x01) ? +1.0 : -1.0);
808		if((data & 0x02) != (state->m_cp_prev & 0x02))
809		space->machine().device<cassette_image_device>(CASSETTE_TAG)->change_state((data & 0x02) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
	789	if((data & 0x01) != (m_cp_prev & 0x01))
	790	machine().device<cassette_image_device>(CASSETTE_TAG)->output((data & 0x01) ? +1.0 : -1.0);
	791	if((data & 0x02) != (m_cp_prev & 0x02))
	792	machine().device<cassette_image_device>(CASSETTE_TAG)->change_state((data & 0x02) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
810	793	centronics->strobe_w(!(data & 0x40));
811		state->m_cp_prev = data;
	794	m_cp_prev = data;
812	795	break;
813	796	case 1:
814	797	// Printer data
815		centronics->write(*space,0,data);
	798	centronics->write(space,0,data);
816	799	break;
817	800	}
818	801	}
r14963	r14964
821	804	*  Main CPU: 0xfd0b
822	805	*   - bit 0: Boot mode: 0=BASIC, 1=DOS
823	806	*/
824		static READ8_HANDLER( fm77av_boot_mode_r )
	807	READ8_MEMBER(fm7_state::fm77av_boot_mode_r)
825	808	{
826	809	UINT8 ret = 0xff;
827	810
828		if(input_port_read(space->machine(),"DSW") & 0x02)
	811	if(input_port_read(machine(),"DSW") & 0x02)
829	812	ret &= ~0x01;
830	813
831	814	return 0xff;
r14963	r14964
897	880	}
898	881	}
899	882
900		static READ8_HANDLER( fm7_psg_select_r )
	883	READ8_MEMBER(fm7_state::fm7_psg_select_r)
901	884	{
902	885	return 0xff;
903	886	}
904	887
905		static WRITE8_HANDLER( fm7_psg_select_w )
	888	WRITE8_MEMBER(fm7_state::fm7_psg_select_w)
906	889	{
907		fm7_state *state = space->machine().driver_data<fm7_state>();
908		state->m_psg_regsel = data & 0x03;
909		fm7_update_psg(space->machine());
	890	m_psg_regsel = data & 0x03;
	891	fm7_update_psg(machine());
910	892	}
911	893
912		static WRITE8_HANDLER( fm77av_ym_select_w )
	894	WRITE8_MEMBER(fm7_state::fm77av_ym_select_w)
913	895	{
914		fm7_state *state = space->machine().driver_data<fm7_state>();
915		state->m_psg_regsel = data & 0x0f;
916		fm7_update_psg(space->machine());
	896	m_psg_regsel = data & 0x0f;
	897	fm7_update_psg(machine());
917	898	}
918	899
919		static READ8_HANDLER( fm7_psg_data_r )
	900	READ8_MEMBER(fm7_state::fm7_psg_data_r)
920	901	{
921		fm7_state *state = space->machine().driver_data<fm7_state>();
922		//  fm7_update_psg(space->machine());
923		return state->m_psg_data;
	902	//  fm7_update_psg(machine());
	903	return m_psg_data;
924	904	}
925	905
926		static WRITE8_HANDLER( fm7_psg_data_w )
	906	WRITE8_MEMBER(fm7_state::fm7_psg_data_w)
927	907	{
928		fm7_state *state = space->machine().driver_data<fm7_state>();
929		state->m_psg_data = data;
930		//  fm7_update_psg(space->machine());
	908	m_psg_data = data;
	909	//  fm7_update_psg(machine());
931	910	}
932	911
933		static WRITE8_HANDLER( fm77av_bootram_w )
	912	WRITE8_MEMBER(fm7_state::fm77av_bootram_w)
934	913	{
935		fm7_state *state = space->machine().driver_data<fm7_state>();
936		if(!(state->m_mmr.mode & 0x01))
	914	if(!(m_mmr.mode & 0x01))
937	915	return;
938		state->m_boot_ram[offset] = data;
	916	m_boot_ram[offset] = data;
939	917	}
940	918
941	919	// Shared RAM is only usable on the main CPU if the sub CPU is halted
942		static READ8_HANDLER( fm7_main_shared_r )
	920	READ8_MEMBER(fm7_state::fm7_main_shared_r)
943	921	{
944		fm7_state *state = space->machine().driver_data<fm7_state>();
945		if(state->m_video.sub_halt != 0)
946		return state->m_shared_ram[offset];
	922	if(m_video.sub_halt != 0)
	923	return m_shared_ram[offset];
947	924	else
948	925	return 0xff;
949	926	}
950	927
951		static WRITE8_HANDLER( fm7_main_shared_w )
	928	WRITE8_MEMBER(fm7_state::fm7_main_shared_w)
952	929	{
953		fm7_state *state = space->machine().driver_data<fm7_state>();
954		if(state->m_video.sub_halt != 0)
955		state->m_shared_ram[offset] = data;
	930	if(m_video.sub_halt != 0)
	931	m_shared_ram[offset] = data;
956	932	}
957	933
958		static READ8_HANDLER( fm7_fmirq_r )
	934	READ8_MEMBER(fm7_state::fm7_fmirq_r)
959	935	{
960		fm7_state *state = space->machine().driver_data<fm7_state>();
961	936	UINT8 ret = 0xff;
962	937
963		if(state->m_fm77av_ym_irq != 0)
	938	if(m_fm77av_ym_irq != 0)
964	939	ret &= ~0x08;
965	940
966	941	return ret;
r14963	r14964
976	951	return input_port_read(device->machine(),"joy2");
977	952	}
978	953
979		static READ8_HANDLER( fm7_unknown_r )
	954	READ8_MEMBER(fm7_state::fm7_unknown_r)
980	955	{
981	956	// Port 0xFDFC is read by Dig Dug.  Controller port, perhaps?
982	957	// Must return 0xff for it to read the keyboard.
r14963	r14964
999	974	*              - bit 0: boot RAM read-write/read-only
1000	975	*
1001	976	*/
1002		static READ8_HANDLER( fm7_mmr_r )
	977	READ8_MEMBER(fm7_state::fm7_mmr_r)
1003	978	{
1004		fm7_state *state = space->machine().driver_data<fm7_state>();
1005	979	if(offset < 0x10)
1006	980	{
1007		return state->m_mmr.bank_addr[state->m_mmr.segment][offset];
	981	return m_mmr.bank_addr[m_mmr.segment][offset];
1008	982	}
1009	983	if(offset == 0x13)
1010		return state->m_mmr.mode;
	984	return m_mmr.mode;
1011	985	return 0xff;
1012	986	}
1013	987
r14963	r14964
1028	1002	switch(physical)
1029	1003	{
1030	1004	case 0x10:
1031		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram0_r),FUNC(fm7_vram0_w));
	1005	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram0_r),state),write8_delegate(FUNC(fm7_state::fm7_vram0_w),state));
1032	1006	break;
1033	1007	case 0x11:
1034		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram1_r),FUNC(fm7_vram1_w));
	1008	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram1_r),state),write8_delegate(FUNC(fm7_state::fm7_vram1_w),state));
1035	1009	break;
1036	1010	case 0x12:
1037		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram2_r),FUNC(fm7_vram2_w));
	1011	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram2_r),state),write8_delegate(FUNC(fm7_state::fm7_vram2_w),state));
1038	1012	break;
1039	1013	case 0x13:
1040		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram3_r),FUNC(fm7_vram3_w));
	1014	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram3_r),state),write8_delegate(FUNC(fm7_state::fm7_vram3_w),state));
1041	1015	break;
1042	1016	case 0x14:
1043		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram4_r),FUNC(fm7_vram4_w));
	1017	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram4_r),state),write8_delegate(FUNC(fm7_state::fm7_vram4_w),state));
1044	1018	break;
1045	1019	case 0x15:
1046		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram5_r),FUNC(fm7_vram5_w));
	1020	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram5_r),state),write8_delegate(FUNC(fm7_state::fm7_vram5_w),state));
1047	1021	break;
1048	1022	case 0x16:
1049		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram6_r),FUNC(fm7_vram6_w));
	1023	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram6_r),state),write8_delegate(FUNC(fm7_state::fm7_vram6_w),state));
1050	1024	break;
1051	1025	case 0x17:
1052		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram7_r),FUNC(fm7_vram7_w));
	1026	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram7_r),state),write8_delegate(FUNC(fm7_state::fm7_vram7_w),state));
1053	1027	break;
1054	1028	case 0x18:
1055		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram8_r),FUNC(fm7_vram8_w));
	1029	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram8_r),state),write8_delegate(FUNC(fm7_state::fm7_vram8_w),state));
1056	1030	break;
1057	1031	case 0x19:
1058		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vram9_r),FUNC(fm7_vram9_w));
	1032	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram9_r),state),write8_delegate(FUNC(fm7_state::fm7_vram9_w),state));
1059	1033	break;
1060	1034	case 0x1a:
1061		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vramA_r),FUNC(fm7_vramA_w));
	1035	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramA_r),state),write8_delegate(FUNC(fm7_state::fm7_vramA_w),state));
1062	1036	break;
1063	1037	case 0x1b:
1064		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_vramB_r),FUNC(fm7_vramB_w));
	1038	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramB_r),state),write8_delegate(FUNC(fm7_state::fm7_vramB_w),state));
1065	1039	break;
1066	1040	}
1067	1041	//      memory_set_bankptr(space->machine(),bank+1,RAM+(physical<<12)-0x10000);
r14963	r14964
1069	1043	}
1070	1044	if(physical == 0x1c)
1071	1045	{
1072		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_console_ram_banked_r),FUNC(fm7_console_ram_banked_w));
	1046	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_console_ram_banked_r),state),write8_delegate(FUNC(fm7_state::fm7_console_ram_banked_w),state));
1073	1047	return;
1074	1048	}
1075	1049	if(physical == 0x1d)
1076	1050	{
1077		space->install_legacy_readwrite_handler(bank*0x1000,(bank*0x1000)+size,FUNC(fm7_sub_ram_ports_banked_r),FUNC(fm7_sub_ram_ports_banked_w));
	1051	space->install_readwrite_handler(bank*0x1000,(bank*0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_r),state),write8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_w),state));
1078	1052	return;
1079	1053	}
1080	1054	if(physical == 0x35)
r14963	r14964
1147	1121	}
1148	1122	}
1149	1123
1150		static WRITE8_HANDLER( fm7_mmr_w )
	1124	WRITE8_MEMBER(fm7_state::fm7_mmr_w)
1151	1125	{
1152		fm7_state *state = space->machine().driver_data<fm7_state>();
1153	1126	if(offset < 0x10)
1154	1127	{
1155		state->m_mmr.bank_addr[state->m_mmr.segment][offset] = data;
1156		if(state->m_mmr.enabled)
1157		fm7_update_bank(space,offset,data);
1158		logerror("MMR: Segment %i, bank %i, set to  0x%02x\n",state->m_mmr.segment,offset,data);
	1128	m_mmr.bank_addr[m_mmr.segment][offset] = data;
	1129	if(m_mmr.enabled)
	1130	fm7_update_bank(&space,offset,data);
	1131	logerror("MMR: Segment %i, bank %i, set to  0x%02x\n",m_mmr.segment,offset,data);
1159	1132	return;
1160	1133	}
1161	1134	switch(offset)
1162	1135	{
1163	1136	case 0x10:
1164		state->m_mmr.segment = data & 0x07;
1165		fm7_mmr_refresh(space);
1166		logerror("MMR: Active segment set to %i\n",state->m_mmr.segment);
	1137	m_mmr.segment = data & 0x07;
	1138	fm7_mmr_refresh(&space);
	1139	logerror("MMR: Active segment set to %i\n",m_mmr.segment);
1167	1140	break;
1168	1141	case 0x12:
1169		state->m_mmr.window_offset = data;
1170		fm7_mmr_refresh(space);
	1142	m_mmr.window_offset = data;
	1143	fm7_mmr_refresh(&space);
1171	1144	logerror("MMR: Window offset set to %02x\n",data);
1172	1145	break;
1173	1146	case 0x13:
1174		state->m_mmr.mode = data;
1175		state->m_mmr.enabled = data & 0x80;
1176		fm7_mmr_refresh(space);
	1147	m_mmr.mode = data;
	1148	m_mmr.enabled = data & 0x80;
	1149	fm7_mmr_refresh(&space);
1177	1150	logerror("MMR: Mode register set to %02x\n",data);
1178	1151	break;
1179	1152	}
r14963	r14964
1189	1162	*
1190	1163	*  Kanji ROM is visible at 0x20000 (first half only?)
1191	1164	*/
1192		static READ8_HANDLER( fm7_kanji_r )
	1165	READ8_MEMBER(fm7_state::fm7_kanji_r)
1193	1166	{
1194		fm7_state *state = space->machine().driver_data<fm7_state>();
1195		UINT8* KROM = space->machine().region("kanji1")->base();
1196		UINT32 addr = state->m_kanji_address << 1;
	1167	UINT8* KROM = machine().region("kanji1")->base();
	1168	UINT32 addr = m_kanji_address << 1;
1197	1169
1198	1170	switch(offset)
1199	1171	{
r14963	r14964
1211	1183	}
1212	1184	}
1213	1185
1214		static WRITE8_HANDLER( fm7_kanji_w )
	1186	WRITE8_MEMBER(fm7_state::fm7_kanji_w)
1215	1187	{
1216		fm7_state *state = space->machine().driver_data<fm7_state>();
1217	1188	UINT16 addr;
1218	1189
1219	1190	switch(offset)
1220	1191	{
1221	1192	case 0:
1222		addr = ((data & 0xff) << 8) | (state->m_kanji_address & 0x00ff);
1223		state->m_kanji_address = addr;
	1193	addr = ((data & 0xff) << 8) | (m_kanji_address & 0x00ff);
	1194	m_kanji_address = addr;
1224	1195	break;
1225	1196	case 1:
1226		addr = (data & 0xff) | (state->m_kanji_address & 0xff00);
1227		state->m_kanji_address = addr;
	1197	addr = (data & 0xff) | (m_kanji_address & 0xff00);
	1198	m_kanji_address = addr;
1228	1199	break;
1229	1200	case 2:
1230	1201	case 3:
r14963	r14964
1416	1387	AM_RANGE(0x0000,0x7fff) AM_RAM
1417	1388	AM_RANGE(0x8000,0xfbff) AM_ROMBANK("bank1") // also F-BASIC ROM, when enabled
1418	1389	AM_RANGE(0xfc00,0xfc7f) AM_RAM
1419		AM_RANGE(0xfc80,0xfcff) AM_READWRITE_LEGACY(fm7_main_shared_r,fm7_main_shared_w)
	1390	AM_RANGE(0xfc80,0xfcff) AM_READWRITE(fm7_main_shared_r,fm7_main_shared_w)
1420	1391	// I/O space (FD00-FDFF)
1421		AM_RANGE(0xfd00,0xfd01) AM_READWRITE_LEGACY(fm7_keyboard_r,fm7_cassette_printer_w)
1422		AM_RANGE(0xfd02,0xfd02) AM_READWRITE_LEGACY(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
1423		AM_RANGE(0xfd03,0xfd03) AM_READWRITE_LEGACY(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
1424		AM_RANGE(0xfd04,0xfd04) AM_READ_LEGACY(fm7_fd04_r)
1425		AM_RANGE(0xfd05,0xfd05) AM_READWRITE_LEGACY(fm7_subintf_r,fm7_subintf_w)
1426		AM_RANGE(0xfd06,0xfd0c) AM_READ_LEGACY(fm7_unknown_r)
1427		AM_RANGE(0xfd0d,0xfd0d) AM_READWRITE_LEGACY(fm7_psg_select_r,fm7_psg_select_w)
1428		AM_RANGE(0xfd0e,0xfd0e) AM_READWRITE_LEGACY(fm7_psg_data_r, fm7_psg_data_w)
1429		AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE_LEGACY(fm7_rom_en_r,fm7_rom_en_w)
1430		AM_RANGE(0xfd10,0xfd17) AM_READ_LEGACY(fm7_unknown_r)
1431		AM_RANGE(0xfd18,0xfd1f) AM_READWRITE_LEGACY(fm7_fdc_r,fm7_fdc_w)
1432		AM_RANGE(0xfd20,0xfd23) AM_READWRITE_LEGACY(fm7_kanji_r,fm7_kanji_w)
1433		AM_RANGE(0xfd24,0xfd36) AM_READ_LEGACY(fm7_unknown_r)
1434		AM_RANGE(0xfd37,0xfd37) AM_WRITE_LEGACY(fm7_multipage_w)
1435		AM_RANGE(0xfd38,0xfd3f) AM_READWRITE_LEGACY(fm7_palette_r,fm7_palette_w)
1436		AM_RANGE(0xfd40,0xfdff) AM_READ_LEGACY(fm7_unknown_r)
	1392	AM_RANGE(0xfd00,0xfd01) AM_READWRITE(fm7_keyboard_r,fm7_cassette_printer_w)
	1393	AM_RANGE(0xfd02,0xfd02) AM_READWRITE(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
	1394	AM_RANGE(0xfd03,0xfd03) AM_READWRITE(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
	1395	AM_RANGE(0xfd04,0xfd04) AM_READ(fm7_fd04_r)
	1396	AM_RANGE(0xfd05,0xfd05) AM_READWRITE(fm7_subintf_r,fm7_subintf_w)
	1397	AM_RANGE(0xfd06,0xfd0c) AM_READ(fm7_unknown_r)
	1398	AM_RANGE(0xfd0d,0xfd0d) AM_READWRITE(fm7_psg_select_r,fm7_psg_select_w)
	1399	AM_RANGE(0xfd0e,0xfd0e) AM_READWRITE(fm7_psg_data_r, fm7_psg_data_w)
	1400	AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE(fm7_rom_en_r,fm7_rom_en_w)
	1401	AM_RANGE(0xfd10,0xfd17) AM_READ(fm7_unknown_r)
	1402	AM_RANGE(0xfd18,0xfd1f) AM_READWRITE(fm7_fdc_r,fm7_fdc_w)
	1403	AM_RANGE(0xfd20,0xfd23) AM_READWRITE(fm7_kanji_r,fm7_kanji_w)
	1404	AM_RANGE(0xfd24,0xfd36) AM_READ(fm7_unknown_r)
	1405	AM_RANGE(0xfd37,0xfd37) AM_WRITE(fm7_multipage_w)
	1406	AM_RANGE(0xfd38,0xfd3f) AM_READWRITE(fm7_palette_r,fm7_palette_w)
	1407	AM_RANGE(0xfd40,0xfdff) AM_READ(fm7_unknown_r)
1437	1408	// Boot ROM
1438	1409	AM_RANGE(0xfe00,0xffdf) AM_ROMBANK("bank17")
1439	1410	AM_RANGE(0xffe0,0xffef) AM_RAM
1440		AM_RANGE(0xfff0,0xffff) AM_READWRITE_LEGACY(vector_r,vector_w)
	1411	AM_RANGE(0xfff0,0xffff) AM_READWRITE(vector_r,vector_w)
1441	1412	ADDRESS_MAP_END
1442	1413
1443	1414	static ADDRESS_MAP_START( fm8_mem, AS_PROGRAM, 8, fm7_state )
1444	1415	AM_RANGE(0x0000,0x7fff) AM_RAM
1445	1416	AM_RANGE(0x8000,0xfbff) AM_ROMBANK("bank1") // also F-BASIC ROM, when enabled
1446	1417	AM_RANGE(0xfc00,0xfc7f) AM_RAM
1447		AM_RANGE(0xfc80,0xfcff) AM_READWRITE_LEGACY(fm7_main_shared_r,fm7_main_shared_w)
	1418	AM_RANGE(0xfc80,0xfcff) AM_READWRITE(fm7_main_shared_r,fm7_main_shared_w)
1448	1419	// I/O space (FD00-FDFF)
1449		AM_RANGE(0xfd00,0xfd01) AM_READWRITE_LEGACY(fm7_keyboard_r,fm7_cassette_printer_w)
1450		AM_RANGE(0xfd02,0xfd02) AM_READWRITE_LEGACY(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
1451		AM_RANGE(0xfd03,0xfd03) AM_READWRITE_LEGACY(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
1452		AM_RANGE(0xfd04,0xfd04) AM_READ_LEGACY(fm7_fd04_r)
1453		AM_RANGE(0xfd05,0xfd05) AM_READWRITE_LEGACY(fm7_subintf_r,fm7_subintf_w)
1454		AM_RANGE(0xfd06,0xfd0c) AM_READ_LEGACY(fm7_unknown_r)
1455		AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE_LEGACY(fm7_rom_en_r,fm7_rom_en_w)
1456		AM_RANGE(0xfd10,0xfd17) AM_READ_LEGACY(fm7_unknown_r)
1457		AM_RANGE(0xfd18,0xfd1f) AM_READWRITE_LEGACY(fm7_fdc_r,fm7_fdc_w)
1458		AM_RANGE(0xfd20,0xfd23) AM_READWRITE_LEGACY(fm7_kanji_r,fm7_kanji_w)
1459		AM_RANGE(0xfd24,0xfd36) AM_READ_LEGACY(fm7_unknown_r)
1460		AM_RANGE(0xfd37,0xfd37) AM_WRITE_LEGACY(fm7_multipage_w)
1461		AM_RANGE(0xfd38,0xfd3f) AM_READWRITE_LEGACY(fm7_palette_r,fm7_palette_w)
1462		AM_RANGE(0xfd40,0xfdff) AM_READ_LEGACY(fm7_unknown_r)
	1420	AM_RANGE(0xfd00,0xfd01) AM_READWRITE(fm7_keyboard_r,fm7_cassette_printer_w)
	1421	AM_RANGE(0xfd02,0xfd02) AM_READWRITE(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
	1422	AM_RANGE(0xfd03,0xfd03) AM_READWRITE(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
	1423	AM_RANGE(0xfd04,0xfd04) AM_READ(fm7_fd04_r)
	1424	AM_RANGE(0xfd05,0xfd05) AM_READWRITE(fm7_subintf_r,fm7_subintf_w)
	1425	AM_RANGE(0xfd06,0xfd0c) AM_READ(fm7_unknown_r)
	1426	AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE(fm7_rom_en_r,fm7_rom_en_w)
	1427	AM_RANGE(0xfd10,0xfd17) AM_READ(fm7_unknown_r)
	1428	AM_RANGE(0xfd18,0xfd1f) AM_READWRITE(fm7_fdc_r,fm7_fdc_w)
	1429	AM_RANGE(0xfd20,0xfd23) AM_READWRITE(fm7_kanji_r,fm7_kanji_w)
	1430	AM_RANGE(0xfd24,0xfd36) AM_READ(fm7_unknown_r)
	1431	AM_RANGE(0xfd37,0xfd37) AM_WRITE(fm7_multipage_w)
	1432	AM_RANGE(0xfd38,0xfd3f) AM_READWRITE(fm7_palette_r,fm7_palette_w)
	1433	AM_RANGE(0xfd40,0xfdff) AM_READ(fm7_unknown_r)
1463	1434	// Boot ROM
1464	1435	AM_RANGE(0xfe00,0xffdf) AM_ROMBANK("bank17")
1465	1436	AM_RANGE(0xffe0,0xffef) AM_RAM
1466		AM_RANGE(0xfff0,0xffff) AM_READWRITE_LEGACY(vector_r,vector_w)
	1437	AM_RANGE(0xfff0,0xffff) AM_READWRITE(vector_r,vector_w)
1467	1438	ADDRESS_MAP_END
1468	1439
1469	1440	/*
r14963	r14964
1478	1449	*/
1479	1450
1480	1451	static ADDRESS_MAP_START( fm7_sub_mem, AS_PROGRAM, 8, fm7_state )
1481		AM_RANGE(0x0000,0xbfff) AM_READWRITE_LEGACY(fm7_vram_r,fm7_vram_w) // VRAM
	1452	AM_RANGE(0x0000,0xbfff) AM_READWRITE(fm7_vram_r,fm7_vram_w) // VRAM
1482	1453	AM_RANGE(0xc000,0xcfff) AM_RAM // Console RAM
1483	1454	AM_RANGE(0xd000,0xd37f) AM_RAM // Work RAM
1484	1455	AM_RANGE(0xd380,0xd3ff) AM_RAM AM_SHARE("shared_ram")
1485	1456	// I/O space (D400-D4FF)
1486		AM_RANGE(0xd400,0xd401) AM_READ_LEGACY(fm7_sub_keyboard_r)
1487		AM_RANGE(0xd402,0xd402) AM_READ_LEGACY(fm7_cancel_ack)
1488		AM_RANGE(0xd403,0xd403) AM_READ_LEGACY(fm7_sub_beeper_r)
1489		AM_RANGE(0xd404,0xd404) AM_READ_LEGACY(fm7_attn_irq_r)
1490		AM_RANGE(0xd408,0xd408) AM_READWRITE_LEGACY(fm7_crt_r,fm7_crt_w)
1491		AM_RANGE(0xd409,0xd409) AM_READWRITE_LEGACY(fm7_vram_access_r,fm7_vram_access_w)
1492		AM_RANGE(0xd40a,0xd40a) AM_READWRITE_LEGACY(fm7_sub_busyflag_r,fm7_sub_busyflag_w)
1493		AM_RANGE(0xd40e,0xd40f) AM_WRITE_LEGACY(fm7_vram_offset_w)
	1457	AM_RANGE(0xd400,0xd401) AM_READ(fm7_sub_keyboard_r)
	1458	AM_RANGE(0xd402,0xd402) AM_READ(fm7_cancel_ack)
	1459	AM_RANGE(0xd403,0xd403) AM_READ(fm7_sub_beeper_r)
	1460	AM_RANGE(0xd404,0xd404) AM_READ(fm7_attn_irq_r)
	1461	AM_RANGE(0xd408,0xd408) AM_READWRITE(fm7_crt_r,fm7_crt_w)
	1462	AM_RANGE(0xd409,0xd409) AM_READWRITE(fm7_vram_access_r,fm7_vram_access_w)
	1463	AM_RANGE(0xd40a,0xd40a) AM_READWRITE(fm7_sub_busyflag_r,fm7_sub_busyflag_w)
	1464	AM_RANGE(0xd40e,0xd40f) AM_WRITE(fm7_vram_offset_w)
1494	1465	AM_RANGE(0xd800,0xffff) AM_ROM
1495	1466	ADDRESS_MAP_END
1496	1467
r14963	r14964
1512	1483	AM_RANGE(0xe000,0xefff) AM_RAMBANK("bank15")
1513	1484	AM_RANGE(0xf000,0xfbff) AM_RAMBANK("bank16")
1514	1485	AM_RANGE(0xfc00,0xfc7f) AM_RAM
1515		AM_RANGE(0xfc80,0xfcff) AM_READWRITE_LEGACY(fm7_main_shared_r,fm7_main_shared_w)
	1486	AM_RANGE(0xfc80,0xfcff) AM_READWRITE(fm7_main_shared_r,fm7_main_shared_w)
1516	1487	// I/O space (FD00-FDFF)
1517		AM_RANGE(0xfd00,0xfd01) AM_READWRITE_LEGACY(fm7_keyboard_r,fm7_cassette_printer_w)
1518		AM_RANGE(0xfd02,0xfd02) AM_READWRITE_LEGACY(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
1519		AM_RANGE(0xfd03,0xfd03) AM_READWRITE_LEGACY(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
1520		AM_RANGE(0xfd04,0xfd04) AM_READ_LEGACY(fm7_fd04_r)
1521		AM_RANGE(0xfd05,0xfd05) AM_READWRITE_LEGACY(fm7_subintf_r,fm7_subintf_w)
1522		AM_RANGE(0xfd06,0xfd0a) AM_READ_LEGACY(fm7_unknown_r)
1523		AM_RANGE(0xfd0b,0xfd0b) AM_READ_LEGACY(fm77av_boot_mode_r)
1524		AM_RANGE(0xfd0c,0xfd0c) AM_READ_LEGACY(fm7_unknown_r)
1525		AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE_LEGACY(fm7_rom_en_r,fm7_rom_en_w)
1526		AM_RANGE(0xfd10,0xfd10) AM_WRITE_LEGACY(fm7_init_en_w)
1527		AM_RANGE(0xfd11,0xfd11) AM_READ_LEGACY(fm7_unknown_r)
1528		AM_RANGE(0xfd12,0xfd12) AM_READWRITE_LEGACY(fm77av_sub_modestatus_r,fm77av_sub_modestatus_w)
1529		AM_RANGE(0xfd13,0xfd13) AM_WRITE_LEGACY(fm77av_sub_bank_w)
1530		AM_RANGE(0xfd14,0xfd14) AM_READ_LEGACY(fm7_unknown_r)
1531		AM_RANGE(0xfd17,0xfd17) AM_READ_LEGACY(fm7_fmirq_r)
1532		AM_RANGE(0xfd18,0xfd1f) AM_READWRITE_LEGACY(fm7_fdc_r,fm7_fdc_w)
1533		AM_RANGE(0xfd20,0xfd23) AM_READWRITE_LEGACY(fm7_kanji_r,fm7_kanji_w)
1534		AM_RANGE(0xfd24,0xfd2b) AM_READ_LEGACY(fm7_unknown_r)
1535		AM_RANGE(0xfd30,0xfd34) AM_WRITE_LEGACY(fm77av_analog_palette_w)
1536		AM_RANGE(0xfd35,0xfd36) AM_READ_LEGACY(fm7_unknown_r)
1537		AM_RANGE(0xfd37,0xfd37) AM_WRITE_LEGACY(fm7_multipage_w)
1538		AM_RANGE(0xfd38,0xfd3f) AM_READWRITE_LEGACY(fm7_palette_r,fm7_palette_w)
1539		AM_RANGE(0xfd40,0xfd7f) AM_READ_LEGACY(fm7_unknown_r)
1540		AM_RANGE(0xfd80,0xfd93) AM_READWRITE_LEGACY(fm7_mmr_r,fm7_mmr_w)
1541		AM_RANGE(0xfd94,0xfdff) AM_READ_LEGACY(fm7_unknown_r)
1542		AM_RANGE(0xfe00,0xffdf) AM_RAM_WRITE_LEGACY(fm77av_bootram_w) AM_SHARE("boot_ram")
	1488	AM_RANGE(0xfd00,0xfd01) AM_READWRITE(fm7_keyboard_r,fm7_cassette_printer_w)
	1489	AM_RANGE(0xfd02,0xfd02) AM_READWRITE(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
	1490	AM_RANGE(0xfd03,0xfd03) AM_READWRITE(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
	1491	AM_RANGE(0xfd04,0xfd04) AM_READ(fm7_fd04_r)
	1492	AM_RANGE(0xfd05,0xfd05) AM_READWRITE(fm7_subintf_r,fm7_subintf_w)
	1493	AM_RANGE(0xfd06,0xfd0a) AM_READ(fm7_unknown_r)
	1494	AM_RANGE(0xfd0b,0xfd0b) AM_READ(fm77av_boot_mode_r)
	1495	AM_RANGE(0xfd0c,0xfd0c) AM_READ(fm7_unknown_r)
	1496	AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE(fm7_rom_en_r,fm7_rom_en_w)
	1497	AM_RANGE(0xfd10,0xfd10) AM_WRITE(fm7_init_en_w)
	1498	AM_RANGE(0xfd11,0xfd11) AM_READ(fm7_unknown_r)
	1499	AM_RANGE(0xfd12,0xfd12) AM_READWRITE(fm77av_sub_modestatus_r,fm77av_sub_modestatus_w)
	1500	AM_RANGE(0xfd13,0xfd13) AM_WRITE(fm77av_sub_bank_w)
	1501	AM_RANGE(0xfd14,0xfd14) AM_READ(fm7_unknown_r)
	1502	AM_RANGE(0xfd17,0xfd17) AM_READ(fm7_fmirq_r)
	1503	AM_RANGE(0xfd18,0xfd1f) AM_READWRITE(fm7_fdc_r,fm7_fdc_w)
	1504	AM_RANGE(0xfd20,0xfd23) AM_READWRITE(fm7_kanji_r,fm7_kanji_w)
	1505	AM_RANGE(0xfd24,0xfd2b) AM_READ(fm7_unknown_r)
	1506	AM_RANGE(0xfd30,0xfd34) AM_WRITE(fm77av_analog_palette_w)
	1507	AM_RANGE(0xfd35,0xfd36) AM_READ(fm7_unknown_r)
	1508	AM_RANGE(0xfd37,0xfd37) AM_WRITE(fm7_multipage_w)
	1509	AM_RANGE(0xfd38,0xfd3f) AM_READWRITE(fm7_palette_r,fm7_palette_w)
	1510	AM_RANGE(0xfd40,0xfd7f) AM_READ(fm7_unknown_r)
	1511	AM_RANGE(0xfd80,0xfd93) AM_READWRITE(fm7_mmr_r,fm7_mmr_w)
	1512	AM_RANGE(0xfd94,0xfdff) AM_READ(fm7_unknown_r)
	1513	AM_RANGE(0xfe00,0xffdf) AM_RAM_WRITE(fm77av_bootram_w) AM_SHARE("boot_ram")
1543	1514	AM_RANGE(0xffe0,0xffef) AM_RAM
1544		AM_RANGE(0xfff0,0xffff) AM_READWRITE_LEGACY(vector_r,vector_w)
	1515	AM_RANGE(0xfff0,0xffff) AM_READWRITE(vector_r,vector_w)
1545	1516	ADDRESS_MAP_END
1546	1517
1547	1518	// Much of this is guesswork at the moment
1548	1519	static ADDRESS_MAP_START( fm11_sub_mem, AS_PROGRAM, 8, fm7_state )
1549		AM_RANGE(0x0000,0x7fff) AM_READWRITE_LEGACY(fm7_vram_r,fm7_vram_w) // VRAM
	1520	AM_RANGE(0x0000,0x7fff) AM_READWRITE(fm7_vram_r,fm7_vram_w) // VRAM
1550	1521	AM_RANGE(0x8000,0x8fff) AM_RAM // Console RAM(?)
1551	1522	AM_RANGE(0x9000,0x9f7f) AM_RAM // Work RAM(?)
1552	1523	AM_RANGE(0x9f80,0x9fff) AM_RAM AM_SHARE("shared_ram")
1553		AM_RANGE(0xafe4,0xafe4) AM_READWRITE_LEGACY(fm7_sub_busyflag_r,fm7_sub_busyflag_w)
1554		AM_RANGE(0xafe6,0xafe6) AM_READWRITE_LEGACY(fm77av_video_flags_r,fm77av_video_flags_w)
	1524	AM_RANGE(0xafe4,0xafe4) AM_READWRITE(fm7_sub_busyflag_r,fm7_sub_busyflag_w)
	1525	AM_RANGE(0xafe6,0xafe6) AM_READWRITE(fm77av_video_flags_r,fm77av_video_flags_w)
1555	1526	AM_RANGE(0xc000,0xffff) AM_ROM // sybsystem ROM
1556	1527	ADDRESS_MAP_END
1557	1528
r14963	r14964
1562	1533	ADDRESS_MAP_END
1563	1534
1564	1535	static ADDRESS_MAP_START( fm11_x86_io, AS_IO, 8, fm7_state )
1565		AM_RANGE(0xfd00,0xfd01) AM_READWRITE_LEGACY(fm7_keyboard_r,fm7_cassette_printer_w)
1566		AM_RANGE(0xfd02,0xfd02) AM_READWRITE_LEGACY(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
1567		AM_RANGE(0xfd03,0xfd03) AM_READWRITE_LEGACY(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
1568		AM_RANGE(0xfd04,0xfd04) AM_READ_LEGACY(fm7_fd04_r)
1569		AM_RANGE(0xfd05,0xfd05) AM_READWRITE_LEGACY(fm7_subintf_r,fm7_subintf_w)
1570		AM_RANGE(0xfd06,0xfd0c) AM_READ_LEGACY(fm7_unknown_r)
1571		AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE_LEGACY(fm7_rom_en_r,fm7_rom_en_w)
1572		AM_RANGE(0xfd10,0xfd17) AM_READ_LEGACY(fm7_unknown_r)
1573		AM_RANGE(0xfd18,0xfd1f) AM_READWRITE_LEGACY(fm7_fdc_r,fm7_fdc_w)
1574		AM_RANGE(0xfd20,0xfd23) AM_READWRITE_LEGACY(fm7_kanji_r,fm7_kanji_w)
1575		AM_RANGE(0xfd24,0xfd36) AM_READ_LEGACY(fm7_unknown_r)
1576		AM_RANGE(0xfd37,0xfd37) AM_WRITE_LEGACY(fm7_multipage_w)
1577		AM_RANGE(0xfd38,0xfd3f) AM_READWRITE_LEGACY(fm7_palette_r,fm7_palette_w)
1578		AM_RANGE(0xfd40,0xfdff) AM_READ_LEGACY(fm7_unknown_r)
	1536	AM_RANGE(0xfd00,0xfd01) AM_READWRITE(fm7_keyboard_r,fm7_cassette_printer_w)
	1537	AM_RANGE(0xfd02,0xfd02) AM_READWRITE(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
	1538	AM_RANGE(0xfd03,0xfd03) AM_READWRITE(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
	1539	AM_RANGE(0xfd04,0xfd04) AM_READ(fm7_fd04_r)
	1540	AM_RANGE(0xfd05,0xfd05) AM_READWRITE(fm7_subintf_r,fm7_subintf_w)
	1541	AM_RANGE(0xfd06,0xfd0c) AM_READ(fm7_unknown_r)
	1542	AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE(fm7_rom_en_r,fm7_rom_en_w)
	1543	AM_RANGE(0xfd10,0xfd17) AM_READ(fm7_unknown_r)
	1544	AM_RANGE(0xfd18,0xfd1f) AM_READWRITE(fm7_fdc_r,fm7_fdc_w)
	1545	AM_RANGE(0xfd20,0xfd23) AM_READWRITE(fm7_kanji_r,fm7_kanji_w)
	1546	AM_RANGE(0xfd24,0xfd36) AM_READ(fm7_unknown_r)
	1547	AM_RANGE(0xfd37,0xfd37) AM_WRITE(fm7_multipage_w)
	1548	AM_RANGE(0xfd38,0xfd3f) AM_READWRITE(fm7_palette_r,fm7_palette_w)
	1549	AM_RANGE(0xfd40,0xfdff) AM_READ(fm7_unknown_r)
1579	1550	ADDRESS_MAP_END
1580	1551
1581	1552	static ADDRESS_MAP_START( fm16_mem, AS_PROGRAM, 16, fm7_state )
r14963	r14964
1584	1555	ADDRESS_MAP_END
1585	1556
1586	1557	static ADDRESS_MAP_START( fm16_io, AS_IO, 16, fm7_state )
1587		AM_RANGE(0xfd00,0xfd01) AM_READWRITE8_LEGACY(fm7_keyboard_r,fm7_cassette_printer_w,0xffff)
1588		AM_RANGE(0xfd02,0xfd03) AM_READWRITE8_LEGACY(fm7_cassette_printer_r,fm7_irq_mask_w,0x00ff)  // IRQ mask
1589		AM_RANGE(0xfd02,0xfd03) AM_READWRITE8_LEGACY(fm7_irq_cause_r,fm7_beeper_w,0xff00)  // IRQ flags
1590		AM_RANGE(0xfd04,0xfd05) AM_READ8_LEGACY(fm7_fd04_r,0x00ff)
1591		AM_RANGE(0xfd04,0xfd05) AM_READWRITE8_LEGACY(fm7_subintf_r,fm7_subintf_w,0xff00)
1592		//  AM_RANGE(0xfd06,0xfd0c) AM_READ8_LEGACY(fm7_unknown_r,0xffff)
1593		AM_RANGE(0xfd0e,0xfd0f) AM_READWRITE8_LEGACY(fm7_rom_en_r,fm7_rom_en_w,0xff00)
1594		//  AM_RANGE(0xfd10,0xfd17) AM_READ8_LEGACY(fm7_unknown_r,0xffff)
1595		AM_RANGE(0xfd18,0xfd1f) AM_READWRITE8_LEGACY(fm7_fdc_r,fm7_fdc_w,0xffff)
1596		AM_RANGE(0xfd20,0xfd23) AM_READWRITE8_LEGACY(fm7_kanji_r,fm7_kanji_w,0xffff)
1597		//  AM_RANGE(0xfd24,0xfd36) AM_READ8_LEGACY(fm7_unknown_r,0xffff)
1598		AM_RANGE(0xfd36,0xfd37) AM_WRITE8_LEGACY(fm7_multipage_w,0xff00)
1599		AM_RANGE(0xfd38,0xfd3f) AM_READWRITE8_LEGACY(fm7_palette_r,fm7_palette_w,0xffff)
1600		//  AM_RANGE(0xfd40,0xfdff) AM_READ8_LEGACY(fm7_unknown_r,0xffff)
	1558	AM_RANGE(0xfd00,0xfd01) AM_READWRITE8(fm7_keyboard_r,fm7_cassette_printer_w,0xffff)
	1559	AM_RANGE(0xfd02,0xfd03) AM_READWRITE8(fm7_cassette_printer_r,fm7_irq_mask_w,0x00ff)  // IRQ mask
	1560	AM_RANGE(0xfd02,0xfd03) AM_READWRITE8(fm7_irq_cause_r,fm7_beeper_w,0xff00)  // IRQ flags
	1561	AM_RANGE(0xfd04,0xfd05) AM_READ8(fm7_fd04_r,0x00ff)
	1562	AM_RANGE(0xfd04,0xfd05) AM_READWRITE8(fm7_subintf_r,fm7_subintf_w,0xff00)
	1563	//  AM_RANGE(0xfd06,0xfd0c) AM_READ8(fm7_unknown_r,0xffff)
	1564	AM_RANGE(0xfd0e,0xfd0f) AM_READWRITE8(fm7_rom_en_r,fm7_rom_en_w,0xff00)
	1565	//  AM_RANGE(0xfd10,0xfd17) AM_READ8(fm7_unknown_r,0xffff)
	1566	AM_RANGE(0xfd18,0xfd1f) AM_READWRITE8(fm7_fdc_r,fm7_fdc_w,0xffff)
	1567	AM_RANGE(0xfd20,0xfd23) AM_READWRITE8(fm7_kanji_r,fm7_kanji_w,0xffff)
	1568	//  AM_RANGE(0xfd24,0xfd36) AM_READ8(fm7_unknown_r,0xffff)
	1569	AM_RANGE(0xfd36,0xfd37) AM_WRITE8(fm7_multipage_w,0xff00)
	1570	AM_RANGE(0xfd38,0xfd3f) AM_READWRITE8(fm7_palette_r,fm7_palette_w,0xffff)
	1571	//  AM_RANGE(0xfd40,0xfdff) AM_READ8(fm7_unknown_r,0xffff)
1601	1572	ADDRESS_MAP_END
1602	1573
1603	1574	static ADDRESS_MAP_START( fm16_sub_mem, AS_PROGRAM, 8, fm7_state )
1604		AM_RANGE(0x0000,0xafff) AM_READWRITE_LEGACY(fm7_vram_r,fm7_vram_w) // VRAM
	1575	AM_RANGE(0x0000,0xafff) AM_READWRITE(fm7_vram_r,fm7_vram_w) // VRAM
1605	1576	AM_RANGE(0xb000,0xffff) AM_ROM // subsystem ROM
1606	1577	ADDRESS_MAP_END
1607	1578
r14963	r14964
1623	1594	AM_RANGE(0xe000,0xefff) AM_RAMBANK("bank15")
1624	1595	AM_RANGE(0xf000,0xfbff) AM_RAMBANK("bank16")
1625	1596	AM_RANGE(0xfc00,0xfc7f) AM_RAM
1626		AM_RANGE(0xfc80,0xfcff) AM_READWRITE_LEGACY(fm7_main_shared_r,fm7_main_shared_w)
	1597	AM_RANGE(0xfc80,0xfcff) AM_READWRITE(fm7_main_shared_r,fm7_main_shared_w)
1627	1598	// I/O space (FD00-FDFF)
1628		AM_RANGE(0xfd00,0xfd01) AM_READWRITE_LEGACY(fm7_keyboard_r,fm7_cassette_printer_w)
1629		AM_RANGE(0xfd02,0xfd02) AM_READWRITE_LEGACY(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
1630		AM_RANGE(0xfd03,0xfd03) AM_READWRITE_LEGACY(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
1631		AM_RANGE(0xfd04,0xfd04) AM_READ_LEGACY(fm7_fd04_r)
1632		AM_RANGE(0xfd05,0xfd05) AM_READWRITE_LEGACY(fm7_subintf_r,fm7_subintf_w)
1633		AM_RANGE(0xfd06,0xfd0a) AM_READ_LEGACY(fm7_unknown_r)
1634		AM_RANGE(0xfd0b,0xfd0b) AM_READ_LEGACY(fm77av_boot_mode_r)
1635		AM_RANGE(0xfd0c,0xfd0c) AM_READ_LEGACY(fm7_unknown_r)
1636		AM_RANGE(0xfd0d,0xfd0d) AM_READWRITE_LEGACY(fm7_psg_select_r,fm7_psg_select_w)
1637		AM_RANGE(0xfd0e,0xfd0e) AM_READWRITE_LEGACY(fm7_psg_data_r, fm7_psg_data_w)
1638		AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE_LEGACY(fm7_rom_en_r,fm7_rom_en_w)
1639		AM_RANGE(0xfd10,0xfd10) AM_WRITE_LEGACY(fm7_init_en_w)
1640		AM_RANGE(0xfd11,0xfd11) AM_READ_LEGACY(fm7_unknown_r)
1641		AM_RANGE(0xfd12,0xfd12) AM_READWRITE_LEGACY(fm77av_sub_modestatus_r,fm77av_sub_modestatus_w)
1642		AM_RANGE(0xfd13,0xfd13) AM_WRITE_LEGACY(fm77av_sub_bank_w)
1643		AM_RANGE(0xfd14,0xfd14) AM_READ_LEGACY(fm7_unknown_r)
1644		AM_RANGE(0xfd15,0xfd15) AM_READWRITE_LEGACY(fm7_psg_select_r,fm77av_ym_select_w)
1645		AM_RANGE(0xfd16,0xfd16) AM_READWRITE_LEGACY(fm7_psg_data_r,fm7_psg_data_w)
1646		AM_RANGE(0xfd17,0xfd17) AM_READ_LEGACY(fm7_fmirq_r)
1647		AM_RANGE(0xfd18,0xfd1f) AM_READWRITE_LEGACY(fm7_fdc_r,fm7_fdc_w)
1648		AM_RANGE(0xfd20,0xfd23) AM_READWRITE_LEGACY(fm7_kanji_r,fm7_kanji_w)
1649		AM_RANGE(0xfd24,0xfd2b) AM_READ_LEGACY(fm7_unknown_r)
1650		AM_RANGE(0xfd30,0xfd34) AM_WRITE_LEGACY(fm77av_analog_palette_w)
1651		AM_RANGE(0xfd35,0xfd36) AM_READ_LEGACY(fm7_unknown_r)
1652		AM_RANGE(0xfd37,0xfd37) AM_WRITE_LEGACY(fm7_multipage_w)
1653		AM_RANGE(0xfd38,0xfd3f) AM_READWRITE_LEGACY(fm7_palette_r,fm7_palette_w)
1654		AM_RANGE(0xfd40,0xfd7f) AM_READ_LEGACY(fm7_unknown_r)
1655		AM_RANGE(0xfd80,0xfd93) AM_READWRITE_LEGACY(fm7_mmr_r,fm7_mmr_w)
1656		AM_RANGE(0xfd94,0xfdff) AM_READ_LEGACY(fm7_unknown_r)
	1599	AM_RANGE(0xfd00,0xfd01) AM_READWRITE(fm7_keyboard_r,fm7_cassette_printer_w)
	1600	AM_RANGE(0xfd02,0xfd02) AM_READWRITE(fm7_cassette_printer_r,fm7_irq_mask_w)  // IRQ mask
	1601	AM_RANGE(0xfd03,0xfd03) AM_READWRITE(fm7_irq_cause_r,fm7_beeper_w)  // IRQ flags
	1602	AM_RANGE(0xfd04,0xfd04) AM_READ(fm7_fd04_r)
	1603	AM_RANGE(0xfd05,0xfd05) AM_READWRITE(fm7_subintf_r,fm7_subintf_w)
	1604	AM_RANGE(0xfd06,0xfd0a) AM_READ(fm7_unknown_r)
	1605	AM_RANGE(0xfd0b,0xfd0b) AM_READ(fm77av_boot_mode_r)
	1606	AM_RANGE(0xfd0c,0xfd0c) AM_READ(fm7_unknown_r)
	1607	AM_RANGE(0xfd0d,0xfd0d) AM_READWRITE(fm7_psg_select_r,fm7_psg_select_w)
	1608	AM_RANGE(0xfd0e,0xfd0e) AM_READWRITE(fm7_psg_data_r, fm7_psg_data_w)
	1609	AM_RANGE(0xfd0f,0xfd0f) AM_READWRITE(fm7_rom_en_r,fm7_rom_en_w)
	1610	AM_RANGE(0xfd10,0xfd10) AM_WRITE(fm7_init_en_w)
	1611	AM_RANGE(0xfd11,0xfd11) AM_READ(fm7_unknown_r)
	1612	AM_RANGE(0xfd12,0xfd12) AM_READWRITE(fm77av_sub_modestatus_r,fm77av_sub_modestatus_w)
	1613	AM_RANGE(0xfd13,0xfd13) AM_WRITE(fm77av_sub_bank_w)
	1614	AM_RANGE(0xfd14,0xfd14) AM_READ(fm7_unknown_r)
	1615	AM_RANGE(0xfd15,0xfd15) AM_READWRITE(fm7_psg_select_r,fm77av_ym_select_w)
	1616	AM_RANGE(0xfd16,0xfd16) AM_READWRITE(fm7_psg_data_r,fm7_psg_data_w)
	1617	AM_RANGE(0xfd17,0xfd17) AM_READ(fm7_fmirq_r)
	1618	AM_RANGE(0xfd18,0xfd1f) AM_READWRITE(fm7_fdc_r,fm7_fdc_w)
	1619	AM_RANGE(0xfd20,0xfd23) AM_READWRITE(fm7_kanji_r,fm7_kanji_w)
	1620	AM_RANGE(0xfd24,0xfd2b) AM_READ(fm7_unknown_r)
	1621	AM_RANGE(0xfd30,0xfd34) AM_WRITE(fm77av_analog_palette_w)
	1622	AM_RANGE(0xfd35,0xfd36) AM_READ(fm7_unknown_r)
	1623	AM_RANGE(0xfd37,0xfd37) AM_WRITE(fm7_multipage_w)
	1624	AM_RANGE(0xfd38,0xfd3f) AM_READWRITE(fm7_palette_r,fm7_palette_w)
	1625	AM_RANGE(0xfd40,0xfd7f) AM_READ(fm7_unknown_r)
	1626	AM_RANGE(0xfd80,0xfd93) AM_READWRITE(fm7_mmr_r,fm7_mmr_w)
	1627	AM_RANGE(0xfd94,0xfdff) AM_READ(fm7_unknown_r)
1657	1628	// Boot ROM (RAM on FM77AV and later)
1658		AM_RANGE(0xfe00,0xffdf) AM_RAM_WRITE_LEGACY(fm77av_bootram_w) AM_SHARE("boot_ram")
	1629	AM_RANGE(0xfe00,0xffdf) AM_RAM_WRITE(fm77av_bootram_w) AM_SHARE("boot_ram")
1659	1630	AM_RANGE(0xffe0,0xffef) AM_RAM
1660		AM_RANGE(0xfff0,0xffff) AM_READWRITE_LEGACY(vector_r,vector_w)
	1631	AM_RANGE(0xfff0,0xffff) AM_READWRITE(vector_r,vector_w)
1661	1632	ADDRESS_MAP_END
1662	1633
1663	1634	static ADDRESS_MAP_START( fm77av_sub_mem, AS_PROGRAM, 8, fm7_state )
1664		AM_RANGE(0x0000,0xbfff) AM_READWRITE_LEGACY(fm7_vram_r,fm7_vram_w) // VRAM
	1635	AM_RANGE(0x0000,0xbfff) AM_READWRITE(fm7_vram_r,fm7_vram_w) // VRAM
1665	1636	AM_RANGE(0xc000,0xcfff) AM_RAM AM_REGION("maincpu",0x1c000) // Console RAM
1666	1637	AM_RANGE(0xd000,0xd37f) AM_RAM AM_REGION("maincpu",0x1d000) // Work RAM
1667	1638	AM_RANGE(0xd380,0xd3ff) AM_RAM AM_SHARE("shared_ram")
1668	1639	// I/O space (D400-D4FF)
1669		AM_RANGE(0xd400,0xd401) AM_READ_LEGACY(fm7_sub_keyboard_r)
1670		AM_RANGE(0xd402,0xd402) AM_READ_LEGACY(fm7_cancel_ack)
1671		AM_RANGE(0xd403,0xd403) AM_READ_LEGACY(fm7_sub_beeper_r)
1672		AM_RANGE(0xd404,0xd404) AM_READ_LEGACY(fm7_attn_irq_r)
1673		AM_RANGE(0xd408,0xd408) AM_READWRITE_LEGACY(fm7_crt_r,fm7_crt_w)
1674		AM_RANGE(0xd409,0xd409) AM_READWRITE_LEGACY(fm7_vram_access_r,fm7_vram_access_w)
1675		AM_RANGE(0xd40a,0xd40a) AM_READWRITE_LEGACY(fm7_sub_busyflag_r,fm7_sub_busyflag_w)
1676		AM_RANGE(0xd40e,0xd40f) AM_WRITE_LEGACY(fm7_vram_offset_w)
1677		AM_RANGE(0xd410,0xd42b) AM_READWRITE_LEGACY(fm77av_alu_r, fm77av_alu_w)
1678		AM_RANGE(0xd430,0xd430) AM_READWRITE_LEGACY(fm77av_video_flags_r,fm77av_video_flags_w)
1679		AM_RANGE(0xd431,0xd432) AM_READWRITE_LEGACY(fm77av_key_encoder_r,fm77av_key_encoder_w)
	1640	AM_RANGE(0xd400,0xd401) AM_READ(fm7_sub_keyboard_r)
	1641	AM_RANGE(0xd402,0xd402) AM_READ(fm7_cancel_ack)
	1642	AM_RANGE(0xd403,0xd403) AM_READ(fm7_sub_beeper_r)
	1643	AM_RANGE(0xd404,0xd404) AM_READ(fm7_attn_irq_r)
	1644	AM_RANGE(0xd408,0xd408) AM_READWRITE(fm7_crt_r,fm7_crt_w)
	1645	AM_RANGE(0xd409,0xd409) AM_READWRITE(fm7_vram_access_r,fm7_vram_access_w)
	1646	AM_RANGE(0xd40a,0xd40a) AM_READWRITE(fm7_sub_busyflag_r,fm7_sub_busyflag_w)
	1647	AM_RANGE(0xd40e,0xd40f) AM_WRITE(fm7_vram_offset_w)
	1648	AM_RANGE(0xd410,0xd42b) AM_READWRITE(fm77av_alu_r, fm77av_alu_w)
	1649	AM_RANGE(0xd430,0xd430) AM_READWRITE(fm77av_video_flags_r,fm77av_video_flags_w)
	1650	AM_RANGE(0xd431,0xd432) AM_READWRITE(fm77av_key_encoder_r,fm77av_key_encoder_w)
1680	1651	AM_RANGE(0xd500,0xd7ff) AM_RAM AM_REGION("maincpu",0x1d500) // Work RAM
1681	1652	AM_RANGE(0xd800,0xdfff) AM_ROMBANK("bank20")
1682	1653	AM_RANGE(0xe000,0xffff) AM_ROMBANK("bank21")

src/mess/drivers/vtech2.c

r14963	r14964
83	83
84	84	static ADDRESS_MAP_START(vtech2_io, AS_IO, 8, vtech2_state )
85	85	ADDRESS_MAP_GLOBAL_MASK(0xff)
86		AM_RANGE(0x10, 0x1f) AM_READWRITE_LEGACY(laser_fdc_r, laser_fdc_w)
87		AM_RANGE(0x40, 0x43) AM_WRITE_LEGACY(laser_bank_select_w)
88		AM_RANGE(0x44, 0x44) AM_WRITE_LEGACY(laser_bg_mode_w)
89		AM_RANGE(0x45, 0x45) AM_WRITE_LEGACY(laser_two_color_w)
	86	AM_RANGE(0x10, 0x1f) AM_READWRITE(laser_fdc_r, laser_fdc_w)
	87	AM_RANGE(0x40, 0x43) AM_WRITE(laser_bank_select_w)
	88	AM_RANGE(0x44, 0x44) AM_WRITE(laser_bg_mode_w)
	89	AM_RANGE(0x45, 0x45) AM_WRITE(laser_two_color_w)
90	90	ADDRESS_MAP_END
91	91
92	92	/* 2008-05 FP:

src/mess/drivers/z80ne.c

r14963	r14964
142	142
143	143	static ADDRESS_MAP_START( z80ne_io, AS_IO, 8, z80ne_state )
144	144	ADDRESS_MAP_GLOBAL_MASK(0xff)
145		AM_RANGE(0xee, 0xee) AM_READWRITE_LEGACY(lx385_data_r, lx385_data_w )
146		AM_RANGE(0xef, 0xef) AM_READWRITE_LEGACY(lx385_ctrl_r, lx385_ctrl_w )
147		AM_RANGE(0xf0, 0xff) AM_READWRITE_LEGACY(lx383_r, lx383_w )
	145	AM_RANGE(0xee, 0xee) AM_READWRITE(lx385_data_r, lx385_data_w )
	146	AM_RANGE(0xef, 0xef) AM_READWRITE(lx385_ctrl_r, lx385_ctrl_w )
	147	AM_RANGE(0xf0, 0xff) AM_READWRITE(lx383_r, lx383_w )
148	148	ADDRESS_MAP_END
149	149
150	150	static ADDRESS_MAP_START( z80net_io, AS_IO, 8, z80ne_state )
151	151	ADDRESS_MAP_GLOBAL_MASK(0xff)
152		AM_RANGE(0xea, 0xea) AM_READ_LEGACY(lx388_data_r )
153		AM_RANGE(0xeb, 0xeb) AM_READ_LEGACY(lx388_read_field_sync )
154		AM_RANGE(0xee, 0xee) AM_READWRITE_LEGACY(lx385_data_r, lx385_data_w )
155		AM_RANGE(0xef, 0xef) AM_READWRITE_LEGACY(lx385_ctrl_r, lx385_ctrl_w )
156		AM_RANGE(0xf0, 0xff) AM_READWRITE_LEGACY(lx383_r, lx383_w )
	152	AM_RANGE(0xea, 0xea) AM_READ(lx388_data_r )
	153	AM_RANGE(0xeb, 0xeb) AM_READ(lx388_read_field_sync )
	154	AM_RANGE(0xee, 0xee) AM_READWRITE(lx385_data_r, lx385_data_w )
	155	AM_RANGE(0xef, 0xef) AM_READWRITE(lx385_ctrl_r, lx385_ctrl_w )
	156	AM_RANGE(0xf0, 0xff) AM_READWRITE(lx383_r, lx383_w )
157	157	ADDRESS_MAP_END
158	158
159	159	static ADDRESS_MAP_START( z80netf_mem, AS_PROGRAM, 8, z80ne_state )
r14963	r14964
172	172	static ADDRESS_MAP_START( z80netf_io, AS_IO, 8, z80ne_state )
173	173	ADDRESS_MAP_GLOBAL_MASK(0xff)
174	174	AM_RANGE(0xd0, 0xd7) AM_DEVREADWRITE_LEGACY("wd1771", lx390_fdc_r, lx390_fdc_w)
175		AM_RANGE(0xea, 0xea) AM_READ_LEGACY(lx388_data_r )
176		AM_RANGE(0xeb, 0xeb) AM_READ_LEGACY(lx388_read_field_sync )
177		AM_RANGE(0xee, 0xee) AM_READWRITE_LEGACY(lx385_data_r, lx385_data_w )
178		AM_RANGE(0xef, 0xef) AM_READWRITE_LEGACY(lx385_ctrl_r, lx385_ctrl_w )
179		AM_RANGE(0xf0, 0xff) AM_READWRITE_LEGACY(lx383_r, lx383_w )
	175	AM_RANGE(0xea, 0xea) AM_READ(lx388_data_r )
	176	AM_RANGE(0xeb, 0xeb) AM_READ(lx388_read_field_sync )
	177	AM_RANGE(0xee, 0xee) AM_READWRITE(lx385_data_r, lx385_data_w )
	178	AM_RANGE(0xef, 0xef) AM_READWRITE(lx385_ctrl_r, lx385_ctrl_w )
	179	AM_RANGE(0xf0, 0xff) AM_READWRITE(lx383_r, lx383_w )
180	180	ADDRESS_MAP_END
181	181
182	182

src/mess/drivers/ami1200.c

r14963	r14964
36	36	UINT16 m_potgo_value;
37	37	int m_cd32_shifter[2];
38	38	int m_oldstate[2];
	39	DECLARE_WRITE32_MEMBER(aga_overlay_w);
39	40	};
40	41
41	42
r14963	r14964
47	48
48	49	static void handle_cd32_joystick_cia(ami1200_state *state, UINT8 pra, UINT8 dra);
49	50
50		static WRITE32_HANDLER( aga_overlay_w )
	51	WRITE32_MEMBER(ami1200_state::aga_overlay_w)
51	52	{
52	53	if (ACCESSING_BITS_16_23)
53	54	{
54	55	data = (data >> 16) & 1;
55	56
56	57	/* switch banks as appropriate */
57		memory_set_bank(space->machine(), "bank1", data & 1);
	58	memory_set_bank(machine(), "bank1", data & 1);
58	59
59	60	/* swap the write handlers between ROM and bank 1 based on the bit */
60	61	if ((data & 1) == 0)
61	62	/* overlay disabled, map RAM on 0x000000 */
62		space->install_write_bank(0x000000, 0x1fffff, "bank1");
	63	space.install_write_bank(0x000000, 0x1fffff, "bank1");
63	64	else
64	65	/* overlay enabled, map Amiga system ROM on 0x000000 */
65		space->unmap_write(0x000000, 0x1fffff);
	66	space.unmap_write(0x000000, 0x1fffff);
66	67	}
67	68	}
68	69
r14963	r14964
122	123	static ADDRESS_MAP_START( a1200_map, AS_PROGRAM, 32, ami1200_state )
123	124	ADDRESS_MAP_UNMAP_HIGH
124	125	AM_RANGE(0x000000, 0x1fffff) AM_RAMBANK("bank1") AM_SHARE("chip_ram")
125		AM_RANGE(0xbfa000, 0xbfa003) AM_WRITE_LEGACY(aga_overlay_w)
	126	AM_RANGE(0xbfa000, 0xbfa003) AM_WRITE(aga_overlay_w)
126	127	AM_RANGE(0xbfd000, 0xbfefff) AM_READWRITE16_LEGACY(amiga_cia_r, amiga_cia_w, 0xffffffff)
127	128	AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE16_LEGACY(amiga_custom_r, amiga_custom_w, 0xffffffff) AM_SHARE("custom_regs")
128	129	AM_RANGE(0xe80000, 0xe8ffff) AM_READWRITE16_LEGACY(amiga_autoconfig_r, amiga_autoconfig_w, 0xffffffff)

src/mess/drivers/nc.c

r14963	r14964
585	585	ADDRESS_MAP_END
586	586
587	587
588		static  READ8_HANDLER(nc_memory_management_r)
	588	READ8_MEMBER(nc_state::nc_memory_management_r)
589	589	{
590		nc_state *state = space->machine().driver_data<nc_state>();
591		return state->m_memory_config[offset];
	590	return m_memory_config[offset];
592	591	}
593	592
594		static WRITE8_HANDLER(nc_memory_management_w)
	593	WRITE8_MEMBER(nc_state::nc_memory_management_w)
595	594	{
596		nc_state *state = space->machine().driver_data<nc_state>();
597	595	LOG(("Memory management W: %02x %02x\n",offset,data));
598		state->m_memory_config[offset] = data;
	596	m_memory_config[offset] = data;
599	597
600		nc_refresh_memory_config(space->machine());
	598	nc_refresh_memory_config(machine());
601	599	}
602	600
603		static WRITE8_HANDLER(nc_irq_mask_w)
	601	WRITE8_MEMBER(nc_state::nc_irq_mask_w)
604	602	{
605		nc_state *state = space->machine().driver_data<nc_state>();
606	603	LOG(("irq mask w: %02x\n", data));
607	604	LOG_DEBUG(("irq mask nc200 w: %02x\n",data & ((1<<4) | (1<<5) | (1<<6) | (1<<7))));
608	605
609	606	/* writing mask clears ints that are to be masked? */
610		state->m_irq_mask = data;
	607	m_irq_mask = data;
611	608
612		nc_update_interrupts(space->machine());
	609	nc_update_interrupts(machine());
613	610	}
614	611
615		static WRITE8_HANDLER(nc_irq_status_w)
	612	WRITE8_MEMBER(nc_state::nc_irq_status_w)
616	613	{
617		nc_state *state = space->machine().driver_data<nc_state>();
618	614	LOG(("irq status w: %02x\n", data));
619	615	data = data^0x0ff;
620	616
621		if (state->m_type == NC_TYPE_200)
	617	if (m_type == NC_TYPE_200)
622	618	{
623	619	/* Russell Marks confirms that on the NC200, the key scan interrupt must be explicitly
624	620	cleared. It is not automatically cleared when reading 0x0b9 */
625	621	if ((data & (1<<3))!=0)
626	622	{
627	623	/* set timer to occur again */
628		state->m_keyboard_timer->reset(attotime::from_msec(10));
	624	m_keyboard_timer->reset(attotime::from_msec(10));
629	625
630		nc_update_interrupts(space->machine());
	626	nc_update_interrupts(machine());
631	627	}
632	628	}
633	629
r14963	r14964
638	634	/* clearing keyboard int? */
639	635	((data & (1<<3))!=0) &&
640	636	/* keyboard int request? */
641		((state->m_irq_status & (1<<3))!=0)
	637	((m_irq_status & (1<<3))!=0)
642	638	)
643	639	{
644	640	/* set timer to occur again */
645		state->m_keyboard_timer->reset(attotime::from_msec(10));
	641	m_keyboard_timer->reset(attotime::from_msec(10));
646	642	}
647	643	#endif
648		state->m_irq_status &=~data;
	644	m_irq_status &=~data;
649	645
650		nc_update_interrupts(space->machine());
	646	nc_update_interrupts(machine());
651	647	}
652	648
653		static READ8_HANDLER(nc_irq_status_r)
	649	READ8_MEMBER(nc_state::nc_irq_status_r)
654	650	{
655		nc_state *state = space->machine().driver_data<nc_state>();
656		return ~((state->m_irq_status & (~state->m_irq_latch_mask)) | state->m_irq_latch);
	651	return ~((m_irq_status & (~m_irq_latch_mask)) | m_irq_latch);
657	652	}
658	653
659	654
660		static READ8_HANDLER(nc_key_data_in_r)
	655	READ8_MEMBER(nc_state::nc_key_data_in_r)
661	656	{
662		nc_state *state = space->machine().driver_data<nc_state>();
663	657	static const char *const keynames[] = {
664	658	"LINE0", "LINE1", "LINE2", "LINE3", "LINE4",
665	659	"LINE5", "LINE6", "LINE7", "LINE8", "LINE9"
r14963	r14964
668	662	if (offset==9)
669	663	{
670	664	/* reading 0x0b9 will clear int and re-start scan procedure! */
671		state->m_irq_status &= ~(1<<3);
	665	m_irq_status &= ~(1<<3);
672	666
673	667	/* set timer to occur again */
674		state->m_keyboard_timer->reset(attotime::from_msec(10));
	668	m_keyboard_timer->reset(attotime::from_msec(10));
675	669
676		nc_update_interrupts(space->machine());
	670	nc_update_interrupts(machine());
677	671	}
678	672
679		return input_port_read(space->machine(), keynames[offset]);
	673	return input_port_read(machine(), keynames[offset]);
680	674	}
681	675
682	676
r14963	r14964
712	706	beep_set_frequency(machine.device(beep_device), frequency);
713	707	}
714	708
715		static WRITE8_HANDLER(nc_sound_w)
	709	WRITE8_MEMBER(nc_state::nc_sound_w)
716	710	{
717		nc_state *state = space->machine().driver_data<nc_state>();
718	711	LOG(("sound w: %04x %02x\n", offset, data));
719	712
720	713	switch (offset)
r14963	r14964
722	715	case 0x0:
723	716	{
724	717	/* update period value */
725		state->m_sound_channel_periods[0]  =
726		(state->m_sound_channel_periods[0] & 0x0ff00) | (data & 0x0ff);
	718	m_sound_channel_periods[0]  =
	719	(m_sound_channel_periods[0] & 0x0ff00) | (data & 0x0ff);
727	720
728		nc_sound_update(space->machine(), 0);
	721	nc_sound_update(machine(), 0);
729	722	}
730	723	break;
731	724
732	725	case 0x01:
733	726	{
734		state->m_sound_channel_periods[0] =
735		(state->m_sound_channel_periods[0] & 0x0ff) | ((data & 0x0ff)<<8);
	727	m_sound_channel_periods[0] =
	728	(m_sound_channel_periods[0] & 0x0ff) | ((data & 0x0ff)<<8);
736	729
737		nc_sound_update(space->machine(), 0);
	730	nc_sound_update(machine(), 0);
738	731	}
739	732	break;
740	733
741	734	case 0x02:
742	735	{
743	736	/* update period value */
744		state->m_sound_channel_periods[1]  =
745		(state->m_sound_channel_periods[1] & 0x0ff00) | (data & 0x0ff);
	737	m_sound_channel_periods[1]  =
	738	(m_sound_channel_periods[1] & 0x0ff00) | (data & 0x0ff);
746	739
747		nc_sound_update(space->machine(), 1);
	740	nc_sound_update(machine(), 1);
748	741	}
749	742	break;
750	743
751	744	case 0x03:
752	745	{
753		state->m_sound_channel_periods[1] =
754		(state->m_sound_channel_periods[1] & 0x0ff) | ((data & 0x0ff)<<8);
	746	m_sound_channel_periods[1] =
	747	(m_sound_channel_periods[1] & 0x0ff) | ((data & 0x0ff)<<8);
755	748
756		nc_sound_update(space->machine(), 1);
	749	nc_sound_update(machine(), 1);
757	750	}
758	751	break;
759	752
r14963	r14964
782	775	uart->receive_clock();
783	776	}
784	777
785		static WRITE8_HANDLER(nc_uart_control_w)
	778	WRITE8_MEMBER(nc_state::nc_uart_control_w)
786	779	{
787		nc_state *state = space->machine().driver_data<nc_state>();
788	780	/* update printer state */
789		nc_printer_update(space->machine(), data);
	781	nc_printer_update(machine(), data);
790	782
791	783	/* on/off changed state? */
792		if (((state->m_uart_control ^ data) & (1<<3))!=0)
	784	if (((m_uart_control ^ data) & (1<<3))!=0)
793	785	{
794	786	/* changed uart from off to on */
795	787	if ((data & (1<<3))==0)
796	788	{
797		devtag_reset(space->machine(), "uart");
	789	devtag_reset(machine(), "uart");
798	790	}
799	791	}
800	792
801		state->m_serial_timer->adjust(attotime::zero, 0, attotime::from_hz(baud_rate_table[(data & 0x07)]));
	793	m_serial_timer->adjust(attotime::zero, 0, attotime::from_hz(baud_rate_table[(data & 0x07)]));
802	794
803		state->m_uart_control = data;
	795	m_uart_control = data;
804	796	}
805	797
806	798	/* NC100 printer emulation */
r14963	r14964
820	812
821	813
822	814
823		static WRITE8_HANDLER(nc100_display_memory_start_w)
	815	WRITE8_MEMBER(nc_state::nc100_display_memory_start_w)
824	816	{
825		nc_state *state = space->machine().driver_data<nc_state>();
826	817	/* bit 7: A15 */
827	818	/* bit 6: A14 */
828	819	/* bit 5: A13 */
829	820	/* bit 4: A12 */
830	821	/* bit 3-0: not used */
831		state->m_display_memory_start = (data & 0x0f0)<<(12-4);
	822	m_display_memory_start = (data & 0x0f0)<<(12-4);
832	823
833		LOG(("disp memory w: %04x\n", (int) state->m_display_memory_start));
	824	LOG(("disp memory w: %04x\n", (int) m_display_memory_start));
834	825	}
835	826
836	827
837		static WRITE8_HANDLER(nc100_uart_control_w)
	828	WRITE8_MEMBER(nc_state::nc100_uart_control_w)
838	829	{
839		//nc_state *state = space->machine().driver_data<nc_state>();
840	830	nc_uart_control_w(space, offset,data);
841	831
842	832	//  /* is this correct?? */
843	833	//  if (data & (1<<3))
844	834	//  {
845	835	//      /* clear latched irq's */
846		//      state->m_irq_latch &= ~3;
	836	//      m_irq_latch &= ~3;
847	837	//      nc_update_interrupts(machine);
848	838	//  }
849	839	}
r14963	r14964
972	962	}
973	963
974	964
975		static WRITE8_HANDLER(nc100_poweroff_control_w)
	965	WRITE8_MEMBER(nc_state::nc100_poweroff_control_w)
976	966	{
977		nc_state *state = space->machine().driver_data<nc_state>();
978	967	/* bits 7-1: not used */
979	968	/* bit 0: 1 = no effect, 0 = power off */
980		state->m_poweroff_control = data;
	969	m_poweroff_control = data;
981	970	LOG(("nc poweroff control: %02x\n",data));
982	971	}
983	972
984	973
985	974	/* nc100 version of card/battery status */
986		static  READ8_HANDLER(nc100_card_battery_status_r)
	975	READ8_MEMBER(nc_state::nc100_card_battery_status_r)
987	976	{
988		nc_state *state = space->machine().driver_data<nc_state>();
989		centronics_device *printer = space->machine().device<centronics_device>("centronics");
	977	centronics_device *printer = machine().device<centronics_device>("centronics");
990	978	int nc_card_battery_status = 0x0fc;
991	979
992	980	/* printer */
993	981	nc_card_battery_status |= printer->ack_r();
994	982	nc_card_battery_status |= printer->busy_r() << 1;
995	983
996		if (state->m_card_status)
	984	if (m_card_status)
997	985	{
998	986	/* card present */
999	987	nc_card_battery_status &=~(1<<7);
1000	988	}
1001	989
1002		if (input_port_read(space->machine(), "EXTRA") & 0x02)
	990	if (input_port_read(machine(), "EXTRA") & 0x02)
1003	991	{
1004	992	/* card write enable */
1005	993	nc_card_battery_status &=~(1<<6);
r14963	r14964
1013	1001	return nc_card_battery_status;
1014	1002	}
1015	1003
1016		static WRITE8_HANDLER(nc100_memory_card_wait_state_w)
	1004	WRITE8_MEMBER(nc_state::nc100_memory_card_wait_state_w)
1017	1005	{
1018	1006	LOG(("nc100 memory card wait state: %02x\n",data));
1019	1007	}
r14963	r14964
1023	1011	static ADDRESS_MAP_START(nc100_io, AS_IO, 8, nc_state )
1024	1012	ADDRESS_MAP_GLOBAL_MASK(0xff)
1025	1013	ADDRESS_MAP_UNMAP_HIGH
1026		AM_RANGE(0x00, 0x0f) AM_WRITE_LEGACY(nc100_display_memory_start_w)
1027		AM_RANGE(0x10, 0x13) AM_READWRITE_LEGACY(nc_memory_management_r, nc_memory_management_w)
1028		AM_RANGE(0x20, 0x20) AM_WRITE_LEGACY(nc100_memory_card_wait_state_w)
1029		AM_RANGE(0x30, 0x30) AM_WRITE_LEGACY(nc100_uart_control_w)
	1014	AM_RANGE(0x00, 0x0f) AM_WRITE(nc100_display_memory_start_w)
	1015	AM_RANGE(0x10, 0x13) AM_READWRITE(nc_memory_management_r, nc_memory_management_w)
	1016	AM_RANGE(0x20, 0x20) AM_WRITE(nc100_memory_card_wait_state_w)
	1017	AM_RANGE(0x30, 0x30) AM_WRITE(nc100_uart_control_w)
1030	1018	AM_RANGE(0x40, 0x40) AM_DEVWRITE("centronics", centronics_device, write)
1031		AM_RANGE(0x50, 0x53) AM_WRITE_LEGACY(nc_sound_w)
1032		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(nc_irq_mask_w)
1033		AM_RANGE(0x70, 0x70) AM_WRITE_LEGACY(nc100_poweroff_control_w)
1034		AM_RANGE(0x90, 0x90) AM_READWRITE_LEGACY(nc_irq_status_r, nc_irq_status_w)
1035		AM_RANGE(0x91, 0x9f) AM_READ_LEGACY(nc_irq_status_r)
1036		AM_RANGE(0xa0, 0xaf) AM_READ_LEGACY(nc100_card_battery_status_r)
1037		AM_RANGE(0xb0, 0xb9) AM_READ_LEGACY(nc_key_data_in_r)
	1019	AM_RANGE(0x50, 0x53) AM_WRITE(nc_sound_w)
	1020	AM_RANGE(0x60, 0x60) AM_WRITE(nc_irq_mask_w)
	1021	AM_RANGE(0x70, 0x70) AM_WRITE(nc100_poweroff_control_w)
	1022	AM_RANGE(0x90, 0x90) AM_READWRITE(nc_irq_status_r, nc_irq_status_w)
	1023	AM_RANGE(0x91, 0x9f) AM_READ(nc_irq_status_r)
	1024	AM_RANGE(0xa0, 0xaf) AM_READ(nc100_card_battery_status_r)
	1025	AM_RANGE(0xb0, 0xb9) AM_READ(nc_key_data_in_r)
1038	1026	AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("uart",i8251_device, data_r, data_w)
1039	1027	AM_RANGE(0xc1, 0xc1) AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)
1040	1028	AM_RANGE(0xd0, 0xdf) AM_DEVREADWRITE("rtc", rp5c01_device, read, write)
r14963	r14964
1186	1174	/* NC200 hardware */
1187	1175
1188	1176	#ifdef UNUSED_FUNCTION
1189		static WRITE8_HANDLER(nc200_display_memory_start_w)
	1177	WRITE8_MEMBER(nc_state::nc200_display_memory_start_w)
1190	1178	{
1191		nc_state *state = space->machine().driver_data<nc_state>();
1192	1179	/* bit 7: A15 */
1193	1180	/* bit 6: A14 */
1194	1181	/* bit 5: A13 */
1195	1182	/* bit 4-0: not used */
1196		state->m_display_memory_start = (data & 0x0e0)<<(12-4);
	1183	m_display_memory_start = (data & 0x0e0)<<(12-4);
1197	1184
1198		LOG(("disp memory w: %04x\n", (int) state->m_display_memory_start));
	1185	LOG(("disp memory w: %04x\n", (int) m_display_memory_start));
1199	1186	}
1200	1187	#endif
1201	1188
r14963	r14964
1381	1368
1382	1369
1383	1370	/* nc200 version of card/battery status */
1384		static  READ8_HANDLER(nc200_card_battery_status_r)
	1371	READ8_MEMBER(nc_state::nc200_card_battery_status_r)
1385	1372	{
1386		nc_state *state = space->machine().driver_data<nc_state>();
1387	1373	int nc_card_battery_status = 0x0ff;
1388	1374
1389	1375	/* enough power */
r14963	r14964
1394	1380	and there is enough power for disk usage */
1395	1381	nc_card_battery_status &=~((1<<5) | (1<<2) | (1<<0));
1396	1382
1397		if (state->m_card_status)
	1383	if (m_card_status)
1398	1384	{
1399	1385	/* card present */
1400	1386	nc_card_battery_status&=~(1<<7);
1401	1387	}
1402	1388
1403		if (input_port_read(space->machine(), "EXTRA") & 0x02)
	1389	if (input_port_read(machine(), "EXTRA") & 0x02)
1404	1390	{
1405	1391	/* card write enable */
1406	1392	nc_card_battery_status &=~(1<<6);
r14963	r14964
1415	1401	bit 0: Parallel interface BUSY
1416	1402	*/
1417	1403
1418		static READ8_HANDLER(nc200_printer_status_r)
	1404	READ8_MEMBER(nc_state::nc200_printer_status_r)
1419	1405	{
1420		centronics_device *printer = space->machine().device<centronics_device>("centronics");
	1406	centronics_device *printer = machine().device<centronics_device>("centronics");
1421	1407	UINT8 result = 0;
1422	1408
1423	1409	result |= printer->busy_r();
r14963	r14964
1426	1412	}
1427	1413
1428	1414
1429		static WRITE8_HANDLER(nc200_uart_control_w)
	1415	WRITE8_MEMBER(nc_state::nc200_uart_control_w)
1430	1416	{
1431		nc_state *state = space->machine().driver_data<nc_state>();
1432		/* int reset_fdc = (state->m_uart_control^data) & (1<<5); */
	1417	/* int reset_fdc = (m_uart_control^data) & (1<<5); */
1433	1418
1434	1419	nc_uart_control_w(space, offset,data);
1435	1420
1436	1421	if (data & (1<<3))
1437	1422	{
1438		state->m_nc200_uart_interrupt_irq &=~3;
	1423	m_nc200_uart_interrupt_irq &=~3;
1439	1424
1440		nc200_refresh_uart_interrupt(space->machine());
	1425	nc200_refresh_uart_interrupt(machine());
1441	1426	}
1442	1427
1443	1428	/* bit 5 is used in disk interface */
1444		LOG_DEBUG(("bit 5: PC: %04x %02x\n", cpu_get_pc(space->machine().device("maincpu")), data & (1 << 5)));
	1429	LOG_DEBUG(("bit 5: PC: %04x %02x\n", cpu_get_pc(machine().device("maincpu")), data & (1 << 5)));
1445	1430	}
1446	1431
1447	1432
r14963	r14964
1457	1442	/* bit 1: disk motor??  */
1458	1443	/* bit 0: UPD765 Terminal Count input */
1459	1444
1460		static WRITE8_HANDLER(nc200_memory_card_wait_state_w)
	1445	WRITE8_MEMBER(nc_state::nc200_memory_card_wait_state_w)
1461	1446	{
1462		device_t *fdc = space->machine().device("upd765");
1463		LOG_DEBUG(("nc200 memory card wait state: PC: %04x %02x\n", cpu_get_pc(space->machine().device("maincpu")), data));
	1447	device_t *fdc = machine().device("upd765");
	1448	LOG_DEBUG(("nc200 memory card wait state: PC: %04x %02x\n", cpu_get_pc(machine().device("maincpu")), data));
1464	1449	#if 0
1465	1450	floppy_drive_set_motor_state(0, 1);
1466	1451	floppy_drive_set_ready_state(0, 1, 1);
r14963	r14964
1471	1456	/* bit 2: backlight: 1=off, 0=on */
1472	1457	/* bit 1 cleared to zero in disk code */
1473	1458	/* bit 0 seems to be the same as nc100 */
1474		static WRITE8_HANDLER(nc200_poweroff_control_w)
	1459	WRITE8_MEMBER(nc_state::nc200_poweroff_control_w)
1475	1460	{
1476		LOG_DEBUG(("nc200 power off: PC: %04x %02x\n", cpu_get_pc(space->machine().device("maincpu")), data));
	1461	LOG_DEBUG(("nc200 power off: PC: %04x %02x\n", cpu_get_pc(machine().device("maincpu")), data));
1477	1462
1478		nc200_video_set_backlight(space->machine(), ((data ^ (1 << 2)) >> 2) & 0x01);
	1463	nc200_video_set_backlight(machine(), ((data ^ (1 << 2)) >> 2) & 0x01);
1479	1464	}
1480	1465
1481	1466	static ADDRESS_MAP_START(nc200_io, AS_IO, 8, nc_state )
1482	1467	ADDRESS_MAP_GLOBAL_MASK(0xff)
1483		AM_RANGE(0x00, 0x0f) AM_WRITE_LEGACY(nc100_display_memory_start_w)
1484		AM_RANGE(0x10, 0x13) AM_READWRITE_LEGACY(nc_memory_management_r, nc_memory_management_w)
1485		AM_RANGE(0x20, 0x20) AM_WRITE_LEGACY(nc200_memory_card_wait_state_w)
1486		AM_RANGE(0x30, 0x30) AM_WRITE_LEGACY(nc200_uart_control_w)
	1468	AM_RANGE(0x00, 0x0f) AM_WRITE(nc100_display_memory_start_w)
	1469	AM_RANGE(0x10, 0x13) AM_READWRITE(nc_memory_management_r, nc_memory_management_w)
	1470	AM_RANGE(0x20, 0x20) AM_WRITE(nc200_memory_card_wait_state_w)
	1471	AM_RANGE(0x30, 0x30) AM_WRITE(nc200_uart_control_w)
1487	1472	AM_RANGE(0x40, 0x40) AM_DEVWRITE("centronics", centronics_device, write)
1488		AM_RANGE(0x50, 0x53) AM_WRITE_LEGACY(nc_sound_w)
1489		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(nc_irq_mask_w)
1490		AM_RANGE(0x70, 0x70) AM_WRITE_LEGACY(nc200_poweroff_control_w)
1491		AM_RANGE(0x80, 0x80) AM_READ_LEGACY(nc200_printer_status_r)
1492		AM_RANGE(0x90, 0x90) AM_READWRITE_LEGACY(nc_irq_status_r, nc_irq_status_w)
1493		AM_RANGE(0xa0, 0xa0) AM_READ_LEGACY(nc200_card_battery_status_r)
1494		AM_RANGE(0xb0, 0xb9) AM_READ_LEGACY(nc_key_data_in_r)
	1473	AM_RANGE(0x50, 0x53) AM_WRITE(nc_sound_w)
	1474	AM_RANGE(0x60, 0x60) AM_WRITE(nc_irq_mask_w)
	1475	AM_RANGE(0x70, 0x70) AM_WRITE(nc200_poweroff_control_w)
	1476	AM_RANGE(0x80, 0x80) AM_READ(nc200_printer_status_r)
	1477	AM_RANGE(0x90, 0x90) AM_READWRITE(nc_irq_status_r, nc_irq_status_w)
	1478	AM_RANGE(0xa0, 0xa0) AM_READ(nc200_card_battery_status_r)
	1479	AM_RANGE(0xb0, 0xb9) AM_READ(nc_key_data_in_r)
1495	1480	AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("uart",i8251_device, data_r, data_w)
1496	1481	AM_RANGE(0xc1, 0xc1) AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)
1497	1482	AM_RANGE(0xd0, 0xd1) AM_DEVREADWRITE("mc", mc146818_device, read, write)

src/mess/drivers/pentagon.c

r14963	r14964
93	93	AM_RANGE(0x003f, 0x003f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_track_r,betadisk_track_w) AM_MIRROR(0xff00)
94	94	AM_RANGE(0x005f, 0x005f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_sector_r,betadisk_sector_w) AM_MIRROR(0xff00)
95	95	AM_RANGE(0x007f, 0x007f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_data_r,betadisk_data_w) AM_MIRROR(0xff00)
96		AM_RANGE(0x00fe, 0x00fe) AM_READWRITE_LEGACY(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xff00) AM_MASK(0xffff)
	96	AM_RANGE(0x00fe, 0x00fe) AM_READWRITE(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xff00) AM_MASK(0xffff)
97	97	AM_RANGE(0x00ff, 0x00ff) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_state_r, betadisk_param_w) AM_MIRROR(0xff00)
98	98	AM_RANGE(0x4000, 0x4000) AM_WRITE_LEGACY(pentagon_port_7ffd_w)  AM_MIRROR(0x3ffd)
99	99	AM_RANGE(0x8000, 0x8000) AM_DEVWRITE_LEGACY("ay8912", ay8910_data_w) AM_MIRROR(0x3ffd)

src/mess/drivers/nes.c

r14963	r14964
36	36	nes_psg_w(device, 0x17, data);
37	37	}
38	38
39		static WRITE8_HANDLER(nes_vh_sprite_dma_w)
	39	WRITE8_MEMBER(nes_state::nes_vh_sprite_dma_w)
40	40	{
41		nes_state *state = space->machine().driver_data<nes_state>();
42		state->m_ppu->spriteram_dma(space, data);
	41	m_ppu->spriteram_dma(&space, data);
43	42	}
44	43
45	44	static ADDRESS_MAP_START( nes_map, AS_PROGRAM, 8, nes_state )
46	45	AM_RANGE(0x0000, 0x07ff) AM_RAM AM_MIRROR(0x1800)               /* RAM */
47	46	AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)      /* PPU registers */
48	47	AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nessound", nes_psg_r, nes_psg_w)      /* PSG primary registers */
49		AM_RANGE(0x4014, 0x4014) AM_WRITE_LEGACY(nes_vh_sprite_dma_w)            /* stupid address space hole */
	48	AM_RANGE(0x4014, 0x4014) AM_WRITE(nes_vh_sprite_dma_w)            /* stupid address space hole */
50	49	AM_RANGE(0x4015, 0x4015) AM_DEVREADWRITE_LEGACY("nessound", psg_4015_r, psg_4015_w)      /* PSG status / first control register */
51		AM_RANGE(0x4016, 0x4016) AM_READWRITE_LEGACY(nes_IN0_r, nes_IN0_w)         /* IN0 - input port 1 */
52		AM_RANGE(0x4017, 0x4017) AM_READ_LEGACY(nes_IN1_r)                     /* IN1 - input port 2 */
	50	AM_RANGE(0x4016, 0x4016) AM_READWRITE(nes_IN0_r, nes_IN0_w)         /* IN0 - input port 1 */
	51	AM_RANGE(0x4017, 0x4017) AM_READ(nes_IN1_r)                     /* IN1 - input port 2 */
53	52	AM_RANGE(0x4017, 0x4017) AM_DEVWRITE_LEGACY("nessound", psg_4017_w)      /* PSG second control register */
54	53	AM_RANGE(0x4100, 0x5fff) AM_READWRITE_LEGACY(nes_low_mapper_r, nes_low_mapper_w)   /* Perform unholy acts on the machine */
55	54	ADDRESS_MAP_END

src/mess/drivers/concept.c

r14963	r14964
42	42	AM_RANGE(0x000008, 0x000fff) AM_RAM                              /* static RAM */
43	43	AM_RANGE(0x010000, 0x011fff) AM_ROM AM_REGION("maincpu", 0x010000)   /* boot ROM */
44	44	AM_RANGE(0x020000, 0x021fff) AM_ROM                              /* macsbugs ROM (optional) */
45		AM_RANGE(0x030000, 0x03ffff) AM_READWRITE_LEGACY(concept_io_r,concept_io_w)   /* I/O space */
	45	AM_RANGE(0x030000, 0x03ffff) AM_READWRITE(concept_io_r,concept_io_w)   /* I/O space */
46	46
47	47	AM_RANGE(0x080000, 0x0fffff) AM_RAM AM_SHARE("videoram")/* AM_RAMBANK(2) */   /* DRAM */
48	48	ADDRESS_MAP_END

src/mess/drivers/pcw16.c

r14963	r14964
120	120	// bit 0: Display ints
121	121
122	122	// debugging - write ram as seen by cpu
123		static void pcw16_refresh_ints(running_machine &machine)
	123	void pcw16_state::pcw16_refresh_ints()
124	124	{
125		pcw16_state *state = machine.driver_data<pcw16_state>();
126	125	/* any bits set excluding vsync */
127		if ((state->m_system_status & (~0x04))!=0)
	126	if ((m_system_status & (~0x04))!=0)
128	127	{
129		cputag_set_input_line(machine, "maincpu", 0, HOLD_LINE);
	128	cputag_set_input_line(machine(), "maincpu", 0, HOLD_LINE);
130	129	}
131	130	else
132	131	{
133		cputag_set_input_line(machine, "maincpu", 0, CLEAR_LINE);
	132	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
134	133	}
135	134	}
136	135
r14963	r14964
148	147
149	148	if (state->m_interrupt_counter!=0)
150	149	{
151		pcw16_refresh_ints(timer.machine());
	150	state->pcw16_refresh_ints();
152	151	}
153	152	}
154	153
r14963	r14964
160	159	ADDRESS_MAP_END
161	160
162	161
163		static WRITE8_HANDLER(pcw16_palette_w)
	162	WRITE8_MEMBER(pcw16_state::pcw16_palette_w)
164	163	{
165		pcw16_state *state = space->machine().driver_data<pcw16_state>();
166		state->m_colour_palette[offset & 0x0f] = data & 31;
	164	m_colour_palette[offset & 0x0f] = data & 31;
167	165	}
168	166
169	167
r14963	r14964
362	360	PCW16_MEM_NONE
363	361	} PCW16_RAM_TYPE;
364	362
365		static  READ8_HANDLER(pcw16_no_mem_r)
	363	READ8_MEMBER(pcw16_state::pcw16_no_mem_r)
366	364	{
367	365	return 0x0ff;
368	366	}
r14963	r14964
370	368	static void pcw16_set_bank_handlers(running_machine &machine, int bank, PCW16_RAM_TYPE type)
371	369	{
372	370	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
373
	371	pcw16_state *state = machine.driver_data<pcw16_state>();
374	372	switch (type) {
375	373	case PCW16_MEM_ROM:
376	374	/* rom */
r14963	r14964
390	388	break;
391	389
392	390	case PCW16_MEM_NONE:
393		space->install_legacy_read_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, FUNC(pcw16_no_mem_r));
	391	space->install_read_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, read8_delegate(FUNC(pcw16_state::pcw16_no_mem_r),state));
394	392	space->nop_write((bank * 0x4000), (bank * 0x4000) + 0x3fff);
395	393	break;
396	394
r14963	r14964
498	496
499	497	}
500	498
501		static  READ8_HANDLER(pcw16_bankhw_r)
	499	READ8_MEMBER(pcw16_state::pcw16_bankhw_r)
502	500	{
503		pcw16_state *state = space->machine().driver_data<pcw16_state>();
504	501	//  logerror("bank r: %d \n", offset);
505	502
506		return state->m_banks[offset];
	503	return m_banks[offset];
507	504	}
508	505
509		static WRITE8_HANDLER(pcw16_bankhw_w)
	506	WRITE8_MEMBER(pcw16_state::pcw16_bankhw_w)
510	507	{
511		pcw16_state *state = space->machine().driver_data<pcw16_state>();
512	508	//logerror("bank w: %d block: %02x\n", offset, data);
513	509
514		state->m_banks[offset] = data;
	510	m_banks[offset] = data;
515	511
516		pcw16_update_memory(space->machine());
	512	pcw16_update_memory(machine());
517	513	}
518	514
519		static WRITE8_HANDLER(pcw16_video_control_w)
	515	WRITE8_MEMBER(pcw16_state::pcw16_video_control_w)
520	516	{
521		pcw16_state *state = space->machine().driver_data<pcw16_state>();
522	517	//logerror("video control w: %02x\n", data);
523	518
524		state->m_video_control = data;
	519	m_video_control = data;
525	520	}
526	521
527	522	/* PCW16 KEYBOARD */
r14963	r14964
544	539
545	540	/* parity table. Used to set parity bit in keyboard status register */
546	541
547
548		static void pcw16_keyboard_reset(pcw16_state *state);
549		static void pcw16_keyboard_int(running_machine &, int);
550
551		static void pcw16_keyboard_init(running_machine &machine)
	542	void pcw16_state::pcw16_keyboard_init()
552	543	{
553		pcw16_state *state = machine.driver_data<pcw16_state>();
554	544	int i;
555	545	int b;
556	546
r14963	r14964
571	561	data = data>>1;
572	562	}
573	563
574		state->m_keyboard_parity_table[i] = sum & 0x01;
	564	m_keyboard_parity_table[i] = sum & 0x01;
575	565	}
576	566
577	567
578	568	/* clear int */
579		pcw16_keyboard_int(machine, 0);
	569	pcw16_keyboard_int(0);
580	570	/* reset state */
581		state->m_keyboard_state = 0;
	571	m_keyboard_state = 0;
582	572	/* reset ready for transmit */
583		pcw16_keyboard_reset(state);
	573	pcw16_keyboard_reset();
584	574	}
585	575
586		static void pcw16_keyboard_refresh_outputs(pcw16_state *state)
	576	void pcw16_state::pcw16_keyboard_refresh_outputs()
587	577	{
588	578	/* generate output bits */
589		state->m_keyboard_bits_output = state->m_keyboard_bits;
	579	m_keyboard_bits_output = m_keyboard_bits;
590	580
591	581	/* force clock low? */
592		if (state->m_keyboard_state & PCW16_KEYBOARD_FORCE_KEYBOARD_CLOCK)
	582	if (m_keyboard_state & PCW16_KEYBOARD_FORCE_KEYBOARD_CLOCK)
593	583	{
594		state->m_keyboard_bits_output &= ~PCW16_KEYBOARD_CLOCK;
	584	m_keyboard_bits_output &= ~PCW16_KEYBOARD_CLOCK;
595	585	}
596	586	}
597	587
598		static void pcw16_keyboard_set_clock_state(pcw16_state *drvstate, int state)
	588	void pcw16_state::pcw16_keyboard_set_clock_state(int state)
599	589	{
600		drvstate->m_keyboard_bits &= ~PCW16_KEYBOARD_CLOCK;
	590	m_keyboard_bits &= ~PCW16_KEYBOARD_CLOCK;
601	591
602	592	if (state)
603	593	{
604		drvstate->m_keyboard_bits |= PCW16_KEYBOARD_CLOCK;
	594	m_keyboard_bits |= PCW16_KEYBOARD_CLOCK;
605	595	}
606	596
607		pcw16_keyboard_refresh_outputs(drvstate);
	597	pcw16_keyboard_refresh_outputs();
608	598	}
609	599
610		static void pcw16_keyboard_int(running_machine &machine, int state)
	600	void pcw16_state::pcw16_keyboard_int(int state)
611	601	{
612		pcw16_state *drvstate = machine.driver_data<pcw16_state>();
613		drvstate->m_system_status &= ~(1<<1);
	602	m_system_status &= ~(1<<1);
614	603
615	604	if (state)
616	605	{
617		drvstate->m_system_status |= (1<<1);
	606	m_system_status |= (1<<1);
618	607	}
619	608
620		pcw16_refresh_ints(machine);
	609	pcw16_refresh_ints();
621	610	}
622	611
623		static void pcw16_keyboard_reset(pcw16_state *state)
	612	void pcw16_state::pcw16_keyboard_reset()
624	613	{
625	614	/* clock set to high */
626		pcw16_keyboard_set_clock_state(state, 1);
	615	pcw16_keyboard_set_clock_state(1);
627	616	}
628	617
629	618	/* interfaces to a pc-at keyboard */
630		static READ8_HANDLER(pcw16_keyboard_data_shift_r)
	619	READ8_MEMBER(pcw16_state::pcw16_keyboard_data_shift_r)
631	620	{
632		pcw16_state *state = space->machine().driver_data<pcw16_state>();
633		//logerror("keyboard data shift r: %02x\n", state->m_keyboard_data_shift);
634		state->m_keyboard_state &= ~(PCW16_KEYBOARD_BUSY_STATUS);
	621	//logerror("keyboard data shift r: %02x\n", m_keyboard_data_shift);
	622	m_keyboard_state &= ~(PCW16_KEYBOARD_BUSY_STATUS);
635	623
636		pcw16_keyboard_int(space->machine(), 0);
	624	pcw16_keyboard_int(0);
637	625	/* reset for reception */
638		pcw16_keyboard_reset(state);
	626	pcw16_keyboard_reset();
639	627
640	628	/* read byte */
641		return state->m_keyboard_data_shift;
	629	return m_keyboard_data_shift;
642	630	}
643	631
644	632	/* if force keyboard clock is low it is safe to send */
645		static int pcw16_keyboard_can_transmit(pcw16_state *state)
	633	int pcw16_state::pcw16_keyboard_can_transmit()
646	634	{
647	635	/* clock is not forced low */
648	636	/* and not busy - i.e. not already sent a char */
649		return ((state->m_keyboard_bits_output & PCW16_KEYBOARD_CLOCK)!=0);
	637	return ((m_keyboard_bits_output & PCW16_KEYBOARD_CLOCK)!=0);
650	638	}
651	639
652	640	#ifdef UNUSED_FUNCTION
r14963	r14964
657	645	#endif
658	646
659	647	/* signal a code has been received */
660		static void pcw16_keyboard_signal_byte_received(running_machine &machine, int data)
	648	void pcw16_state::pcw16_keyboard_signal_byte_received(int data)
661	649	{
662		pcw16_state *state = machine.driver_data<pcw16_state>();
663	650	/* clear clock */
664		pcw16_keyboard_set_clock_state(state, 0);
	651	pcw16_keyboard_set_clock_state(0);
665	652
666	653	/* set code in shift register */
667		state->m_keyboard_data_shift = data;
	654	m_keyboard_data_shift = data;
668	655	/* busy */
669		state->m_keyboard_state |= PCW16_KEYBOARD_BUSY_STATUS;
	656	m_keyboard_state |= PCW16_KEYBOARD_BUSY_STATUS;
670	657
671	658	/* initialise start, stop and parity bits */
672		state->m_keyboard_state &= ~PCW16_KEYBOARD_START_BIT_MASK;
673		state->m_keyboard_state |=PCW16_KEYBOARD_STOP_BIT_MASK;
	659	m_keyboard_state &= ~PCW16_KEYBOARD_START_BIT_MASK;
	660	m_keyboard_state |=PCW16_KEYBOARD_STOP_BIT_MASK;
674	661
675	662	/* "Keyboard data has odd parity, so the parity bit in the
676	663	status register should only be set when the shift register
677	664	data itself has even parity. */
678	665
679		state->m_keyboard_state &= ~PCW16_KEYBOARD_PARITY_MASK;
	666	m_keyboard_state &= ~PCW16_KEYBOARD_PARITY_MASK;
680	667
681	668	/* if data has even parity, set parity bit */
682		if ((state->m_keyboard_parity_table[data])==0)
683		state->m_keyboard_state |= PCW16_KEYBOARD_PARITY_MASK;
	669	if ((m_keyboard_parity_table[data])==0)
	670	m_keyboard_state |= PCW16_KEYBOARD_PARITY_MASK;
684	671
685		pcw16_keyboard_int(machine, 1);
	672	pcw16_keyboard_int(1);
686	673	}
687	674
688	675
689		static WRITE8_HANDLER(pcw16_keyboard_data_shift_w)
	676	WRITE8_MEMBER(pcw16_state::pcw16_keyboard_data_shift_w)
690	677	{
691		pcw16_state *state = space->machine().driver_data<pcw16_state>();
692	678	//logerror("Keyboard Data Shift: %02x\n", data);
693	679	/* writing to shift register clears parity */
694	680	/* writing to shift register clears start bit */
695		state->m_keyboard_state &= ~(
	681	m_keyboard_state &= ~(
696	682	PCW16_KEYBOARD_PARITY_MASK |
697	683	PCW16_KEYBOARD_START_BIT_MASK);
698	684
699	685	/* writing to shift register sets stop bit */
700		state->m_keyboard_state |= PCW16_KEYBOARD_STOP_BIT_MASK;
	686	m_keyboard_state |= PCW16_KEYBOARD_STOP_BIT_MASK;
701	687
702		state->m_keyboard_data_shift = data;
	688	m_keyboard_data_shift = data;
703	689
704	690	}
705	691
706		static  READ8_HANDLER(pcw16_keyboard_status_r)
	692	READ8_MEMBER(pcw16_state::pcw16_keyboard_status_r)
707	693	{
708		pcw16_state *state = space->machine().driver_data<pcw16_state>();
709	694	/* bit 2,3 are bits 8 and 9 of vdu pointer */
710		return (state->m_keyboard_state &
	695	return (m_keyboard_state &
711	696	(PCW16_KEYBOARD_PARITY_MASK |
712	697	PCW16_KEYBOARD_STOP_BIT_MASK |
713	698	PCW16_KEYBOARD_START_BIT_MASK |
r14963	r14964
716	701	PCW16_KEYBOARD_TRANSMIT_MODE));
717	702	}
718	703
719		static WRITE8_HANDLER(pcw16_keyboard_control_w)
	704	WRITE8_MEMBER(pcw16_state::pcw16_keyboard_control_w)
720	705	{
721		pcw16_state *state = space->machine().driver_data<pcw16_state>();
722	706	//logerror("Keyboard control w: %02x\n",data);
723	707
724		state->m_keyboard_previous_state = state->m_keyboard_state;
	708	m_keyboard_previous_state = m_keyboard_state;
725	709
726	710	/* if set, set parity */
727	711	if (data & 0x080)
728	712	{
729		state->m_keyboard_state |= PCW16_KEYBOARD_PARITY_MASK;
	713	m_keyboard_state |= PCW16_KEYBOARD_PARITY_MASK;
730	714	}
731	715
732	716	/* clear read/write bits */
733		state->m_keyboard_state &=
	717	m_keyboard_state &=
734	718	~(PCW16_KEYBOARD_FORCE_KEYBOARD_CLOCK |
735	719	PCW16_KEYBOARD_TRANSMIT_MODE);
736	720	/* set read/write bits from data */
737		state->m_keyboard_state |= (data & 0x03);
	721	m_keyboard_state |= (data & 0x03);
738	722
739	723	if (data & PCW16_KEYBOARD_RESET_INTERFACE)
740	724	{
741		pcw16_keyboard_reset(state);
	725	pcw16_keyboard_reset();
742	726	}
743	727
744	728	if (data & PCW16_KEYBOARD_TRANSMIT_MODE)
745	729	{
746	730	/* force clock changed */
747		if (((state->m_keyboard_state^state->m_keyboard_previous_state) & PCW16_KEYBOARD_FORCE_KEYBOARD_CLOCK)!=0)
	731	if (((m_keyboard_state^m_keyboard_previous_state) & PCW16_KEYBOARD_FORCE_KEYBOARD_CLOCK)!=0)
748	732	{
749	733	/* just cleared? */
750		if ((state->m_keyboard_state & PCW16_KEYBOARD_FORCE_KEYBOARD_CLOCK)==0)
	734	if ((m_keyboard_state & PCW16_KEYBOARD_FORCE_KEYBOARD_CLOCK)==0)
751	735	{
752	736
753	737	/* write */
754	738	/* busy */
755		state->m_keyboard_state |= PCW16_KEYBOARD_BUSY_STATUS;
	739	m_keyboard_state |= PCW16_KEYBOARD_BUSY_STATUS;
756	740	/* keyboard takes data */
757		at_keyboard_write(space->machine(),state->m_keyboard_data_shift);
	741	at_keyboard_write(machine(),m_keyboard_data_shift);
758	742	/* set clock low - no furthur transmissions */
759		pcw16_keyboard_set_clock_state(state, 0);
	743	pcw16_keyboard_set_clock_state(0);
760	744	/* set int */
761		pcw16_keyboard_int(space->machine(), 1);
	745	pcw16_keyboard_int(1);
762	746	}
763	747	}
764	748
765	749
766	750	}
767	751
768		if (((state->m_keyboard_state^state->m_keyboard_previous_state) & PCW16_KEYBOARD_TRANSMIT_MODE)!=0)
	752	if (((m_keyboard_state^m_keyboard_previous_state) & PCW16_KEYBOARD_TRANSMIT_MODE)!=0)
769	753	{
770		if ((state->m_keyboard_state & PCW16_KEYBOARD_TRANSMIT_MODE)==0)
	754	if ((m_keyboard_state & PCW16_KEYBOARD_TRANSMIT_MODE)==0)
771	755	{
772		if ((state->m_system_status & (1<<1))!=0)
	756	if ((m_system_status & (1<<1))!=0)
773	757	{
774		pcw16_keyboard_int(space->machine(), 0);
	758	pcw16_keyboard_int(0);
775	759	}
776	760	}
777	761	}
778	762
779		pcw16_keyboard_refresh_outputs(state);
	763	pcw16_keyboard_refresh_outputs();
780	764	}
781	765
782	766
r14963	r14964
784	768	{
785	769	pcw16_state *state = timer.machine().driver_data<pcw16_state>();
786	770	at_keyboard_polling();
787		if (pcw16_keyboard_can_transmit(state))
	771	if (state->pcw16_keyboard_can_transmit())
788	772	{
789	773	int data;
790	774
r14963	r14964
797	781	//              pcw16_dump_cpu_ram();
798	782	//          }
799	783
800		pcw16_keyboard_signal_byte_received(timer.machine(), data);
	784	state->pcw16_keyboard_signal_byte_received(data);
801	785	}
802	786	}
803	787	// TODO: fix
r14963	r14964
826	810	29, 28, 28, 28
827	811	};
828	812
829		static void rtc_setup_max_days(pcw16_state *state)
	813	void pcw16_state::rtc_setup_max_days()
830	814	{
831	815	/* february? */
832		if (state->m_rtc_months == 2)
	816	if (m_rtc_months == 2)
833	817	{
834	818	/* low two bits of year select number of days in february */
835		state->m_rtc_days_max = rtc_days_in_february[state->m_rtc_years & 0x03];
	819	m_rtc_days_max = rtc_days_in_february[m_rtc_years & 0x03];
836	820	}
837	821	else
838	822	{
839		state->m_rtc_days_max = (unsigned char)rtc_days_in_each_month[state->m_rtc_months];
	823	m_rtc_days_max = (unsigned char)rtc_days_in_each_month[m_rtc_months];
840	824	}
841	825	}
842	826
r14963	r14964
891	875
892	876	}
893	877
894		rtc_setup_max_days(state);
	878	state->rtc_setup_max_days();
895	879	}
896	880
897	881	}
r14963	r14964
901	885	}
902	886	}
903	887
904		static  READ8_HANDLER(rtc_year_invalid_r)
	888	READ8_MEMBER(pcw16_state::rtc_year_invalid_r)
905	889	{
906		pcw16_state *state = space->machine().driver_data<pcw16_state>();
907		/* year in lower 7 bits. RTC Invalid status is state->m_rtc_control bit 0
	890	/* year in lower 7 bits. RTC Invalid status is m_rtc_control bit 0
908	891	inverted */
909		return (state->m_rtc_years & 0x07f) | (((state->m_rtc_control & 0x01)<<7)^0x080);
	892	return (m_rtc_years & 0x07f) | (((m_rtc_control & 0x01)<<7)^0x080);
910	893	}
911	894
912		static  READ8_HANDLER(rtc_month_r)
	895	READ8_MEMBER(pcw16_state::rtc_month_r)
913	896	{
914		pcw16_state *state = space->machine().driver_data<pcw16_state>();
915		return state->m_rtc_months;
	897	return m_rtc_months;
916	898	}
917	899
918		static  READ8_HANDLER(rtc_days_r)
	900	READ8_MEMBER(pcw16_state::rtc_days_r)
919	901	{
920		pcw16_state *state = space->machine().driver_data<pcw16_state>();
921		return state->m_rtc_days;
	902	return m_rtc_days;
922	903	}
923	904
924		static  READ8_HANDLER(rtc_hours_r)
	905	READ8_MEMBER(pcw16_state::rtc_hours_r)
925	906	{
926		pcw16_state *state = space->machine().driver_data<pcw16_state>();
927		return state->m_rtc_hours;
	907	return m_rtc_hours;
928	908	}
929	909
930		static  READ8_HANDLER(rtc_minutes_r)
	910	READ8_MEMBER(pcw16_state::rtc_minutes_r)
931	911	{
932		pcw16_state *state = space->machine().driver_data<pcw16_state>();
933		return state->m_rtc_minutes;
	912	return m_rtc_minutes;
934	913	}
935	914
936		static  READ8_HANDLER(rtc_seconds_r)
	915	READ8_MEMBER(pcw16_state::rtc_seconds_r)
937	916	{
938		pcw16_state *state = space->machine().driver_data<pcw16_state>();
939		return state->m_rtc_seconds;
	917	return m_rtc_seconds;
940	918	}
941	919
942		static  READ8_HANDLER(rtc_256ths_seconds_r)
	920	READ8_MEMBER(pcw16_state::rtc_256ths_seconds_r)
943	921	{
944		pcw16_state *state = space->machine().driver_data<pcw16_state>();
945		return state->m_rtc_256ths_seconds;
	922	return m_rtc_256ths_seconds;
946	923	}
947	924
948		static WRITE8_HANDLER(rtc_control_w)
	925	WRITE8_MEMBER(pcw16_state::rtc_control_w)
949	926	{
950		pcw16_state *state = space->machine().driver_data<pcw16_state>();
951	927	/* write control */
952		state->m_rtc_control = data;
	928	m_rtc_control = data;
953	929	}
954	930
955		static WRITE8_HANDLER(rtc_seconds_w)
	931	WRITE8_MEMBER(pcw16_state::rtc_seconds_w)
956	932	{
957		pcw16_state *state = space->machine().driver_data<pcw16_state>();
958	933	/* TODO: Writing register could cause next to increment! */
959		state->m_rtc_seconds = data;
	934	m_rtc_seconds = data;
960	935	}
961	936
962		static WRITE8_HANDLER(rtc_minutes_w)
	937	WRITE8_MEMBER(pcw16_state::rtc_minutes_w)
963	938	{
964		pcw16_state *state = space->machine().driver_data<pcw16_state>();
965	939	/* TODO: Writing register could cause next to increment! */
966		state->m_rtc_minutes = data;
	940	m_rtc_minutes = data;
967	941	}
968	942
969		static WRITE8_HANDLER(rtc_hours_w)
	943	WRITE8_MEMBER(pcw16_state::rtc_hours_w)
970	944	{
971		pcw16_state *state = space->machine().driver_data<pcw16_state>();
972	945	/* TODO: Writing register could cause next to increment! */
973		state->m_rtc_hours = data;
	946	m_rtc_hours = data;
974	947	}
975	948
976		static WRITE8_HANDLER(rtc_days_w)
	949	WRITE8_MEMBER(pcw16_state::rtc_days_w)
977	950	{
978		pcw16_state *state = space->machine().driver_data<pcw16_state>();
979	951	/* TODO: Writing register could cause next to increment! */
980		state->m_rtc_days = data;
	952	m_rtc_days = data;
981	953	}
982	954
983		static WRITE8_HANDLER(rtc_month_w)
	955	WRITE8_MEMBER(pcw16_state::rtc_month_w)
984	956	{
985		pcw16_state *state = space->machine().driver_data<pcw16_state>();
986	957	/* TODO: Writing register could cause next to increment! */
987		state->m_rtc_months = data;
	958	m_rtc_months = data;
988	959
989		rtc_setup_max_days(state);
	960	rtc_setup_max_days();
990	961	}
991	962
992	963
993		static WRITE8_HANDLER(rtc_year_w)
	964	WRITE8_MEMBER(pcw16_state::rtc_year_w)
994	965	{
995		pcw16_state *state = space->machine().driver_data<pcw16_state>();
996	966	/* TODO: Writing register could cause next to increment! */
997		state->m_rtc_hours = data;
	967	m_rtc_hours = data;
998	968
999		rtc_setup_max_days(state);
	969	rtc_setup_max_days();
1000	970	}
1001	971
1002	972
r14963	r14964
1033	1003	/* attach fdc to int */
1034	1004	case 1:
1035	1005	{
1036		pcw16_refresh_ints(machine);
	1006	drvstate->pcw16_refresh_ints();
1037	1007	}
1038	1008	break;
1039	1009
r14963	r14964
1045	1015	drvstate->m_previous_fdc_int_state = state;
1046	1016	}
1047	1017
1048		static READ8_HANDLER(pcw16_system_status_r)
	1018	READ8_MEMBER(pcw16_state::pcw16_system_status_r)
1049	1019	{
1050		pcw16_state *state = space->machine().driver_data<pcw16_state>();
1051	1020	//  logerror("system status r: \n");
1052	1021
1053		return state->m_system_status | (input_port_read(space->machine(), "EXTRA") & 0x04);
	1022	return m_system_status | (input_port_read(machine(), "EXTRA") & 0x04);
1054	1023	}
1055	1024
1056		static READ8_HANDLER(pcw16_timer_interrupt_counter_r)
	1025	READ8_MEMBER(pcw16_state::pcw16_timer_interrupt_counter_r)
1057	1026	{
1058		pcw16_state *state = space->machine().driver_data<pcw16_state>();
1059	1027	int data;
1060	1028
1061		data = state->m_interrupt_counter;
	1029	data = m_interrupt_counter;
1062	1030
1063		state->m_interrupt_counter = 0;
	1031	m_interrupt_counter = 0;
1064	1032	/* clear display int */
1065		state->m_system_status &= ~(1<<0);
	1033	m_system_status &= ~(1<<0);
1066	1034
1067		pcw16_refresh_ints(space->machine());
	1035	pcw16_refresh_ints();
1068	1036
1069	1037	return data;
1070	1038	}
1071	1039
1072	1040
1073		static WRITE8_HANDLER(pcw16_system_control_w)
	1041	WRITE8_MEMBER(pcw16_state::pcw16_system_control_w)
1074	1042	{
1075		pcw16_state *state = space->machine().driver_data<pcw16_state>();
1076		device_t *speaker = space->machine().device(BEEPER_TAG);
	1043	device_t *speaker = machine().device(BEEPER_TAG);
1077	1044	//logerror("0x0f8: function: %d\n",data);
1078	1045
1079	1046	/* lower 4 bits define function code */
r14963	r14964
1094	1061	/* connect IRQ6 input to /NMI */
1095	1062	case 0x02:
1096	1063	{
1097		state->m_fdc_int_code = 0;
	1064	m_fdc_int_code = 0;
1098	1065	}
1099	1066	break;
1100	1067
1101	1068	/* connect IRQ6 input to /INT */
1102	1069	case 0x03:
1103	1070	{
1104		state->m_fdc_int_code = 1;
	1071	m_fdc_int_code = 1;
1105	1072	}
1106	1073	break;
1107	1074
1108	1075	/* dis-connect IRQ6 input from /NMI and /INT */
1109	1076	case 0x04:
1110	1077	{
1111		state->m_fdc_int_code = 2;
	1078	m_fdc_int_code = 2;
1112	1079	}
1113	1080	break;
1114	1081
1115	1082	/* set terminal count */
1116	1083	case 0x05:
1117	1084	{
1118		pc_fdc_set_tc_state(space->machine(), 1);
	1085	pc_fdc_set_tc_state(machine(), 1);
1119	1086	}
1120	1087	break;
1121	1088
1122	1089	/* clear terminal count */
1123	1090	case 0x06:
1124	1091	{
1125		pc_fdc_set_tc_state(space->machine(), 0);
	1092	pc_fdc_set_tc_state(machine(), 0);
1126	1093	}
1127	1094	break;
1128	1095
r14963	r14964
1160	1127	/* bit 5 - green/red led (1==green)*/
1161	1128	/* bit 4 - monitor on/off (1==on) */
1162	1129
1163		state->m_4_bit_port = data>>4;
	1130	m_4_bit_port = data>>4;
1164	1131
1165	1132
1166	1133	}
r14963	r14964
1171	1138	/**** SUPER I/O connections */
1172	1139
1173	1140	/* write to Super I/O chip. FDC Data Rate. */
1174		static WRITE8_HANDLER(pcw16_superio_fdc_datarate_w)
	1141	WRITE8_MEMBER(pcw16_state::pcw16_superio_fdc_datarate_w)
1175	1142	{
1176		pc_fdc_w(space, PC_FDC_DATA_RATE_REGISTER,data);
	1143	pc_fdc_w(&space, PC_FDC_DATA_RATE_REGISTER,data);
1177	1144	}
1178	1145
1179	1146	/* write to Super I/O chip. FDC Digital output register */
1180		static WRITE8_HANDLER(pcw16_superio_fdc_digital_output_register_w)
	1147	WRITE8_MEMBER(pcw16_state::pcw16_superio_fdc_digital_output_register_w)
1181	1148	{
1182		pc_fdc_w(space, PC_FDC_DIGITAL_OUTPUT_REGISTER, data);
	1149	pc_fdc_w(&space, PC_FDC_DIGITAL_OUTPUT_REGISTER, data);
1183	1150	}
1184	1151
1185	1152	/* write to Super I/O chip. FDC Data Register */
1186		static WRITE8_HANDLER(pcw16_superio_fdc_data_w)
	1153	WRITE8_MEMBER(pcw16_state::pcw16_superio_fdc_data_w)
1187	1154	{
1188		pc_fdc_w(space, PC_FDC_DATA_REGISTER, data);
	1155	pc_fdc_w(&space, PC_FDC_DATA_REGISTER, data);
1189	1156	}
1190	1157
1191	1158	/* write to Super I/O chip. FDC Data Register */
1192		static  READ8_HANDLER(pcw16_superio_fdc_data_r)
	1159	READ8_MEMBER(pcw16_state::pcw16_superio_fdc_data_r)
1193	1160	{
1194		return pc_fdc_r(space, PC_FDC_DATA_REGISTER);
	1161	return pc_fdc_r(&space, PC_FDC_DATA_REGISTER);
1195	1162	}
1196	1163
1197	1164	/* write to Super I/O chip. FDC Main Status Register */
1198		static  READ8_HANDLER(pcw16_superio_fdc_main_status_register_r)
	1165	READ8_MEMBER(pcw16_state::pcw16_superio_fdc_main_status_register_r)
1199	1166	{
1200		return pc_fdc_r(space, PC_FDC_MAIN_STATUS_REGISTER);
	1167	return pc_fdc_r(&space, PC_FDC_MAIN_STATUS_REGISTER);
1201	1168	}
1202	1169
1203		static  READ8_HANDLER(pcw16_superio_fdc_digital_input_register_r)
	1170	READ8_MEMBER(pcw16_state::pcw16_superio_fdc_digital_input_register_r)
1204	1171	{
1205		return pc_fdc_r(space, PC_FDC_DIGITIAL_INPUT_REGISTER);
	1172	return pc_fdc_r(&space, PC_FDC_DIGITIAL_INPUT_REGISTER);
1206	1173	}
1207	1174
1208	1175	static void pcw16_fdc_interrupt(running_machine &machine, int state)
r14963	r14964
1243	1210	drvstate->m_system_status |= (1 << 4);
1244	1211	}
1245	1212
1246		pcw16_refresh_ints(device->machine());
	1213	drvstate->pcw16_refresh_ints();
1247	1214	}
1248	1215
1249	1216
r14963	r14964
1256	1223	drvstate->m_system_status |= (1 << 3);
1257	1224	}
1258	1225
1259		pcw16_refresh_ints(device->machine());
	1226	drvstate->pcw16_refresh_ints();
1260	1227	}
1261	1228
1262	1229	static WRITE_LINE_DEVICE_HANDLER( pcw16_com_tx_0 ) { }
r14963	r14964
1292	1259	static ADDRESS_MAP_START(pcw16_io, AS_IO, 8, pcw16_state )
1293	1260	ADDRESS_MAP_GLOBAL_MASK(0xff)
1294	1261	/* super i/o chip */
1295		AM_RANGE(0x01a, 0x01a) AM_WRITE_LEGACY(pcw16_superio_fdc_digital_output_register_w)
1296		AM_RANGE(0x01c, 0x01c) AM_READ_LEGACY(pcw16_superio_fdc_main_status_register_r)
1297		AM_RANGE(0x01d, 0x01d) AM_READWRITE_LEGACY(pcw16_superio_fdc_data_r, pcw16_superio_fdc_data_w)
1298		AM_RANGE(0x01f, 0x01f) AM_READWRITE_LEGACY(pcw16_superio_fdc_digital_input_register_r, pcw16_superio_fdc_datarate_w)
	1262	AM_RANGE(0x01a, 0x01a) AM_WRITE(pcw16_superio_fdc_digital_output_register_w)
	1263	AM_RANGE(0x01c, 0x01c) AM_READ(pcw16_superio_fdc_main_status_register_r)
	1264	AM_RANGE(0x01d, 0x01d) AM_READWRITE(pcw16_superio_fdc_data_r, pcw16_superio_fdc_data_w)
	1265	AM_RANGE(0x01f, 0x01f) AM_READWRITE(pcw16_superio_fdc_digital_input_register_r, pcw16_superio_fdc_datarate_w)
1299	1266	AM_RANGE(0x020, 0x027) AM_DEVREADWRITE("ns16550_1", ns16550_device, ins8250_r, ins8250_w)
1300	1267	AM_RANGE(0x028, 0x02f) AM_DEVREADWRITE("ns16550_2", ns16550_device, ins8250_r, ins8250_w)
1301	1268	AM_RANGE(0x038, 0x03a) AM_DEVREADWRITE_LEGACY("lpt", pc_lpt_r, pc_lpt_w)
1302	1269	/* anne asic */
1303		AM_RANGE(0x0e0, 0x0ef) AM_WRITE_LEGACY(pcw16_palette_w)
1304		AM_RANGE(0x0f0, 0x0f3) AM_READWRITE_LEGACY(pcw16_bankhw_r, pcw16_bankhw_w)
1305		AM_RANGE(0x0f4, 0x0f4) AM_READWRITE_LEGACY(pcw16_keyboard_data_shift_r, pcw16_keyboard_data_shift_w)
1306		AM_RANGE(0x0f5, 0x0f5) AM_READWRITE_LEGACY(pcw16_keyboard_status_r, pcw16_keyboard_control_w)
1307		AM_RANGE(0x0f7, 0x0f7) AM_READWRITE_LEGACY(pcw16_timer_interrupt_counter_r, pcw16_video_control_w)
1308		AM_RANGE(0x0f8, 0x0f8) AM_READWRITE_LEGACY(pcw16_system_status_r, pcw16_system_control_w)
1309		AM_RANGE(0x0f9, 0x0f9) AM_READWRITE_LEGACY(rtc_256ths_seconds_r, rtc_control_w)
1310		AM_RANGE(0x0fa, 0x0fa) AM_READWRITE_LEGACY(rtc_seconds_r, rtc_seconds_w)
1311		AM_RANGE(0x0fb, 0x0fb) AM_READWRITE_LEGACY(rtc_minutes_r, rtc_minutes_w)
1312		AM_RANGE(0x0fc, 0x0fc) AM_READWRITE_LEGACY(rtc_hours_r, rtc_hours_w)
1313		AM_RANGE(0x0fd, 0x0fd) AM_READWRITE_LEGACY(rtc_days_r, rtc_days_w)
1314		AM_RANGE(0x0fe, 0x0fe) AM_READWRITE_LEGACY(rtc_month_r, rtc_month_w)
1315		AM_RANGE(0x0ff, 0x0ff) AM_READWRITE_LEGACY(rtc_year_invalid_r, rtc_year_w)
	1270	AM_RANGE(0x0e0, 0x0ef) AM_WRITE(pcw16_palette_w)
	1271	AM_RANGE(0x0f0, 0x0f3) AM_READWRITE(pcw16_bankhw_r, pcw16_bankhw_w)
	1272	AM_RANGE(0x0f4, 0x0f4) AM_READWRITE(pcw16_keyboard_data_shift_r, pcw16_keyboard_data_shift_w)
	1273	AM_RANGE(0x0f5, 0x0f5) AM_READWRITE(pcw16_keyboard_status_r, pcw16_keyboard_control_w)
	1274	AM_RANGE(0x0f7, 0x0f7) AM_READWRITE(pcw16_timer_interrupt_counter_r, pcw16_video_control_w)
	1275	AM_RANGE(0x0f8, 0x0f8) AM_READWRITE(pcw16_system_status_r, pcw16_system_control_w)
	1276	AM_RANGE(0x0f9, 0x0f9) AM_READWRITE(rtc_256ths_seconds_r, rtc_control_w)
	1277	AM_RANGE(0x0fa, 0x0fa) AM_READWRITE(rtc_seconds_r, rtc_seconds_w)
	1278	AM_RANGE(0x0fb, 0x0fb) AM_READWRITE(rtc_minutes_r, rtc_minutes_w)
	1279	AM_RANGE(0x0fc, 0x0fc) AM_READWRITE(rtc_hours_r, rtc_hours_w)
	1280	AM_RANGE(0x0fd, 0x0fd) AM_READWRITE(rtc_days_r, rtc_days_w)
	1281	AM_RANGE(0x0fe, 0x0fe) AM_READWRITE(rtc_month_r, rtc_month_w)
	1282	AM_RANGE(0x0ff, 0x0ff) AM_READWRITE(rtc_year_invalid_r, rtc_year_w)
1316	1283	ADDRESS_MAP_END
1317	1284
1318	1285
r14963	r14964
1338	1305	state->m_rtc_control = 1;
1339	1306	state->m_rtc_256ths_seconds = 0;
1340	1307
1341		pcw16_keyboard_init(machine);
	1308	state->pcw16_keyboard_init();
1342	1309	}
1343	1310
1344	1311

src/mess/drivers/msx.c

r14963	r14964
1013	1013	{
1014	1014	AY8910_LEGACY_OUTPUT,
1015	1015	AY8910_DEFAULT_LOADS,
1016		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, msx_psg_port_a_r),
1017		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, msx_psg_port_b_r),
1018		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, msx_psg_port_a_w),
1019		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, msx_psg_port_b_w)
	1016	DEVCB_DRIVER_MEMBER(msx_state, msx_psg_port_a_r),
	1017	DEVCB_DRIVER_MEMBER(msx_state, msx_psg_port_b_r),
	1018	DEVCB_DRIVER_MEMBER(msx_state, msx_psg_port_a_w),
	1019	DEVCB_DRIVER_MEMBER(msx_state, msx_psg_port_b_w)
1020	1020	};
1021	1021
1022	1022	#define MSX_XBORDER_PIXELS      15

src/mess/drivers/mz700.c

r14963	r14964
105	105
106	106	static ADDRESS_MAP_START( mz700_io, AS_IO, 8, mz_state )
107	107	ADDRESS_MAP_GLOBAL_MASK(0xff)
108		AM_RANGE(0xe0, 0xe0) AM_WRITE_LEGACY(mz700_bank_0_w)
109		AM_RANGE(0xe1, 0xe1) AM_WRITE_LEGACY(mz700_bank_1_w)
110		AM_RANGE(0xe2, 0xe2) AM_WRITE_LEGACY(mz700_bank_2_w)
111		AM_RANGE(0xe3, 0xe3) AM_WRITE_LEGACY(mz700_bank_3_w)
112		AM_RANGE(0xe4, 0xe4) AM_WRITE_LEGACY(mz700_bank_4_w)
113		AM_RANGE(0xe5, 0xe5) AM_WRITE_LEGACY(mz700_bank_5_w)
114		AM_RANGE(0xe6, 0xe6) AM_WRITE_LEGACY(mz700_bank_6_w)
	108	AM_RANGE(0xe0, 0xe0) AM_WRITE(mz700_bank_0_w)
	109	AM_RANGE(0xe1, 0xe1) AM_WRITE(mz700_bank_1_w)
	110	AM_RANGE(0xe2, 0xe2) AM_WRITE(mz700_bank_2_w)
	111	AM_RANGE(0xe3, 0xe3) AM_WRITE(mz700_bank_3_w)
	112	AM_RANGE(0xe4, 0xe4) AM_WRITE(mz700_bank_4_w)
	113	AM_RANGE(0xe5, 0xe5) AM_WRITE(mz700_bank_5_w)
	114	AM_RANGE(0xe6, 0xe6) AM_WRITE(mz700_bank_6_w)
115	115	ADDRESS_MAP_END
116	116
117	117	static ADDRESS_MAP_START( mz800_mem, AS_PROGRAM, 8, mz_state )
r14963	r14964
119	119
120	120	static ADDRESS_MAP_START( mz800_io, AS_IO, 8, mz_state )
121	121	ADDRESS_MAP_GLOBAL_MASK(0xff)
122		AM_RANGE(0xcc, 0xcc) AM_WRITE_LEGACY(mz800_write_format_w )
123		AM_RANGE(0xcd, 0xcd) AM_WRITE_LEGACY(mz800_read_format_w )
124		AM_RANGE(0xce, 0xce) AM_READWRITE_LEGACY(mz800_crtc_r, mz800_display_mode_w )
125		AM_RANGE(0xcf, 0xcf) AM_WRITE_LEGACY(mz800_scroll_border_w )
	122	AM_RANGE(0xcc, 0xcc) AM_WRITE(mz800_write_format_w )
	123	AM_RANGE(0xcd, 0xcd) AM_WRITE(mz800_read_format_w )
	124	AM_RANGE(0xce, 0xce) AM_READWRITE(mz800_crtc_r, mz800_display_mode_w )
	125	AM_RANGE(0xcf, 0xcf) AM_WRITE(mz800_scroll_border_w )
126	126	AM_RANGE(0xd0, 0xd3) AM_DEVREADWRITE("ppi8255", i8255_device, read, write)
127	127	AM_RANGE(0xd4, 0xd7) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r, pit8253_w)
128		AM_RANGE(0xe0, 0xe0) AM_READWRITE_LEGACY(mz800_bank_0_r, mz800_bank_0_w)
129		AM_RANGE(0xe1, 0xe1) AM_READWRITE_LEGACY(mz800_bank_1_r, mz700_bank_1_w)
130		AM_RANGE(0xe2, 0xe2) AM_WRITE_LEGACY(mz700_bank_2_w)
131		AM_RANGE(0xe3, 0xe3) AM_WRITE_LEGACY(mz700_bank_3_w)
132		AM_RANGE(0xe4, 0xe4) AM_WRITE_LEGACY(mz700_bank_4_w)
133		AM_RANGE(0xe5, 0xe5) AM_WRITE_LEGACY(mz700_bank_5_w)
134		AM_RANGE(0xe6, 0xe6) AM_WRITE_LEGACY(mz700_bank_6_w)
135		AM_RANGE(0xea, 0xea) AM_READWRITE_LEGACY(mz800_ramdisk_r, mz800_ramdisk_w )
136		AM_RANGE(0xeb, 0xeb) AM_WRITE_LEGACY(mz800_ramaddr_w )
137		AM_RANGE(0xf0, 0xf0) AM_READ_PORT("atari_joy1") AM_WRITE_LEGACY(mz800_palette_w)
	128	AM_RANGE(0xe0, 0xe0) AM_READWRITE(mz800_bank_0_r, mz800_bank_0_w)
	129	AM_RANGE(0xe1, 0xe1) AM_READWRITE(mz800_bank_1_r, mz700_bank_1_w)
	130	AM_RANGE(0xe2, 0xe2) AM_WRITE(mz700_bank_2_w)
	131	AM_RANGE(0xe3, 0xe3) AM_WRITE(mz700_bank_3_w)
	132	AM_RANGE(0xe4, 0xe4) AM_WRITE(mz700_bank_4_w)
	133	AM_RANGE(0xe5, 0xe5) AM_WRITE(mz700_bank_5_w)
	134	AM_RANGE(0xe6, 0xe6) AM_WRITE(mz700_bank_6_w)
	135	AM_RANGE(0xea, 0xea) AM_READWRITE(mz800_ramdisk_r, mz800_ramdisk_w )
	136	AM_RANGE(0xeb, 0xeb) AM_WRITE(mz800_ramaddr_w )
	137	AM_RANGE(0xf0, 0xf0) AM_READ_PORT("atari_joy1") AM_WRITE(mz800_palette_w)
138	138	AM_RANGE(0xf1, 0xf1) AM_READ_PORT("atari_joy2")
139	139	AM_RANGE(0xf2, 0xf2) AM_DEVWRITE_LEGACY("sn76489n", sn76496_w)
140	140	AM_RANGE(0xfc, 0xfd) AM_DEVREADWRITE_LEGACY("z80pio", z80pio_c_r, z80pio_c_w)

src/mess/drivers/apollo.c

r14963	r14964
297	297	DN3500 Cache Control/Status Register at 0x10200
298	298	***************************************************************************/
299	299
300		static WRITE8_HANDLER(cache_control_register_w ) {
	300	WRITE8_MEMBER(apollo_state::cache_control_register_w){
301	301	if (apollo_is_dn5500())
302	302	{
303	303	SLOG1(("Error: writing DN5500 Cache Status Register at offset %02x = %02x", offset, data));
r14963	r14964
310	310	}
311	311	}
312	312
313		static READ8_HANDLER( cache_status_register_r ) {
	313	READ8_MEMBER(apollo_state::cache_status_register_r){
314	314	UINT8 data = cache_status_register;
315	315
316	316	if (apollo_is_dn5500()) {
r14963	r14964
336	336	DN3500 Task Alias Register at 0x10300
337	337	***************************************************************************/
338	338
339		static WRITE8_HANDLER(task_alias_register_w ) {
	339	WRITE8_MEMBER(apollo_state::task_alias_register_w){
340	340	task_alias_register = data;
341	341	apollo_set_cache_status_register(0x07,  data);
342	342	SLOG(("writing Task Alias Register at offset %02x = %02x",offset, data));
343	343	}
344	344
345		static READ8_HANDLER( task_alias_register_r ) {
	345	READ8_MEMBER(apollo_state::task_alias_register_r){
346	346	UINT8 data = 0xff;
347	347	SLOG(("reading Task Alias Register at offset %02x = %02x", offset, data));
348	348	return data;
r14963	r14964
352	352	DN3000/DN3500 Node Id PROM at 0x9600/0x11200
353	353	***************************************************************************/
354	354
355		static WRITE16_HANDLER(apollo_node_id_w ) {
	355	WRITE16_MEMBER(apollo_state::apollo_node_id_w){
356	356	SLOG1(("Error: writing node id ROM at offset %02x = %04x & %04x", offset, data, mem_mask));
357	357	}
358	358
359		static READ16_HANDLER( apollo_node_id_r ) {
	359	READ16_MEMBER(apollo_state::apollo_node_id_r){
360	360	UINT16 data;
361	361	switch (offset & 0x0f) {
362	362	case 1: // msb
r14963	r14964
384	384	DN3000/DN3500 Latch Page on Parity Error Register at 0x9300/0x11300
385	385	***************************************************************************/
386	386
387		static WRITE16_HANDLER(latch_page_on_parity_error_register_w ) {
	387	WRITE16_MEMBER(apollo_state::latch_page_on_parity_error_register_w){
388	388	latch_page_on_parity_error_register = data;
389	389	SLOG1(("writing Latch Page on Error Parity Register at offset %02x = %04x", offset*2, data));
390	390	}
391	391
392		static READ16_HANDLER( latch_page_on_parity_error_register_r ) {
	392	READ16_MEMBER(apollo_state::latch_page_on_parity_error_register_r){
393	393	UINT16 data = latch_page_on_parity_error_register;
394	394	SLOG2(("reading Latch Page on Error Parity Register at offset %02x = %04x", offset*2, data));
395	395	return data;
r14963	r14964
399	399	DN3500 Master REQ Register at 0x11600
400	400	***************************************************************************/
401	401
402		static WRITE8_HANDLER(master_req_register_w ) {
	402	WRITE8_MEMBER(apollo_state::master_req_register_w){
403	403	master_req_register = data;
404	404	SLOG2(("writing Master REQ Register at offset %02x = %02x", offset, data));
405	405	}
406	406
407		static READ8_HANDLER( master_req_register_r ) {
	407	READ8_MEMBER(apollo_state::master_req_register_r){
408	408	UINT8 data = 0xff;
409	409	SLOG1(("reading Master REQ Register at offset %02x = %02x", offset, data));
410	410	return data;
r14963	r14964
414	414	DN3500 Selective Clear Locations at 0x11600
415	415	***************************************************************************/
416	416
417		static WRITE16_HANDLER(selective_clear_locations_w ) {
	417	WRITE16_MEMBER(apollo_state::selective_clear_locations_w){
418	418	SLOG2(("writing Selective Clear Locations at offset %02x = %02x", offset*2, data));
419	419	switch (offset * 2) {
420	420	case 0x00: // Clear All
r14963	r14964
434	434	}
435	435	}
436	436
437		static READ16_HANDLER(selective_clear_locations_r ) {
	437	READ16_MEMBER(apollo_state::selective_clear_locations_r){
438	438	UINT16 data = 0xffff;
439	439	SLOG1(("reading Selective Clear Locations at offset %02x = %02x", offset*2, data));
440	440	return data;
r14963	r14964
444	444	DN3000/DN3500 RAM with parity (and null proc loop delay for DomainOS)
445	445	***************************************************************************/
446	446
447		static READ32_HANDLER( ram_with_parity_r ) {
	447	READ32_MEMBER(apollo_state::ram_with_parity_r){
448	448	UINT32 data = messram_ptr.u32[parity_error_offset+offset];
449	449
450	450	SLOG2(("memory dword read with parity error at %08x = %08x & %08x parity_byte=%04x",
r14963	r14964
457	457
458	458	if (apollo_csr_get_control_register() & APOLLO_CSR_CR_INTERRUPT_ENABLE) {
459	459	// force parity error (if NMI is enabled)
460		//          cpu_set_input_line_and_vector(&space->device(), 7, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
461		cputag_set_input_line_and_vector(space->machine(), MAINCPU, 7, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	460	//          cpu_set_input_line_and_vector(&space.device(), 7, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	461	cputag_set_input_line_and_vector(machine(), MAINCPU, 7, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
462	462
463	463	}
464	464	}
465	465	return data;
466	466	}
467	467
468		static WRITE32_HANDLER( ram_with_parity_w ) {
	468	WRITE32_MEMBER(apollo_state::ram_with_parity_w){
469	469
470	470	COMBINE_DATA(messram_ptr.u32+offset);
471	471
r14963	r14964
486	486	// no more than 192 read/write handlers may be used
487	487	// see table_assign_handler in memory.c
488	488	if (parity_error_handler_install_counter < 40) {
489		//memory_install_read32_handler(space, ram_base_address+offset*4, ram_base_address+offset*4+3, 0xffffffff, 0, ram_with_parity_r);
490		space->install_legacy_read_handler(ram_base_address+offset*4, ram_base_address+offset*4+3, 0xffffffff,0,FUNC(ram_with_parity_r));
	489	//memory_install_read32_handler(&space, ram_base_address+offset*4, ram_base_address+offset*4+3, 0xffffffff, 0, ram_with_parity_r);
	490	space.install_read_handler(ram_base_address+offset*4, ram_base_address+offset*4+3, 0xffffffff,0,read32_delegate(FUNC(apollo_state::ram_with_parity_r),this));
491	491	parity_error_handler_is_installed = 1;
492	492	parity_error_handler_install_counter++;
493	493	}
r14963	r14964
498	498
499	499	// uninstall not supported, reinstall previous read handler instead
500	500
501		// memory_install_rom(space, ram_base_address, ram_end_address, 0xffffffff, 0, messram_ptr.v);
502		space->install_rom(ram_base_address,ram_end_address,0xffffffff,0,messram_ptr.v);
	501	// memory_install_rom(&space, ram_base_address, ram_end_address, 0xffffffff, 0, messram_ptr.v);
	502	space.install_rom(ram_base_address,ram_end_address,0xffffffff,0,messram_ptr.v);
503	503
504	504	parity_error_handler_is_installed = 0;
505	505	parity_error_byte_mask = 0;
r14963	r14964
510	510	DN3000/DN3500 unmapped memory
511	511	***************************************************************************/
512	512
513		static READ32_HANDLER( apollo_unmapped_r )
	513	READ32_MEMBER(apollo_state::apollo_unmapped_r)
514	514	{
515	515	offs_t address = offset * 4;
516	516
517		m68ki_cpu_core *m68k = (m68ki_cpu_core *) downcast<legacy_cpu_device *>(&space->device())->token();
	517	m68ki_cpu_core *m68k = (m68ki_cpu_core *) downcast<legacy_cpu_device *>(&space.device())->token();
518	518
519	519	if ((address & 0xfff00000) == 0xfa800000 && VERBOSE < 2) {
520	520	// ?
521	521	} else if ((address & 0xfff00ff7) == 0xfd800000 && VERBOSE < 2) {
522		// omit logging for memory sizing in FPA address space
	522	// omit logging for memory sizing in FPA address &space
523	523	// strange: MD seems to search for the 3C505 Boot ROM
524		// note (6.10.2010): might be color7 address space (!?!)
	524	// note (6.10.2010): might be color7 address &space (!?!)
525	525	} else if ((address & 0xfc03ffff) == 0x00000000 && VERBOSE < 2) {
526	526	// omit logging for memory sizing in standalone utilities
527	527	} else if (address == 0xfff90000 && VERBOSE < 2) {
r14963	r14964
535	535	}
536	536
537	537	/* unmapped; access causes a bus error */
538		apollo_bus_error(space->machine());
	538	apollo_bus_error(machine());
539	539	return 0xffffffff;
540	540	}
541	541
542		static WRITE32_HANDLER( apollo_unmapped_w )
	542	WRITE32_MEMBER(apollo_state::apollo_unmapped_w)
543	543	{
544	544	SLOG(("unmapped memory dword write to %08x = %08x & %08x", offset * 4, data, mem_mask));
545	545
546	546	/* unmapped; access causes a bus error */
547		apollo_bus_error(space->machine());
	547	apollo_bus_error(machine());
548	548	}
549	549
550	550	/***************************************************************************
551	551	DN3000/DN3500 ROM write
552	552	***************************************************************************/
553	553
554		static WRITE32_HANDLER( apollo_rom_w )
	554	WRITE32_MEMBER(apollo_state::apollo_rom_w)
555	555	{
556	556	offs_t address =  offset * 4;
557		offs_t pc = cpu_get_previouspc(&space->device());
	557	offs_t pc = cpu_get_previouspc(&space.device());
558	558
559	559	if (pc == 0x00002c1c && address == 0x00000004 && VERBOSE < 2) {
560	560	// don't log invalid code in 3500_boot_12191_7.bin
r14963	r14964
567	567	DN3000/DN3500 AT Bus I/O space
568	568	***************************************************************************/
569	569
570		static READ16_HANDLER( apollo_atbus_io_r ) {
	570	READ16_MEMBER(apollo_state::apollo_atbus_io_r){
571	571	UINT16 data = 0xffff;
572	572	offs_t address = ATBUS_IO_BASE + offset * 2;
573	573
r14963	r14964
600	600	return data;
601	601	}
602	602
603		static WRITE16_HANDLER( apollo_atbus_io_w ) {
	603	WRITE16_MEMBER(apollo_state::apollo_atbus_io_w){
604	604	offs_t address = ATBUS_IO_BASE + offset * 2;
605	605
606	606	switch (address & ~7) {
r14963	r14964
635	635	DN3000/DN3500 AT Bus memory space
636	636	***************************************************************************/
637	637
638		static READ32_HANDLER( apollo_atbus_memory_r ) {
	638	READ32_MEMBER(apollo_state::apollo_atbus_memory_r){
639	639	UINT32 data = 0xffffffff;
640	640	offs_t address = ATBUS_MEMORY_BASE +  offset * 4;
641	641	if (VERBOSE < 2 && (address & 0xfff) == 0 && address >= 0x80000 && address < 0x1000000) {
r14963	r14964
651	651	return data;
652	652	}
653	653
654		static WRITE32_HANDLER( apollo_atbus_memory_w ) {
	654	WRITE32_MEMBER(apollo_state::apollo_atbus_memory_w){
655	655	SLOG1(("AT Bus memory dword write to %08x = %08x & %08x ",
656	656	ATBUS_MEMORY_BASE+offset * 4, data, mem_mask));
657	657
r14963	r14964
665	665	Strange: documented but not used
666	666	***************************************************************************/
667	667
668		static WRITE8_HANDLER( dn5500_memory_present_register_w ) {
	668	WRITE8_MEMBER(apollo_state::dn5500_memory_present_register_w){
669	669	SLOG(("Error: writing DN5500 Memory Present Register at offset %02x = %02x", offset, data));
670	670	}
671	671
672		static READ8_HANDLER( dn5500_memory_present_register_r ) {
	672	READ8_MEMBER(apollo_state::dn5500_memory_present_register_r){
673	673	UINT8 data = DN5500_MEM_PRESENT_BYTE;
674	674	SLOG(("reading DN5500 Memory Present Register at offset %02x = %02x", offset, data));
675	675	return data;
r14963	r14964
679	679	DN5500 11500 Registers at 0x11500-0x115ff (undocumented, what does it do?)
680	680	***************************************************************************/
681	681
682		static WRITE8_HANDLER( dn5500_11500_w ) {
	682	WRITE8_MEMBER(apollo_state::dn5500_11500_w){
683	683	SLOG1(("writing DN5500 11500 at offset %02x = %02x", offset, data));
684	684	}
685	685
686		static READ8_HANDLER( dn5500_11500_r ) {
	686	READ8_MEMBER(apollo_state::dn5500_11500_r){
687	687	UINT8 data = 0xff;
688	688	SLOG1(("reading DN5500 11500 at offset %02x = %02x", offset, data));
689	689	return data;
r14963	r14964
693	693	DN5500 I/O Protection Map at 0x7000000-0x700FFFF
694	694	***************************************************************************/
695	695
696		static WRITE8_HANDLER(dn5500_io_protection_map_w ) {
	696	WRITE8_MEMBER(apollo_state::dn5500_io_protection_map_w){
697	697	// TODO
698	698	SLOG1(("writing DN5500 I/O Protection Map at offset %02x = %02x", offset, data));
699	699	}
700	700
701		static READ8_HANDLER( dn5500_io_protection_map_r ) {
	701	READ8_MEMBER(apollo_state::dn5500_io_protection_map_r){
702	702	UINT8 data = 0xff;
703	703	SLOG1(("reading DN5500 I/O Protection Map at offset %02x = %02x", offset, data));
704	704	return data;
r14963	r14964
709	709	DN3000/DN3500 at f8000000 - ffffffff (used by fpa and/or color7?)
710	710	***************************************************************************/
711	711
712		static READ32_HANDLER( apollo_f8_r ) {
	712	READ32_MEMBER(apollo_state::apollo_f8_r){
713	713	offs_t address = 0xf8000000 + offset * 4;
714	714	UINT32 data = 0xffffffff;
715	715	SLOG2(("unexpected memory dword read from %08x = %08x & %08x",
r14963	r14964
717	717	return data;
718	718	}
719	719
720		static WRITE32_HANDLER( apollo_f8_w ) {
	720	WRITE32_MEMBER(apollo_state::apollo_f8_w){
721	721	offs_t address = 0xf8000000 +offset * 4;
722	722
723	723	SLOG2(("unexpected memory dword write to %08x = %08x & %08x",
r14963	r14964
731	731
732	732	static ADDRESS_MAP_START(dn3500_map, AS_PROGRAM, 32, apollo_state )
733	733	AM_RANGE(0x000000, 0x00ffff) AM_ROM /* boot ROM  */
734		AM_RANGE(0x000000, 0x00ffff) AM_WRITE_LEGACY(apollo_rom_w)
735		AM_RANGE(0x010000, 0x0100ff) AM_READWRITE16_LEGACY(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
736		AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16_LEGACY(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
737		AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8_LEGACY(cache_status_register_r, cache_control_register_w, 0xffffffff )
738		AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8_LEGACY(task_alias_register_r , task_alias_register_w , 0xffffffff )
	734	AM_RANGE(0x000000, 0x00ffff) AM_WRITE(apollo_rom_w)
	735	AM_RANGE(0x010000, 0x0100ff) AM_READWRITE16(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
	736	AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
	737	AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8(cache_status_register_r, cache_control_register_w, 0xffffffff )
	738	AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8(task_alias_register_r , task_alias_register_w , 0xffffffff )
739	739	AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO_TAG, apollo_sio_r, apollo_sio_w, 0xffffffff )
740	740	AM_RANGE(0x010500, 0x0105ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO2_TAG, apollo_sio2_r, apollo_sio2_w, 0xffffffff )
741	741	AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PTM_TAG, apollo_ptm_r, apollo_ptm_w, 0xffffffff )
742		AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8_LEGACY(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
743		AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8_LEGACY(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
744		AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8_LEGACY(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
	742	AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
	743	AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
	744	AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
745	745	AM_RANGE(0x011000, 0x0110ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC1_TAG, apollo_pic8259_master_r, apollo_pic8259_master_w, 0xffffffff)
746	746	AM_RANGE(0x011100, 0x0111ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC2_TAG, apollo_pic8259_slave_r, apollo_pic8259_slave_w, 0xffffffff)
747		AM_RANGE(0x011200, 0x0112ff) AM_READWRITE16_LEGACY(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
748		AM_RANGE(0x011300, 0x0113ff) AM_READWRITE16_LEGACY(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
749		AM_RANGE(0x011600, 0x0116ff) AM_READWRITE8_LEGACY(master_req_register_r, master_req_register_w, 0xffffffff)
	747	AM_RANGE(0x011200, 0x0112ff) AM_READWRITE16(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
	748	AM_RANGE(0x011300, 0x0113ff) AM_READWRITE16(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
	749	AM_RANGE(0x011600, 0x0116ff) AM_READWRITE8(master_req_register_r, master_req_register_w, 0xffffffff)
750	750
751		AM_RANGE(0x016400, 0x0164ff) AM_READWRITE16_LEGACY(selective_clear_locations_r, selective_clear_locations_w, 0xffffffff )
752		AM_RANGE(0x017000, 0x017fff) AM_READWRITE16_LEGACY(apollo_address_translation_map_r, apollo_address_translation_map_w, 0xffffffff )
	751	AM_RANGE(0x016400, 0x0164ff) AM_READWRITE16(selective_clear_locations_r, selective_clear_locations_w, 0xffffffff )
	752	AM_RANGE(0x017000, 0x017fff) AM_READWRITE16(apollo_address_translation_map_r, apollo_address_translation_map_w, 0xffffffff )
753	753
754	754	AM_RANGE(0x04D000, 0x04D007) AM_DEVREADWRITE16_LEGACY(APOLLO_WDC_TAG, omti8621_r, omti8621_w, 0xffffffff)
755	755	AM_RANGE(0x050000, 0x050007) AM_DEVREADWRITE8_LEGACY(APOLLO_CTAPE_TAG, sc499_r, sc499_w, 0xffffffff)
756	756	AM_RANGE(0x058000, 0x058007) AM_DEVREADWRITE8_LEGACY(APOLLO_ETH_TAG, threecom3c505_r, threecom3c505_w, 0xffffffff)
757		AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8_LEGACY(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
	757	AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
758	758
759	759	AM_RANGE(0x05d800, 0x05dc07) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mcr_r, apollo_mcr_w, 0xffffffff)
760	760	AM_RANGE(0xfa0000, 0xfdffff) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mgm_r, apollo_mgm_w, 0xffffffff)
761	761
762		AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16_LEGACY(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
	762	AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
763	763
764	764	AM_RANGE(0x080000, 0x081fff) AM_ROM /* 3C505 boot ROM  */
765	765
766	766	// FIXME: must match with RAM size in driver/apollo_sio.c
767	767	// AM_RANGE(DN3500_RAM_BASE, DN3500_RAM_END) AM_RAM  AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size) /* 8MB RAM */
768		AM_RANGE(DN3500_RAM_BASE, DN3500_RAM_END) AM_RAM_WRITE_LEGACY(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
	768	AM_RANGE(DN3500_RAM_BASE, DN3500_RAM_END) AM_RAM_WRITE(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
769	769
770		AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE_LEGACY(apollo_atbus_memory_r, apollo_atbus_memory_w)
	770	AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE(apollo_atbus_memory_r, apollo_atbus_memory_w)
771	771
772	772	//      AM_RANGE(0x03020000, 0x0303ffff) Cache Tag Store (DN4500 only)
773	773	//      AM_RANGE(0x04000000, 0x0400ffff) Cache Tag Data (DN4500 only)
774	774	//      AM_RANGE(0x0e000000, 0x0fffffff) FPA address space
775	775
776		//      AM_RANGE(0xf8000000, 0xffffffff) AM_READWRITE_LEGACY(apollo_f8_r, apollo_f8_w)
777		AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE_LEGACY(apollo_unmapped_r, apollo_unmapped_w)
	776	//      AM_RANGE(0xf8000000, 0xffffffff) AM_READWRITE(apollo_f8_r, apollo_f8_w)
	777	AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(apollo_unmapped_r, apollo_unmapped_w)
778	778	ADDRESS_MAP_END
779	779
780	780	static ADDRESS_MAP_START(dsp3500_map, AS_PROGRAM, 32, apollo_state )
781	781	AM_RANGE(0x000000, 0x00ffff) AM_ROM /* boot ROM  */
782		AM_RANGE(0x000000, 0x00ffff) AM_WRITE_LEGACY(apollo_rom_w)
783		AM_RANGE(0x010000, 0x0100ff) AM_READWRITE16_LEGACY(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
784		AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16_LEGACY(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
785		AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8_LEGACY(cache_status_register_r, cache_control_register_w, 0xffffffff )
786		AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8_LEGACY(task_alias_register_r , task_alias_register_w , 0xffffffff )
	782	AM_RANGE(0x000000, 0x00ffff) AM_WRITE(apollo_rom_w)
	783	AM_RANGE(0x010000, 0x0100ff) AM_READWRITE16(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
	784	AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
	785	AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8(cache_status_register_r, cache_control_register_w, 0xffffffff )
	786	AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8(task_alias_register_r , task_alias_register_w , 0xffffffff )
787	787	AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO_TAG, apollo_sio_r, apollo_sio_w, 0xffffffff )
788	788	AM_RANGE(0x010500, 0x0105ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO2_TAG, apollo_sio2_r, apollo_sio2_w, 0xffffffff )
789	789	AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PTM_TAG, apollo_ptm_r, apollo_ptm_w, 0xffffffff )
790		AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8_LEGACY(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
791		AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8_LEGACY(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
792		AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8_LEGACY(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
	790	AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
	791	AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
	792	AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
793	793	AM_RANGE(0x011000, 0x0110ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC1_TAG, apollo_pic8259_master_r, apollo_pic8259_master_w, 0xffffffff)
794	794	AM_RANGE(0x011100, 0x0111ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC2_TAG, apollo_pic8259_slave_r, apollo_pic8259_slave_w, 0xffffffff)
795		AM_RANGE(0x011200, 0x0112ff) AM_READWRITE16_LEGACY(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
796		AM_RANGE(0x011300, 0x0113ff) AM_READWRITE16_LEGACY(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
797		AM_RANGE(0x011600, 0x0116ff) AM_READWRITE8_LEGACY(master_req_register_r, master_req_register_w, 0xffffffff)
	795	AM_RANGE(0x011200, 0x0112ff) AM_READWRITE16(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
	796	AM_RANGE(0x011300, 0x0113ff) AM_READWRITE16(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
	797	AM_RANGE(0x011600, 0x0116ff) AM_READWRITE8(master_req_register_r, master_req_register_w, 0xffffffff)
798	798
799		AM_RANGE(0x016400, 0x0164ff) AM_READWRITE16_LEGACY(selective_clear_locations_r, selective_clear_locations_w, 0xffffffff )
800		AM_RANGE(0x017000, 0x017fff) AM_READWRITE16_LEGACY(apollo_address_translation_map_r, apollo_address_translation_map_w, 0xffffffff )
	799	AM_RANGE(0x016400, 0x0164ff) AM_READWRITE16(selective_clear_locations_r, selective_clear_locations_w, 0xffffffff )
	800	AM_RANGE(0x017000, 0x017fff) AM_READWRITE16(apollo_address_translation_map_r, apollo_address_translation_map_w, 0xffffffff )
801	801
802	802	AM_RANGE(0x04D000, 0x04D007) AM_DEVREADWRITE16_LEGACY(APOLLO_WDC_TAG, omti8621_r, omti8621_w, 0xffffffff)
803	803	AM_RANGE(0x050000, 0x050007) AM_DEVREADWRITE8_LEGACY(APOLLO_CTAPE_TAG, sc499_r, sc499_w, 0xffffffff)
804	804	AM_RANGE(0x058000, 0x058007) AM_DEVREADWRITE8_LEGACY(APOLLO_ETH_TAG, threecom3c505_r, threecom3c505_w, 0xffffffff)
805		AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8_LEGACY(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
	805	AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
806	806
807	807	//      AM_RANGE(0x05d800, 0x05dc07) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mcr_r, apollo_mcr_w, 0xffffffff)
808	808	//      AM_RANGE(0xfa0000, 0xfdffff) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mgm_r, apollo_mgm_w, 0xffffffff)
809	809
810		AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16_LEGACY(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
	810	AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
811	811
812	812	AM_RANGE(0x080000, 0x081fff) AM_ROM /* 3C505 boot ROM  */
813	813
814	814	// FIXME: must match with RAM size in driver/apollo_sio.c
815	815	// AM_RANGE(DN3500_RAM_BASE, DN3500_RAM_END) AM_RAM  AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size) /* 8MB RAM */
816		AM_RANGE(DN3500_RAM_BASE, DN3500_RAM_END) AM_RAM_WRITE_LEGACY(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
	816	AM_RANGE(DN3500_RAM_BASE, DN3500_RAM_END) AM_RAM_WRITE(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
817	817
818		AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE_LEGACY(apollo_atbus_memory_r, apollo_atbus_memory_w)
	818	AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE(apollo_atbus_memory_r, apollo_atbus_memory_w)
819	819
820		//      AM_RANGE(0xf8000000, 0xffffffff) AM_READWRITE_LEGACY(apollo_f8_r, apollo_f8_w)
821		AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE_LEGACY(apollo_unmapped_r, apollo_unmapped_w)
	820	//      AM_RANGE(0xf8000000, 0xffffffff) AM_READWRITE(apollo_f8_r, apollo_f8_w)
	821	AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(apollo_unmapped_r, apollo_unmapped_w)
822	822	ADDRESS_MAP_END
823	823
824	824	static ADDRESS_MAP_START(dn3000_map, AS_PROGRAM, 32, apollo_state )
825	825	AM_RANGE(0x000000, 0x007fff) AM_ROM /* boot ROM  */
826		AM_RANGE(0x000000, 0x007fff) AM_WRITE_LEGACY(apollo_rom_w)
827		AM_RANGE(0x008000, 0x0080ff) AM_READWRITE16_LEGACY(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
828		AM_RANGE(0x008100, 0x0081ff) AM_READWRITE16_LEGACY(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
	826	AM_RANGE(0x000000, 0x007fff) AM_WRITE(apollo_rom_w)
	827	AM_RANGE(0x008000, 0x0080ff) AM_READWRITE16(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
	828	AM_RANGE(0x008100, 0x0081ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
829	829	AM_RANGE(0x008400, 0x0087ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO_TAG, apollo_sio_r, apollo_sio_w, 0xffffffff )
830	830	AM_RANGE(0x008800, 0x0088ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PTM_TAG, apollo_ptm_r, apollo_ptm_w, 0xffffffff )
831		AM_RANGE(0x008900, 0x0089ff) AM_READWRITE8_LEGACY(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
	831	AM_RANGE(0x008900, 0x0089ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
832	832
833		AM_RANGE(0x009000, 0x0090ff) AM_READWRITE8_LEGACY(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
834		AM_RANGE(0x009100, 0x0091ff) AM_READWRITE8_LEGACY(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
835		AM_RANGE(0x009200, 0x0092ff) AM_READWRITE8_LEGACY(apollo_dma_page_register_r, apollo_dma_page_register_w, 0xffffffff )
836		AM_RANGE(0x009300, 0x0093ff) AM_READWRITE16_LEGACY(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
	833	AM_RANGE(0x009000, 0x0090ff) AM_READWRITE8(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
	834	AM_RANGE(0x009100, 0x0091ff) AM_READWRITE8(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
	835	AM_RANGE(0x009200, 0x0092ff) AM_READWRITE8(apollo_dma_page_register_r, apollo_dma_page_register_w, 0xffffffff )
	836	AM_RANGE(0x009300, 0x0093ff) AM_READWRITE16(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
837	837	AM_RANGE(0x009400, 0x0094ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC1_TAG, apollo_pic8259_master_r, apollo_pic8259_master_w, 0xffffffff)
838	838	AM_RANGE(0x009500, 0x0095ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC2_TAG, apollo_pic8259_slave_r, apollo_pic8259_slave_w, 0xffffffff)
839		AM_RANGE(0x009600, 0x0096ff) AM_READWRITE16_LEGACY(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
	839	AM_RANGE(0x009600, 0x0096ff) AM_READWRITE16(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
840	840
841	841	AM_RANGE(0x04D000, 0x04D007) AM_DEVREADWRITE16_LEGACY(APOLLO_WDC_TAG, omti8621_r, omti8621_w, 0xffffffff)
842	842	AM_RANGE(0x050000, 0x050007) AM_DEVREADWRITE8_LEGACY(APOLLO_CTAPE_TAG, sc499_r, sc499_w, 0xffffffff)
843	843	AM_RANGE(0x058000, 0x058007) AM_DEVREADWRITE8_LEGACY(APOLLO_ETH_TAG, threecom3c505_r, threecom3c505_w, 0xffffffff)
844		AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8_LEGACY(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
	844	AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
845	845
846	846	AM_RANGE(0x05d800, 0x05dc07) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mcr_r, apollo_mcr_w, 0xffffffff)
847	847	AM_RANGE(0xfa0000, 0xfdffff) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mgm_r, apollo_mgm_w, 0xffffffff)
848	848
849		AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16_LEGACY(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
	849	AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
850	850
851	851	AM_RANGE(0x080000, 0x081fff) AM_ROM /* 3C505 boot ROM  */
852	852
853	853	// FIXME: must match with RAM size in driver/apollo_sio.c
854	854	// AM_RANGE(DN3000_RAM_BASE, DN3000_RAM_END) AM_RAM  AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size) /* 8MB RAM */
855		AM_RANGE(DN3000_RAM_BASE, DN3000_RAM_END) AM_RAM_WRITE_LEGACY(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
	855	AM_RANGE(DN3000_RAM_BASE, DN3000_RAM_END) AM_RAM_WRITE(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
856	856
857		AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE_LEGACY(apollo_atbus_memory_r, apollo_atbus_memory_w)
	857	AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE(apollo_atbus_memory_r, apollo_atbus_memory_w)
858	858
859		AM_RANGE(0x000000, 0xffffff) AM_READWRITE_LEGACY(apollo_unmapped_r, apollo_unmapped_w)
	859	AM_RANGE(0x000000, 0xffffff) AM_READWRITE(apollo_unmapped_r, apollo_unmapped_w)
860	860	ADDRESS_MAP_END
861	861
862	862	static ADDRESS_MAP_START(dsp3000_map, AS_PROGRAM, 32, apollo_state )
863	863	AM_RANGE(0x000000, 0x007fff) AM_ROM /* boot ROM  */
864		AM_RANGE(0x000000, 0x007fff) AM_WRITE_LEGACY(apollo_rom_w)
865		AM_RANGE(0x008000, 0x0080ff) AM_READWRITE16_LEGACY(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
866		AM_RANGE(0x008100, 0x0081ff) AM_READWRITE16_LEGACY(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
	864	AM_RANGE(0x000000, 0x007fff) AM_WRITE(apollo_rom_w)
	865	AM_RANGE(0x008000, 0x0080ff) AM_READWRITE16(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
	866	AM_RANGE(0x008100, 0x0081ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
867	867	AM_RANGE(0x008400, 0x0087ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO_TAG, apollo_sio_r, apollo_sio_w, 0xffffffff )
868	868	AM_RANGE(0x008800, 0x0088ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PTM_TAG, apollo_ptm_r, apollo_ptm_w, 0xffffffff )
869		AM_RANGE(0x008900, 0x0089ff) AM_READWRITE8_LEGACY(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
	869	AM_RANGE(0x008900, 0x0089ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
870	870
871		AM_RANGE(0x009000, 0x0090ff) AM_READWRITE8_LEGACY(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
872		AM_RANGE(0x009100, 0x0091ff) AM_READWRITE8_LEGACY(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
873		AM_RANGE(0x009200, 0x0092ff) AM_READWRITE8_LEGACY(apollo_dma_page_register_r, apollo_dma_page_register_w, 0xffffffff )
874		AM_RANGE(0x009300, 0x0093ff) AM_READWRITE16_LEGACY(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
	871	AM_RANGE(0x009000, 0x0090ff) AM_READWRITE8(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
	872	AM_RANGE(0x009100, 0x0091ff) AM_READWRITE8(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
	873	AM_RANGE(0x009200, 0x0092ff) AM_READWRITE8(apollo_dma_page_register_r, apollo_dma_page_register_w, 0xffffffff )
	874	AM_RANGE(0x009300, 0x0093ff) AM_READWRITE16(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
875	875	AM_RANGE(0x009400, 0x0094ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC1_TAG, apollo_pic8259_master_r, apollo_pic8259_master_w, 0xffffffff)
876	876	AM_RANGE(0x009500, 0x0095ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC2_TAG, apollo_pic8259_slave_r, apollo_pic8259_slave_w, 0xffffffff)
877		AM_RANGE(0x009600, 0x0096ff) AM_READWRITE16_LEGACY(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
	877	AM_RANGE(0x009600, 0x0096ff) AM_READWRITE16(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
878	878
879	879	AM_RANGE(0x04D000, 0x04D007) AM_DEVREADWRITE16_LEGACY(APOLLO_WDC_TAG, omti8621_r, omti8621_w, 0xffffffff)
880	880	AM_RANGE(0x050000, 0x050007) AM_DEVREADWRITE8_LEGACY(APOLLO_CTAPE_TAG, sc499_r, sc499_w, 0xffffffff)
881	881	AM_RANGE(0x058000, 0x058007) AM_DEVREADWRITE8_LEGACY(APOLLO_ETH_TAG, threecom3c505_r, threecom3c505_w, 0xffffffff)
882		AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8_LEGACY(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
	882	AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
883	883
884	884	//      AM_RANGE(0x05d800, 0x05dc07) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mcr_r, apollo_mcr_w, 0xffffffff)
885	885	//      AM_RANGE(0xfa0000, 0xfdffff) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mgm_r, apollo_mgm_w, 0xffffffff)
886	886
887		AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16_LEGACY(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
	887	AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
888	888
889	889	AM_RANGE(0x080000, 0x081fff) AM_ROM /* 3C505 boot ROM  */
890	890
891	891	// FIXME: must match with RAM size in driver/apollo_sio.c
892	892	// AM_RANGE(DN3000_RAM_BASE, DN3000_RAM_END) AM_RAM  AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size) /* 8MB RAM */
893		AM_RANGE(DN3000_RAM_BASE, DN3000_RAM_END) AM_RAM_WRITE_LEGACY(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
	893	AM_RANGE(DN3000_RAM_BASE, DN3000_RAM_END) AM_RAM_WRITE(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
894	894
895		AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE_LEGACY(apollo_atbus_memory_r, apollo_atbus_memory_w)
	895	AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE(apollo_atbus_memory_r, apollo_atbus_memory_w)
896	896
897		AM_RANGE(0x000000, 0xffffff) AM_READWRITE_LEGACY(apollo_unmapped_r, apollo_unmapped_w)
	897	AM_RANGE(0x000000, 0xffffff) AM_READWRITE(apollo_unmapped_r, apollo_unmapped_w)
898	898	ADDRESS_MAP_END
899	899
900	900
901	901	static ADDRESS_MAP_START(dn5500_map, AS_PROGRAM, 32, apollo_state )
902	902	AM_RANGE(0x000000, 0x00ffff) AM_ROM /* boot ROM  */
903		AM_RANGE(0x000000, 0x00ffff) AM_WRITE_LEGACY(apollo_rom_w)
904		AM_RANGE(0x010000, 0x0100ff) AM_READWRITE16_LEGACY(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
905		AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16_LEGACY(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
906		AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8_LEGACY(cache_status_register_r, cache_control_register_w, 0xffffffff )
907		AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8_LEGACY(task_alias_register_r , task_alias_register_w , 0xffffffff )
	903	AM_RANGE(0x000000, 0x00ffff) AM_WRITE(apollo_rom_w)
	904	AM_RANGE(0x010000, 0x0100ff) AM_READWRITE16(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
	905	AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
	906	AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8(cache_status_register_r, cache_control_register_w, 0xffffffff )
	907	AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8(task_alias_register_r , task_alias_register_w , 0xffffffff )
908	908	AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO_TAG, apollo_sio_r, apollo_sio_w, 0xffffffff )
909	909	AM_RANGE(0x010500, 0x0105ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO2_TAG, apollo_sio2_r, apollo_sio2_w, 0xffffffff )
910	910	AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PTM_TAG, apollo_ptm_r, apollo_ptm_w, 0xffffffff )
911		AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8_LEGACY(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
912		AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8_LEGACY(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
913		AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8_LEGACY(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
	911	AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
	912	AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
	913	AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
914	914	AM_RANGE(0x011000, 0x0110ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC1_TAG, apollo_pic8259_master_r, apollo_pic8259_master_w, 0xffffffff)
915	915	AM_RANGE(0x011100, 0x0111ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC2_TAG, apollo_pic8259_slave_r, apollo_pic8259_slave_w, 0xffffffff)
916		AM_RANGE(0x011200, 0x0112ff) AM_READWRITE16_LEGACY(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
917		AM_RANGE(0x011300, 0x0113ff) AM_READWRITE16_LEGACY(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
918		AM_RANGE(0x011400, 0x0114ff) AM_READWRITE8_LEGACY(dn5500_memory_present_register_r, dn5500_memory_present_register_w, 0xffffffff )
919		AM_RANGE(0x011500, 0x0115ff) AM_READWRITE8_LEGACY(dn5500_11500_r, dn5500_11500_w, 0xffffffff )
920		AM_RANGE(0x011600, 0x0116ff) AM_READWRITE8_LEGACY(master_req_register_r, master_req_register_w, 0xffffffff)
	916	AM_RANGE(0x011200, 0x0112ff) AM_READWRITE16(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
	917	AM_RANGE(0x011300, 0x0113ff) AM_READWRITE16(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
	918	AM_RANGE(0x011400, 0x0114ff) AM_READWRITE8(dn5500_memory_present_register_r, dn5500_memory_present_register_w, 0xffffffff )
	919	AM_RANGE(0x011500, 0x0115ff) AM_READWRITE8(dn5500_11500_r, dn5500_11500_w, 0xffffffff )
	920	AM_RANGE(0x011600, 0x0116ff) AM_READWRITE8(master_req_register_r, master_req_register_w, 0xffffffff)
921	921
922		AM_RANGE(0x016400, 0x0164ff) AM_READWRITE16_LEGACY(selective_clear_locations_r, selective_clear_locations_w, 0xffffffff )
923		AM_RANGE(0x017000, 0x017fff) AM_READWRITE16_LEGACY(apollo_address_translation_map_r, apollo_address_translation_map_w, 0xffffffff )
	922	AM_RANGE(0x016400, 0x0164ff) AM_READWRITE16(selective_clear_locations_r, selective_clear_locations_w, 0xffffffff )
	923	AM_RANGE(0x017000, 0x017fff) AM_READWRITE16(apollo_address_translation_map_r, apollo_address_translation_map_w, 0xffffffff )
924	924
925	925	AM_RANGE(0x04D000, 0x04D007) AM_DEVREADWRITE16_LEGACY(APOLLO_WDC_TAG, omti8621_r, omti8621_w, 0xffffffff)
926	926	AM_RANGE(0x050000, 0x050007) AM_DEVREADWRITE8_LEGACY(APOLLO_CTAPE_TAG, sc499_r, sc499_w, 0xffffffff)
927	927	AM_RANGE(0x058000, 0x058007) AM_DEVREADWRITE8_LEGACY(APOLLO_ETH_TAG, threecom3c505_r, threecom3c505_w, 0xffffffff)
928		AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8_LEGACY(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
	928	AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
929	929
930	930	AM_RANGE(0x05d800, 0x05dc07) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mcr_r, apollo_mcr_w, 0xffffffff)
931	931	AM_RANGE(0xfa0000, 0xfdffff) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mgm_r, apollo_mgm_w, 0xffffffff)
932	932
933		AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16_LEGACY(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
	933	AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
934	934
935	935	AM_RANGE(0x080000, 0x081fff) AM_ROM /* 3C505 boot ROM  */
936	936
937	937	// FIXME: must match with RAM size in driver/apollo_sio.c
938	938	// AM_RANGE(DN3500_RAM_BASE, DN3500_RAM_END) AM_RAM  AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size) /* 8MB RAM */
939		AM_RANGE(DN5500_RAM_BASE, DN5500_RAM_END) AM_RAM_WRITE_LEGACY(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
	939	AM_RANGE(DN5500_RAM_BASE, DN5500_RAM_END) AM_RAM_WRITE(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
940	940
941		AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE_LEGACY(apollo_atbus_memory_r, apollo_atbus_memory_w)
	941	AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE(apollo_atbus_memory_r, apollo_atbus_memory_w)
942	942
943	943	//      AM_RANGE(0x03020000, 0x0303ffff) Cache Tag Store (DN4500 only)
944	944	//      AM_RANGE(0x04000000, 0x0400ffff) Cache Tag Data (DN4500 only)
945		AM_RANGE(0x07000000, 0x0700FFFF) AM_READWRITE8_LEGACY(dn5500_io_protection_map_r, dn5500_io_protection_map_w, 0xffffffff )
	945	AM_RANGE(0x07000000, 0x0700FFFF) AM_READWRITE8(dn5500_io_protection_map_r, dn5500_io_protection_map_w, 0xffffffff )
946	946	//      AM_RANGE(0x0e000000, 0x0fffffff) FPA address space
947	947
948		//      AM_RANGE(0xf8000000, 0xffffffff) AM_READWRITE_LEGACY(apollo_f8_r, apollo_f8_w)
949		AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE_LEGACY(apollo_unmapped_r, apollo_unmapped_w)
	948	//      AM_RANGE(0xf8000000, 0xffffffff) AM_READWRITE(apollo_f8_r, apollo_f8_w)
	949	AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(apollo_unmapped_r, apollo_unmapped_w)
950	950	ADDRESS_MAP_END
951	951
952	952
953	953	static ADDRESS_MAP_START(dsp5500_map, AS_PROGRAM, 32, apollo_state )
954	954	AM_RANGE(0x000000, 0x00ffff) AM_ROM /* boot ROM  */
955		AM_RANGE(0x000000, 0x00ffff) AM_WRITE_LEGACY(apollo_rom_w)
956		AM_RANGE(0x010000, 0x0100ff) AM_READWRITE16_LEGACY(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
957		AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16_LEGACY(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
958		AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8_LEGACY(cache_status_register_r, cache_control_register_w, 0xffffffff )
959		AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8_LEGACY(task_alias_register_r , task_alias_register_w , 0xffffffff )
	955	AM_RANGE(0x000000, 0x00ffff) AM_WRITE(apollo_rom_w)
	956	AM_RANGE(0x010000, 0x0100ff) AM_READWRITE16(apollo_csr_status_register_r, apollo_csr_status_register_w, 0xffffffff)
	957	AM_RANGE(0x010100, 0x0101ff) AM_READWRITE16(apollo_csr_control_register_r, apollo_csr_control_register_w, 0xffffffff)
	958	AM_RANGE(0x010200, 0x0102ff) AM_READWRITE8(cache_status_register_r, cache_control_register_w, 0xffffffff )
	959	AM_RANGE(0x010300, 0x0103ff) AM_READWRITE8(task_alias_register_r , task_alias_register_w , 0xffffffff )
960	960	AM_RANGE(0x010400, 0x0104ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO_TAG, apollo_sio_r, apollo_sio_w, 0xffffffff )
961	961	AM_RANGE(0x010500, 0x0105ff) AM_DEVREADWRITE8_LEGACY(APOLLO_SIO2_TAG, apollo_sio2_r, apollo_sio2_w, 0xffffffff )
962	962	AM_RANGE(0x010800, 0x0108ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PTM_TAG, apollo_ptm_r, apollo_ptm_w, 0xffffffff )
963		AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8_LEGACY(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
964		AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8_LEGACY(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
965		AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8_LEGACY(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
	963	AM_RANGE(0x010900, 0x0109ff) AM_READWRITE8(apollo_rtc_r, apollo_rtc_w, 0xffffffff )
	964	AM_RANGE(0x010c00, 0x010cff) AM_READWRITE8(/*"dma1",*/apollo_dma_1_r, apollo_dma_1_w, 0xffffffff )
	965	AM_RANGE(0x010d00, 0x010dff) AM_READWRITE8(/*"dma2",*/apollo_dma_2_r, apollo_dma_2_w, 0xffffffff )
966	966	AM_RANGE(0x011000, 0x0110ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC1_TAG, apollo_pic8259_master_r, apollo_pic8259_master_w, 0xffffffff)
967	967	AM_RANGE(0x011100, 0x0111ff) AM_DEVREADWRITE8_LEGACY(APOLLO_PIC2_TAG, apollo_pic8259_slave_r, apollo_pic8259_slave_w, 0xffffffff)
968		AM_RANGE(0x011200, 0x0112ff) AM_READWRITE16_LEGACY(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
969		AM_RANGE(0x011300, 0x0113ff) AM_READWRITE16_LEGACY(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
970		AM_RANGE(0x011400, 0x0114ff) AM_READWRITE8_LEGACY(dn5500_memory_present_register_r, dn5500_memory_present_register_w, 0xffffffff )
971		AM_RANGE(0x011500, 0x0115ff) AM_READWRITE8_LEGACY(dn5500_11500_r, dn5500_11500_w, 0xffffffff )
972		AM_RANGE(0x011600, 0x0116ff) AM_READWRITE8_LEGACY(master_req_register_r, master_req_register_w, 0xffffffff)
	968	AM_RANGE(0x011200, 0x0112ff) AM_READWRITE16(apollo_node_id_r, apollo_node_id_w, 0xffffffff)
	969	AM_RANGE(0x011300, 0x0113ff) AM_READWRITE16(latch_page_on_parity_error_register_r, latch_page_on_parity_error_register_w, 0xffffffff )
	970	AM_RANGE(0x011400, 0x0114ff) AM_READWRITE8(dn5500_memory_present_register_r, dn5500_memory_present_register_w, 0xffffffff )
	971	AM_RANGE(0x011500, 0x0115ff) AM_READWRITE8(dn5500_11500_r, dn5500_11500_w, 0xffffffff )
	972	AM_RANGE(0x011600, 0x0116ff) AM_READWRITE8(master_req_register_r, master_req_register_w, 0xffffffff)
973	973
974		AM_RANGE(0x016400, 0x0164ff) AM_READWRITE16_LEGACY(selective_clear_locations_r, selective_clear_locations_w, 0xffffffff )
975		AM_RANGE(0x017000, 0x017fff) AM_READWRITE16_LEGACY(apollo_address_translation_map_r, apollo_address_translation_map_w, 0xffffffff )
	974	AM_RANGE(0x016400, 0x0164ff) AM_READWRITE16(selective_clear_locations_r, selective_clear_locations_w, 0xffffffff )
	975	AM_RANGE(0x017000, 0x017fff) AM_READWRITE16(apollo_address_translation_map_r, apollo_address_translation_map_w, 0xffffffff )
976	976
977	977	AM_RANGE(0x04D000, 0x04D007) AM_DEVREADWRITE16_LEGACY(APOLLO_WDC_TAG, omti8621_r, omti8621_w, 0xffffffff)
978	978	AM_RANGE(0x050000, 0x050007) AM_DEVREADWRITE8_LEGACY(APOLLO_CTAPE_TAG, sc499_r, sc499_w, 0xffffffff)
979	979	AM_RANGE(0x058000, 0x058007) AM_DEVREADWRITE8_LEGACY(APOLLO_ETH_TAG, threecom3c505_r, threecom3c505_w, 0xffffffff)
980		AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8_LEGACY(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
	980	AM_RANGE(0x05f800, 0x05f807) AM_READWRITE8(apollo_fdc_r, apollo_fdc_w, 0xffffffff)
981	981
982	982	//      AM_RANGE(0x05d800, 0x05dc07) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mcr_r, apollo_mcr_w, 0xffffffff)
983	983	//      AM_RANGE(0xfa0000, 0xfdffff) AM_DEVREADWRITE16_LEGACY(APOLLO_SCREEN_TAG, apollo_mgm_r, apollo_mgm_w, 0xffffffff)
984	984
985		AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16_LEGACY(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
	985	AM_RANGE(ATBUS_IO_BASE, ATBUS_IO_END) AM_READWRITE16(apollo_atbus_io_r, apollo_atbus_io_w, 0xffffffff)
986	986
987	987	AM_RANGE(0x080000, 0x081fff) AM_ROM /* 3C505 boot ROM  */
988	988
989	989	// FIXME: must match with RAM size in driver/apollo_sio.c
990		AM_RANGE(DN5500_RAM_BASE, DN5500_RAM_END) AM_RAM_WRITE_LEGACY(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
	990	AM_RANGE(DN5500_RAM_BASE, DN5500_RAM_END) AM_RAM_WRITE(ram_with_parity_w) AM_BASE_LEGACY(&messram_ptr.u32) AM_SIZE_LEGACY(&messram_size)
991	991
992		AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE_LEGACY(apollo_atbus_memory_r, apollo_atbus_memory_w)
	992	AM_RANGE(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END) AM_READWRITE(apollo_atbus_memory_r, apollo_atbus_memory_w)
993	993
994		AM_RANGE(0x07000000, 0x0700FFFF) AM_READWRITE8_LEGACY(dn5500_io_protection_map_r, dn5500_io_protection_map_w, 0xffffffff )
995		//      AM_RANGE(0xf8000000, 0xffffffff) AM_READWRITE_LEGACY(apollo_f8_r, apollo_f8_w)
996		AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE_LEGACY(apollo_unmapped_r, apollo_unmapped_w)
	994	AM_RANGE(0x07000000, 0x0700FFFF) AM_READWRITE8(dn5500_io_protection_map_r, dn5500_io_protection_map_w, 0xffffffff )
	995	//      AM_RANGE(0xf8000000, 0xffffffff) AM_READWRITE(apollo_f8_r, apollo_f8_w)
	996	AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(apollo_unmapped_r, apollo_unmapped_w)
997	997	ADDRESS_MAP_END
998	998
999	999	/***************************************************************************

src/mess/drivers/lisa.c

r14963	r14964
25	25	***************************************************************************/
26	26
27	27	static ADDRESS_MAP_START(lisa_map, AS_PROGRAM, 16, lisa_state )
28		AM_RANGE(0x000000, 0xffffff) AM_READWRITE_LEGACY(lisa_r, lisa_w)         /* no fixed map, we use an MMU */
	28	AM_RANGE(0x000000, 0xffffff) AM_READWRITE(lisa_r, lisa_w)         /* no fixed map, we use an MMU */
29	29	ADDRESS_MAP_END
30	30
31	31	static ADDRESS_MAP_START( lisa_cop_io_map, AS_IO, 8, lisa_state )
r14963	r14964
51	51	static ADDRESS_MAP_START(lisa_fdc_map, AS_PROGRAM, 8, lisa_state )
52	52	ADDRESS_MAP_GLOBAL_MASK(0x1fff)   // only 8k of address space
53	53	AM_RANGE(0x0000, 0x03ff) AM_RAM   AM_SHARE("fdc_ram")            /* RAM (shared with 68000) */
54		AM_RANGE(0x0400, 0x07ff) AM_READWRITE_LEGACY(lisa_fdc_io_r, lisa_fdc_io_w)   /* disk controller (IWM and TTL logic) */
	54	AM_RANGE(0x0400, 0x07ff) AM_READWRITE(lisa_fdc_io_r, lisa_fdc_io_w)   /* disk controller (IWM and TTL logic) */
55	55	AM_RANGE(0x0800, 0x0fff) AM_NOP
56	56	AM_RANGE(0x1000, 0x1fff) AM_ROM   AM_SHARE("fdc_rom")            /* ROM */
57		AM_RANGE(0x2000, 0xffff) AM_READWRITE_LEGACY(lisa_fdc_r, lisa_fdc_w)      /* handler for wrap-around */
	57	AM_RANGE(0x2000, 0xffff) AM_READWRITE(lisa_fdc_r, lisa_fdc_w)      /* handler for wrap-around */
58	58	ADDRESS_MAP_END
59	59
60	60	static ADDRESS_MAP_START(lisa210_fdc_map, AS_PROGRAM, 8, lisa_state )
61	61	ADDRESS_MAP_GLOBAL_MASK(0x1fff)   // only 8k of address space
62	62	AM_RANGE(0x0000, 0x03ff) AM_RAM   AM_SHARE("fdc_ram")            /* RAM (shared with 68000) */
63	63	AM_RANGE(0x0400, 0x07ff) AM_NOP                              /* nothing, or RAM wrap-around ??? */
64		AM_RANGE(0x0800, 0x0bff) AM_READWRITE_LEGACY(lisa_fdc_io_r, lisa_fdc_io_w)   /* disk controller (IWM and TTL logic) */
	64	AM_RANGE(0x0800, 0x0bff) AM_READWRITE(lisa_fdc_io_r, lisa_fdc_io_w)   /* disk controller (IWM and TTL logic) */
65	65	AM_RANGE(0x0c00, 0x0fff) AM_NOP                              /* nothing, or IO port wrap-around ??? */
66	66	AM_RANGE(0x1000, 0x1fff) AM_ROM   AM_SHARE("fdc_rom")            /* ROM */
67		AM_RANGE(0x2000, 0xffff) AM_READWRITE_LEGACY(lisa_fdc_r, lisa_fdc_w)      /* handler for wrap-around */
	67	AM_RANGE(0x2000, 0xffff) AM_READWRITE(lisa_fdc_r, lisa_fdc_w)      /* handler for wrap-around */
68	68	ADDRESS_MAP_END
69	69
70	70

src/mess/drivers/lynx.c

r14963	r14964
21	21	AM_RANGE(0xfd00, 0xfdff) AM_RAM AM_SHARE("mem_fd00")
22	22	AM_RANGE(0xfe00, 0xfff7) AM_READ_BANK("bank3") AM_WRITEONLY AM_SHARE("mem_fe00")
23	23	AM_RANGE(0xfff8, 0xfff8) AM_RAM
24		AM_RANGE(0xfff9, 0xfff9) AM_READWRITE_LEGACY(lynx_memory_config_r, lynx_memory_config_w)
	24	AM_RANGE(0xfff9, 0xfff9) AM_READWRITE(lynx_memory_config_r, lynx_memory_config_w)
25	25	AM_RANGE(0xfffa, 0xffff) AM_READ_BANK("bank4") AM_WRITEONLY AM_SHARE("mem_fffa")
26	26	ADDRESS_MAP_END
27	27

src/mess/drivers/aquarius.c

r14963	r14964
59	59	mark cycle. Control must be returned at that time to the cassette routine
60	60	in order to maintain data integrity.
61	61	*/
62		static READ8_HANDLER( cassette_r )
	62	READ8_MEMBER(aquarius_state::cassette_r)
63	63	{
64		cassette_image_device *cassette = space->machine().device<cassette_image_device>(CASSETTE_TAG);
	64	cassette_image_device *cassette = machine().device<cassette_image_device>(CASSETTE_TAG);
65	65	return ((cassette)->input() < +0.0) ? 0 : 1;
66	66	}
67	67
r14963	r14964
71	71	will appear on audio output. Sound port is a simple one bit I/O and therefore
72	72	it must be toggled at a specific rate under software control.
73	73	*/
74		static WRITE8_HANDLER( cassette_w )
	74	WRITE8_MEMBER(aquarius_state::cassette_w)
75	75	{
76		device_t *speaker = space->machine().device(SPEAKER_TAG);
77		cassette_image_device *cassette = space->machine().device<cassette_image_device>(CASSETTE_TAG);
	76	device_t *speaker = machine().device(SPEAKER_TAG);
	77	cassette_image_device *cassette = machine().device<cassette_image_device>(CASSETTE_TAG);
78	78
79	79	speaker_level_w(speaker, BIT(data, 0));
80	80	cassette->output( BIT(data, 0) ? +1.0 : -1.0);
r14963	r14964
93	93	+                             +       +
94	94	+++++                             +++++++++
95	95	*/
96		static READ8_HANDLER( vsync_r )
	96	READ8_MEMBER(aquarius_state::vsync_r)
97	97	{
98		screen_device *screen = space->machine().primary_screen;
	98	screen_device *screen = machine().primary_screen;
99	99	return screen->vblank() ? 0 : 1;
100	100	}
101	101
r14963	r14964
105	105	map with the upper 16K. A 1 in this bit indicates swapping. This bit is reset
106	106	after power up initialization.
107	107	*/
108		static WRITE8_HANDLER( mapper_w )
	108	WRITE8_MEMBER(aquarius_state::mapper_w)
109	109	{
110	110	}
111	111
r14963	r14964
115	115	to send status from PRNHASK pin at bit D0. A 1 indicates printer is ready,
116	116	0 means not ready.
117	117	*/
118		static READ8_HANDLER( printer_r )
	118	READ8_MEMBER(aquarius_state::printer_r)
119	119	{
120	120	return 1; /* ready */
121	121	}
r14963	r14964
127	127	baudrate is variable. In BASIC this is a 1200 baud printer port for
128	128	the 40 column thermal printer.
129	129	*/
130		static WRITE8_HANDLER( printer_w )
	130	WRITE8_MEMBER(aquarius_state::printer_w)
131	131	{
132	132	}
133	133
r14963	r14964
143	143	Therefore the keyboard can be scanned by placing a specific scanning
144	144	pattern in (A) or (B) and reading the result returned on rows.
145	145	*/
146		static READ8_HANDLER( keyboard_r )
	146	READ8_MEMBER(aquarius_state::keyboard_r)
147	147	{
148	148	UINT8 result = 0xff;
149	149
150		if (!BIT(offset,  8)) result &= input_port_read(space->machine(), "ROW0");
151		if (!BIT(offset,  9)) result &= input_port_read(space->machine(), "ROW1");
152		if (!BIT(offset, 10)) result &= input_port_read(space->machine(), "ROW2");
153		if (!BIT(offset, 11)) result &= input_port_read(space->machine(), "ROW3");
154		if (!BIT(offset, 12)) result &= input_port_read(space->machine(), "ROW4");
155		if (!BIT(offset, 13)) result &= input_port_read(space->machine(), "ROW5");
156		if (!BIT(offset, 14)) result &= input_port_read(space->machine(), "ROW6");
157		if (!BIT(offset, 15)) result &= input_port_read(space->machine(), "ROW7");
	150	if (!BIT(offset,  8)) result &= input_port_read(machine(), "ROW0");
	151	if (!BIT(offset,  9)) result &= input_port_read(machine(), "ROW1");
	152	if (!BIT(offset, 10)) result &= input_port_read(machine(), "ROW2");
	153	if (!BIT(offset, 11)) result &= input_port_read(machine(), "ROW3");
	154	if (!BIT(offset, 12)) result &= input_port_read(machine(), "ROW4");
	155	if (!BIT(offset, 13)) result &= input_port_read(machine(), "ROW5");
	156	if (!BIT(offset, 14)) result &= input_port_read(machine(), "ROW6");
	157	if (!BIT(offset, 15)) result &= input_port_read(machine(), "ROW7");
158	158
159	159	return result;
160	160	}
r14963	r14964
178	178	routine. For game cartridge the lock pattern is generated from data in the
179	179	game cartridge itself.
180	180	*/
181		static WRITE8_HANDLER( scrambler_w )
	181	WRITE8_MEMBER(aquarius_state::scrambler_w)
182	182	{
183		aquarius_state *state = space->machine().driver_data<aquarius_state>();
184		state->m_scrambler = data;
	183	m_scrambler = data;
185	184	}
186	185
187		static READ8_HANDLER( cartridge_r )
	186	READ8_MEMBER(aquarius_state::cartridge_r)
188	187	{
189		aquarius_state *state = space->machine().driver_data<aquarius_state>();
190		UINT8 *rom = space->machine().region("maincpu")->base() + 0xc000;
191		return rom[offset] ^ state->m_scrambler;
	188	UINT8 *rom = machine().region("maincpu")->base() + 0xc000;
	189	return rom[offset] ^ m_scrambler;
192	190	}
193	191
194	192
r14963	r14964
197	195	***************************************************************************/
198	196
199	197	/* note: 0xe6-0xe7 = drive 1, 0xea-0xeb = drive 2 */
200		static READ8_HANDLER( floppy_r )
	198	READ8_MEMBER(aquarius_state::floppy_r)
201	199	{
202		logerror("%s: floppy_r[0x%02x]\n", space->machine().describe_context(), offset);
	200	logerror("%s: floppy_r[0x%02x]\n", machine().describe_context(), offset);
203	201	return 0xff;
204	202	}
205	203
206		static WRITE8_HANDLER( floppy_w )
	204	WRITE8_MEMBER(aquarius_state::floppy_w)
207	205	{
208		logerror("%s: floppy_w[0x%02x] (0x%02x)\n", space->machine().describe_context(), offset, data);
	206	logerror("%s: floppy_w[0x%02x] (0x%02x)\n", machine().describe_context(), offset, data);
209	207	}
210	208
211	209
r14963	r14964
232	230
233	231	static ADDRESS_MAP_START( aquarius_mem, AS_PROGRAM, 8, aquarius_state )
234	232	AM_RANGE(0x0000, 0x1fff) AM_ROM
235		AM_RANGE(0x3000, 0x33ff) AM_RAM_WRITE_LEGACY(aquarius_videoram_w) AM_SHARE("videoram")
236		AM_RANGE(0x3400, 0x37ff) AM_RAM_WRITE_LEGACY(aquarius_colorram_w) AM_SHARE("colorram")
	233	AM_RANGE(0x3000, 0x33ff) AM_RAM_WRITE(aquarius_videoram_w) AM_SHARE("videoram")
	234	AM_RANGE(0x3400, 0x37ff) AM_RAM_WRITE(aquarius_colorram_w) AM_SHARE("colorram")
237	235	AM_RANGE(0x3800, 0x3fff) AM_RAM
238	236	AM_RANGE(0x4000, 0xbfff) AM_NOP /* expansion ram */
239		AM_RANGE(0xc000, 0xffff) AM_READ_LEGACY(cartridge_r)
	237	AM_RANGE(0xc000, 0xffff) AM_READ(cartridge_r)
240	238	ADDRESS_MAP_END
241	239
242	240	static ADDRESS_MAP_START( aquarius_io, AS_IO, 8, aquarius_state )
243	241	//  AM_RANGE(0x7e, 0x7f) AM_MIRROR(0xff00) AM_READWRITE_LEGACY(modem_r, modem_w)
244	242	AM_RANGE(0xf6, 0xf6) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY("ay8910", ay8910_r, ay8910_data_w)
245	243	AM_RANGE(0xf7, 0xf7) AM_MIRROR(0xff00) AM_DEVWRITE_LEGACY("ay8910", ay8910_address_w)
246		AM_RANGE(0xfc, 0xfc) AM_MIRROR(0xff00) AM_READWRITE_LEGACY(cassette_r, cassette_w)
247		AM_RANGE(0xfd, 0xfd) AM_MIRROR(0xff00) AM_READWRITE_LEGACY(vsync_r, mapper_w)
248		AM_RANGE(0xfe, 0xfe) AM_MIRROR(0xff00) AM_READWRITE_LEGACY(printer_r, printer_w)
249		AM_RANGE(0xff, 0xff) AM_MIRROR(0xff00) AM_MASK(0xff00) AM_READWRITE_LEGACY(keyboard_r, scrambler_w)
	244	AM_RANGE(0xfc, 0xfc) AM_MIRROR(0xff00) AM_READWRITE(cassette_r, cassette_w)
	245	AM_RANGE(0xfd, 0xfd) AM_MIRROR(0xff00) AM_READWRITE(vsync_r, mapper_w)
	246	AM_RANGE(0xfe, 0xfe) AM_MIRROR(0xff00) AM_READWRITE(printer_r, printer_w)
	247	AM_RANGE(0xff, 0xff) AM_MIRROR(0xff00) AM_MASK(0xff00) AM_READWRITE(keyboard_r, scrambler_w)
250	248	ADDRESS_MAP_END
251	249
252	250	static ADDRESS_MAP_START( aquarius_qd_io, AS_IO, 8, aquarius_state )
253	251	AM_IMPORT_FROM(aquarius_io)
254		AM_RANGE(0xe0, 0xef) AM_MIRROR(0xff00) AM_READWRITE_LEGACY(floppy_r, floppy_w)
	252	AM_RANGE(0xe0, 0xef) AM_MIRROR(0xff00) AM_READWRITE(floppy_r, floppy_w)
255	253	ADDRESS_MAP_END
256	254
257	255

src/mess/drivers/specpls3.c

r14963	r14964
342	342	The function decodes the ports appropriately */
343	343	static ADDRESS_MAP_START (spectrum_plus3_io, AS_IO, 8, spectrum_state )
344	344	ADDRESS_MAP_UNMAP_HIGH
345		AM_RANGE(0x0000, 0x0000) AM_READWRITE_LEGACY(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xfffe) AM_MASK(0xffff)
346		AM_RANGE(0x001f, 0x001f) AM_READ_LEGACY(spectrum_port_1f_r) AM_MIRROR(0xff00)
	345	AM_RANGE(0x0000, 0x0000) AM_READWRITE(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xfffe) AM_MASK(0xffff)
	346	AM_RANGE(0x001f, 0x001f) AM_READ(spectrum_port_1f_r) AM_MIRROR(0xff00)
347	347	AM_RANGE(0x4000, 0x4000) AM_WRITE_LEGACY(spectrum_plus3_port_7ffd_w) AM_MIRROR(0x3ffd)
348	348	AM_RANGE(0x8000, 0x8000) AM_DEVWRITE_LEGACY("ay8912", ay8910_data_w) AM_MIRROR(0x3ffd)
349	349	AM_RANGE(0xc000, 0xc000) AM_DEVREADWRITE_LEGACY("ay8912", ay8910_r, ay8910_address_w) AM_MIRROR(0x3ffd)

src/mess/drivers/x68k.c

r14963	r14964
2131	2131
2132	2132	static const ym2151_interface x68k_ym2151_interface =
2133	2133	{
2134		x68k_fm_irq,
2135		x68k_ct_w  // CT1, CT2 from YM2151 port 0x1b
	2134	DEVCB_LINE(x68k_fm_irq),
	2135	DEVCB_HANDLER(x68k_ct_w)  // CT1, CT2 from YM2151 port 0x1b
2136	2136	};
2137	2137
2138	2138	static const okim6258_interface x68k_okim6258_interface =

src/mess/drivers/ondra.c

r14963	r14964
24	24	static ADDRESS_MAP_START( ondra_io, AS_IO, 8, ondra_state )
25	25	ADDRESS_MAP_GLOBAL_MASK(0x0b)
26	26	ADDRESS_MAP_UNMAP_HIGH
27		AM_RANGE(0x03, 0x03) AM_WRITE_LEGACY(ondra_port_03_w)
28		//AM_RANGE(0x09, 0x09) AM_WRITE_LEGACY(ondra_port_09_w)
29		//AM_RANGE(0x0a, 0x0a) AM_WRITE_LEGACY(ondra_port_0a_w)
	27	AM_RANGE(0x03, 0x03) AM_WRITE(ondra_port_03_w)
	28	//AM_RANGE(0x09, 0x09) AM_WRITE(ondra_port_09_w)
	29	//AM_RANGE(0x0a, 0x0a) AM_WRITE(ondra_port_0a_w)
30	30	ADDRESS_MAP_END
31	31
32	32	/* Input ports */

src/mess/drivers/lviv.c

r14963	r14964
294	294	/* I/O ports */
295	295
296	296	static ADDRESS_MAP_START(io_map, AS_IO, 8, lviv_state )
297		AM_RANGE(0x00, 0xff) AM_READWRITE_LEGACY(lviv_io_r,lviv_io_w)
	297	AM_RANGE(0x00, 0xff) AM_READWRITE(lviv_io_r,lviv_io_w)
298	298	ADDRESS_MAP_END
299	299
300	300	/* memory w/r functions */

src/mess/drivers/timex.c

r14963	r14964
539	539	}
540	540
541	541	static ADDRESS_MAP_START(ts2068_io, AS_IO, 8, spectrum_state )
542		AM_RANGE(0x1f, 0x1f) AM_READ_LEGACY(spectrum_port_1f_r ) AM_MIRROR(0xff00)
543		AM_RANGE(0x7f, 0x7f) AM_READ_LEGACY(spectrum_port_7f_r ) AM_MIRROR(0xff00)
544		AM_RANGE(0xdf, 0xdf) AM_READ_LEGACY(spectrum_port_df_r ) AM_MIRROR(0xff00)
	542	AM_RANGE(0x1f, 0x1f) AM_READ(spectrum_port_1f_r ) AM_MIRROR(0xff00)
	543	AM_RANGE(0x7f, 0x7f) AM_READ(spectrum_port_7f_r ) AM_MIRROR(0xff00)
	544	AM_RANGE(0xdf, 0xdf) AM_READ(spectrum_port_df_r ) AM_MIRROR(0xff00)
545	545	AM_RANGE(0xf4, 0xf4) AM_READWRITE_LEGACY(ts2068_port_f4_r,ts2068_port_f4_w ) AM_MIRROR(0xff00)
546	546	AM_RANGE(0xf5, 0xf5) AM_DEVWRITE_LEGACY("ay8912", ay8910_address_w ) AM_MIRROR(0xff00)
547	547	AM_RANGE(0xf6, 0xf6) AM_DEVREADWRITE_LEGACY("ay8912", ay8910_r, ay8910_data_w ) AM_MIRROR(0xff00)
548		AM_RANGE(0xfe, 0xfe) AM_READWRITE_LEGACY(spectrum_port_fe_r,spectrum_port_fe_w )  AM_MIRROR(0xff00)  AM_MASK(0xffff)
	548	AM_RANGE(0xfe, 0xfe) AM_READWRITE(spectrum_port_fe_r,spectrum_port_fe_w )  AM_MIRROR(0xff00)  AM_MASK(0xffff)
549	549	AM_RANGE(0xff, 0xff) AM_READWRITE_LEGACY(ts2068_port_ff_r,ts2068_port_ff_w ) AM_MIRROR(0xff00)
550	550	ADDRESS_MAP_END
551	551
r14963	r14964
586	586	}
587	587
588	588	static ADDRESS_MAP_START(tc2048_io, AS_IO, 8, spectrum_state )
589		AM_RANGE(0x00, 0x00) AM_READWRITE_LEGACY(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xfffe) AM_MASK(0xffff)
590		AM_RANGE(0x1f, 0x1f) AM_READ_LEGACY(spectrum_port_1f_r) AM_MIRROR(0xff00)
591		AM_RANGE(0x7f, 0x7f) AM_READ_LEGACY(spectrum_port_7f_r) AM_MIRROR(0xff00)
592		AM_RANGE(0xdf, 0xdf) AM_READ_LEGACY(spectrum_port_df_r) AM_MIRROR(0xff00)
	589	AM_RANGE(0x00, 0x00) AM_READWRITE(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xfffe) AM_MASK(0xffff)
	590	AM_RANGE(0x1f, 0x1f) AM_READ(spectrum_port_1f_r) AM_MIRROR(0xff00)
	591	AM_RANGE(0x7f, 0x7f) AM_READ(spectrum_port_7f_r) AM_MIRROR(0xff00)
	592	AM_RANGE(0xdf, 0xdf) AM_READ(spectrum_port_df_r) AM_MIRROR(0xff00)
593	593	AM_RANGE(0xff, 0xff) AM_READWRITE_LEGACY(ts2068_port_ff_r,tc2048_port_ff_w)  AM_MIRROR(0xff00)
594	594	ADDRESS_MAP_END
595	595

src/mess/drivers/enterp.c

r14963	r14964
209	209	bit 6 - Disk change signal from disk drive
210	210	bit 7 - DRQ from WD1770
211	211	*/
212		static READ8_HANDLER( exdos_card_r )
	212	READ8_MEMBER(ep_state::exdos_card_r)
213	213	{
214		ep_state *ep = space->machine().driver_data<ep_state>();
215		return ep->exdos_card_value;
	214	return exdos_card_value;
216	215	}
217	216
218	217
r14963	r14964
225	224	bit 6 - disk change reset
226	225	bit 7 - in use
227	226	*/
228		static WRITE8_HANDLER( exdos_card_w )
	227	WRITE8_MEMBER(ep_state::exdos_card_w)
229	228	{
230		device_t *fdc = space->machine().device("wd1770");
	229	device_t *fdc = machine().device("wd1770");
231	230
232	231	/* drive */
233	232	if (BIT(data, 0)) wd17xx_set_drive(fdc, 0);
r14963	r14964
254	253	static ADDRESS_MAP_START( enterprise_io, AS_IO, 8, ep_state )
255	254	ADDRESS_MAP_GLOBAL_MASK(0xff)
256	255	AM_RANGE(0x10, 0x13) AM_MIRROR(0x04) AM_DEVREADWRITE_LEGACY("wd1770", wd17xx_r, wd17xx_w)
257		AM_RANGE(0x18, 0x18) AM_MIRROR(0x04) AM_READWRITE_LEGACY(exdos_card_r, exdos_card_w)
	256	AM_RANGE(0x18, 0x18) AM_MIRROR(0x04) AM_READWRITE(exdos_card_r, exdos_card_w)
258	257	AM_RANGE(0x80, 0x8f) AM_WRITE_LEGACY(epnick_reg_w)
259	258	AM_RANGE(0xa0, 0xbf) AM_DEVREADWRITE_LEGACY("custom", dave_reg_r, dave_reg_w)
260	259	ADDRESS_MAP_END

src/mess/drivers/mbc55x.c

r14963	r14964
67	67
68	68	static ADDRESS_MAP_START(mbc55x_io, AS_IO, 8, mbc55x_state)
69	69	ADDRESS_MAP_GLOBAL_MASK(0xff)
70		AM_RANGE( 0X0000, 0X0003) AM_READWRITE_LEGACY(pic8259_r, pic8259_w)
71		AM_RANGE( 0x0008, 0x000F) AM_READWRITE_LEGACY(mbc55x_disk_r, mbc55x_disk_w)
	70	AM_RANGE( 0X0000, 0X0003) AM_READWRITE(mbcpic8259_r, mbcpic8259_w)
	71	AM_RANGE( 0x0008, 0x000F) AM_READWRITE(mbc55x_disk_r, mbc55x_disk_w)
72	72	AM_RANGE( 0X0010, 0X0010) AM_READWRITE( vram_page_r, vram_page_w)
73	73	AM_RANGE( 0x0018, 0x001F) AM_READWRITE( ppi8255_r, ppi8255_w)
74		AM_RANGE( 0X0020, 0X0027) AM_READWRITE_LEGACY(pit8253_r, pit8253_w)
	74	AM_RANGE( 0X0020, 0X0027) AM_READWRITE(mbcpit8253_r, mbcpit8253_w)
75	75	AM_RANGE( 0x0028, 0x002B) AM_READWRITE( mbc55x_usart_r, mbc55x_usart_w)
76	76	AM_RANGE( 0x0030, 0x0031) AM_DEVREADWRITE(VID_MC6845_NAME, mc6845_device, status_r, address_w )
77	77	AM_RANGE( 0x0032, 0x0033) AM_DEVREADWRITE(VID_MC6845_NAME, mc6845_device, register_r, register_w )
78		AM_RANGE( 0x0038, 0x003B) AM_READWRITE_LEGACY(mbc55x_kb_usart_r, mbc55x_kb_usart_w)
	78	AM_RANGE( 0x0038, 0x003B) AM_READWRITE(mbc55x_kb_usart_r, mbc55x_kb_usart_w)
79	79	ADDRESS_MAP_END
80	80
81	81	static INPUT_PORTS_START( mbc55x )

src/mess/drivers/gp32.c

r14963	r14964
300	300	return 0;
301	301	}
302	302
303		static READ32_HANDLER( s3c240x_lcd_r )
	303	READ32_MEMBER(gp32_state::s3c240x_lcd_r)
304	304	{
305		gp32_state *state = space->machine().driver_data<gp32_state>();
306		running_machine &machine = space->machine();
307		UINT32 data = state->m_s3c240x_lcd_regs[offset];
	305	UINT32 data = m_s3c240x_lcd_regs[offset];
308	306	switch (offset)
309	307	{
310	308	// LCDCON1
311	309	case 0x00 / 4 :
312	310	{
313	311	// make sure line counter is going
314		UINT32 lineval = BITS( state->m_s3c240x_lcd_regs[1], 23, 14);
315		data = (data & ~0xFFFC0000) | ((lineval - machine.primary_screen->vpos()) << 18);
	312	UINT32 lineval = BITS( m_s3c240x_lcd_regs[1], 23, 14);
	313	data = (data & ~0xFFFC0000) | ((lineval - machine().primary_screen->vpos()) << 18);
316	314	}
317	315	break;
318	316	}
319		verboselog( machine, 9, "(LCD) %08X -> %08X (PC %08X)\n", 0x14A00000 + (offset << 2), data, cpu_get_pc( &space->device()));
	317	verboselog( machine(), 9, "(LCD) %08X -> %08X (PC %08X)\n", 0x14A00000 + (offset << 2), data, cpu_get_pc( &space.device()));
320	318	return data;
321	319	}
322	320
r14963	r14964
377	375	}
378	376	}
379	377
380		static WRITE32_HANDLER( s3c240x_lcd_w )
	378	WRITE32_MEMBER(gp32_state::s3c240x_lcd_w)
381	379	{
382		gp32_state *state = space->machine().driver_data<gp32_state>();
383		running_machine &machine = space->machine();
384		UINT32 old_value = state->m_s3c240x_lcd_regs[offset];
385		verboselog( machine, 9, "(LCD) %08X <- %08X (PC %08X)\n", 0x14A00000 + (offset << 2), data, cpu_get_pc( &space->device()));
386		COMBINE_DATA(&state->m_s3c240x_lcd_regs[offset]);
	380	UINT32 old_value = m_s3c240x_lcd_regs[offset];
	381	verboselog( machine(), 9, "(LCD) %08X <- %08X (PC %08X)\n", 0x14A00000 + (offset << 2), data, cpu_get_pc( &space.device()));
	382	COMBINE_DATA(&m_s3c240x_lcd_regs[offset]);
387	383	switch (offset)
388	384	{
389	385	// LCDCON1
r14963	r14964
391	387	{
392	388	if ((old_value & 1) != (data & 1))
393	389	{
394		s3c240x_lcd_recalc( machine);
	390	s3c240x_lcd_recalc( machine());
395	391	}
396	392	}
397	393	break;
r14963	r14964
401	397	// LCD PALETTE
402	398
403	399
404		static READ32_HANDLER( s3c240x_lcd_palette_r )
	400	READ32_MEMBER(gp32_state::s3c240x_lcd_palette_r)
405	401	{
406		gp32_state *state = space->machine().driver_data<gp32_state>();
407		running_machine &machine = space->machine();
408		UINT32 data = state->m_s3c240x_lcd_palette[offset];
409		verboselog( machine, 9, "(LCD) %08X -> %08X (PC %08X)\n", 0x14A00400 + (offset << 2), data, cpu_get_pc( &space->device()));
	402	UINT32 data = m_s3c240x_lcd_palette[offset];
	403	verboselog( machine(), 9, "(LCD) %08X -> %08X (PC %08X)\n", 0x14A00400 + (offset << 2), data, cpu_get_pc( &space.device()));
410	404	return data;
411	405	}
412	406
413		static WRITE32_HANDLER( s3c240x_lcd_palette_w )
	407	WRITE32_MEMBER(gp32_state::s3c240x_lcd_palette_w)
414	408	{
415		gp32_state *state = space->machine().driver_data<gp32_state>();
416		running_machine &machine = space->machine();
417		verboselog( machine, 9, "(LCD) %08X <- %08X (PC %08X)\n", 0x14A00400 + (offset << 2), data, cpu_get_pc( &space->device()));
418		COMBINE_DATA(&state->m_s3c240x_lcd_palette[offset]);
	409	verboselog( machine(), 9, "(LCD) %08X <- %08X (PC %08X)\n", 0x14A00400 + (offset << 2), data, cpu_get_pc( &space.device()));
	410	COMBINE_DATA(&m_s3c240x_lcd_palette[offset]);
419	411	if (mem_mask != 0xffffffff)
420	412	{
421		verboselog( machine, 0, "s3c240x_lcd_palette_w: unknown mask %08x\n", mem_mask);
	413	verboselog( machine(), 0, "s3c240x_lcd_palette_w: unknown mask %08x\n", mem_mask);
422	414	}
423		palette_set_color( machine, offset, s3c240x_get_color_5551( data & 0xFFFF));
	415	palette_set_color( machine(), offset, s3c240x_get_color_5551( data & 0xFFFF));
424	416	}
425	417
426	418	// CLOCK & POWER MANAGEMENT
r14963	r14964
460	452	return 0;
461	453	}
462	454
463		static READ32_HANDLER( s3c240x_clkpow_r )
	455	READ32_MEMBER(gp32_state::s3c240x_clkpow_r)
464	456	{
465		gp32_state *state = space->machine().driver_data<gp32_state>();
466		running_machine &machine = space->machine();
467		UINT32 data = state->m_s3c240x_clkpow_regs[offset];
468		verboselog( machine, 9, "(CLKPOW) %08X -> %08X (PC %08X)\n", 0x14800000 + (offset << 2), data, cpu_get_pc( &space->device()));
	457	UINT32 data = m_s3c240x_clkpow_regs[offset];
	458	verboselog( machine(), 9, "(CLKPOW) %08X -> %08X (PC %08X)\n", 0x14800000 + (offset << 2), data, cpu_get_pc( &space.device()));
469	459	return data;
470	460	}
471	461
472		static WRITE32_HANDLER( s3c240x_clkpow_w )
	462	WRITE32_MEMBER(gp32_state::s3c240x_clkpow_w)
473	463	{
474		gp32_state *state = space->machine().driver_data<gp32_state>();
475		running_machine &machine = space->machine();
476		verboselog( machine, 9, "(CLKPOW) %08X <- %08X (PC %08X)\n", 0x14800000 + (offset << 2), data, cpu_get_pc( &space->device()));
477		COMBINE_DATA(&state->m_s3c240x_clkpow_regs[offset]);
	464	verboselog( machine(), 9, "(CLKPOW) %08X <- %08X (PC %08X)\n", 0x14800000 + (offset << 2), data, cpu_get_pc( &space.device()));
	465	COMBINE_DATA(&m_s3c240x_clkpow_regs[offset]);
478	466	switch (offset)
479	467	{
480	468	// MPLLCON
481	469	case 0x04 / 4 :
482	470	{
483		machine.device("maincpu")->set_unscaled_clock(s3c240x_get_fclk(state, MPLLCON) * CLOCK_MULTIPLIER);
	471	gp32_state *state = machine().driver_data<gp32_state>();
	472	machine().device("maincpu")->set_unscaled_clock(s3c240x_get_fclk(state, MPLLCON) * CLOCK_MULTIPLIER);
484	473	}
485	474	break;
486	475	}
r14963	r14964
530	519	}
531	520
532	521
533		static READ32_HANDLER( s3c240x_irq_r )
	522	READ32_MEMBER(gp32_state::s3c240x_irq_r)
534	523	{
535		gp32_state *state = space->machine().driver_data<gp32_state>();
536		running_machine &machine = space->machine();
537		UINT32 data = state->m_s3c240x_irq_regs[offset];
538		verboselog( machine, 9, "(IRQ) %08X -> %08X (PC %08X)\n", 0x14400000 + (offset << 2), data, cpu_get_pc( &space->device()));
	524	UINT32 data = m_s3c240x_irq_regs[offset];
	525	verboselog( machine(), 9, "(IRQ) %08X -> %08X (PC %08X)\n", 0x14400000 + (offset << 2), data, cpu_get_pc( &space.device()));
539	526	return data;
540	527	}
541	528
542		static WRITE32_HANDLER( s3c240x_irq_w )
	529	WRITE32_MEMBER(gp32_state::s3c240x_irq_w)
543	530	{
544		gp32_state *state = space->machine().driver_data<gp32_state>();
545		running_machine &machine = space->machine();
546		UINT32 old_value = state->m_s3c240x_irq_regs[offset];
547		verboselog( machine, 9, "(IRQ) %08X <- %08X (PC %08X)\n", 0x14400000 + (offset << 2), data, cpu_get_pc( &space->device()));
548		COMBINE_DATA(&state->m_s3c240x_irq_regs[offset]);
	531	UINT32 old_value = m_s3c240x_irq_regs[offset];
	532	verboselog( machine(), 9, "(IRQ) %08X <- %08X (PC %08X)\n", 0x14400000 + (offset << 2), data, cpu_get_pc( &space.device()));
	533	COMBINE_DATA(&m_s3c240x_irq_regs[offset]);
549	534	switch (offset)
550	535	{
551	536	// SRCPND
552	537	case 0x00 / 4 :
553	538	{
554		state->m_s3c240x_irq_regs[0] = (old_value & ~data); // clear only the bit positions of SRCPND corresponding to those set to one in the data
555		s3c240x_check_pending_irq( machine);
	539	m_s3c240x_irq_regs[0] = (old_value & ~data); // clear only the bit positions of SRCPND corresponding to those set to one in the data
	540	s3c240x_check_pending_irq( machine());
556	541	}
557	542	break;
558	543	// INTPND
559	544	case 0x10 / 4 :
560	545	{
561		state->m_s3c240x_irq_regs[4] = (old_value & ~data); // clear only the bit positions of INTPND corresponding to those set to one in the data
	546	m_s3c240x_irq_regs[4] = (old_value & ~data); // clear only the bit positions of INTPND corresponding to those set to one in the data
562	547	}
563	548	break;
564	549	}
r14963	r14964
591	576	#endif
592	577
593	578
594		static READ32_HANDLER( s3c240x_pwm_r )
	579	READ32_MEMBER(gp32_state::s3c240x_pwm_r)
595	580	{
596		gp32_state *state = space->machine().driver_data<gp32_state>();
597		running_machine &machine = space->machine();
598		UINT32 data = state->m_s3c240x_pwm_regs[offset];
599		verboselog( machine, 9, "(PWM) %08X -> %08X (PC %08X)\n", 0x15100000 + (offset << 2), data, cpu_get_pc( &space->device()));
	581	UINT32 data = m_s3c240x_pwm_regs[offset];
	582	verboselog( machine(), 9, "(PWM) %08X -> %08X (PC %08X)\n", 0x15100000 + (offset << 2), data, cpu_get_pc( &space.device()));
600	583	return data;
601	584	}
602	585
r14963	r14964
658	641	}
659	642	}
660	643
661		static WRITE32_HANDLER( s3c240x_pwm_w )
	644	WRITE32_MEMBER(gp32_state::s3c240x_pwm_w)
662	645	{
663		gp32_state *state = space->machine().driver_data<gp32_state>();
664		running_machine &machine = space->machine();
665		UINT32 old_value = state->m_s3c240x_pwm_regs[offset];
666		verboselog( machine, 9, "(PWM) %08X <- %08X (PC %08X)\n", 0x15100000 + (offset << 2), data, cpu_get_pc( &space->device()));
667		COMBINE_DATA(&state->m_s3c240x_pwm_regs[offset]);
	646	UINT32 old_value = m_s3c240x_pwm_regs[offset];
	647	verboselog( machine(), 9, "(PWM) %08X <- %08X (PC %08X)\n", 0x15100000 + (offset << 2), data, cpu_get_pc( &space.device()));
	648	COMBINE_DATA(&m_s3c240x_pwm_regs[offset]);
668	649	switch (offset)
669	650	{
670	651	// TCON
r14963	r14964
672	653	{
673	654	if ((data & 1) != (old_value & 1))
674	655	{
675		s3c240x_pwm_recalc( machine, 0);
	656	s3c240x_pwm_recalc( machine(), 0);
676	657	}
677	658	if ((data & 0x100) != (old_value & 0x100))
678	659	{
679		s3c240x_pwm_recalc( machine, 1);
	660	s3c240x_pwm_recalc( machine(), 1);
680	661	}
681	662	if ((data & 0x1000) != (old_value & 0x1000))
682	663	{
683		s3c240x_pwm_recalc( machine, 2);
	664	s3c240x_pwm_recalc( machine(), 2);
684	665	}
685	666	if ((data & 0x10000) != (old_value & 0x10000))
686	667	{
687		s3c240x_pwm_recalc( machine, 3);
	668	s3c240x_pwm_recalc( machine(), 3);
688	669	}
689	670	if ((data & 0x100000) != (old_value & 0x100000))
690	671	{
691		s3c240x_pwm_recalc( machine, 4);
	672	s3c240x_pwm_recalc( machine(), 4);
692	673	}
693	674	}
694	675	}
r14963	r14964
855	836	}
856	837	}
857	838
858		static READ32_HANDLER( s3c240x_dma_r )
	839	READ32_MEMBER(gp32_state::s3c240x_dma_r)
859	840	{
860		gp32_state *state = space->machine().driver_data<gp32_state>();
861		running_machine &machine = space->machine();
862		UINT32 data = state->m_s3c240x_dma_regs[offset];
863		verboselog( machine, 9, "(DMA) %08X -> %08X (PC %08X)\n", 0x14600000 + (offset << 2), data, cpu_get_pc( &space->device()));
	841	UINT32 data = m_s3c240x_dma_regs[offset];
	842	verboselog( machine(), 9, "(DMA) %08X -> %08X (PC %08X)\n", 0x14600000 + (offset << 2), data, cpu_get_pc( &space.device()));
864	843	return data;
865	844	}
866	845
867		static WRITE32_HANDLER( s3c240x_dma_w )
	846	WRITE32_MEMBER(gp32_state::s3c240x_dma_w)
868	847	{
869		gp32_state *state = space->machine().driver_data<gp32_state>();
870		running_machine &machine = space->machine();
871		UINT32 old_value = state->m_s3c240x_dma_regs[offset];
872		verboselog( machine, 9, "(DMA) %08X <- %08X (PC %08X)\n", 0x14600000 + (offset << 2), data, cpu_get_pc( &space->device()));
873		COMBINE_DATA(&state->m_s3c240x_dma_regs[offset]);
	848	UINT32 old_value = m_s3c240x_dma_regs[offset];
	849	verboselog( machine(), 9, "(DMA) %08X <- %08X (PC %08X)\n", 0x14600000 + (offset << 2), data, cpu_get_pc( &space.device()));
	850	COMBINE_DATA(&m_s3c240x_dma_regs[offset]);
874	851	switch (offset)
875	852	{
876	853	// DCON0
r14963	r14964
878	855	{
879	856	if (((data >> 22) & 1) != 0) // reload
880	857	{
881		state->m_s3c240x_dma_regs[0x18/4] &= ~(1 << 1); // clear on/off
	858	m_s3c240x_dma_regs[0x18/4] &= ~(1 << 1); // clear on/off
882	859	}
883	860	}
884	861	break;
885	862	// DMASKTRIG0
886	863	case 0x18 / 4 :
887	864	{
888		if ((old_value & 2) != (data & 2)) s3c240x_dma_recalc( machine, 0);
	865	if ((old_value & 2) != (data & 2)) s3c240x_dma_recalc( machine(), 0);
889	866	}
890	867	break;
891	868	// DCON1
r14963	r14964
893	870	{
894	871	if (((data >> 22) & 1) != 0) // reload
895	872	{
896		state->m_s3c240x_dma_regs[0x38/4] &= ~(1 << 1); // clear on/off
	873	m_s3c240x_dma_regs[0x38/4] &= ~(1 << 1); // clear on/off
897	874	}
898	875	}
899	876	break;
900	877	// DMASKTRIG1
901	878	case 0x38 / 4 :
902	879	{
903		if ((old_value & 2) != (data & 2)) s3c240x_dma_recalc( machine, 1);
	880	if ((old_value & 2) != (data & 2)) s3c240x_dma_recalc( machine(), 1);
904	881	}
905	882	break;
906	883	// DCON2
r14963	r14964
908	885	{
909	886	if (((data >> 22) & 1) != 0) // reload
910	887	{
911		state->m_s3c240x_dma_regs[0x58/4] &= ~(1 << 1); // clear on/off
	888	m_s3c240x_dma_regs[0x58/4] &= ~(1 << 1); // clear on/off
912	889	}
913	890	}
914	891	break;
915	892	// DMASKTRIG2
916	893	case 0x58 / 4 :
917	894	{
918		if ((old_value & 2) != (data & 2)) s3c240x_dma_recalc( machine, 2);
	895	if ((old_value & 2) != (data & 2)) s3c240x_dma_recalc( machine(), 2);
919	896	}
920	897	break;
921	898	// DCON3
r14963	r14964
923	900	{
924	901	if (((data >> 22) & 1) != 0) // reload
925	902	{
926		state->m_s3c240x_dma_regs[0x78/4] &= ~(1 << 1); // clear on/off
	903	m_s3c240x_dma_regs[0x78/4] &= ~(1 << 1); // clear on/off
927	904	}
928	905	}
929	906	break;
930	907	// DMASKTRIG3
931	908	case 0x78 / 4 :
932	909	{
933		if ((old_value & 2) != (data & 2)) s3c240x_dma_recalc( machine, 3);
	910	if ((old_value & 2) != (data & 2)) s3c240x_dma_recalc( machine(), 3);
934	911	}
935	912	break;
936	913	}
r14963	r14964
1077	1054	// I/O PORT
1078	1055
1079	1056
1080		static READ32_HANDLER( s3c240x_gpio_r )
	1057	READ32_MEMBER(gp32_state::s3c240x_gpio_r)
1081	1058	{
1082		gp32_state *state = space->machine().driver_data<gp32_state>();
1083		running_machine &machine = space->machine();
1084		UINT32 data = state->m_s3c240x_gpio[offset];
	1059	UINT32 data = m_s3c240x_gpio[offset];
1085	1060	switch (offset)
1086	1061	{
1087	1062	// PBCON
r14963	r14964
1089	1064	{
1090	1065	// smartmedia
1091	1066	data = (data & ~0x00000001);
1092		if (!state->m_smc.read) data = data | 0x00000001;
	1067	if (!m_smc.read) data = data | 0x00000001;
1093	1068	}
1094	1069	break;
1095	1070	// PBDAT
1096	1071	case 0x0C / 4 :
1097	1072	{
1098	1073	// smartmedia
1099		data = (data & ~0x000000FF) | (state->m_smc.datarx & 0xFF);
	1074	data = (data & ~0x000000FF) | (m_smc.datarx & 0xFF);
1100	1075	// buttons
1101		data = (data & ~0x0000FF00) | (input_port_read( machine, "IN0") & 0x0000FF00);
	1076	data = (data & ~0x0000FF00) | (input_port_read( machine(), "IN0") & 0x0000FF00);
1102	1077	}
1103	1078	break;
1104	1079	// PDDAT
1105	1080	case 0x24 / 4 :
1106	1081	{
1107		smartmedia_image_device *smartmedia = machine.device<smartmedia_image_device>( "smartmedia");
	1082	smartmedia_image_device *smartmedia = machine().device<smartmedia_image_device>( "smartmedia");
1108	1083	// smartmedia
1109	1084	data = (data & ~0x000003C0);
1110		if (!state->m_smc.busy) data = data | 0x00000200;
1111		if (!state->m_smc.do_read) data = data | 0x00000100;
1112		if (!state->m_smc.chip) data = data | 0x00000080;
	1085	if (!m_smc.busy) data = data | 0x00000200;
	1086	if (!m_smc.do_read) data = data | 0x00000100;
	1087	if (!m_smc.chip) data = data | 0x00000080;
1113	1088	if (!smartmedia->is_protected()) data = data | 0x00000040;
1114	1089	}
1115	1090	break;
1116	1091	// PEDAT
1117	1092	case 0x30 / 4 :
1118	1093	{
1119		smartmedia_image_device *smartmedia = machine.device<smartmedia_image_device>( "smartmedia");
	1094	smartmedia_image_device *smartmedia = machine().device<smartmedia_image_device>( "smartmedia");
1120	1095	// smartmedia
1121	1096	data = (data & ~0x0000003C);
1122		if (state->m_smc.cmd_latch) data = data | 0x00000020;
1123		if (state->m_smc.add_latch) data = data | 0x00000010;
1124		if (!state->m_smc.do_write) data = data | 0x00000008;
	1097	if (m_smc.cmd_latch) data = data | 0x00000020;
	1098	if (m_smc.add_latch) data = data | 0x00000010;
	1099	if (!m_smc.do_write) data = data | 0x00000008;
1125	1100	if (!smartmedia->is_present()) data = data | 0x00000004;
1126	1101	// buttons
1127		data = (data & ~0x000000C0) | (input_port_read( machine, "IN1") & 0x000000C0);
	1102	data = (data & ~0x000000C0) | (input_port_read( machine(), "IN1") & 0x000000C0);
1128	1103	}
1129	1104	break;
1130	1105	}
1131		verboselog( machine, 9, "(GPIO) %08X -> %08X (PC %08X)\n", 0x15600000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1106	verboselog( machine(), 9, "(GPIO) %08X -> %08X (PC %08X)\n", 0x15600000 + (offset << 2), data, cpu_get_pc( &space.device()));
1132	1107	return data;
1133	1108	}
1134	1109
1135		static WRITE32_HANDLER( s3c240x_gpio_w )
	1110	WRITE32_MEMBER(gp32_state::s3c240x_gpio_w)
1136	1111	{
1137		gp32_state *state = space->machine().driver_data<gp32_state>();
1138		running_machine &machine = space->machine();
1139		COMBINE_DATA(&state->m_s3c240x_gpio[offset]);
1140		verboselog( machine, 9, "(GPIO) %08X <- %08X (PC %08X)\n", 0x15600000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1112	COMBINE_DATA(&m_s3c240x_gpio[offset]);
	1113	verboselog( machine(), 9, "(GPIO) %08X <- %08X (PC %08X)\n", 0x15600000 + (offset << 2), data, cpu_get_pc( &space.device()));
1141	1114	switch (offset)
1142	1115	{
1143	1116	// PBCON
1144	1117	case 0x08 / 4 :
1145	1118	{
1146	1119	// smartmedia
1147		state->m_smc.read = ((data & 0x00000001) == 0);
1148		smc_update( machine);
	1120	m_smc.read = ((data & 0x00000001) == 0);
	1121	smc_update( machine());
1149	1122	}
1150	1123	break;
1151	1124	// PBDAT
1152	1125	case 0x0C / 4 :
1153	1126	{
1154	1127	// smartmedia
1155		state->m_smc.datatx = data & 0xFF;
	1128	m_smc.datatx = data & 0xFF;
1156	1129	}
1157	1130	break;
1158	1131	// PDDAT
1159	1132	case 0x24 / 4 :
1160	1133	{
1161	1134	// smartmedia
1162		state->m_smc.do_read = ((data & 0x00000100) == 0);
1163		state->m_smc.chip = ((data & 0x00000080) == 0);
1164		state->m_smc.wp = ((data & 0x00000040) == 0);
1165		smc_update( machine);
	1135	m_smc.do_read = ((data & 0x00000100) == 0);
	1136	m_smc.chip = ((data & 0x00000080) == 0);
	1137	m_smc.wp = ((data & 0x00000040) == 0);
	1138	smc_update( machine());
1166	1139	}
1167	1140	break;
1168	1141	// PEDAT
1169	1142	case 0x30 / 4 :
1170	1143	{
1171	1144	// smartmedia
1172		state->m_smc.cmd_latch = ((data & 0x00000020) != 0);
1173		state->m_smc.add_latch = ((data & 0x00000010) != 0);
1174		state->m_smc.do_write = ((data & 0x00000008) == 0);
1175		smc_update( machine);
	1145	m_smc.cmd_latch = ((data & 0x00000020) != 0);
	1146	m_smc.add_latch = ((data & 0x00000010) != 0);
	1147	m_smc.do_write = ((data & 0x00000008) == 0);
	1148	smc_update( machine());
1176	1149	// sound
1177		i2s_write( machine, I2S_L3D, (data & 0x00000800) ? 1 : 0);
1178		i2s_write( machine, I2S_L3M, (data & 0x00000400) ? 1 : 0);
1179		i2s_write( machine, I2S_L3C, (data & 0x00000200) ? 1 : 0);
	1150	i2s_write( machine(), I2S_L3D, (data & 0x00000800) ? 1 : 0);
	1151	i2s_write( machine(), I2S_L3M, (data & 0x00000400) ? 1 : 0);
	1152	i2s_write( machine(), I2S_L3C, (data & 0x00000200) ? 1 : 0);
1180	1153	}
1181	1154	break;
1182	1155	#if 0
r14963	r14964
1194	1167	// MEMORY CONTROLLER
1195	1168
1196	1169
1197		static READ32_HANDLER( s3c240x_memcon_r )
	1170	READ32_MEMBER(gp32_state::s3c240x_memcon_r)
1198	1171	{
1199		gp32_state *state = space->machine().driver_data<gp32_state>();
1200		running_machine &machine = space->machine();
1201		UINT32 data = state->m_s3c240x_memcon_regs[offset];
1202		verboselog( machine, 9, "(MEMCON) %08X -> %08X (PC %08X)\n", 0x14000000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1172	UINT32 data = m_s3c240x_memcon_regs[offset];
	1173	verboselog( machine(), 9, "(MEMCON) %08X -> %08X (PC %08X)\n", 0x14000000 + (offset << 2), data, cpu_get_pc( &space.device()));
1203	1174	return data;
1204	1175	}
1205	1176
1206		static WRITE32_HANDLER( s3c240x_memcon_w )
	1177	WRITE32_MEMBER(gp32_state::s3c240x_memcon_w)
1207	1178	{
1208		gp32_state *state = space->machine().driver_data<gp32_state>();
1209		running_machine &machine = space->machine();
1210		verboselog( machine, 9, "(MEMCON) %08X <- %08X (PC %08X)\n", 0x14000000 + (offset << 2), data, cpu_get_pc( &space->device()));
1211		COMBINE_DATA(&state->m_s3c240x_memcon_regs[offset]);
	1179	verboselog( machine(), 9, "(MEMCON) %08X <- %08X (PC %08X)\n", 0x14000000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1180	COMBINE_DATA(&m_s3c240x_memcon_regs[offset]);
1212	1181	}
1213	1182
1214	1183	// USB HOST CONTROLLER
1215	1184
1216	1185
1217		static READ32_HANDLER( s3c240x_usb_host_r )
	1186	READ32_MEMBER(gp32_state::s3c240x_usb_host_r)
1218	1187	{
1219		gp32_state *state = space->machine().driver_data<gp32_state>();
1220		running_machine &machine = space->machine();
1221		UINT32 data = state->m_s3c240x_usb_host_regs[offset];
1222		verboselog( machine, 9, "(USB H) %08X -> %08X (PC %08X)\n", 0x14200000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1188	UINT32 data = m_s3c240x_usb_host_regs[offset];
	1189	verboselog( machine(), 9, "(USB H) %08X -> %08X (PC %08X)\n", 0x14200000 + (offset << 2), data, cpu_get_pc( &space.device()));
1223	1190	return data;
1224	1191	}
1225	1192
1226		static WRITE32_HANDLER( s3c240x_usb_host_w )
	1193	WRITE32_MEMBER(gp32_state::s3c240x_usb_host_w)
1227	1194	{
1228		gp32_state *state = space->machine().driver_data<gp32_state>();
1229		running_machine &machine = space->machine();
1230		verboselog( machine, 9, "(USB H) %08X <- %08X (PC %08X)\n", 0x14200000 + (offset << 2), data, cpu_get_pc( &space->device()));
1231		COMBINE_DATA(&state->m_s3c240x_usb_host_regs[offset]);
	1195	verboselog( machine(), 9, "(USB H) %08X <- %08X (PC %08X)\n", 0x14200000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1196	COMBINE_DATA(&m_s3c240x_usb_host_regs[offset]);
1232	1197	}
1233	1198
1234	1199	// UART 0
1235	1200
1236	1201
1237		static READ32_HANDLER( s3c240x_uart_0_r )
	1202	READ32_MEMBER(gp32_state::s3c240x_uart_0_r)
1238	1203	{
1239		gp32_state *state = space->machine().driver_data<gp32_state>();
1240		running_machine &machine = space->machine();
1241		UINT32 data = state->m_s3c240x_uart_0_regs[offset];
	1204	UINT32 data = m_s3c240x_uart_0_regs[offset];
1242	1205	switch (offset)
1243	1206	{
1244	1207	// UTRSTAT0
r14963	r14964
1248	1211	}
1249	1212	break;
1250	1213	}
1251		verboselog( machine, 9, "(UART 0) %08X -> %08X (PC %08X)\n", 0x15000000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1214	verboselog( machine(), 9, "(UART 0) %08X -> %08X (PC %08X)\n", 0x15000000 + (offset << 2), data, cpu_get_pc( &space.device()));
1252	1215	return data;
1253	1216	}
1254	1217
1255		static WRITE32_HANDLER( s3c240x_uart_0_w )
	1218	WRITE32_MEMBER(gp32_state::s3c240x_uart_0_w)
1256	1219	{
1257		gp32_state *state = space->machine().driver_data<gp32_state>();
1258		running_machine &machine = space->machine();
1259		verboselog( machine, 9, "(UART 0) %08X <- %08X (PC %08X)\n", 0x15000000 + (offset << 2), data, cpu_get_pc( &space->device()));
1260		COMBINE_DATA(&state->m_s3c240x_uart_0_regs[offset]);
	1220	verboselog( machine(), 9, "(UART 0) %08X <- %08X (PC %08X)\n", 0x15000000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1221	COMBINE_DATA(&m_s3c240x_uart_0_regs[offset]);
1261	1222	}
1262	1223
1263	1224	// UART 1
1264	1225
1265	1226
1266		static READ32_HANDLER( s3c240x_uart_1_r )
	1227	READ32_MEMBER(gp32_state::s3c240x_uart_1_r)
1267	1228	{
1268		gp32_state *state = space->machine().driver_data<gp32_state>();
1269		running_machine &machine = space->machine();
1270		UINT32 data = state->m_s3c240x_uart_1_regs[offset];
	1229	UINT32 data = m_s3c240x_uart_1_regs[offset];
1271	1230	switch (offset)
1272	1231	{
1273	1232	// UTRSTAT1
r14963	r14964
1277	1236	}
1278	1237	break;
1279	1238	}
1280		verboselog( machine, 9, "(UART 1) %08X -> %08X (PC %08X)\n", 0x15004000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1239	verboselog( machine(), 9, "(UART 1) %08X -> %08X (PC %08X)\n", 0x15004000 + (offset << 2), data, cpu_get_pc( &space.device()));
1281	1240	return data;
1282	1241	}
1283	1242
1284		static WRITE32_HANDLER( s3c240x_uart_1_w )
	1243	WRITE32_MEMBER(gp32_state::s3c240x_uart_1_w)
1285	1244	{
1286		gp32_state *state = space->machine().driver_data<gp32_state>();
1287		running_machine &machine = space->machine();
1288		verboselog( machine, 9, "(UART 1) %08X <- %08X (PC %08X)\n", 0x15004000 + (offset << 2), data, cpu_get_pc( &space->device()));
1289		COMBINE_DATA(&state->m_s3c240x_uart_1_regs[offset]);
	1245	verboselog( machine(), 9, "(UART 1) %08X <- %08X (PC %08X)\n", 0x15004000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1246	COMBINE_DATA(&m_s3c240x_uart_1_regs[offset]);
1290	1247	}
1291	1248
1292	1249	// USB DEVICE
1293	1250
1294	1251
1295		static READ32_HANDLER( s3c240x_usb_device_r )
	1252	READ32_MEMBER(gp32_state::s3c240x_usb_device_r)
1296	1253	{
1297		gp32_state *state = space->machine().driver_data<gp32_state>();
1298		running_machine &machine = space->machine();
1299		UINT32 data = state->m_s3c240x_usb_device_regs[offset];
1300		verboselog( machine, 9, "(USB D) %08X -> %08X (PC %08X)\n", 0x15200140 + (offset << 2), data, cpu_get_pc( &space->device()));
	1254	UINT32 data = m_s3c240x_usb_device_regs[offset];
	1255	verboselog( machine(), 9, "(USB D) %08X -> %08X (PC %08X)\n", 0x15200140 + (offset << 2), data, cpu_get_pc( &space.device()));
1301	1256	return data;
1302	1257	}
1303	1258
1304		static WRITE32_HANDLER( s3c240x_usb_device_w )
	1259	WRITE32_MEMBER(gp32_state::s3c240x_usb_device_w)
1305	1260	{
1306		gp32_state *state = space->machine().driver_data<gp32_state>();
1307		running_machine &machine = space->machine();
1308		verboselog( machine, 9, "(USB D) %08X <- %08X (PC %08X)\n", 0x15200140 + (offset << 2), data, cpu_get_pc( &space->device()));
1309		COMBINE_DATA(&state->m_s3c240x_usb_device_regs[offset]);
	1261	verboselog( machine(), 9, "(USB D) %08X <- %08X (PC %08X)\n", 0x15200140 + (offset << 2), data, cpu_get_pc( &space.device()));
	1262	COMBINE_DATA(&m_s3c240x_usb_device_regs[offset]);
1310	1263	}
1311	1264
1312	1265	// WATCHDOG TIMER
1313	1266
1314	1267
1315		static READ32_HANDLER( s3c240x_watchdog_r )
	1268	READ32_MEMBER(gp32_state::s3c240x_watchdog_r)
1316	1269	{
1317		gp32_state *state = space->machine().driver_data<gp32_state>();
1318		running_machine &machine = space->machine();
1319		UINT32 data = state->m_s3c240x_watchdog_regs[offset];
1320		verboselog( machine, 9, "(WDOG) %08X -> %08X (PC %08X)\n", 0x15300000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1270	UINT32 data = m_s3c240x_watchdog_regs[offset];
	1271	verboselog( machine(), 9, "(WDOG) %08X -> %08X (PC %08X)\n", 0x15300000 + (offset << 2), data, cpu_get_pc( &space.device()));
1321	1272	return data;
1322	1273	}
1323	1274
1324		static WRITE32_HANDLER( s3c240x_watchdog_w )
	1275	WRITE32_MEMBER(gp32_state::s3c240x_watchdog_w)
1325	1276	{
1326		gp32_state *state = space->machine().driver_data<gp32_state>();
1327		running_machine &machine = space->machine();
1328		verboselog( machine, 9, "(WDOG) %08X <- %08X (PC %08X)\n", 0x15300000 + (offset << 2), data, cpu_get_pc( &space->device()));
1329		COMBINE_DATA(&state->m_s3c240x_watchdog_regs[offset]);
	1277	verboselog( machine(), 9, "(WDOG) %08X <- %08X (PC %08X)\n", 0x15300000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1278	COMBINE_DATA(&m_s3c240x_watchdog_regs[offset]);
1330	1279	}
1331	1280
1332	1281	// EEPROM
r14963	r14964
1427	1376	state->m_s3c240x_iic_timer->adjust( attotime::from_msec( 1));
1428	1377	}
1429	1378
1430		static READ32_HANDLER( s3c240x_iic_r )
	1379	READ32_MEMBER(gp32_state::s3c240x_iic_r)
1431	1380	{
1432		gp32_state *state = space->machine().driver_data<gp32_state>();
1433		running_machine &machine = space->machine();
1434		UINT32 data = state->m_s3c240x_iic_regs[offset];
	1381	UINT32 data = m_s3c240x_iic_regs[offset];
1435	1382	switch (offset)
1436	1383	{
1437	1384	// IICSTAT
r14963	r14964
1441	1388	}
1442	1389	break;
1443	1390	}
1444		verboselog( machine, 9, "(IIC) %08X -> %08X (PC %08X)\n", 0x15400000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1391	verboselog( machine(), 9, "(IIC) %08X -> %08X (PC %08X)\n", 0x15400000 + (offset << 2), data, cpu_get_pc( &space.device()));
1445	1392	return data;
1446	1393	}
1447	1394
1448		static WRITE32_HANDLER( s3c240x_iic_w )
	1395	WRITE32_MEMBER(gp32_state::s3c240x_iic_w)
1449	1396	{
1450		gp32_state *state = space->machine().driver_data<gp32_state>();
1451		running_machine &machine = space->machine();
1452		verboselog( machine, 9, "(IIC) %08X <- %08X (PC %08X)\n", 0x15400000 + (offset << 2), data, cpu_get_pc( &space->device()));
1453		COMBINE_DATA(&state->m_s3c240x_iic_regs[offset]);
	1397	verboselog( machine(), 9, "(IIC) %08X <- %08X (PC %08X)\n", 0x15400000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1398	COMBINE_DATA(&m_s3c240x_iic_regs[offset]);
1454	1399	switch (offset)
1455	1400	{
1456	1401	// ADDR_IICCON
r14963	r14964
1470	1415	if (interrupt_pending_flag == 0)
1471	1416	{
1472	1417	int start_stop_condition;
1473		start_stop_condition = BIT( state->m_s3c240x_iic_regs[1], 5);
	1418	start_stop_condition = BIT( m_s3c240x_iic_regs[1], 5);
1474	1419	if (start_stop_condition != 0)
1475	1420	{
1476		iic_resume( machine);
	1421	iic_resume( machine());
1477	1422	}
1478	1423	}
1479	1424	}
r14963	r14964
1485	1430	start_stop_condition = BIT( data, 5);
1486	1431	if (start_stop_condition != 0)
1487	1432	{
1488		iic_start( machine);
	1433	iic_start( machine());
1489	1434	}
1490	1435	else
1491	1436	{
1492		iic_stop( machine);
	1437	iic_stop( machine());
1493	1438	}
1494	1439	}
1495	1440	break;
r14963	r14964
1583	1528	}
1584	1529	}
1585	1530
1586		static READ32_HANDLER( s3c240x_iis_r )
	1531	READ32_MEMBER(gp32_state::s3c240x_iis_r)
1587	1532	{
1588		gp32_state *state = space->machine().driver_data<gp32_state>();
1589		running_machine &machine = space->machine();
1590		UINT32 data = state->m_s3c240x_iis_regs[offset];
	1533	UINT32 data = m_s3c240x_iis_regs[offset];
1591	1534	#if 0
1592	1535	switch (offset)
1593	1536	{
r14963	r14964
1599	1542	break;
1600	1543	}
1601	1544	#endif
1602		verboselog( machine, 9, "(IIS) %08X -> %08X (PC %08X)\n", 0x15508000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1545	verboselog( machine(), 9, "(IIS) %08X -> %08X (PC %08X)\n", 0x15508000 + (offset << 2), data, cpu_get_pc( &space.device()));
1603	1546	return data;
1604	1547	}
1605	1548
1606		static WRITE32_HANDLER( s3c240x_iis_w )
	1549	WRITE32_MEMBER(gp32_state::s3c240x_iis_w)
1607	1550	{
1608		gp32_state *state = space->machine().driver_data<gp32_state>();
1609		running_machine &machine = space->machine();
1610		UINT32 old_value = state->m_s3c240x_iis_regs[offset];
1611		verboselog( machine, 9, "(IIS) %08X <- %08X (PC %08X)\n", 0x15508000 + (offset << 2), data, cpu_get_pc( &space->device()));
1612		COMBINE_DATA(&state->m_s3c240x_iis_regs[offset]);
	1551	UINT32 old_value = m_s3c240x_iis_regs[offset];
	1552	verboselog( machine(), 9, "(IIS) %08X <- %08X (PC %08X)\n", 0x15508000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1553	COMBINE_DATA(&m_s3c240x_iis_regs[offset]);
1613	1554	switch (offset)
1614	1555	{
1615	1556	// IISCON
1616	1557	case 0x00 / 4 :
1617	1558	{
1618		if ((old_value & 1) != (data & 1)) s3c240x_iis_recalc( machine);
	1559	if ((old_value & 1) != (data & 1)) s3c240x_iis_recalc( machine());
1619	1560	}
1620	1561	break;
1621	1562	// IISFIF
r14963	r14964
1623	1564	{
1624	1565	if (ACCESSING_BITS_16_31)
1625	1566	{
1626		state->m_s3c240x_iis.fifo[state->m_s3c240x_iis.fifo_index++] = BITS( data, 31, 16);
	1567	m_s3c240x_iis.fifo[m_s3c240x_iis.fifo_index++] = BITS( data, 31, 16);
1627	1568	}
1628	1569	if (ACCESSING_BITS_0_15)
1629	1570	{
1630		state->m_s3c240x_iis.fifo[state->m_s3c240x_iis.fifo_index++] = BITS( data, 15, 0);
	1571	m_s3c240x_iis.fifo[m_s3c240x_iis.fifo_index++] = BITS( data, 15, 0);
1631	1572	}
1632		if (state->m_s3c240x_iis.fifo_index == 2)
	1573	if (m_s3c240x_iis.fifo_index == 2)
1633	1574	{
1634	1575	device_t *dac[2];
1635		dac[0] = machine.device( "dac1");
1636		dac[1] = machine.device( "dac2");
1637		state->m_s3c240x_iis.fifo_index = 0;
1638		dac_signed_data_16_w( dac[0], state->m_s3c240x_iis.fifo[0] + 0x8000);
1639		dac_signed_data_16_w( dac[1], state->m_s3c240x_iis.fifo[1] + 0x8000);
	1576	dac[0] = machine().device( "dac1");
	1577	dac[1] = machine().device( "dac2");
	1578	m_s3c240x_iis.fifo_index = 0;
	1579	dac_signed_data_16_w( dac[0], m_s3c240x_iis.fifo[0] + 0x8000);
	1580	dac_signed_data_16_w( dac[1], m_s3c240x_iis.fifo[1] + 0x8000);
1640	1581	}
1641	1582	}
1642	1583	break;
r14963	r14964
1652	1593	// RTC
1653	1594
1654	1595
1655		static READ32_HANDLER( s3c240x_rtc_r )
	1596	READ32_MEMBER(gp32_state::s3c240x_rtc_r)
1656	1597	{
1657		gp32_state *state = space->machine().driver_data<gp32_state>();
1658		running_machine &machine = space->machine();
1659		UINT32 data = state->m_s3c240x_rtc_regs[offset];
1660		verboselog( machine, 9, "(RTC) %08X -> %08X (PC %08X)\n", 0x15700040 + (offset << 2), data, cpu_get_pc( &space->device()));
	1598	UINT32 data = m_s3c240x_rtc_regs[offset];
	1599	verboselog( machine(), 9, "(RTC) %08X -> %08X (PC %08X)\n", 0x15700040 + (offset << 2), data, cpu_get_pc( &space.device()));
1661	1600	return data;
1662	1601	}
1663	1602
1664		static WRITE32_HANDLER( s3c240x_rtc_w )
	1603	WRITE32_MEMBER(gp32_state::s3c240x_rtc_w)
1665	1604	{
1666		gp32_state *state = space->machine().driver_data<gp32_state>();
1667		running_machine &machine = space->machine();
1668		verboselog( machine, 9, "(RTC) %08X <- %08X (PC %08X)\n", 0x15700040 + (offset << 2), data, cpu_get_pc( &space->device()));
1669		COMBINE_DATA(&state->m_s3c240x_rtc_regs[offset]);
	1605	verboselog( machine(), 9, "(RTC) %08X <- %08X (PC %08X)\n", 0x15700040 + (offset << 2), data, cpu_get_pc( &space.device()));
	1606	COMBINE_DATA(&m_s3c240x_rtc_regs[offset]);
1670	1607	}
1671	1608
1672	1609	// A/D CONVERTER
1673	1610
1674	1611
1675		static READ32_HANDLER( s3c240x_adc_r )
	1612	READ32_MEMBER(gp32_state::s3c240x_adc_r)
1676	1613	{
1677		gp32_state *state = space->machine().driver_data<gp32_state>();
1678		running_machine &machine = space->machine();
1679		UINT32 data = state->m_s3c240x_adc_regs[offset];
1680		verboselog( machine, 9, "(ADC) %08X -> %08X (PC %08X)\n", 0x15800000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1614	UINT32 data = m_s3c240x_adc_regs[offset];
	1615	verboselog( machine(), 9, "(ADC) %08X -> %08X (PC %08X)\n", 0x15800000 + (offset << 2), data, cpu_get_pc( &space.device()));
1681	1616	return data;
1682	1617	}
1683	1618
1684		static WRITE32_HANDLER( s3c240x_adc_w )
	1619	WRITE32_MEMBER(gp32_state::s3c240x_adc_w)
1685	1620	{
1686		gp32_state *state = space->machine().driver_data<gp32_state>();
1687		running_machine &machine = space->machine();
1688		verboselog( machine, 9, "(ADC) %08X <- %08X (PC %08X)\n", 0x15800000 + (offset << 2), data, cpu_get_pc( &space->device()));
1689		COMBINE_DATA(&state->m_s3c240x_adc_regs[offset]);
	1621	verboselog( machine(), 9, "(ADC) %08X <- %08X (PC %08X)\n", 0x15800000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1622	COMBINE_DATA(&m_s3c240x_adc_regs[offset]);
1690	1623	}
1691	1624
1692	1625	// SPI
1693	1626
1694	1627
1695		static READ32_HANDLER( s3c240x_spi_r )
	1628	READ32_MEMBER(gp32_state::s3c240x_spi_r)
1696	1629	{
1697		gp32_state *state = space->machine().driver_data<gp32_state>();
1698		running_machine &machine = space->machine();
1699		UINT32 data = state->m_s3c240x_spi_regs[offset];
1700		verboselog( machine, 9, "(SPI) %08X -> %08X (PC %08X)\n", 0x15900000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1630	UINT32 data = m_s3c240x_spi_regs[offset];
	1631	verboselog( machine(), 9, "(SPI) %08X -> %08X (PC %08X)\n", 0x15900000 + (offset << 2), data, cpu_get_pc( &space.device()));
1701	1632	return data;
1702	1633	}
1703	1634
1704		static WRITE32_HANDLER( s3c240x_spi_w )
	1635	WRITE32_MEMBER(gp32_state::s3c240x_spi_w)
1705	1636	{
1706		gp32_state *state = space->machine().driver_data<gp32_state>();
1707		running_machine &machine = space->machine();
1708		verboselog( machine, 9, "(SPI) %08X <- %08X (PC %08X)\n", 0x15900000 + (offset << 2), data, cpu_get_pc( &space->device()));
1709		COMBINE_DATA(&state->m_s3c240x_spi_regs[offset]);
	1637	verboselog( machine(), 9, "(SPI) %08X <- %08X (PC %08X)\n", 0x15900000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1638	COMBINE_DATA(&m_s3c240x_spi_regs[offset]);
1710	1639	}
1711	1640
1712	1641	// MMC INTERFACE
1713	1642
1714	1643
1715		static READ32_HANDLER( s3c240x_mmc_r )
	1644	READ32_MEMBER(gp32_state::s3c240x_mmc_r)
1716	1645	{
1717		gp32_state *state = space->machine().driver_data<gp32_state>();
1718		running_machine &machine = space->machine();
1719		UINT32 data = state->m_s3c240x_mmc_regs[offset];
1720		verboselog( machine, 9, "(MMC) %08X -> %08X (PC %08X)\n", 0x15A00000 + (offset << 2), data, cpu_get_pc( &space->device()));
	1646	UINT32 data = m_s3c240x_mmc_regs[offset];
	1647	verboselog( machine(), 9, "(MMC) %08X -> %08X (PC %08X)\n", 0x15A00000 + (offset << 2), data, cpu_get_pc( &space.device()));
1721	1648	return data;
1722	1649	}
1723	1650
1724		static WRITE32_HANDLER( s3c240x_mmc_w )
	1651	WRITE32_MEMBER(gp32_state::s3c240x_mmc_w)
1725	1652	{
1726		gp32_state *state = space->machine().driver_data<gp32_state>();
1727		running_machine &machine = space->machine();
1728		verboselog( machine, 9, "(MMC) %08X <- %08X (PC %08X)\n", 0x15A00000 + (offset << 2), data, cpu_get_pc( &space->device()));
1729		COMBINE_DATA(&state->m_s3c240x_mmc_regs[offset]);
	1653	verboselog( machine(), 9, "(MMC) %08X <- %08X (PC %08X)\n", 0x15A00000 + (offset << 2), data, cpu_get_pc( &space.device()));
	1654	COMBINE_DATA(&m_s3c240x_mmc_regs[offset]);
1730	1655	}
1731	1656
1732	1657	// ...
r14963	r14964
1764	1689	static ADDRESS_MAP_START( gp32_map, AS_PROGRAM, 32, gp32_state )
1765	1690	AM_RANGE(0x00000000, 0x0007ffff) AM_ROM
1766	1691	AM_RANGE(0x0c000000, 0x0c7fffff) AM_RAM AM_SHARE("s3c240x_ram")
1767		AM_RANGE(0x14000000, 0x1400003b) AM_READWRITE_LEGACY(s3c240x_memcon_r, s3c240x_memcon_w)
1768		AM_RANGE(0x14200000, 0x1420005b) AM_READWRITE_LEGACY(s3c240x_usb_host_r, s3c240x_usb_host_w)
1769		AM_RANGE(0x14400000, 0x14400017) AM_READWRITE_LEGACY(s3c240x_irq_r, s3c240x_irq_w)
1770		AM_RANGE(0x14600000, 0x1460007b) AM_READWRITE_LEGACY(s3c240x_dma_r, s3c240x_dma_w)
1771		AM_RANGE(0x14800000, 0x14800017) AM_READWRITE_LEGACY(s3c240x_clkpow_r, s3c240x_clkpow_w)
1772		AM_RANGE(0x14a00000, 0x14a003ff) AM_READWRITE_LEGACY(s3c240x_lcd_r, s3c240x_lcd_w)
1773		AM_RANGE(0x14a00400, 0x14a007ff) AM_READWRITE_LEGACY(s3c240x_lcd_palette_r, s3c240x_lcd_palette_w)
1774		AM_RANGE(0x15000000, 0x1500002b) AM_READWRITE_LEGACY(s3c240x_uart_0_r, s3c240x_uart_0_w)
1775		AM_RANGE(0x15004000, 0x1500402b) AM_READWRITE_LEGACY(s3c240x_uart_1_r, s3c240x_uart_1_w)
1776		AM_RANGE(0x15100000, 0x15100043) AM_READWRITE_LEGACY(s3c240x_pwm_r, s3c240x_pwm_w)
1777		AM_RANGE(0x15200140, 0x152001fb) AM_READWRITE_LEGACY(s3c240x_usb_device_r, s3c240x_usb_device_w)
1778		AM_RANGE(0x15300000, 0x1530000b) AM_READWRITE_LEGACY(s3c240x_watchdog_r, s3c240x_watchdog_w)
1779		AM_RANGE(0x15400000, 0x1540000f) AM_READWRITE_LEGACY(s3c240x_iic_r, s3c240x_iic_w)
1780		AM_RANGE(0x15508000, 0x15508013) AM_READWRITE_LEGACY(s3c240x_iis_r, s3c240x_iis_w)
1781		AM_RANGE(0x15600000, 0x1560005b) AM_READWRITE_LEGACY(s3c240x_gpio_r, s3c240x_gpio_w)
1782		AM_RANGE(0x15700040, 0x1570008b) AM_READWRITE_LEGACY(s3c240x_rtc_r, s3c240x_rtc_w)
1783		AM_RANGE(0x15800000, 0x15800007) AM_READWRITE_LEGACY(s3c240x_adc_r, s3c240x_adc_w)
1784		AM_RANGE(0x15900000, 0x15900017) AM_READWRITE_LEGACY(s3c240x_spi_r, s3c240x_spi_w)
1785		AM_RANGE(0x15a00000, 0x15a0003f) AM_READWRITE_LEGACY(s3c240x_mmc_r, s3c240x_mmc_w)
	1692	AM_RANGE(0x14000000, 0x1400003b) AM_READWRITE(s3c240x_memcon_r, s3c240x_memcon_w)
	1693	AM_RANGE(0x14200000, 0x1420005b) AM_READWRITE(s3c240x_usb_host_r, s3c240x_usb_host_w)
	1694	AM_RANGE(0x14400000, 0x14400017) AM_READWRITE(s3c240x_irq_r, s3c240x_irq_w)
	1695	AM_RANGE(0x14600000, 0x1460007b) AM_READWRITE(s3c240x_dma_r, s3c240x_dma_w)
	1696	AM_RANGE(0x14800000, 0x14800017) AM_READWRITE(s3c240x_clkpow_r, s3c240x_clkpow_w)
	1697	AM_RANGE(0x14a00000, 0x14a003ff) AM_READWRITE(s3c240x_lcd_r, s3c240x_lcd_w)
	1698	AM_RANGE(0x14a00400, 0x14a007ff) AM_READWRITE(s3c240x_lcd_palette_r, s3c240x_lcd_palette_w)
	1699	AM_RANGE(0x15000000, 0x1500002b) AM_READWRITE(s3c240x_uart_0_r, s3c240x_uart_0_w)
	1700	AM_RANGE(0x15004000, 0x1500402b) AM_READWRITE(s3c240x_uart_1_r, s3c240x_uart_1_w)
	1701	AM_RANGE(0x15100000, 0x15100043) AM_READWRITE(s3c240x_pwm_r, s3c240x_pwm_w)
	1702	AM_RANGE(0x15200140, 0x152001fb) AM_READWRITE(s3c240x_usb_device_r, s3c240x_usb_device_w)
	1703	AM_RANGE(0x15300000, 0x1530000b) AM_READWRITE(s3c240x_watchdog_r, s3c240x_watchdog_w)
	1704	AM_RANGE(0x15400000, 0x1540000f) AM_READWRITE(s3c240x_iic_r, s3c240x_iic_w)
	1705	AM_RANGE(0x15508000, 0x15508013) AM_READWRITE(s3c240x_iis_r, s3c240x_iis_w)
	1706	AM_RANGE(0x15600000, 0x1560005b) AM_READWRITE(s3c240x_gpio_r, s3c240x_gpio_w)
	1707	AM_RANGE(0x15700040, 0x1570008b) AM_READWRITE(s3c240x_rtc_r, s3c240x_rtc_w)
	1708	AM_RANGE(0x15800000, 0x15800007) AM_READWRITE(s3c240x_adc_r, s3c240x_adc_w)
	1709	AM_RANGE(0x15900000, 0x15900017) AM_READWRITE(s3c240x_spi_r, s3c240x_spi_w)
	1710	AM_RANGE(0x15a00000, 0x15a0003f) AM_READWRITE(s3c240x_mmc_r, s3c240x_mmc_w)
1786	1711	ADDRESS_MAP_END
1787	1712
1788	1713	static INPUT_PORTS_START( gp32 )

src/mess/drivers/partner.c

r14963	r14964
36	36	AM_RANGE( 0xd000, 0xd7ff ) AM_RAMBANK("bank10")
37	37	AM_RANGE( 0xd800, 0xd8ff ) AM_DEVREADWRITE_LEGACY("i8275", i8275_r, i8275_w)  // video
38	38	AM_RANGE( 0xd900, 0xd9ff ) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
39		AM_RANGE( 0xda00, 0xdaff ) AM_WRITE_LEGACY(partner_mem_page_w)
	39	AM_RANGE( 0xda00, 0xdaff ) AM_WRITE(partner_mem_page_w)
40	40	AM_RANGE( 0xdb00, 0xdbff ) AM_DEVWRITE_LEGACY("dma8257", i8257_w)    // DMA
41	41	AM_RANGE( 0xdc00, 0xddff ) AM_RAMBANK("bank11")
42		AM_RANGE( 0xde00, 0xdeff ) AM_WRITE_LEGACY(partner_win_memory_page_w)
	42	AM_RANGE( 0xde00, 0xdeff ) AM_WRITE(partner_win_memory_page_w)
43	43	AM_RANGE( 0xe000, 0xe7ff ) AM_RAMBANK("bank12")
44	44	AM_RANGE( 0xe800, 0xffff ) AM_RAMBANK("bank13")
45	45	ADDRESS_MAP_END

src/mess/drivers/apple1.c

r14963	r14964
140	140	AM_RANGE(0x0000, 0xbfff) AM_NOP
141	141
142	142	/* Cassette interface I/O space: */
143		AM_RANGE(0xc000, 0xc0ff) AM_READWRITE_LEGACY(apple1_cassette_r, apple1_cassette_w)
	143	AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(apple1_cassette_r, apple1_cassette_w)
144	144	/* Cassette interface ROM: */
145	145	AM_RANGE(0xc100, 0xc1ff) AM_ROM
146	146

src/mess/drivers/hec2hrp.c

r14963	r14964
120	120	/*****************************************************************************/
121	121	ADDRESS_MAP_UNMAP_HIGH
122	122	/* Hardware address mapping*/
123		AM_RANGE(0x0800,0x0808) AM_WRITE_LEGACY(hector_switch_bank_w)/* Bank management*/
124		AM_RANGE(0x1000,0x1000) AM_WRITE_LEGACY(hector_color_a_w)  /* Color c0/c1*/
125		AM_RANGE(0x1800,0x1800) AM_WRITE_LEGACY(hector_color_b_w)  /* Color c2/c3*/
126		AM_RANGE(0x2000,0x2003) AM_WRITE_LEGACY(hector_sn_2000_w)  /* Sound*/
127		AM_RANGE(0x2800,0x2803) AM_WRITE_LEGACY(hector_sn_2800_w)  /* Sound*/
128		AM_RANGE(0x3000,0x3000) AM_READWRITE_LEGACY(hector_cassette_r, hector_sn_3000_w)/* Write necessary*/
129		AM_RANGE(0x3800,0x3807) AM_READWRITE_LEGACY(hector_keyboard_r, hector_keyboard_w)  /* Keyboard*/
	123	AM_RANGE(0x0800,0x0808) AM_WRITE(hector_switch_bank_w)/* Bank management*/
	124	AM_RANGE(0x1000,0x1000) AM_WRITE(hector_color_a_w)  /* Color c0/c1*/
	125	AM_RANGE(0x1800,0x1800) AM_WRITE(hector_color_b_w)  /* Color c2/c3*/
	126	AM_RANGE(0x2000,0x2003) AM_WRITE(hector_sn_2000_w)  /* Sound*/
	127	AM_RANGE(0x2800,0x2803) AM_WRITE(hector_sn_2800_w)  /* Sound*/
	128	AM_RANGE(0x3000,0x3000) AM_READWRITE(hector_cassette_r, hector_sn_3000_w)/* Write necessary*/
	129	AM_RANGE(0x3800,0x3807) AM_READWRITE(hector_keyboard_r, hector_keyboard_w)  /* Keyboard*/
130	130
131	131	/* Main ROM page*/
132	132	AM_RANGE(0x0000,0x3fff) AM_ROM
r14963	r14964
144	144	/*****************************************************************************/
145	145	ADDRESS_MAP_UNMAP_HIGH
146	146	/* Hardware address mapping*/
147		AM_RANGE(0x0800,0x0808) AM_WRITE_LEGACY(hector_switch_bank_w)/* Bank management*/
148		AM_RANGE(0x1000,0x1000) AM_WRITE_LEGACY(hector_color_a_w)  /* Color c0/c1*/
149		AM_RANGE(0x1800,0x1800) AM_WRITE_LEGACY(hector_color_b_w)  /* Color c2/c3*/
150		AM_RANGE(0x2000,0x2003) AM_WRITE_LEGACY(hector_sn_2000_w)  /* Sound*/
151		AM_RANGE(0x2800,0x2803) AM_WRITE_LEGACY(hector_sn_2800_w)  /* Sound*/
152		AM_RANGE(0x3000,0x3000) AM_READWRITE_LEGACY(hector_cassette_r, hector_sn_3000_w)/* Write necessary*/
153		AM_RANGE(0x3800,0x3807) AM_READWRITE_LEGACY(hector_keyboard_r, hector_keyboard_w)  /* Keyboard*/
	147	AM_RANGE(0x0800,0x0808) AM_WRITE(hector_switch_bank_w)/* Bank management*/
	148	AM_RANGE(0x1000,0x1000) AM_WRITE(hector_color_a_w)  /* Color c0/c1*/
	149	AM_RANGE(0x1800,0x1800) AM_WRITE(hector_color_b_w)  /* Color c2/c3*/
	150	AM_RANGE(0x2000,0x2003) AM_WRITE(hector_sn_2000_w)  /* Sound*/
	151	AM_RANGE(0x2800,0x2803) AM_WRITE(hector_sn_2800_w)  /* Sound*/
	152	AM_RANGE(0x3000,0x3000) AM_READWRITE(hector_cassette_r, hector_sn_3000_w)/* Write necessary*/
	153	AM_RANGE(0x3800,0x3807) AM_READWRITE(hector_keyboard_r, hector_keyboard_w)  /* Keyboard*/
154	154
155	155	/* Main ROM page*/
156	156	AM_RANGE(0x0000,0x3fff) AM_ROMBANK("bank2")
r14963	r14964
166	166	static ADDRESS_MAP_START( hec2hrp_io , AS_IO, 8, hec2hrp_state )
167	167	ADDRESS_MAP_UNMAP_HIGH
168	168	ADDRESS_MAP_GLOBAL_MASK(0xff)
169		AM_RANGE(0x000,0x0ff) AM_READWRITE_LEGACY(hector_io_8255_r, hector_io_8255_w )
	169	AM_RANGE(0x000,0x0ff) AM_READWRITE(hector_io_8255_r, hector_io_8255_w )
170	170	ADDRESS_MAP_END
171	171
172	172	static ADDRESS_MAP_START( hec2hrx_io , AS_IO, 8, hec2hrp_state )
173	173	ADDRESS_MAP_UNMAP_HIGH
174	174	ADDRESS_MAP_GLOBAL_MASK(0xff)
175		AM_RANGE(0x0f0,0x0ff) AM_READWRITE_LEGACY(hector_io_8255_r, hector_io_8255_w )
	175	AM_RANGE(0x0f0,0x0ff) AM_READWRITE(hector_io_8255_r, hector_io_8255_w )
176	176	ADDRESS_MAP_END
177	177
178	178	static ADDRESS_MAP_START( hec2mdhrx_io , AS_IO, 8, hec2hrp_state )
r14963	r14964
180	180	ADDRESS_MAP_GLOBAL_MASK(0xff)
181	181
182	182	// Minidisc commands and changing the rom page !*/
183		AM_RANGE(0x000,0x0EF) AM_READWRITE_LEGACY(hector_179x_register_r,hector_179x_register_w)/* 179x registers*/
184		AM_RANGE(0x0f0,0x0ff) AM_READWRITE_LEGACY(hector_io_8255_r, hector_io_8255_w )
	183	AM_RANGE(0x000,0x0EF) AM_READWRITE(hector_179x_register_r,hector_179x_register_w)/* 179x registers*/
	184	AM_RANGE(0x0f0,0x0ff) AM_READWRITE(hector_io_8255_r, hector_io_8255_w )
185	185	ADDRESS_MAP_END
186	186
187	187	static ADDRESS_MAP_START( hec2mx40_io , AS_IO, 8, hec2hrp_state )
188	188	ADDRESS_MAP_UNMAP_HIGH
189	189	ADDRESS_MAP_GLOBAL_MASK(0xff)
190		AM_RANGE(0x000,0x0ef) AM_WRITE_LEGACY(hector_mx40_io_port_w )
191		AM_RANGE(0x0f0,0x0f3) AM_READWRITE_LEGACY(hector_io_8255_r, hector_io_8255_w )
	190	AM_RANGE(0x000,0x0ef) AM_WRITE(hector_mx40_io_port_w )
	191	AM_RANGE(0x0f0,0x0f3) AM_READWRITE(hector_io_8255_r, hector_io_8255_w )
192	192	ADDRESS_MAP_END
193	193
194	194	static ADDRESS_MAP_START( hec2mx80_io , AS_IO, 8, hec2hrp_state )
195	195	ADDRESS_MAP_UNMAP_HIGH
196	196	ADDRESS_MAP_GLOBAL_MASK(0xff)
197		AM_RANGE(0x000,0x0ef) AM_WRITE_LEGACY(hector_mx80_io_port_w )
198		AM_RANGE(0x0f0,0x0f3) AM_READWRITE_LEGACY(hector_io_8255_r, hector_io_8255_w )
	197	AM_RANGE(0x000,0x0ef) AM_WRITE(hector_mx80_io_port_w )
	198	AM_RANGE(0x0f0,0x0f3) AM_READWRITE(hector_io_8255_r, hector_io_8255_w )
199	199
200	200
201	201	ADDRESS_MAP_END

src/mess/drivers/craft.c

r14963	r14964
69	69	emu_timer* m_timer2_timer;
70	70	UINT8 m_timer2_top;
71	71	INT32 m_timer2_increment;
	72	DECLARE_READ8_MEMBER(avr8_read);
	73	DECLARE_WRITE8_MEMBER(avr8_write);
72	74	};
73	75
74	76	void craft_state::machine_start()
r14963	r14964
200	202	*/
201	203	}
202	204
203		static READ8_HANDLER( avr8_read )
	205	READ8_MEMBER(craft_state::avr8_read)
204	206	{
205		craft_state *state = space->machine().driver_data<craft_state>();
206	207
207	208	if(offset <= Avr8::REGIDX_R31)
208	209	{
209		return state->m_regs[offset];
	210	return m_regs[offset];
210	211	}
211	212
212	213	switch( offset )
r14963	r14964
214	215	case Avr8::REGIDX_SPL:
215	216	case Avr8::REGIDX_SPH:
216	217	case Avr8::REGIDX_SREG:
217		return state->m_regs[offset];
	218	return m_regs[offset];
218	219
219	220	default:
220		verboselog(space->machine(), 0, "AVR8: Unrecognized register read: %02x\n", offset );
	221	verboselog(machine(), 0, "AVR8: Unrecognized register read: %02x\n", offset );
221	222	}
222	223
223	224	return 0;
r14963	r14964
831	832	verboselog(machine, 0, "avr8_update_ocr1: TODO: new OCR1%c = %04x\n", avr8_reg_name[reg], newval);
832	833	}
833	834
834		static WRITE8_HANDLER( avr8_write )
	835	WRITE8_MEMBER(craft_state::avr8_write)
835	836	{
836		craft_state *state = space->machine().driver_data<craft_state>();
837
	837	craft_state *state = machine().driver_data<craft_state>();
838	838	if(offset <= Avr8::REGIDX_R31)
839	839	{
840		state->m_regs[offset] = data;
	840	m_regs[offset] = data;
841	841	return;
842	842	}
843	843
844	844	switch( offset )
845	845	{
846	846	case Avr8::REGIDX_OCR1BH:
847		verboselog(space->machine(), 0, "AVR8: OCR1BH = %02x\n", data );
848		avr8_update_ocr1(space->machine(), (AVR8_OCR1B & 0x00ff) | (data << 8), AVR8_REG_B);
	847	verboselog(machine(), 0, "AVR8: OCR1BH = %02x\n", data );
	848	avr8_update_ocr1(machine(), (AVR8_OCR1B & 0x00ff) | (data << 8), AVR8_REG_B);
849	849	break;
850	850
851	851	case Avr8::REGIDX_OCR1BL:
852		verboselog(space->machine(), 0, "AVR8: OCR1BL = %02x\n", data );
853		avr8_update_ocr1(space->machine(), (AVR8_OCR1B & 0xff00) | data, AVR8_REG_B);
	852	verboselog(machine(), 0, "AVR8: OCR1BL = %02x\n", data );
	853	avr8_update_ocr1(machine(), (AVR8_OCR1B & 0xff00) | data, AVR8_REG_B);
854	854	break;
855	855
856	856	case Avr8::REGIDX_OCR1AH:
857		verboselog(space->machine(), 0, "AVR8: OCR1AH = %02x\n", data );
858		avr8_update_ocr1(space->machine(), (AVR8_OCR1A & 0x00ff) | (data << 8), AVR8_REG_A);
	857	verboselog(machine(), 0, "AVR8: OCR1AH = %02x\n", data );
	858	avr8_update_ocr1(machine(), (AVR8_OCR1A & 0x00ff) | (data << 8), AVR8_REG_A);
859	859	break;
860	860
861	861	case Avr8::REGIDX_OCR1AL:
862		verboselog(space->machine(), 0, "AVR8: OCR1AL = %02x\n", data );
863		avr8_update_ocr1(space->machine(), (AVR8_OCR1A & 0xff00) | data, AVR8_REG_A);
	862	verboselog(machine(), 0, "AVR8: OCR1AL = %02x\n", data );
	863	avr8_update_ocr1(machine(), (AVR8_OCR1A & 0xff00) | data, AVR8_REG_A);
864	864	break;
865	865
866	866	case Avr8::REGIDX_TCCR1B:
867		verboselog(space->machine(), 0, "AVR8: TCCR1B = %02x\n", data );
868		avr8_changed_tccr1b(space->machine(), data);
	867	verboselog(machine(), 0, "AVR8: TCCR1B = %02x\n", data );
	868	avr8_changed_tccr1b(machine(), data);
869	869	break;
870	870
871	871	case Avr8::REGIDX_TCCR1A:
872		verboselog(space->machine(), 0, "AVR8: TCCR1A = %02x\n", data );
873		avr8_changed_tccr1a(space->machine(), data);
	872	verboselog(machine(), 0, "AVR8: TCCR1A = %02x\n", data );
	873	avr8_changed_tccr1a(machine(), data);
874	874	break;
875	875
876	876	case Avr8::REGIDX_TIMSK1:
877		verboselog(space->machine(), 0, "AVR8: TIMSK1 = %02x\n", data );
878		avr8_change_timsk1(space->machine(), data);
	877	verboselog(machine(), 0, "AVR8: TIMSK1 = %02x\n", data );
	878	avr8_change_timsk1(machine(), data);
879	879	break;
880	880
881	881	case Avr8::REGIDX_TCCR2B:
882		verboselog(space->machine(), 0, "AVR8: TCCR2B = %02x\n", data );
883		avr8_changed_tccr2b(space->machine(), data);
	882	verboselog(machine(), 0, "AVR8: TCCR2B = %02x\n", data );
	883	avr8_changed_tccr2b(machine(), data);
884	884	break;
885	885
886	886	case Avr8::REGIDX_TCCR2A:
887		verboselog(space->machine(), 0, "AVR8: TCCR2A = %02x\n", data );
888		avr8_changed_tccr2a(space->machine(), data);
	887	verboselog(machine(), 0, "AVR8: TCCR2A = %02x\n", data );
	888	avr8_changed_tccr2a(machine(), data);
889	889	break;
890	890
891	891	case Avr8::REGIDX_SPL:
892	892	case Avr8::REGIDX_SPH:
893	893	case Avr8::REGIDX_SREG:
894		state->m_regs[offset] = data;
	894	m_regs[offset] = data;
895	895	break;
896	896
897	897	case Avr8::REGIDX_SPSR:
898		avr8_change_spsr(space->machine(), data);
	898	avr8_change_spsr(machine(), data);
899	899	break;
900	900
901	901	case Avr8::REGIDX_SPCR:
902		avr8_change_spcr(space->machine(), data);
	902	avr8_change_spcr(machine(), data);
903	903	break;
904	904
905	905	case Avr8::REGIDX_DDRD:
906		avr8_change_ddr(space->machine(), AVR8_REG_D, data);
	906	avr8_change_ddr(machine(), AVR8_REG_D, data);
907	907	break;
908	908
909	909	case Avr8::REGIDX_DDRC:
910		avr8_change_ddr(space->machine(), AVR8_REG_C, data);
	910	avr8_change_ddr(machine(), AVR8_REG_C, data);
911	911	break;
912	912
913	913	case Avr8::REGIDX_PORTB:
914		avr8_change_port(space->machine(), AVR8_REG_B, data);
	914	avr8_change_port(machine(), AVR8_REG_B, data);
915	915	break;
916	916
917	917	case Avr8::REGIDX_DDRB:
918		avr8_change_ddr(space->machine(), AVR8_REG_B, data);
	918	avr8_change_ddr(machine(), AVR8_REG_B, data);
919	919	break;
920	920
921	921	default:
922		verboselog(space->machine(), 0, "AVR8: Unrecognized register write: %02x = %02x\n", offset, data );
	922	verboselog(machine(), 0, "AVR8: Unrecognized register write: %02x = %02x\n", offset, data );
923	923	}
924	924	}
925	925
r14963	r14964
932	932	ADDRESS_MAP_END
933	933
934	934	static ADDRESS_MAP_START( craft_io_map, AS_IO, 8, craft_state )
935		AM_RANGE(0x0000, 0x00ff) AM_READWRITE_LEGACY(avr8_read, avr8_write)
	935	AM_RANGE(0x0000, 0x00ff) AM_READWRITE(avr8_read, avr8_write)
936	936	AM_RANGE(0x0100, 0x04ff) AM_RAM
937	937	ADDRESS_MAP_END
938	938

src/mess/drivers/mtx.c

r14963	r14964
56	56
57	57	static ADDRESS_MAP_START( mtx_io, AS_IO, 8, mtx_state )
58	58	ADDRESS_MAP_GLOBAL_MASK(0xff)
59		AM_RANGE(0x00, 0x00) AM_DEVREAD_LEGACY(CENTRONICS_TAG, mtx_strobe_r) AM_WRITE_LEGACY(mtx_bankswitch_w)
	59	AM_RANGE(0x00, 0x00) AM_DEVREAD_LEGACY(CENTRONICS_TAG, mtx_strobe_r) AM_WRITE(mtx_bankswitch_w)
60	60	AM_RANGE(0x01, 0x01) AM_DEVREADWRITE("tms9929a", tms9929a_device, vram_read, vram_write)
61	61	AM_RANGE(0x02, 0x02) AM_DEVREADWRITE("tms9929a", tms9929a_device, register_read, register_write)
62	62	AM_RANGE(0x03, 0x03) AM_DEVREAD_LEGACY(SN76489A_TAG, mtx_sound_strobe_r) AM_DEVWRITE_LEGACY(CASSETTE_TAG, mtx_cst_w)
63	63	AM_RANGE(0x04, 0x04) AM_DEVREAD_LEGACY(CENTRONICS_TAG, mtx_prt_r)
64	64	AM_RANGE(0x04, 0x04) AM_DEVWRITE(CENTRONICS_TAG, centronics_device, write)
65		AM_RANGE(0x05, 0x05) AM_READWRITE_LEGACY(mtx_key_lo_r, mtx_sense_w)
66		AM_RANGE(0x06, 0x06) AM_READWRITE_LEGACY(mtx_key_hi_r, mtx_sound_latch_w)
	65	AM_RANGE(0x05, 0x05) AM_READWRITE(mtx_key_lo_r, mtx_sense_w)
	66	AM_RANGE(0x06, 0x06) AM_READWRITE(mtx_key_hi_r, mtx_sound_latch_w)
67	67	//  AM_RANGE(0x07, 0x07) PIO
68	68	AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE_LEGACY(Z80CTC_TAG, z80ctc_r, z80ctc_w)
69		AM_RANGE(0x30, 0x31) AM_WRITE_LEGACY(hrx_address_w)
70		AM_RANGE(0x32, 0x32) AM_READWRITE_LEGACY(hrx_data_r, hrx_data_w)
71		AM_RANGE(0x33, 0x33) AM_READWRITE_LEGACY(hrx_attr_r, hrx_attr_w)
	69	AM_RANGE(0x30, 0x31) AM_WRITE(hrx_address_w)
	70	AM_RANGE(0x32, 0x32) AM_READWRITE(hrx_data_r, hrx_data_w)
	71	AM_RANGE(0x33, 0x33) AM_READWRITE(hrx_attr_r, hrx_attr_w)
72	72	//  AM_RANGE(0x38, 0x38) AM_DEVWRITE_LEGACY(MC6845_TAG, mc6845_address_w)
73	73	//  AM_RANGE(0x39, 0x39) AM_DEVWRITE_LEGACY(MC6845_TAG, mc6845_register_r, mc6845_register_w)
74	74	/*  AM_RANGE(0x40, 0x43) AM_DEVREADWRITE_LEGACY(FD1791_TAG, wd17xx_r, wd17xx_w)

src/mess/drivers/elwro800.c

r14963	r14964
46	46	UINT8 m_df_on_databus;
47	47
48	48	DECLARE_DIRECT_UPDATE_MEMBER(elwro800_direct_handler);
	49	DECLARE_WRITE8_MEMBER(elwro800jr_fdc_control_w);
	50	DECLARE_READ8_MEMBER(elwro800jr_io_r);
	51	DECLARE_WRITE8_MEMBER(elwro800jr_io_w);
49	52	};
50	53
51	54
r14963	r14964
81	84	{FLOPPY_0,FLOPPY_1, NULL, NULL}
82	85	};
83	86
84		static WRITE8_HANDLER(elwro800jr_fdc_control_w)
	87	WRITE8_MEMBER(elwro800_state::elwro800jr_fdc_control_w)
85	88	{
86		device_t *fdc = space->machine().device("upd765");
	89	device_t *fdc = machine().device("upd765");
87	90
88		floppy_mon_w(floppy_get_device(space->machine(), 0), !BIT(data, 0));
89		floppy_mon_w(floppy_get_device(space->machine(), 1), !BIT(data, 1));
90		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), 1,1);
91		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), 1,1);
	91	floppy_mon_w(floppy_get_device(machine(), 0), !BIT(data, 0));
	92	floppy_mon_w(floppy_get_device(machine(), 1), !BIT(data, 1));
	93	floppy_drive_set_ready_state(floppy_get_device(machine(), 0), 1,1);
	94	floppy_drive_set_ready_state(floppy_get_device(machine(), 1), 1,1);
92	95
93	96	upd765_tc_w(fdc, data & 0x04);
94	97
r14963	r14964
220	223	*  0x??FE, 0x??7F, 0x??7B (read): keyboard reading
221	224	*************************************/
222	225
223		static READ8_HANDLER(elwro800jr_io_r)
	226	READ8_MEMBER(elwro800_state::elwro800jr_io_r)
224	227	{
225		UINT8 *prom = space->machine().region("proms")->base();
	228	UINT8 *prom = machine().region("proms")->base();
226	229	UINT8 cs = prom[offset & 0x1ff];
227		elwro800_state *state = space->machine().driver_data<elwro800_state>();
228	230
229	231	if (!BIT(cs,0))
230	232	{
r14963	r14964
234	236	int i;
235	237	char port_name[6] = "LINE0";
236	238
237		if ( !state->m_NR )
	239	if ( !m_NR )
238	240	{
239	241	for (i = 0; i < 9; mask >>= 1, i++)
240	242	{
r14963	r14964
248	250	{
249	251	port_name[4] = '0' + (7 - i);
250	252	}
251		data &= (input_port_read(space->machine(), port_name));
	253	data &= (input_port_read(machine(), port_name));
252	254	}
253	255	}
254	256
255	257	if ((offset & 0xff) == 0xfb)
256	258	{
257		data &= input_port_read(space->machine(), "LINE9");
	259	data &= input_port_read(machine(), "LINE9");
258	260	}
259	261
260	262	/* cassette input from wav */
261		if ((space->machine().device<cassette_image_device>(CASSETTE_TAG))->input() > 0.0038 )
	263	if ((machine().device<cassette_image_device>(CASSETTE_TAG))->input() > 0.0038 )
262	264	{
263	265	data &= ~0x40;
264	266	}
265	267	}
266	268	else
267	269	{
268		data = input_port_read(space->machine(), "NETWORK ID");
	270	data = input_port_read(machine(), "NETWORK ID");
269	271	}
270	272
271	273	return data;
r14963	r14964
277	279	else if (!BIT(cs,2))
278	280	{
279	281	// CS55
280		i8255_device *ppi = space->machine().device<i8255_device>("ppi8255");
281		return ppi->read(*space, (offset & 0x03) ^ 0x03);
	282	i8255_device *ppi = machine().device<i8255_device>("ppi8255");
	283	return ppi->read(space, (offset & 0x03) ^ 0x03);
282	284	}
283	285	else if (!BIT(cs,3))
284	286	{
285	287	// CSFDC
286		device_t *fdc = space->machine().device("upd765");
	288	device_t *fdc = machine().device("upd765");
287	289	if (offset & 1)
288	290	{
289	291	return upd765_data_r(fdc,0);
r14963	r14964
296	298	else if (!BIT(cs,4))
297	299	{
298	300	// CS51
299		i8251_device *usart = space->machine().device<i8251_device>("i8251");
	301	i8251_device *usart = machine().device<i8251_device>("i8251");
300	302	if (offset & 1)
301	303	{
302		return usart->status_r(*space, 0);
	304	return usart->status_r(space, 0);
303	305	}
304	306	else
305	307	{
306		return usart->data_r(*space, 0);
	308	return usart->data_r(space, 0);
307	309	}
308	310	}
309	311	else if (!BIT(cs,5))
r14963	r14964
317	319	return 0x00;
318	320	}
319	321
320		static WRITE8_HANDLER(elwro800jr_io_w)
	322	WRITE8_MEMBER(elwro800_state::elwro800jr_io_w)
321	323	{
322		UINT8 *prom = space->machine().region("proms")->base();
	324	UINT8 *prom = machine().region("proms")->base();
323	325	UINT8 cs = prom[offset & 0x1ff];
324	326
325	327	if (!BIT(cs,0))
r14963	r14964
330	332	else if (!BIT(cs,1))
331	333	{
332	334	// CF7
333		elwro800jr_mmu_w(space->machine(), data);
	335	elwro800jr_mmu_w(machine(), data);
334	336	}
335	337	else if (!BIT(cs,2))
336	338	{
337	339	// CS55
338		i8255_device *ppi = space->machine().device<i8255_device>("ppi8255");
339		ppi->write(*space, (offset & 0x03) ^ 0x03, data);
	340	i8255_device *ppi = machine().device<i8255_device>("ppi8255");
	341	ppi->write(space, (offset & 0x03) ^ 0x03, data);
340	342	}
341	343	else if (!BIT(cs,3))
342	344	{
343	345	// CSFDC
344		device_t *fdc = space->machine().device("upd765");
	346	device_t *fdc = machine().device("upd765");
345	347	if (offset & 1)
346	348	{
347	349	upd765_data_w(fdc, 0, data);
r14963	r14964
350	352	else if (!BIT(cs,4))
351	353	{
352	354	// CS51
353		i8251_device *usart = space->machine().device<i8251_device>("i8251");
	355	i8251_device *usart = machine().device<i8251_device>("i8251");
354	356	if (offset & 1)
355	357	{
356		usart->control_w(*space, 0, data);
	358	usart->control_w(space, 0, data);
357	359	}
358	360	else
359	361	{
360		usart->data_w(*space, 0, data);
	362	usart->data_w(space, 0, data);
361	363	}
362	364	}
363	365	else if (!BIT(cs,5))
r14963	r14964
384	386	ADDRESS_MAP_END
385	387
386	388	static ADDRESS_MAP_START(elwro800_io, AS_IO, 8, elwro800_state )
387		AM_RANGE(0x0000, 0xffff) AM_READWRITE_LEGACY(elwro800jr_io_r, elwro800jr_io_w)
	389	AM_RANGE(0x0000, 0xffff) AM_READWRITE(elwro800jr_io_r, elwro800jr_io_w)
388	390	ADDRESS_MAP_END
389	391
390	392	/*************************************

src/mess/drivers/mikro80.c

r14963	r14964
29	29
30	30	static ADDRESS_MAP_START( mikro80_io , AS_IO, 8, mikro80_state )
31	31	ADDRESS_MAP_UNMAP_HIGH
32		AM_RANGE( 0x01, 0x01) AM_READWRITE_LEGACY(mikro80_tape_r, mikro80_tape_w )
33		AM_RANGE( 0x04, 0x07) AM_READWRITE_LEGACY(mikro80_keyboard_r, mikro80_keyboard_w )
	32	AM_RANGE( 0x01, 0x01) AM_READWRITE(mikro80_tape_r, mikro80_tape_w )
	33	AM_RANGE( 0x04, 0x07) AM_READWRITE(mikro80_keyboard_r, mikro80_keyboard_w )
34	34	ADDRESS_MAP_END
35	35
36	36	static WRITE8_DEVICE_HANDLER( radio99_dac_w )   { dac_data_w(device, data); }
37	37
38	38	static ADDRESS_MAP_START( radio99_io , AS_IO, 8, mikro80_state )
39	39	ADDRESS_MAP_UNMAP_HIGH
40		AM_RANGE( 0x01, 0x01) AM_READWRITE_LEGACY(mikro80_tape_r, mikro80_tape_w )
	40	AM_RANGE( 0x01, 0x01) AM_READWRITE(mikro80_tape_r, mikro80_tape_w )
41	41	AM_RANGE( 0x04, 0x04) AM_DEVWRITE_LEGACY("dac", radio99_dac_w )
42		AM_RANGE( 0x05, 0x05) AM_READWRITE_LEGACY(mikro80_8255_portc_r, mikro80_8255_portc_w )
43		AM_RANGE( 0x06, 0x06) AM_READ_LEGACY(mikro80_8255_portb_r)
44		AM_RANGE( 0x07, 0x07) AM_WRITE_LEGACY(mikro80_8255_porta_w)
	42	AM_RANGE( 0x05, 0x05) AM_READWRITE(mikro80_8255_portc_r, mikro80_8255_portc_w )
	43	AM_RANGE( 0x06, 0x06) AM_READ(mikro80_8255_portb_r)
	44	AM_RANGE( 0x07, 0x07) AM_WRITE(mikro80_8255_porta_w)
45	45	ADDRESS_MAP_END
46	46
47	47	/* Input ports */

src/mess/drivers/rmnimbus.c

r14963	r14964
67	67	AY8910_DEFAULT_LOADS,
68	68	DEVCB_NULL,                       /* portA read */
69	69	DEVCB_NULL,                /* portB read */
70		DEVCB_MEMORY_HANDLER(MAINCPU_TAG, PROGRAM, nimbus_sound_ay8910_porta_w),   /* portA write */
71		DEVCB_MEMORY_HANDLER(MAINCPU_TAG, PROGRAM, nimbus_sound_ay8910_portb_w)    /* portB write */
	70	DEVCB_DRIVER_MEMBER(rmnimbus_state, nimbus_sound_ay8910_porta_w),   /* portA write */
	71	DEVCB_DRIVER_MEMBER(rmnimbus_state, nimbus_sound_ay8910_portb_w)    /* portB write */
72	72	};
73	73
74	74	static const msm5205_interface msm5205_config =
r14963	r14964
115	115	ADDRESS_MAP_END
116	116
117	117	static ADDRESS_MAP_START(nimbus_io, AS_IO, 16, rmnimbus_state )
118		AM_RANGE( 0x0000, 0x0031) AM_READWRITE_LEGACY(nimbus_video_io_r, nimbus_video_io_w)
119		AM_RANGE( 0x0032, 0x007f) AM_READWRITE_LEGACY(nimbus_io_r, nimbus_io_w)
120		AM_RANGE( 0x0080, 0x0081) AM_READWRITE8_LEGACY(nimbus_mcu_r, nimbus_mcu_w, 0x00FF)
121		AM_RANGE( 0x0092, 0x0093) AM_READWRITE8_LEGACY(nimbus_iou_r, nimbus_iou_w, 0x00FF)
122		AM_RANGE( 0x00A4, 0x00A5) AM_READWRITE8_LEGACY(nimbus_mouse_js_r, nimbus_mouse_js_w, 0x00FF)
123		AM_RANGE( 0X00c0, 0X00cf) AM_READWRITE8_LEGACY(nimbus_pc8031_r, nimbus_pc8031_w, 0x00FF)
124		AM_RANGE( 0X00e0, 0X00ef) AM_READWRITE8_LEGACY(nimbus_sound_ay8910_r, nimbus_sound_ay8910_w, 0x00FF)
	118	AM_RANGE( 0x0000, 0x0031) AM_READWRITE(nimbus_video_io_r, nimbus_video_io_w)
	119	AM_RANGE( 0x0032, 0x007f) AM_READWRITE(nimbus_io_r, nimbus_io_w)
	120	AM_RANGE( 0x0080, 0x0081) AM_READWRITE8(nimbus_mcu_r, nimbus_mcu_w, 0x00FF)
	121	AM_RANGE( 0x0092, 0x0093) AM_READWRITE8(nimbus_iou_r, nimbus_iou_w, 0x00FF)
	122	AM_RANGE( 0x00A4, 0x00A5) AM_READWRITE8(nimbus_mouse_js_r, nimbus_mouse_js_w, 0x00FF)
	123	AM_RANGE( 0X00c0, 0X00cf) AM_READWRITE8(nimbus_pc8031_r, nimbus_pc8031_w, 0x00FF)
	124	AM_RANGE( 0X00e0, 0X00ef) AM_READWRITE8(nimbus_sound_ay8910_r, nimbus_sound_ay8910_w, 0x00FF)
125	125	AM_RANGE( 0x00f0, 0x00f7) AM_DEVREADWRITE8_LEGACY(Z80SIO_TAG, z80sio_cd_ba_r, z80sio_cd_ba_w, 0x00ff)
126		AM_RANGE( 0x0400, 0x041f) AM_READWRITE8_LEGACY(nimbus_disk_r, nimbus_disk_w, 0x00FF)
	126	AM_RANGE( 0x0400, 0x041f) AM_READWRITE8(nimbus_disk_r, nimbus_disk_w, 0x00FF)
127	127	AM_RANGE( 0x0480, 0x049f) AM_DEVREADWRITE8(VIA_TAG, via6522_device, read, write, 0x00FF)
128		AM_RANGE( 0xff00, 0xffff) AM_READWRITE_LEGACY(nimbus_i186_internal_port_r, nimbus_i186_internal_port_w)/* CPU 80186         */
	128	AM_RANGE( 0xff00, 0xffff) AM_READWRITE(nimbus_i186_internal_port_r, nimbus_i186_internal_port_w)/* CPU 80186         */
129	129	ADDRESS_MAP_END
130	130
131	131	static INPUT_PORTS_START( nimbus )
r14963	r14964
279	279
280	280	static ADDRESS_MAP_START( nimbus_iocpu_io , AS_IO, 8, rmnimbus_state )
281	281	ADDRESS_MAP_UNMAP_HIGH
282		AM_RANGE(0x00000, 0x000FF) AM_READWRITE_LEGACY(nimbus_pc8031_iou_r, nimbus_pc8031_iou_w)
	282	AM_RANGE(0x00000, 0x000FF) AM_READWRITE(nimbus_pc8031_iou_r, nimbus_pc8031_iou_w)
283	283	AM_RANGE(0x00010, 0x07fff) AM_RAM
284		AM_RANGE(0x20000, 0x20004) AM_READWRITE_LEGACY(nimbus_pc8031_port_r, nimbus_pc8031_port_w)
	284	AM_RANGE(0x20000, 0x20004) AM_READWRITE(nimbus_pc8031_port_r, nimbus_pc8031_port_w)
285	285	ADDRESS_MAP_END
286	286
287	287

src/mess/drivers/pp01.c

r14963	r14964
36	36	static ADDRESS_MAP_START( pp01_io, AS_IO, 8, pp01_state )
37	37	AM_RANGE(0xc0, 0xc3) AM_DEVREADWRITE("ppi8255", i8255_device, read, write)
38	38	//AM_RANGE(0xc4, 0xc7) AM_DEVREADWRITE("ppi8255", i8255_device, read, write)
39		AM_RANGE(0xcc, 0xcf) AM_WRITE_LEGACY(pp01_video_write_mode_w)
	39	AM_RANGE(0xcc, 0xcf) AM_WRITE(pp01_video_write_mode_w)
40	40	AM_RANGE(0xd0, 0xd3) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r, pit8253_w)
41		AM_RANGE(0xe0, 0xef) AM_READWRITE_LEGACY(pp01_mem_block_r, pp01_mem_block_w)
42		AM_RANGE(0xf0, 0xff) AM_READWRITE_LEGACY(pp01_mem_block_r, pp01_mem_block_w)
	41	AM_RANGE(0xe0, 0xef) AM_READWRITE(pp01_mem_block_r, pp01_mem_block_w)
	42	AM_RANGE(0xf0, 0xff) AM_READWRITE(pp01_mem_block_r, pp01_mem_block_w)
43	43	ADDRESS_MAP_END
44	44
45	45	/* Input ports */

src/mess/drivers/svision.c

r14963	r14964
22	22	#define XSIZE (state->m_reg[0]&~3)
23	23	#define XPOS state->m_reg[2]
24	24	#define YPOS state->m_reg[3]
25		#define BANK state->m_reg[0x26]
	25	#define BANK m_reg[0x26]
26	26
27	27	static TIMER_CALLBACK(svision_pet_timer)
28	28	{
r14963	r14964
59	59	void svision_irq(running_machine &machine)
60	60	{
61	61	svision_state *state = machine.driver_data<svision_state>();
62		int irq = state->m_svision.timer_shot && (BANK & 2);
63		irq = irq || (*state->m_dma_finished && (BANK & 4));
	62	int irq = state->m_svision.timer_shot && (state->BANK & 2);
	63	irq = irq || (*state->m_dma_finished && (state->BANK & 4));
64	64
65	65	cputag_set_input_line(machine, "maincpu", M6502_IRQ_LINE, irq ? ASSERT_LINE : CLEAR_LINE);
66	66	}
r14963	r14964
73	73	svision_irq( machine );
74	74	}
75	75
76		static READ8_HANDLER(svision_r)
	76	READ8_MEMBER(svision_state::svision_r)
77	77	{
78		svision_state *state = space->machine().driver_data<svision_state>();
79		int data = state->m_reg[offset];
	78	int data = m_reg[offset];
80	79	switch (offset)
81	80	{
82	81	case 0x20:
83		data = input_port_read(space->machine(), "JOY");
	82	data = input_port_read(machine(), "JOY");
84	83	break;
85	84	case 0x21:
86	85	data &= ~0xf;
87		data |= state->m_reg[0x22] & 0xf;
88		if (state->m_pet.on)
	86	data |= m_reg[0x22] & 0xf;
	87	if (m_pet.on)
89	88	{
90		if (!state->m_pet.clock)
	89	if (!m_pet.clock)
91	90	data &= ~4;
92		if (!state->m_pet.data)
	91	if (!m_pet.data)
93	92	data &= ~8;
94	93	}
95	94	break;
96	95	case 0x27:
97	96	data &= ~3;
98		if (state->m_svision.timer_shot)
	97	if (m_svision.timer_shot)
99	98	data|=1;
100		if (*state->m_dma_finished)
	99	if (*m_dma_finished)
101	100	data|=2;
102	101	break;
103	102	case 0x24:
104		state->m_svision.timer_shot = FALSE;
105		svision_irq(space->machine());
	103	m_svision.timer_shot = FALSE;
	104	svision_irq(machine());
106	105	break;
107	106	case 0x25:
108		*state->m_dma_finished = FALSE;
109		svision_irq(space->machine());
	107	*m_dma_finished = FALSE;
	108	svision_irq(machine());
110	109	break;
111	110	default:
112		logerror("%.6f svision read %04x %02x\n", space->machine().time().as_double(),offset,data);
	111	logerror("%.6f svision read %04x %02x\n", machine().time().as_double(),offset,data);
113	112	break;
114	113	}
115	114
116	115	return data;
117	116	}
118	117
119		static WRITE8_HANDLER(svision_w)
	118	WRITE8_MEMBER(svision_state::svision_w)
120	119	{
121		svision_state *state = space->machine().driver_data<svision_state>();
122	120	int value;
123	121	int delay;
124	122
125		state->m_reg[offset] = data;
	123	m_reg[offset] = data;
126	124
127	125	switch (offset)
128	126	{
r14963	r14964
130	128	case 3:
131	129	break;
132	130	case 0x26: /* bits 5,6 memory management for a000? */
133		logerror("%.6f svision write %04x %02x\n", space->machine().time().as_double(),offset,data);
134		memory_set_bankptr(space->machine(), "bank1", space->machine().region("user1")->base() + ((state->m_reg[0x26] & 0xe0) << 9));
135		svision_irq(space->machine());
	131	logerror("%.6f svision write %04x %02x\n", machine().time().as_double(),offset,data);
	132	memory_set_bankptr(machine(), "bank1", machine().region("user1")->base() + ((m_reg[0x26] & 0xe0) << 9));
	133	svision_irq(machine());
136	134	break;
137	135	case 0x23: /* delta hero irq routine write */
138	136	value = data;
r14963	r14964
142	140	delay = 16384;
143	141	else
144	142	delay = 256;
145		state->m_svision.timer1->enable(TRUE);
146		state->m_svision.timer1->reset(space->machine().device<cpu_device>("maincpu")->cycles_to_attotime(value * delay));
	143	m_svision.timer1->enable(TRUE);
	144	m_svision.timer1->reset(machine().device<cpu_device>("maincpu")->cycles_to_attotime(value * delay));
147	145	break;
148	146	case 0x10: case 0x11: case 0x12: case 0x13:
149		svision_soundport_w(state->m_sound, 0, offset & 3, data);
	147	svision_soundport_w(m_sound, 0, offset & 3, data);
150	148	break;
151	149	case 0x14: case 0x15: case 0x16: case 0x17:
152		svision_soundport_w(state->m_sound, 1, offset & 3, data);
	150	svision_soundport_w(m_sound, 1, offset & 3, data);
153	151	break;
154	152	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c:
155		svision_sounddma_w(state->m_sound, offset - 0x18, data);
	153	svision_sounddma_w(m_sound, offset - 0x18, data);
156	154	break;
157	155	case 0x28: case 0x29: case 0x2a:
158		svision_noise_w(state->m_sound, offset - 0x28, data);
	156	svision_noise_w(m_sound, offset - 0x28, data);
159	157	break;
160	158	default:
161		logerror("%.6f svision write %04x %02x\n", space->machine().time().as_double(), offset, data);
	159	logerror("%.6f svision write %04x %02x\n", machine().time().as_double(), offset, data);
162	160	break;
163	161	}
164	162	}
165	163
166		static READ8_HANDLER(tvlink_r)
	164	READ8_MEMBER(svision_state::tvlink_r)
167	165	{
168	166	switch(offset)
169	167	{
r14963	r14964
180	178	}
181	179	}
182	180
183		static WRITE8_HANDLER(tvlink_w)
	181	WRITE8_MEMBER(svision_state::tvlink_w)
184	182	{
185		svision_state *state = space->machine().driver_data<svision_state>();
186	183	switch (offset)
187	184	{
188	185	case 0x0e:
189		state->m_reg[offset] = data;
190		state->m_tvlink.palette_on = data & 1;
191		if (state->m_tvlink.palette_on)
	186	m_reg[offset] = data;
	187	m_tvlink.palette_on = data & 1;
	188	if (m_tvlink.palette_on)
192	189	{
193	190	// hack, normally initialising with palette from ram
194		state->m_tvlink.palette[0] = MAKE12_RGB32(163/16,172/16,115/16); // these are the tron colors messured from screenshot
195		state->m_tvlink.palette[1] = MAKE12_RGB32(163/16,155/16,153/16);
196		state->m_tvlink.palette[2] = MAKE12_RGB32(77/16,125/16,73/16);
197		state->m_tvlink.palette[3] = MAKE12_RGB32(59/16,24/16,20/16);
	191	m_tvlink.palette[0] = MAKE12_RGB32(163/16,172/16,115/16); // these are the tron colors messured from screenshot
	192	m_tvlink.palette[1] = MAKE12_RGB32(163/16,155/16,153/16);
	193	m_tvlink.palette[2] = MAKE12_RGB32(77/16,125/16,73/16);
	194	m_tvlink.palette[3] = MAKE12_RGB32(59/16,24/16,20/16);
198	195	}
199	196	else
200	197	{
201	198	// cleaner to use colors from compile time palette, or compose from "fixed" palette values
202		state->m_tvlink.palette[0]=MAKE12_RGB32(0,0,0);
203		state->m_tvlink.palette[1]=MAKE12_RGB32(5*16/256,18*16/256,9*16/256);
204		state->m_tvlink.palette[2]=MAKE12_RGB32(48*16/256,76*16/256,100*16/256);
205		state->m_tvlink.palette[3]=MAKE12_RGB32(190*16/256,190*16/256,190*16/256);
	199	m_tvlink.palette[0]=MAKE12_RGB32(0,0,0);
	200	m_tvlink.palette[1]=MAKE12_RGB32(5*16/256,18*16/256,9*16/256);
	201	m_tvlink.palette[2]=MAKE12_RGB32(48*16/256,76*16/256,100*16/256);
	202	m_tvlink.palette[3]=MAKE12_RGB32(190*16/256,190*16/256,190*16/256);
206	203	}
207	204	break;
208	205	default:
r14963	r14964
213	210	if (offset == 0x803 && data == 0x07)
214	211	{
215	212	/* tron hack */
216		state->m_reg[0x0804]=0x00;
217		state->m_reg[0x0805]=0x01;
218		state->m_reg[0x0806]=0x00;
219		state->m_reg[0x0807]=0x00;
	213	m_reg[0x0804]=0x00;
	214	m_reg[0x0805]=0x01;
	215	m_reg[0x0806]=0x00;
	216	m_reg[0x0807]=0x00;
220	217	}
221		c = state->m_reg[0x800] | (state->m_reg[0x804] << 8);
222		state->m_tvlink.palette[0] = MAKE9_RGB32( (c>>0)&7, (c>>3)&7, (c>>6)&7);
223		c = state->m_reg[0x801] | (state->m_reg[0x805] << 8);
224		state->m_tvlink.palette[1] = MAKE9_RGB32( (c>>0)&7, (c>>3)&7, (c>>6)&7);
225		c = state->m_reg[0x802] | (state->m_reg[0x806]<<8);
226		state->m_tvlink.palette[2]=MAKE9_RGB32( (c>>0)&7, (c>>3)&7, (c>>6)&7);
227		c = state->m_reg[0x803] | (state->m_reg[0x807]<<8);
228		state->m_tvlink.palette[3]=MAKE9_RGB32( (c>>0)&7, (c>>3)&7, (c>>6)&7);
	218	c = m_reg[0x800] | (m_reg[0x804] << 8);
	219	m_tvlink.palette[0] = MAKE9_RGB32( (c>>0)&7, (c>>3)&7, (c>>6)&7);
	220	c = m_reg[0x801] | (m_reg[0x805] << 8);
	221	m_tvlink.palette[1] = MAKE9_RGB32( (c>>0)&7, (c>>3)&7, (c>>6)&7);
	222	c = m_reg[0x802] | (m_reg[0x806]<<8);
	223	m_tvlink.palette[2]=MAKE9_RGB32( (c>>0)&7, (c>>3)&7, (c>>6)&7);
	224	c = m_reg[0x803] | (m_reg[0x807]<<8);
	225	m_tvlink.palette[3]=MAKE9_RGB32( (c>>0)&7, (c>>3)&7, (c>>6)&7);
229	226	/* writes to palette effect video color immediately */
230	227	/* some writes modify other registers, */
231	228	/* encoding therefor not known (rgb8 or rgb9) */
r14963	r14964
235	232
236	233	static ADDRESS_MAP_START( svision_mem , AS_PROGRAM, 8, svision_state )
237	234	AM_RANGE( 0x0000, 0x1fff) AM_RAM
238		AM_RANGE( 0x2000, 0x3fff) AM_READWRITE_LEGACY(svision_r, svision_w) AM_SHARE("reg")
	235	AM_RANGE( 0x2000, 0x3fff) AM_READWRITE(svision_r, svision_w) AM_SHARE("reg")
239	236	AM_RANGE( 0x4000, 0x5fff) AM_RAM AM_SHARE("videoram")
240	237	AM_RANGE( 0x6000, 0x7fff) AM_NOP
241	238	AM_RANGE( 0x8000, 0xbfff) AM_ROMBANK("bank1")
r14963	r14964
244	241
245	242	static ADDRESS_MAP_START( tvlink_mem , AS_PROGRAM, 8, svision_state )
246	243	AM_RANGE( 0x0000, 0x1fff) AM_RAM
247		AM_RANGE( 0x2000, 0x3fff) AM_READWRITE_LEGACY(tvlink_r, tvlink_w) AM_SHARE("reg")
	244	AM_RANGE( 0x2000, 0x3fff) AM_READWRITE(tvlink_r, tvlink_w) AM_SHARE("reg")
248	245	AM_RANGE( 0x4000, 0x5fff) AM_RAM AM_SHARE("videoram")
249	246	AM_RANGE( 0x6000, 0x7fff) AM_NOP
250	247	AM_RANGE( 0x8000, 0xbfff) AM_ROMBANK("bank1")
r14963	r14964
359	356	int x, y, i, j=XPOS/4+YPOS*0x30;
360	357	UINT8 *videoram = state->m_videoram;
361	358
362		if (BANK&8)
	359	if (state->BANK&8)
363	360	{
364	361	for (y=0; y<160; y++)
365	362	{
r14963	r14964
391	388	int x, y, i, j = XPOS/4+YPOS*0x30;
392	389	UINT8 *videoram = state->m_videoram;
393	390
394		if (BANK & 8)
	391	if (state->BANK & 8)
395	392	{
396	393	for (y = 0; y < 160; y++)
397	394	{
r14963	r14964
420	417	static INTERRUPT_GEN( svision_frame_int )
421	418	{
422	419	svision_state *state = device->machine().driver_data<svision_state>();
423		if (BANK&1)
	420	if (state->BANK&1)
424	421	device_set_input_line(device, INPUT_LINE_NMI, PULSE_LINE);
425	422
426	423	svision_sound_decrement(state->m_sound);

src/mess/drivers/busicom.c

r14963	r14964
19	19	}
20	20	return 0;
21	21	}
22		static READ8_HANDLER(keyboard_r)
	22	READ8_MEMBER(busicom_state::keyboard_r)
23	23	{
24		busicom_state *state = space->machine().driver_data<busicom_state>();
25	24	static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7", "LINE8" , "LINE9"};
26		return input_port_read(space->machine(),keynames[get_bit_selected(state->m_keyboard_shifter & 0x3ff,10)]);
	25	return input_port_read(machine(),keynames[get_bit_selected(m_keyboard_shifter & 0x3ff,10)]);
27	26	}
28	27
29		static READ8_HANDLER(printer_r)
	28	READ8_MEMBER(busicom_state::printer_r)
30	29	{
31		busicom_state *state = space->machine().driver_data<busicom_state>();
32	30	UINT8 retVal = 0;
33		if (state->m_drum_index==0) retVal |= 1;
34		retVal |= input_port_read(space->machine(),"PAPERADV") & 1 ? 8 : 0;
	31	if (m_drum_index==0) retVal |= 1;
	32	retVal |= input_port_read(machine(),"PAPERADV") & 1 ? 8 : 0;
35	33	return retVal;
36	34	}
37	35
38	36
39		static WRITE8_HANDLER(shifter_w)
	37	WRITE8_MEMBER(busicom_state::shifter_w)
40	38	{
41		busicom_state *state = space->machine().driver_data<busicom_state>();
42	39	if (BIT(data,0)) {
43		state->m_keyboard_shifter <<= 1;
44		state->m_keyboard_shifter |= BIT(data,1);
	40	m_keyboard_shifter <<= 1;
	41	m_keyboard_shifter |= BIT(data,1);
45	42	}
46	43	if (BIT(data,2)) {
47		state->m_printer_shifter <<= 1;
48		state->m_printer_shifter |= BIT(data,1);
	44	m_printer_shifter <<= 1;
	45	m_printer_shifter |= BIT(data,1);
49	46	}
50	47	}
51	48
52		static WRITE8_HANDLER(printer_w)
	49	WRITE8_MEMBER(busicom_state::printer_w)
53	50	{
54		busicom_state *state = space->machine().driver_data<busicom_state>();
55	51	int i,j;
56	52	if (BIT(data,0)) {
57		logerror("color : %02x %02x %d\n",BIT(data,0),data,state->m_drum_index);
58		state->m_printer_line_color[10] = 1;
	53	logerror("color : %02x %02x %d\n",BIT(data,0),data,m_drum_index);
	54	m_printer_line_color[10] = 1;
59	55
60	56	}
61	57	if (BIT(data,1)) {
62	58	for(i=3;i<18;i++) {
63		if(BIT(state->m_printer_shifter,i)) {
64		state->m_printer_line[10][i-3] = state->m_drum_index + 1;
	59	if(BIT(m_printer_shifter,i)) {
	60	m_printer_line[10][i-3] = m_drum_index + 1;
65	61	}
66	62	}
67		if(BIT(state->m_printer_shifter,0)) {
68		state->m_printer_line[10][15] = state->m_drum_index + 13 + 1;
	63	if(BIT(m_printer_shifter,0)) {
	64	m_printer_line[10][15] = m_drum_index + 13 + 1;
69	65	}
70		if(BIT(state->m_printer_shifter,1)) {
71		state->m_printer_line[10][16] = state->m_drum_index + 26 + 1;
	66	if(BIT(m_printer_shifter,1)) {
	67	m_printer_line[10][16] = m_drum_index + 26 + 1;
72	68	}
73	69	}
74	70	if (BIT(data,3)) {
75	71
76	72	for(j=0;j<10;j++) {
77	73	for(i=0;i<17;i++) {
78		state->m_printer_line[j][i] = state->m_printer_line[j+1][i];
79		state->m_printer_line_color[j] = state->m_printer_line_color[j+1];
	74	m_printer_line[j][i] = m_printer_line[j+1][i];
	75	m_printer_line_color[j] = m_printer_line_color[j+1];
80	76	}
81	77	}
82	78	for(i=0;i<17;i++) {
83		state->m_printer_line[10][i] = 0;
	79	m_printer_line[10][i] = 0;
84	80	}
85		state->m_printer_line_color[10] = 0;
	81	m_printer_line_color[10] = 0;
86	82
87	83	}
88	84	}
89		static WRITE8_HANDLER(status_w)
	85	WRITE8_MEMBER(busicom_state::status_w)
90	86	{
91	87	#if 0
92	88	UINT8 mem_lamp = BIT(data,0);
r14963	r14964
96	92	//logerror("status %c %c %c\n",mem_lamp ? 'M':'x',over_lamp ? 'O':'x',minus_lamp ? '-':'x');
97	93	}
98	94
99		static WRITE8_HANDLER(printer_ctrl_w)
	95	WRITE8_MEMBER(busicom_state::printer_ctrl_w)
100	96	{
101	97	}
102	98
r14963	r14964
112	108
113	109	static ADDRESS_MAP_START( busicom_io , AS_IO, 8, busicom_state )
114	110	ADDRESS_MAP_UNMAP_HIGH
115		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(shifter_w) // ROM0 I/O
116		AM_RANGE(0x01, 0x01) AM_READWRITE_LEGACY(keyboard_r,printer_ctrl_w) // ROM1 I/O
117		AM_RANGE(0x02, 0x02) AM_READ_LEGACY(printer_r)  // ROM2 I/O
118		AM_RANGE(0x10, 0x10) AM_WRITE_LEGACY(printer_w) // RAM0 output
119		AM_RANGE(0x11, 0x11) AM_WRITE_LEGACY(status_w)  // RAM1 output
	111	AM_RANGE(0x00, 0x00) AM_WRITE(shifter_w) // ROM0 I/O
	112	AM_RANGE(0x01, 0x01) AM_READWRITE(keyboard_r,printer_ctrl_w) // ROM1 I/O
	113	AM_RANGE(0x02, 0x02) AM_READ(printer_r)  // ROM2 I/O
	114	AM_RANGE(0x10, 0x10) AM_WRITE(printer_w) // RAM0 output
	115	AM_RANGE(0x11, 0x11) AM_WRITE(status_w)  // RAM1 output
120	116	ADDRESS_MAP_END
121	117
122	118	/* Input ports */

src/mess/drivers/pc.c

r14963	r14964
157	157	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE_LEGACY("pic8259", pic8259_r, pic8259_w)
158	158	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r, pit8253_w)
159	159	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE("ppi8255", i8255_device, read, write)
160		AM_RANGE(0x0080, 0x0087) AM_READWRITE_LEGACY(pc_page_r,         pc_page_w)
161		AM_RANGE(0x00a0, 0x00a0) AM_WRITE_LEGACY(pc_nmi_enable_w )
	160	AM_RANGE(0x0080, 0x0087) AM_READWRITE(pc_page_r,         pc_page_w)
	161	AM_RANGE(0x00a0, 0x00a0) AM_WRITE(pc_nmi_enable_w )
162	162	AM_RANGE(0x0200, 0x0207) AM_READWRITE_LEGACY(pc_JOY_r,            pc_JOY_w)
163		AM_RANGE(0x0240, 0x0257) AM_READWRITE_LEGACY(pc_rtc_r,            pc_rtc_w)
	163	AM_RANGE(0x0240, 0x0257) AM_READWRITE(pc_rtc_r,            pc_rtc_w)
164	164	AM_RANGE(0x0278, 0x027b) AM_DEVREADWRITE_LEGACY("lpt_2", pc_lpt_r, pc_lpt_w)
165	165	AM_RANGE(0x02e8, 0x02ef) AM_DEVREADWRITE("ins8250_3", ins8250_device, ins8250_r, ins8250_w)
166	166	AM_RANGE(0x02f8, 0x02ff) AM_DEVREADWRITE("ins8250_1", ins8250_device, ins8250_r, ins8250_w)
r14963	r14964
183	183	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8_LEGACY("pit8253", pit8253_r, pit8253_w, 0xffff)
184	184	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("ppi8255", i8255_device, read, write, 0xffff)
185	185	AM_RANGE(0x0070, 0x007f) AM_RAM // needed for Poisk-2
186		AM_RANGE(0x0080, 0x0087) AM_READWRITE8_LEGACY(pc_page_r,            pc_page_w, 0xffff)
187		AM_RANGE(0x00a0, 0x00a1) AM_WRITE8_LEGACY(pc_nmi_enable_w, 0x00ff )
	186	AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r,            pc_page_w, 0xffff)
	187	AM_RANGE(0x00a0, 0x00a1) AM_WRITE8(pc_nmi_enable_w, 0x00ff )
188	188	AM_RANGE(0x0200, 0x0207) AM_READWRITE_LEGACY(pc16le_JOY_r,            pc16le_JOY_w)
189		AM_RANGE(0x0240, 0x0257) AM_READWRITE_LEGACY(pc16le_rtc_r,            pc16le_rtc_w)
	189	AM_RANGE(0x0240, 0x0257) AM_READWRITE8(pc_rtc_r,            pc_rtc_w, 0xffff)
190	190	AM_RANGE(0x0278, 0x027b) AM_DEVREADWRITE8_LEGACY("lpt_2", pc_lpt_r, pc_lpt_w, 0x00ff)
191	191	AM_RANGE(0x02b0, 0x02bf) AM_RAM // needed for EC-18xx
192	192	AM_RANGE(0x02e8, 0x02ef) AM_DEVREADWRITE8("ins8250_3", ins8250_device, ins8250_r, ins8250_w, 0xffff)
r14963	r14964
207	207	AM_RANGE(0xfc000, 0xfffff) AM_ROM
208	208	ADDRESS_MAP_END
209	209
210		static READ8_HANDLER( unk_r )
	210	READ8_MEMBER(pc_state::unk_r)
211	211	{
212	212	return 0;
213	213	}
r14963	r14964
219	219	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8_LEGACY("pit8253", pit8253_r, pit8253_w, 0xffff)
220	220	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("ppi8255", i8255_device, read, write, 0xffff)
221	221	AM_RANGE(0x0070, 0x007f) AM_RAM // needed for Poisk-2
222		AM_RANGE(0x0080, 0x0087) AM_READWRITE8_LEGACY(pc_page_r,            pc_page_w, 0xffff)
223		AM_RANGE(0x00a0, 0x00a1) AM_READWRITE8_LEGACY(unk_r, pc_nmi_enable_w, 0x00ff )
	222	AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r,            pc_page_w, 0xffff)
	223	AM_RANGE(0x00a0, 0x00a1) AM_READWRITE8(unk_r, pc_nmi_enable_w, 0x00ff )
224	224	AM_RANGE(0x0200, 0x0207) AM_READWRITE_LEGACY(pc16le_JOY_r,            pc16le_JOY_w)
225		AM_RANGE(0x0240, 0x0257) AM_READWRITE_LEGACY(pc16le_rtc_r,            pc16le_rtc_w)
	225	AM_RANGE(0x0240, 0x0257) AM_READWRITE8(pc_rtc_r,            pc_rtc_w, 0xffff)
226	226	AM_RANGE(0x0278, 0x027b) AM_DEVREADWRITE8_LEGACY("lpt_2", pc_lpt_r, pc_lpt_w, 0x00ff)
227	227	AM_RANGE(0x02b0, 0x02bf) AM_RAM // needed for EC-18xx
228	228	AM_RANGE(0x02e8, 0x02ef) AM_DEVREADWRITE8("ins8250_3", ins8250_device, ins8250_r, ins8250_w, 0xffff)
r14963	r14964
252	252	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE_LEGACY("pic8259", pic8259_r, pic8259_w)
253	253	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r, pit8253_w)
254	254	AM_RANGE(0x0060, 0x0063) AM_READWRITE_LEGACY(europc_pio_r,         europc_pio_w)
255		AM_RANGE(0x0080, 0x0087) AM_READWRITE_LEGACY(pc_page_r,         pc_page_w)
	255	AM_RANGE(0x0080, 0x0087) AM_READWRITE(pc_page_r,         pc_page_w)
256	256	AM_RANGE(0x0200, 0x0207) AM_READWRITE_LEGACY(pc_JOY_r,            pc_JOY_w)
257	257	AM_RANGE(0x0250, 0x025f) AM_READWRITE_LEGACY(europc_jim_r,         europc_jim_w)
258	258	AM_RANGE(0x0278, 0x027b) AM_DEVREADWRITE_LEGACY("lpt_2", pc_lpt_r, pc_lpt_w)
r14963	r14964
286	286	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE_LEGACY("pic8259", pic8259_r, pic8259_w)
287	287	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r, pit8253_w)
288	288	AM_RANGE(0x0060, 0x0063) AM_READWRITE_LEGACY(tandy1000_pio_r,         tandy1000_pio_w)
289		AM_RANGE(0x0080, 0x0087) AM_READWRITE_LEGACY(pc_page_r,            pc_page_w)
	289	AM_RANGE(0x0080, 0x0087) AM_READWRITE(pc_page_r,            pc_page_w)
290	290	AM_RANGE(0x00c0, 0x00c0) AM_DEVWRITE_LEGACY("sn76496",   sn76496_w)
291	291	AM_RANGE(0x0200, 0x0207) AM_READWRITE_LEGACY(pc_JOY_r,               pc_JOY_w)
292	292	AM_RANGE(0x02f8, 0x02ff) AM_DEVREADWRITE("ins8250_1", ins8250_device, ins8250_r, ins8250_w)
r14963	r14964
316	316	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE8_LEGACY("pic8259", pic8259_r, pic8259_w, 0xffff)
317	317	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8_LEGACY("pit8253", pit8253_r, pit8253_w, 0xffff)
318	318	AM_RANGE(0x0060, 0x0063) AM_READWRITE8_LEGACY(tandy1000_pio_r,         tandy1000_pio_w, 0xffff)
319		AM_RANGE(0x0080, 0x0087) AM_READWRITE8_LEGACY(pc_page_r,            pc_page_w, 0xffff)
	319	AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r,            pc_page_w, 0xffff)
320	320	AM_RANGE(0x00c0, 0x00c1) AM_DEVWRITE8_LEGACY("sn76496",   sn76496_w, 0xffff)
321	321	AM_RANGE(0x0200, 0x0207) AM_READWRITE8_LEGACY(pc_JOY_r,               pc_JOY_w, 0xffff)
322	322	AM_RANGE(0x02f8, 0x02ff) AM_DEVREADWRITE8("ins8250_1", ins8250_device, ins8250_r, ins8250_w, 0xffff)
r14963	r14964
347	347	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE8_LEGACY("pic8259", pic8259_r, pic8259_w, 0xffff)
348	348	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8_LEGACY("pit8253", pit8253_r, pit8253_w, 0xffff)
349	349	AM_RANGE(0x0060, 0x0063) AM_READWRITE8_LEGACY(tandy1000_pio_r,         tandy1000_pio_w, 0xffff)
350		AM_RANGE(0x0080, 0x0087) AM_READWRITE8_LEGACY(pc_page_r,               pc_page_w, 0xffff)
	350	AM_RANGE(0x0080, 0x0087) AM_READWRITE8(pc_page_r,               pc_page_w, 0xffff)
351	351	AM_RANGE(0x00c0, 0x00c1) AM_DEVWRITE8_LEGACY("sn76496",    sn76496_w, 0xffff)
352	352	AM_RANGE(0x0200, 0x0207) AM_READWRITE8_LEGACY(pc_JOY_r,                    pc_JOY_w, 0xffff)
353	353	AM_RANGE(0x02f8, 0x02ff) AM_DEVREADWRITE8("ins8250_1", ins8250_device, ins8250_r, ins8250_w, 0xffff)
r14963	r14964
376	376	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE_LEGACY("pic8259", pic8259_r, pic8259_w)
377	377	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE_LEGACY("pit8253", pit8253_r, pit8253_w)
378	378	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE("ppi8255", i8255_device, read, write)
379		AM_RANGE(0x0080, 0x0087) AM_READWRITE_LEGACY(pc_page_r,            pc_page_w)
380		AM_RANGE(0x00a0, 0x00a0) AM_READWRITE_LEGACY(pcjr_nmi_enable_r, pc_nmi_enable_w )
	379	AM_RANGE(0x0080, 0x0087) AM_READWRITE(pc_page_r,            pc_page_w)
	380	AM_RANGE(0x00a0, 0x00a0) AM_READWRITE(pcjr_nmi_enable_r, pc_nmi_enable_w )
381	381	AM_RANGE(0x00c0, 0x00c0) AM_DEVWRITE_LEGACY("sn76496",   sn76496_w)
382	382	AM_RANGE(0x00f0, 0x00f7) AM_READWRITE_LEGACY(pc_fdc_r,               pcjr_fdc_w)
383	383	AM_RANGE(0x0200, 0x0207) AM_READWRITE_LEGACY(pc_JOY_r,               pc_JOY_w)
r14963	r14964
728	728
729	729	static const kb_keytronic_interface pc_keytronic_intf =
730	730	{
731		DEVCB_MEMORY_HANDLER("maincpu", IO, ibm5150_kb_set_clock_signal),
732		DEVCB_MEMORY_HANDLER("maincpu", IO, ibm5150_kb_set_data_signal),
	731	DEVCB_DRIVER_MEMBER(pc_state, ibm5150_kb_set_clock_signal),
	732	DEVCB_DRIVER_MEMBER(pc_state, ibm5150_kb_set_data_signal),
733	733	};
734	734
735	735

src/mess/drivers/pecom.c

r14963	r14964
24	24	ADDRESS_MAP_END
25	25
26	26	static ADDRESS_MAP_START( pecom64_io, AS_IO, 8, pecom_state )
27		AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(pecom_bank_w)
28		AM_RANGE(0x03, 0x03) AM_READ_LEGACY(pecom_keyboard_r)
29		AM_RANGE(0x03, 0x07) AM_WRITE_LEGACY(pecom_cdp1869_w)
	27	AM_RANGE(0x01, 0x01) AM_WRITE(pecom_bank_w)
	28	AM_RANGE(0x03, 0x03) AM_READ(pecom_keyboard_r)
	29	AM_RANGE(0x03, 0x07) AM_WRITE(pecom_cdp1869_w)
30	30	ADDRESS_MAP_END
31	31
32	32	/* Input ports */

src/mess/drivers/pce.c

r14963	r14964
72	72	AM_RANGE( 0x0D0000, 0x0FFFFF) AM_ROMBANK("bank4")
73	73	AM_RANGE( 0x100000, 0x10FFFF) AM_RAM AM_SHARE("cd_ram")
74	74	AM_RANGE( 0x110000, 0x1EDFFF) AM_NOP
75		AM_RANGE( 0x1EE000, 0x1EE7FF) AM_ROMBANK("bank10") AM_WRITE_LEGACY(pce_cd_bram_w )
	75	AM_RANGE( 0x1EE000, 0x1EE7FF) AM_ROMBANK("bank10") AM_WRITE(pce_cd_bram_w )
76	76	AM_RANGE( 0x1EE800, 0x1EFFFF) AM_NOP
77	77	AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000) AM_SHARE("user_ram")
78	78	AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
79	79	AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
80	80	AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY(C6280_TAG, c6280_r, c6280_w )
81	81	AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w )
82		AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE_LEGACY(mess_pce_joystick_r, mess_pce_joystick_w )
	82	AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE(mess_pce_joystick_r, mess_pce_joystick_w )
83	83	AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
84		AM_RANGE( 0x1FF800, 0x1FFBFF) AM_READWRITE_LEGACY(pce_cd_intf_r, pce_cd_intf_w )
	84	AM_RANGE( 0x1FF800, 0x1FFBFF) AM_READWRITE(pce_cd_intf_r, pce_cd_intf_w )
85	85	ADDRESS_MAP_END
86	86
87	87	static ADDRESS_MAP_START( pce_io , AS_IO, 8, pce_state )
r14963	r14964
95	95	AM_RANGE( 0x0D0000, 0x0FFFFF) AM_ROMBANK("bank4")
96	96	AM_RANGE( 0x100000, 0x10FFFF) AM_RAM AM_SHARE("cd_ram")
97	97	AM_RANGE( 0x110000, 0x1EDFFF) AM_NOP
98		AM_RANGE( 0x1EE000, 0x1EE7FF) AM_ROMBANK("bank10") AM_WRITE_LEGACY(pce_cd_bram_w )
	98	AM_RANGE( 0x1EE000, 0x1EE7FF) AM_ROMBANK("bank10") AM_WRITE(pce_cd_bram_w )
99	99	AM_RANGE( 0x1EE800, 0x1EFFFF) AM_NOP
100	100	AM_RANGE( 0x1F0000, 0x1F7FFF) AM_RAM AM_SHARE("user_ram")
101	101	AM_RANGE( 0x1FE000, 0x1FE007) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w ) AM_MIRROR(0x03E0)
r14963	r14964
104	104	AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
105	105	AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY(C6280_TAG, c6280_r, c6280_w )
106	106	AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w )
107		AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE_LEGACY(mess_pce_joystick_r, mess_pce_joystick_w )
	107	AM_RANGE( 0x1FF000, 0x1FF3FF) AM_READWRITE(mess_pce_joystick_r, mess_pce_joystick_w )
108	108	AM_RANGE( 0x1FF400, 0x1FF7FF) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
109		AM_RANGE( 0x1FF800, 0x1FFBFF) AM_READWRITE_LEGACY(pce_cd_intf_r, pce_cd_intf_w )
	109	AM_RANGE( 0x1FF800, 0x1FFBFF) AM_READWRITE(pce_cd_intf_r, pce_cd_intf_w )
110	110	ADDRESS_MAP_END
111	111
112	112	static ADDRESS_MAP_START( sgx_io , AS_IO, 8, pce_state )

src/mess/drivers/bbc.c

r14963	r14964
91	91	&E0-&FF Tube ULA        Tube system interface           32 (32 bytes x  1 ) 2MHz
92	92	******************************************************************************/
93	93
94		static READ8_HANDLER( bbc_fe_r )
	94	READ8_MEMBER(bbc_state::bbc_fe_r)
95	95	{
96	96	return 0xfe;
97	97	}
r14963	r14964
99	99	static ADDRESS_MAP_START( bbca_mem, AS_PROGRAM, 8, bbc_state )
100	100	ADDRESS_MAP_UNMAP_HIGH                                                       /*  Hardware marked with a # is not present in a Model A        */
101	101
102		AM_RANGE(0x0000, 0x3fff) AM_READ_BANK("bank1") AM_WRITE_LEGACY(bbc_memorya1_w)                  /*    0000-3fff                 Regular Ram                     */
103		AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank3") AM_WRITE_LEGACY(bbc_memorya1_w)                  /*    4000-7fff                 Repeat of the Regular Ram       */
	102	AM_RANGE(0x0000, 0x3fff) AM_READ_BANK("bank1") AM_WRITE(bbc_memorya1_w)                  /*    0000-3fff                 Regular Ram                     */
	103	AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank3") AM_WRITE(bbc_memorya1_w)                  /*    4000-7fff                 Repeat of the Regular Ram       */
104	104
105	105	AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank4")                                          /*    8000-bfff                 Paged ROM                       */
106	106
r14963	r14964
109	109	AM_RANGE(0xfc00, 0xfdff) AM_NOP                                                          /*    fc00-fdff                 FRED & JIM Pages                */
110	110
111	111	/*    fe00-feff                 Shiela Address Page             */
112		AM_RANGE(0xfe00, 0xfe07) AM_READWRITE_LEGACY(bbc_6845_r , bbc_6845_w)                        /*    fe00-fe07  6845 CRTA      Video controller                */
	112	AM_RANGE(0xfe00, 0xfe07) AM_READWRITE(bbc_6845_r , bbc_6845_w)                        /*    fe00-fe07  6845 CRTA      Video controller                */
113	113	AM_RANGE(0xfe08, 0xfe08) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, status_read, control_write)
114	114	AM_RANGE(0xfe09, 0xfe09) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, data_read, data_write)
115		AM_RANGE(0xfe10, 0xfe17) AM_READWRITE_LEGACY(bbc_fe_r, bbc_SerialULA_w)                     /*    fe10-fe17  Serial ULA     Serial system chip              */
	115	AM_RANGE(0xfe10, 0xfe17) AM_READWRITE(bbc_fe_r, bbc_SerialULA_w)                     /*    fe10-fe17  Serial ULA     Serial system chip              */
116	116	AM_RANGE(0xfe18, 0xfe1f) AM_NOP                                                /*    fe18-fe1f  INTOFF/STATID  # ECONET Interrupt Off / ID No. */
117		AM_RANGE(0xfe20, 0xfe2f) AM_WRITE_LEGACY(bbc_videoULA_w)                                 /* R: fe20-fe2f  INTON          # ECONET Interrupt On           */
	117	AM_RANGE(0xfe20, 0xfe2f) AM_WRITE(bbc_videoULA_w)                                 /* R: fe20-fe2f  INTON          # ECONET Interrupt On           */
118	118	/* W: fe20-fe2f  Video ULA      Video system chip               */
119		AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE_LEGACY(bbc_fe_r, bbc_page_selecta_w)                     /* R: fe30-fe3f  NC             Not Connected                   */
	119	AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selecta_w)                     /* R: fe30-fe3f  NC             Not Connected                   */
120	120	/* W: fe30-fe3f  84LS161        Paged ROM selector              */
121	121	AM_RANGE(0xfe40, 0xfe5f) AM_DEVREADWRITE("via6522_0", via6522_device, read, write)   /*    fe40-fe5f  6522 VIA       SYSTEM VIA                      */
122	122	AM_RANGE(0xfe60, 0xfe7f) AM_NOP                                                /*    fe60-fe7f  6522 VIA       # USER VIA                      */
123	123	AM_RANGE(0xfe80, 0xfe9f) AM_NOP                                                /*    fe80-fe9f  8271/1770 FDC  # Floppy disc controller        */
124		AM_RANGE(0xfea0, 0xfebf) AM_READ_LEGACY(bbc_fe_r)                                       /*    fea0-febf  68B54 ADLC     # ECONET controller             */
	124	AM_RANGE(0xfea0, 0xfebf) AM_READ(bbc_fe_r)                                       /*    fea0-febf  68B54 ADLC     # ECONET controller             */
125	125	AM_RANGE(0xfec0, 0xfedf) AM_NOP                                                /*    fec0-fedf  uPD7002        # Analogue to digital converter */
126		AM_RANGE(0xfee0, 0xfeff) AM_READ_LEGACY(bbc_fe_r)                                       /*    fee0-feff  Tube ULA       # Tube system interface         */
	126	AM_RANGE(0xfee0, 0xfeff) AM_READ(bbc_fe_r)                                       /*    fee0-feff  Tube ULA       # Tube system interface         */
127	127
128	128	AM_RANGE(0xff00, 0xffff) AM_ROM AM_REGION("user1", 0x13f00)                           /*    ff00-ffff                 OS Rom (continued)              */
129	129	ADDRESS_MAP_END
r14963	r14964
132	132	static ADDRESS_MAP_START( bbcb_mem, AS_PROGRAM, 8, bbc_state )
133	133	ADDRESS_MAP_UNMAP_HIGH
134	134
135		AM_RANGE(0x0000, 0x3fff) AM_READ_BANK("bank1") AM_WRITE_LEGACY(bbc_memorya1_w)                  /*    0000-3fff                 Regular Ram                     */
136		AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank3") AM_WRITE_LEGACY(bbc_memoryb3_w)                  /*    4000-7fff                 Repeat of the Regular Ram       */
	135	AM_RANGE(0x0000, 0x3fff) AM_READ_BANK("bank1") AM_WRITE(bbc_memorya1_w)                  /*    0000-3fff                 Regular Ram                     */
	136	AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank3") AM_WRITE(bbc_memoryb3_w)                  /*    4000-7fff                 Repeat of the Regular Ram       */
137	137
138	138
139		AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank4") AM_WRITE_LEGACY(bbc_memoryb4_w)                  /*    8000-bfff                 Paged ROM                       */
	139	AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank4") AM_WRITE(bbc_memoryb4_w)                  /*    8000-bfff                 Paged ROM                       */
140	140
141	141	AM_RANGE(0xc000, 0xfbff) AM_READ_BANK("bank7")                                    /*    c000-fbff                 OS ROM                          */
142	142
143		AM_RANGE(0xfc00, 0xfdff) AM_READWRITE_LEGACY(bbc_opus_read, bbc_opus_write)                  /*    fc00-fdff                 OPUS Disc Controller            */
	143	AM_RANGE(0xfc00, 0xfdff) AM_READWRITE(bbc_opus_read, bbc_opus_write)                  /*    fc00-fdff                 OPUS Disc Controller            */
144	144
145	145	/*    fe00-feff                 Shiela Address Page             */
146		AM_RANGE(0xfe00, 0xfe07) AM_READWRITE_LEGACY(bbc_6845_r, bbc_6845_w)                        /*    fe00-fe07  6845 CRTC      Video controller                */
	146	AM_RANGE(0xfe00, 0xfe07) AM_READWRITE(bbc_6845_r, bbc_6845_w)                        /*    fe00-fe07  6845 CRTC      Video controller                */
147	147	AM_RANGE(0xfe08, 0xfe08) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, status_read, control_write)
148	148	AM_RANGE(0xfe09, 0xfe09) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, data_read, data_write)
149		AM_RANGE(0xfe10, 0xfe17) AM_READWRITE_LEGACY(bbc_fe_r, bbc_SerialULA_w)                     /*    fe10-fe17  Serial ULA     Serial system chip              */
	149	AM_RANGE(0xfe10, 0xfe17) AM_READWRITE(bbc_fe_r, bbc_SerialULA_w)                     /*    fe10-fe17  Serial ULA     Serial system chip              */
150	150	AM_RANGE(0xfe18, 0xfe1f) AM_NOP                                                /*    fe18-fe1f  INTOFF/STATID  ECONET Interrupt Off / ID No.   */
151		AM_RANGE(0xfe20, 0xfe2f) AM_WRITE_LEGACY(bbc_videoULA_w)                                 /* R: fe20-fe2f  INTON          ECONET Interrupt On             */
	151	AM_RANGE(0xfe20, 0xfe2f) AM_WRITE(bbc_videoULA_w)                                 /* R: fe20-fe2f  INTON          ECONET Interrupt On             */
152	152	/* W: fe20-fe2f  Video ULA      Video system chip               */
153		AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE_LEGACY(bbc_fe_r, bbc_page_selectb_w)                     /* R: fe30-fe3f  NC             Not Connected                   */
	153	AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selectb_w)                     /* R: fe30-fe3f  NC             Not Connected                   */
154	154	/* W: fe30-fe3f  84LS161        Paged ROM selector              */
155	155	AM_RANGE(0xfe40, 0xfe5f) AM_DEVREADWRITE("via6522_0", via6522_device, read, write)   /*    fe40-fe5f  6522 VIA       SYSTEM VIA                      */
156	156	AM_RANGE(0xfe60, 0xfe7f) AM_DEVREADWRITE("via6522_1", via6522_device, read, write)   /*    fe60-fe7f  6522 VIA       USER VIA                        */
157		AM_RANGE(0xfe80, 0xfe9f) AM_READWRITE_LEGACY(bbc_disc_r, bbc_disc_w)                        /*    fe80-fe9f  8271 FDC       Floppy disc controller          */
158		AM_RANGE(0xfea0, 0xfebf) AM_READ_LEGACY(bbc_fe_r)                                       /*    fea0-febf  68B54 ADLC     ECONET controller               */
	157	AM_RANGE(0xfe80, 0xfe9f) AM_READWRITE(bbc_disc_r, bbc_disc_w)                        /*    fe80-fe9f  8271 FDC       Floppy disc controller          */
	158	AM_RANGE(0xfea0, 0xfebf) AM_READ(bbc_fe_r)                                       /*    fea0-febf  68B54 ADLC     ECONET controller               */
159	159	AM_RANGE(0xfec0, 0xfedf) AM_DEVREADWRITE_LEGACY("upd7002",uPD7002_r,uPD7002_w)                  /*    fec0-fedf  uPD7002        Analogue to digital converter   */
160		AM_RANGE(0xfee0, 0xfeff) AM_READ_LEGACY(bbc_fe_r)                                       /*    fee0-feff  Tube ULA       Tube system interface           */
	160	AM_RANGE(0xfee0, 0xfeff) AM_READ(bbc_fe_r)                                       /*    fee0-feff  Tube ULA       Tube system interface           */
161	161
162	162	AM_RANGE(0xff00, 0xffff) AM_ROM AM_REGION("user1", 0x43f00)                           /*    ff00-ffff                 OS Rom (continued)              */
163	163	ADDRESS_MAP_END
r14963	r14964
166	166	static ADDRESS_MAP_START( bbcbp_mem, AS_PROGRAM, 8, bbc_state )
167	167	ADDRESS_MAP_UNMAP_HIGH
168	168
169		AM_RANGE(0x0000, 0x2fff) AM_READ_BANK("bank1") AM_WRITE_LEGACY(bbc_memorybp1_w)               /*    0000-2fff                 Regular Ram                     */
170		AM_RANGE(0x3000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE_LEGACY(bbc_memorybp2_w)               /*    3000-7fff                 Video/Shadow Ram                */
	169	AM_RANGE(0x0000, 0x2fff) AM_READ_BANK("bank1") AM_WRITE(bbc_memorybp1_w)               /*    0000-2fff                 Regular Ram                     */
	170	AM_RANGE(0x3000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE(bbc_memorybp2_w)               /*    3000-7fff                 Video/Shadow Ram                */
171	171
172		AM_RANGE(0x8000, 0xafff) AM_READ_BANK("bank4") AM_WRITE_LEGACY(bbc_memorybp4_w)               /*    8000-afff                 Paged ROM or 12K of RAM         */
	172	AM_RANGE(0x8000, 0xafff) AM_READ_BANK("bank4") AM_WRITE(bbc_memorybp4_w)               /*    8000-afff                 Paged ROM or 12K of RAM         */
173	173	AM_RANGE(0xb000, 0xbfff) AM_READ_BANK("bank6")                                    /*    b000-bfff                 Rest of paged ROM area          */
174	174
175	175	AM_RANGE(0xc000, 0xfbff) AM_READ_BANK("bank7")                                   /*    c000-fbff                 OS ROM                          */
r14963	r14964
177	177	AM_RANGE(0xfc00, 0xfdff) AM_NOP                                                /*    fc00-fdff                 FRED & JIM Pages                */
178	178
179	179	/*    fe00-feff                 Shiela Address Page             */
180		AM_RANGE(0xfe00, 0xfe07) AM_READWRITE_LEGACY(bbc_6845_r, bbc_6845_w)                        /*    fe00-fe07  6845 CRTC      Video controller                */
	180	AM_RANGE(0xfe00, 0xfe07) AM_READWRITE(bbc_6845_r, bbc_6845_w)                        /*    fe00-fe07  6845 CRTC      Video controller                */
181	181	AM_RANGE(0xfe08, 0xfe08) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, status_read, control_write)
182	182	AM_RANGE(0xfe09, 0xfe09) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, data_read, data_write)
183		AM_RANGE(0xfe10, 0xfe17) AM_READWRITE_LEGACY(bbc_fe_r, bbc_SerialULA_w)                     /*    fe10-fe17  Serial ULA     Serial system chip              */
	183	AM_RANGE(0xfe10, 0xfe17) AM_READWRITE(bbc_fe_r, bbc_SerialULA_w)                     /*    fe10-fe17  Serial ULA     Serial system chip              */
184	184	AM_RANGE(0xfe18, 0xfe1f) AM_NOP                                                /*    fe18-fe1f  INTOFF/STATID  ECONET Interrupt Off / ID No.   */
185		AM_RANGE(0xfe20, 0xfe2f) AM_WRITE_LEGACY(bbc_videoULA_w)                                 /* R: fe20-fe2f  INTON          ECONET Interrupt On             */
	185	AM_RANGE(0xfe20, 0xfe2f) AM_WRITE(bbc_videoULA_w)                                 /* R: fe20-fe2f  INTON          ECONET Interrupt On             */
186	186	/* W: fe20-fe2f  Video ULA      Video system chip               */
187		AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE_LEGACY(bbc_fe_r, bbc_page_selectbp_w)                  /* R: fe30-fe3f  NC             Not Connected                   */
	187	AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selectbp_w)                  /* R: fe30-fe3f  NC             Not Connected                   */
188	188	/* W: fe30-fe3f  84LS161        Paged ROM selector              */
189	189	AM_RANGE(0xfe40, 0xfe5f) AM_DEVREADWRITE("via6522_0", via6522_device, read, write)   /*    fe40-fe5f  6522 VIA       SYSTEM VIA                      */
190	190	AM_RANGE(0xfe60, 0xfe7f) AM_DEVREADWRITE("via6522_1", via6522_device, read, write)   /*    fe60-fe7f  6522 VIA       USER VIA                        */
191		AM_RANGE(0xfe80, 0xfe9f) AM_READWRITE_LEGACY(bbc_wd1770_read, bbc_wd1770_write)               /*    fe80-fe9f  1770 FDC       Floppy disc controller          */
192		AM_RANGE(0xfea0, 0xfebf) AM_READ_LEGACY(bbc_fe_r)                                       /*    fea0-febf  68B54 ADLC     ECONET controller               */
	191	AM_RANGE(0xfe80, 0xfe9f) AM_READWRITE(bbc_wd1770_read, bbc_wd1770_write)               /*    fe80-fe9f  1770 FDC       Floppy disc controller          */
	192	AM_RANGE(0xfea0, 0xfebf) AM_READ(bbc_fe_r)                                       /*    fea0-febf  68B54 ADLC     ECONET controller               */
193	193	AM_RANGE(0xfec0, 0xfedf) AM_DEVREADWRITE_LEGACY("upd7002", uPD7002_r, uPD7002_w)               /*    fec0-fedf  uPD7002        Analogue to digital converter   */
194		AM_RANGE(0xfee0, 0xfeff) AM_READ_LEGACY(bbc_fe_r)                                       /*    fee0-feff  Tube ULA       Tube system interface           */
	194	AM_RANGE(0xfee0, 0xfeff) AM_READ(bbc_fe_r)                                       /*    fee0-feff  Tube ULA       Tube system interface           */
195	195
196	196	AM_RANGE(0xff00, 0xffff) AM_ROM AM_REGION("user1", 0x43f00)                           /*    ff00-ffff                 OS Rom (continued)              */
197	197	ADDRESS_MAP_END
r14963	r14964
201	201	static ADDRESS_MAP_START( bbcbp128_mem, AS_PROGRAM, 8, bbc_state )
202	202	ADDRESS_MAP_UNMAP_HIGH
203	203
204		AM_RANGE(0x0000, 0x2fff) AM_READ_BANK("bank1") AM_WRITE_LEGACY(bbc_memorybp1_w)               /*    0000-2fff                 Regular Ram                     */
205		AM_RANGE(0x3000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE_LEGACY(bbc_memorybp2_w)               /*    3000-7fff                 Video/Shadow Ram                */
	204	AM_RANGE(0x0000, 0x2fff) AM_READ_BANK("bank1") AM_WRITE(bbc_memorybp1_w)               /*    0000-2fff                 Regular Ram                     */
	205	AM_RANGE(0x3000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE(bbc_memorybp2_w)               /*    3000-7fff                 Video/Shadow Ram                */
206	206
207		AM_RANGE(0x8000, 0xafff) AM_READ_BANK("bank4") AM_WRITE_LEGACY(bbc_memorybp4_128_w)            /*    8000-afff                 Paged ROM or 12K of RAM         */
208		AM_RANGE(0xb000, 0xbfff) AM_READ_BANK("bank6") AM_WRITE_LEGACY(bbc_memorybp6_128_w)            /*    b000-bfff                 Rest of paged ROM area          */
	207	AM_RANGE(0x8000, 0xafff) AM_READ_BANK("bank4") AM_WRITE(bbc_memorybp4_128_w)            /*    8000-afff                 Paged ROM or 12K of RAM         */
	208	AM_RANGE(0xb000, 0xbfff) AM_READ_BANK("bank6") AM_WRITE(bbc_memorybp6_128_w)            /*    b000-bfff                 Rest of paged ROM area          */
209	209
210	210	AM_RANGE(0xc000, 0xfbff) AM_READ_BANK("bank7")                                    /*    c000-fbff                 OS ROM                          */
211	211
212	212	AM_RANGE(0xfc00, 0xfdff) AM_NOP                                                /*    fc00-fdff                 FRED & JIM Pages                */
213	213
214	214	/*    fe00-feff                 Shiela Address Page             */
215		AM_RANGE(0xfe00, 0xfe07) AM_READWRITE_LEGACY(bbc_6845_r, bbc_6845_w)                        /*    fe00-fe07  6845 CRTC      Video controller                */
	215	AM_RANGE(0xfe00, 0xfe07) AM_READWRITE(bbc_6845_r, bbc_6845_w)                        /*    fe00-fe07  6845 CRTC      Video controller                */
216	216	AM_RANGE(0xfe08, 0xfe08) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, status_read, control_write)
217	217	AM_RANGE(0xfe09, 0xfe09) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, data_read, data_write)
218		AM_RANGE(0xfe10, 0xfe17) AM_READWRITE_LEGACY(bbc_fe_r, bbc_SerialULA_w)                     /*    fe10-fe17  Serial ULA     Serial system chip              */
	218	AM_RANGE(0xfe10, 0xfe17) AM_READWRITE(bbc_fe_r, bbc_SerialULA_w)                     /*    fe10-fe17  Serial ULA     Serial system chip              */
219	219	AM_RANGE(0xfe10, 0xfe17) AM_NOP                                                /*    fe10-fe17  Serial ULA     Serial system chip              */
220	220	AM_RANGE(0xfe18, 0xfe1f) AM_NOP                                                /*    fe18-fe1f  INTOFF/STATID  ECONET Interrupt Off / ID No.   */
221		AM_RANGE(0xfe20, 0xfe2f) AM_WRITE_LEGACY(bbc_videoULA_w)                                 /* R: fe20-fe2f  INTON          ECONET Interrupt On             */
	221	AM_RANGE(0xfe20, 0xfe2f) AM_WRITE(bbc_videoULA_w)                                 /* R: fe20-fe2f  INTON          ECONET Interrupt On             */
222	222	/* W: fe20-fe2f  Video ULA      Video system chip               */
223		AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE_LEGACY(bbc_fe_r, bbc_page_selectbp_w)                  /* R: fe30-fe3f  NC             Not Connected                   */
	223	AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selectbp_w)                  /* R: fe30-fe3f  NC             Not Connected                   */
224	224	/* W: fe30-fe3f  84LS161        Paged ROM selector              */
225	225	AM_RANGE(0xfe40, 0xfe5f) AM_DEVREADWRITE("via6522_0", via6522_device, read, write)   /*    fe40-fe5f  6522 VIA       SYSTEM VIA                      */
226	226	AM_RANGE(0xfe60, 0xfe7f) AM_DEVREADWRITE("via6522_1", via6522_device, read, write)   /*    fe60-fe7f  6522 VIA       USER VIA                        */
227		AM_RANGE(0xfe80, 0xfe9f) AM_READWRITE_LEGACY(bbc_wd1770_read, bbc_wd1770_write)               /*    fe80-fe9f  1770 FDC       Floppy disc controller          */
228		AM_RANGE(0xfea0, 0xfebf) AM_READ_LEGACY(bbc_fe_r)                                       /*    fea0-febf  68B54 ADLC     ECONET controller               */
	227	AM_RANGE(0xfe80, 0xfe9f) AM_READWRITE(bbc_wd1770_read, bbc_wd1770_write)               /*    fe80-fe9f  1770 FDC       Floppy disc controller          */
	228	AM_RANGE(0xfea0, 0xfebf) AM_READ(bbc_fe_r)                                       /*    fea0-febf  68B54 ADLC     ECONET controller               */
229	229	AM_RANGE(0xfec0, 0xfedf) AM_DEVREADWRITE_LEGACY("upd7002", uPD7002_r, uPD7002_w)               /*    fec0-fedf  uPD7002        Analogue to digital converter   */
230		AM_RANGE(0xfee0, 0xfeff) AM_READ_LEGACY(bbc_fe_r)                                       /*    fee0-feff  Tube ULA       Tube system interface           */
	230	AM_RANGE(0xfee0, 0xfeff) AM_READ(bbc_fe_r)                                       /*    fee0-feff  Tube ULA       Tube system interface           */
231	231
232	232	AM_RANGE(0xff00, 0xffff) AM_ROM AM_REGION("user1", 0x43f00)                           /*    ff00-ffff                 OS Rom (continued)              */
233	233	ADDRESS_MAP_END
r14963	r14964
260	260
261	261	static ADDRESS_MAP_START(bbcm_mem, AS_PROGRAM, 8, bbc_state )
262	262
263		AM_RANGE(0x0000, 0x2fff) AM_READ_BANK("bank1") AM_WRITE_LEGACY(bbc_memorybm1_w)               /*    0000-2fff                 Regular Ram                     */
	263	AM_RANGE(0x0000, 0x2fff) AM_READ_BANK("bank1") AM_WRITE(bbc_memorybm1_w)               /*    0000-2fff                 Regular Ram                     */
264	264
265		AM_RANGE(0x3000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE_LEGACY(bbc_memorybm2_w)               /*    3000-7fff                 Video/Shadow Ram                */
	265	AM_RANGE(0x3000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE(bbc_memorybm2_w)               /*    3000-7fff                 Video/Shadow Ram                */
266	266
267		AM_RANGE(0x8000, 0x8fff) AM_READ_BANK("bank4") AM_WRITE_LEGACY(bbc_memorybm4_w)               /*    8000-8fff                 Paged ROM/RAM or 4K of RAM ANDY */
268		AM_RANGE(0x9000, 0xbfff) AM_READ_BANK("bank5") AM_WRITE_LEGACY(bbc_memorybm5_w)               /*    9000-bfff                 Rest of paged ROM/RAM area      */
	267	AM_RANGE(0x8000, 0x8fff) AM_READ_BANK("bank4") AM_WRITE(bbc_memorybm4_w)               /*    8000-8fff                 Paged ROM/RAM or 4K of RAM ANDY */
	268	AM_RANGE(0x9000, 0xbfff) AM_READ_BANK("bank5") AM_WRITE(bbc_memorybm5_w)               /*    9000-bfff                 Rest of paged ROM/RAM area      */
269	269
270		AM_RANGE(0xc000, 0xdfff) AM_READ_BANK("bank7") AM_WRITE_LEGACY(bbc_memorybm7_w)               /*    c000-dfff                 OS ROM or 8K of RAM       HAZEL */
	270	AM_RANGE(0xc000, 0xdfff) AM_READ_BANK("bank7") AM_WRITE(bbc_memorybm7_w)               /*    c000-dfff                 OS ROM or 8K of RAM       HAZEL */
271	271	AM_RANGE(0xe000, 0xfbff) AM_ROM AM_REGION("user1", 0x42000)                           /*    e000-fbff                 OS ROM                          */
272	272
273		//AM_RANGE(0xfc00, 0xfeff) AM_READWRITE_LEGACY(bbcm_r, bbcm_w)
274		AM_RANGE(0xfc00, 0xfeff) AM_READ_BANK("bank8") AM_WRITE_LEGACY(bbcm_w)                        /*    this is now processed directly because it can be ROM or hardware */
	273	//AM_RANGE(0xfc00, 0xfeff) AM_READWRITE(bbcm_r, bbcm_w)
	274	AM_RANGE(0xfc00, 0xfeff) AM_READ_BANK("bank8") AM_WRITE(bbcm_w)                        /*    this is now processed directly because it can be ROM or hardware */
275	275
276	276	AM_RANGE(0xff00, 0xffff) AM_ROM AM_REGION("user1", 0x43f00)                           /*    ff00-ffff                 OS Rom (continued)              */
277	277	ADDRESS_MAP_END

src/mess/drivers/gba.c

r14963	r14964
522	522	state->m_irq_timer->adjust(attotime::never);
523	523	}
524	524
525		static READ32_HANDLER( gba_io_r )
	525	READ32_MEMBER(gba_state::gba_io_r)
526	526	{
527	527	UINT32 retval = 0;
528		running_machine &machine = space->machine();
529		device_t *gb_device = space->machine().device("custom");
530		gba_state *state = machine.driver_data<gba_state>();
	528	device_t *gb_device = machine().device("custom");
531	529
532	530	switch( offset )
533	531	{
534	532	case 0x0000/4:
535	533	if( (mem_mask) & 0x0000ffff )
536	534	{
537		verboselog(machine, 2, "GBA IO Register Read: DISPCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_DISPCNT );
538		retval |= state->m_DISPCNT;
	535	verboselog(machine(), 2, "GBA IO Register Read: DISPCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_DISPCNT );
	536	retval |= m_DISPCNT;
539	537	}
540	538	if( (mem_mask) & 0xffff0000 )
541	539	{
542		verboselog(machine, 2, "GBA IO Register Read: Green Swap (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_GRNSWAP );
543		retval |= state->m_GRNSWAP << 16;
	540	verboselog(machine(), 2, "GBA IO Register Read: Green Swap (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_GRNSWAP );
	541	retval |= m_GRNSWAP << 16;
544	542	}
545	543	break;
546	544	case 0x0004/4:
547		retval = (state->m_DISPSTAT & 0xffff) | (machine.primary_screen->vpos()<<16);
	545	retval = (m_DISPSTAT & 0xffff) | (machine().primary_screen->vpos()<<16);
548	546	break;
549	547	case 0x0008/4:
550	548	if( (mem_mask) & 0x0000ffff )
551	549	{
552		verboselog(machine, 2, "GBA IO Register Read: BG0CNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_BG0CNT );
553		retval |= state->m_BG0CNT;
	550	verboselog(machine(), 2, "GBA IO Register Read: BG0CNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_BG0CNT );
	551	retval |= m_BG0CNT;
554	552	}
555	553	if( (mem_mask) & 0xffff0000 )
556	554	{
557		verboselog(machine, 2, "GBA IO Register Read: BG1CNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_BG1CNT );
558		retval |= state->m_BG1CNT << 16;
	555	verboselog(machine(), 2, "GBA IO Register Read: BG1CNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_BG1CNT );
	556	retval |= m_BG1CNT << 16;
559	557	}
560	558	break;
561	559	case 0x000c/4:
562	560	if( (mem_mask) & 0x0000ffff )
563	561	{
564		verboselog(machine, 2, "GBA IO Register Read: BG2CNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_BG2CNT );
565		retval |= state->m_BG2CNT;
	562	verboselog(machine(), 2, "GBA IO Register Read: BG2CNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_BG2CNT );
	563	retval |= m_BG2CNT;
566	564	}
567	565	if( (mem_mask) & 0xffff0000 )
568	566	{
569		verboselog(machine, 2, "GBA IO Register Read: BG3CNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_BG3CNT );
570		retval |= state->m_BG3CNT << 16;
	567	verboselog(machine(), 2, "GBA IO Register Read: BG3CNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_BG3CNT );
	568	retval |= m_BG3CNT << 16;
571	569	}
572	570	break;
573	571	case 0x0010/4:
574	572	if( (mem_mask) & 0x0000ffff )
575	573	{
576		verboselog(machine, 2, "GBA IO Register Read: BG0HOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	574	verboselog(machine(), 2, "GBA IO Register Read: BG0HOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
577	575	}
578	576	if( (mem_mask) & 0xffff0000 )
579	577	{
580		verboselog(machine, 2, "GBA IO Register Read: BG0VOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	578	verboselog(machine(), 2, "GBA IO Register Read: BG0VOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
581	579	}
582	580	break;
583	581	case 0x0014/4:
584	582	if( (mem_mask) & 0x0000ffff )
585	583	{
586		verboselog(machine, 2, "GBA IO Register Read: BG1HOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	584	verboselog(machine(), 2, "GBA IO Register Read: BG1HOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
587	585	}
588	586	if( (mem_mask) & 0xffff0000 )
589	587	{
590		verboselog(machine, 2, "GBA IO Register Read: BG1VOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	588	verboselog(machine(), 2, "GBA IO Register Read: BG1VOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
591	589	}
592	590	break;
593	591	case 0x0018/4:
594	592	if( (mem_mask) & 0x0000ffff )
595	593	{
596		verboselog(machine, 2, "GBA IO Register Read: BG2HOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	594	verboselog(machine(), 2, "GBA IO Register Read: BG2HOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
597	595	}
598	596	if( (mem_mask) & 0xffff0000 )
599	597	{
600		verboselog(machine, 2, "GBA IO Register Read: BG2VOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	598	verboselog(machine(), 2, "GBA IO Register Read: BG2VOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
601	599	}
602	600	break;
603	601	case 0x001c/4:
604	602	if( (mem_mask) & 0x0000ffff )
605	603	{
606		verboselog(machine, 2, "GBA IO Register Read: BG3HOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	604	verboselog(machine(), 2, "GBA IO Register Read: BG3HOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
607	605	}
608	606	if( (mem_mask) & 0xffff0000 )
609	607	{
610		verboselog(machine, 2, "GBA IO Register Read: BG3VOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	608	verboselog(machine(), 2, "GBA IO Register Read: BG3VOFS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
611	609	}
612	610	break;
613	611	case 0x0020/4:
614	612	if( (mem_mask) & 0x0000ffff )
615	613	{
616		verboselog(machine, 2, "GBA IO Register Read: BG2PA (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	614	verboselog(machine(), 2, "GBA IO Register Read: BG2PA (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
617	615	}
618	616	if( (mem_mask) & 0xffff0000 )
619	617	{
620		verboselog(machine, 2, "GBA IO Register Read: BG2PB (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	618	verboselog(machine(), 2, "GBA IO Register Read: BG2PB (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
621	619	}
622	620	break;
623	621	case 0x0024/4:
624	622	if( (mem_mask) & 0x0000ffff )
625	623	{
626		verboselog(machine, 2, "GBA IO Register Read: BG2PC (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	624	verboselog(machine(), 2, "GBA IO Register Read: BG2PC (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
627	625	}
628	626	if( (mem_mask) & 0xffff0000 )
629	627	{
630		verboselog(machine, 2, "GBA IO Register Read: BG2PD (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	628	verboselog(machine(), 2, "GBA IO Register Read: BG2PD (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
631	629	}
632	630	break;
633	631	case 0x0028/4:
634	632	if( (mem_mask) & 0x0000ffff )
635	633	{
636		verboselog(machine, 2, "GBA IO Register Read: BG2X_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	634	verboselog(machine(), 2, "GBA IO Register Read: BG2X_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
637	635	}
638	636	if( (mem_mask) & 0xffff0000 )
639	637	{
640		verboselog(machine, 2, "GBA IO Register Read: BG2X_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	638	verboselog(machine(), 2, "GBA IO Register Read: BG2X_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
641	639	}
642	640	break;
643	641	case 0x002c/4:
644	642	if( (mem_mask) & 0x0000ffff )
645	643	{
646		verboselog(machine, 2, "GBA IO Register Read: BG2Y_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	644	verboselog(machine(), 2, "GBA IO Register Read: BG2Y_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
647	645	}
648	646	if( (mem_mask) & 0xffff0000 )
649	647	{
650		verboselog(machine, 2, "GBA IO Register Read: BG2Y_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	648	verboselog(machine(), 2, "GBA IO Register Read: BG2Y_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
651	649	}
652	650	break;
653	651	case 0x0030/4:
654	652	if( (mem_mask) & 0x0000ffff )
655	653	{
656		verboselog(machine, 2, "GBA IO Register Read: BG3PA (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	654	verboselog(machine(), 2, "GBA IO Register Read: BG3PA (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
657	655	}
658	656	if( (mem_mask) & 0xffff0000 )
659	657	{
660		verboselog(machine, 2, "GBA IO Register Read: BG3PB (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	658	verboselog(machine(), 2, "GBA IO Register Read: BG3PB (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
661	659	}
662	660	break;
663	661	case 0x0034/4:
664	662	if( (mem_mask) & 0x0000ffff )
665	663	{
666		verboselog(machine, 2, "GBA IO Register Read: BG3PC (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	664	verboselog(machine(), 2, "GBA IO Register Read: BG3PC (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
667	665	}
668	666	if( (mem_mask) & 0xffff0000 )
669	667	{
670		verboselog(machine, 2, "GBA IO Register Read: BG3PD (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	668	verboselog(machine(), 2, "GBA IO Register Read: BG3PD (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
671	669	}
672	670	break;
673	671	case 0x0038/4:
674	672	if( (mem_mask) & 0x0000ffff )
675	673	{
676		verboselog(machine, 2, "GBA IO Register Read: BG3X_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	674	verboselog(machine(), 2, "GBA IO Register Read: BG3X_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
677	675	}
678	676	if( (mem_mask) & 0xffff0000 )
679	677	{
680		verboselog(machine, 2, "GBA IO Register Read: BG3X_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	678	verboselog(machine(), 2, "GBA IO Register Read: BG3X_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
681	679	}
682	680	break;
683	681	case 0x003c/4:
684	682	if( (mem_mask) & 0x0000ffff )
685	683	{
686		verboselog(machine, 2, "GBA IO Register Read: BG3Y_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	684	verboselog(machine(), 2, "GBA IO Register Read: BG3Y_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
687	685	}
688	686	if( (mem_mask) & 0xffff0000 )
689	687	{
690		verboselog(machine, 2, "GBA IO Register Read: BG3Y_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	688	verboselog(machine(), 2, "GBA IO Register Read: BG3Y_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
691	689	}
692	690	break;
693	691	case 0x0040/4:
694	692	if( (mem_mask) & 0x0000ffff )
695	693	{
696		verboselog(machine, 2, "GBA IO Register Read: WIN0H (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	694	verboselog(machine(), 2, "GBA IO Register Read: WIN0H (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
697	695	}
698	696	if( (mem_mask) & 0xffff0000 )
699	697	{
700		verboselog(machine, 2, "GBA IO Register Read: WIN1H (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	698	verboselog(machine(), 2, "GBA IO Register Read: WIN1H (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
701	699	}
702	700	break;
703	701	case 0x0044/4:
704	702	if( (mem_mask) & 0x0000ffff )
705	703	{
706		verboselog(machine, 2, "GBA IO Register Read: WIN0V (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	704	verboselog(machine(), 2, "GBA IO Register Read: WIN0V (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
707	705	}
708	706	if( (mem_mask) & 0xffff0000 )
709	707	{
710		verboselog(machine, 2, "GBA IO Register Read: WIN1V (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	708	verboselog(machine(), 2, "GBA IO Register Read: WIN1V (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
711	709	}
712	710	break;
713	711	case 0x0048/4:
714	712	if( (mem_mask) & 0x0000ffff )
715	713	{
716		verboselog(machine, 2, "GBA IO Register Read: WININ (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_WININ );
717		retval |= state->m_WININ;
	714	verboselog(machine(), 2, "GBA IO Register Read: WININ (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_WININ );
	715	retval |= m_WININ;
718	716	}
719	717	if( (mem_mask) & 0xffff0000 )
720	718	{
721		verboselog(machine, 2, "GBA IO Register Read: WINOUT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_WINOUT );
722		retval |= state->m_WINOUT << 16;
	719	verboselog(machine(), 2, "GBA IO Register Read: WINOUT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_WINOUT );
	720	retval |= m_WINOUT << 16;
723	721	}
724	722	break;
725	723	case 0x004c/4:
726	724	if( (mem_mask) & 0x0000ffff )
727	725	{
728		verboselog(machine, 2, "GBA IO Register Read: MOSAIC (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	726	verboselog(machine(), 2, "GBA IO Register Read: MOSAIC (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
729	727	}
730	728	if( (mem_mask) & 0xffff0000 )
731	729	{
732		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	730	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
733	731	}
734	732	break;
735	733	case 0x0050/4:
736	734	if( (mem_mask) & 0x0000ffff )
737	735	{
738		verboselog(machine, 2, "GBA IO Register Read: BLDCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_BLDCNT );
739		retval |= state->m_BLDCNT;
	736	verboselog(machine(), 2, "GBA IO Register Read: BLDCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_BLDCNT );
	737	retval |= m_BLDCNT;
740	738	}
741	739	if( (mem_mask) & 0xffff0000 )
742	740	{
743		verboselog(machine, 2, "GBA IO Register Read: BLDALPHA (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_BLDALPHA );
744		retval |= state->m_BLDALPHA << 16;
	741	verboselog(machine(), 2, "GBA IO Register Read: BLDALPHA (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_BLDALPHA );
	742	retval |= m_BLDALPHA << 16;
745	743	}
746	744	break;
747	745	case 0x0054/4:
748	746	if( (mem_mask) & 0x0000ffff )
749	747	{
750		verboselog(machine, 2, "GBA IO Register Read: BLDY (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	748	verboselog(machine(), 2, "GBA IO Register Read: BLDY (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
751	749	}
752	750	if( (mem_mask) & 0xffff0000 )
753	751	{
754		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	752	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
755	753	}
756	754	break;
757	755	case 0x0058/4:
758	756	if( (mem_mask) & 0x0000ffff )
759	757	{
760		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	758	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
761	759	}
762	760	if( (mem_mask) & 0xffff0000 )
763	761	{
764		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	762	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
765	763	}
766	764	break;
767	765	case 0x005c/4:
768	766	if( (mem_mask) & 0x0000ffff )
769	767	{
770		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
	768	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), 0 );
771	769	}
772	770	if( (mem_mask) & 0xffff0000 )
773	771	{
774		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	772	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
775	773	}
776	774	break;
777	775	case 0x0060/4:
r14963	r14964
802	800	retval = gb_sound_r(gb_device, 0x14) | gb_sound_r(gb_device, 0x15)<<8;
803	801	if( (mem_mask) & 0xffff0000 )
804	802	{
805		verboselog(machine, 2, "GBA IO Register Read: SOUNDCNT_H (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_SOUNDCNT_H );
806		retval |= state->m_SOUNDCNT_H << 16;
	803	verboselog(machine(), 2, "GBA IO Register Read: SOUNDCNT_H (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_SOUNDCNT_H );
	804	retval |= m_SOUNDCNT_H << 16;
807	805	}
808	806	break;
809	807	case 0x0084/4:
r14963	r14964
812	810	case 0x0088/4:
813	811	if( (mem_mask) & 0x0000ffff )
814	812	{
815		verboselog(machine, 2, "GBA IO Register Read: SOUNDBIAS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_SOUNDBIAS );
816		retval |= state->m_SOUNDBIAS;
	813	verboselog(machine(), 2, "GBA IO Register Read: SOUNDBIAS (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_SOUNDBIAS );
	814	retval |= m_SOUNDBIAS;
817	815	}
818	816	if( (mem_mask) & 0xffff0000 )
819	817	{
820		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	818	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
821	819	}
822	820	break;
823	821	case 0x0090/4:
r14963	r14964
854	852	#if 0
855	853	if (((offset-0xb0/4) % 3) == 2)
856	854	{
857		return state->m_dma_regs[offset-(0xb0/4)] & 0xff000000;
	855	return m_dma_regs[offset-(0xb0/4)] & 0xff000000;
858	856	}
859	857	#endif
860	858
861		return state->m_dma_regs[offset-(0xb0/4)];
	859	return m_dma_regs[offset-(0xb0/4)];
862	860	}
863	861	break;
864	862	case 0x0100/4:
r14963	r14964
870	868	double time, ticks;
871	869	int timer = offset-(0x100/4);
872	870
873		//              printf("Read timer reg %x (PC=%x)\n", timer, cpu_get_pc(&space->device()));
	871	//              printf("Read timer reg %x (PC=%x)\n", timer, cpu_get_pc(&space.device()));
874	872
875	873	// update times for
876		if (state->m_timer_regs[timer] & 0x800000)
	874	if (m_timer_regs[timer] & 0x800000)
877	875	{
878		if (state->m_timer_regs[timer] & 0x00040000)
	876	if (m_timer_regs[timer] & 0x00040000)
879	877	{
880		elapsed = state->m_timer_regs[timer] & 0xffff;
	878	elapsed = m_timer_regs[timer] & 0xffff;
881	879	}
882	880	else
883	881	{
884	882
885		time = state->m_tmr_timer[timer]->elapsed().as_double();
	883	time = m_tmr_timer[timer]->elapsed().as_double();
886	884
887		ticks = (double)(0x10000 - (state->m_timer_regs[timer] & 0xffff));
	885	ticks = (double)(0x10000 - (m_timer_regs[timer] & 0xffff));
888	886
889		//                  printf("time %f ticks %f 1/hz %f\n", time, ticks, 1.0 / state->m_timer_hz[timer]);
	887	//                  printf("time %f ticks %f 1/hz %f\n", time, ticks, 1.0 / m_timer_hz[timer]);
890	888
891	889	time *= ticks;
892		time /= (1.0 / state->m_timer_hz[timer]);
	890	time /= (1.0 / m_timer_hz[timer]);
893	891
894	892	elapsed = (UINT32)time;
895	893
r14963	r14964
903	901	elapsed = 0;
904	902	}
905	903
906		return (state->m_timer_regs[timer] & 0xffff0000) | (elapsed & 0xffff);
	904	return (m_timer_regs[timer] & 0xffff0000) | (elapsed & 0xffff);
907	905	}
908	906	break;
909	907	case 0x0120/4:
910	908	if( (mem_mask) & 0x0000ffff )
911	909	{
912		verboselog(machine, 2, "GBA IO Register Read: SIOMULTI0 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_SIOMULTI0 );
913		retval |= state->m_SIOMULTI0;
	910	verboselog(machine(), 2, "GBA IO Register Read: SIOMULTI0 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_SIOMULTI0 );
	911	retval |= m_SIOMULTI0;
914	912	}
915	913	if( (mem_mask) & 0xffff0000 )
916	914	{
917		verboselog(machine, 2, "GBA IO Register Read: SIOMULTI1 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_SIOMULTI1 );
918		retval |= state->m_SIOMULTI1 << 16;
	915	verboselog(machine(), 2, "GBA IO Register Read: SIOMULTI1 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_SIOMULTI1 );
	916	retval |= m_SIOMULTI1 << 16;
919	917	}
920	918	break;
921	919	case 0x0124/4:
922	920	if( (mem_mask) & 0x0000ffff )
923	921	{
924		verboselog(machine, 2, "GBA IO Register Read: SIOMULTI2 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_SIOMULTI2 );
925		retval |= state->m_SIOMULTI2;
	922	verboselog(machine(), 2, "GBA IO Register Read: SIOMULTI2 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_SIOMULTI2 );
	923	retval |= m_SIOMULTI2;
926	924	}
927	925	if( (mem_mask) & 0xffff0000 )
928	926	{
929		verboselog(machine, 2, "GBA IO Register Read: SIOMULTI3 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_SIOMULTI3 );
930		retval |= state->m_SIOMULTI3 << 16;
	927	verboselog(machine(), 2, "GBA IO Register Read: SIOMULTI3 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_SIOMULTI3 );
	928	retval |= m_SIOMULTI3 << 16;
931	929	}
932	930	break;
933	931	case 0x0128/4:
934	932	if( (mem_mask) & 0x0000ffff )
935	933	{
936		verboselog(machine, 2, "GBA IO Register Read: SIOCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_SIOCNT );
937		retval |= state->m_SIOCNT;
	934	verboselog(machine(), 2, "GBA IO Register Read: SIOCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_SIOCNT );
	935	retval |= m_SIOCNT;
938	936	}
939	937	if( (mem_mask) & 0xffff0000 )
940	938	{
941		verboselog(machine, 2, "GBA IO Register Read: SIODATA8 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_SIODATA8 );
942		retval |= state->m_SIODATA8 << 16;
	939	verboselog(machine(), 2, "GBA IO Register Read: SIODATA8 (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_SIODATA8 );
	940	retval |= m_SIODATA8 << 16;
943	941	}
944	942	break;
945	943	case 0x0130/4:
946	944	if( (mem_mask) & 0x0000ffff )   // KEYINPUT
947	945	{
948		return input_port_read(machine, "IN0");
	946	return input_port_read(machine(), "IN0");
949	947	}
950	948	if( (mem_mask) & 0xffff0000 )
951	949	{
952		verboselog(machine, 2, "GBA IO Register Read: KEYCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_KEYCNT );
953		retval |= state->m_KEYCNT << 16;
	950	verboselog(machine(), 2, "GBA IO Register Read: KEYCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_KEYCNT );
	951	retval |= m_KEYCNT << 16;
954	952	}
955	953	break;
956	954	case 0x0134/4:
957	955	if( (mem_mask) & 0x0000ffff )
958	956	{
959		verboselog(machine, 2, "GBA IO Register Read: RCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_RCNT );
960		retval |= state->m_RCNT;
	957	verboselog(machine(), 2, "GBA IO Register Read: RCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_RCNT );
	958	retval |= m_RCNT;
961	959	}
962	960	if( (mem_mask) & 0xffff0000 )
963	961	{
964		verboselog(machine, 2, "GBA IO Register Read: IR (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	962	verboselog(machine(), 2, "GBA IO Register Read: IR (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
965	963	}
966	964	break;
967	965	case 0x0140/4:
968	966	if( (mem_mask) & 0x0000ffff )
969	967	{
970		verboselog(machine, 2, "GBA IO Register Read: JOYCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_JOYCNT );
971		retval |= state->m_JOYCNT;
	968	verboselog(machine(), 2, "GBA IO Register Read: JOYCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_JOYCNT );
	969	retval |= m_JOYCNT;
972	970	}
973	971	if( (mem_mask) & 0xffff0000 )
974	972	{
975		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	973	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
976	974	}
977	975	break;
978	976	case 0x0150/4:
979	977	if( (mem_mask) & 0x0000ffff )
980	978	{
981		verboselog(machine, 2, "GBA IO Register Read: JOY_RECV_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_JOY_RECV & 0x0000ffff );
982		retval |= state->m_JOY_RECV & 0x0000ffff;
	979	verboselog(machine(), 2, "GBA IO Register Read: JOY_RECV_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_JOY_RECV & 0x0000ffff );
	980	retval |= m_JOY_RECV & 0x0000ffff;
983	981	}
984	982	if( (mem_mask) & 0xffff0000 )
985	983	{
986		verboselog(machine, 2, "GBA IO Register Read: JOY_RECV_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, ( state->m_JOY_RECV & 0xffff0000 ) >> 16 );
987		retval |= state->m_JOY_RECV & 0xffff0000;
	984	verboselog(machine(), 2, "GBA IO Register Read: JOY_RECV_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, ( m_JOY_RECV & 0xffff0000 ) >> 16 );
	985	retval |= m_JOY_RECV & 0xffff0000;
988	986	}
989	987	break;
990	988	case 0x0154/4:
991	989	if( (mem_mask) & 0x0000ffff )
992	990	{
993		verboselog(machine, 2, "GBA IO Register Read: JOY_TRANS_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_JOY_TRANS & 0x0000ffff );
994		retval |= state->m_JOY_TRANS & 0x0000ffff;
	991	verboselog(machine(), 2, "GBA IO Register Read: JOY_TRANS_LSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_JOY_TRANS & 0x0000ffff );
	992	retval |= m_JOY_TRANS & 0x0000ffff;
995	993	}
996	994	if( (mem_mask) & 0xffff0000 )
997	995	{
998		verboselog(machine, 2, "GBA IO Register Read: JOY_TRANS_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, ( state->m_JOY_TRANS & 0xffff0000 ) >> 16 );
999		retval |= state->m_JOY_TRANS & 0xffff0000;
	996	verboselog(machine(), 2, "GBA IO Register Read: JOY_TRANS_MSW (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, ( m_JOY_TRANS & 0xffff0000 ) >> 16 );
	997	retval |= m_JOY_TRANS & 0xffff0000;
1000	998	}
1001	999	break;
1002	1000	case 0x0158/4:
1003	1001	if( (mem_mask) & 0x0000ffff )
1004	1002	{
1005		verboselog(machine, 2, "GBA IO Register Read: JOYSTAT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_JOYSTAT );
1006		retval |= state->m_JOYSTAT;
	1003	verboselog(machine(), 2, "GBA IO Register Read: JOYSTAT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_JOYSTAT );
	1004	retval |= m_JOYSTAT;
1007	1005	}
1008	1006	if( (mem_mask) & 0xffff0000 )
1009	1007	{
1010		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	1008	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
1011	1009	}
1012	1010	break;
1013	1011	case 0x0200/4:
1014	1012	if( (mem_mask) & 0x0000ffff )
1015	1013	{
1016		//              printf("Read: IE (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_IE );
	1014	//              printf("Read: IE (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_IE );
1017	1015	}
1018	1016	if( (mem_mask) & 0xffff0000 )
1019	1017	{
1020		verboselog(machine, 2, "GBA IO Register Read: IF (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, state->m_IF );
	1018	verboselog(machine(), 2, "GBA IO Register Read: IF (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, m_IF );
1021	1019	}
1022	1020
1023		retval = state->m_IE | (state->m_IF<<16);
	1021	retval = m_IE | (m_IF<<16);
1024	1022	break;
1025	1023	case 0x0204/4:
1026	1024	if( (mem_mask) & 0x0000ffff )
1027	1025	{
1028		verboselog(machine, 2, "GBA IO Register Read: WAITCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_WAITCNT );
1029		retval |= state->m_WAITCNT;
	1026	verboselog(machine(), 2, "GBA IO Register Read: WAITCNT (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_WAITCNT );
	1027	retval |= m_WAITCNT;
1030	1028	}
1031	1029	if( (mem_mask) & 0xffff0000 )
1032	1030	{
1033		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	1031	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
1034	1032	}
1035	1033	break;
1036	1034	case 0x0208/4:
1037	1035	if( (mem_mask) & 0x0000ffff )
1038	1036	{
1039		verboselog(machine, 2, "GBA IO Register Read: IME (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), state->m_IME );
1040		retval |= state->m_IME;
	1037	verboselog(machine(), 2, "GBA IO Register Read: IME (%08x) = %04x\n", 0x04000000 + ( offset << 2 ), m_IME );
	1038	retval |= m_IME;
1041	1039	}
1042	1040	if( (mem_mask) & 0xffff0000 )
1043	1041	{
1044		verboselog(machine, 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
	1042	verboselog(machine(), 2, "GBA IO Register Read: UNKNOWN (%08x) = %04x\n", 0x04000000 + ( offset << 2 ) + 2, 0 );
1045	1043	}
1046	1044	break;
1047	1045	case 0x0300/4:
1048		retval = state->m_HALTCNT << 8;
	1046	retval = m_HALTCNT << 8;
1049	1047	break;
1050	1048	default:
1051		//          verboselog(machine, 0, "Unknown GBA I/O register Read: %08x (%08x)\n", 0x04000000 + ( offset << 2 ), ~mem_mask );
	1049	//          verboselog(machine(), 0, "Unknown GBA I/O register Read: %08x (%08x)\n", 0x04000000 + ( offset << 2 ), ~mem_mask );
1052	1050	break;
1053	1051	}
1054	1052	return retval;
1055	1053	}
1056	1054
1057		static WRITE32_HANDLER( gba_io_w )
	1055	WRITE32_MEMBER(gba_state::gba_io_w)
1058	1056	{
1059		running_machine &machine = space->machine();
1060		device_t *gb_device = space->machine().device("custom");
1061		gba_state *state = machine.driver_data<gba_state>();
1062
	1057	device_t *gb_device = machine().device("custom");
1063	1058	switch( offset )
1064	1059	{
1065	1060	case 0x0000/4:
1066	1061	if( (mem_mask) & 0x0000ffff )
1067	1062	{
1068		verboselog(machine, 2, "GBA IO Register Write: DISPCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1069		state->m_DISPCNT = ( state->m_DISPCNT & ~mem_mask ) | ( data & mem_mask );
1070		if(state->m_DISPCNT & (DISPCNT_WIN0_EN | DISPCNT_WIN1_EN))
	1063	verboselog(machine(), 2, "GBA IO Register Write: DISPCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1064	m_DISPCNT = ( m_DISPCNT & ~mem_mask ) | ( data & mem_mask );
	1065	if(m_DISPCNT & (DISPCNT_WIN0_EN | DISPCNT_WIN1_EN))
1071	1066	{
1072		state->m_windowOn = 1;
	1067	m_windowOn = 1;
1073	1068	}
1074	1069	else
1075	1070	{
1076		state->m_windowOn = 0;
	1071	m_windowOn = 0;
1077	1072	}
1078	1073	}
1079	1074	if( (mem_mask) & 0xffff0000 )
1080	1075	{
1081		verboselog(machine, 2, "GBA IO Register Write: Green Swap (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1082		state->m_GRNSWAP = ( state->m_GRNSWAP & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1076	verboselog(machine(), 2, "GBA IO Register Write: Green Swap (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1077	m_GRNSWAP = ( m_GRNSWAP & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1083	1078	}
1084	1079	break;
1085	1080	case 0x0004/4:
1086		COMBINE_DATA(&state->m_DISPSTAT);
	1081	COMBINE_DATA(&m_DISPSTAT);
1087	1082	break;
1088	1083	case 0x0008/4:
1089	1084	if( (mem_mask) & 0x0000ffff )
1090	1085	{
1091		verboselog(machine, 2, "GBA IO Register Write: BG0CNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1092		state->m_BG0CNT = ( state->m_BG0CNT & ~mem_mask ) | ( data & mem_mask );
	1086	verboselog(machine(), 2, "GBA IO Register Write: BG0CNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1087	m_BG0CNT = ( m_BG0CNT & ~mem_mask ) | ( data & mem_mask );
1093	1088	}
1094	1089	if( (mem_mask) & 0xffff0000 )
1095	1090	{
1096		verboselog(machine, 2, "GBA IO Register Write: BG1CNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1097		state->m_BG1CNT = ( state->m_BG1CNT & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1091	verboselog(machine(), 2, "GBA IO Register Write: BG1CNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1092	m_BG1CNT = ( m_BG1CNT & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1098	1093	}
1099	1094	break;
1100	1095	case 0x000c/4:
1101	1096	if( (mem_mask) & 0x0000ffff )
1102	1097	{
1103		verboselog(machine, 2, "GBA IO Register Write: BG2CNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1104		state->m_BG2CNT = ( state->m_BG2CNT & ~mem_mask ) | ( data & mem_mask );
	1098	verboselog(machine(), 2, "GBA IO Register Write: BG2CNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1099	m_BG2CNT = ( m_BG2CNT & ~mem_mask ) | ( data & mem_mask );
1105	1100	}
1106	1101	if( (mem_mask) & 0xffff0000 )
1107	1102	{
1108		verboselog(machine, 2, "GBA IO Register Write: BG3CNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1109		state->m_BG3CNT = ( state->m_BG3CNT & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1103	verboselog(machine(), 2, "GBA IO Register Write: BG3CNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1104	m_BG3CNT = ( m_BG3CNT & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1110	1105	}
1111	1106	break;
1112	1107	case 0x0010/4:
1113	1108	if( (mem_mask) & 0x0000ffff )
1114	1109	{
1115		verboselog(machine, 2, "GBA IO Register Write: BG0HOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1116		state->m_BG0HOFS = ( state->m_BG0HOFS & ~mem_mask ) | ( data & mem_mask );
	1110	verboselog(machine(), 2, "GBA IO Register Write: BG0HOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1111	m_BG0HOFS = ( m_BG0HOFS & ~mem_mask ) | ( data & mem_mask );
1117	1112	}
1118	1113	if( (mem_mask) & 0xffff0000 )
1119	1114	{
1120		verboselog(machine, 2, "GBA IO Register Write: BG0VOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1121		state->m_BG0VOFS = ( state->m_BG0VOFS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1115	verboselog(machine(), 2, "GBA IO Register Write: BG0VOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1116	m_BG0VOFS = ( m_BG0VOFS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1122	1117	}
1123	1118	break;
1124	1119	case 0x0014/4:
1125	1120	if( (mem_mask) & 0x0000ffff )
1126	1121	{
1127		verboselog(machine, 2, "GBA IO Register Write: BG1HOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1128		state->m_BG1HOFS = ( state->m_BG1HOFS & ~mem_mask ) | ( data & mem_mask );
	1122	verboselog(machine(), 2, "GBA IO Register Write: BG1HOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1123	m_BG1HOFS = ( m_BG1HOFS & ~mem_mask ) | ( data & mem_mask );
1129	1124	}
1130	1125	if( (mem_mask) & 0xffff0000 )
1131	1126	{
1132		verboselog(machine, 2, "GBA IO Register Write: BG1VOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1133		state->m_BG1VOFS = ( state->m_BG1VOFS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1127	verboselog(machine(), 2, "GBA IO Register Write: BG1VOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1128	m_BG1VOFS = ( m_BG1VOFS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1134	1129	}
1135	1130	break;
1136	1131	case 0x0018/4:
1137	1132	if( (mem_mask) & 0x0000ffff )
1138	1133	{
1139		verboselog(machine, 2, "GBA IO Register Write: BG2HOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1140		state->m_BG2HOFS = ( state->m_BG2HOFS & ~mem_mask ) | ( data & mem_mask );
	1134	verboselog(machine(), 2, "GBA IO Register Write: BG2HOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1135	m_BG2HOFS = ( m_BG2HOFS & ~mem_mask ) | ( data & mem_mask );
1141	1136	}
1142	1137	if( (mem_mask) & 0xffff0000 )
1143	1138	{
1144		verboselog(machine, 2, "GBA IO Register Write: BG2VOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1145		state->m_BG2VOFS = ( state->m_BG2VOFS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1139	verboselog(machine(), 2, "GBA IO Register Write: BG2VOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1140	m_BG2VOFS = ( m_BG2VOFS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1146	1141	}
1147	1142	break;
1148	1143	case 0x001c/4:
1149	1144	if( (mem_mask) & 0x0000ffff )
1150	1145	{
1151		verboselog(machine, 2, "GBA IO Register Write: BG3HOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1152		state->m_BG3HOFS = ( state->m_BG3HOFS & ~mem_mask ) | ( data & mem_mask );
	1146	verboselog(machine(), 2, "GBA IO Register Write: BG3HOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1147	m_BG3HOFS = ( m_BG3HOFS & ~mem_mask ) | ( data & mem_mask );
1153	1148	}
1154	1149	if( (mem_mask) & 0xffff0000 )
1155	1150	{
1156		verboselog(machine, 2, "GBA IO Register Write: BG3VOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1157		state->m_BG3VOFS = ( state->m_BG3VOFS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1151	verboselog(machine(), 2, "GBA IO Register Write: BG3VOFS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1152	m_BG3VOFS = ( m_BG3VOFS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1158	1153	}
1159	1154	break;
1160	1155	case 0x0020/4:
1161	1156	if( (mem_mask) & 0x0000ffff )
1162	1157	{
1163		verboselog(machine, 2, "GBA IO Register Write: BG2PA (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1164		state->m_BG2PA = ( state->m_BG2PA & ~mem_mask ) | ( data & mem_mask );
	1158	verboselog(machine(), 2, "GBA IO Register Write: BG2PA (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1159	m_BG2PA = ( m_BG2PA & ~mem_mask ) | ( data & mem_mask );
1165	1160	}
1166	1161	if( (mem_mask) & 0xffff0000 )
1167	1162	{
1168		verboselog(machine, 2, "GBA IO Register Write: BG2PB (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1169		state->m_BG2PB = ( state->m_BG2PB & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1163	verboselog(machine(), 2, "GBA IO Register Write: BG2PB (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1164	m_BG2PB = ( m_BG2PB & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1170	1165	}
1171	1166	break;
1172	1167	case 0x0024/4:
1173	1168	if( (mem_mask) & 0x0000ffff )
1174	1169	{
1175		verboselog(machine, 2, "GBA IO Register Write: BG2PC (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1176		state->m_BG2PC = ( state->m_BG2PC & ~mem_mask ) | ( data & mem_mask );
	1170	verboselog(machine(), 2, "GBA IO Register Write: BG2PC (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1171	m_BG2PC = ( m_BG2PC & ~mem_mask ) | ( data & mem_mask );
1177	1172	}
1178	1173	if( (mem_mask) & 0xffff0000 )
1179	1174	{
1180		verboselog(machine, 2, "GBA IO Register Write: BG2PD (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1181		state->m_BG2PD = ( state->m_BG2PD & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1175	verboselog(machine(), 2, "GBA IO Register Write: BG2PD (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1176	m_BG2PD = ( m_BG2PD & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1182	1177	}
1183	1178	break;
1184	1179	case 0x0028/4:
1185	1180	if( (mem_mask) & 0x0000ffff )
1186	1181	{
1187		verboselog(machine, 2, "GBA IO Register Write: BG2X_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1182	verboselog(machine(), 2, "GBA IO Register Write: BG2X_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1188	1183	}
1189	1184	if( (mem_mask) & 0xffff0000 )
1190	1185	{
1191		verboselog(machine, 2, "GBA IO Register Write: BG2X_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1186	verboselog(machine(), 2, "GBA IO Register Write: BG2X_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1192	1187	}
1193		COMBINE_DATA(&state->m_BG2X);
1194		state->m_gfxBG2Changed |= 1;
	1188	COMBINE_DATA(&m_BG2X);
	1189	m_gfxBG2Changed |= 1;
1195	1190	break;
1196	1191	case 0x002c/4:
1197	1192	if( (mem_mask) & 0x0000ffff )
1198	1193	{
1199		verboselog(machine, 2, "GBA IO Register Write: BG2Y_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1194	verboselog(machine(), 2, "GBA IO Register Write: BG2Y_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1200	1195	}
1201	1196	if( (mem_mask) & 0xffff0000 )
1202	1197	{
1203		verboselog(machine, 2, "GBA IO Register Write: BG2Y_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1198	verboselog(machine(), 2, "GBA IO Register Write: BG2Y_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1204	1199	}
1205		COMBINE_DATA(&state->m_BG2Y);
1206		state->m_gfxBG2Changed |= 2;
	1200	COMBINE_DATA(&m_BG2Y);
	1201	m_gfxBG2Changed |= 2;
1207	1202	break;
1208	1203	case 0x0030/4:
1209	1204	if( (mem_mask) & 0x0000ffff )
1210	1205	{
1211		verboselog(machine, 2, "GBA IO Register Write: BG3PA (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1212		state->m_BG3PA = ( state->m_BG3PA & ~mem_mask ) | ( data & mem_mask );
	1206	verboselog(machine(), 2, "GBA IO Register Write: BG3PA (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1207	m_BG3PA = ( m_BG3PA & ~mem_mask ) | ( data & mem_mask );
1213	1208	}
1214	1209	if( (mem_mask) & 0xffff0000 )
1215	1210	{
1216		verboselog(machine, 2, "GBA IO Register Write: BG3PB (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1217		state->m_BG3PB = ( state->m_BG3PB & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1211	verboselog(machine(), 2, "GBA IO Register Write: BG3PB (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1212	m_BG3PB = ( m_BG3PB & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1218	1213	}
1219	1214	break;
1220	1215	case 0x0034/4:
1221	1216	if( (mem_mask) & 0x0000ffff )
1222	1217	{
1223		verboselog(machine, 2, "GBA IO Register Write: BG3PC (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1224		state->m_BG3PC = ( state->m_BG3PC & ~mem_mask ) | ( data & mem_mask );
	1218	verboselog(machine(), 2, "GBA IO Register Write: BG3PC (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1219	m_BG3PC = ( m_BG3PC & ~mem_mask ) | ( data & mem_mask );
1225	1220	}
1226	1221	if( (mem_mask) & 0xffff0000 )
1227	1222	{
1228		verboselog(machine, 2, "GBA IO Register Write: BG3PD (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1229		state->m_BG3PD = ( state->m_BG3PD & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1223	verboselog(machine(), 2, "GBA IO Register Write: BG3PD (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1224	m_BG3PD = ( m_BG3PD & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1230	1225	}
1231	1226	break;
1232	1227	case 0x0038/4:
1233	1228	if( (mem_mask) & 0x0000ffff )
1234	1229	{
1235		verboselog(machine, 2, "GBA IO Register Write: BG3X_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1230	verboselog(machine(), 2, "GBA IO Register Write: BG3X_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1236	1231	}
1237	1232	if( (mem_mask) & 0xffff0000 )
1238	1233	{
1239		verboselog(machine, 2, "GBA IO Register Write: BG3X_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1234	verboselog(machine(), 2, "GBA IO Register Write: BG3X_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1240	1235	}
1241		COMBINE_DATA(&state->m_BG3X);
1242		state->m_gfxBG3Changed |= 1;
	1236	COMBINE_DATA(&m_BG3X);
	1237	m_gfxBG3Changed |= 1;
1243	1238	break;
1244	1239	case 0x003c/4:
1245	1240	if( (mem_mask) & 0x0000ffff )
1246	1241	{
1247		verboselog(machine, 2, "GBA IO Register Write: BG3Y_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1242	verboselog(machine(), 2, "GBA IO Register Write: BG3Y_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1248	1243	}
1249	1244	if( (mem_mask) & 0xffff0000 )
1250	1245	{
1251		verboselog(machine, 2, "GBA IO Register Write: BG3Y_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1246	verboselog(machine(), 2, "GBA IO Register Write: BG3Y_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1252	1247	}
1253		COMBINE_DATA(&state->m_BG3Y);
1254		state->m_gfxBG3Changed |= 2;
	1248	COMBINE_DATA(&m_BG3Y);
	1249	m_gfxBG3Changed |= 2;
1255	1250	break;
1256	1251	case 0x0040/4:
1257	1252	if( (mem_mask) & 0x0000ffff )
1258	1253	{
1259		verboselog(machine, 2, "GBA IO Register Write: WIN0H (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1260		state->m_WIN0H = ( state->m_WIN0H & ~mem_mask ) | ( data & mem_mask );
	1254	verboselog(machine(), 2, "GBA IO Register Write: WIN0H (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1255	m_WIN0H = ( m_WIN0H & ~mem_mask ) | ( data & mem_mask );
1261	1256	}
1262	1257	if( (mem_mask) & 0xffff0000 )
1263	1258	{
1264		verboselog(machine, 2, "GBA IO Register Write: WIN1H (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1265		state->m_WIN1H = ( state->m_WIN1H & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1259	verboselog(machine(), 2, "GBA IO Register Write: WIN1H (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1260	m_WIN1H = ( m_WIN1H & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1266	1261	}
1267	1262	break;
1268	1263	case 0x0044/4:
1269	1264	if( (mem_mask) & 0x0000ffff )
1270	1265	{
1271		verboselog(machine, 2, "GBA IO Register Write: WIN0V (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1272		state->m_WIN0V = ( state->m_WIN0V & ~mem_mask ) | ( data & mem_mask );
	1266	verboselog(machine(), 2, "GBA IO Register Write: WIN0V (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1267	m_WIN0V = ( m_WIN0V & ~mem_mask ) | ( data & mem_mask );
1273	1268	}
1274	1269	if( (mem_mask) & 0xffff0000 )
1275	1270	{
1276		verboselog(machine, 2, "GBA IO Register Write: WIN1V (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1277		state->m_WIN1V = ( state->m_WIN1V & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1271	verboselog(machine(), 2, "GBA IO Register Write: WIN1V (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1272	m_WIN1V = ( m_WIN1V & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1278	1273	}
1279	1274	break;
1280	1275	case 0x0048/4:
1281	1276	if( (mem_mask) & 0x0000ffff )
1282	1277	{
1283		verboselog(machine, 2, "GBA IO Register Write: WININ (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1284		state->m_WININ = ( state->m_WININ & ~mem_mask ) | ( data & mem_mask );
	1278	verboselog(machine(), 2, "GBA IO Register Write: WININ (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1279	m_WININ = ( m_WININ & ~mem_mask ) | ( data & mem_mask );
1285	1280	}
1286	1281	if( (mem_mask) & 0xffff0000 )
1287	1282	{
1288		verboselog(machine, 2, "GBA IO Register Write: WINOUT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1289		state->m_WINOUT = ( state->m_WINOUT & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1283	verboselog(machine(), 2, "GBA IO Register Write: WINOUT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1284	m_WINOUT = ( m_WINOUT & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1290	1285	}
1291	1286	break;
1292	1287	case 0x004c/4:
1293	1288	if( (mem_mask) & 0x0000ffff )
1294	1289	{
1295		verboselog(machine, 2, "GBA IO Register Write: MOSAIC (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1296		state->m_MOSAIC = ( state->m_MOSAIC & ~mem_mask ) | ( data & mem_mask );
	1290	verboselog(machine(), 2, "GBA IO Register Write: MOSAIC (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1291	m_MOSAIC = ( m_MOSAIC & ~mem_mask ) | ( data & mem_mask );
1297	1292	}
1298	1293	if( (mem_mask) & 0xffff0000 )
1299	1294	{
1300		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1295	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1301	1296	}
1302	1297	break;
1303	1298	case 0x0050/4:
1304	1299	if( (mem_mask) & 0x0000ffff )
1305	1300	{
1306		verboselog(machine, 2, "GBA IO Register Write: BLDCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1307		state->m_BLDCNT = ( state->m_BLDCNT & ~mem_mask ) | ( data & mem_mask );
1308		if(state->m_BLDCNT & BLDCNT_SFX)
	1301	verboselog(machine(), 2, "GBA IO Register Write: BLDCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1302	m_BLDCNT = ( m_BLDCNT & ~mem_mask ) | ( data & mem_mask );
	1303	if(m_BLDCNT & BLDCNT_SFX)
1309	1304	{
1310		state->m_fxOn = 1;
	1305	m_fxOn = 1;
1311	1306	}
1312	1307	else
1313	1308	{
1314		state->m_fxOn = 0;
	1309	m_fxOn = 0;
1315	1310	}
1316	1311	}
1317	1312	if( (mem_mask) & 0xffff0000 )
1318	1313	{
1319		verboselog(machine, 2, "GBA IO Register Write: BLDALPHA (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1320		state->m_BLDALPHA = ( state->m_BLDALPHA & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1314	verboselog(machine(), 2, "GBA IO Register Write: BLDALPHA (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1315	m_BLDALPHA = ( m_BLDALPHA & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1321	1316	}
1322	1317	break;
1323	1318	case 0x0054/4:
1324	1319	if( (mem_mask) & 0x0000ffff )
1325	1320	{
1326		verboselog(machine, 2, "GBA IO Register Write: BLDY (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1327		state->m_BLDY = ( state->m_BLDY & ~mem_mask ) | ( data & mem_mask );
	1321	verboselog(machine(), 2, "GBA IO Register Write: BLDY (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1322	m_BLDY = ( m_BLDY & ~mem_mask ) | ( data & mem_mask );
1328	1323	}
1329	1324	if( (mem_mask) & 0xffff0000 )
1330	1325	{
1331		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1326	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1332	1327	}
1333	1328	break;
1334	1329	case 0x0058/4:
1335	1330	if( (mem_mask) & 0x0000ffff )
1336	1331	{
1337		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1332	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1338	1333	}
1339	1334	if( (mem_mask) & 0xffff0000 )
1340	1335	{
1341		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1336	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1342	1337	}
1343	1338	break;
1344	1339	case 0x005c/4:
1345	1340	if( (mem_mask) & 0x0000ffff )
1346	1341	{
1347		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1342	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1348	1343	}
1349	1344	if( (mem_mask) & 0xffff0000 )
1350	1345	{
1351		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1346	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1352	1347	}
1353	1348	break;
1354	1349	case 0x0060/4:
r14963	r14964
1452	1447	if ((mem_mask) & 0xffff0000)
1453	1448	{
1454	1449	data >>= 16;
1455		state->m_SOUNDCNT_H = data;
	1450	m_SOUNDCNT_H = data;
1456	1451
1457	1452	// DAC A reset?
1458	1453	if (data & 0x0800)
1459	1454	{
1460		device_t *gb_a_l = machine.device("direct_a_left");
1461		device_t *gb_a_r = machine.device("direct_a_right");
	1455	device_t *gb_a_l = machine().device("direct_a_left");
	1456	device_t *gb_a_r = machine().device("direct_a_right");
1462	1457
1463		state->m_fifo_a_ptr = 17;
1464		state->m_fifo_a_in = 17;
	1458	m_fifo_a_ptr = 17;
	1459	m_fifo_a_in = 17;
1465	1460	dac_signed_data_w(gb_a_l, 0x80);
1466	1461	dac_signed_data_w(gb_a_r, 0x80);
1467	1462	}
r14963	r14964
1469	1464	// DAC B reset?
1470	1465	if (data & 0x8000)
1471	1466	{
1472		device_t *gb_b_l = machine.device("direct_b_left");
1473		device_t *gb_b_r = machine.device("direct_b_right");
	1467	device_t *gb_b_l = machine().device("direct_b_left");
	1468	device_t *gb_b_r = machine().device("direct_b_right");
1474	1469
1475		state->m_fifo_b_ptr = 17;
1476		state->m_fifo_b_in = 17;
	1470	m_fifo_b_ptr = 17;
	1471	m_fifo_b_in = 17;
1477	1472	dac_signed_data_w(gb_b_l, 0x80);
1478	1473	dac_signed_data_w(gb_b_r, 0x80);
1479	1474	}
r14963	r14964
1482	1477	case 0x0084/4:
1483	1478	if( (mem_mask) & 0x000000ff )
1484	1479	{
1485		device_t *gb_a_l = machine.device("direct_a_left");
1486		device_t *gb_a_r = machine.device("direct_a_right");
1487		device_t *gb_b_l = machine.device("direct_b_left");
1488		device_t *gb_b_r = machine.device("direct_b_right");
	1480	device_t *gb_a_l = machine().device("direct_a_left");
	1481	device_t *gb_a_r = machine().device("direct_a_right");
	1482	device_t *gb_b_l = machine().device("direct_b_left");
	1483	device_t *gb_b_r = machine().device("direct_b_right");
1489	1484
1490	1485	gb_sound_w(gb_device, 0x16, data);
1491		if ((data & 0x80) && !(state->m_SOUNDCNT_X & 0x80))
	1486	if ((data & 0x80) && !(m_SOUNDCNT_X & 0x80))
1492	1487	{
1493		state->m_fifo_a_ptr = state->m_fifo_a_in = 17;
1494		state->m_fifo_b_ptr = state->m_fifo_b_in = 17;
	1488	m_fifo_a_ptr = m_fifo_a_in = 17;
	1489	m_fifo_b_ptr = m_fifo_b_in = 17;
1495	1490	dac_signed_data_w(gb_a_l, 0x80);
1496	1491	dac_signed_data_w(gb_a_r, 0x80);
1497	1492	dac_signed_data_w(gb_b_l, 0x80);
1498	1493	dac_signed_data_w(gb_b_r, 0x80);
1499	1494	}
1500		state->m_SOUNDCNT_X = data;
	1495	m_SOUNDCNT_X = data;
1501	1496	}
1502	1497	break;
1503	1498	case 0x0088/4:
1504	1499	if( (mem_mask) & 0x0000ffff )
1505	1500	{
1506		verboselog(machine, 2, "GBA IO Register Write: SOUNDBIAS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
1507		state->m_SOUNDBIAS = ( state->m_SOUNDBIAS & ~mem_mask ) | ( data & mem_mask );
	1501	verboselog(machine(), 2, "GBA IO Register Write: SOUNDBIAS (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x0000ffff, ~mem_mask );
	1502	m_SOUNDBIAS = ( m_SOUNDBIAS & ~mem_mask ) | ( data & mem_mask );
1508	1503	}
1509	1504	if( (mem_mask) & 0xffff0000 )
1510	1505	{
1511		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1506	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1512	1507	}
1513	1508	break;
1514	1509	case 0x0090/4:
r14963	r14964
1584	1579	}
1585	1580	break;
1586	1581	case 0x00a0/4:
1587		state->m_fifo_a_in %= 17;
1588		state->m_fifo_a[state->m_fifo_a_in++] = (data)&0xff;
1589		state->m_fifo_a_in %= 17;
1590		state->m_fifo_a[state->m_fifo_a_in++] = (data>>8)&0xff;
1591		state->m_fifo_a_in %= 17;
1592		state->m_fifo_a[state->m_fifo_a_in++] = (data>>16)&0xff;
1593		state->m_fifo_a_in %= 17;
1594		state->m_fifo_a[state->m_fifo_a_in++] = (data>>24)&0xff;
	1582	m_fifo_a_in %= 17;
	1583	m_fifo_a[m_fifo_a_in++] = (data)&0xff;
	1584	m_fifo_a_in %= 17;
	1585	m_fifo_a[m_fifo_a_in++] = (data>>8)&0xff;
	1586	m_fifo_a_in %= 17;
	1587	m_fifo_a[m_fifo_a_in++] = (data>>16)&0xff;
	1588	m_fifo_a_in %= 17;
	1589	m_fifo_a[m_fifo_a_in++] = (data>>24)&0xff;
1595	1590	break;
1596	1591	case 0x00a4/4:
1597		state->m_fifo_b_in %= 17;
1598		state->m_fifo_b[state->m_fifo_b_in++] = (data)&0xff;
1599		state->m_fifo_b_in %= 17;
1600		state->m_fifo_b[state->m_fifo_b_in++] = (data>>8)&0xff;
1601		state->m_fifo_b_in %= 17;
1602		state->m_fifo_b[state->m_fifo_b_in++] = (data>>16)&0xff;
1603		state->m_fifo_b_in %= 17;
1604		state->m_fifo_b[state->m_fifo_b_in++] = (data>>24)&0xff;
	1592	m_fifo_b_in %= 17;
	1593	m_fifo_b[m_fifo_b_in++] = (data)&0xff;
	1594	m_fifo_b_in %= 17;
	1595	m_fifo_b[m_fifo_b_in++] = (data>>8)&0xff;
	1596	m_fifo_b_in %= 17;
	1597	m_fifo_b[m_fifo_b_in++] = (data>>16)&0xff;
	1598	m_fifo_b_in %= 17;
	1599	m_fifo_b[m_fifo_b_in++] = (data>>24)&0xff;
1605	1600	break;
1606	1601	case 0x00b0/4:
1607	1602	case 0x00b4/4:
r14963	r14964
1638	1633
1639	1634	// retrigger/restart on a rising edge.
1640	1635	// also reload internal regs
1641		if ((ctrl & 0x8000) && !(state->m_dma_regs[offset] & 0x80000000))
	1636	if ((ctrl & 0x8000) && !(m_dma_regs[offset] & 0x80000000))
1642	1637	{
1643		state->m_dma_src[ch] = state->m_dma_regs[(ch*3)+0];
1644		state->m_dma_dst[ch] = state->m_dma_regs[(ch*3)+1];
1645		state->m_dma_srcadd[ch] = (ctrl>>7)&3;
1646		state->m_dma_dstadd[ch] = (ctrl>>5)&3;
	1638	m_dma_src[ch] = m_dma_regs[(ch*3)+0];
	1639	m_dma_dst[ch] = m_dma_regs[(ch*3)+1];
	1640	m_dma_srcadd[ch] = (ctrl>>7)&3;
	1641	m_dma_dstadd[ch] = (ctrl>>5)&3;
1647	1642
1648		COMBINE_DATA(&state->m_dma_regs[offset]);
1649		state->m_dma_cnt[ch] = state->m_dma_regs[(ch*3)+2]&0xffff;
	1643	COMBINE_DATA(&m_dma_regs[offset]);
	1644	m_dma_cnt[ch] = m_dma_regs[(ch*3)+2]&0xffff;
1650	1645
1651	1646	// immediate start
1652	1647	if ((ctrl & 0x3000) == 0)
1653	1648	{
1654		dma_exec(machine, ch);
	1649	dma_exec(machine(), ch);
1655	1650	return;
1656	1651	}
1657	1652	}
1658	1653	}
1659	1654
1660		COMBINE_DATA(&state->m_dma_regs[offset]);
	1655	COMBINE_DATA(&m_dma_regs[offset]);
1661	1656	}
1662	1657	break;
1663	1658	case 0x0100/4:
r14963	r14964
1670	1665
1671	1666	offset -= (0x100/4);
1672	1667
1673		old_timer_regs = state->m_timer_regs[offset];
	1668	old_timer_regs = m_timer_regs[offset];
1674	1669
1675		state->m_timer_regs[offset] = (state->m_timer_regs[offset] & ~(mem_mask & 0xFFFF0000)) | (data & (mem_mask & 0xFFFF0000));
	1670	m_timer_regs[offset] = (m_timer_regs[offset] & ~(mem_mask & 0xFFFF0000)) | (data & (mem_mask & 0xFFFF0000));
1676	1671
1677		//              printf("%x to timer %d (mask %x PC %x)\n", data, offset, ~mem_mask, cpu_get_pc(&space->device()));
	1672	//              printf("%x to timer %d (mask %x PC %x)\n", data, offset, ~mem_mask, cpu_get_pc(&space.device()));
1678	1673
1679	1674	if (ACCESSING_BITS_0_15)
1680	1675	{
1681		state->m_timer_reload[offset] = ((state->m_timer_reload[offset] & ~mem_mask) | (data & mem_mask)) & 0x0000FFFF;
1682		state->m_timer_recalc[offset] = 1;
	1676	m_timer_reload[offset] = ((m_timer_reload[offset] & ~mem_mask) | (data & mem_mask)) & 0x0000FFFF;
	1677	m_timer_recalc[offset] = 1;
1683	1678	}
1684	1679
1685	1680	// enabling this timer?
r14963	r14964
1689	1684
1690	1685	if ((old_timer_regs & 0x00800000) == 0) // start bit 0 -> 1
1691	1686	{
1692		state->m_timer_regs[offset] = (state->m_timer_regs[offset] & 0xFFFF0000) | (state->m_timer_reload[offset] & 0x0000FFFF);
	1687	m_timer_regs[offset] = (m_timer_regs[offset] & 0xFFFF0000) | (m_timer_reload[offset] & 0x0000FFFF);
1693	1688	}
1694	1689
1695		rate = 0x10000 - (state->m_timer_regs[offset] & 0xffff);
	1690	rate = 0x10000 - (m_timer_regs[offset] & 0xffff);
1696	1691
1697		clocksel = timer_clks[(state->m_timer_regs[offset] >> 16) & 3];
	1692	clocksel = timer_clks[(m_timer_regs[offset] >> 16) & 3];
1698	1693
1699	1694	final = clocksel / rate;
1700	1695
1701		state->m_timer_hz[offset] = final;
	1696	m_timer_hz[offset] = final;
1702	1697
1703		state->m_timer_recalc[offset] = 0;
	1698	m_timer_recalc[offset] = 0;
1704	1699
1705	1700	//                  printf("Enabling timer %d @ %f Hz\n", offset, final);
1706	1701
r14963	r14964
1709	1704	{
1710	1705	attotime time = attotime::from_hz(final);
1711	1706	GBA_ATTOTIME_NORMALIZE(time);
1712		state->m_tmr_timer[offset]->adjust(time, offset, time);
	1707	m_tmr_timer[offset]->adjust(time, offset, time);
1713	1708	}
1714	1709	}
1715	1710	}
r14963	r14964
1717	1712	case 0x0120/4:
1718	1713	if( (mem_mask) & 0x0000ffff )
1719	1714	{
1720		verboselog(machine, 2, "GBA IO Register Write: SIOMULTI0 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1721		state->m_SIOMULTI0 = ( state->m_SIOMULTI0 & ~mem_mask ) | ( data & mem_mask );
	1715	verboselog(machine(), 2, "GBA IO Register Write: SIOMULTI0 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1716	m_SIOMULTI0 = ( m_SIOMULTI0 & ~mem_mask ) | ( data & mem_mask );
1722	1717	}
1723	1718	if( (mem_mask) & 0xffff0000 )
1724	1719	{
1725		verboselog(machine, 2, "GBA IO Register Write: SIOMULTI1 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1726		state->m_SIOMULTI1 = ( state->m_SIOMULTI1 & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1720	verboselog(machine(), 2, "GBA IO Register Write: SIOMULTI1 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1721	m_SIOMULTI1 = ( m_SIOMULTI1 & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1727	1722	}
1728	1723	break;
1729	1724	case 0x0124/4:
1730	1725	if( (mem_mask) & 0x0000ffff )
1731	1726	{
1732		verboselog(machine, 2, "GBA IO Register Write: SIOMULTI2 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1733		state->m_SIOMULTI2 = ( state->m_SIOMULTI2 & ~mem_mask ) | ( data & mem_mask );
	1727	verboselog(machine(), 2, "GBA IO Register Write: SIOMULTI2 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1728	m_SIOMULTI2 = ( m_SIOMULTI2 & ~mem_mask ) | ( data & mem_mask );
1734	1729	}
1735	1730	if( (mem_mask) & 0xffff0000 )
1736	1731	{
1737		verboselog(machine, 2, "GBA IO Register Write: SIOMULTI3 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1738		state->m_SIOMULTI3 = ( state->m_SIOMULTI3 & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1732	verboselog(machine(), 2, "GBA IO Register Write: SIOMULTI3 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1733	m_SIOMULTI3 = ( m_SIOMULTI3 & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1739	1734	}
1740	1735	break;
1741	1736	case 0x0128/4:
1742	1737	if( (mem_mask) & 0x0000ffff )
1743	1738	{
1744		verboselog(machine, 2, "GBA IO Register Write: SIOCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1739	verboselog(machine(), 2, "GBA IO Register Write: SIOCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1745	1740	// normal mode ?
1746		if (((state->m_RCNT & 0x8000) == 0) && ((data & 0x2000) == 0))
	1741	if (((m_RCNT & 0x8000) == 0) && ((data & 0x2000) == 0))
1747	1742	{
1748	1743	// start ?
1749		if (((state->m_SIOCNT & 0x0080) == 0) && ((data & 0x0080) != 0))
	1744	if (((m_SIOCNT & 0x0080) == 0) && ((data & 0x0080) != 0))
1750	1745	{
1751	1746	data &= ~0x0080;
1752	1747	// request interrupt ?
1753	1748	if (data & 0x4000)
1754	1749	{
1755		gba_request_irq( machine, INT_SIO);
	1750	gba_request_irq( machine(), INT_SIO);
1756	1751	}
1757	1752	}
1758	1753	}
1759		state->m_SIOCNT = ( state->m_SIOCNT & ~mem_mask ) | ( data & mem_mask );
	1754	m_SIOCNT = ( m_SIOCNT & ~mem_mask ) | ( data & mem_mask );
1760	1755	}
1761	1756	if( (mem_mask) & 0xffff0000 )
1762	1757	{
1763		verboselog(machine, 2, "GBA IO Register Write: SIODATA8 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1764		state->m_SIODATA8 = ( state->m_SIODATA8 & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1758	verboselog(machine(), 2, "GBA IO Register Write: SIODATA8 (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1759	m_SIODATA8 = ( m_SIODATA8 & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1765	1760	}
1766	1761	break;
1767	1762	case 0x0130/4:
1768	1763	if( (mem_mask) & 0xffff0000 )
1769	1764	{
1770	1765	//              printf("KEYCNT = %04x\n", data>>16);
1771		verboselog(machine, 2, "GBA IO Register Write: KEYCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1772		state->m_KEYCNT = ( state->m_KEYCNT & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1766	verboselog(machine(), 2, "GBA IO Register Write: KEYCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1767	m_KEYCNT = ( m_KEYCNT & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1773	1768	}
1774	1769	break;
1775	1770	case 0x0134/4:
1776	1771	if( (mem_mask) & 0x0000ffff )
1777	1772	{
1778		verboselog(machine, 2, "GBA IO Register Write: RCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1779		state->m_RCNT = ( state->m_RCNT & ~mem_mask ) | ( data & mem_mask );
	1773	verboselog(machine(), 2, "GBA IO Register Write: RCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1774	m_RCNT = ( m_RCNT & ~mem_mask ) | ( data & mem_mask );
1780	1775	}
1781	1776	if( (mem_mask) & 0xffff0000 )
1782	1777	{
1783		verboselog(machine, 2, "GBA IO Register Write: IR (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1784		state->m_IR = ( state->m_IR & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1778	verboselog(machine(), 2, "GBA IO Register Write: IR (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1779	m_IR = ( m_IR & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1785	1780	}
1786	1781	break;
1787	1782	case 0x0140/4:
1788	1783	if( (mem_mask) & 0x0000ffff )
1789	1784	{
1790		verboselog(machine, 2, "GBA IO Register Write: JOYCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1791		state->m_JOYCNT = ( state->m_JOYCNT & ~mem_mask ) | ( data & mem_mask );
	1785	verboselog(machine(), 2, "GBA IO Register Write: JOYCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1786	m_JOYCNT = ( m_JOYCNT & ~mem_mask ) | ( data & mem_mask );
1792	1787	}
1793	1788	if( (mem_mask) & 0xffff0000 )
1794	1789	{
1795		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1790	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1796	1791	}
1797	1792	break;
1798	1793	case 0x0150/4:
1799	1794	if( (mem_mask) & 0x0000ffff )
1800	1795	{
1801		verboselog(machine, 2, "GBA IO Register Write: JOY_RECV_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1802		state->m_JOY_RECV = ( state->m_JOY_RECV & ~mem_mask ) | ( data & mem_mask );
	1796	verboselog(machine(), 2, "GBA IO Register Write: JOY_RECV_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1797	m_JOY_RECV = ( m_JOY_RECV & ~mem_mask ) | ( data & mem_mask );
1803	1798	}
1804	1799	if( (mem_mask) & 0xffff0000 )
1805	1800	{
1806		verboselog(machine, 2, "GBA IO Register Write: JOY_RECV_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1807		state->m_JOY_RECV = ( state->m_JOY_RECV & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1801	verboselog(machine(), 2, "GBA IO Register Write: JOY_RECV_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1802	m_JOY_RECV = ( m_JOY_RECV & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1808	1803	}
1809	1804	break;
1810	1805	case 0x0154/4:
1811	1806	if( (mem_mask) & 0x0000ffff )
1812	1807	{
1813		verboselog(machine, 2, "GBA IO Register Write: JOY_TRANS_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1814		state->m_JOY_TRANS = ( state->m_JOY_TRANS & ~mem_mask ) | ( data & mem_mask );
	1808	verboselog(machine(), 2, "GBA IO Register Write: JOY_TRANS_LSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1809	m_JOY_TRANS = ( m_JOY_TRANS & ~mem_mask ) | ( data & mem_mask );
1815	1810	}
1816	1811	if( (mem_mask) & 0xffff0000 )
1817	1812	{
1818		verboselog(machine, 2, "GBA IO Register Write: JOY_TRANS_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1819		state->m_JOY_TRANS = ( state->m_JOY_TRANS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
	1813	verboselog(machine(), 2, "GBA IO Register Write: JOY_TRANS_MSW (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1814	m_JOY_TRANS = ( m_JOY_TRANS & ( ~mem_mask >> 16 ) ) | ( ( data & mem_mask ) >> 16 );
1820	1815	}
1821	1816	break;
1822	1817	case 0x0158/4:
1823	1818	if( (mem_mask) & 0x0000ffff )
1824	1819	{
1825		verboselog(machine, 2, "GBA IO Register Write: JOYSTAT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1826		state->m_JOYSTAT = ( state->m_JOYSTAT & ~mem_mask ) | ( data & mem_mask );
	1820	verboselog(machine(), 2, "GBA IO Register Write: JOYSTAT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1821	m_JOYSTAT = ( m_JOYSTAT & ~mem_mask ) | ( data & mem_mask );
1827	1822	}
1828	1823	if( (mem_mask) & 0xffff0000 )
1829	1824	{
1830		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1825	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1831	1826	}
1832	1827	break;
1833	1828	case 0x0200/4:
1834	1829	if( (mem_mask) & 0x0000ffff )
1835	1830	{
1836		//              printf("IE (%08x) = %04x raw %x (%08x) (scan %d PC %x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, data, ~mem_mask, machine.primary_screen->vpos(), cpu_get_pc(&space->device()));
1837		state->m_IE = ( state->m_IE & ~mem_mask ) | ( data & mem_mask );
	1831	//              printf("IE (%08x) = %04x raw %x (%08x) (scan %d PC %x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, data, ~mem_mask, machine.primary_screen->vpos(), cpu_get_pc(&space.device()));
	1832	m_IE = ( m_IE & ~mem_mask ) | ( data & mem_mask );
1838	1833	#if 0
1839		if (state->m_IE & state->m_IF)
	1834	if (m_IE & m_IF)
1840	1835	{
1841		gba_request_irq(machine, state->m_IF);
	1836	gba_request_irq(machine(), m_IF);
1842	1837	}
1843	1838	#endif
1844	1839	}
1845	1840	if( (mem_mask) & 0xffff0000 )
1846	1841	{
1847		verboselog(machine, 2, "GBA IO Register Write: IF (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ) + 2, ( data & mem_mask ) >> 16, ~mem_mask );
1848		state->m_IF &= ~( ( data & mem_mask ) >> 16 );
	1842	verboselog(machine(), 2, "GBA IO Register Write: IF (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ) + 2, ( data & mem_mask ) >> 16, ~mem_mask );
	1843	m_IF &= ~( ( data & mem_mask ) >> 16 );
1849	1844
1850	1845	// if we still have interrupts, yank the IRQ line again
1851		if (state->m_IF)
	1846	if (m_IF)
1852	1847	{
1853		state->m_irq_timer->adjust(machine.device<cpu_device>("maincpu")->clocks_to_attotime(120));
	1848	m_irq_timer->adjust(machine().device<cpu_device>("maincpu")->clocks_to_attotime(120));
1854	1849	}
1855	1850	}
1856	1851	break;
1857	1852	case 0x0204/4:
1858	1853	if( (mem_mask) & 0x0000ffff )
1859	1854	{
1860		verboselog(machine, 2, "GBA IO Register Write: WAITCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1861		state->m_WAITCNT = ( state->m_WAITCNT & ~mem_mask ) | ( data & mem_mask );
	1855	verboselog(machine(), 2, "GBA IO Register Write: WAITCNT (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1856	m_WAITCNT = ( m_WAITCNT & ~mem_mask ) | ( data & mem_mask );
1862	1857	}
1863	1858	if( (mem_mask) & 0xffff0000 )
1864	1859	{
1865		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1860	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1866	1861	}
1867	1862	break;
1868	1863	case 0x0208/4:
1869	1864	if( (mem_mask) & 0x0000ffff )
1870	1865	{
1871		verboselog(machine, 3, "GBA IO Register Write: IME (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
1872		state->m_IME = ( state->m_IME & ~mem_mask ) | ( data & mem_mask );
1873		if (state->m_IF)
	1866	verboselog(machine(), 3, "GBA IO Register Write: IME (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), data & mem_mask, ~mem_mask );
	1867	m_IME = ( m_IME & ~mem_mask ) | ( data & mem_mask );
	1868	if (m_IF)
1874	1869	{
1875		state->m_irq_timer->adjust(attotime::zero);
	1870	m_irq_timer->adjust(attotime::zero);
1876	1871	}
1877	1872	}
1878	1873	if( (mem_mask) & 0xffff0000 )
1879	1874	{
1880		verboselog(machine, 3, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
	1875	verboselog(machine(), 3, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & mem_mask ) >> 16, ~mem_mask );
1881	1876	}
1882	1877	break;
1883	1878	case 0x0300/4:
r14963	r14964
1885	1880	{
1886	1881	if( (mem_mask) & 0x000000ff )
1887	1882	{
1888		verboselog(machine, 2, "GBA IO Register Write: POSTFLG (%08x) = %02x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x000000ff, ~mem_mask );
1889		state->m_POSTFLG = data & 0x000000ff;
	1883	verboselog(machine(), 2, "GBA IO Register Write: POSTFLG (%08x) = %02x (%08x)\n", 0x04000000 + ( offset << 2 ), data & 0x000000ff, ~mem_mask );
	1884	m_POSTFLG = data & 0x000000ff;
1890	1885	}
1891	1886	else
1892	1887	{
1893		state->m_HALTCNT = data & 0x000000ff;
	1888	m_HALTCNT = data & 0x000000ff;
1894	1889
1895	1890	// either way, wait for an IRQ
1896		device_spin_until_interrupt(machine.device("maincpu"));
	1891	device_spin_until_interrupt(machine().device("maincpu"));
1897	1892	}
1898	1893	}
1899	1894	if( (mem_mask) & 0xffff0000 )
1900	1895	{
1901		verboselog(machine, 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
	1896	verboselog(machine(), 2, "GBA IO Register Write: UNKNOWN (%08x) = %04x (%08x)\n", 0x04000000 + ( offset << 2 ), ( data & 0xffff0000 ) >> 16, ~mem_mask );
1902	1897	}
1903	1898	break;
1904	1899	default:
r14963	r14964
1934	1929	return prev;
1935	1930	}
1936	1931
1937		static WRITE32_HANDLER(gba_pram_w)
	1932	WRITE32_MEMBER(gba_state::gba_pram_w)
1938	1933	{
1939		running_machine &machine = space->machine();
1940		gba_state *state = machine.driver_data<gba_state>();
1941
1942		state->m_gba_pram[offset] = COMBINE_DATA32_16(state->m_gba_pram[offset], data, mem_mask);
	1934	m_gba_pram[offset] = COMBINE_DATA32_16(m_gba_pram[offset], data, mem_mask);
1943	1935	}
1944	1936
1945		static WRITE32_HANDLER(gba_vram_w)
	1937	WRITE32_MEMBER(gba_state::gba_vram_w)
1946	1938	{
1947		running_machine &machine = space->machine();
1948		gba_state *state = machine.driver_data<gba_state>();
1949
1950		state->m_gba_vram[offset] = COMBINE_DATA32_16(state->m_gba_vram[offset], data, mem_mask);
	1939	m_gba_vram[offset] = COMBINE_DATA32_16(m_gba_vram[offset], data, mem_mask);
1951	1940	}
1952	1941
1953		static WRITE32_HANDLER(gba_oam_w)
	1942	WRITE32_MEMBER(gba_state::gba_oam_w)
1954	1943	{
1955		running_machine &machine = space->machine();
1956		gba_state *state = machine.driver_data<gba_state>();
1957
1958		state->m_gba_oam[offset] = COMBINE_DATA32_16(state->m_gba_oam[offset], data, mem_mask);
	1944	m_gba_oam[offset] = COMBINE_DATA32_16(m_gba_oam[offset], data, mem_mask);
1959	1945	}
1960	1946
1961		static READ32_HANDLER(gba_bios_r)
	1947	READ32_MEMBER(gba_state::gba_bios_r)
1962	1948	{
1963		running_machine &machine = space->machine();
1964		gba_state *state = machine.driver_data<gba_state>();
1965		UINT32 *rom = (UINT32 *)(*space->machine().region("maincpu"));
1966		if (state->m_bios_protected != 0)
	1949	UINT32 *rom = (UINT32 *)(*machine().region("maincpu"));
	1950	if (m_bios_protected != 0)
1967	1951	{
1968		offset = (state->m_bios_last_address + 8) / 4;
	1952	offset = (m_bios_last_address + 8) / 4;
1969	1953	}
1970	1954	return rom[offset&0x3fff];
1971	1955	}
1972	1956
1973		static READ32_HANDLER(gba_10000000_r)
	1957	READ32_MEMBER(gba_state::gba_10000000_r)
1974	1958	{
1975	1959	UINT32 data, cpsr, pc;
1976		cpu_device *cpu = downcast<cpu_device *>(space->machine().device( "maincpu"));
	1960	cpu_device *cpu = downcast<cpu_device *>(machine().device( "maincpu"));
1977	1961	pc = cpu_get_reg( cpu, ARM7_PC);
1978	1962	cpsr = cpu_get_reg( cpu, ARM7_CPSR);
1979	1963	if (T_IS_SET( cpsr))
1980	1964	{
1981		data = space->read_dword( pc + 8);
	1965	data = space.read_dword( pc + 8);
1982	1966	}
1983	1967	else
1984	1968	{
1985		UINT16 insn = space->read_word( pc + 4);
	1969	UINT16 insn = space.read_word( pc + 4);
1986	1970	data = (insn << 16) | (insn << 0);
1987	1971	}
1988		logerror( "%s: unmapped program memory read from %08X = %08X & %08X\n", space->machine().describe_context( ), 0x10000000 + (offset << 2), data, mem_mask);
	1972	logerror( "%s: unmapped program memory read from %08X = %08X & %08X\n", machine().describe_context( ), 0x10000000 + (offset << 2), data, mem_mask);
1989	1973	return data;
1990	1974	}
1991	1975
1992	1976	static ADDRESS_MAP_START( gbadvance_map, AS_PROGRAM, 32, gba_state )
1993	1977	ADDRESS_MAP_UNMAP_HIGH // for "Fruit Mura no Doubutsu Tachi" and "Classic NES Series"
1994		AM_RANGE(0x00000000, 0x00003fff) AM_ROM AM_READ_LEGACY(gba_bios_r)
	1978	AM_RANGE(0x00000000, 0x00003fff) AM_ROM AM_READ(gba_bios_r)
1995	1979	AM_RANGE(0x02000000, 0x0203ffff) AM_RAM AM_MIRROR(0xfc0000)
1996	1980	AM_RANGE(0x03000000, 0x03007fff) AM_RAM AM_MIRROR(0xff8000)
1997		AM_RANGE(0x04000000, 0x040003ff) AM_READWRITE_LEGACY(gba_io_r, gba_io_w )
1998		AM_RANGE(0x05000000, 0x050003ff) AM_RAM_WRITE_LEGACY(gba_pram_w) AM_SHARE("gba_pram")   // Palette RAM
1999		AM_RANGE(0x06000000, 0x06017fff) AM_RAM_WRITE_LEGACY(gba_vram_w) AM_SHARE("gba_vram")   // VRAM
2000		AM_RANGE(0x07000000, 0x070003ff) AM_RAM_WRITE_LEGACY(gba_oam_w) AM_SHARE("gba_oam")   // OAM
	1981	AM_RANGE(0x04000000, 0x040003ff) AM_READWRITE(gba_io_r, gba_io_w )
	1982	AM_RANGE(0x05000000, 0x050003ff) AM_RAM_WRITE(gba_pram_w) AM_SHARE("gba_pram")   // Palette RAM
	1983	AM_RANGE(0x06000000, 0x06017fff) AM_RAM_WRITE(gba_vram_w) AM_SHARE("gba_vram")   // VRAM
	1984	AM_RANGE(0x07000000, 0x070003ff) AM_RAM_WRITE(gba_oam_w) AM_SHARE("gba_oam")   // OAM
2001	1985	AM_RANGE(0x08000000, 0x09ffffff) AM_ROM AM_REGION("cartridge", 0)   // cartridge ROM (mirror 0)
2002	1986	AM_RANGE(0x0a000000, 0x0bffffff) AM_ROM AM_REGION("cartridge", 0)   // cartridge ROM (mirror 1)
2003	1987	AM_RANGE(0x0c000000, 0x0cffffff) AM_ROM AM_REGION("cartridge", 0)   // final mirror
2004		AM_RANGE(0x10000000, 0xffffffff) AM_READ_LEGACY(gba_10000000_r) // for "Justice League Chronicles" (game bug)
	1988	AM_RANGE(0x10000000, 0xffffffff) AM_READ(gba_10000000_r) // for "Justice League Chronicles" (game bug)
2005	1989	ADDRESS_MAP_END
2006	1990
2007	1991	static INPUT_PORTS_START( gbadv )
r14963	r14964
2233	2217	ROM_REGION( 0x2000000, "cartridge", ROMREGION_ERASEFF )
2234	2218	ROM_END
2235	2219
2236		static READ32_HANDLER( sram_r )
	2220	READ32_MEMBER(gba_state::sram_r)
2237	2221	{
2238		gba_state *state = space->machine().driver_data<gba_state>();
2239	2222
2240		return state->m_gba_sram[offset];
	2223	return m_gba_sram[offset];
2241	2224	}
2242	2225
2243		static WRITE32_HANDLER( sram_w )
	2226	WRITE32_MEMBER(gba_state::sram_w)
2244	2227	{
2245		gba_state *state = space->machine().driver_data<gba_state>();
2246	2228
2247		COMBINE_DATA(&state->m_gba_sram[offset]);
	2229	COMBINE_DATA(&m_gba_sram[offset]);
2248	2230	}
2249	2231
2250		static READ32_HANDLER( flash_r )
	2232	READ32_MEMBER(gba_state::flash_r)
2251	2233	{
2252		gba_state *state = space->machine().driver_data<gba_state>();
2253	2234	UINT32 rv;
2254	2235
2255	2236	rv = 0;
2256		offset &= state->m_flash_mask;
2257		if (mem_mask & 0xff) rv |= state->m_mFlashDev->read(offset*4);
2258		if (mem_mask & 0xff00) rv |= state->m_mFlashDev->read((offset*4)+1)<<8;
2259		if (mem_mask & 0xff0000) rv |= state->m_mFlashDev->read((offset*4)+2)<<16;
2260		if (mem_mask & 0xff000000) rv |= state->m_mFlashDev->read((offset*4)+3)<<24;
	2237	offset &= m_flash_mask;
	2238	if (mem_mask & 0xff) rv |= m_mFlashDev->read(offset*4);
	2239	if (mem_mask & 0xff00) rv |= m_mFlashDev->read((offset*4)+1)<<8;
	2240	if (mem_mask & 0xff0000) rv |= m_mFlashDev->read((offset*4)+2)<<16;
	2241	if (mem_mask & 0xff000000) rv |= m_mFlashDev->read((offset*4)+3)<<24;
2261	2242
2262	2243	return rv;
2263	2244	}
2264	2245
2265		static WRITE32_HANDLER( flash_w )
	2246	WRITE32_MEMBER(gba_state::flash_w)
2266	2247	{
2267		gba_state *state = space->machine().driver_data<gba_state>();
2268	2248
2269		offset &= state->m_flash_mask;
	2249	offset &= m_flash_mask;
2270	2250	switch (mem_mask)
2271	2251	{
2272	2252	case 0xff:
2273		state->m_mFlashDev->write(offset*4, data&0xff);
	2253	m_mFlashDev->write(offset*4, data&0xff);
2274	2254	break;
2275	2255	case 0xff00:
2276		state->m_mFlashDev->write((offset*4)+1, (data>>8)&0xff);
	2256	m_mFlashDev->write((offset*4)+1, (data>>8)&0xff);
2277	2257	break;
2278	2258	case 0xff0000:
2279		state->m_mFlashDev->write((offset*4)+2, (data>>16)&0xff);
	2259	m_mFlashDev->write((offset*4)+2, (data>>16)&0xff);
2280	2260	break;
2281	2261	case 0xff000000:
2282		state->m_mFlashDev->write((offset*4)+3, (data>>24)&0xff);
	2262	m_mFlashDev->write((offset*4)+3, (data>>24)&0xff);
2283	2263	break;
2284	2264	default:
2285	2265	fatalerror("Unknown mem_mask for GBA flash_w %x\n", mem_mask);
r14963	r14964
2287	2267	}
2288	2268	}
2289	2269
2290		static READ32_HANDLER( eeprom_r )
	2270	READ32_MEMBER(gba_state::eeprom_r)
2291	2271	{
2292	2272	UINT32 out;
2293		gba_state *state = space->machine().driver_data<gba_state>();
2294	2273
2295		switch (state->m_eeprom_state)
	2274	switch (m_eeprom_state)
2296	2275	{
2297	2276	case EEP_IDLE:
2298		//          printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %d\n", offset, ~mem_mask, state->m_eeprom_state, activecpu_get_pc(), 1);
	2277	//          printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %d\n", offset, ~mem_mask, m_eeprom_state, activecpu_get_pc(), 1);
2299	2278	return 0x00010001;   // "ready"
2300	2279
2301	2280	case EEP_READFIRST:
2302		state->m_eeprom_count--;
	2281	m_eeprom_count--;
2303	2282
2304		if (!state->m_eeprom_count)
	2283	if (!m_eeprom_count)
2305	2284	{
2306		state->m_eeprom_count = 64;
2307		state->m_eeprom_bits = 0;
2308		state->m_eep_data = 0;
2309		state->m_eeprom_state = EEP_READ;
	2285	m_eeprom_count = 64;
	2286	m_eeprom_bits = 0;
	2287	m_eep_data = 0;
	2288	m_eeprom_state = EEP_READ;
2310	2289	}
2311	2290	break;
2312	2291	case EEP_READ:
2313		if ((state->m_eeprom_bits == 0) && (state->m_eeprom_count))
	2292	if ((m_eeprom_bits == 0) && (m_eeprom_count))
2314	2293	{
2315		if (state->m_eeprom_addr >= sizeof( state->m_gba_eeprom))
	2294	if (m_eeprom_addr >= sizeof( m_gba_eeprom))
2316	2295	{
2317		fatalerror( "eeprom: invalid address (%x)", state->m_eeprom_addr);
	2296	fatalerror( "eeprom: invalid address (%x)", m_eeprom_addr);
2318	2297	}
2319		state->m_eep_data = state->m_gba_eeprom[state->m_eeprom_addr];
2320		//printf("EEPROM read @ %x = %x (%x)\n", state->m_eeprom_addr, state->m_eep_data, (state->m_eep_data & 0x80) ? 1 : 0);
2321		state->m_eeprom_addr++;
2322		state->m_eeprom_bits = 8;
	2298	m_eep_data = m_gba_eeprom[m_eeprom_addr];
	2299	//printf("EEPROM read @ %x = %x (%x)\n", m_eeprom_addr, m_eep_data, (m_eep_data & 0x80) ? 1 : 0);
	2300	m_eeprom_addr++;
	2301	m_eeprom_bits = 8;
2323	2302	}
2324	2303
2325		out = (state->m_eep_data & 0x80) ? 1 : 0;
	2304	out = (m_eep_data & 0x80) ? 1 : 0;
2326	2305	out |= (out<<16);
2327		state->m_eep_data <<= 1;
	2306	m_eep_data <<= 1;
2328	2307
2329		state->m_eeprom_bits--;
2330		state->m_eeprom_count--;
	2308	m_eeprom_bits--;
	2309	m_eeprom_count--;
2331	2310
2332		if (!state->m_eeprom_count)
	2311	if (!m_eeprom_count)
2333	2312	{
2334		state->m_eeprom_state = EEP_IDLE;
	2313	m_eeprom_state = EEP_IDLE;
2335	2314	}
2336	2315
2337	2316	//          printf("out = %08x\n", out);
2338		//          printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %08x\n", offset, ~mem_mask, state->m_eeprom_state, activecpu_get_pc(), out);
	2317	//          printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %08x\n", offset, ~mem_mask, m_eeprom_state, activecpu_get_pc(), out);
2339	2318	return out;
2340	2319	}
2341		//  printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %d\n", offset, ~mem_mask, state->m_eeprom_state, cpu_get_pc(&space->device()), 0);
	2320	//  printf("eeprom_r: @ %x, mask %08x (state %d) (PC=%x) = %d\n", offset, ~mem_mask, m_eeprom_state, cpu_get_pc(&space.device()), 0);
2342	2321	return 0;
2343	2322	}
2344	2323
2345		static WRITE32_HANDLER( eeprom_w )
	2324	WRITE32_MEMBER(gba_state::eeprom_w)
2346	2325	{
2347		gba_state *state = space->machine().driver_data<gba_state>();
2348	2326
2349	2327	if (~mem_mask == 0x0000ffff)
2350	2328	{
2351	2329	data >>= 16;
2352	2330	}
2353	2331
2354		//  printf("eeprom_w: %x @ %x (state %d) (PC=%x)\n", data, offset, state->m_eeprom_state, cpu_get_pc(&space->device()));
	2332	//  printf("eeprom_w: %x @ %x (state %d) (PC=%x)\n", data, offset, m_eeprom_state, cpu_get_pc(&space.device()));
2355	2333
2356		switch (state->m_eeprom_state)
	2334	switch (m_eeprom_state)
2357	2335	{
2358	2336	case EEP_IDLE:
2359	2337	if (data == 1)
2360	2338	{
2361		state->m_eeprom_state++;
	2339	m_eeprom_state++;
2362	2340	}
2363	2341	break;
2364	2342
2365	2343	case EEP_COMMAND:
2366	2344	if (data == 1)
2367	2345	{
2368		state->m_eeprom_command = EEP_READFIRST;
	2346	m_eeprom_command = EEP_READFIRST;
2369	2347	}
2370	2348	else
2371	2349	{
2372		state->m_eeprom_command = EEP_WRITE;
	2350	m_eeprom_command = EEP_WRITE;
2373	2351	}
2374		state->m_eeprom_state = EEP_ADDR;
2375		state->m_eeprom_count = state->m_eeprom_addr_bits;
2376		state->m_eeprom_addr = 0;
	2352	m_eeprom_state = EEP_ADDR;
	2353	m_eeprom_count = m_eeprom_addr_bits;
	2354	m_eeprom_addr = 0;
2377	2355	break;
2378	2356
2379	2357	case EEP_ADDR:
2380		state->m_eeprom_addr <<= 1;
2381		state->m_eeprom_addr |= (data & 1);
2382		state->m_eeprom_count--;
2383		if (!state->m_eeprom_count)
	2358	m_eeprom_addr <<= 1;
	2359	m_eeprom_addr |= (data & 1);
	2360	m_eeprom_count--;
	2361	if (!m_eeprom_count)
2384	2362	{
2385		state->m_eeprom_addr *= 8;   // each address points to 8 bytes
2386		if (state->m_eeprom_command == EEP_READFIRST)
	2363	m_eeprom_addr *= 8;   // each address points to 8 bytes
	2364	if (m_eeprom_command == EEP_READFIRST)
2387	2365	{
2388		state->m_eeprom_state = EEP_AFTERADDR;
	2366	m_eeprom_state = EEP_AFTERADDR;
2389	2367	}
2390	2368	else
2391	2369	{
2392		state->m_eeprom_count = 64;
2393		state->m_eeprom_bits = 8;
2394		state->m_eeprom_state = EEP_WRITE;
2395		state->m_eep_data = 0;
	2370	m_eeprom_count = 64;
	2371	m_eeprom_bits = 8;
	2372	m_eeprom_state = EEP_WRITE;
	2373	m_eep_data = 0;
2396	2374	}
2397	2375	}
2398	2376	break;
2399	2377
2400	2378	case EEP_AFTERADDR:
2401		state->m_eeprom_state = state->m_eeprom_command;
2402		state->m_eeprom_count = 64;
2403		state->m_eeprom_bits = 0;
2404		state->m_eep_data = 0;
2405		if( state->m_eeprom_state == EEP_READFIRST )
	2379	m_eeprom_state = m_eeprom_command;
	2380	m_eeprom_count = 64;
	2381	m_eeprom_bits = 0;
	2382	m_eep_data = 0;
	2383	if( m_eeprom_state == EEP_READFIRST )
2406	2384	{
2407		state->m_eeprom_count = 4;
	2385	m_eeprom_count = 4;
2408	2386	}
2409	2387	break;
2410	2388
2411	2389	case EEP_WRITE:
2412		state->m_eep_data<<= 1;
2413		state->m_eep_data |= (data & 1);
2414		state->m_eeprom_bits--;
2415		state->m_eeprom_count--;
	2390	m_eep_data<<= 1;
	2391	m_eep_data |= (data & 1);
	2392	m_eeprom_bits--;
	2393	m_eeprom_count--;
2416	2394
2417		if (state->m_eeprom_bits == 0)
	2395	if (m_eeprom_bits == 0)
2418	2396	{
2419		mame_printf_verbose("%08x: EEPROM: %02x to %x\n", cpu_get_pc(space->machine().device("maincpu")), state->m_eep_data, state->m_eeprom_addr );
2420		if (state->m_eeprom_addr >= sizeof( state->m_gba_eeprom))
	2397	mame_printf_verbose("%08x: EEPROM: %02x to %x\n", cpu_get_pc(machine().device("maincpu")), m_eep_data, m_eeprom_addr );
	2398	if (m_eeprom_addr >= sizeof( m_gba_eeprom))
2421	2399	{
2422		fatalerror( "eeprom: invalid address (%x)", state->m_eeprom_addr);
	2400	fatalerror( "eeprom: invalid address (%x)", m_eeprom_addr);
2423	2401	}
2424		state->m_gba_eeprom[state->m_eeprom_addr] = state->m_eep_data;
2425		state->m_eeprom_addr++;
2426		state->m_eep_data = 0;
2427		state->m_eeprom_bits = 8;
	2402	m_gba_eeprom[m_eeprom_addr] = m_eep_data;
	2403	m_eeprom_addr++;
	2404	m_eep_data = 0;
	2405	m_eeprom_bits = 8;
2428	2406	}
2429	2407
2430		if (!state->m_eeprom_count)
	2408	if (!m_eeprom_count)
2431	2409	{
2432		state->m_eeprom_state = EEP_AFTERWRITE;
	2410	m_eeprom_state = EEP_AFTERWRITE;
2433	2411	}
2434	2412	break;
2435	2413
2436	2414	case EEP_AFTERWRITE:
2437		state->m_eeprom_state = EEP_IDLE;
	2415	m_eeprom_state = EEP_IDLE;
2438	2416	break;
2439	2417	}
2440	2418	}
r14963	r14964
3085	3063
3086	3064	if (cart_size <= (16 * 1024 * 1024))
3087	3065	{
3088		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xd000000, 0xdffffff, FUNC(eeprom_r));
3089		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xd000000, 0xdffffff, FUNC(eeprom_w));
	3066	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xd000000, 0xdffffff, read32_delegate(FUNC(gba_state::eeprom_r),state));
	3067	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xd000000, 0xdffffff, write32_delegate(FUNC(gba_state::eeprom_w),state));
3090	3068	}
3091	3069	else
3092	3070	{
3093		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xdffff00, 0xdffffff, FUNC(eeprom_r));
3094		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xdffff00, 0xdffffff, FUNC(eeprom_w));
	3071	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xdffff00, 0xdffffff, read32_delegate(FUNC(gba_state::eeprom_r),state));
	3072	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xdffff00, 0xdffffff, write32_delegate(FUNC(gba_state::eeprom_w),state));
3095	3073	}
3096	3074	}
3097	3075
r14963	r14964
3100	3078	state->m_nvptr = (UINT8 *)&state->m_gba_sram;
3101	3079	state->m_nvsize = 0x10000;
3102	3080
3103		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xe000000, 0xe00ffff, FUNC(sram_r));
3104		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xe000000, 0xe00ffff, FUNC(sram_w));
	3081	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xe000000, 0xe00ffff, read32_delegate(FUNC(gba_state::sram_r),state));
	3082	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xe000000, 0xe00ffff, write32_delegate(FUNC(gba_state::sram_w),state));
3105	3083	}
3106	3084
3107	3085	if (chip & GBA_CHIP_FLASH_1M)
r14963	r14964
3111	3089	state->m_flash_size = 0x20000;
3112	3090	state->m_flash_mask = 0x1ffff/4;
3113	3091
3114		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xe000000, 0xe01ffff, FUNC(flash_r));
3115		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xe000000, 0xe01ffff, FUNC(flash_w));
	3092	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xe000000, 0xe01ffff, read32_delegate(FUNC(gba_state::flash_r),state));
	3093	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xe000000, 0xe01ffff, write32_delegate(FUNC(gba_state::flash_w),state));
3116	3094	}
3117	3095
3118	3096	if ((chip & GBA_CHIP_FLASH) || (chip & GBA_CHIP_FLASH_512))
r14963	r14964
3122	3100	state->m_flash_size = 0x10000;
3123	3101	state->m_flash_mask = 0xffff/4;
3124	3102
3125		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xe000000, 0xe00ffff, FUNC(flash_r));
3126		image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xe000000, 0xe00ffff, FUNC(flash_w));
	3103	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xe000000, 0xe00ffff, read32_delegate(FUNC(gba_state::flash_r),state));
	3104	image.device().machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xe000000, 0xe00ffff, write32_delegate(FUNC(gba_state::flash_w),state));
3127	3105	}
3128	3106
3129	3107	if (chip & GBA_CHIP_RTC)

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