src/mess/machine/a2scsi.c
| r14907 | r14908 | |
| 10 | 10 | |
| 11 | 11 | Notes: |
| 12 | 12 | |
| 13 | | PAL U3C: |
| 14 | | I1 = A0 |
| 15 | | I2 = A1 |
| 16 | | I3 = A2 |
| 17 | | I4 = A3 |
| 18 | | I5 = O2 of PAL U3D |
| 19 | | I6 = (logic maze) |
| 20 | | I7 = R/W (also I7 of PAL U3D) |
| 21 | | I8 = PHI0 (via flip flops) |
| 22 | | I9 = RESET |
| 23 | | I10 = GND |
| 13 | C0n0-C0n7 = NCR5380 registers in normal order |
| 14 | C0n9 = DIP switches |
| 15 | C0na = RAM and ROM bank switching |
| 16 | C0nb = reset 5380 |
| 17 | C0ne = into the PAL stuff |
| 24 | 18 | |
| 25 | | O1 = P on flip-flops U6DA/U6DB, I8 on PAL U3D |
| 26 | | O2 = N/C |
| 27 | | O3 = I6 on PAL U3D |
| 28 | | O4 = N/C |
| 29 | | O5 = /CS on NCR 5380 |
| 30 | | O6 = /WR on NCR 5380 |
| 31 | | O7 = /RD on NCR 5380 |
| 32 | | O8 = /DACK on NCR 5380 |
| 33 | | |
| 34 | | PAL U3D: |
| 35 | | I1 = A0-A10 NANDed together (goes low on CFFF access, i.e.) |
| 36 | | I2 = /IOSTB |
| 37 | | I3 = /IOSEL |
| 38 | | I4 = RESET |
| 39 | | I5 = A10 (splits C800 space at C800/CC00) |
| 40 | | I6 = O3 of PAL U3C |
| 41 | | I7 = R/W |
| 42 | | I8 = O1 of PAL U3C |
| 43 | | I9 = DRQ from 5380 |
| 44 | | I10 = Y6 from 74LS138 at U3D (C0n6 access) |
| 45 | | |
| 46 | | O1 = G on 74LS245 main data bus buffer |
| 47 | | O2 = I5 of PAL U3C |
| 48 | | O3 = D to flip-flop at U6DB |
| 49 | | O4 = CLK to flip-flop at U6DA |
| 50 | | O5 = D7 (?) |
| 51 | | O6 = CS1 on RAM |
| 52 | | O7 = EPROM CE |
| 53 | | O8 = EPROM OE |
| 54 | | |
| 55 | 19 | *********************************************************************/ |
| 56 | 20 | |
| 57 | 21 | #include "a2scsi.h" |
| r14907 | r14908 | |
| 124 | 88 | |
| 125 | 89 | a2bus_scsi_device::a2bus_scsi_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) : |
| 126 | 90 | device_t(mconfig, type, name, tag, owner, clock), |
| 127 | | device_a2bus_card_interface(mconfig, *this) |
| 91 | device_a2bus_card_interface(mconfig, *this), |
| 92 | m_ncr5380(*this, SCSI_5380_TAG) |
| 128 | 93 | { |
| 129 | 94 | m_shortname = "a2scsi"; |
| 130 | 95 | } |
| 131 | 96 | |
| 132 | 97 | a2bus_scsi_device::a2bus_scsi_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : |
| 133 | 98 | device_t(mconfig, A2BUS_SCSI, "Apple II SCSI Card", tag, owner, clock), |
| 134 | | device_a2bus_card_interface(mconfig, *this) |
| 99 | device_a2bus_card_interface(mconfig, *this), |
| 100 | m_ncr5380(*this, SCSI_5380_TAG) |
| 135 | 101 | { |
| 136 | 102 | m_shortname = "a2scsi"; |
| 137 | 103 | } |
| r14907 | r14908 | |
| 161 | 127 | read_c0nx - called for reads from this card's c0nx space |
| 162 | 128 | -------------------------------------------------*/ |
| 163 | 129 | |
| 164 | | /* |
| 165 | | |
| 166 | | From schematic (decoded by 74LS138 at U2D) |
| 167 | | |
| 168 | | C0n1/9 = DIP switches |
| 169 | | C0n2/a = clock to 74LS273 bank switcher (so data here should be the bank) |
| 170 | | C0n3/b = reset 5380 |
| 171 | | C0n6/e = into the PAL stuff |
| 172 | | |
| 173 | | */ |
| 174 | | |
| 175 | 130 | UINT8 a2bus_scsi_device::read_c0nx(address_space &space, UINT8 offset) |
| 176 | 131 | { |
| 177 | 132 | printf("Read c0n%x (PC=%x)\n", offset, cpu_get_pc(&space.device())); |
| 178 | 133 | |
| 134 | switch (offset) |
| 135 | { |
| 136 | case 0: |
| 137 | case 1: |
| 138 | case 2: |
| 139 | case 3: |
| 140 | case 4: |
| 141 | case 5: |
| 142 | case 6: |
| 143 | case 7: |
| 144 | return ncr5380_read_reg(m_ncr5380, offset); |
| 145 | |
| 146 | case 9: // card's ID? |
| 147 | return 7; |
| 148 | } |
| 149 | |
| 179 | 150 | return 0xff; |
| 180 | 151 | } |
| 181 | 152 | |
| r14907 | r14908 | |
| 188 | 159 | { |
| 189 | 160 | printf("Write %02x to c0n%x (PC=%x)\n", data, offset, cpu_get_pc(&space.device())); |
| 190 | 161 | |
| 191 | | switch (offset & 7) |
| 162 | switch (offset) |
| 192 | 163 | { |
| 193 | | case 0x2: // ROM and RAM banking (74LS273 at U3E) |
| 164 | case 0: |
| 165 | case 1: |
| 166 | case 2: |
| 167 | case 3: |
| 168 | case 4: |
| 169 | case 5: |
| 170 | case 6: |
| 171 | case 7: |
| 172 | ncr5380_write_reg(m_ncr5380, offset, data); |
| 173 | break; |
| 174 | |
| 175 | case 0xa: // ROM and RAM banking (74LS273 at U3E) |
| 194 | 176 | /* |
| 195 | 177 | ROM banking: |
| 196 | 178 | (bits EA8-EA13 are all zeroed when /IOSEL is asserted, so CnXX always gets the first page of the ROM) |
| r14907 | r14908 | |
| 209 | 191 | m_rombank = (data & 0xf) * 0x400; |
| 210 | 192 | printf("RAM bank to %x, ROM bank to %x\n", m_rambank, m_rombank); |
| 211 | 193 | break; |
| 194 | |
| 195 | case 0xb: |
| 196 | printf("Reset NCR5380\n"); |
| 197 | break; |
| 212 | 198 | } |
| 213 | 199 | } |
| 214 | 200 | |