src/mess/machine/a2memexp.c
| r14876 | r14877 | |
| 82 | 82 | { |
| 83 | 83 | m_shortname = "a2memexp"; |
| 84 | 84 | m_isramfactor = false; |
| 85 | m_bankhior = 0xf0; |
| 86 | m_addrmask = 0xfffff; |
| 85 | 87 | } |
| 86 | 88 | |
| 87 | 89 | a2bus_ramfactor_device::a2bus_ramfactor_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : |
| r14876 | r14877 | |
| 89 | 91 | { |
| 90 | 92 | m_shortname = "a2ramfac"; |
| 91 | 93 | m_isramfactor = true; |
| 94 | m_bankhior = 0x00; |
| 95 | m_addrmask = 0x7fffff; |
| 92 | 96 | } |
| 93 | 97 | |
| 94 | 98 | //------------------------------------------------- |
| r14876 | r14877 | |
| 123 | 127 | |
| 124 | 128 | if (offset == 3) |
| 125 | 129 | { |
| 126 | | retval = m_ram[m_liveptr&0xfffff]; |
| 130 | retval = m_ram[m_liveptr&m_addrmask]; |
| 127 | 131 | // printf("Read RAM[%x] = %02x\n", m_liveptr, retval); |
| 128 | 132 | m_liveptr++; |
| 129 | 133 | m_regs[0] = m_liveptr & 0xff; |
| 130 | 134 | m_regs[1] = (m_liveptr>>8) & 0xff; |
| 131 | | m_regs[2] = ((m_liveptr>>16) & 0xff) | 0xf0; |
| 135 | m_regs[2] = ((m_liveptr>>16) & 0xff) | m_bankhior; |
| 132 | 136 | } |
| 133 | 137 | |
| 134 | | // if (offset > 3) printf("Read c0n%x (PC=%x) = %02x\n", offset, cpu_get_pc(&space.device()), retval); |
| 138 | // printf("Read c0n%x (PC=%x) = %02x\n", offset, cpu_get_pc(&space.device()), retval); |
| 135 | 139 | |
| 136 | 140 | return retval; |
| 137 | 141 | } |
| r14876 | r14877 | |
| 143 | 147 | |
| 144 | 148 | void a2bus_memexp_device::write_c0nx(address_space &space, UINT8 offset, UINT8 data) |
| 145 | 149 | { |
| 146 | | // if (offset > 3) printf("Write %02x to c0n%x (PC=%x)\n", data, offset, cpu_get_pc(&space.device())); |
| 150 | // printf("Write %02x to c0n%x (PC=%x)\n", data, offset, cpu_get_pc(&space.device())); |
| 147 | 151 | |
| 148 | 152 | switch (offset) |
| 149 | 153 | { |
| r14876 | r14877 | |
| 152 | 156 | m_wptr |= data; |
| 153 | 157 | m_regs[0] = m_wptr & 0xff; |
| 154 | 158 | m_regs[1] = (m_wptr>>8) & 0xff; |
| 155 | | m_regs[2] = ((m_wptr>>16) & 0xff) | 0xf0; |
| 159 | m_regs[2] = ((m_wptr>>16) & 0xff) | m_bankhior; |
| 156 | 160 | m_liveptr = m_wptr; |
| 157 | 161 | break; |
| 158 | 162 | |
| r14876 | r14877 | |
| 161 | 165 | m_wptr |= (data<<8); |
| 162 | 166 | m_regs[0] = m_wptr & 0xff; |
| 163 | 167 | m_regs[1] = (m_wptr>>8) & 0xff; |
| 164 | | m_regs[2] = ((m_wptr>>16) & 0xff) | 0xf0; |
| 168 | m_regs[2] = ((m_wptr>>16) & 0xff) | m_bankhior; |
| 165 | 169 | m_liveptr = m_wptr; |
| 166 | 170 | break; |
| 167 | 171 | |
| r14876 | r14877 | |
| 170 | 174 | m_wptr |= (data<<16); |
| 171 | 175 | m_regs[0] = m_wptr & 0xff; |
| 172 | 176 | m_regs[1] = (m_wptr>>8) & 0xff; |
| 173 | | m_regs[2] = ((m_wptr>>16) & 0xff) | 0xf0; |
| 177 | m_regs[2] = ((m_wptr>>16) & 0xff) | m_bankhior; |
| 174 | 178 | m_liveptr = m_wptr; |
| 175 | 179 | break; |
| 176 | 180 | |
| 177 | 181 | case 3: |
| 178 | 182 | // printf("Write %02x to RAM[%x]\n", data, m_liveptr); |
| 179 | | m_ram[(m_liveptr&0xfffff)] = data; |
| 183 | m_ram[(m_liveptr&m_addrmask)] = data; |
| 180 | 184 | m_liveptr++; |
| 181 | 185 | m_regs[0] = m_liveptr & 0xff; |
| 182 | 186 | m_regs[1] = (m_liveptr>>8) & 0xff; |
| 183 | | m_regs[2] = ((m_liveptr>>16) & 0xff) | 0xf0; |
| 187 | m_regs[2] = ((m_liveptr>>16) & 0xff) | m_bankhior; |
| 184 | 188 | break; |
| 185 | 189 | |
| 186 | 190 | default: |