MESS SVN History

15994 Revisions

r14747 Sunday 11th March, 2012 at 17:43:03 UTC by Miodrag Milanović
Sync with MAME r15683 (nw)

[src]	version.c
[src/emu]	device.h save.h
[src/emu/cpu/i386]	i386.c
[src/emu/cpu/lr35902]	lr35902.c
[src/emu/cpu/m6502]	ill02.h
[src/emu/cpu/m68000]	m68kcpu.c
[src/emu/cpu/powerpc]	ppcdrc.c
[src/emu/imagedev]	flopdrv.c flopdrv.h
[src/emu/machine]	ins8250.c nscsi_hd.c
[src/emu/sound]	k054539.c k054539.h votrax.c votrax.h
[src/emu/video]	bufsprite.h
[src/lib]	lib.mak
[src/lib/util]	cdrom.c
[src/mame]	mame.lst
[src/mame/audio]	gottlieb.c
[src/mame/drivers]	armedf.c bbusters.c bfm_sc1.c bionicc.c blktiger.c boogwing.c cninja.c commando.c crshrace.c darkseal.c dassault.c dec8.c deco32.c gottlieb.c lastduel.c m90.c megatech.c namcops2.c naomi.c neodrvr.c popobear.c pyson.c seibuspi.c taitotz.c tnzs.c undrfire.c
[src/mame/includes]	actfancr.h armedf.h bbusters.h bionicc.h exedexes.h galaga.h gng.h gottlieb.h hcastle.h lwings.h m92.h sidearms.h

src/mame/mame.lst
r14746	r14747
2356	2356	pwrshovl // E74 (c) 1999 Taito
2357	2357	landhigh // E82 (c) 1999 Taito
2358	2358	batlgr2 // E87 (c) 2000 Taito (2.04J)
2359		batlgr2a // E87 (c) 2000 Taito (2.01J)
	2359	batlgr2a // E87 (c) 2000 Taito (2.01J)
2360	2360
2361	2361	// Toaplan games
2362	2362	perfrman // (c) 1985 Data East Corporation (Japan)
r14746	r14747
11900	11900	sc1barcd
11901	11901	sc1barcda
11902	11902	sc1bigmt
	11903	sc1btclka
	11904	sc1btclkb
11903	11905	sc1calyp
11904	11906	sc1carro
	11907	sc1cdmp
11905	11908	sc1cshat
11906	11909	sc1cshata
11907	11910	sc1cshatb
r14746	r14747
11964	11967	sc1dream // Dream Machine (Bellfruit)
11965	11968	sc1final // Final Touch (Bellfruit)
11966	11969	sc1flash // Flash (Bellfruit)
	11970	sc1frpusa
11967	11971	sc1fruit // Fruit Lines (Bellfruit)
11968	11972	sc1frtln // Fruitlines (Bellfruit)
11969	11973	sc1funh // Fun House Club (Bellfruit)
r14746	r14747
11975	11979	sc1gprix // Grand Prix (Bellfruit)
11976	11980	sc1gslam // Grand Slam (Bellfruit) (Dutch)
11977	11981	sc1happy // Happy Hour (Bellfruit - Elam)
	11982	sc1hfccp
11978	11983	sc1impc // Impact (Bellfruit)
11979	11984	sc1kings // Kings Club (Bellfruit)
11980	11985	sc1linx // Linx (Bellfruit)

src/mame/audio/gottlieb.c
r14746	r14747
4	4
5	5	Gottlieb 6502-based sound hardware implementations.
6	6
7		Dedicated to Warren Davis, Jeff Lee, Tim Skelly & David Thiel
	7	Dedicated to Warren Davis, Jeff Lee, Tim Skelly & David Thiel
8	8
9	9	****************************************************************************
10	10
r14746	r14747
361	361
362	362	//-------------------------------------------------
363	363	// r6532_portb_w - handle writes to the RIOT's
364		// port B
	364	// port B
365	365	//-------------------------------------------------
366	366
367	367	WRITE8_MEMBER( gottlieb_sound_r1_device::r6532_portb_w )
r14746	r14747
372	372
373	373
374	374	//-------------------------------------------------
375		// votrax_data_w - write data to the Votrax SC-01
	375	// votrax_data_w - write data to the Votrax SC-01
376	376	// speech chip
377	377	//-------------------------------------------------
378	378
r14746	r14747
392	392
393	393	//-------------------------------------------------
394	394	// speech_clock_dac_w - modify the clock driving
395		// the Votrax SC-01 speech chip
	395	// the Votrax SC-01 speech chip
396	396	//-------------------------------------------------
397	397
398	398	WRITE8_MEMBER( gottlieb_sound_r1_device::speech_clock_dac_w )
r14746	r14747
403	403	if (data != m_last_speech_clock)
404	404	{
405	405	mame_printf_debug("clock = %02X\n", data);
406
	406
407	407	// totally random guesswork; would like to get real measurements on a board
408	408	if (m_votrax != NULL)
409	409	m_votrax->set_unscaled_clock(600000 + (data - 0xa0) * 10000);
r14746	r14747
415	415
416	416	//-------------------------------------------------
417	417	// votrax_request - map the VOTRAX SC-01 request
418		// line to the NMI pin on the sound chip
	418	// line to the NMI pin on the sound chip
419	419	//-------------------------------------------------
420	420
421	421	WRITE_LINE_MEMBER( gottlieb_sound_r1_device::votrax_request )
r14746	r14747
483	483
484	484	MACHINE_CONFIG_FRAGMENT( gottlieb_sound_r1_with_votrax )
485	485	MCFG_FRAGMENT_ADD(gottlieb_sound_r1)
486
	486
487	487	// add the VOTRAX
488	488	MCFG_VOTRAX_SC01_ADD("votrax", 720000, gottlieb_votrax_interface)
489	489	MCFG_SOUND_ROUTE(ALL_OUTPUTS, DEVICE_SELF_OWNER, 0.50)
r14746	r14747
552	552	//**************************************************************************
553	553
554	554	//-------------------------------------------------
555		// gottlieb_sound_r1_with_votrax_device -
556		// constructor
	555	// gottlieb_sound_r1_with_votrax_device -
	556	// constructor
557	557	//-------------------------------------------------
558	558
559	559	gottlieb_sound_r1_with_votrax_device::gottlieb_sound_r1_with_votrax_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
r14746	r14747
618	618
619	619	//-------------------------------------------------
620	620	// static_enable_cobram3_mods - enable changes
621		// for cobram3
	621	// for cobram3
622	622	//-------------------------------------------------
623	623
624	624	void gottlieb_sound_r2_device::static_enable_cobram3_mods(device_t &device)
r14746	r14747
652	652
653	653	//-------------------------------------------------
654	654	// nmi_timer_adjust - adjust the NMI timer to
655		// fire based on its configured rate
	655	// fire based on its configured rate
656	656	//-------------------------------------------------
657	657
658	658	inline void gottlieb_sound_r2_device::nmi_timer_adjust()
r14746	r14747
664	664
665	665	//-------------------------------------------------
666	666	// nmi_state_update - update the NMI state based
667		// on the timer firing and the enable control
	667	// on the timer firing and the enable control
668	668	//-------------------------------------------------
669	669
670	670	inline void gottlieb_sound_r2_device::nmi_state_update()
r14746	r14747
676	676
677	677	//-------------------------------------------------
678	678	// speech_data_r - read the input command latch
679		// from the audio CPU
	679	// from the audio CPU
680	680	//-------------------------------------------------
681	681
682	682	READ8_MEMBER( gottlieb_sound_r2_device::audio_data_r )
r14746	r14747
688	688
689	689	//-------------------------------------------------
690	690	// speech_data_r - read the input command latch
691		// from the speech CPU
	691	// from the speech CPU
692	692	//-------------------------------------------------
693	693
694	694	READ8_MEMBER( gottlieb_sound_r2_device::speech_data_r )
r14746	r14747
700	700
701	701	//-------------------------------------------------
702	702	// signal_audio_nmi_w - signal an NMI from the
703		// speech CPU to the audio CPU
	703	// speech CPU to the audio CPU
704	704	//-------------------------------------------------
705	705
706	706	WRITE8_MEMBER( gottlieb_sound_r2_device::signal_audio_nmi_w )
r14746	r14747
712	712
713	713	//-------------------------------------------------
714	714	// nmi_rate_w - adjust the NMI rate on the speech
715		// CPU
	715	// CPU
716	716	//-------------------------------------------------
717	717
718	718	WRITE8_MEMBER( gottlieb_sound_r2_device::nmi_rate_w )
r14746	r14747
723	723
724	724
725	725	//-------------------------------------------------
726		// speech_drq_custom_r - return the SP0250
727		// request line as an input port bit
	726	// speech_drq_custom_r - return the SP0250
	727	// request line as an input port bit
728	728	//-------------------------------------------------
729	729
730	730	CUSTOM_INPUT_MEMBER( gottlieb_sound_r2_device::speech_drq_custom_r )
r14746	r14747
735	735
736	736	//-------------------------------------------------
737	737	// dac_w - write to one of the two DACs on the
738		// board
	738	// board
739	739	//-------------------------------------------------
740	740
741	741	WRITE8_MEMBER( gottlieb_sound_r2_device::dac_w )
r14746	r14747
748	748
749	749
750	750	//-------------------------------------------------
751		// speech_control_w - primary audio control
752		// register on the speech board
	751	// speech_control_w - primary audio control
	752	// register on the speech board
753	753	//-------------------------------------------------
754	754
755	755	WRITE8_MEMBER( gottlieb_sound_r2_device::speech_control_w )
r14746	r14747
761	761	nmi_state_update();
762	762
763	763	// bit 1 controls a LED on the sound board
764
	764
765	765	// bits 2-4 control the AY-8913, but act differently between the
766	766	// standard sound board and the modified Cobra Command board
767	767	if (!m_cobram3_mod)
r14746	r14747
805	805
806	806	//-------------------------------------------------
807	807	// psg_latch_w - store an 8-bit value in the PSG
808		// latch register
	808	// latch register
809	809	//-------------------------------------------------
810	810
811	811	WRITE8_MEMBER( gottlieb_sound_r2_device::psg_latch_w )
r14746	r14747
815	815
816	816
817	817	//-------------------------------------------------
818		// psg_latch_w - store an 8-bit value in the
819		// SP0250 latch register
	818	// psg_latch_w - store an 8-bit value in the
	819	// SP0250 latch register
820	820	//-------------------------------------------------
821	821
822	822	WRITE8_MEMBER( gottlieb_sound_r2_device::sp0250_latch_w )
r14746	r14747
935	935
936	936	// reset the DACs
937	937	m_dac_data[0] = m_dac_data[1] = 0xff;
938
	938
939	939	// disable the non-speech CPU for cobram3
940	940	if (m_cobram3_mod)
941	941	m_audiocpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
r14746	r14747
967	967	// adjust the NMI timer for the next time
968	968	nmi_timer_adjust();
969	969	break;
970
	970
971	971	case TID_NMI_CLEAR:
972	972	// update state
973	973	m_nmi_state = 0;
974	974	nmi_state_update();
975	975	break;
976
	976
977	977	case TID_SOUND_LATCH_WRITE:
978	978	// each CPU has its own latch
979	979	m_audiocpu_latch = param;

src/mame/includes/hcastle.h
r14746	r14747
32	32	device_t *m_audiocpu;
33	33	device_t *m_k007121_1;
34	34	device_t *m_k007121_2;
35
	35
36	36	required_device<buffered_spriteram8_device> m_spriteram;
37	37	required_device<buffered_spriteram8_device> m_spriteram2;
38	38	};

src/mame/includes/exedexes.h
r14746	r14747
28	28	int m_objon;
29	29	int m_sc1on;
30	30	int m_sc2on;
31
	31
32	32	required_device<buffered_spriteram8_device> m_spriteram;
33	33	};
34	34

src/mame/includes/lwings.h
r14746	r14747
29	29	UINT8 m_soundstate;
30	30	UINT8 m_adpcm;
31	31	UINT8 m_nmi_mask;
32
	32
33	33	required_device<buffered_spriteram8_device> m_spriteram;
34	34	};
35	35

src/mame/includes/armedf.h
r14746	r14747
29	29	int m_sprite_offy;
30	30	int m_old_mcu_mode;
31	31	int m_waiting_msb;
32
	32
33	33	required_device<buffered_spriteram16_device> m_spriteram;
34	34	};
35	35

src/mame/includes/actfancr.h
r14746	r14747
15	15	UINT16 m_spriteram16[0x800/2]; // a 16-bit copy of spriteram for use with the MXC06 code
16	16
17	17	/* video-related */
18		int m_flipscreen;
	18	int m_flipscreen;
19	19
20	20	/* misc */
21	21	int m_trio_control_select;

src/mame/includes/bbusters.h
r14746	r14747
25	25	UINT16 *m_pf2_data;
26	26	UINT16 *m_pf1_scroll_data;
27	27	UINT16 *m_pf2_scroll_data;
28
	28
29	29	required_device<buffered_spriteram16_device> m_spriteram;
30	30	optional_device<buffered_spriteram16_device> m_spriteram2;
31	31	};

src/mame/includes/bionicc.h
r14746	r14747
27	27
28	28	UINT16 m_inp[3];
29	29	UINT16 m_soundcommand;
30
	30
31	31	required_device<buffered_spriteram16_device> m_spriteram;
32	32	};
33	33

src/mame/includes/gng.h
r14746	r14747
24	24	tilemap_t *m_fg_tilemap;
25	25	UINT8 m_scrollx[2];
26	26	UINT8 m_scrolly[2];
27
	27
28	28	required_device<buffered_spriteram8_device> m_spriteram;
29	29	};
30	30

src/mame/includes/galaga.h
r14746	r14747
65	65
66	66	UINT8 *m_bosco_radarx;
67	67	UINT8 *m_bosco_radary;
68
	68
69	69	UINT8 *m_spriteram;
70	70	UINT8 *m_spriteram2;
71	71	UINT32 m_spriteram_size;

src/mame/includes/sidearms.h
r14746	r14747
27	27	UINT32 m_hcount_191;
28	28	UINT32 m_vcount_191;
29	29	UINT32 m_latch_374;
30
	30
31	31	required_device<buffered_spriteram8_device> m_spriteram;
32	32	};
33	33

src/mame/includes/gottlieb.h
r14746	r14747
62	62	// ======================> gottlieb_sound_r1_device
63	63
64	64	// rev 1 sound board, with unpopulated VOTRAX
65		class gottlieb_sound_r1_device : public device_t,
	65	class gottlieb_sound_r1_device : public device_t,
66	66	public device_mixer_interface
67	67	{
68	68	public:
r14746	r14747
72	72
73	73	// read/write
74	74	DECLARE_WRITE8_MEMBER( write );
75
	75
76	76	// internal communications
77	77	DECLARE_WRITE_LINE_MEMBER( snd_interrupt );
78	78	DECLARE_WRITE8_MEMBER( r6532_portb_w );
r14746	r14747
88	88
89	89	private:
90	90	// devices
91		required_device<m6502_device> m_audiocpu;
92		required_device<riot6532_device> m_riot;
	91	required_device<m6502_device> m_audiocpu;
	92	required_device<riot6532_device> m_riot;
93	93	required_device<dac_device> m_dac;
94	94	optional_device<votrax_sc01_device> m_votrax;
95	95
96	96	// internal state
97	97	bool m_populate_votrax;
98		UINT8 m_last_speech_clock;
	98	UINT8 m_last_speech_clock;
99	99
100	100	#if USE_FAKE_VOTRAX
101	101	protected:
r14746	r14747
128	128	// ======================> gottlieb_sound_r2_device
129	129
130	130	// fully populated rev 2 sound board
131		class gottlieb_sound_r2_device : public device_t,
	131	class gottlieb_sound_r2_device : public device_t,
132	132	public device_mixer_interface
133	133	{
134	134	public:
r14746	r14747
140	140
141	141	// read/write
142	142	DECLARE_WRITE8_MEMBER( write );
143
	143
144	144	// internal communications
145	145	DECLARE_READ8_MEMBER( speech_data_r );
146	146	DECLARE_READ8_MEMBER( audio_data_r );
r14746	r14747
171	171	TID_NMI_CLEAR,
172	172	TID_SOUND_LATCH_WRITE
173	173	};
174
	174
175	175	// devices
176		required_device<m6502_device> m_audiocpu;
177		required_device<m6502_device> m_speechcpu;
	176	required_device<m6502_device> m_audiocpu;
	177	required_device<m6502_device> m_speechcpu;
178	178	required_device<dac_device> m_dac;
179		required_device<ay8913_device> m_ay1;
180		required_device<ay8913_device> m_ay2;
181		optional_device<sp0250_device> m_sp0250;
	179	required_device<ay8913_device> m_ay1;
	180	required_device<ay8913_device> m_ay2;
	181	optional_device<sp0250_device> m_sp0250;
182	182
183	183	// internal state
184	184	bool m_cobram3_mod;
185	185	emu_timer * m_nmi_timer;
186		UINT8 m_nmi_rate;
187		UINT8 m_nmi_state;
	186	UINT8 m_nmi_rate;
	187	UINT8 m_nmi_state;
188	188	UINT8 m_audiocpu_latch;
189	189	UINT8 m_speechcpu_latch;
190		UINT8 m_speech_control;
191		UINT8 m_last_command;
192		UINT8 m_dac_data[2];
	190	UINT8 m_speech_control;
	191	UINT8 m_last_command;
	192	UINT8 m_dac_data[2];
193	193	UINT8 m_psg_latch;
194		UINT8 m_psg_data_latch;
	194	UINT8 m_psg_data_latch;
195	195	UINT8 m_sp0250_latch;
196	196	};
197	197

src/mame/includes/m92.h
r14746	r14747
33	33	UINT16 m_pf_master_control[4];
34	34	INT32 m_sprite_list;
35	35	UINT8 m_palette_bank;
36
	36
37	37	required_device<buffered_spriteram16_device> m_spriteram;
38	38	};
39	39

src/mame/drivers/blktiger.c
r14746	r14747
349	349	MCFG_PALETTE_LENGTH(1024)
350	350
351	351	MCFG_VIDEO_START(blktiger)
352
	352
353	353	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
354	354
355	355	/* sound hardware */

src/mame/drivers/bfm_sc1.c
r14746	r14747
1402	1402	ROM_REGION( 0x10000, "maincpu", 0 )
1403	1403	ROM_LOAD( "cash_attraction_b", 0x0000, 0x8000, CRC(79870574) SHA1(89e5db89064a9e24bc37389d78f4defb7d2f479b) )
1404	1404	ROM_LOAD( "cash_attraction_a", 0x8000, 0x8000, CRC(fab3283c) SHA1(669b425687faad0ebf88c1aaaafa40c446fa2e24) )
1405
	1405
1406	1406	ROM_REGION( 0x10000, "altrevs", 0 )
1407	1407	ROM_LOAD( "957172.40 b std var%.bin", 0x0000, 0x008000, CRC(5e4381f9) SHA1(ae6d64c42ae7ddc2ed0ab5c3b56222090004d88a) )
1408	1408	ROM_LOAD( "957182.20 var% proto a.bin", 0x0000, 0x008000, CRC(3a2dd72d) SHA1(29d962702095aa0f252210da68a89c557fa9db69) )
r14746	r14747
1466	1466	ROM_REGION( 0x10000, "maincpu", 0 )
1467	1467	ROM_LOAD( "cashxpl2.bin", 0x0000, 0x8000, CRC(0199136c) SHA1(bed1df64ecc0d7ef951a59717e219e6fe7ebf99c) )
1468	1468	ROM_LOAD( "cashxpl1.bin", 0x8000, 0x8000, CRC(0fe62ead) SHA1(bd56a216292e9bf2b7753616a6cd25b37e22095f) )
1469
	1469
1470	1470	ROM_REGION( 0x10000, "altrevs", 0 ) // i think some of this is on different hw (SC2?)
1471	1471	ROM_LOAD( "cash_explosion_dat_ac_8_10pnd_20p_a.bin", 0x0000, 0x010000, CRC(1d155799) SHA1(4e76328a4d093d1f9c64c633c3558db2dce4e219) )
1472	1472	ROM_LOAD( "cash_explosion_dat_ac_var_8pnd_a.bin", 0x0000, 0x010000, CRC(4aa53121) SHA1(cf0510e224de62b837915d39c2fe3559cfe8c85f) )
r14746	r14747
1504	1504	ROM_REGION( 0x10000, "maincpu", 0 )
1505	1505	ROM_LOAD( "95717206b std.bin", 0x0000, 0x8000, CRC(2478530f) SHA1(be82a4e36a3c076b9e94fa2364904ca463b6b4ed) )
1506	1506	ROM_LOAD( "95717205a std.bin", 0x8000, 0x8000, CRC(795bbeea) SHA1(22e0fc9bc3c70e05e51cb98837a9c706eb2ca080) )
1507
	1507
1508	1508	ROM_REGION( 0x10000, "altrevs", 0 )//these seem to be halves without a partner, do these share the same b ROM?
1509	1509	ROM_LOAD( "95718205a std ptel.bin", 0x0000, 0x008000, CRC(c88f476c) SHA1(a5d8f12ade77bdb100ece5f2eecec35ae09f3b0e) )
1510	1510	ROM_LOAD( "95718210a proto var.bin", 0x0000, 0x008000, CRC(0997c4e9) SHA1(1013a12803796d3926cceeb671c7c07cc66d418e) )
r14746	r14747
1571	1571	ROM_REGION( 0x10000, "maincpu", 0 )
1572	1572	ROM_LOAD( "club-china-town_std_ac_150pnd_lfj_bss.bin", 0x0000, 0x8000, CRC(d41c6999) SHA1(cc2eb2e74ca3bfa78d74dd08f83acb2fe650e13d) )
1573	1573	ROM_LOAD( "club-china-town_std_ac_150pnd_lfj_ass.bin", 0x8000, 0x8000, CRC(8c3e69f1) SHA1(cb0cbf7a6039549b969160a162a0cd5511b24cd3) )
1574
	1574
1575	1575	sc1_china_sound
1576	1576	ROM_END
1577	1577
r14746	r14747
1679	1679	ROM_REGION( 0x10000, "maincpu", 0 )
1680	1680	ROM_LOAD( "club-six-five-special_std_ac_rot_10po_bss.bin", 0x0000, 0x8000, CRC(3371dc55) SHA1(52d75a90933acc7a03821e5c2821df6126c72a6c) )
1681	1681	ROM_LOAD( "club-six-five-special_std_ac_rot_10po_ass.bin", 0x8000, 0x8000, CRC(cf48ba99) SHA1(5da4321ff349964e903f1bebd3e5ddd0799fc478) )
1682
	1682
1683	1683	sc1_cl65_sound_alt
1684	1684	ROM_END
1685	1685
r14746	r14747
1687	1687	ROM_REGION( 0x10000, "maincpu", 0 )
1688	1688	ROM_LOAD( "club-six-five-special_std_ac_rot_10po_bss.bin", 0x0000, 0x8000, CRC(3371dc55) SHA1(52d75a90933acc7a03821e5c2821df6126c72a6c) )
1689	1689	ROM_LOAD( "club-six-five-special_dat_ac_rot_10po_ass.bin", 0x8000, 0x8000, CRC(77ddf81d) SHA1(522d9f84ab6e31586f371548e2f146ac193f06f5) )
1690
	1690
1691	1691	sc1_cl65_sound_alt
1692	1692	ROM_END
1693	1693
r14746	r14747
1752	1752	ROM_REGION( 0x10000, "maincpu", 0 )
1753	1753	ROM_LOAD( "temptp2", 0x0000, 0x8000, CRC(d165fa87) SHA1(aef8a4af8b6e83ef09dffc8aca305eaf7dd3936b) )
1754	1754	ROM_LOAD( "temptp1", 0x8000, 0x8000, CRC(6f03648d) SHA1(a6402c94ebf4d570d1d3fb462eb621566c27f307) )
1755
	1755
1756	1756	ROM_REGION( 0x40000, "upd", 0 )
1757	1757	ROM_LOAD( "tempsnd1.bin", 0x00000, 0x10000, CRC(168e2a18) SHA1(db97acf9131b1a54efe1cd375aecae1679bab19e) )
1758	1758	ROM_LOAD( "tempsnd2.bin", 0x00000, 0x10000, CRC(b717f347) SHA1(189c82318d622f18580a23eed48b17c0c34dedd5) )
r14746	r14747
1859	1859	ROM_REGION( 0x10000, "maincpu", 0 )
1860	1860	ROM_LOAD( "doublechancegame2.bin", 0x0000, 0x008000, CRC(d4f49454) SHA1(53b97f941a4abfeb3e498b4295f98e80bd182b7e) )
1861	1861	ROM_LOAD( "doublechancegame1.bin", 0x8000, 0x008000, CRC(9e24e0e3) SHA1(fff1fe9219c052750709d13c06148c7926a22910) )
1862
	1862
1863	1863	ROM_REGION( 0x40000, "altrevs", 0 )//orphans?
1864	1864	ROM_LOAD( "95717787 10p20p.bin", 0x0000, 0x008000, CRC(69ba126c) SHA1(f59aa5a632d0bc5102c206f986f86b6c7c1352fb) )
1865	1865	ROM_LOAD( "95717789 10p.bin", 0x0000, 0x008000, CRC(fc338d38) SHA1(65457f2611ffa22ac35f1e7ad10c290c01b9c3ac) )
r14746	r14747
2409	2409	sc1_winst_sound
2410	2410	ROM_END
2411	2411
2412
	2412
2413	2413	ROM_START( sc1winstp )
2414	2414	ROM_REGION( 0x10000, "maincpu", 0 )
2415	2415	ROM_LOAD( "95717110 var% b.bin", 0x0000, 0x8000, CRC(1c2ebd26) SHA1(462baa4df7c01d101798df1d90bb5719cdc9647e) )
r14746	r14747
2601	2601	ROM_REGION( 0x10000, "maincpu", 0 )
2602	2602	ROM_LOAD( "dsnl1-6.p2", 0x0000, 0x8000, CRC(0eb10c01) SHA1(16456ec1e32bfbd873bdebd6a760041bc9cd8648) )
2603	2603	ROM_LOAD( "dsnl1-6.p1", 0x8000, 0x8000, CRC(174c4432) SHA1(82519ede8220d3d717ee0ebe57374357afe38949) )
2604
	2604
2605	2605	sc1_driv_sound
2606	2606	ROM_END
2607
	2607
2608	2608	ROM_START( sc1vsd )
2609	2609	ROM_REGION( 0x10000, "maincpu", 0 )
2610	2610	ROM_LOAD( "supd1-4n.p1", 0x8000, 0x8000, CRC(ad581f7d) SHA1(99b9bf1016cd52467f5c9f6e427305e81033e82f) )
r14746	r14747
2733	2733	ROM_LOAD( "bc6-4_0b.bin", 0x0000, 0x8000, CRC(106265c8) SHA1(6465f7e868c5b04776fee69295a52197abb45ad0) )
2734	2734	ROM_LOAD( "bc6-4_0a.bin", 0x8000, 0x8000, CRC(750645e7) SHA1(65eee2a00a1914bb8dc989b131eaa39d2881105d) )
2735	2735
2736		// ROM_REGION( 0x80000, "altrevs", 0 )
	2736	// ROM_REGION( 0x80000, "altrevs", 0 )
2737	2737
2738	2738	ROM_REGION( 0x200000, "upd", ROMREGION_ERASE00 )
2739	2739	ROM_END

src/mame/drivers/deco32.c
r14746	r14747
1965	1965	MCFG_SCREEN_VISIBLE_AREA(08, 408-1, 18, 318-1)
1966	1966	MCFG_SCREEN_UPDATE_STATIC(dragngun)
1967	1967	MCFG_SCREEN_VBLANK_STATIC(dragngun)
1968
	1968
1969	1969	MCFG_BUFFERED_SPRITERAM32_ADD("spriteram")
1970	1970
1971	1971	MCFG_DECO16IC_ADD("tilegen1", dragngun_deco16ic_tilegen1_intf)
r14746	r14747
2038	2038	MCFG_SCREEN_VISIBLE_AREA(08, 408-1, 18, 318-1)
2039	2039	MCFG_SCREEN_UPDATE_STATIC(dragngun)
2040	2040	MCFG_SCREEN_VBLANK_STATIC(dragngun)
2041
	2041
2042	2042	MCFG_BUFFERED_SPRITERAM32_ADD("spriteram")
2043	2043
2044	2044	MCFG_DECO16IC_ADD("tilegen1", lockload_deco16ic_tilegen1_intf)

src/mame/drivers/namcops2.c
r14746	r14747
208	208	SYSTEM246_BIOS
209	209
210	210	ROM_REGION(0x840000, "key", ROMREGION_ERASE00)
211		ROM_LOAD( "sc31002-na-a.ic002", 0x000000, 0x840000, CRC(2ebf91ff) SHA1(01e628344b2cde2edbda9ffea53af6a63e3bddf1) )
	211	ROM_LOAD( "sc31002-na-a.ic002", 0x000000, 0x840000, CRC(2ebf91ff) SHA1(01e628344b2cde2edbda9ffea53af6a63e3bddf1) )
212	212
213	213	DISK_REGION("dvd")
214	214	DISK_IMAGE_READONLY( "sc31001-na-dvd0-b", 0, SHA1(b46ee35083f8fcc091ce562951c55fbdbb929e4b) )
r14746	r14747
291	291	SYSTEM246_BIOS
292	292
293	293	ROM_REGION(0x840000, "key", ROMREGION_ERASE00)
294		ROM_LOAD( "tef1verc.ic002", 0x000000, 0x840000, CRC(92697a2b) SHA1(e9ec254d52187f5be0d9be58b25821c1e63bba8e) )
	294	ROM_LOAD( "tef1verc.ic002", 0x000000, 0x840000, CRC(92697a2b) SHA1(e9ec254d52187f5be0d9be58b25821c1e63bba8e) )
295	295
296	296	DISK_REGION("dvd")
297	297	DISK_IMAGE_READONLY( "tef1dvd0", 0, SHA1(f39aa37156245f622a6e19e8a0e081418e247b36) )

src/mame/drivers/darkseal.c
r14746	r14747
279	279
280	280	MCFG_GFXDECODE(darkseal)
281	281	MCFG_PALETTE_LENGTH(2048)
282
	282
283	283	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
284	284
285	285	MCFG_DECO16IC_ADD("tilegen1", darkseal_deco16ic_tilegen1_intf)

src/mame/drivers/bionicc.c
r14746	r14747
387	387	MCFG_PALETTE_LENGTH(1024)
388	388
389	389	MCFG_VIDEO_START(bionicc)
390
	390
391	391	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
392	392
393	393	MCFG_SPEAKER_STANDARD_MONO("mono")

src/mame/drivers/lastduel.c
r14746	r14747
521	521	MCFG_SCREEN_VISIBLE_AREA(88, (64-8)8-1, 18, 318-1 )
522	522	MCFG_SCREEN_UPDATE_STATIC(lastduel)
523	523	MCFG_SCREEN_VBLANK_DEVICE("spriteram", buffered_spriteram16_device, vblank_copy_rising)
524
	524
525	525	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
526	526
527	527	MCFG_GFXDECODE(lastduel)

src/mame/drivers/commando.c
r14746	r14747
272	272
273	273	MCFG_PALETTE_INIT(RRRR_GGGG_BBBB)
274	274	MCFG_VIDEO_START(commando)
275
	275
276	276	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
277	277
278	278	/* sound hardware */

src/mame/drivers/naomi.c
r14746	r14747
5524	5524	NAOMI_DEFAULT_EEPROM
5525	5525
5526	5526	ROM_REGION( 0x10000000, "rom_board", ROMREGION_ERASEFF)
5527		ROM_LOAD( "maz1fl1.2d", 0x0000000, 0x0800000, CRC(620cdbb6) SHA1(95e9d0858e1d3060b3c1c41adfff0539185fb03d) )
	5527	ROM_LOAD( "maz1fl1.2d", 0x0000000, 0x0800000, CRC(620cdbb6) SHA1(95e9d0858e1d3060b3c1c41adfff0539185fb03d) )
5528	5528	ROM_RELOAD( 0x800000, 0x800000 )
5529		ROM_LOAD( "maz1ma1.4m", 0x1000000, 0x1000000, CRC(68e12189) SHA1(5a434bd0305189620a62c785c5ac2812dae033d6) )
5530		ROM_LOAD( "maz1ma2.4l", 0x2000000, 0x1000000, CRC(c7a05b44) SHA1(dfbeb3be5adfdf3d4f1d330f3654a5532eb28cc2) )
5531		ROM_LOAD( "maz1ma3.4k", 0x3000000, 0x1000000, CRC(48e1a8a5) SHA1(8b0d83c02ab576d90c95aad297c7447326154c0e) )
5532		ROM_LOAD( "maz1ma4.4j", 0x4000000, 0x1000000, CRC(0187cdab) SHA1(aaa9fd208103426eb0eee58ae0a64a191abcd126) )
5533		ROM_LOAD( "maz1ma5.4h", 0x5000000, 0x1000000, CRC(c6885ee7) SHA1(14e7e017438adcbe0136d7d863af95fe65bd15d8) )
5534		ROM_LOAD( "maz1ma6.4f", 0x6000000, 0x1000000, CRC(a6593c36) SHA1(627bf19d960037ea92b673b786a9da7208acd447) )
5535		ROM_LOAD( "maz1ma7.4e", 0x7000000, 0x1000000, CRC(6103ad9c) SHA1(e4abbb5867cae6a9bf9067ab3a091ef7b18fa0cd) )
5536		ROM_LOAD( "maz1ma8.4d", 0x8000000, 0x1000000, CRC(d46c9f40) SHA1(45eec7fa3d4261f12438e841254fa75d572331b3) )
	5529	ROM_LOAD( "maz1ma1.4m", 0x1000000, 0x1000000, CRC(68e12189) SHA1(5a434bd0305189620a62c785c5ac2812dae033d6) )
	5530	ROM_LOAD( "maz1ma2.4l", 0x2000000, 0x1000000, CRC(c7a05b44) SHA1(dfbeb3be5adfdf3d4f1d330f3654a5532eb28cc2) )
	5531	ROM_LOAD( "maz1ma3.4k", 0x3000000, 0x1000000, CRC(48e1a8a5) SHA1(8b0d83c02ab576d90c95aad297c7447326154c0e) )
	5532	ROM_LOAD( "maz1ma4.4j", 0x4000000, 0x1000000, CRC(0187cdab) SHA1(aaa9fd208103426eb0eee58ae0a64a191abcd126) )
	5533	ROM_LOAD( "maz1ma5.4h", 0x5000000, 0x1000000, CRC(c6885ee7) SHA1(14e7e017438adcbe0136d7d863af95fe65bd15d8) )
	5534	ROM_LOAD( "maz1ma6.4f", 0x6000000, 0x1000000, CRC(a6593c36) SHA1(627bf19d960037ea92b673b786a9da7208acd447) )
	5535	ROM_LOAD( "maz1ma7.4e", 0x7000000, 0x1000000, CRC(6103ad9c) SHA1(e4abbb5867cae6a9bf9067ab3a091ef7b18fa0cd) )
	5536	ROM_LOAD( "maz1ma8.4d", 0x8000000, 0x1000000, CRC(d46c9f40) SHA1(45eec7fa3d4261f12438e841254fa75d572331b3) )
5537	5537
5538	5538	ROM_REGION( 4, "rom_key", 0 )
5539		ROM_LOAD( "maz1-key.bin", 0x000000, 0x000004, CRC(79ebd41a) SHA1(3545dacdeac66b46e8706565f0eca784291040d1) )
	5539	ROM_LOAD( "maz1-key.bin", 0x000000, 0x000004, CRC(79ebd41a) SHA1(3545dacdeac66b46e8706565f0eca784291040d1) )
5540	5540	ROM_END
5541	5541
5542	5542	ROM_START( vtenis2c )
r14746	r14747
7907	7907	/* 25349801 */ GAME( 2000, toukon4, naomi, naomim2, naomi, naomi, ROT0, "Capcom / Namco", "Shin Nihon Pro Wrestling Toukon Retsuden 4 Arcade Edition (TRF1 Ver. A)", GAME_UNEMULATED_PROTECTION\|GAME_FLAGS )
7908	7908	// 25469801 Ninja Assault
7909	7909	/* 25709801 */ GAME( 2001, gunsur2, naomi, naomi, naomi, naomi, ROT0, "Capcom / Namco", "Gun Survivor 2 Biohazard Code: Veronica (BHF1 Ver. A)", GAME_UNEMULATED_PROTECTION\|GAME_FLAGS )
7910		/* 25869812 */ GAME( 2002, mazan, naomi, naomim2, naomi, naomi, ROT0, "Capcom / Namco", "Mazan: Flash of the Blade (MAZ1 Ver. A)", GAME_UNEMULATED_PROTECTION\|GAME_FLAGS )
	7910	/* 25869812 */ GAME( 2002, mazan, naomi, naomim2, naomi, naomi, ROT0, "Capcom / Namco", "Mazan: Flash of the Blade (MAZ1 Ver. A)", GAME_UNEMULATED_PROTECTION\|GAME_FLAGS )
7911	7911
7912	7912	/* GDS-xxxx (Sega GD-ROM games) */
7913	7913	/* 0001 */ GAME( 2000, confmiss, naomigd, naomigd, hotd2, naomigd, ROT0, "Sega", "Confidential Mission (GDS-0001)", GAME_FLAGS )

src/mame/drivers/megatech.c
r14746	r14747
314	314	static WRITE8_HANDLER( bios_ctrl_w )
315	315	{
316	316	mtech_state *state = space->machine().driver_data<mtech_state>();
317
	317
318	318	if (offset == 1)
319	319	{
320	320	output_set_value("Alarm_sound", data>>7 & 0x01);
r14746	r14747
324	324	{
325	325	output_set_value("Flash_screen", data>>1 & 0x01);
326	326	}
327
	327
328	328	state->m_bios_ctrl[offset] = data;
329	329	}
330	330

src/mame/drivers/cninja.c
r14746	r14747
932	932
933	933	MCFG_GFXDECODE(cninja)
934	934	MCFG_PALETTE_LENGTH(2048)
935
	935
936	936	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
937	937
938	938	MCFG_DECOCOMN_ADD("deco_common", cninja_decocomn_intf)

src/mame/drivers/dassault.c
r14746	r14747
593	593
594	594	MCFG_GFXDECODE(dassault)
595	595	MCFG_PALETTE_LENGTH(4096)
596
	596
597	597	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
598	598	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram2")
599	599

src/mame/drivers/pyson.c
r14746	r14747
3	3	Konami Pyson Hardware Overview
4	4	Konami 2001-2005
5	5
6		This system uses a standard GH-006 PS2 main board (the older Playstation 2 square type) with a
7		Sony-supplied PS2 power supply which bolts onto the top of the main board. This power supply
8		has a single 12 volt power input and creates all of the voltages for the PS2. The same 12 volt input
9		extends via a splitter to the Konami interface PCB into CN3. The PS2 main board is connected to the
10		custom Konami interface PCB via the PS2 main board AV connector and the IEEE 1394 'i.LINK' connector.
	6	This system uses a standard GH-006 PS2 main board (the older Playstation 2 square type) with a
	7	Sony-supplied PS2 power supply which bolts onto the top of the main board. This power supply
	8	has a single 12 volt power input and creates all of the voltages for the PS2. The same 12 volt input
	9	extends via a splitter to the Konami interface PCB into CN3. The PS2 main board is connected to the
	10	custom Konami interface PCB via the PS2 main board AV connector and the IEEE 1394 'i.LINK' connector.
11	11	A security dongle with no label on the top which looks like a PS2 memory card is plugged into the left
12	12	PS2 memory card slot. This card is identical to the dongles used in Namco System 246/256. Note that the
13		two games dumped so far have the same label on the security dongle (KN00002) but the ROM inside is not
14		identical. So far all the Konami game software resides on a 128M CF card. However there are probably
	13	two games dumped so far have the same label on the security dongle (KN00002) but the ROM inside is not
	14	identical. So far all the Konami game software resides on a 128M CF card. However there are probably
15	15	HDD/CDROM/DVDROM-based games too since the Konami interface board has connectors for IDE drives.
16	16
17	17	Games known to run on this system include.... DIN5
18		CF Card Dongle PS2 Cart
	18	CF Card Dongle PS2 Cart
19	19	Game Title Label Label Label (bottom)
20	20	---------------------------------------------------------------------------------------------------------
21	21	*Baseball Heroes 2005
r14746	r14747
30	30	*Paintball Mania
31	31	*Perfect Pool
32	32	*Pool Pocket Fortunes
33		*R.P.M. Red
	33	*R.P.M. Red
34	34	World Soccer Winning Eleven Arcade Game Style C18JAA03 DIN5 dongle GCC27JA KN00002
35	35	World Soccer Winning Eleven Arcade Game Style 2003 C27JAA03 not used KN00002
36	36	---------------------------------------------------------------------------------------------------------
37	37
38		* denotes not dumped. If you can help with the remaining undumped games
	38	* denotes not dumped. If you can help with the remaining undumped games
39	39	please contact us via http://mamedev.org or http://guru.mameworld.info
40	40
41	41
r14746	r14747
90	90	TMPR3927 - Toshiba TMPR3927 32-bit R3000A-based RISC micro-controller (QFP240)
91	91	48LC2M32B2 - Micron 48LC2M32B2 512k x32-bit x4-banks (64MBit) SDRAM (TSOP86)
92	92	XC9536 - Xilinx XC9536XL CPLD stamped 'QB22A1' (PLCC44)
93		B22A01.U42 - Fujitsu MBM29F400 512k x8-bit flash ROM stamped 'B22A01' (TSOP48). This is probably
	93	B22A01.U42 - Fujitsu MBM29F400 512k x8-bit flash ROM stamped 'B22A01' (TSOP48). This is probably
94	94	the common-to-all-games Pyson BIOS for the TMPR3927
95	95	XCS10XL - Xilinx Spartan XCS10XL FPGA (TQFP144)
96	96	M48T58Y - ST Microelectronics M48T58Y 8k Timekeeper/NVRAM (DIP28). As well as being used for protection
97		with the Konami game code/year etc (the usual first 16 bytes) it also seems to contain code
98		or other data in some of the games, meaning it's not possible to hand-create the NVRAMs.
	97	with the Konami game code/year etc (the usual first 16 bytes) it also seems to contain code
	98	or other data in some of the games, meaning it's not possible to hand-create the NVRAMs.
99	99	The same 'extended usage' of this chip is also present on Konami Viper PCBs.
100	100	DS2430 - Dallas DS2430 256-bit EEPROM and silicon serial number (3 pin TO-92 package)
101	101	CN2 - RJ45 network connector
r14746	r14747
107	107	CN15 - 28 way edge connector which connects to the filter board along with the JAMMA edge connector
108	108	CN16 - 40 pin standard IDE connector (for CDROM/DVDROM or 3.5" IDE HDD)
109	109	CN17 - 44 pin standard IDE connector (for 2.5" IDE HDD)
110		CN19 - DIN5 connector for plug-in security module. The module contains a Dallas DS2430 which
	110	CN19 - DIN5 connector for plug-in security module. The module contains a Dallas DS2430 which
111	111	effectively replaces the common-to-most-games one on the main board (same a Viper h/w)
112	112	CN20 - 4 pin connector
113	113	CN21 - Standard Compact Flash card slot
114	114	SW4 - 4 position DIP switch
115
116
	115
	116
117	117	Filter Board
118	118	------------
119	119
r14746	r14747
133	133	\|-------------------------------------------------------------------------\|
134	134	Notes:
135	135	CN4 - 8-pin mini-DIN connector
136		CN5/7 - 15-pin VGA connectors
	136	CN5/7 - 15-pin VGA connectors
137	137	CN14 - Standard USB connector. This connects to a standard JVS I/O board. It was tested with
138	138	a common Sega JVS I/O and works fine however Konami probably have their own JVS I/O board
139	139	for use with this system

src/mame/drivers/taitotz.c
r14746	r14747
520	520	TAITOTZ_BIOS
521	521
522	522	ROM_REGION( 0x40000, "io_cpu", 0 )
523		ROM_LOAD16_BYTE( "e74-04.ic14", 0x000000, 0x020000, CRC(ef21a261) SHA1(7398826dbf48014b9c7e9454f978f3e419ebc64b) )
524		ROM_LOAD16_BYTE( "e74-05.ic15", 0x000001, 0x020000, CRC(2466217d) SHA1(dc814da3a1679cff001f179d3c1641af985a6490) )
	523	ROM_LOAD16_BYTE( "e74-04.ic14", 0x000000, 0x020000, CRC(ef21a261) SHA1(7398826dbf48014b9c7e9454f978f3e419ebc64b) )
	524	ROM_LOAD16_BYTE( "e74-05.ic15", 0x000001, 0x020000, CRC(2466217d) SHA1(dc814da3a1679cff001f179d3c1641af985a6490) )
525	525
526	526	ROM_REGION( 0x10000, "sound_cpu", 0 ) /* Internal ROM :( */
527	527	ROM_LOAD( "e68-01.ic7", 0x000000, 0x010000, NO_DUMP )

src/mame/drivers/m90.c
r14746	r14747
950	950
951	951	ROM_START( dynablstb2 )
952	952	ROM_REGION( CODE_SIZE, "maincpu", 0 )
953		ROM_LOAD16_BYTE( "2.bin", 0x000001, 0x020000, CRC(9c3e996a) SHA1(9244f6a8b498d0f488bbfc68465916ea0560f3be) )
954		ROM_LOAD16_BYTE( "3.bin", 0x000000, 0x020000, CRC(697a2ed9) SHA1(d329987f7a0321414347b8e6a6dfc4304fbe4987) )
	953	ROM_LOAD16_BYTE( "2.bin", 0x000001, 0x020000, CRC(9c3e996a) SHA1(9244f6a8b498d0f488bbfc68465916ea0560f3be) )
	954	ROM_LOAD16_BYTE( "3.bin", 0x000000, 0x020000, CRC(697a2ed9) SHA1(d329987f7a0321414347b8e6a6dfc4304fbe4987) )
955	955	ROM_COPY( "maincpu", 0x3fff0, 0xffff0, 0x10 ) /* start vector */
956	956
957	957	ROM_REGION( 0x10000, "soundcpu", 0 )

src/mame/drivers/boogwing.c
r14746	r14747
361	361	MCFG_GFXDECODE(boogwing)
362	362
363	363	MCFG_VIDEO_START(boogwing)
364
	364
365	365	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
366	366	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram2")
367	367

src/mame/drivers/neodrvr.c
r14746	r14747
427	427	-- SNKPLAYMORE --
428	428	. NEO-MVS CHAFIO (2003.7.24) - used only with NEO-CMC 90G06C7050
429	429
430		-- SNK development boards --
431		. NEO-MVS CHAMC2
	430	-- SNK development boards --
	431	. NEO-MVS CHAMC2
432	432
433	433	MVS PROG:
434	434	-- SNK --
r14746	r14747
463	463	. NEO-MVS PROGBK3S (2003.10.1)
464	464	. NEO-MVS PROGBK2S (2003.10.18)
465	465
466		-- SNK development boards --
467		. NEO-MVS PROGMC2
	466	-- SNK development boards --
	467	. NEO-MVS PROGMC2
468	468
469	469
470	470	AES CHA:

src/mame/drivers/gottlieb.c
r14746	r14747
692	692	* Main CPU memory handlers
693	693	*
694	694	*************************************/
695
	695
696	696	static WRITE8_HANDLER( gottlieb_sh_w )
697	697	{
698	698	gottlieb_state *state = space->machine().driver_data<gottlieb_state>();
r14746	r14747
2485	2485
2486	2486	/* games using rev 1 sound board */
2487	2487	GAME( 1982, reactor, 0, reactor, reactor, ramtiles, ROT0, "Gottlieb", "Reactor", GAME_IMPERFECT_SOUND )
2488		GAME( 1982, qbert, 0, qbert, qbert, romtiles, ROT270, "Gottlieb", "Q*bert (US set 1)", GAME_IMPERFECT_SOUND )
	2488	GAME( 1982, qbert, 0, qbert, qbert, romtiles, ROT270, "Gottlieb", "Q*bert (US set 1)", GAME_IMPERFECT_SOUND )
2489	2489	GAME( 1982, qberta, qbert, qbert, qbert, romtiles, ROT270, "Gottlieb", "Q*bert (US set 2)", GAME_IMPERFECT_SOUND )
2490		GAME( 1982, qbertj, qbert, qbert, qbert, romtiles, ROT270, "Gottlieb (Konami license)", "Q*bert (Japan)", GAME_IMPERFECT_SOUND )
2491		GAME( 1982, myqbert, qbert, qbert, qbert, romtiles, ROT270, "Gottlieb", "Mello Yello Q*bert", GAME_IMPERFECT_SOUND )
2492		GAME( 1982, qberttst, qbert, qbert, qbert, romtiles, ROT270, "Gottlieb", "Q*bert (early test version)", GAME_IMPERFECT_SOUND )
2493		GAME( 1982, qbtrktst, qbert, qbert, qbert, romtiles, ROT270, "Gottlieb", "Q*bert Board Input Test Rom", GAME_IMPERFECT_SOUND )
	2490	GAME( 1982, qbertj, qbert, qbert, qbert, romtiles, ROT270, "Gottlieb (Konami license)", "Q*bert (Japan)", GAME_IMPERFECT_SOUND )
	2491	GAME( 1982, myqbert, qbert, qbert, qbert, romtiles, ROT270, "Gottlieb", "Mello Yello Q*bert", GAME_IMPERFECT_SOUND )
	2492	GAME( 1982, qberttst, qbert, qbert, qbert, romtiles, ROT270, "Gottlieb", "Q*bert (early test version)", GAME_IMPERFECT_SOUND )
	2493	GAME( 1982, qbtrktst, qbert, qbert, qbert, romtiles, ROT270, "Gottlieb", "Q*bert Board Input Test Rom", GAME_IMPERFECT_SOUND )
2494	2494	GAME( 1982, insector, 0, gottlieb1, insector, romtiles, ROT0, "Gottlieb", "Insector (prototype)", 0 )
2495	2495	GAME( 1982, tylz, 0, gottlieb1_votrax, tylz, romtiles, ROT0, "Mylstar", "Tylz (prototype)", GAME_IMPERFECT_SOUND ) // modified sound hw?
2496	2496	GAME( 1984, argusg, 0, gottlieb1, argusg, ramtiles, ROT0, "Gottlieb", "Argus (Gottlieb, prototype)" , 0) // aka Guardian / Protector?
r14746	r14747
2498	2498	GAME( 1983, mplanetsuk,mplanets, gottlieb1, mplanets, romtiles, ROT270, "Gottlieb (Taitel license)", "Mad Planets (UK)", 0 )
2499	2499	GAME( 1983, krull, 0, gottlieb1, krull, ramtiles, ROT270, "Gottlieb", "Krull", 0 )
2500	2500	GAME( 1983, kngtmare, 0, gottlieb1, kngtmare, romtiles, ROT0, "Gottlieb", "Knightmare (prototype)", GAME_NO_SOUND )
2501		GAME( 1983, sqbert, 0, qbert, qbert, romtiles, ROT270, "Mylstar", "Faster, Harder, More Challenging Q*bert (prototype)", GAME_IMPERFECT_SOUND )
2502		GAME( 1983, qbertqub, 0, qbert, qbertqub, romtiles, ROT270, "Mylstar", "Q*bert's Qubes", GAME_IMPERFECT_SOUND )
	2501	GAME( 1983, sqbert, 0, qbert, qbert, romtiles, ROT270, "Mylstar", "Faster, Harder, More Challenging Q*bert (prototype)", GAME_IMPERFECT_SOUND )
	2502	GAME( 1983, qbertqub, 0, qbert, qbertqub, romtiles, ROT270, "Mylstar", "Q*bert's Qubes", GAME_IMPERFECT_SOUND )
2503	2503	GAME( 1984, curvebal, 0, gottlieb1, curvebal, romtiles, ROT270, "Mylstar", "Curve Ball", 0 )
2504	2504
2505	2505	/* games using rev 2 sound board */

src/mame/drivers/seibuspi.c
r14746	r14747
3402	3402
3403	3403	ROM_START( rfjett ) /* SPI Cart, Taiwan */
3404	3404	ROM_REGION32_LE(0x200000, "user1", 0) /* i386 program */
3405		ROM_LOAD32_BYTE( "prg0.u0211", 0x000000, 0x080000, CRC(a4734579) SHA1(dfbd8e2a3178c7cfd7bd3698999f14bc80f5212f) )
3406		ROM_LOAD32_BYTE( "prg1.u0212", 0x000001, 0x080000, CRC(5e4ad3a4) SHA1(ff66e16f48978b88b298c78e21309208ccb3ff15) )
3407		ROM_LOAD32_BYTE( "prg2.u0221", 0x000002, 0x080000, CRC(21c9942e) SHA1(ededa05a4b5dae2dec5c4409f22e9a66d2c8e98e) )
3408		ROM_LOAD32_BYTE( "prg3.u0220", 0x000003, 0x080000, CRC(ea3657f4) SHA1(2291e31243af7d2e79ae727d9b5484e8d49cc7d9) )
	3405	ROM_LOAD32_BYTE( "prg0.u0211", 0x000000, 0x080000, CRC(a4734579) SHA1(dfbd8e2a3178c7cfd7bd3698999f14bc80f5212f) )
	3406	ROM_LOAD32_BYTE( "prg1.u0212", 0x000001, 0x080000, CRC(5e4ad3a4) SHA1(ff66e16f48978b88b298c78e21309208ccb3ff15) )
	3407	ROM_LOAD32_BYTE( "prg2.u0221", 0x000002, 0x080000, CRC(21c9942e) SHA1(ededa05a4b5dae2dec5c4409f22e9a66d2c8e98e) )
	3408	ROM_LOAD32_BYTE( "prg3.u0220", 0x000003, 0x080000, CRC(ea3657f4) SHA1(2291e31243af7d2e79ae727d9b5484e8d49cc7d9) )
3409	3409
3410	3410	ROM_REGION( 0x30000, "gfx1", ROMREGION_ERASEFF)
3411	3411	ROM_LOAD24_BYTE("fix0.u0524", 0x000001, 0x10000, CRC(8bc080be) SHA1(ad296fb98242c963072346a8de289e704b445ad4) )

src/mame/drivers/popobear.c
r14746	r14747
1	1	/*******************************************************************************************
2	2
3		Popo Bear (c) 2000 BMC
	3	Popo Bear (c) 2000 BMC
4	4
5		preliminary driver by Angelo Salese
	5	preliminary driver by Angelo Salese
6	6
7		TODO:
8		- auto-animation speed is erratic (way too fast);
9		- sprites;
10		- tilemap effects (scrolling, colscroll, linescroll);
11		- BGM seems quite off, YM2413 core bug?
12		- I/Os;
13		- IRQ generation;
14		- Port 0x620000 is quite a mystery, some silly protection?
	7	TODO:
	8	- auto-animation speed is erratic (way too fast);
	9	- sprites;
	10	- tilemap effects (scrolling, colscroll, linescroll);
	11	- BGM seems quite off, YM2413 core bug?
	12	- I/Os;
	13	- IRQ generation;
	14	- Port 0x620000 is quite a mystery, some silly protection?
15	15
16	16	============================================================================================
17	17	Popo Bear - BMC-A00211
r14746	r14747
106	106	const UINT8 vreg_base[] = { 0x10/2, 0x14/2 };
107	107	int xscroll,yscroll;
108	108
109		// count = (state->m_vregs[vreg_base[layer_n]]<<5);
110		// count &= 0xfc000;
	109	// count = (state->m_vregs[vreg_base[layer_n]]<<5);
	110	// count &= 0xfc000;
111	111	count = (0xf0000+layer_n*0x4000);
112	112	if(layer_n & 2)
113	113	{
r14746	r14747
153	153	bitmap.pix16(yoffs+512, xoffs+1) = machine.pens[color];
154	154
155	155	//if(cliprect.contains(xoffs+1, yoffs+256) && color)
156		// bitmap.pix16(yoffs+512, xoffs+1) = machine.pens[color];
	156	// bitmap.pix16(yoffs+512, xoffs+1) = machine.pens[color];
157	157
158	158	color = (vram[((xi+1+yi*1024)+xtile+ytile) & 0xfffff] & 0xff);
159	159
r14746	r14747
188	188	#endif
189	189
190	190	/*
191		???? ---- ---- ---- unused?
192		---- xxxx ---- ---- priority?
193		---- ---- x--- ---- Y direction
194		---- ---- -x-- ---- X direction
195		---- ---- --xx ---- width
196		---- ---- ---- xx-- color bank
197		---- ---- ---- --xx height?
198		*/
	191	???? ---- ---- ---- unused?
	192	---- xxxx ---- ---- priority?
	193	---- ---- x--- ---- Y direction
	194	---- ---- -x-- ---- X direction
	195	---- ---- --xx ---- width
	196	---- ---- ---- xx-- color bank
	197	---- ---- ---- --xx height?
	198	*/
199	199
200	200	/* 0x106 = 8 x 8 */
201	201	/* 0x29 = 32 x 32 /
r14746	r14747
218	218	continue;
219	219
220	220	//if(param & bank_test)
221		// continue;
	221	// continue;
222	222
223	223	spr_num <<= 3;
224	224
r14746	r14747
251	251
252	252	SCREEN_UPDATE_IND16( popobear )
253	253	{
254		// popobear_state *state = screen.machine().driver_data<popobear_state>();
	254	// popobear_state *state = screen.machine().driver_data<popobear_state>();
255	255
256	256	bitmap.fill(0, cliprect);
257	257
r14746	r14747
295	295	AM_RANGE(0x480000, 0x48001f) AM_RAM AM_BASE_MEMBER(popobear_state, m_vregs)
296	296	AM_RANGE(0x480020, 0x480023) AM_RAM
297	297	AM_RANGE(0x480028, 0x48002d) AM_RAM
298		// AM_RANGE(0x480020, 0x480021) AM_NOP //AM_READ(popo_480020_r) AM_WRITE(popo_480020_w)
299		// AM_RANGE(0x480028, 0x480029) AM_NOP //AM_WRITE(popo_480028_w)
300		// AM_RANGE(0x48002c, 0x48002d) AM_NOP //AM_WRITE(popo_48002c_w)
	298	// AM_RANGE(0x480020, 0x480021) AM_NOP //AM_READ(popo_480020_r) AM_WRITE(popo_480020_w)
	299	// AM_RANGE(0x480028, 0x480029) AM_NOP //AM_WRITE(popo_480028_w)
	300	// AM_RANGE(0x48002c, 0x48002d) AM_NOP //AM_WRITE(popo_48002c_w)
301	301	AM_RANGE(0x480030, 0x480031) AM_WRITE8(popobear_irq_ack_w, 0x00ff)
302	302	AM_RANGE(0x480034, 0x480035) AM_RAM // coin counter or coin lockout
303	303	AM_RANGE(0x48003a, 0x48003b) AM_RAM //AM_READ(popo_48003a_r) AM_WRITE(popo_48003a_w)
r14746	r14747
461	461	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
462	462	MCFG_SCREEN_UPDATE_STATIC(popobear)
463	463
464		// MCFG_GFXDECODE(popobear)
	464	// MCFG_GFXDECODE(popobear)
465	465
466	466	MCFG_SCREEN_SIZE(1288, 328)
467	467	MCFG_SCREEN_VISIBLE_AREA(08, 648-1, 08, 328-1)

src/mame/drivers/undrfire.c
r14746	r14747
457	457	output_set_value("Lamp_5", (data >> 4) & 1 );
458	458	output_set_value("Lamp_6", (data >> 5) & 1 );
459	459	output_set_value("Wheel_vibration", (data >> 6) & 1 );
460
	460
461	461	cputag_set_input_line(space->machine(), "sub", INPUT_LINE_RESET, (data & 0x1000) ? CLEAR_LINE : ASSERT_LINE);
462	462	}
463	463

src/mame/drivers/armedf.c
r14746	r14747
1265	1265
1266	1266	MCFG_GFXDECODE(armedf)
1267	1267	MCFG_PALETTE_LENGTH(2048)
1268
	1268
1269	1269	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
1270	1270
1271	1271	/* sound hardware */

src/mame/drivers/bbusters.c
r14746	r14747
696	696	MCFG_PALETTE_LENGTH(2048)
697	697
698	698	MCFG_VIDEO_START(bbuster)
699
	699
700	700	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
701	701	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram2")
702	702

src/mame/drivers/tnzs.c
r14746	r14747
2138	2138
2139	2139	ROM_START( arknoid2b )
2140	2140	ROM_REGION( 0x30000, "maincpu", 0 ) /* Region 0 - main cpu */
2141		ROM_LOAD( "boot.11c", 0x00000, 0x08000, CRC(3847dfb0) SHA1(993c8af3df7a4d5a2523f0e31a6df1c07ba13c7d) )
	2141	ROM_LOAD( "boot.11c", 0x00000, 0x08000, CRC(3847dfb0) SHA1(993c8af3df7a4d5a2523f0e31a6df1c07ba13c7d) )
2142	2142	ROM_CONTINUE( 0x18000, 0x08000 ) /* banked at 8000-bfff */
2143	2143	/* 20000-2ffff empty */
2144	2144

src/mame/drivers/crshrace.c
r14746	r14747
487	487
488	488	MCFG_GFXDECODE(crshrace)
489	489	MCFG_PALETTE_LENGTH(2048)
490
	490
491	491	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
492	492	MCFG_BUFFERED_SPRITERAM16_ADD("spriteram2")
493	493

src/mame/drivers/dec8.c
r14746	r14747
339	339	static WRITE8_HANDLER( srdarwin_i8751_w )
340	340	{
341	341	dec8_state *state = space->machine().driver_data<dec8_state>();
342
	342
343	343	/* Japan coinage first, then World coinage - US coinage shall be the same as the Japan one */
344	344	int lneed1[2][4] = {{1, 1, 1, 2}, {1, 1, 1, 1}}; /* slot 1 : coins needed */
345	345	int lcred1[2][4] = {{1, 2, 3, 1}, {2, 3, 4, 6}}; /* slot 1 : credits awarded */
r14746	r14747
398	398	if (state->m_i8751_value == 0x5000) { state->m_i8751_return = ((state->m_credits / 10) << 4) \| (state->m_credits % 10); } /* Credits request */
399	399	if (state->m_i8751_value == 0x6000 && state->m_credits) { state->m_i8751_value = -1; state->m_credits--; } /* Credits clear */
400	400
401		/*
402		This next value is the index to a series of tables,
	401	/*
	402	This next value is the index to a series of tables,
403	403	each table controls the end of level bad guy,
404	404	wrong values crash the cpu right away via a bogus jump.
405	405
r14746	r14747
2065	2065
2066	2066	/* video hardware */
2067	2067	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2068
	2068
2069	2069	MCFG_DEVICE_ADD("spritegen", DECO_KARNOVSPRITES, 0)
2070	2070	deco_karnovsprites_device::set_gfx_region(*device, 1);
2071	2071
r14746	r14747
2114	2114
2115	2115	/* video hardware */
2116	2116	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2117
	2117
2118	2118	MCFG_DEVICE_ADD("spritegen", DECO_KARNOVSPRITES, 0)
2119	2119	deco_karnovsprites_device::set_gfx_region(*device, 1);
2120	2120
r14746	r14747
2163	2163
2164	2164	/* video hardware */
2165	2165	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2166
	2166
2167	2167	MCFG_DEVICE_ADD("spritegen", DECO_KARNOVSPRITES, 0)
2168	2168	deco_karnovsprites_device::set_gfx_region(*device, 1);
2169	2169
r14746	r14747
2213	2213
2214	2214	/* video hardware */
2215	2215	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2216
	2216
2217	2217	MCFG_DEVICE_ADD("spritegen", DECO_KARNOVSPRITES, 0)
2218	2218	deco_karnovsprites_device::set_gfx_region(*device, 1);
2219	2219
r14746	r14747
2263	2263
2264	2264	/* video hardware */
2265	2265	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2266
	2266
2267	2267	MCFG_DEVICE_ADD("tilegen1", DECO_BAC06, 0)
2268	2268	deco_bac06_device::set_gfx_region_wide(*device, 2,2,0);
2269	2269
r14746	r14747
2318	2318
2319	2319	/* video hardware */
2320	2320	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2321
	2321
2322	2322	MCFG_DEVICE_ADD("spritegen", DECO_KARNOVSPRITES, 0)
2323	2323	deco_karnovsprites_device::set_gfx_region(*device, 1);
2324	2324
r14746	r14747
2372	2372
2373	2373	/* video hardware */
2374	2374	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2375
	2375
2376	2376	MCFG_DEVICE_ADD("tilegen1", DECO_BAC06, 0)
2377	2377	deco_bac06_device::set_gfx_region_wide(*device, 2,2,0);
2378	2378
r14746	r14747
2421	2421
2422	2422	/* video hardware */
2423	2423	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2424
	2424
2425	2425	MCFG_SCREEN_ADD("screen", RASTER)
2426	2426	MCFG_SCREEN_REFRESH_RATE(58)
2427	2427	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
r14746	r14747
2464	2464
2465	2465	/* video hardware */
2466	2466	MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
2467
	2467
2468	2468	MCFG_DEVICE_ADD("tilegen1", DECO_BAC06, 0)
2469	2469	deco_bac06_device::set_gfx_region_wide(*device, 2,2,0);
2470	2470	MCFG_DEVICE_ADD("tilegen2", DECO_BAC06, 0)

src/emu/cpu/m68000/m68kcpu.c
r14746	r14747
1911	1911
1912	1912	static CPU_INIT( m68301 )
1913	1913	{
1914		// m68ki_cpu_core *m68k = get_safe_token(device);
	1914	// m68ki_cpu_core *m68k = get_safe_token(device);
1915	1915
1916	1916	CPU_INIT_CALL(m68000);
1917	1917
r14746	r14747
1941	1941	CPU_INIT_CALL(m68000);
1942	1942
1943	1943	/* basic CS logic, timers, mbus, serial logic
1944		set via remappable register
1945		*/
	1944	set via remappable register
	1945	*/
1946	1946	new(&m68k->memory) m68k_memory_interface;
1947	1947	m68k->memory.init16_68307(*m68k->program);
1948	1948

src/emu/cpu/i386/i386.c
r14746	r14747
406	406	if((cpustate->sreg[seg].flags & 0x0018) == 0x0010 && cpustate->sreg[seg].flags & 0x0004) // if expand-down data segment
407	407	{
408	408	// compare if greater then 0xffffffff when we're passed the access size
409		if((offset <= cpustate->sreg[seg].limit) \|\| ((cpustate->sreg[seg].d)?0:(offset > 0xffff)))
	409	if((offset <= cpustate->sreg[seg].limit) \|\| ((cpustate->sreg[seg].d)?0:(offset > 0xffff)))
410	410	{
411	411	logerror("Limit check at 0x%08x failed. Segment %04x, limit %08x, offset %08x (expand-down)\n",cpustate->pc,cpustate->sreg[seg].selector,cpustate->sreg[seg].limit,offset);
412	412	return 1;

src/emu/cpu/m6502/ill02.h
r14746	r14747
175	175	/* 6510 ********************************************************
176	176	* OAL load accumulator and index X
177	177	***************************************************************/
178		#define OAL_6510 \
	178	#define OAL_6510 \
179	179	A = X = (UINT8)((A\|0xee)&tmp); \
180	180	SET_NZ(A)
181	181

src/emu/cpu/powerpc/ppcdrc.c
r14746	r14747
2270	2270	if (xermask & XER_OV)
2271	2271	{
2272	2272	UML_ROLAND(block, I0, I0, 31, 1); // roland i0,i0,31,0x0001
2273		UML_OR(block, XERSO32, XERSO32, I0); // or [xerso],i0
	2273	UML_OR(block, XERSO32, XERSO32, I0); // or [xerso],i0
2274	2274	UML_AND(block, CR32(0), CR32(0), 0xfffffffe); // and [cr0], [cr0], 0xfffffffe (clear SO copy in CR32)
2275		UML_OR(block, CR32(0), I1, XERSO32); // or [cr0],i1,[xerso]
	2275	UML_OR(block, CR32(0), I1, XERSO32); // or [cr0],i1,[xerso]
2276	2276	}
2277	2277	else
2278	2278	{

src/emu/cpu/lr35902/lr35902.c
r14746	r14747
157	157
158	158	state_add(STATE_GENPC, "curpc", m_PC).callimport().callexport().formatstr("%8s").noshow();
159	159	state_add(STATE_GENFLAGS, "GENFLAGS", m_F).mask(0xf0).formatstr("%8s").noshow();
160
	160
161	161	m_icountptr = &m_icount;
162	162	}
163	163

src/emu/video/bufsprite.h
r14746	r14747
89	89	buffered_spriteram_device(const machine_config &mconfig, device_type type, const char tag, device_t owner, UINT32 clock)
90	90	: device_t(mconfig, type, "Buffered Sprite RAM", tag, owner, clock),
91	91	m_spriteram(*owner, tag) { }
92
	92
93	93	// getters
94	94	_Type *live() const { return m_spriteram; }
95	95	_Type *buffer() { return m_buffered; }
96	96	UINT32 bytes() const { return m_spriteram.bytes(); }
97
	97
98	98	// operations
99	99	_Type *copy(UINT32 srcoffset = 0, UINT32 srclength = 0x7fffffff)
100	100	{
r14746	r14747
103	103	memcpy(m_buffered, m_spriteram + srcoffset, MIN(srclength, m_spriteram.bytes() / sizeof(_Type) - srcoffset) * sizeof(_Type));
104	104	return m_buffered;
105	105	}
106
	106
107	107	// read/write handlers
108	108	void write(address_space &space, offs_t offset, _Type data, _Type mem_mask = ~_Type(0)) { copy(); }
109	109
r14746	r14747
124	124
125	125	private:
126	126	// internal state
127		required_shared_ptr<_Type> m_spriteram;
	127	required_shared_ptr<_Type> m_spriteram;
128	128	dynamic_array<_Type> m_buffered;
129	129	};
130	130

src/emu/sound/k054539.c
r14746	r14747
123	123	else
124	124	lval = rval = 0;
125	125	rbase[reverb_pos] = 0;
126
	126
127	127	for(int ch=0; ch<8; ch++)
128	128	if(regs[0x22c] & (1<<ch)) {
129	129	unsigned char base1 = regs + 0x20ch;
r14746	r14747
165	165	rdelta = (rdelta + reverb_pos) & 0x3fff;
166	166
167	167	int cur_pos = (base1[0x0c] \| (base1[0x0d] << 8) \| (base1[0x0e] << 16)) & rom_mask;
168
	168
169	169	int fdelta, pdelta;
170	170	if(base2[0] & 0x20) {
171	171	delta = -delta;
r14746	r14747
281	281	lval += cur_val * lvol;
282	282	rval += cur_val * rvol;
283	283	rbase[(rdelta + reverb_pos) & 0x1fff] += INT16(cur_val*rbvol);
284
	284
285	285	chan->pos = cur_pos;
286	286	chan->pfrac = cur_pfrac;
287	287	chan->pval = cur_pval;
288	288	chan->val = cur_val;
289
	289
290	290	if(regupdate()) {
291	291	base1[0x0c] = cur_pos & 0xff;
292	292	base1[0x0d] = cur_pos>> 8 & 0xff;
r14746	r14747
349	349	int voice, reg;
350	350
351	351	/* The K054539 has behavior like many other wavetable chips including
352		the Ensoniq 550x and Gravis GF-1: if a voice is active, writing
353		to it's current position is silently ignored.
	352	the Ensoniq 550x and Gravis GF-1: if a voice is active, writing
	353	to it's current position is silently ignored.
354	354
355		Dadandaan depends on this or the vocals go wrong.
356		*/
	355	Dadandaan depends on this or the vocals go wrong.
	356	*/
357	357	if (offset < 8*0x20)
358	358	{
359	359	voice = offset / 0x20;

src/emu/sound/k054539.h
r14746	r14747
55	55	void init_flags(int flags);
56	56
57	57	/*
58		Note that the eight PCM channels of a K054539 do not have separate
59		volume controls. Considering the global attenuation equation may not
60		be entirely accurate, k054539_set_gain() provides means to control
61		channel gain. It can be called anywhere but preferrably from
62		DRIVER_INIT().
	58	Note that the eight PCM channels of a K054539 do not have separate
	59	volume controls. Considering the global attenuation equation may not
	60	be entirely accurate, k054539_set_gain() provides means to control
	61	channel gain. It can be called anywhere but preferrably from
	62	DRIVER_INIT().
63	63
64		Parameters:
65		channel : 0 - 7
66		gain : 0.0=silent, 1.0=no gain, 2.0=twice as loud, etc.
67		*/
	64	Parameters:
	65	channel : 0 - 7
	66	gain : 0.0=silent, 1.0=no gain, 2.0=twice as loud, etc.
	67	*/
68	68	void set_gain(int channel, double gain);
69	69
70	70	protected:

src/emu/sound/votrax.c
r14746	r14747
95	95	// it is only an approximation
96	96	const double votrax_sc01_device::s_glottal_wave[16] =
97	97	{
98		0,
99		16.0/22.0,
100		-22.0/22.0,
101		-17.0/22.0,
102		-15.0/22.0,
103		-10.0/22.0,
104		-7.0/22.0,
	98	0,
	99	16.0/22.0,
	100	-22.0/22.0,
	101	-17.0/22.0,
	102	-15.0/22.0,
	103	-10.0/22.0,
	104	-7.0/22.0,
105	105	-4.0/22.0,
106		0,
107		0,
108		0,
109		0,
110		0,
111		0,
112		0,
	106	0,
	107	0,
	108	0,
	109	0,
	110	0,
	111	0,
	112	0,
113	113	0
114	114	};
115	115
r14746	r14747
161	161	// only 6 bits matter
162	162	m_phoneme = data & 0x3f;
163	163	const UINT8 *rom = m_rom + (m_phoneme << 3);
164		mame_printf_debug("%s: STROBE %s (F1=%X F2=%X FC=%X F3=%X F2Q=%X VA=%X FA=%X CL=%X CLD=%X VD=%X PAC=%X PH=%02X)\n",
	164	mame_printf_debug("%s: STROBE %s (F1=%X F2=%X FC=%X F3=%X F2Q=%X VA=%X FA=%X CL=%X CLD=%X VD=%X PAC=%X PH=%02X)\n",
165	165	machine().time().as_string(3), s_phoneme_table[m_phoneme],
166	166	rom[0] >> 4, rom[1] >> 4, rom[2] >> 4, rom[3] >> 4, rom[4] >> 4, rom[5] >> 4, rom[6] >> 4,
167	167	rom[3] & 0xf, rom[4] & 0xf, rom[5] & 0xf, rom[6] & 0xf, rom[7]);
168
	168
169	169	// the STROBE signal resets the phoneme counter
170	170	m_counter_84 = 0xf;
171
	171
172	172	// not in the schematics, but necessary to fully reset the request latch
173	173	m_latch_92 = 0;
174	174
r14746	r14747
179	179
180	180
181	181	//-------------------------------------------------
182		// inflection_w - handle a write to the
183		// inflection bits
	182	// inflection_w - handle a write to the
	183	// inflection bits
184	184	//-------------------------------------------------
185	185
186	186	WRITE8_MEMBER( votrax_sc01_device::inflection_w )
r14746	r14747
189	189	data &= 3;
190	190	if (m_inflection == data)
191	191	return;
192
	192
193	193	// append an inflection marker
194	194	m_stream->update();
195	195	m_inflection = data;
r14746	r14747
202	202	//**************************************************************************
203	203
204	204	//-------------------------------------------------
205		// update_subphoneme_clock_period - re-compute the
206		// period of the sub-phoneme clock, as a multiple
	205	// update_subphoneme_clock_period - re-compute the
	206	// period of the sub-phoneme clock, as a multiple
207	207	// of the master clock
208	208	//-------------------------------------------------
209	209
210	210	void votrax_sc01_device::update_subphoneme_clock_period()
211	211	{
212	212	assert(m_latch_80 < 128);
213
	213
214	214	/*
215		The sub-phoneme timing circuit is based off the switching capacitor
216		technique described in the Votrax patent. Replacing the capacitor
217		ladder with [Rx] representing the effective resistance, the circuit
218		becomes essentially a pair of op-amps:
	215	The sub-phoneme timing circuit is based off the switching capacitor
	216	technique described in the Votrax patent. Replacing the capacitor
	217	ladder with [Rx] representing the effective resistance, the circuit
	218	becomes essentially a pair of op-amps:
219	219
220		VM
221		\| i1
222		[R1]
223		\| Vc
224		+----------------------+
225		\| +---\|C1\|---+ \|
226		[R2] \| \| \| \|\
227		\|Vb i2 \| \|\ \| +--++\
228		+--[Rx]--+----+-\ \| \| >
229		\| \| >--+-----+-/
230		[R3] +----++/ Vc \|/
231		\|i3 \| \|/
232		+--------+ Va
233		\|
234		[R4]
235		\|
236		0
	220	VM
	221	\| i1
	222	[R1]
	223	\| Vc
	224	+----------------------+
	225	\| +---\|C1\|---+ \|
	226	[R2] \| \| \| \|\
	227	\|Vb i2 \| \|\ \| +--++\
	228	+--[Rx]--+----+-\ \| \| >
	229	\| \| >--+-----+-/
	230	[R3] +----++/ Vc \|/
	231	\|i3 \| \|/
	232	+--------+ Va
	233	\|
	234	[R4]
	235	\|
	236	0
237	237
238		We have two op-amps, the left used as a standard amplifier, the right
239		one as a comparator. The circuit triggers when the two inputs of the
240		right op-amp are equal.
	238	We have two op-amps, the left used as a standard amplifier, the right
	239	one as a comparator. The circuit triggers when the two inputs of the
	240	right op-amp are equal.
241	241
242		The left part of the circuit (before C1) is simply a current injector.
243		It's all made of resistors, there's no modulated input, so everything
244		is going to be constant. If you don't know about op-amps used as
245		amplifiers, you just need to know that it forces its two inputs to
246		have the same voltage while not sending or providing any current
247		through there (only though its output in fact).
	242	The left part of the circuit (before C1) is simply a current injector.
	243	It's all made of resistors, there's no modulated input, so everything
	244	is going to be constant. If you don't know about op-amps used as
	245	amplifiers, you just need to know that it forces its two inputs to
	246	have the same voltage while not sending or providing any current
	247	through there (only though its output in fact).
248	248
249		In the schema, the injected current is i2. Basic equations apply:
250		Va = R4.i3
251		Vb = Va + R3.i3
252		Vb = Va + Rx.i2
253		Vc = Vb + R2.i1
254		VM = Vc + R1.i1
255		i1 = i2 + i3
	249	In the schema, the injected current is i2. Basic equations apply:
	250	Va = R4.i3
	251	Vb = Va + R3.i3
	252	Vb = Va + Rx.i2
	253	Vc = Vb + R2.i1
	254	VM = Vc + R1.i1
	255	i1 = i2 + i3
256	256
257		And the tipping happens when the voltage on the right of C1 reaches
258		Vc, so:
259		Vc = Va + i2.T/C1
	257	And the tipping happens when the voltage on the right of C1 reaches
	258	Vc, so:
	259	Vc = Va + i2.T/C1
260	260
261		(i2 being a constant, the integration is kinda easy)
	261	(i2 being a constant, the integration is kinda easy)
262	262
263		Some maths later:
264		R3.i3 = Rx.i2 -> i3 = Rx/R3.i2
265		i1 = (1+Rx/R3).i2
266		Va + (Rx + R2 + R2.Rx/R3).i2 = Va + T/C1.i2
267		T = C1(Rx(1+R2/R3) + R2)
	263	Some maths later:
	264	R3.i3 = Rx.i2 -> i3 = Rx/R3.i2
	265	i1 = (1+Rx/R3).i2
	266	Va + (Rx + R2 + R2.Rx/R3).i2 = Va + T/C1.i2
	267	T = C1(Rx(1+R2/R3) + R2)
268	268
269		Which isn't, interestingly though not surprisingly, dependant on Vm,
270		R1 or R4. And you have to round it to the next multiple of
271		0.2ms+0.1ms due to the clocking on p2 and its offset to p1 (charging
272		only happens on p1 active), and add one p1/p2 cycle (0.2ms) for the
273		discharge.
	269	Which isn't, interestingly though not surprisingly, dependant on Vm,
	270	R1 or R4. And you have to round it to the next multiple of
	271	0.2ms+0.1ms due to the clocking on p2 and its offset to p1 (charging
	272	only happens on p1 active), and add one p1/p2 cycle (0.2ms) for the
	273	discharge.
274	274
275		So now you have your base clock, which you have to multiply by 16 to
276		get the phoneme length.
	275	So now you have your base clock, which you have to multiply by 16 to
	276	get the phoneme length.
277	277
278		r2 = 9e3
279		r3 = 1e3
280		c1 = 1000e-12
281		rx = 1/(5KHz * cx)
	278	r2 = 9e3
	279	r3 = 1e3
	280	c1 = 1000e-12
	281	rx = 1/(5KHz * cx)
282	282	*/
283	283
284	284	// determine total capacitance
r14746	r14747
290	290	if ((m_latch_80 & 0x10) != 0) cx += 86e-12;
291	291	if ((m_latch_80 & 0x20) != 0) cx += 173e-12;
292	292	if ((m_latch_80 & 0x40) != 0) cx += 345e-12;
293
	293
294	294	// apply the equation above to determine charging time
295	295	// note that the 5kHz listed above for P1 is for a nominal master
296	296	// clock frequency of 1.28MHz, meaning it is master clock / 128
r14746	r14747
298	298	double p1_frequency = double(m_master_clock_freq) / double(1 << (P_CLOCK_BIT + 2));
299	299	double rx = 1.0 / (p1_frequency * cx);
300	300	double period = 1000e-12 * (rx * (1.0 + 9e3 / 1e3) + 9e3);
301
	301
302	302	// convert to master clock cycles and round up
303	303	m_subphoneme_period = UINT32(ceil(period * double(m_master_clock_freq)));
304	304	}
r14746	r14747
489	489	double fpeak = sqrt(fabs(k[0]k[1]-k[2]))/(2M_PI*k[2]);
490	490	double zc = 2M_PIfpeak/tan(M_PI*fpeak/fs);
491	491
492		double m0 = zc*k[0];
493		double m1 = zc*k[1];
494		double m2 = zczck[2];
	492	double m0 = zc*k[0];
	493	double m1 = zc*k[1];
	494	double m2 = zczck[2];
495	495
496	496	a[0] = 1+m0;
497	497	a[1] = 3+m0;
r14746	r14747
578	578
579	579	// update master clock
580	580	m_master_clock ^= 1;
581
	581
582	582	// on the falling edge of the master clock, advance the 10-bit counter at 34
583	583	UINT8 old_latch_72 = m_latch_72;
584	584	if (m_master_clock == 0)
r14746	r14747
590	590	}
591	591
592	592	// derive beta 1 clock:
593		// set if m_latch_70.0 == 1
594		// reset if m_latch_70.0 == 0
595		// UINT8 old_beta1 = m_beta1;
	593	// set if m_latch_70.0 == 1
	594	// reset if m_latch_70.0 == 0
	595	// UINT8 old_beta1 = m_beta1;
596	596	m_beta1 = BIT(m_latch_70, 0);
597	597
598	598	// derive p2 clock:
599		// set if (m_counter_34.P_CLOCK_BIT & clock) == 1
600		// reset if (m_counter_34.P_CLOCK_BIT == 0)
	599	// set if (m_counter_34.P_CLOCK_BIT & clock) == 1
	600	// reset if (m_counter_34.P_CLOCK_BIT == 0)
601	601	UINT8 old_p2 = m_p2;
602	602	if (BIT(m_counter_34, P_CLOCK_BIT) & m_master_clock)
603	603	m_p2 = 1;
604	604	else if (!BIT(m_counter_34, P_CLOCK_BIT))
605	605	m_p2 = 0;
606
	606
607	607	// derive p1 clock:
608		// set if (!m_counter_34.P_CLOCK_BIT & clock) == 1
609		// reset if (m_counter_34.P_CLOCK_BIT == 1)
610		// UINT8 old_p1 = m_p1;
	608	// set if (!m_counter_34.P_CLOCK_BIT & clock) == 1
	609	// reset if (m_counter_34.P_CLOCK_BIT == 1)
	610	// UINT8 old_p1 = m_p1;
611	611	if (BIT(~m_counter_34, P_CLOCK_BIT) & m_master_clock)
612	612	m_p1 = 1;
613	613	else if (BIT(m_counter_34, P_CLOCK_BIT))
614	614	m_p1 = 0;
615
	615
616	616	// derive phi2 clock:
617		// set if (m_counter_34.PHI_CLOCK_BIT & clock) == 1
618		// reset if (m_counter_34.PHI_CLOCK_BIT == 0)
	617	// set if (m_counter_34.PHI_CLOCK_BIT & clock) == 1
	618	// reset if (m_counter_34.PHI_CLOCK_BIT == 0)
619	619	UINT8 old_phi2 = m_phi2;
620	620	if (BIT(m_counter_34, PHI_CLOCK_BIT) & m_master_clock)
621	621	m_phi2 = 1;
622	622	else if (!BIT(m_counter_34, PHI_CLOCK_BIT))
623	623	m_phi2 = 0;
624
	624
625	625	// derive phi1 clock:
626		// set if (!m_counter_34.PHI_CLOCK_BIT & clock) == 1
627		// reset if (m_counter_34.PHI_CLOCK_BIT == 1)
	626	// set if (!m_counter_34.PHI_CLOCK_BIT & clock) == 1
	627	// reset if (m_counter_34.PHI_CLOCK_BIT == 1)
628	628	UINT8 old_phi1 = m_phi1;
629	629	if (BIT(~m_counter_34, PHI_CLOCK_BIT) & m_master_clock)
630	630	m_phi1 = 1;
r14746	r14747
632	632	m_phi1 = 0;
633	633
634	634	// derive alternate phi2 clock:
635		// set if (m_counter_34.PHI_CLOCK_BIT & clock) == 1
636		// reset if (m_counter_34.PHI_CLOCK_BIT == 0)
	635	// set if (m_counter_34.PHI_CLOCK_BIT & clock) == 1
	636	// reset if (m_counter_34.PHI_CLOCK_BIT == 0)
637	637	UINT8 old_phi2_20 = m_phi2_20;
638	638	if (BIT(m_counter_34, PHI_CLOCK_BIT + 2) & m_master_clock)
639	639	m_phi2_20 = 1;
640	640	else if (!BIT(m_counter_34, PHI_CLOCK_BIT + 2))
641	641	m_phi2_20 = 0;
642
	642
643	643	// derive alternate phi1 clock:
644		// set if (!m_counter_34.PHI_CLOCK_BIT & clock) == 1
645		// reset if (m_counter_34.PHI_CLOCK_BIT == 1)
646		// UINT8 old_phi1_20 = m_phi1_20;
	644	// set if (!m_counter_34.PHI_CLOCK_BIT & clock) == 1
	645	// reset if (m_counter_34.PHI_CLOCK_BIT == 1)
	646	// UINT8 old_phi1_20 = m_phi1_20;
647	647	if (BIT(~m_counter_34, PHI_CLOCK_BIT + 2) & m_master_clock)
648	648	m_phi1_20 = 1;
649	649	else if (BIT(m_counter_34, PHI_CLOCK_BIT + 2))
650	650	m_phi1_20 = 0;
651	651
652	652	// determine rising edges of each clock of interest
653		// UINT8 beta1_rising = (old_beta1 ^ m_beta1) & m_beta1;
	653	// UINT8 beta1_rising = (old_beta1 ^ m_beta1) & m_beta1;
654	654	UINT8 p2_rising = (old_p2 ^ m_p2) & m_p2;
655		// UINT8 p1_rising = (old_p1 ^ m_p1) & m_p1;
	655	// UINT8 p1_rising = (old_p1 ^ m_p1) & m_p1;
656	656	UINT8 phi2_rising = (old_phi2 ^ m_phi2) & m_phi2;
657	657	UINT8 phi1_rising = (old_phi1 ^ m_phi1) & m_phi1;
658	658	UINT8 phi2_20_rising = (old_phi2_20 ^ m_phi2_20) & m_phi2_20;
659		// UINT8 phi1_20_rising = (old_phi1_20 ^ m_phi1_20) & m_phi1_20;
	659	// UINT8 phi1_20_rising = (old_phi1_20 ^ m_phi1_20) & m_phi1_20;
660	660	UINT8 a0_rising = BIT((old_latch_72 ^ m_latch_72) & m_latch_72, 0);
661	661	UINT8 a2_rising = BIT((old_latch_72 ^ m_latch_72) & m_latch_72, 2);
662	662	UINT8 _125k_rising = BIT((old_latch_72 ^ m_latch_72) & m_latch_72, 3);
r14746	r14747
673	673	UINT8 old_clock_88 = m_clock_88;
674	674	m_clock_88 = !m_latch_42; //!(m_latch_42 \| m_phi1); -- figure 7 seems to be wrong here
675	675	UINT8 clock_88_rising = (old_clock_88 ^ m_clock_88) & m_clock_88;
676
	676
677	677	// the A/R line holds the counter in reset except during phoneme processing,
678	678	// when it is clocked on the rising edge of the subphoneme timer clock
679	679	if (m_internal_request != CLEAR_LINE)
r14746	r14747
683	683	m_counter_84 = (m_counter_84 - 1) & 0x0f;
684	684	mame_printf_debug("counter=%d\n", m_counter_84);
685	685	}
686
	686
687	687	// clock the zero count latch
688	688	if (p2_rising)
689	689	m_latch_92 = ((m_counter_84 == 0) \| (m_latch_92 << 1)) & 3;
690
	690
691	691	// once both bits are set, the request line goes high
692	692	if (m_latch_92 == 3)
693	693	{
r14746	r14747
708	708	UINT8 romdata = m_rom[(m_phoneme << 3) \| ((m_counter_34 >> 4) & 7)];
709	709
710	710	// update the ROM data; ROM format is (upper nibble/lower nibble)
711		// +00 = F1 parameter / 0
712		// +01 = F2 parameter / 0
713		// +02 = FC parameter / 0
714		// +03 = F3 parameter / CL
715		// +04 = F2Q Parameter / CLD
716		// +05 = VA Parameter / VD
717		// +06 = FA Parameter / PAC
718		// +07 = Phoneme timing (full 7 bits)
719
	711	// +00 = F1 parameter / 0
	712	// +01 = F2 parameter / 0
	713	// +02 = FC parameter / 0
	714	// +03 = F3 parameter / CL
	715	// +04 = F2Q Parameter / CLD
	716	// +05 = VA Parameter / VD
	717	// +06 = FA Parameter / PAC
	718	// +07 = Phoneme timing (full 7 bits)
	719
720	720	// latch a new value from ROM on phi2
721	721	UINT8 a = m_latch_72 & 7;
722	722	UINT8 romdata_swapped;
r14746	r14747
728	728	case 3:
729	729	m_srff_132 = m_srff_114 & BIT(~romdata, 3);
730	730	break;
731
	731
732	732	// update CLD
733	733	case 4:
734	734	romdata_swapped = (BIT(romdata, 0) << 3) \| (BIT(romdata, 1) << 2) \| (BIT(romdata, 2) << 1) \| (BIT(romdata, 3) << 0);
735	735	if (m_counter_84 != 0 && romdata_swapped == (m_counter_84 ^ 0xf))
736	736	m_srff_114 = 1;
737	737	break;
738
	738
739	739	// update VD
740	740	case 5:
741	741	romdata_swapped = (BIT(romdata, 0) << 3) \| (BIT(romdata, 1) << 2) \| (BIT(romdata, 2) << 1) \| (BIT(romdata, 3) << 0);
742	742	if (m_counter_84 != 0 && romdata_swapped == (m_counter_84 ^ 0xf))
743	743	m_srff_112 = 1;
744	744	break;
745
	745
746	746	// update FF == PAC & (VA \| FA)
747	747	case 6:
748	748	m_srff_142 = BIT(romdata, 3);
749	749	break;
750
	750
751	751	// update PH
752	752	case 7:
753	753	if (m_latch_80 != (romdata & 0x7f))
r14746	r14747
762	762	break;
763	763	}
764	764	}
765
	765
766	766	//==============================================
767	767	//
768	768	// Glottal circuit (patent figure 6)
r14746	r14747
787	787	m_counter_224 = (m_counter_224 + 1) & 0xf;
788	788	}
789	789	}
790
	790
791	791	// clock remaining glottal counters (220, 222, 236) on rising edge of phi2
792	792	if (phi2_20_rising)
793	793	{
r14746	r14747
800	800	else
801	801	m_counter_220 = (m_counter_220 + 1) & 0xf;
802	802	}
803
	803
804	804	// counter 222 is always enabled
805	805	if (1)
806	806	{
r14746	r14747
810	810	else
811	811	m_counter_222 = (m_counter_222 + 1) & 0xf;
812	812	}
813
	813
814	814	// counter 236 is always enabled
815	815	if (1)
816	816	{
817	817	m_counter_236 = (m_counter_236 + 1) & 0xf;
818
	818
819	819	// rising edge of Q1 from counter 236 clocks counter 234
820	820	if ((m_counter_236 & 0x3) == 0x2)
821	821	{
r14746	r14747
825	825	}
826	826	}
827	827	}
828
	828
829	829	// update FGATE state
830	830	if (counter_220_tc)
831	831	m_fgate = 0;
832	832	if (counter_224_tc)
833	833	m_fgate = 1;
834
	834
835	835	// apply asynchronous clear to counters 234/236
836	836	if (counter_220_tc && m_phi1_20)
837	837	m_counter_236 = m_counter_234 = 0;
838
	838
839	839	// derive glottal circuit output signals
840	840	#if !TEMP_HACKS
841	841	UINT8 old_glottal_sync = m_glottal_sync;
842	842	#endif
843	843	m_glottal_sync = (m_counter_234 == 0);
844	844	glottal_out = s_glottal_wave[m_counter_234];
845
	845
846	846	//==============================================
847	847	//
848	848	// Transition circuit (patent figure 3a/3b)
849	849	//
850	850	//==============================================
851
	851
852	852	// divide 1.25k clock by 2 (lower-left of 46)
853	853	UINT8 old_0625_clock = m_0625_clock;
854	854	if (_125k_rising)
855	855	m_0625_clock = !m_0625_clock;
856	856	UINT8 _0625_rising = (old_0625_clock ^ m_0625_clock) & m_0625_clock;
857
	857
858	858	// update counter above
859	859	if (_0625_rising)
860	860	{
r14746	r14747
863	863	else
864	864	m_counter_46 = (m_counter_46 + 1) & 0xf;
865	865	}
866
	866
867	867	// and then the latch to the right
868	868	if (a2_rising)
869	869	m_latch_46 = (BIT(m_counter_46, 1) << 0) \|
r14746	r14747
885	885	if (!(m_srff_142 & !((m_fa == 0) & (m_va == 0))) && (m_latch_46 & 0x3) == 0x3)
886	886	ram_write = 1;
887	887	break;
888
	888
889	889	case 5:
890	890	if ((m_latch_46 & 0xc) == 0xc && m_srff_112)
891	891	ram_write = 1;
892	892	break;
893
	893
894	894	case 6:
895	895	if ((m_latch_46 & 0xc) == 0xc && m_srff_114)
896	896	ram_write = 1;
897	897	break;
898	898	}
899
	899
900	900	// gate on the phi2 clock (OR gate @ 172)
901	901	ram_write &= m_phi2;
902
	902
903	903	// write the transitioned values to RAM if requested
904	904	// (note we consolidate the serial addition and clocking steps here)
905	905	if (ram_write)
r14746	r14747
907	907	UINT8 old = (m_latch_168 << 4) \| m_latch_170;
908	908	m_ram[a] = old - (old >> 3) + ((romdata & 0xf0) >> 3);
909	909	}
910
	910
911	911	// latch some parameter values on rising edge of phi2
912	912	if (phi2_rising)
913	913	{
r14746	r14747
916	916	case 2:
917	917	m_fc = m_latch_168;
918	918	break;
919
	919
920	920	case 5:
921	921	m_va = m_latch_168;
922	922	break;
923
	923
924	924	case 6:
925	925	m_fa = m_latch_168;
926	926	break;
927	927	}
928	928	}
929
	929
930	930	// latch remaining parameter values on rising edge of (phi2 & glottal sync)
931	931	#if TEMP_HACKS
932	932	if (phi2_rising)
r14746	r14747
940	940	case 0:
941	941	m_f1 = m_latch_168;
942	942	break;
943
	943
944	944	case 1:
945	945	m_f2 = (m_latch_168 << 1) \| (m_latch_170 >> 3);
946	946	break;
947
	947
948	948	case 3:
949	949	m_f3 = m_latch_168;
950	950	break;
951
	951
952	952	case 4:
953	953	m_f2q = m_latch_168;
954	954	break;
955	955	}
956
	956
957	957	// latch value from RAM on rising edge of phi1
958	958	if (phi1_rising)
959	959	{
r14746	r14747
966	966	// Noise generator circuit (patent figure 8)
967	967	//
968	968	//==============================================
969
	969
970	970	// nose is clocked by the NOR of /FA and P1
971	971	UINT8 old_noise_clock = m_noise_clock;
972	972	m_noise_clock = !((m_fa == 0) \| m_p1);
973	973	UINT8 noise_clock_rising = (old_noise_clock ^ m_noise_clock) & m_noise_clock;
974	974	UINT8 noise_clock_falling = (old_noise_clock ^ m_noise_clock) & old_noise_clock;
975
	975
976	976	// falling edge clocks the shift register
977	977	if (noise_clock_falling)
978	978	{
r14746	r14747
981	981	// XOR'ed input goes into d4, which shifts in to d2, then d3, then d1
982	982	// thus the full 18-bit value is effectively
983	983	//
984		// d4 = (m_shift_252 >> 0) & 0x1f;
985		// d2 = (m_shift_252 >> 5) & 0x1f;
986		// d3 = (m_shift_252 >> 10) & 0xf;
987		// d1 = (m_shift_252 >> 14) & 0xf;
	984	// d4 = (m_shift_252 >> 0) & 0x1f;
	985	// d2 = (m_shift_252 >> 5) & 0x1f;
	986	// d3 = (m_shift_252 >> 10) & 0xf;
	987	// d1 = (m_shift_252 >> 14) & 0xf;
988	988	//
989	989	// input at the low end is ((d1+4 ^ d2+5) ^ (d4+4 ^ d4+5)) ^ !(counter2 \| counter3)
990	990	// output is tapped at d3+4
991	991
992	992	UINT32 old_shift = m_shift_252;
993	993	m_shift_252 <<= 1;
994		m_shift_252 \|= ((BIT(old_shift, 17) ^ BIT(old_shift, 9)) ^ (BIT(old_shift, 3) ^ BIT(old_shift, 4))) ^
	994	m_shift_252 \|= ((BIT(old_shift, 17) ^ BIT(old_shift, 9)) ^ (BIT(old_shift, 3) ^ BIT(old_shift, 4))) ^
995	995	((m_counter_250 & 0xc) == 0);
996	996	}
997
	997
998	998	// rising edge clocks the counter
999	999	if (noise_clock_rising)
1000	1000	{
r14746	r14747
1004	1004	else
1005	1005	m_counter_250 = (m_counter_250 + 1) & 0xf;
1006	1006	}
1007
	1007
1008	1008	// compute final noise out signal
1009	1009	noise_out_digital = !(BIT(m_shift_252, 13) & (m_fgate \| (m_va == 0)));
1010	1010	}
r14746	r14747
1132	1132	double s4_out = apply_filter(m_s4i_hist, m_s4_hist, a, b);
1133	1133	shift_hist(s4_out, m_s4_hist, 4);
1134	1134
1135
	1135
1136	1136	// TODO: apply closure circuit (undocumented)
1137
	1137
1138	1138	// output the current result
1139	1139	dest++ = INT16(s4_out 4000);
1140	1140	}
r14746	r14747
1168	1168	m_stream = stream_alloc(0, 1, m_master_clock_freq / 16);
1169	1169	m_phoneme_timer = timer_alloc();
1170	1170	m_rom = subregion("phoneme")->base();
1171
	1171
1172	1172	// reset inputs
1173	1173	m_inflection = 0;
1174	1174	m_phoneme = 0x3f;
1175
	1175
1176	1176	// reset outputs
1177	1177	m_request_func.resolve(m_request_cb, *this);
1178	1178	m_request_state = ASSERT_LINE;
1179	1179	m_internal_request = ASSERT_LINE;
1180
	1180
1181	1181	// save inputs
1182	1182	save_item(NAME(m_inflection));
1183	1183	save_item(NAME(m_phoneme));
1184
	1184
1185	1185	// save outputs
1186	1186	save_item(NAME(m_request_state));
1187	1187	save_item(NAME(m_internal_request));
1188
	1188
1189	1189	// save timing circuit
1190	1190	save_item(NAME(m_master_clock_freq));
1191	1191	save_item(NAME(m_master_clock));
r14746	r14747
1203	1203	save_item(NAME(m_latch_42));
1204	1204	save_item(NAME(m_counter_84));
1205	1205	save_item(NAME(m_latch_92));
1206
	1206
1207	1207	// save low parameter clocking
1208	1208	save_item(NAME(m_srff_132));
1209	1209	save_item(NAME(m_srff_114));
1210	1210	save_item(NAME(m_srff_112));
1211	1211	save_item(NAME(m_srff_142));
1212	1212	save_item(NAME(m_latch_80));
1213
	1213
1214	1214	// save glottal circuit
1215	1215	save_item(NAME(m_counter_220));
1216	1216	save_item(NAME(m_counter_222));
r14746	r14747
1234	1234	save_item(NAME(m_f2q));
1235	1235	save_item(NAME(m_va));
1236	1236	save_item(NAME(m_fa));
1237
	1237
1238	1238	// save noise generator circuit
1239	1239	save_item(NAME(m_noise_clock));
1240	1240	save_item(NAME(m_shift_252));
r14746	r14747
1263	1263	{
1264	1264	// set the initial state
1265	1265	m_stream->update();
1266
	1266
1267	1267	// reset inputs
1268	1268	m_phoneme = 0x3f;
1269	1269	m_request_func(m_internal_request = m_request_state = ASSERT_LINE);
1270
	1270
1271	1271	// reset timing circuit
1272	1272	m_master_clock = 0;
1273	1273	m_counter_34 = 0;
r14746	r14747
1284	1284	m_latch_42 = 0;
1285	1285	m_counter_84 = 0;
1286	1286	m_latch_92 = 0;
1287
	1287
1288	1288	// reset low parameter clocking
1289	1289	m_srff_132 = 0;
1290	1290	m_srff_114 = 0;
r14746	r14747
1292	1292	m_srff_142 = 0;
1293	1293	m_latch_80 = 50;
1294	1294	update_subphoneme_clock_period();
1295
	1295
1296	1296	// reset glottal circuit
1297	1297	m_counter_220 = 0;
1298	1298	m_counter_222 = 0;
r14746	r14747
1301	1301	m_counter_236 = 0;
1302	1302	m_fgate = 0;
1303	1303	m_glottal_sync = 0;
1304
	1304
1305	1305	// reset transition circuit
1306	1306	m_0625_clock = 0;
1307	1307	m_counter_46 = 0;
r14746	r14747
1316	1316	m_f2q = 0;
1317	1317	m_va = 0;
1318	1318	m_fa = 0;
1319
	1319
1320	1320	// reset noise circuit
1321	1321	m_noise_clock = 0;
1322	1322	m_shift_252 = 0;
r14746	r14747
1339	1339
1340	1340	//-------------------------------------------------
1341	1341	// device_clock_changed - handle dynamic clock
1342		// changes by altering our output frequency
	1342	// changes by altering our output frequency
1343	1343	//-------------------------------------------------
1344	1344
1345	1345	void votrax_sc01_device::device_clock_changed()
r14746	r14747
1354	1354	m_stream->update();
1355	1355	m_stream->set_sample_rate(newfreq / 16);
1356	1356	}
1357
	1357
1358	1358	// determine how many clock ticks remained on the phoneme timer
1359	1359	UINT64 remaining = m_phoneme_timer->remaining().as_ticks(m_master_clock_freq);
1360
	1360
1361	1361	// recompute the master clock
1362	1362	m_master_clock_freq = newfreq;
1363	1363
r14746	r14747
1376	1376	{
1377	1377	// force a stream update
1378	1378	m_stream->update();
1379
	1379
1380	1380	// if we're requesting more data, no need for timing
1381	1381	if (m_request_state == ASSERT_LINE)
1382	1382	return;
1383
	1383
1384	1384	// if we're supposed to have fired, do it now
1385	1385	if (m_internal_request == ASSERT_LINE)
1386	1386	{
r14746	r14747
1397	1397	clocks_until_request += m_subphoneme_period - m_subphoneme_count;
1398	1398	clocks_until_request += m_subphoneme_period * (m_counter_84 - 1);
1399	1399	}
1400
	1400
1401	1401	// plus 1/2
1402	1402	clocks_until_request = MAX(clocks_until_request, (1 << P_CLOCK_BIT) / 2);
1403	1403	timer.adjust(attotime::from_ticks(clocks_until_request, m_master_clock_freq));

src/emu/sound/votrax.h
r14746	r14747
52	52	#define MCFG_VOTRAX_SC01_ADD(_tag, _clock, _interface) \
53	53	MCFG_DEVICE_ADD(_tag, VOTRAX_SC01, _clock) \
54	54	votrax_sc01_device::static_set_interface(*device, _interface); \
55
56	55
57	56
	57
58	58	//**************************************************************************
59	59	// TYPE DEFINITIONS
60	60	//**************************************************************************
r14746	r14747
117	117	devcb_resolved_write_line m_request_func; // request callback
118	118	UINT8 m_request_state; // request as seen to the outside world
119	119	UINT8 m_internal_request; // request managed by stream timing
120
	120
121	121	// timing circuit
122	122	UINT32 m_master_clock_freq; // frequency of the master clock
123	123	UINT8 m_master_clock; // master clock
r14746	r14747
137	137	UINT8 m_latch_42; // D flip-flop @ 42
138	138	UINT8 m_counter_84; // 4-bit phoneme counter @ 84
139	139	UINT8 m_latch_92; // 2-bit latch @ 92
140
	140
141	141	// low parameter clocking
142	142	UINT8 m_srff_132; // S/R flip-flop @ 132
143	143	UINT8 m_srff_114; // S/R flip-flop @ 114
144	144	UINT8 m_srff_112; // S/R flip-flop @ 112
145	145	UINT8 m_srff_142; // S/R flip-flop @ 142
146	146	UINT8 m_latch_80; // phoneme timing latch @ 80
147
	147
148	148	// glottal circuit
149	149	UINT8 m_counter_220; // 4-bit counter @ 220
150	150	UINT8 m_counter_222; // 4-bit counter @ 222
r14746	r14747
153	153	UINT8 m_counter_236; // 4-bit counter @ 236
154	154	UINT8 m_fgate; // FGATE signal
155	155	UINT8 m_glottal_sync; // Glottal Sync signal
156
	156
157	157	// transition circuit
158	158	UINT8 m_0625_clock; // state of 0.625kHz clock
159	159	UINT8 m_counter_46; // 4-bit counter in block @ 46
r14746	r14747
168	168	UINT8 m_f2q; // latched 4-bit F2Q value
169	169	UINT8 m_va; // latched 4-bit VA value
170	170	UINT8 m_fa; // latched 4-bit FA value
171
	171
172	172	// noise generator circuit
173	173	UINT8 m_noise_clock; // clock input to noise generator
174	174	UINT32 m_shift_252; // shift register @ 252
175	175	UINT8 m_counter_250; // 4-bit counter @ 250
176	176
177	177	// stages outputs history
178		double m_ni_hist[4];
179		double m_no_hist[4];
180		double m_va_hist[4];
181		double m_s1_hist[4];
182		double m_s2g_hist[4];
183		double m_s2ni_hist[4];
184		double m_s2n_hist[4];
185		double m_s2_hist[4];
186		double m_s3_hist[4];
187		double m_s4i_hist[4];
188		double m_s4_hist[4];
	178	double m_ni_hist[4];
	179	double m_no_hist[4];
	180	double m_va_hist[4];
	181	double m_s1_hist[4];
	182	double m_s2g_hist[4];
	183	double m_s2ni_hist[4];
	184	double m_s2n_hist[4];
	185	double m_s2_hist[4];
	186	double m_s3_hist[4];
	187	double m_s4i_hist[4];
	188	double m_s4_hist[4];
189	189
190	190	// static tables
191	191	static const char *const s_phoneme_table[64];

src/emu/imagedev/flopdrv.c
r14746	r14747
963	963	cnt++;
964	964	}
965	965	image_specify_extension( m_extension_list, 256, floppy_options[i].extensions );
966		}
967
	966	}
	967
968	968	// set brief and instance name
969	969	update_names();
970	970	}

src/emu/imagedev/flopdrv.h
r14746	r14747
191	191	~legacy_floppy_image_device();
192	192
193	193	virtual bool call_load();
194		virtual bool call_softlist_load(char swlist, char swname, rom_entry *start_entry) { return load_software(swlist, swname, start_entry); }
	194	virtual bool call_softlist_load(char swlist, char swname, rom_entry *start_entry) { return load_software(swlist, swname, start_entry); }
195	195	virtual bool call_create(int format_type, option_resolution *format_options);
196	196	virtual void call_unload();
197	197	virtual void call_display_info();
r14746	r14747
206	206	virtual const char *image_interface() const;
207	207	virtual const char *file_extensions() const { return m_extension_list; }
208	208	virtual const option_guide *create_option_guide() const { return floppy_option_guide; }
209
	209
210	210	// access to legacy token
211		void *token() const { assert(m_token != NULL); return m_token; }
	211	void *token() const { assert(m_token != NULL); return m_token; }
212	212	protected:
213	213	// device overrides
214	214	virtual void device_config_complete();
215	215	virtual void device_start();
216
	216
217	217	void *m_token;
218	218	char m_extension_list[256];
219	219	};

src/emu/device.h
r14746	r14747
365	365	optional_shared_ptr(device_t &base, const char tag) : auto_finder_type<_PointerType , false>(base, tag), m_bytes(0) { }
366	366	virtual void findit(device_t &base) { this->set_target(reinterpret_cast<_PointerType *>(this->find_shared_ptr(base, this->m_tag, m_bytes))); }
367	367	UINT32 bytes() const { return m_bytes; }
368
	368
369	369	private:
370	370	// internal state
371	371	size_t m_bytes;
r14746	r14747
379	379	required_shared_ptr(device_t &base, const char tag) : auto_finder_type<_PointerType , true>(base, tag), m_bytes(0) { }
380	380	virtual void findit(device_t &base) { this->set_target(reinterpret_cast<_PointerType *>(this->find_shared_ptr(base, this->m_tag, m_bytes))); }
381	381	UINT32 bytes() const { return m_bytes; }
382
	382
383	383	private:
384	384	// internal state
385	385	size_t m_bytes;

src/emu/machine/nscsi_hd.c
r14746	r14747
161	161	scsi_cmdbuf[pos++] = 0x00; // Meh
162	162	scsi_cmdbuf[pos++] = 0x00; // Double meh
163	163	break;
164
	164
165	165	case 0x03: { // Format parameters page
166	166	scsi_cmdbuf[pos++] = 0x83; // PS, page id
167	167	scsi_cmdbuf[pos++] = 0x16; // Page length

src/emu/machine/ins8250.c
r14746	r14747
21	21
22	22	The original 8250 pulses the interrupt line if a higher priority interrupt is
23	23	cleared but a lower priority one is still active. It also clears the tsre bit
24		for a moment before loading the tsr from the thr. These may be the bugs the
	24	for a moment before loading the tsr from the thr. These may be the bugs the
25	25	PC and XT depend on as the 8250A and up fix them.
26	26
27	27	INS8250-B
r14746	r14747
140	140	{
141	141	m_regs.iir \|=0x04;
142	142	if ((m_int_pending & COM_INT_PENDING_CHAR_TIMEOUT) == 0x11)
143		m_regs.iir \|= 0x08;
	143	m_regs.iir \|= 0x08;
144	144	}
145	145	else if (m_regs.ier & m_int_pending & COM_INT_PENDING_TRANSMITTER_HOLDING_REGISTER_EMPTY)
146	146	m_regs.iir \|=0x02;
r14746	r14747
390	390	{
391	391	if(!(m_regs.fcr & 1))
392	392	return ins8250_uart_device::rcv_complete();
393
	393
394	394	receive_register_extract();
395
	395
396	396	if(m_rnum == 16)
397	397	{
398	398	m_regs.lsr \|= 0x02; //overrun
399	399	trigger_int(COM_INT_PENDING_RECEIVER_LINE_STATUS);
400	400	return;
401	401	}
402
	402
403	403	m_regs.lsr \|= 0x01;
404	404	m_rfifo[m_rhead] = get_received_char();
405	405	++m_rhead &= 0x0f;
r14746	r14747
568	568	{
569	569	UINT8 data = m_rfifo[m_rtail];
570	570	clear_int(COM_INT_PENDING_CHAR_TIMEOUT & ~1); // don't clear bit 1 yet
571
	571
572	572	if(m_rnum)
573	573	{
574	574	++m_rtail &= 0x0f;
r14746	r14747
576	576	}
577	577	else
578	578	data = 0;
579
	579
580	580	if(m_rnum < m_rintlvl)
581	581	clear_int(COM_INT_PENDING_RECEIVED_DATA_AVAILABLE);
582	582
583	583	if(m_rnum)
584	584	set_timer();
585		else
	585	else
586	586	{
587	587	m_timeout->adjust(attotime::never);
588	588	m_regs.lsr &= ~1;

src/emu/save.h
r14746	r14747
307	307
308	308
309	309	//-------------------------------------------------
310		// save_item - specialized save_item for
	310	// save_item - specialized save_item for
311	311	// dynamic_arrays
312	312	//-------------------------------------------------
313	313

src/lib/lib.mak
r14746	r14747
295	295	ARCHFLAGS = -m32 -arch i386 -DWORDS_BIGENDIAN=0
296	296	endif
297	297	endif # BIGENDIAN
298		else # ifeq ($(TARGETOS),macosx)
	298	else # ifeq ($(TARGETOS),macosx)
299	299	ARCHFLAGS = -DWORDS_BIGENDIAN=0
300	300	endif # ifeq ($(TARGETOS),macosx)
301	301

src/lib/util/cdrom.c
r14746	r14747
864	864	else
865	865	{
866	866	metadata.format(GDROM_TRACK_METADATA_FORMAT, i + 1, cdrom_get_type_string(toc->tracks[i].trktype),
867		cdrom_get_subtype_string(toc->tracks[i].subtype), toc->tracks[i].frames, toc->tracks[i].padframes,
868		toc->tracks[i].pregap, cdrom_get_type_string(toc->tracks[i].pgtype),
	867	cdrom_get_subtype_string(toc->tracks[i].subtype), toc->tracks[i].frames, toc->tracks[i].padframes,
	868	toc->tracks[i].pregap, cdrom_get_type_string(toc->tracks[i].pgtype),
869	869	cdrom_get_subtype_string(toc->tracks[i].pgsub), toc->tracks[i].postgap);
870	870
871	871	err = chd->write_metadata(GDROM_TRACK_METADATA_TAG, i, metadata);

src/version.c
r14746	r14747
38	38	***************************************************************************/
39	39
40	40	extern const char build_version[];
41		const char build_version[] = "0.145u3 ("__DATE__")";
	41	const char build_version[] = "0.145u4 ("__DATE__")";

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