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r14643 Sunday 26th February, 2012 at 20:38:12 UTC by Wilbert Pol
lr35902.c: Converted cpu core to C++ (nw)
[src/emu/cpu/lr35902]lr35902.c lr35902.h opc_cb.h opc_main.h
[src/mess/drivers]gb.c
[src/mess/includes]gb.h
[src/mess/machine]gb.c

src/emu/cpu/lr35902/lr35902.c
r14642r14643
4141#include "debugger.h"
4242#include "lr35902.h"
4343
44#define FLAG_Z   0x80
45#define FLAG_N  0x40
46#define FLAG_H  0x20
47#define FLAG_C  0x10
4844
49#define CYCLES_PASSED(X)      cpustate->icount -= ((X) / (cpustate->gb_speed));   \
50               if ( cpustate->timer_expired_func ) {         \
51                  cpustate->timer_expired_func( cpustate->device, X );      \
52               }
45#define IME     0x01
46#define HALTED  0x02
5347
54typedef struct _lr35902_state {
55   UINT8 A;
56   UINT8 F;
57   UINT8 B;
58   UINT8 C;
59   UINT8 D;
60   UINT8 E;
61   UINT8 H;
62   UINT8 L;
6348
64   UINT16 SP;
65   UINT16 PC;
66   /* Interrupt related */
67   UINT8   IE;
68   UINT8   IF;
69   int   irq_state;
70   int   ei_delay;
71   device_irq_callback irq_callback;
72   legacy_cpu_device *device;
73   address_space *program;
74   int icount;
75   /* Timer stuff */
76   lr35902_timer_fired_func timer_expired_func;
77   /* Fetch & execute related */
78   int      execution_state;
79   UINT8   op;
80   /* Others */
81   int gb_speed;
82   int gb_speed_change_pending;
83   int enable;
84   int doHALTbug;
85   UINT8   features;
86   const lr35902_cpu_core *config;
87} lr35902_state;
49//**************************************************************************
50//  LR35902 DEVICE
51//**************************************************************************
8852
89INLINE lr35902_state *get_safe_token(device_t *device)
53const device_type LR35902 = &device_creator<lr35902_cpu_device>;
54
55
56lr35902_cpu_device::lr35902_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
57   : cpu_device(mconfig, LR35902, "LR35902", tag, owner, clock),
58    m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0)
9059{
91   assert(device != NULL);
92   assert(device->type() == LR35902);
93   return (lr35902_state *)downcast<legacy_cpu_device *>(device)->token();
60   c_regs = NULL;
61   c_features = 0;
62   c_timer_expired_func = NULL;
9463}
9564
96typedef int (*OpcodeEmulator) (lr35902_state *cpustate);
9765
98#define IME     0x01
99#define HALTED   0x02
66void lr35902_cpu_device::static_set_config(device_t &device, const lr35902_config &config)
67{
68   lr35902_cpu_device &conf = downcast<lr35902_cpu_device &>(device);
69   static_cast<lr35902_config &>(conf) = config;
70}
10071
72
10173/****************************************************************************/
10274/* Memory functions                                                         */
10375/****************************************************************************/
10476
105#define mem_ReadByte(cs,A)      ((UINT8)(cs)->program->read_byte(A)); CYCLES_PASSED(4);
106#define mem_WriteByte(cs,A,V)   ((cs)->program->write_byte(A,V)); CYCLES_PASSED(4);
77inline void lr35902_cpu_device::cycles_passed(UINT8 cycles)
78{
79   m_icount -= cycles / m_gb_speed;
80   if ( m_timer_expired_func )
81   {
82      m_timer_expired_func( this, cycles );
83   }
84}
10785
108INLINE UINT8 mem_ReadOp(lr35902_state *cpustate)
86
87inline UINT8 lr35902_cpu_device::mem_read_byte( UINT16 addr )
10988{
110   UINT8 r = mem_ReadByte (cpustate, cpustate->PC++);
111   return r;
89   UINT8 data = m_program->read_byte( addr );
90   cycles_passed( 4 );
91   return data;
11292}
11393
114INLINE UINT16 mem_ReadWord (lr35902_state *cpustate, UINT32 address)
94
95inline void lr35902_cpu_device::mem_write_byte( UINT16 addr, UINT8 data )
11596{
116   UINT16 value = mem_ReadByte (cpustate, (address + 1) & 0xffff);
117   value <<= 8;
118   value |= mem_ReadByte (cpustate, address);
119   return value;
97   m_program->write_byte( addr, data );
98   cycles_passed( 4 );
12099}
121100
122INLINE void mem_WriteWord (lr35902_state *cpustate, UINT32 address, UINT16 value)
101
102inline UINT16 lr35902_cpu_device::mem_read_word( UINT16 addr )
123103{
124   mem_WriteByte (cpustate, address, value & 0xFF);
125   mem_WriteByte (cpustate, (address + 1) & 0xffff, value >> 8);
104   UINT16 data = mem_read_byte( addr );
105   data |= ( mem_read_byte( addr + 1 ) << 8 );
106   return data;
126107}
127108
128static CPU_INIT( lr35902 )
109
110inline void lr35902_cpu_device::mem_write_word( UINT16 addr, UINT16 data )
129111{
130   lr35902_state *cpustate = get_safe_token(device);
112   mem_write_byte( addr, data & 0xFF );
113   mem_write_byte( addr + 1, data >> 8 );
114}
131115
132   cpustate->config = (const lr35902_cpu_core *) device->static_config();
133   cpustate->irq_callback = irqcallback;
134   cpustate->device = device;
135   cpustate->program = device->space(AS_PROGRAM);
116
117void lr35902_cpu_device::device_start()
118{
119   m_device = this;
120   m_program = this->space(AS_PROGRAM);
121
122   save_item(NAME(m_A));
123   save_item(NAME(m_F));
124   save_item(NAME(m_B));
125   save_item(NAME(m_C));
126   save_item(NAME(m_D));
127   save_item(NAME(m_E));
128   save_item(NAME(m_H));
129   save_item(NAME(m_L));
130   save_item(NAME(m_PC));
131   save_item(NAME(m_SP));
132   save_item(NAME(m_IE));
133   save_item(NAME(m_IF));
134   save_item(NAME(m_irq_state));
135   save_item(NAME(m_ei_delay));
136   save_item(NAME(m_execution_state));
137   save_item(NAME(m_op));
138   save_item(NAME(m_gb_speed));
139   save_item(NAME(m_gb_speed_change_pending));
140   save_item(NAME(m_enable));
141   save_item(NAME(m_doHALTbug));
142
143   // Register state for debugger
144   state_add( LR35902_PC, "PC", m_PC ).callimport().callexport().formatstr("%04X");
145   state_add( LR35902_SP, "SP", m_SP ).callimport().callexport().formatstr("%04X");
146   state_add( LR35902_A,  "A",  m_A  ).callimport().callexport().formatstr("%02X");
147   state_add( LR35902_F,  "F",  m_F  ).callimport().callexport().formatstr("%02X");
148   state_add( LR35902_B,  "B",  m_B  ).callimport().callexport().formatstr("%02X");
149   state_add( LR35902_C,  "C",  m_C  ).callimport().callexport().formatstr("%02X");
150   state_add( LR35902_D,  "D",  m_D  ).callimport().callexport().formatstr("%02X");
151   state_add( LR35902_E,  "E",  m_E  ).callimport().callexport().formatstr("%02X");
152   state_add( LR35902_H,  "H",  m_H  ).callimport().callexport().formatstr("%02X");
153   state_add( LR35902_L,  "L",  m_L  ).callimport().callexport().formatstr("%02X");
154   state_add( LR35902_IRQ_STATE, "IRQ", m_enable ).callimport().callexport().formatstr("%02X");
155   state_add( LR35902_IE, "IE", m_IE ).callimport().callexport().formatstr("%02X");
156   state_add( LR35902_IF, "IF", m_IF ).callimport().callexport().formatstr("%02X");
157
158   state_add(STATE_GENPC, "curpc", m_PC).callimport().callexport().formatstr("%8s").noshow();
159   state_add(STATE_GENFLAGS, "GENFLAGS",  m_F).mask(0xf0).formatstr("%8s").noshow();
160   
161   m_icountptr = &m_icount;
136162}
137163
164
165void lr35902_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
166{
167   switch (entry.index())
168   {
169      case LR35902_SPEED:
170         string.printf("%02X", 0x7E | ( ( m_gb_speed - 1 ) << 7 ) | m_gb_speed_change_pending );
171         break;
172
173      case STATE_GENFLAGS:
174         string.printf("%c%c%c%c",
175            m_F & FLAG_Z   ? 'Z' : '.',
176            m_F & FLAG_N   ? 'N' : '.',
177            m_F & FLAG_H   ? 'H' : '.',
178            m_F & FLAG_C   ? 'C' : '.'
179         );
180         break;
181   }
182}
183
138184/*** Reset lr353902 registers: ******************************/
139185/*** This function can be used to reset the register      ***/
140186/*** file before starting execution with lr35902_execute(cpustate)***/
141187/*** It sets the registers to their initial values.       ***/
142188/************************************************************/
143static CPU_RESET( lr35902 )
189void lr35902_cpu_device::device_reset()
144190{
145   lr35902_state *cpustate = get_safe_token(device);
146
147   cpustate->A = 0x00;
148   cpustate->F = 0x00;
149   cpustate->B = 0x00;
150   cpustate->C = 0x00;
151   cpustate->D = 0x00;
152   cpustate->E = 0x00;
153   cpustate->H = 0x00;
154   cpustate->L = 0x00;
155   cpustate->SP = 0x0000;
156   cpustate->PC = 0x0000;
157   cpustate->timer_expired_func = NULL;
158   cpustate->features = LR35902_FEATURE_HALT_BUG;
159   if (cpustate->config)
160   {
161      if ( cpustate->config->regs ) {
162         cpustate->A = cpustate->config->regs[0] >> 8;
163         cpustate->F = cpustate->config->regs[0] & 0xFF;
164         cpustate->B = cpustate->config->regs[1] >> 8;
165         cpustate->C = cpustate->config->regs[1] & 0xFF;
166         cpustate->D = cpustate->config->regs[2] >> 8;
167         cpustate->E = cpustate->config->regs[2] & 0xFF;
168         cpustate->H = cpustate->config->regs[3] >> 8;
169         cpustate->L = cpustate->config->regs[3] & 0xFF;
170         cpustate->SP = cpustate->config->regs[4];
171         cpustate->PC = cpustate->config->regs[5];
172      }
173      cpustate->timer_expired_func = cpustate->config->timer_expired_func;
174      cpustate->features = cpustate->config->features;
191   m_A = 0x00;
192   m_F = 0x00;
193   m_B = 0x00;
194   m_C = 0x00;
195   m_D = 0x00;
196   m_E = 0x00;
197   m_H = 0x00;
198   m_L = 0x00;
199   m_SP = 0x0000;
200   m_PC = 0x0000;
201   m_timer_expired_func = NULL;
202   m_features = LR35902_FEATURE_HALT_BUG;
203   if ( c_regs ) {
204      m_A = c_regs[0] >> 8;
205      m_F = c_regs[0] & 0xFF;
206      m_B = c_regs[1] >> 8;
207      m_C = c_regs[1] & 0xFF;
208      m_D = c_regs[2] >> 8;
209      m_E = c_regs[2] & 0xFF;
210      m_H = c_regs[3] >> 8;
211      m_L = c_regs[3] & 0xFF;
212      m_SP = c_regs[4];
213      m_PC = c_regs[5];
175214   }
176   cpustate->enable = 0;
177   cpustate->IE = 0;
178   cpustate->IF = 0;
215   m_timer_expired_func = c_timer_expired_func;
216   m_features = c_features;
179217
180   cpustate->execution_state = 0;
181   cpustate->doHALTbug = 0;
182   cpustate->ei_delay = 0;
183   cpustate->gb_speed_change_pending = 0;
184   cpustate->gb_speed = 1;
218   m_enable = 0;
219   m_IE = 0;
220   m_IF = 0;
221
222   m_execution_state = 0;
223   m_doHALTbug = 0;
224   m_ei_delay = 0;
225   m_gb_speed_change_pending = 0;
226   m_gb_speed = 1;
185227}
186228
187INLINE void lr35902_ProcessInterrupts (lr35902_state *cpustate)
229
230offs_t lr35902_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
188231{
189   UINT8 irq = cpustate->IE & cpustate->IF;
232   extern CPU_DISASSEMBLE( lr35902 );
233   return CPU_DISASSEMBLE_NAME( lr35902 )(NULL, buffer, pc, oprom, opram, 0);
234}
190235
236
237void lr35902_cpu_device::check_interrupts()
238{
239   UINT8 irq = m_IE & m_IF;
240
191241   /* Interrupts should be taken after the first instruction after an EI instruction */
192   if (cpustate->ei_delay) {
193      cpustate->ei_delay = 0;
242   if (m_ei_delay) {
243      m_ei_delay = 0;
194244      return;
195245   }
196246
197247   /*
198248       logerror("Attempting to process LR35902 Interrupt IRQ $%02X\n", irq);
199       logerror("Attempting to process LR35902 Interrupt IE $%02X\n", cpustate->IE);
200       logerror("Attempting to process LR35902 Interrupt IF $%02X\n", cpustate->IF);
249       logerror("Attempting to process LR35902 Interrupt IE $%02X\n", m_IE);
250       logerror("Attempting to process LR35902 Interrupt IF $%02X\n", m_IF);
201251    */
202252   if (irq)
203253   {
r14642r14643
210260      {
211261         if( irq & (1<<irqline) )
212262         {
213            if (cpustate->enable & HALTED)
263            if (m_enable & HALTED)
214264            {
215               cpustate->enable &= ~HALTED;
216               cpustate->PC++;
217               if ( cpustate->features & LR35902_FEATURE_HALT_BUG ) {
218                  if ( ! ( cpustate->enable & IME ) ) {
265               m_enable &= ~HALTED;
266               m_PC++;
267               if ( m_features & LR35902_FEATURE_HALT_BUG ) {
268                  if ( ! ( m_enable & IME ) ) {
219269                     /* Old cpu core (dmg/mgb/sgb) */
220                     cpustate->doHALTbug = 1;
270                     m_doHALTbug = 1;
221271                  }
222272               } else {
223273                  /* New cpu core (cgb/agb/ags) */
224274                  /* Adjust for internal syncing with video core */
225275                  /* This feature needs more investigation */
226276                  if ( irqline < 2 ) {
227                     CYCLES_PASSED( 4 );
277                     cycles_passed( 4 );
228278                  }
229279               }
230280            }
231            if ( cpustate->enable & IME ) {
232               if ( cpustate->irq_callback )
233                  (*cpustate->irq_callback)(cpustate->device, irqline);
234               cpustate->enable &= ~IME;
235               cpustate->IF &= ~(1 << irqline);
236               CYCLES_PASSED( 12 );
237               cpustate->SP -= 2;
238               mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
239               cpustate->PC = 0x40 + irqline * 8;
240               /*logerror("LR35902 Interrupt PC $%04X\n", cpustate->PC );*/
281            if ( m_enable & IME ) {
282               m_enable &= ~IME;
283               m_IF &= ~(1 << irqline);
284               cycles_passed( 12 );
285               m_SP -= 2;
286               mem_write_word( m_SP, m_PC );
287               m_PC = 0x40 + irqline * 8;
288               /*logerror("LR35902 Interrupt PC $%04X\n", m_PC );*/
241289               return;
242290            }
243291         }
r14642r14643
245293   }
246294}
247295
296
248297/************************************************************/
249298/*** Execute lr35902 code for cycles cycles, return nr of ***/
250299/*** cycles actually executed.                            ***/
251300/************************************************************/
252static CPU_EXECUTE( lr35902 )
301void lr35902_cpu_device::execute_run()
253302{
254   lr35902_state *cpustate = get_safe_token(device);
255
256303   do
257304   {
258      if ( cpustate->execution_state ) {
305      if ( m_execution_state ) {
259306         UINT8   x;
260307         /* Execute instruction */
261         switch( cpustate->op ) {
308         switch( m_op ) {
262309#include "opc_main.h"
263310         }
264311      } else {
265312         /* Fetch and count cycles */
266         lr35902_ProcessInterrupts (cpustate);
267         debugger_instruction_hook(device, cpustate->PC);
268         if ( cpustate->enable & HALTED ) {
269            CYCLES_PASSED( 4 );
270            cpustate->execution_state = 1;
313         check_interrupts();
314         debugger_instruction_hook(this, m_PC);
315         if ( m_enable & HALTED ) {
316            cycles_passed( 4 );
317            m_execution_state = 1;
271318         } else {
272            cpustate->op = mem_ReadOp (cpustate);
273            if ( cpustate->doHALTbug ) {
274               cpustate->PC--;
275               cpustate->doHALTbug = 0;
319            m_op = mem_read_byte( m_PC++ );
320            if ( m_doHALTbug ) {
321               m_PC--;
322               m_doHALTbug = 0;
276323            }
277324         }
278325      }
279      cpustate->execution_state ^= 1;
280   } while (cpustate->icount > 0);
326      m_execution_state ^= 1;
327   } while (m_icount > 0);
281328}
282329
283static CPU_BURN( lr35902 )
284{
285   lr35902_state *cpustate = get_safe_token(device);
286330
287    if( cycles > 0 )
288    {
289        /* NOP takes 4 cycles per instruction */
290        int n = (cycles + 3) / 4;
291        cpustate->icount -= 4 * n;
292    }
293}
294
295static void lr35902_set_irq_line (lr35902_state *cpustate, int irqline, int state)
331void lr35902_cpu_device::execute_set_input( int inptnum, int state )
296332{
297   /*logerror("setting irq line 0x%02x state 0x%08x\n", irqline, state);*/
298   //if( cpustate->irq_state == state )
299   //  return;
300
301   cpustate->irq_state = state;
333   m_irq_state = state;
302334   if( state == ASSERT_LINE )
303335   {
304
305      cpustate->IF |= (0x01 << irqline);
306      /*logerror("LR35902 assert irq line %d ($%02X)\n", irqline, cpustate->IF);*/
307
336      m_IF |= (0x01 << inptnum);
308337   }
309338   else
310339   {
311
312      cpustate->IF &= ~(0x01 << irqline);
313      /*logerror("LR35902 clear irq line %d ($%02X)\n", irqline, cpustate->IF);*/
314
340      m_IF &= ~(0x01 << inptnum);
315341   }
316342}
317343
318#ifdef UNUSED_FUNCTION
319static void lr35902_clear_pending_interrupts (lr35902_state *cpustate)
320{
321    cpustate->IF = 0;
322}
323#endif
324344
325static CPU_SET_INFO( lr35902 )
345UINT8 lr35902_cpu_device::get_speed()
326346{
327   lr35902_state *cpustate = get_safe_token(device);
328
329   switch (state)
330   {
331   /* --- the following bits of info are set as 64-bit signed integers --- */
332   case CPUINFO_INT_INPUT_STATE + 0:
333   case CPUINFO_INT_INPUT_STATE + 1:
334   case CPUINFO_INT_INPUT_STATE + 2:
335   case CPUINFO_INT_INPUT_STATE + 3:
336   case CPUINFO_INT_INPUT_STATE + 4:         lr35902_set_irq_line(cpustate, state-CPUINFO_INT_INPUT_STATE, info->i); break;
337
338   case CPUINFO_INT_SP:                  cpustate->SP = info->i;                  break;
339   case CPUINFO_INT_PC:                  cpustate->PC = info->i;                  break;
340
341   case CPUINFO_INT_REGISTER + LR35902_PC:      cpustate->PC = info->i;                  break;
342   case CPUINFO_INT_REGISTER + LR35902_SP:      cpustate->SP = info->i;                  break;
343   case CPUINFO_INT_REGISTER + LR35902_AF:      cpustate->A = info->i >> 8; cpustate->F = info->i & 0xFF;      break;
344   case CPUINFO_INT_REGISTER + LR35902_BC:      cpustate->B = info->i >> 8; cpustate->C = info->i & 0xFF;      break;
345   case CPUINFO_INT_REGISTER + LR35902_DE:      cpustate->D = info->i >> 8; cpustate->E = info->i & 0xFF;      break;
346   case CPUINFO_INT_REGISTER + LR35902_HL:      cpustate->H = info->i >> 8; cpustate->L = info->i & 0xFF;      break;
347   case CPUINFO_INT_REGISTER + LR35902_IE:      cpustate->IE = info->i; break;
348   case CPUINFO_INT_REGISTER + LR35902_IF:      cpustate->IF = info->i; break;
349   case CPUINFO_INT_REGISTER + LR35902_SPEED:   cpustate->gb_speed_change_pending = info->i & 0x01; break;
350   }
347   return 0x7E | ( ( m_gb_speed - 1 ) << 7 ) | m_gb_speed_change_pending;
351348}
352349
353CPU_GET_INFO( lr35902 )
354{
355   lr35902_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
356350
357   switch (state)
358   {
359   /* --- the following bits of info are returned as 64-bit signed integers --- */
360   case CPUINFO_INT_CONTEXT_SIZE:               info->i = sizeof(lr35902_state);               break;
361   case CPUINFO_INT_INPUT_LINES:                  info->i = 5;                     break;
362   case CPUINFO_INT_DEFAULT_IRQ_VECTOR:         info->i = 0xff;                     break;
363   case DEVINFO_INT_ENDIANNESS:               info->i = ENDIANNESS_LITTLE;               break;
364   case CPUINFO_INT_CLOCK_MULTIPLIER:            info->i = 1;                     break;
365   case CPUINFO_INT_CLOCK_DIVIDER:               info->i = 1;                     break;
366   case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 1;                     break;
367   case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 4;                     break;
368   case CPUINFO_INT_MIN_CYCLES:               info->i = 1;   /* right? */         break;
369   case CPUINFO_INT_MAX_CYCLES:               info->i = 16;   /* right? */         break;
370
371   case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM:   info->i = 8;               break;
372   case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16;               break;
373   case DEVINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;               break;
374   case DEVINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;               break;
375   case DEVINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;               break;
376   case DEVINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;               break;
377   case DEVINFO_INT_DATABUS_WIDTH + AS_IO:      info->i = 8;               break;
378   case DEVINFO_INT_ADDRBUS_WIDTH + AS_IO:      info->i = 16;               break;
379   case DEVINFO_INT_ADDRBUS_SHIFT + AS_IO:      info->i = 0;               break;
380
381   case CPUINFO_INT_SP:                     info->i = cpustate->SP;               break;
382   case CPUINFO_INT_PC:                     info->i = cpustate->PC;               break;
383   case CPUINFO_INT_PREVIOUSPC:               info->i = 0;   /* TODO??? */         break;
384
385   case CPUINFO_INT_INPUT_STATE + 0:
386   case CPUINFO_INT_INPUT_STATE + 1:
387   case CPUINFO_INT_INPUT_STATE + 2:
388   case CPUINFO_INT_INPUT_STATE + 3:
389   case CPUINFO_INT_INPUT_STATE + 4:               info->i = cpustate->IF & (1 << (state-CPUINFO_INT_INPUT_STATE)); break;
390
391   case CPUINFO_INT_REGISTER + LR35902_PC:         info->i = cpustate->PC;               break;
392   case CPUINFO_INT_REGISTER + LR35902_SP:         info->i = cpustate->SP;               break;
393   case CPUINFO_INT_REGISTER + LR35902_AF:         info->i = ( cpustate->A << 8 ) | cpustate->F;               break;
394   case CPUINFO_INT_REGISTER + LR35902_BC:         info->i = ( cpustate->B << 8 ) | cpustate->C;               break;
395   case CPUINFO_INT_REGISTER + LR35902_DE:         info->i = ( cpustate->D << 8 ) | cpustate->E;               break;
396   case CPUINFO_INT_REGISTER + LR35902_HL:         info->i = ( cpustate->H << 8 ) | cpustate->L;               break;
397   case CPUINFO_INT_REGISTER + LR35902_IE:         info->i = cpustate->IE;               break;
398   case CPUINFO_INT_REGISTER + LR35902_IF:         info->i = cpustate->IF;               break;
399   case CPUINFO_INT_REGISTER + LR35902_SPEED:      info->i = 0x7E | ( ( cpustate->gb_speed - 1 ) << 7 ) | cpustate->gb_speed_change_pending; break;
400
401   /* --- the following bits of info are returned as pointers to data or functions --- */
402   case CPUINFO_FCT_SET_INFO:                  info->setinfo = CPU_SET_INFO_NAME(lr35902);      break;
403   case CPUINFO_FCT_INIT:                     info->init = CPU_INIT_NAME(lr35902);            break;
404   case CPUINFO_FCT_RESET:                     info->reset = CPU_RESET_NAME(lr35902);         break;
405   case CPUINFO_FCT_EXECUTE:                  info->execute = CPU_EXECUTE_NAME(lr35902);      break;
406   case CPUINFO_FCT_BURN:                     info->burn = CPU_BURN_NAME(lr35902);            break;
407   case CPUINFO_FCT_DISASSEMBLE:               info->disassemble = CPU_DISASSEMBLE_NAME(lr35902);      break;
408   case CPUINFO_PTR_INSTRUCTION_COUNTER:         info->icount = &cpustate->icount;         break;
409
410   /* --- the following bits of info are returned as NULL-terminated strings --- */
411   case DEVINFO_STR_NAME:                     strcpy(info->s, "LR35902"); break;
412   case DEVINFO_STR_FAMILY:               strcpy(info->s, "Sharp LR35902"); break;
413   case DEVINFO_STR_VERSION:               strcpy(info->s, "1.4"); break;
414   case DEVINFO_STR_SOURCE_FILE:               strcpy(info->s, __FILE__); break;
415   case DEVINFO_STR_CREDITS:               strcpy(info->s, "Copyright The MESS Team."); break;
416
417   case CPUINFO_STR_FLAGS:
418      sprintf(info->s, "%c%c%c%c%c%c%c%c",
419         cpustate->F & 0x80 ? 'Z':'.',
420         cpustate->F & 0x40 ? 'N':'.',
421         cpustate->F & 0x20 ? 'H':'.',
422         cpustate->F & 0x10 ? 'C':'.',
423         cpustate->F & 0x08 ? '3':'.',
424         cpustate->F & 0x04 ? '2':'.',
425         cpustate->F & 0x02 ? '1':'.',
426         cpustate->F & 0x01 ? '0':'.');
427      break;
428
429   case CPUINFO_STR_REGISTER + LR35902_PC: sprintf(info->s, "PC:%04X", cpustate->PC); break;
430   case CPUINFO_STR_REGISTER + LR35902_SP: sprintf(info->s, "SP:%04X", cpustate->SP); break;
431   case CPUINFO_STR_REGISTER + LR35902_AF: sprintf(info->s, "AF:%02X%02X", cpustate->A, cpustate->F); break;
432   case CPUINFO_STR_REGISTER + LR35902_BC: sprintf(info->s, "BC:%02X%02X", cpustate->B, cpustate->C); break;
433   case CPUINFO_STR_REGISTER + LR35902_DE: sprintf(info->s, "DE:%02X%02X", cpustate->D, cpustate->E); break;
434   case CPUINFO_STR_REGISTER + LR35902_HL: sprintf(info->s, "HL:%02X%02X", cpustate->H, cpustate->L); break;
435   case CPUINFO_STR_REGISTER + LR35902_IRQ_STATE: sprintf(info->s, "IRQ:%X", cpustate->enable & IME ); break;
436   case CPUINFO_STR_REGISTER + LR35902_IE: sprintf(info->s, "IE:%02X", cpustate->IE); break;
437   case CPUINFO_STR_REGISTER + LR35902_IF: sprintf(info->s, "IF:%02X", cpustate->IF); break;
438   case CPUINFO_STR_REGISTER + LR35902_SPEED: sprintf(info->s, "SPD:%02x", 0x7E | ( ( cpustate->gb_speed - 1 ) << 7 ) | cpustate->gb_speed_change_pending ); break;
439   }
351void lr35902_cpu_device::set_speed( UINT8 speed_request )
352{
353   m_gb_speed_change_pending = speed_request & 0x01;
440354}
441355
442DEFINE_LEGACY_CPU_DEVICE(LR35902, lr35902);
src/emu/cpu/lr35902/lr35902.h
r14642r14643
44#define __LR35902_H__
55
66
7typedef void (*lr35902_timer_fired_func)(device_t *device, int cycles);
7#define MCFG_LR35902_CONFIG(_config) \
8   lr35902_cpu_device::static_set_config(*device, _config);
89
9typedef struct _lr35902_cpu_core lr35902_cpu_core;
10struct _lr35902_cpu_core
10class lr35902_cpu_device;
11
12// Perhaps replace this with a standard device callback
13typedef void (*lr35902_timer_fired_func)(lr35902_cpu_device *device, int cycles);
14
15struct lr35902_config
1116{
12   const UINT16   *regs;
13   UINT8         features;
14   lr35902_timer_fired_func timer_expired_func;
17   const UINT16   *c_regs;
18   UINT8         c_features;
19   lr35902_timer_fired_func c_timer_expired_func;
1520};
1621
1722enum
1823{
19   LR35902_PC=1, LR35902_SP, LR35902_AF, LR35902_BC, LR35902_DE, LR35902_HL,
24   LR35902_PC=1, LR35902_SP, LR35902_A, LR35902_F, LR35902_B, LR35902_C, LR35902_D, LR35902_E, LR35902_H, LR35902_L,
2025   LR35902_IRQ_STATE,
2126   /* Pseudo registers to keep track of the interrupt statuses */
2227   LR35902_IE, LR35902_IF,
r14642r14643
2429   LR35902_SPEED,
2530};
2631
32// This and the features configuration could be removed if we introduce proper subclasses
2733#define LR35902_FEATURE_HALT_BUG   0x01
2834
29/****************************************************************************/
30/* Return register contents                                                 */
31/****************************************************************************/
32DECLARE_LEGACY_CPU_DEVICE(LR35902, lr35902);
3335
34extern CPU_DISASSEMBLE( lr35902 );
36class lr35902_cpu_device :   public cpu_device,
37                     public lr35902_config
38{
39public:
40   // construction/destruction
41   lr35902_cpu_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
3542
43   static void static_set_config(device_t &device, const lr35902_config &config);
44
45   UINT8 get_speed();
46   void set_speed( UINT8 speed_request );
47
48   UINT8 get_ie() { return m_IE; }
49   void set_ie( UINT8 data ) { m_IE = data; }
50
51   UINT8 get_if() { return m_IF; }
52   void set_if( UINT8 data ) { m_IF = data; }
53
54protected:
55   // device-level overrides
56   virtual void device_start();
57   virtual void device_reset();
58
59   // device_execute_interface overrides
60   virtual UINT32 execute_min_cycles() const { return 1; }
61   virtual UINT32 execute_max_cycles() const { return 16; }
62   virtual UINT32 execute_input_lines() const { return 5; }
63   virtual void execute_run();
64   virtual void execute_set_input(int inputnum, int state);
65
66   // device_memory_interface overrides
67   virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
68
69   // device_state_interface overrides
70   void state_string_export(const device_state_entry &entry, astring &string);
71
72   // device_disasm_interface overrides
73   virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
74   virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
75   virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
76
77   inline void cycles_passed(UINT8 cycles);
78   inline UINT8 mem_read_byte(UINT16 addr);
79   inline void mem_write_byte(UINT16 addr, UINT8 data);
80   inline UINT16 mem_read_word(UINT16 addr);
81   inline void mem_write_word(UINT16 addr, UINT16 data);
82   inline void check_interrupts();
83
84protected:
85   address_space_config m_program_config;
86
87   UINT8 m_A;
88   UINT8 m_F;
89   UINT8 m_B;
90   UINT8 m_C;
91   UINT8 m_D;
92   UINT8 m_E;
93   UINT8 m_H;
94   UINT8 m_L;
95
96   UINT16 m_SP;
97   UINT16 m_PC;
98   /* Interrupt related */
99   UINT8   m_IE;
100   UINT8   m_IF;
101   int   m_irq_state;
102   int   m_ei_delay;
103   lr35902_cpu_device *m_device;
104   address_space *m_program;
105   int m_icount;
106   /* Timer stuff */
107   lr35902_timer_fired_func m_timer_expired_func;
108   /* Fetch & execute related */
109   int      m_execution_state;
110   UINT8   m_op;
111   /* Others */
112   int m_gb_speed;
113   int m_gb_speed_change_pending;
114   int m_enable;
115   int m_doHALTbug;
116   UINT8   m_features;
117   const struct lr35902_config *m_config;
118
119   /* Flag bit definitions */
120   static const UINT8 FLAG_Z = 0x80;
121   static const UINT8 FLAG_N = 0x40;
122   static const UINT8 FLAG_H = 0x20;
123   static const UINT8 FLAG_C = 0x10;
124};
125
126extern const device_type LR35902;
127
36128#endif /* __LR35902_H__ */
src/emu/cpu/lr35902/opc_cb.h
r14642r14643
88      f=0;               \
99   if( (x)==0 )            \
1010      f|=FLAG_Z;            \
11   cpustate->F=f;         \
11   m_F=f;         \
1212}
1313
1414#define   RL_8BIT(x)            \
1515{                        \
1616   register UINT8 r;         \
1717   r=((x)&0x80)?FLAG_C:0;      \
18   (x)=(UINT8)(((x)<<1)|((cpustate->F&FLAG_C)?1:0));    \
18   (x)=(UINT8)(((x)<<1)|((m_F&FLAG_C)?1:0));    \
1919   if( (x)==0 )            \
2020      r|=FLAG_Z;            \
21   cpustate->F=r;         \
21   m_F=r;         \
2222}
2323
2424#define   RRC_8BIT(x)            \
r14642r14643
3131      f=0;               \
3232   if( (x)==0 )            \
3333      f|=FLAG_Z;            \
34   cpustate->F=f;         \
34   m_F=f;         \
3535}
3636
3737#define   RR_8BIT(x)            \
3838{                        \
3939   register UINT8 r;         \
4040   r=((x)&1)?FLAG_C:0;         \
41   (x)=(UINT8)(((x)>>1)|((cpustate->F&FLAG_C)?0x80:0));    \
41   (x)=(UINT8)(((x)>>1)|((m_F&FLAG_C)?0x80:0));    \
4242   if( (x)==0 )            \
4343      r|=FLAG_Z;            \
44   cpustate->F=r;         \
44   m_F=r;         \
4545}
4646
4747#define   SLA_8BIT(x)            \
r14642r14643
5454   (x)<<=1;               \
5555   if( (x)==0 )            \
5656      f|=FLAG_Z;            \
57   cpustate->F=f;         \
57   m_F=f;         \
5858}
5959
6060#define   SRA_8BIT(x)            \
r14642r14643
6767   (x)=(UINT8)(((char)(x))>>1);    \
6868   if( (x)==0 )            \
6969      f|=FLAG_Z;            \
70   cpustate->F=f;         \
70   m_F=f;         \
7171}
7272
7373#define   SWAP_8BIT(x)         \
7474   (x)=(UINT8)(((x)>>4)|((x)<<4));     \
7575   if( (x)==0 )            \
76      cpustate->F=FLAG_Z;   \
76      m_F=FLAG_Z;   \
7777   else                  \
78      cpustate->F=0;
78      m_F=0;
7979
8080
8181#define   SRL_8BIT(x)            \
r14642r14643
8888   (x)>>=1;               \
8989   if( (x)==0 )            \
9090      f|=FLAG_Z;            \
91   cpustate->F=f;         \
91   m_F=f;         \
9292}
9393
9494#define   BIT_8BIT(n,x)         \
9595   if( (x)&(1<<(n)) )         \
96      cpustate->F=(UINT8)(FLAG_H|(cpustate->F&FLAG_C));  \
96      m_F=(UINT8)(FLAG_H|(m_F&FLAG_C));  \
9797   else                  \
98      cpustate->F=(UINT8)(FLAG_Z|FLAG_H|(cpustate->F&FLAG_C));
98      m_F=(UINT8)(FLAG_Z|FLAG_H|(m_F&FLAG_C));
9999
100100#define   RES_8BIT(n,x)   (x)&=~(1<<(n));
101101
r14642r14643
105105case 0x00:
106106  /*      RLC B */
107107
108  RLC_8BIT (cpustate->B)
108  RLC_8BIT (m_B)
109109  break;
110110case 0x01:
111111  /*      RLC C */
112112
113  RLC_8BIT (cpustate->C)
113  RLC_8BIT (m_C)
114114  break;
115115case 0x02:
116116  /*      RLC D */
117117
118  RLC_8BIT (cpustate->D)
118  RLC_8BIT (m_D)
119119  break;
120120case 0x03:
121121  /*      RLC E */
122122
123  RLC_8BIT (cpustate->E)
123  RLC_8BIT (m_E)
124124  break;
125125case 0x04:
126126  /*      RLC H */
127127
128  RLC_8BIT (cpustate->H)
128  RLC_8BIT (m_H)
129129  break;
130130case 0x05:
131131  /*      RLC L */
132132
133  RLC_8BIT (cpustate->L)
133  RLC_8BIT (m_L)
134134  break;
135135case 0x06:
136136   /*      RLC (HL) */
137137   {
138      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
138      UINT16 addr = ( m_H << 8 ) | m_L;
139139
140      x = mem_ReadByte (cpustate, addr);
140      x = mem_read_byte( addr );
141141      RLC_8BIT (x)
142      mem_WriteByte (cpustate, addr, x);
142      mem_write_byte( addr, x );
143143   }
144144   break;
145145case 0x07:
146146  /*      RLC A */
147147
148  RLC_8BIT (cpustate->A)
148  RLC_8BIT (m_A)
149149  break;
150150case 0x08:
151151  /*      RRC B */
152152
153  RRC_8BIT (cpustate->B)
153  RRC_8BIT (m_B)
154154  break;
155155case 0x09:
156156  /*      RRC C */
157157
158  RRC_8BIT (cpustate->C)
158  RRC_8BIT (m_C)
159159  break;
160160case 0x0A:
161161  /*      RRC D */
162162
163  RRC_8BIT (cpustate->D)
163  RRC_8BIT (m_D)
164164  break;
165165case 0x0B:
166166  /*      RRC E */
167167
168  RRC_8BIT (cpustate->E)
168  RRC_8BIT (m_E)
169169  break;
170170case 0x0C:
171171  /*      RRC H */
172172
173  RRC_8BIT (cpustate->H)
173  RRC_8BIT (m_H)
174174  break;
175175case 0x0D:
176176  /*      RRC L */
177177
178  RRC_8BIT (cpustate->L)
178  RRC_8BIT (m_L)
179179  break;
180180case 0x0E:
181181   /*      RRC (HL) */
182182   {
183      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
183      UINT16 addr = ( m_H << 8 ) | m_L;
184184
185      x = mem_ReadByte (cpustate, addr);
185      x = mem_read_byte( addr);
186186      RRC_8BIT (x)
187      mem_WriteByte (cpustate, addr, x);
187      mem_write_byte( addr, x);
188188   }
189189   break;
190190case 0x0F:
191191  /*      RRC A */
192192
193  RRC_8BIT (cpustate->A)
193  RRC_8BIT (m_A)
194194  break;
195195case 0x10:
196196  /*      RL B */
197197
198  RL_8BIT (cpustate->B)
198  RL_8BIT (m_B)
199199  break;
200200case 0x11:
201201  /*      RL C */
202202
203  RL_8BIT (cpustate->C)
203  RL_8BIT (m_C)
204204  break;
205205case 0x12:
206206  /*      RL D */
207207
208  RL_8BIT (cpustate->D)
208  RL_8BIT (m_D)
209209  break;
210210case 0x13:
211211  /*      RL E */
212212
213  RL_8BIT (cpustate->E)
213  RL_8BIT (m_E)
214214  break;
215215case 0x14:
216216  /*      RL H */
217217
218  RL_8BIT (cpustate->H)
218  RL_8BIT (m_H)
219219  break;
220220case 0x15:
221221  /*      RL L */
222222
223  RL_8BIT (cpustate->L)
223  RL_8BIT (m_L)
224224  break;
225225case 0x16:
226226   /*      RL (HL) */
227227   {
228      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
228      UINT16 addr = ( m_H << 8 ) | m_L;
229229
230      x = mem_ReadByte (cpustate, addr);
230      x = mem_read_byte( addr);
231231      RL_8BIT (x)
232      mem_WriteByte (cpustate, addr, x);
232      mem_write_byte( addr, x);
233233   }
234234   break;
235235case 0x17:
236236  /*      RL A */
237237
238  RL_8BIT (cpustate->A)
238  RL_8BIT (m_A)
239239  break;
240240case 0x18:
241241  /*      RR B */
242242
243  RR_8BIT (cpustate->B)
243  RR_8BIT (m_B)
244244  break;
245245case 0x19:
246246  /*      RR C */
247247
248  RR_8BIT (cpustate->C)
248  RR_8BIT (m_C)
249249  break;
250250case 0x1A:
251251  /*      RR D */
252252
253  RR_8BIT (cpustate->D)
253  RR_8BIT (m_D)
254254  break;
255255case 0x1B:
256256  /*      RR E */
257257
258  RR_8BIT (cpustate->E)
258  RR_8BIT (m_E)
259259  break;
260260case 0x1C:
261261  /*      RR H */
262262
263  RR_8BIT (cpustate->H)
263  RR_8BIT (m_H)
264264  break;
265265case 0x1D:
266266  /*      RR L */
267267
268  RR_8BIT (cpustate->L)
268  RR_8BIT (m_L)
269269  break;
270270case 0x1E:
271271   /*      RR (HL) */
272272   {
273      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
273      UINT16 addr = ( m_H << 8 ) | m_L;
274274
275      x = mem_ReadByte (cpustate, addr);
275      x = mem_read_byte( addr);
276276      RR_8BIT (x)
277      mem_WriteByte (cpustate, addr, x);
277      mem_write_byte( addr, x);
278278   }
279279   break;
280280case 0x1F:
281281  /*      RR A */
282282
283  RR_8BIT (cpustate->A)
283  RR_8BIT (m_A)
284284  break;
285285case 0x20:
286286  /*      SLA B */
287287
288  SLA_8BIT (cpustate->B)
288  SLA_8BIT (m_B)
289289  break;
290290case 0x21:
291291  /*      SLA C */
292292
293  SLA_8BIT (cpustate->C)
293  SLA_8BIT (m_C)
294294  break;
295295case 0x22:
296296  /*      SLA D */
297297
298  SLA_8BIT (cpustate->D)
298  SLA_8BIT (m_D)
299299  break;
300300case 0x23:
301301  /*      SLA E */
302302
303  SLA_8BIT (cpustate->E)
303  SLA_8BIT (m_E)
304304  break;
305305case 0x24:
306306  /*      SLA H */
307307
308  SLA_8BIT (cpustate->H)
308  SLA_8BIT (m_H)
309309  break;
310310case 0x25:
311311  /*      SLA L */
312312
313  SLA_8BIT (cpustate->L)
313  SLA_8BIT (m_L)
314314  break;
315315case 0x26:
316316   /*      SLA (HL) */
317317   {
318      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
318      UINT16 addr = ( m_H << 8 ) | m_L;
319319
320      x = mem_ReadByte (cpustate, addr);
320      x = mem_read_byte( addr);
321321      SLA_8BIT (x)
322      mem_WriteByte (cpustate, addr, x);
322      mem_write_byte( addr, x);
323323   }
324324   break;
325325case 0x27:
326326  /*      SLA A */
327327
328  SLA_8BIT (cpustate->A)
328  SLA_8BIT (m_A)
329329  break;
330330case 0x28:
331331  /*      SRA B */
332332
333  SRA_8BIT (cpustate->B)
333  SRA_8BIT (m_B)
334334  break;
335335case 0x29:
336336  /*      SRA C */
337337
338  SRA_8BIT (cpustate->C)
338  SRA_8BIT (m_C)
339339  break;
340340case 0x2A:
341341  /*      SRA D */
342342
343  SRA_8BIT (cpustate->D)
343  SRA_8BIT (m_D)
344344  break;
345345case 0x2B:
346346  /*      SRA E */
347347
348  SRA_8BIT (cpustate->E)
348  SRA_8BIT (m_E)
349349  break;
350350case 0x2C:
351351  /*      SRA H */
352352
353  SRA_8BIT (cpustate->H)
353  SRA_8BIT (m_H)
354354  break;
355355case 0x2D:
356356  /*      SRA L */
357357
358  SRA_8BIT (cpustate->L)
358  SRA_8BIT (m_L)
359359  break;
360360case 0x2E:
361361   /*      SRA (HL) */
362362   {
363      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
363      UINT16 addr = ( m_H << 8 ) | m_L;
364364
365      x = mem_ReadByte (cpustate, addr);
365      x = mem_read_byte( addr);
366366      SRA_8BIT (x)
367      mem_WriteByte (cpustate, addr, x);
367      mem_write_byte( addr, x);
368368   }
369369   break;
370370case 0x2F:
371371  /*      SRA A */
372372
373  SRA_8BIT (cpustate->A)
373  SRA_8BIT (m_A)
374374  break;
375375case 0x30:
376376  /*      SWAP B */
377377
378  SWAP_8BIT (cpustate->B)
378  SWAP_8BIT (m_B)
379379  break;
380380case 0x31:
381381  /*      SWAP C */
382382
383  SWAP_8BIT (cpustate->C)
383  SWAP_8BIT (m_C)
384384  break;
385385case 0x32:
386386  /*      SWAP D */
387387
388  SWAP_8BIT (cpustate->D)
388  SWAP_8BIT (m_D)
389389  break;
390390case 0x33:
391391  /*      SWAP E */
392392
393  SWAP_8BIT (cpustate->E)
393  SWAP_8BIT (m_E)
394394  break;
395395case 0x34:
396396  /*      SWAP H */
397397
398  SWAP_8BIT (cpustate->H)
398  SWAP_8BIT (m_H)
399399  break;
400400case 0x35:
401401  /*      SWAP L */
402402
403  SWAP_8BIT (cpustate->L)
403  SWAP_8BIT (m_L)
404404  break;
405405case 0x36:
406406   /*      SWAP (HL) */
407407   {
408      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
408      UINT16 addr = ( m_H << 8 ) | m_L;
409409
410      x = mem_ReadByte (cpustate, addr);
410      x = mem_read_byte( addr);
411411      SWAP_8BIT (x)
412      mem_WriteByte (cpustate, addr, x);
412      mem_write_byte( addr, x);
413413   }
414414   break;
415415case 0x37:
416416  /*      SWAP A */
417417
418  SWAP_8BIT (cpustate->A)
418  SWAP_8BIT (m_A)
419419  break;
420420case 0x38:
421421  /*      SRL B */
422422
423  SRL_8BIT (cpustate->B)
423  SRL_8BIT (m_B)
424424  break;
425425case 0x39:
426426  /*      SRL C */
427427
428  SRL_8BIT (cpustate->C)
428  SRL_8BIT (m_C)
429429  break;
430430case 0x3A:
431431  /*      SRL D */
432432
433  SRL_8BIT (cpustate->D)
433  SRL_8BIT (m_D)
434434  break;
435435case 0x3B:
436436  /*      SRL E */
437437
438  SRL_8BIT (cpustate->E)
438  SRL_8BIT (m_E)
439439  break;
440440case 0x3C:
441441  /*      SRL H */
442442
443  SRL_8BIT (cpustate->H)
443  SRL_8BIT (m_H)
444444  break;
445445case 0x3D:
446446  /*      SRL L */
447447
448  SRL_8BIT (cpustate->L)
448  SRL_8BIT (m_L)
449449  break;
450450case 0x3E:
451451   /*      SRL (HL) */
452452   {
453      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
453      UINT16 addr = ( m_H << 8 ) | m_L;
454454
455      x = mem_ReadByte (cpustate, addr);
455      x = mem_read_byte( addr);
456456      SRL_8BIT (x)
457      mem_WriteByte (cpustate, addr, x);
457      mem_write_byte( addr, x);
458458   }
459459   break;
460460case 0x3F:
461461  /*      SRL A */
462462
463  SRL_8BIT (cpustate->A)
463  SRL_8BIT (m_A)
464464  break;
465465case 0x40:
466466  /*      BIT 0,B */
467467
468  BIT_8BIT (0, cpustate->B)
468  BIT_8BIT (0, m_B)
469469  break;
470470case 0x41:
471471  /*      BIT 0,C */
472472
473  BIT_8BIT (0, cpustate->C)
473  BIT_8BIT (0, m_C)
474474  break;
475475case 0x42:
476476  /*      BIT 0,D */
477477
478  BIT_8BIT (0, cpustate->D)
478  BIT_8BIT (0, m_D)
479479  break;
480480case 0x43:
481481  /*      BIT 0,E */
482482
483  BIT_8BIT (0, cpustate->E)
483  BIT_8BIT (0, m_E)
484484  break;
485485case 0x44:
486486  /*      BIT 0,H */
487487
488  BIT_8BIT (0, cpustate->H)
488  BIT_8BIT (0, m_H)
489489  break;
490490case 0x45:
491491  /*      BIT 0,L */
492492
493  BIT_8BIT (0, cpustate->L)
493  BIT_8BIT (0, m_L)
494494  break;
495495case 0x46:
496496   /*      BIT 0,(HL) */
497497   {
498      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
498      UINT16 addr = ( m_H << 8 ) | m_L;
499499
500      x = mem_ReadByte (cpustate, addr);
500      x = mem_read_byte( addr);
501501      BIT_8BIT (0, x)
502502   }
503503   break;
504504case 0x47:
505505  /*      BIT 0,A */
506506
507  BIT_8BIT (0, cpustate->A)
507  BIT_8BIT (0, m_A)
508508  break;
509509case 0x48:
510510  /*      BIT 1,B */
511511
512  BIT_8BIT (1, cpustate->B)
512  BIT_8BIT (1, m_B)
513513  break;
514514case 0x49:
515515  /*      BIT 1,C */
516516
517  BIT_8BIT (1, cpustate->C)
517  BIT_8BIT (1, m_C)
518518  break;
519519case 0x4A:
520520  /*      BIT 1,D */
521521
522  BIT_8BIT (1, cpustate->D)
522  BIT_8BIT (1, m_D)
523523  break;
524524case 0x4B:
525525  /*      BIT 1,E */
526526
527  BIT_8BIT (1, cpustate->E)
527  BIT_8BIT (1, m_E)
528528  break;
529529case 0x4C:
530530  /*      BIT 1,H */
531531
532  BIT_8BIT (1, cpustate->H)
532  BIT_8BIT (1, m_H)
533533  break;
534534case 0x4D:
535535  /*      BIT 1,L */
536536
537  BIT_8BIT (1, cpustate->L)
537  BIT_8BIT (1, m_L)
538538  break;
539539case 0x4E:
540540   /*      BIT 1,(HL) */
541541   {
542      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
542      UINT16 addr = ( m_H << 8 ) | m_L;
543543
544      x = mem_ReadByte (cpustate, addr);
544      x = mem_read_byte( addr);
545545      BIT_8BIT (1, x)
546546   }
547547   break;
548548case 0x4F:
549549  /*      BIT 1,A */
550550
551  BIT_8BIT (1, cpustate->A)
551  BIT_8BIT (1, m_A)
552552  break;
553553case 0x50:
554554  /*      BIT 2,B */
555555
556  BIT_8BIT (2, cpustate->B)
556  BIT_8BIT (2, m_B)
557557  break;
558558case 0x51:
559559  /*      BIT 2,C */
560560
561  BIT_8BIT (2, cpustate->C)
561  BIT_8BIT (2, m_C)
562562  break;
563563case 0x52:
564564  /*      BIT 2,D */
565565
566  BIT_8BIT (2, cpustate->D)
566  BIT_8BIT (2, m_D)
567567  break;
568568case 0x53:
569569  /*      BIT 2,E */
570570
571  BIT_8BIT (2, cpustate->E)
571  BIT_8BIT (2, m_E)
572572  break;
573573case 0x54:
574574  /*      BIT 2,H */
575575
576  BIT_8BIT (2, cpustate->H)
576  BIT_8BIT (2, m_H)
577577  break;
578578case 0x55:
579579  /*      BIT 2,L */
580580
581  BIT_8BIT (2, cpustate->L)
581  BIT_8BIT (2, m_L)
582582  break;
583583case 0x56:
584584   /*      BIT 2,(HL) */
585585   {
586      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
586      UINT16 addr = ( m_H << 8 ) | m_L;
587587
588      x = mem_ReadByte (cpustate, addr);
588      x = mem_read_byte( addr);
589589      BIT_8BIT (2, x)
590590   }
591591   break;
592592case 0x57:
593593  /*      BIT 2,A */
594594
595  BIT_8BIT (2, cpustate->A)
595  BIT_8BIT (2, m_A)
596596  break;
597597case 0x58:
598598  /*      BIT 3,B */
599599
600  BIT_8BIT (3, cpustate->B)
600  BIT_8BIT (3, m_B)
601601  break;
602602case 0x59:
603603  /*      BIT 3,C */
604604
605  BIT_8BIT (3, cpustate->C)
605  BIT_8BIT (3, m_C)
606606  break;
607607case 0x5A:
608608  /*      BIT 3,D */
609609
610  BIT_8BIT (3, cpustate->D)
610  BIT_8BIT (3, m_D)
611611  break;
612612case 0x5B:
613613  /*      BIT 3,E */
614614
615  BIT_8BIT (3, cpustate->E)
615  BIT_8BIT (3, m_E)
616616  break;
617617case 0x5C:
618618  /*      BIT 3,H */
619619
620  BIT_8BIT (3, cpustate->H)
620  BIT_8BIT (3, m_H)
621621  break;
622622case 0x5D:
623623  /*      BIT 3,L */
624624
625  BIT_8BIT (3, cpustate->L)
625  BIT_8BIT (3, m_L)
626626  break;
627627case 0x5E:
628628   /*      BIT 3,(HL) */
629629   {
630      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
630      UINT16 addr = ( m_H << 8 ) | m_L;
631631
632      x = mem_ReadByte (cpustate, addr);
632      x = mem_read_byte( addr);
633633      BIT_8BIT (3, x)
634634   }
635635   break;
636636case 0x5F:
637637  /*      BIT 3,A */
638638
639  BIT_8BIT (3, cpustate->A)
639  BIT_8BIT (3, m_A)
640640  break;
641641case 0x60:
642642  /*      BIT 4,B */
643643
644  BIT_8BIT (4, cpustate->B)
644  BIT_8BIT (4, m_B)
645645  break;
646646case 0x61:
647647  /*      BIT 4,C */
648648
649  BIT_8BIT (4, cpustate->C)
649  BIT_8BIT (4, m_C)
650650  break;
651651case 0x62:
652652  /*      BIT 4,D */
653653
654  BIT_8BIT (4, cpustate->D)
654  BIT_8BIT (4, m_D)
655655  break;
656656case 0x63:
657657  /*      BIT 4,E */
658658
659  BIT_8BIT (4, cpustate->E)
659  BIT_8BIT (4, m_E)
660660  break;
661661case 0x64:
662662  /*      BIT 4,H */
663663
664  BIT_8BIT (4, cpustate->H)
664  BIT_8BIT (4, m_H)
665665  break;
666666case 0x65:
667667  /*      BIT 4,L */
668668
669  BIT_8BIT (4, cpustate->L)
669  BIT_8BIT (4, m_L)
670670  break;
671671case 0x66:
672672   /*      BIT 4,(HL) */
673673   {
674      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
674      UINT16 addr = ( m_H << 8 ) | m_L;
675675
676      x = mem_ReadByte (cpustate, addr);
676      x = mem_read_byte( addr);
677677      BIT_8BIT (4, x)
678678   }
679679   break;
680680case 0x67:
681681  /*      BIT 4,A */
682682
683  BIT_8BIT (4, cpustate->A)
683  BIT_8BIT (4, m_A)
684684  break;
685685case 0x68:
686686  /*      BIT 5,B */
687687
688  BIT_8BIT (5, cpustate->B)
688  BIT_8BIT (5, m_B)
689689  break;
690690case 0x69:
691691  /*      BIT 5,C */
692692
693  BIT_8BIT (5, cpustate->C)
693  BIT_8BIT (5, m_C)
694694  break;
695695case 0x6A:
696696  /*      BIT 5,D */
697697
698  BIT_8BIT (5, cpustate->D)
698  BIT_8BIT (5, m_D)
699699  break;
700700case 0x6B:
701701  /*      BIT 5,E */
702702
703  BIT_8BIT (5, cpustate->E)
703  BIT_8BIT (5, m_E)
704704  break;
705705case 0x6C:
706706  /*      BIT 5,H */
707707
708  BIT_8BIT (5, cpustate->H)
708  BIT_8BIT (5, m_H)
709709  break;
710710case 0x6D:
711711  /*      BIT 5,L */
712712
713  BIT_8BIT (5, cpustate->L)
713  BIT_8BIT (5, m_L)
714714  break;
715715case 0x6E:
716716   /*      BIT 5,(HL) */
717717   {
718      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
718      UINT16 addr = ( m_H << 8 ) | m_L;
719719
720      x = mem_ReadByte (cpustate, addr);
720      x = mem_read_byte( addr);
721721      BIT_8BIT (5, x)
722722   }
723723   break;
724724case 0x6F:
725725  /*      BIT 5,A */
726726
727  BIT_8BIT (5, cpustate->A)
727  BIT_8BIT (5, m_A)
728728  break;
729729case 0x70:
730730  /*      BIT 6,B */
731731
732  BIT_8BIT (6, cpustate->B)
732  BIT_8BIT (6, m_B)
733733  break;
734734case 0x71:
735735  /*      BIT 6,C */
736736
737  BIT_8BIT (6, cpustate->C)
737  BIT_8BIT (6, m_C)
738738  break;
739739case 0x72:
740740  /*      BIT 6,D */
741741
742  BIT_8BIT (6, cpustate->D)
742  BIT_8BIT (6, m_D)
743743  break;
744744case 0x73:
745745  /*      BIT 6,E */
746746
747  BIT_8BIT (6, cpustate->E)
747  BIT_8BIT (6, m_E)
748748  break;
749749case 0x74:
750750  /*      BIT 6,H */
751751
752  BIT_8BIT (6, cpustate->H)
752  BIT_8BIT (6, m_H)
753753  break;
754754case 0x75:
755755  /*      BIT 6,L */
756756
757  BIT_8BIT (6, cpustate->L)
757  BIT_8BIT (6, m_L)
758758  break;
759759case 0x76:
760760   /*      BIT 6,(HL) */
761761   {
762      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
762      UINT16 addr = ( m_H << 8 ) | m_L;
763763
764      x = mem_ReadByte (cpustate, addr);
764      x = mem_read_byte( addr);
765765      BIT_8BIT (6, x)
766766   }
767767   break;
768768case 0x77:
769769  /*      BIT 6,A */
770770
771  BIT_8BIT (6, cpustate->A)
771  BIT_8BIT (6, m_A)
772772  break;
773773case 0x78:
774774  /*      BIT 7,B */
775775
776  BIT_8BIT (7, cpustate->B)
776  BIT_8BIT (7, m_B)
777777  break;
778778case 0x79:
779779  /*      BIT 7,C */
780780
781  BIT_8BIT (7, cpustate->C)
781  BIT_8BIT (7, m_C)
782782  break;
783783case 0x7A:
784784  /*      BIT 7,D */
785785
786  BIT_8BIT (7, cpustate->D)
786  BIT_8BIT (7, m_D)
787787  break;
788788case 0x7B:
789789  /*      BIT 7,E */
790790
791  BIT_8BIT (7, cpustate->E)
791  BIT_8BIT (7, m_E)
792792  break;
793793case 0x7C:
794794  /*      BIT 7,H */
795795
796  BIT_8BIT (7, cpustate->H)
796  BIT_8BIT (7, m_H)
797797  break;
798798case 0x7D:
799799  /*      BIT 7,L */
800800
801  BIT_8BIT (7, cpustate->L)
801  BIT_8BIT (7, m_L)
802802  break;
803803case 0x7E:
804804   /*      BIT 7,(HL) */
805805   {
806      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
806      UINT16 addr = ( m_H << 8 ) | m_L;
807807
808      x = mem_ReadByte (cpustate, addr);
808      x = mem_read_byte( addr);
809809      BIT_8BIT (7, x)
810810   }
811811   break;
812812case 0x7F:
813813  /*      BIT 7,A */
814814
815  BIT_8BIT (7, cpustate->A)
815  BIT_8BIT (7, m_A)
816816  break;
817817case 0x80:
818818  /*      RES 0,B */
819819
820  RES_8BIT (0, cpustate->B)
820  RES_8BIT (0, m_B)
821821  break;
822822case 0x81:
823823  /*      RES 0,C */
824824
825  RES_8BIT (0, cpustate->C)
825  RES_8BIT (0, m_C)
826826  break;
827827case 0x82:
828828  /*      RES 0,D */
829829
830  RES_8BIT (0, cpustate->D)
830  RES_8BIT (0, m_D)
831831  break;
832832case 0x83:
833833  /*      RES 0,E */
834834
835  RES_8BIT (0, cpustate->E)
835  RES_8BIT (0, m_E)
836836  break;
837837case 0x84:
838838  /*      RES 0,H */
839839
840  RES_8BIT (0, cpustate->H)
840  RES_8BIT (0, m_H)
841841  break;
842842case 0x85:
843843  /*      RES 0,L */
844844
845  RES_8BIT (0, cpustate->L)
845  RES_8BIT (0, m_L)
846846  break;
847847case 0x86:
848848   /*      RES 0,(HL) */
849849   {
850      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
850      UINT16 addr = ( m_H << 8 ) | m_L;
851851
852      x = mem_ReadByte (cpustate, addr);
852      x = mem_read_byte( addr);
853853      RES_8BIT (0, x)
854      mem_WriteByte (cpustate, addr, x);
854      mem_write_byte( addr, x);
855855   }
856856   break;
857857case 0x87:
858858  /*      RES 0,A */
859859
860  RES_8BIT (0, cpustate->A)
860  RES_8BIT (0, m_A)
861861  break;
862862case 0x88:
863863  /*      RES 1,B */
864864
865  RES_8BIT (1, cpustate->B)
865  RES_8BIT (1, m_B)
866866  break;
867867case 0x89:
868868  /*      RES 1,C */
869869
870  RES_8BIT (1, cpustate->C)
870  RES_8BIT (1, m_C)
871871  break;
872872case 0x8A:
873873  /*      RES 1,D */
874874
875  RES_8BIT (1, cpustate->D)
875  RES_8BIT (1, m_D)
876876  break;
877877case 0x8B:
878878  /*      RES 1,E */
879879
880  RES_8BIT (1, cpustate->E)
880  RES_8BIT (1, m_E)
881881  break;
882882case 0x8C:
883883  /*      RES 1,H */
884884
885  RES_8BIT (1, cpustate->H)
885  RES_8BIT (1, m_H)
886886  break;
887887case 0x8D:
888888  /*      RES 1,L */
889889
890  RES_8BIT (1, cpustate->L)
890  RES_8BIT (1, m_L)
891891  break;
892892case 0x8E:
893893   /*      RES 1,(HL) */
894894   {
895      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
895      UINT16 addr = ( m_H << 8 ) | m_L;
896896
897      x = mem_ReadByte (cpustate, addr);
897      x = mem_read_byte( addr);
898898      RES_8BIT (1, x)
899      mem_WriteByte (cpustate, addr, x);
899      mem_write_byte( addr, x);
900900   }
901901   break;
902902case 0x8F:
903903  /*      RES 1,A */
904904
905  RES_8BIT (1, cpustate->A)
905  RES_8BIT (1, m_A)
906906  break;
907907case 0x90:
908908  /*      RES 2,B */
909909
910  RES_8BIT (2, cpustate->B)
910  RES_8BIT (2, m_B)
911911  break;
912912case 0x91:
913913  /*      RES 2,C */
914914
915  RES_8BIT (2, cpustate->C)
915  RES_8BIT (2, m_C)
916916  break;
917917case 0x92:
918918  /*      RES 2,D */
919919
920  RES_8BIT (2, cpustate->D)
920  RES_8BIT (2, m_D)
921921  break;
922922case 0x93:
923923  /*      RES 2,E */
924924
925  RES_8BIT (2, cpustate->E)
925  RES_8BIT (2, m_E)
926926  break;
927927case 0x94:
928928  /*      RES 2,H */
929929
930  RES_8BIT (2, cpustate->H)
930  RES_8BIT (2, m_H)
931931  break;
932932case 0x95:
933933  /*      RES 2,L */
934934
935  RES_8BIT (2, cpustate->L)
935  RES_8BIT (2, m_L)
936936  break;
937937case 0x96:
938938   /*      RES 2,(HL) */
939939   {
940      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
940      UINT16 addr = ( m_H << 8 ) | m_L;
941941
942      x = mem_ReadByte (cpustate, addr);
942      x = mem_read_byte( addr);
943943      RES_8BIT (2, x)
944      mem_WriteByte (cpustate, addr, x);
944      mem_write_byte( addr, x);
945945   }
946946   break;
947947case 0x97:
948948  /*      RES 2,A */
949949
950  RES_8BIT (2, cpustate->A)
950  RES_8BIT (2, m_A)
951951  break;
952952case 0x98:
953953  /*      RES 3,B */
954954
955  RES_8BIT (3, cpustate->B)
955  RES_8BIT (3, m_B)
956956  break;
957957case 0x99:
958958  /*      RES 3,C */
959959
960  RES_8BIT (3, cpustate->C)
960  RES_8BIT (3, m_C)
961961  break;
962962case 0x9A:
963963  /*      RES 3,D */
964964
965  RES_8BIT (3, cpustate->D)
965  RES_8BIT (3, m_D)
966966  break;
967967case 0x9B:
968968  /*      RES 3,E */
969969
970  RES_8BIT (3, cpustate->E)
970  RES_8BIT (3, m_E)
971971  break;
972972case 0x9C:
973973  /*      RES 3,H */
974974
975  RES_8BIT (3, cpustate->H)
975  RES_8BIT (3, m_H)
976976  break;
977977case 0x9D:
978978  /*      RES 3,L */
979979
980  RES_8BIT (3, cpustate->L)
980  RES_8BIT (3, m_L)
981981  break;
982982case 0x9E:
983983   /*      RES 3,(HL) */
984984   {
985      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
985      UINT16 addr = ( m_H << 8 ) | m_L;
986986
987      x = mem_ReadByte (cpustate, addr);
987      x = mem_read_byte( addr);
988988      RES_8BIT (3, x)
989      mem_WriteByte (cpustate, addr, x);
989      mem_write_byte( addr, x);
990990   }
991991   break;
992992case 0x9F:
993993  /*      RES 3,A */
994994
995  RES_8BIT (3, cpustate->A)
995  RES_8BIT (3, m_A)
996996  break;
997997case 0xA0:
998998  /*      RES 4,B */
999999
1000  RES_8BIT (4, cpustate->B)
1000  RES_8BIT (4, m_B)
10011001  break;
10021002case 0xA1:
10031003  /*      RES 4,C */
10041004
1005  RES_8BIT (4, cpustate->C)
1005  RES_8BIT (4, m_C)
10061006  break;
10071007case 0xA2:
10081008  /*      RES 4,D */
10091009
1010  RES_8BIT (4, cpustate->D)
1010  RES_8BIT (4, m_D)
10111011  break;
10121012case 0xA3:
10131013  /*      RES 4,E */
10141014
1015  RES_8BIT (4, cpustate->E)
1015  RES_8BIT (4, m_E)
10161016  break;
10171017case 0xA4:
10181018  /*      RES 4,H */
10191019
1020  RES_8BIT (4, cpustate->H)
1020  RES_8BIT (4, m_H)
10211021  break;
10221022case 0xA5:
10231023  /*      RES 4,L */
10241024
1025  RES_8BIT (4, cpustate->L)
1025  RES_8BIT (4, m_L)
10261026  break;
10271027case 0xA6:
10281028   /*      RES 4,(HL) */
10291029   {
1030      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1030      UINT16 addr = ( m_H << 8 ) | m_L;
10311031
1032      x = mem_ReadByte (cpustate, addr);
1032      x = mem_read_byte( addr);
10331033      RES_8BIT (4, x)
1034      mem_WriteByte (cpustate, addr, x);
1034      mem_write_byte( addr, x);
10351035   }
10361036   break;
10371037case 0xA7:
10381038  /*      RES 4,A */
10391039
1040  RES_8BIT (4, cpustate->A)
1040  RES_8BIT (4, m_A)
10411041  break;
10421042case 0xA8:
10431043  /*      RES 5,B */
10441044
1045  RES_8BIT (5, cpustate->B)
1045  RES_8BIT (5, m_B)
10461046  break;
10471047case 0xA9:
10481048  /*      RES 5,C */
10491049
1050  RES_8BIT (5, cpustate->C)
1050  RES_8BIT (5, m_C)
10511051  break;
10521052case 0xAA:
10531053  /*      RES 5,D */
10541054
1055  RES_8BIT (5, cpustate->D)
1055  RES_8BIT (5, m_D)
10561056  break;
10571057case 0xAB:
10581058  /*      RES 5,E */
10591059
1060  RES_8BIT (5, cpustate->E)
1060  RES_8BIT (5, m_E)
10611061  break;
10621062case 0xAC:
10631063  /*      RES 5,H */
10641064
1065  RES_8BIT (5, cpustate->H)
1065  RES_8BIT (5, m_H)
10661066  break;
10671067case 0xAD:
10681068  /*      RES 5,L */
10691069
1070  RES_8BIT (5, cpustate->L)
1070  RES_8BIT (5, m_L)
10711071  break;
10721072case 0xAE:
10731073   /*      RES 5,(HL) */
10741074   {
1075      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1075      UINT16 addr = ( m_H << 8 ) | m_L;
10761076
1077      x = mem_ReadByte (cpustate, addr);
1077      x = mem_read_byte( addr);
10781078      RES_8BIT (5, x)
1079      mem_WriteByte (cpustate, addr, x);
1079      mem_write_byte( addr, x);
10801080   }
10811081   break;
10821082case 0xAF:
10831083  /*      RES 5,A */
10841084
1085  RES_8BIT (5, cpustate->A)
1085  RES_8BIT (5, m_A)
10861086  break;
10871087case 0xB0:
10881088  /*      RES 6,B */
10891089
1090  RES_8BIT (6, cpustate->B)
1090  RES_8BIT (6, m_B)
10911091  break;
10921092case 0xB1:
10931093  /*      RES 6,C */
10941094
1095  RES_8BIT (6, cpustate->C)
1095  RES_8BIT (6, m_C)
10961096  break;
10971097case 0xB2:
10981098  /*      RES 6,D */
10991099
1100  RES_8BIT (6, cpustate->D)
1100  RES_8BIT (6, m_D)
11011101  break;
11021102case 0xB3:
11031103  /*      RES 6,E */
11041104
1105  RES_8BIT (6, cpustate->E)
1105  RES_8BIT (6, m_E)
11061106  break;
11071107case 0xB4:
11081108  /*      RES 6,H */
11091109
1110  RES_8BIT (6, cpustate->H)
1110  RES_8BIT (6, m_H)
11111111  break;
11121112case 0xB5:
11131113  /*      RES 6,L */
11141114
1115  RES_8BIT (6, cpustate->L)
1115  RES_8BIT (6, m_L)
11161116  break;
11171117case 0xB6:
11181118   /*      RES 6,(HL) */
11191119   {
1120      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1120      UINT16 addr = ( m_H << 8 ) | m_L;
11211121
1122      x = mem_ReadByte (cpustate, addr);
1122      x = mem_read_byte( addr);
11231123      RES_8BIT (6, x)
1124      mem_WriteByte (cpustate, addr, x);
1124      mem_write_byte( addr, x);
11251125   }
11261126   break;
11271127case 0xB7:
11281128  /*      RES 6,A */
11291129
1130  RES_8BIT (6, cpustate->A)
1130  RES_8BIT (6, m_A)
11311131  break;
11321132case 0xB8:
11331133  /*      RES 7,B */
11341134
1135  RES_8BIT (7, cpustate->B)
1135  RES_8BIT (7, m_B)
11361136  break;
11371137case 0xB9:
11381138  /*      RES 7,C */
11391139
1140  RES_8BIT (7, cpustate->C)
1140  RES_8BIT (7, m_C)
11411141  break;
11421142case 0xBA:
11431143  /*      RES 7,D */
11441144
1145  RES_8BIT (7, cpustate->D)
1145  RES_8BIT (7, m_D)
11461146  break;
11471147case 0xBB:
11481148  /*      RES 7,E */
11491149
1150  RES_8BIT (7, cpustate->E)
1150  RES_8BIT (7, m_E)
11511151  break;
11521152case 0xBC:
11531153  /*      RES 7,H */
11541154
1155  RES_8BIT (7, cpustate->H)
1155  RES_8BIT (7, m_H)
11561156  break;
11571157case 0xBD:
11581158  /*      RES 7,L */
11591159
1160  RES_8BIT (7, cpustate->L)
1160  RES_8BIT (7, m_L)
11611161  break;
11621162case 0xBE:
11631163   /*      RES 7,(HL) */
11641164   {
1165      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1165      UINT16 addr = ( m_H << 8 ) | m_L;
11661166
1167      x = mem_ReadByte (cpustate, addr);
1167      x = mem_read_byte( addr);
11681168      RES_8BIT (7, x)
1169      mem_WriteByte (cpustate, addr, x);
1169      mem_write_byte( addr, x);
11701170   }
11711171   break;
11721172case 0xBF:
11731173  /*      RES 7,A */
11741174
1175  RES_8BIT (7, cpustate->A)
1175  RES_8BIT (7, m_A)
11761176  break;
11771177case 0xC0:
11781178  /*      SET 0,B */
11791179
1180  SET_8BIT (0, cpustate->B)
1180  SET_8BIT (0, m_B)
11811181  break;
11821182case 0xC1:
11831183  /*      SET 0,C */
11841184
1185  SET_8BIT (0, cpustate->C)
1185  SET_8BIT (0, m_C)
11861186  break;
11871187case 0xC2:
11881188  /*      SET 0,D */
11891189
1190  SET_8BIT (0, cpustate->D)
1190  SET_8BIT (0, m_D)
11911191  break;
11921192case 0xC3:
11931193  /*      SET 0,E */
11941194
1195  SET_8BIT (0, cpustate->E)
1195  SET_8BIT (0, m_E)
11961196  break;
11971197case 0xC4:
11981198  /*      SET 0,H */
11991199
1200  SET_8BIT (0, cpustate->H)
1200  SET_8BIT (0, m_H)
12011201  break;
12021202case 0xC5:
12031203  /*      SET 0,L */
12041204
1205  SET_8BIT (0, cpustate->L)
1205  SET_8BIT (0, m_L)
12061206  break;
12071207case 0xC6:
12081208   /*      SET 0,(HL) */
12091209   {
1210      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1210      UINT16 addr = ( m_H << 8 ) | m_L;
12111211
1212      x = mem_ReadByte (cpustate, addr);
1212      x = mem_read_byte( addr);
12131213      SET_8BIT (0, x)
1214      mem_WriteByte (cpustate, addr, x);
1214      mem_write_byte( addr, x);
12151215   }
12161216   break;
12171217case 0xC7:
12181218  /*      SET 0,A */
12191219
1220  SET_8BIT (0, cpustate->A)
1220  SET_8BIT (0, m_A)
12211221  break;
12221222case 0xC8:
12231223  /*      SET 1,B */
12241224
1225  SET_8BIT (1, cpustate->B)
1225  SET_8BIT (1, m_B)
12261226  break;
12271227case 0xC9:
12281228  /*      SET 1,C */
12291229
1230  SET_8BIT (1, cpustate->C)
1230  SET_8BIT (1, m_C)
12311231  break;
12321232case 0xCA:
12331233  /*      SET 1,D */
12341234
1235  SET_8BIT (1, cpustate->D)
1235  SET_8BIT (1, m_D)
12361236  break;
12371237case 0xCB:
12381238  /*      SET 1,E */
12391239
1240  SET_8BIT (1, cpustate->E)
1240  SET_8BIT (1, m_E)
12411241  break;
12421242case 0xCC:
12431243  /*      SET 1,H */
12441244
1245  SET_8BIT (1, cpustate->H)
1245  SET_8BIT (1, m_H)
12461246  break;
12471247case 0xCD:
12481248  /*      SET 1,L */
12491249
1250  SET_8BIT (1, cpustate->L)
1250  SET_8BIT (1, m_L)
12511251  break;
12521252case 0xCE:
12531253   /*      SET 1,(HL) */
12541254   {
1255      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1255      UINT16 addr = ( m_H << 8 ) | m_L;
12561256
1257      x = mem_ReadByte (cpustate, addr);
1257      x = mem_read_byte( addr);
12581258      SET_8BIT (1, x)
1259      mem_WriteByte (cpustate, addr, x);
1259      mem_write_byte( addr, x);
12601260   }
12611261   break;
12621262case 0xCF:
12631263  /*      SET 1,A */
12641264
1265  SET_8BIT (1, cpustate->A)
1265  SET_8BIT (1, m_A)
12661266  break;
12671267case 0xD0:
12681268  /*      SET 2,B */
12691269
1270  SET_8BIT (2, cpustate->B)
1270  SET_8BIT (2, m_B)
12711271  break;
12721272case 0xD1:
12731273  /*      SET 2,C */
12741274
1275  SET_8BIT (2, cpustate->C)
1275  SET_8BIT (2, m_C)
12761276  break;
12771277case 0xD2:
12781278  /*      SET 2,D */
12791279
1280  SET_8BIT (2, cpustate->D)
1280  SET_8BIT (2, m_D)
12811281  break;
12821282case 0xD3:
12831283  /*      SET 2,E */
12841284
1285  SET_8BIT (2, cpustate->E)
1285  SET_8BIT (2, m_E)
12861286  break;
12871287case 0xD4:
12881288  /*      SET 2,H */
12891289
1290  SET_8BIT (2, cpustate->H)
1290  SET_8BIT (2, m_H)
12911291  break;
12921292case 0xD5:
12931293  /*      SET 2,L */
12941294
1295  SET_8BIT (2, cpustate->L)
1295  SET_8BIT (2, m_L)
12961296  break;
12971297case 0xD6:
12981298   /*      SET 2,(HL) */
12991299   {
1300      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1300      UINT16 addr = ( m_H << 8 ) | m_L;
13011301
1302      x = mem_ReadByte (cpustate, addr);
1302      x = mem_read_byte( addr);
13031303      SET_8BIT (2, x)
1304      mem_WriteByte (cpustate, addr, x);
1304      mem_write_byte( addr, x);
13051305   }
13061306   break;
13071307case 0xD7:
13081308  /*      SET 2,A */
13091309
1310  SET_8BIT (2, cpustate->A)
1310  SET_8BIT (2, m_A)
13111311  break;
13121312case 0xD8:
13131313  /*      SET 3,B */
13141314
1315  SET_8BIT (3, cpustate->B)
1315  SET_8BIT (3, m_B)
13161316  break;
13171317case 0xD9:
13181318  /*      SET 3,C */
13191319
1320  SET_8BIT (3, cpustate->C)
1320  SET_8BIT (3, m_C)
13211321  break;
13221322case 0xDA:
13231323  /*      SET 3,D */
13241324
1325  SET_8BIT (3, cpustate->D)
1325  SET_8BIT (3, m_D)
13261326  break;
13271327case 0xDB:
13281328  /*      SET 3,E */
13291329
1330  SET_8BIT (3, cpustate->E)
1330  SET_8BIT (3, m_E)
13311331  break;
13321332case 0xDC:
13331333  /*      SET 3,H */
13341334
1335  SET_8BIT (3, cpustate->H)
1335  SET_8BIT (3, m_H)
13361336  break;
13371337case 0xDD:
13381338  /*      SET 3,L */
13391339
1340  SET_8BIT (3, cpustate->L)
1340  SET_8BIT (3, m_L)
13411341  break;
13421342case 0xDE:
13431343   /*      SET 3,(HL) */
13441344   {
1345      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1345      UINT16 addr = ( m_H << 8 ) | m_L;
13461346
1347      x = mem_ReadByte (cpustate, addr);
1347      x = mem_read_byte( addr);
13481348      SET_8BIT (3, x)
1349      mem_WriteByte (cpustate, addr, x);
1349      mem_write_byte( addr, x);
13501350   }
13511351   break;
13521352case 0xDF:
13531353  /*      SET 3,A */
13541354
1355  SET_8BIT (3, cpustate->A)
1355  SET_8BIT (3, m_A)
13561356  break;
13571357case 0xE0:
13581358  /*      SET 4,B */
13591359
1360  SET_8BIT (4, cpustate->B)
1360  SET_8BIT (4, m_B)
13611361  break;
13621362case 0xE1:
13631363  /*      SET 4,C */
13641364
1365  SET_8BIT (4, cpustate->C)
1365  SET_8BIT (4, m_C)
13661366  break;
13671367case 0xE2:
13681368  /*      SET 4,D */
13691369
1370  SET_8BIT (4, cpustate->D)
1370  SET_8BIT (4, m_D)
13711371  break;
13721372case 0xE3:
13731373  /*      SET 4,E */
13741374
1375  SET_8BIT (4, cpustate->E)
1375  SET_8BIT (4, m_E)
13761376  break;
13771377case 0xE4:
13781378  /*      SET 4,H */
13791379
1380  SET_8BIT (4, cpustate->H)
1380  SET_8BIT (4, m_H)
13811381  break;
13821382case 0xE5:
13831383  /*      SET 4,L */
13841384
1385  SET_8BIT (4, cpustate->L)
1385  SET_8BIT (4, m_L)
13861386  break;
13871387case 0xE6:
13881388   /*      SET 4,(HL) */
13891389   {
1390      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1390      UINT16 addr = ( m_H << 8 ) | m_L;
13911391
1392      x = mem_ReadByte (cpustate, addr);
1392      x = mem_read_byte( addr);
13931393      SET_8BIT (4, x)
1394      mem_WriteByte (cpustate, addr, x);
1394      mem_write_byte( addr, x);
13951395   }
13961396   break;
13971397case 0xE7:
13981398  /*      SET 4,A */
13991399
1400  SET_8BIT (4, cpustate->A)
1400  SET_8BIT (4, m_A)
14011401  break;
14021402case 0xE8:
14031403  /*      SET 5,B */
14041404
1405  SET_8BIT (5, cpustate->B)
1405  SET_8BIT (5, m_B)
14061406  break;
14071407case 0xE9:
14081408  /*      SET 5,C */
14091409
1410  SET_8BIT (5, cpustate->C)
1410  SET_8BIT (5, m_C)
14111411  break;
14121412case 0xEA:
14131413  /*      SET 5,D */
14141414
1415  SET_8BIT (5, cpustate->D)
1415  SET_8BIT (5, m_D)
14161416  break;
14171417case 0xEB:
14181418  /*      SET 5,E */
14191419
1420  SET_8BIT (5, cpustate->E)
1420  SET_8BIT (5, m_E)
14211421  break;
14221422case 0xEC:
14231423  /*      SET 5,H */
14241424
1425  SET_8BIT (5, cpustate->H)
1425  SET_8BIT (5, m_H)
14261426  break;
14271427case 0xED:
14281428  /*      SET 5,L */
14291429
1430  SET_8BIT (5, cpustate->L)
1430  SET_8BIT (5, m_L)
14311431  break;
14321432case 0xEE:
14331433   /*      SET 5,(HL) */
14341434   {
1435      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1435      UINT16 addr = ( m_H << 8 ) | m_L;
14361436
1437      x = mem_ReadByte (cpustate, addr);
1437      x = mem_read_byte( addr);
14381438      SET_8BIT (5, x)
1439      mem_WriteByte (cpustate, addr, x);
1439      mem_write_byte( addr, x);
14401440   }
14411441   break;
14421442case 0xEF:
14431443  /*      SET 5,A */
14441444
1445  SET_8BIT (5, cpustate->A)
1445  SET_8BIT (5, m_A)
14461446  break;
14471447case 0xF0:
14481448  /*      SET 6,B */
14491449
1450  SET_8BIT (6, cpustate->B)
1450  SET_8BIT (6, m_B)
14511451  break;
14521452case 0xF1:
14531453  /*      SET 6,C */
14541454
1455  SET_8BIT (6, cpustate->C)
1455  SET_8BIT (6, m_C)
14561456  break;
14571457case 0xF2:
14581458  /*      SET 6,D */
14591459
1460  SET_8BIT (6, cpustate->D)
1460  SET_8BIT (6, m_D)
14611461  break;
14621462case 0xF3:
14631463  /*      SET 6,E */
14641464
1465  SET_8BIT (6, cpustate->E)
1465  SET_8BIT (6, m_E)
14661466  break;
14671467case 0xF4:
14681468  /*      SET 6,H */
14691469
1470  SET_8BIT (6, cpustate->H)
1470  SET_8BIT (6, m_H)
14711471  break;
14721472case 0xF5:
14731473  /*      SET 6,L */
14741474
1475  SET_8BIT (6, cpustate->L)
1475  SET_8BIT (6, m_L)
14761476  break;
14771477case 0xF6:
14781478   /*      SET 6,(HL) */
14791479   {
1480      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1480      UINT16 addr = ( m_H << 8 ) | m_L;
14811481
1482      x = mem_ReadByte (cpustate, addr);
1482      x = mem_read_byte( addr);
14831483      SET_8BIT (6, x)
1484      mem_WriteByte (cpustate, addr, x);
1484      mem_write_byte( addr, x);
14851485   }
14861486   break;
14871487case 0xF7:
14881488  /*      SET 6,A */
14891489
1490  SET_8BIT (6, cpustate->A)
1490  SET_8BIT (6, m_A)
14911491  break;
14921492case 0xF8:
14931493  /*      SET 7,B */
14941494
1495  SET_8BIT (7, cpustate->B)
1495  SET_8BIT (7, m_B)
14961496  break;
14971497case 0xF9:
14981498  /*      SET 7,C */
14991499
1500  SET_8BIT (7, cpustate->C)
1500  SET_8BIT (7, m_C)
15011501  break;
15021502case 0xFA:
15031503  /*      SET 7,D */
15041504
1505  SET_8BIT (7, cpustate->D)
1505  SET_8BIT (7, m_D)
15061506  break;
15071507case 0xFB:
15081508  /*      SET 7,E */
15091509
1510  SET_8BIT (7, cpustate->E)
1510  SET_8BIT (7, m_E)
15111511  break;
15121512case 0xFC:
15131513  /*      SET 7,H */
15141514
1515  SET_8BIT (7, cpustate->H)
1515  SET_8BIT (7, m_H)
15161516  break;
15171517case 0xFD:
15181518  /*      SET 7,L */
15191519
1520  SET_8BIT (7, cpustate->L)
1520  SET_8BIT (7, m_L)
15211521  break;
15221522case 0xFE:
15231523   /*      SET 7,(HL) */
15241524   {
1525      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
1525      UINT16 addr = ( m_H << 8 ) | m_L;
15261526
1527      x = mem_ReadByte (cpustate, addr);
1527      x = mem_read_byte( addr);
15281528      SET_8BIT (7, x)
1529      mem_WriteByte (cpustate, addr, x);
1529      mem_write_byte( addr, x);
15301530   }
15311531   break;
15321532case 0xFF:
15331533  /*      SET 7,A */
15341534
1535  SET_8BIT (7, cpustate->A)
1535  SET_8BIT (7, m_A)
15361536  break;
src/emu/cpu/lr35902/opc_main.h
r14642r14643
33  register UINT8 r,f; \
44  x++; \
55  r=(x);  \
6  f=(UINT8)(cpustate->F&FLAG_C); \
6  f=(UINT8)(m_F&FLAG_C); \
77  if( r==0 )       f|=FLAG_Z; \
88  if( (r&0xF)==0 ) f|=FLAG_H; \
9  cpustate->F=f; \
9  m_F=f; \
1010}
1111
1212#define   DEC_8BIT(x) \
r14642r14643
1414  register UINT8 r,f; \
1515  x--; \
1616  r=(x);  \
17  f=(UINT8)((cpustate->F&FLAG_C)|FLAG_N); \
17  f=(UINT8)((m_F&FLAG_C)|FLAG_N); \
1818  if( r==0 )       f|=FLAG_Z; \
1919  if( (r&0xF)==0xF ) f|=FLAG_H; \
20  cpustate->F=f; \
20  m_F=f; \
2121}
2222
2323#define   ADD_HL_RR(x) \
2424{ \
2525  register UINT32 r1,r2; \
2626  register UINT8 f; \
27  r1=((cpustate->H<<8)|cpustate->L)+(x); \
28  r2=(((cpustate->H<<8)|cpustate->L)&0xFFF)+((x)&0xFFF); \
29  f=(UINT8)(cpustate->F&FLAG_Z); \
27  r1=((m_H<<8)|m_L)+(x); \
28  r2=(((m_H<<8)|m_L)&0xFFF)+((x)&0xFFF); \
29  f=(UINT8)(m_F&FLAG_Z); \
3030  if( r1>0xFFFF ) f|=FLAG_C; \
3131  if( r2>0x0FFF ) f|=FLAG_H; \
32  cpustate->L = r1; \
33  cpustate->H = r1 >> 8; \
34  cpustate->F=f; \
32  m_L = r1; \
33  m_H = r1 >> 8; \
34  m_F=f; \
3535}
3636
3737#define   ADD_A_X(x) \
3838{ \
3939  register UINT16 r1,r2; \
4040  register UINT8 f; \
41  r1=(UINT16)((cpustate->A&0xF)+((x)&0xF)); \
42  r2=(UINT16)(cpustate->A+(x)); \
43  cpustate->A=(UINT8)r2; \
41  r1=(UINT16)((m_A&0xF)+((x)&0xF)); \
42  r2=(UINT16)(m_A+(x)); \
43  m_A=(UINT8)r2; \
4444  if( ((UINT8)r2)==0 ) f=FLAG_Z; \
4545    else f=0; \
4646  if( r2>0xFF ) f|=FLAG_C; \
4747  if( r1>0xF )  f|=FLAG_H; \
48  cpustate->F=f; \
48  m_F=f; \
4949}
5050
5151#define   SUB_A_X(x) \
5252{ \
5353  register UINT16 r1,r2; \
5454  register UINT8 f; \
55  r1=(UINT16)((cpustate->A&0xF)-((x)&0xF)); \
56  r2=(UINT16)(cpustate->A-(x)); \
57  cpustate->A=(UINT8)r2; \
55  r1=(UINT16)((m_A&0xF)-((x)&0xF)); \
56  r2=(UINT16)(m_A-(x)); \
57  m_A=(UINT8)r2; \
5858  if( ((UINT8)r2)==0 ) f=FLAG_N|FLAG_Z; \
5959    else f=FLAG_N; \
6060  if( r2>0xFF ) f|=FLAG_C; \
6161  if( r1>0xF )  f|=FLAG_H; \
62  cpustate->F=f; \
62  m_F=f; \
6363}
6464
6565/*
r14642r14643
6767   { \
6868   register UINT16 r; \
6969   register UINT8 f; \
70   r=(UINT16)(cpustate->A-(x)); \
70   r=(UINT16)(m_A-(x)); \
7171   if( ((UINT8)r)==0 ) \
7272   f=FLAG_N|FLAG_Z; \
7373   else \
7474   f=FLAG_N; \
7575   f|=(UINT8)((r>>8)&FLAG_C); \
76   if( (r^cpustate->A^(x))&0x10 ) \
76   if( (r^m_A^(x))&0x10 ) \
7777   f|=FLAG_H; \
78   cpustate->F=f; \
78   m_F=f; \
7979   }
8080 */
8181
r14642r14643
8383{ \
8484  register UINT16 r1,r2; \
8585  register UINT8 f; \
86  r1=(UINT16)((cpustate->A&0xF)-((x)&0xF)); \
87  r2=(UINT16)(cpustate->A-(x)); \
86  r1=(UINT16)((m_A&0xF)-((x)&0xF)); \
87  r2=(UINT16)(m_A-(x)); \
8888  if( ((UINT8)r2)==0 ) f=FLAG_N|FLAG_Z; \
8989    else f=FLAG_N; \
9090  if( r2>0xFF ) f|=FLAG_C; \
9191  if( r1>0xF )  f|=FLAG_H; \
92  cpustate->F=f; \
92  m_F=f; \
9393}
9494
9595#define   SBC_A_X(x) \
9696{ \
9797  register UINT16 r1,r2; \
9898  register UINT8 f; \
99  r1=(UINT16)((cpustate->A&0xF)-((x)&0xF)-((cpustate->F&FLAG_C)?1:0)); \
100  r2=(UINT16)(cpustate->A-(x)-((cpustate->F&FLAG_C)?1:0)); \
101  cpustate->A=(UINT8)r2; \
99  r1=(UINT16)((m_A&0xF)-((x)&0xF)-((m_F&FLAG_C)?1:0)); \
100  r2=(UINT16)(m_A-(x)-((m_F&FLAG_C)?1:0)); \
101  m_A=(UINT8)r2; \
102102  if( ((UINT8)r2)==0 ) f=FLAG_N|FLAG_Z; \
103103    else f=FLAG_N; \
104104  if( r2>0xFF ) f|=FLAG_C; \
105105  if( r1>0xF )  f|=FLAG_H; \
106  cpustate->F=f; \
106  m_F=f; \
107107}
108108
109109#define   ADC_A_X(x) \
110110{ \
111111  register UINT16 r1,r2;  \
112112  register UINT8 f; \
113  r1=(UINT16)((cpustate->A&0xF)+((x)&0xF)+((cpustate->F&FLAG_C)?1:0));  \
114  r2=(UINT16)(cpustate->A+(x)+((cpustate->F&FLAG_C)?1:0)); \
115  if( (cpustate->A=(UINT8)r2)==0 ) f=FLAG_Z; \
113  r1=(UINT16)((m_A&0xF)+((x)&0xF)+((m_F&FLAG_C)?1:0));  \
114  r2=(UINT16)(m_A+(x)+((m_F&FLAG_C)?1:0)); \
115  if( (m_A=(UINT8)r2)==0 ) f=FLAG_Z; \
116116    else f=0; \
117117  if( r2>0xFF )   f|=FLAG_C; \
118118  if( r1>0xF )   f|=FLAG_H; \
119  cpustate->F=f; \
119  m_F=f; \
120120}
121121
122122#define   AND_A_X(x) \
123  if( (cpustate->A&=(x))==0 ) \
124    cpustate->F=FLAG_H|FLAG_Z; \
123  if( (m_A&=(x))==0 ) \
124    m_F=FLAG_H|FLAG_Z; \
125125  else \
126    cpustate->F=FLAG_H;
126    m_F=FLAG_H;
127127
128128#define XOR_A_X(x) \
129  if( (cpustate->A^=(x))==0 ) \
130    cpustate->F=FLAG_Z; \
129  if( (m_A^=(x))==0 ) \
130    m_F=FLAG_Z; \
131131  else \
132    cpustate->F=0;
132    m_F=0;
133133
134134#define   OR_A_X(x) \
135  if( (cpustate->A|=(x))==0 ) \
136    cpustate->F=FLAG_Z; \
135  if( (m_A|=(x))==0 ) \
136    m_F=FLAG_Z; \
137137  else \
138    cpustate->F=0;
138    m_F=0;
139139
140140#define POP(x,y) \
141   y = mem_ReadByte( cpustate, cpustate->SP++ ); \
142   x = mem_ReadByte( cpustate, cpustate->SP++ );
141   y = mem_read_byte( m_SP++ ); \
142   x = mem_read_byte( m_SP++ );
143143
144144#define PUSH(x,y) \
145   cpustate->SP--; \
146   mem_WriteByte( cpustate, cpustate->SP, x ); \
147   cpustate->SP--; \
148   mem_WriteByte( cpustate, cpustate->SP, y );
145   m_SP--; \
146   mem_write_byte( m_SP, x ); \
147   m_SP--; \
148   mem_write_byte( m_SP, y );
149149
150150case 0x00: /*      NOP */
151  break;
151   break;
152
152153case 0x01: /*      LD BC,n16 */
153   cpustate->C = mem_ReadOp (cpustate);
154   cpustate->B = mem_ReadOp (cpustate);
154   m_C = mem_read_byte( m_PC++ );
155   m_B = mem_read_byte( m_PC++ );
155156   break;
157
156158case 0x02: /*      LD (BC),A */
157  mem_WriteByte (cpustate, ( cpustate->B << 8 ) | cpustate->C, cpustate->A);
158  break;
159   mem_write_byte( ( m_B << 8 ) | m_C, m_A );
160   break;
161
159162case 0x03: /*      INC BC */
160163#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
161  if (cpustate->B == 0xFE)
164  if (m_B == 0xFE)
162165  {
163166    trash_sprites (state);
164167  }
165168#endif
166   cpustate->C++;
167   if ( cpustate->C == 0 )
169   m_C++;
170   if ( m_C == 0 )
168171   {
169      cpustate->B++;
172      m_B++;
170173   }
171   CYCLES_PASSED( 4 );
174   cycles_passed( 4 );
172175   break;
173176case 0x04: /*      INC B */
174   INC_8BIT (cpustate->B)
177   INC_8BIT (m_B)
175178   break;
176179case 0x05: /*      DEC B */
177180
178  DEC_8BIT (cpustate->B)
181  DEC_8BIT (m_B)
179182  break;
183
180184case 0x06: /*      LD B,n8 */
185   m_B = mem_read_byte( m_PC++ );
186   break;
181187
182  cpustate->B = mem_ReadByte (cpustate, cpustate->PC++);
183  break;
184188case 0x07: /*      RLCA */
185189
186  cpustate->A = (UINT8) ((cpustate->A << 1) | (cpustate->A >> 7));
187  if (cpustate->A & 1)
190  m_A = (UINT8) ((m_A << 1) | (m_A >> 7));
191  if (m_A & 1)
188192  {
189    cpustate->F = FLAG_C;
193    m_F = FLAG_C;
190194  }
191195  else
192196  {
193    cpustate->F = 0;
197    m_F = 0;
194198  }
195199  break;
200
196201case 0x08: /*      LD (n16),SP */
202   mem_write_word (mem_read_word (m_PC), m_SP);
203   m_PC += 2;
204   break;
197205
198  mem_WriteWord (cpustate, mem_ReadWord (cpustate, cpustate->PC), cpustate->SP);
199  cpustate->PC += 2;
200  break;
201206case 0x09: /*      ADD HL,BC */
202   ADD_HL_RR ((cpustate->B<<8)|cpustate->C)
203   CYCLES_PASSED( 4 );
207   ADD_HL_RR ((m_B<<8)|m_C)
208   cycles_passed( 4 );
204209   break;
205210case 0x0A: /*      LD A,(BC) */
206211
207  cpustate->A = mem_ReadByte (cpustate, (cpustate->B<<8)|cpustate->C);
212  m_A = mem_read_byte ( (m_B<<8)|m_C );
208213  break;
209214case 0x0B: /*      DEC BC */
210215
211216#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
212  if (cpustate->B == 0xFE)
217  if (m_B == 0xFE)
213218  {
214219    trash_sprites (state);
215220  }
216221#endif
217   cpustate->C--;
218   if ( cpustate->C == 0xFF )
222   m_C--;
223   if ( m_C == 0xFF )
219224   {
220      cpustate->B--;
225      m_B--;
221226   }
222   CYCLES_PASSED( 4 );
227   cycles_passed( 4 );
223228   break;
224229case 0x0C: /*      INC C */
225230
226  INC_8BIT (cpustate->C)
231  INC_8BIT (m_C)
227232  break;
228233case 0x0D: /*      DEC C */
229234
230  DEC_8BIT (cpustate->C)
235  DEC_8BIT (m_C)
231236  break;
232237case 0x0E: /*      LD C,n8 */
233238
234  cpustate->C = mem_ReadByte (cpustate, cpustate->PC++);
239  m_C = mem_read_byte ( m_PC++ );
235240  break;
236241case 0x0F: /*      RRCA */
237242
238  cpustate->A = (UINT8) ((cpustate->A >> 1) | (cpustate->A << 7));
239  cpustate->F = 0;
240  if (cpustate->A & 0x80)
243  m_A = (UINT8) ((m_A >> 1) | (m_A << 7));
244  m_F = 0;
245  if (m_A & 0x80)
241246  {
242    cpustate->F |= FLAG_C;
247    m_F |= FLAG_C;
243248  }
244249  break;
245250case 0x10: /*      STOP */
246  if ( cpustate->gb_speed_change_pending ) {
247    cpustate->gb_speed = ( cpustate->gb_speed == 1 ) ? 2 : 1;
251  if ( m_gb_speed_change_pending ) {
252    m_gb_speed = ( m_gb_speed == 1 ) ? 2 : 1;
248253  }
249  cpustate->gb_speed_change_pending = 0;
254  m_gb_speed_change_pending = 0;
250255  break;
251256case 0x11: /*      LD DE,n16 */
252   cpustate->E = mem_ReadOp (cpustate);
253   cpustate->D = mem_ReadOp (cpustate);
257   m_E = mem_read_byte( m_PC++ );
258   m_D = mem_read_byte( m_PC++ );
254259   break;
255260case 0x12: /*      LD (DE),A */
256  mem_WriteByte (cpustate, ( cpustate->D << 8 ) | cpustate->E, cpustate->A);
261  mem_write_byte( ( m_D << 8 ) | m_E, m_A );
257262  break;
258263case 0x13: /*      INC DE */
259264
260265#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
261  if (cpustate->D == 0xFE)
266  if (m_D == 0xFE)
262267  {
263268    trash_sprites (state);
264269  }
265270#endif
266   cpustate->E++;
267   if ( cpustate->E == 0 )
271   m_E++;
272   if ( m_E == 0 )
268273   {
269      cpustate->D++;
274      m_D++;
270275   }
271   CYCLES_PASSED( 4 );
276   cycles_passed( 4 );
272277   break;
273278case 0x14: /*      INC D */
274279
275  INC_8BIT (cpustate->D)
280  INC_8BIT (m_D)
276281  break;
277282case 0x15: /*      DEC D */
278283
279  DEC_8BIT (cpustate->D)
284  DEC_8BIT (m_D)
280285  break;
281286case 0x16: /*      LD D,n8 */
282287
283  cpustate->D = mem_ReadByte (cpustate, cpustate->PC++);
288  m_D = mem_read_byte ( m_PC++ );
284289  break;
285290case 0x17: /*      RLA */
286291
287  x = (cpustate->A & 0x80) ? FLAG_C : 0;
292  x = (m_A & 0x80) ? FLAG_C : 0;
288293
289  cpustate->A = (UINT8) ((cpustate->A << 1) | ((cpustate->F & FLAG_C) ? 1 : 0));
290  cpustate->F = x;
294  m_A = (UINT8) ((m_A << 1) | ((m_F & FLAG_C) ? 1 : 0));
295  m_F = x;
291296  break;
292297case 0x18: /*      JR      n8 */
293298  {
294299   INT8 offset;
295300
296    offset = mem_ReadByte (cpustate, cpustate->PC++);
297    cpustate->PC += offset;
298   CYCLES_PASSED( 4 );
301    offset = mem_read_byte( m_PC++ );
302    m_PC += offset;
303   cycles_passed( 4 );
299304  }
300305  break;
301306case 0x19: /*      ADD HL,DE */
302   ADD_HL_RR (( cpustate->D << 8 ) | cpustate->E)
303   CYCLES_PASSED( 4 );
307   ADD_HL_RR (( m_D << 8 ) | m_E)
308   cycles_passed( 4 );
304309   break;
305310case 0x1A: /*      LD A,(DE) */
306311
307  cpustate->A = mem_ReadByte (cpustate, ( cpustate->D << 8 ) | cpustate->E);
312  m_A = mem_read_byte( ( m_D << 8 ) | m_E );
308313  break;
309314case 0x1B: /*      DEC DE */
310315
311316#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
312  if (cpustate->D == 0xFE)
317  if (m_D == 0xFE)
313318  {
314319    trash_sprites (state);
315320  }
316321#endif
317   cpustate->E--;
318   if ( cpustate->E == 0xFF )
322   m_E--;
323   if ( m_E == 0xFF )
319324   {
320      cpustate->D--;
325      m_D--;
321326   }
322   CYCLES_PASSED( 4 );
327   cycles_passed( 4 );
323328   break;
324329case 0x1C: /*      INC E */
325330
326  INC_8BIT (cpustate->E)
331  INC_8BIT (m_E)
327332  break;
328333case 0x1D: /*      DEC E */
329334
330  DEC_8BIT (cpustate->E)
335  DEC_8BIT (m_E)
331336  break;
332337case 0x1E: /*      LD E,n8 */
333338
334  cpustate->E = mem_ReadByte (cpustate, cpustate->PC++);
339  m_E = mem_read_byte( m_PC++ );
335340  break;
336341case 0x1F: /*      RRA */
337342
338  x = (cpustate->A & 1) ? FLAG_C : 0;
343  x = (m_A & 1) ? FLAG_C : 0;
339344
340  cpustate->A = (UINT8) ((cpustate->A >> 1) | ((cpustate->F & FLAG_C) ? 0x80 : 0));
341  cpustate->F = x;
345  m_A = (UINT8) ((m_A >> 1) | ((m_F & FLAG_C) ? 0x80 : 0));
346  m_F = x;
342347  break;
343348case 0x20: /*      JR NZ,n8 */
344349   {
345      INT8 offset = mem_ReadByte (cpustate, cpustate->PC++);
346      if (! (cpustate->F & FLAG_Z) )
350      INT8 offset = mem_read_byte( m_PC++ );
351      if (! (m_F & FLAG_Z) )
347352      {
348         cpustate->PC += offset;
349         CYCLES_PASSED( 4 );
353         m_PC += offset;
354         cycles_passed( 4 );
350355      }
351356   }
352357   break;
353358case 0x21: /*      LD HL,n16 */
354   cpustate->L = mem_ReadOp (cpustate);
355   cpustate->H = mem_ReadOp (cpustate);
359   m_L = mem_read_byte( m_PC++ );
360   m_H = mem_read_byte( m_PC++ );
356361   break;
357362case 0x22: /*      LD (HL+),A */
358363
359364#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
360  if (cpustate->H == 0xFE)
365  if (m_H == 0xFE)
361366  {
362367    trash_sprites (state);
363368  }
364369#endif
365   mem_WriteByte (cpustate, (cpustate->H << 8 ) | cpustate->L, cpustate->A);
366   cpustate->L++;
367   if ( cpustate->L == 0 )
370   mem_write_byte( (m_H << 8 ) | m_L, m_A );
371   m_L++;
372   if ( m_L == 0 )
368373   {
369      cpustate->H++;
374      m_H++;
370375   }
371376   break;
372377case 0x23: /*      INC HL */
373378
374379#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
375  if (cpustate->H == 0xFE)
380  if (m_H == 0xFE)
376381  {
377382    trash_sprites (state);
378383  }
379384#endif
380   cpustate->L++;
381   if ( cpustate->L == 0 )
385   m_L++;
386   if ( m_L == 0 )
382387   {
383      cpustate->H++;
388      m_H++;
384389   }
385   CYCLES_PASSED( 4 );
390   cycles_passed( 4 );
386391   break;
387392case 0x24: /*      INC H */
388393
389  INC_8BIT (cpustate->H);
394  INC_8BIT (m_H);
390395  break;
391396case 0x25: /*      DEC H */
392397
393  DEC_8BIT (cpustate->H);
398  DEC_8BIT (m_H);
394399  break;
395400case 0x26: /*      LD H,n8 */
396401
397  cpustate->H = mem_ReadByte (cpustate, cpustate->PC++);
402  m_H = mem_read_byte( m_PC++ );
398403  break;
399404case 0x27: /*      DAA */
400405   {
401      int tmp = cpustate->A;
406      int tmp = m_A;
402407
403      if ( ! ( cpustate->F & FLAG_N ) ) {
404         if ( ( cpustate->F & FLAG_H ) || ( tmp & 0x0F ) > 9 )
408      if ( ! ( m_F & FLAG_N ) ) {
409         if ( ( m_F & FLAG_H ) || ( tmp & 0x0F ) > 9 )
405410            tmp += 6;
406         if ( ( cpustate->F & FLAG_C ) || tmp > 0x9F )
411         if ( ( m_F & FLAG_C ) || tmp > 0x9F )
407412            tmp += 0x60;
408413      } else {
409         if ( cpustate->F & FLAG_H ) {
414         if ( m_F & FLAG_H ) {
410415            tmp -= 6;
411            if ( ! ( cpustate->F & FLAG_C ) )
416            if ( ! ( m_F & FLAG_C ) )
412417               tmp &= 0xFF;
413418         }
414         if ( cpustate->F & FLAG_C )
419         if ( m_F & FLAG_C )
415420               tmp -= 0x60;
416421      }
417      cpustate->F &= ~ ( FLAG_H | FLAG_Z );
422      m_F &= ~ ( FLAG_H | FLAG_Z );
418423      if ( tmp & 0x100 )
419         cpustate->F |= FLAG_C;
420      cpustate->A = tmp & 0xFF;
421      if ( ! cpustate->A )
422         cpustate->F |= FLAG_Z;
424         m_F |= FLAG_C;
425      m_A = tmp & 0xFF;
426      if ( ! m_A )
427         m_F |= FLAG_Z;
423428   }
424429  break;
425430case 0x28: /*      JR Z,n8 */
426431   {
427      INT8 offset = mem_ReadByte (cpustate, cpustate->PC++);;
432      INT8 offset = mem_read_byte( m_PC++ );
428433
429      if (cpustate->F & FLAG_Z)
434      if (m_F & FLAG_Z)
430435      {
431         cpustate->PC += offset;
432         CYCLES_PASSED( 4 );
436         m_PC += offset;
437         cycles_passed( 4 );
433438      }
434439   }
435440   break;
436441case 0x29: /*      ADD HL,HL */
437   ADD_HL_RR ((cpustate->H << 8 ) | cpustate->L)
438   CYCLES_PASSED( 4 );
442   ADD_HL_RR ((m_H << 8 ) | m_L)
443   cycles_passed( 4 );
439444   break;
440445case 0x2A: /*      LD A,(HL+) */
441446#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
442  if (cpustate->H == 0xFE)
447  if (m_H == 0xFE)
443448  {
444449    trash_sprites (state);
445450  }
446451#endif
447   cpustate->A = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
448   cpustate->L++;
449   if ( cpustate->L == 0 )
452   m_A = mem_read_byte( ( m_H << 8 ) | m_L );
453   m_L++;
454   if ( m_L == 0 )
450455   {
451      cpustate->H++;
456      m_H++;
452457   }
453458   break;
454459case 0x2B: /*      DEC HL */
455460
456461#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
457  if (cpustate->H == 0xFE)
462  if (m_H == 0xFE)
458463  {
459464    trash_sprites (state);
460465  }
461466#endif
462   cpustate->L--;
463   if ( cpustate->L == 0xFF )
467   m_L--;
468   if ( m_L == 0xFF )
464469   {
465      cpustate->H--;
470      m_H--;
466471   }
467   CYCLES_PASSED( 4 );
472   cycles_passed( 4 );
468473   break;
469474case 0x2C: /*      INC L */
470475
471  INC_8BIT (cpustate->L);
476  INC_8BIT (m_L);
472477  break;
473478case 0x2D: /*      DEC L */
474479
475  DEC_8BIT (cpustate->L);
480  DEC_8BIT (m_L);
476481  break;
477482case 0x2E: /*      LD L,n8 */
478483
479  cpustate->L = mem_ReadByte (cpustate, cpustate->PC++);
484  m_L = mem_read_byte( m_PC++ );
480485  break;
481486case 0x2F: /*      CPL */
482487
483  cpustate->A = ~cpustate->A;
484  cpustate->F |= FLAG_N | FLAG_H;
488  m_A = ~m_A;
489  m_F |= FLAG_N | FLAG_H;
485490  break;
486491case 0x30: /*      JR NC,n8 */
487492   {
488      INT8 offset = mem_ReadByte (cpustate, cpustate->PC++);
493      INT8 offset = mem_read_byte( m_PC++ );
489494
490      if ( ! (cpustate->F & FLAG_C) )
495      if ( ! (m_F & FLAG_C) )
491496      {
492         cpustate->PC += offset;
493         CYCLES_PASSED( 4 );
497         m_PC += offset;
498         cycles_passed( 4 );
494499      }
495500   }
496501   break;
497502case 0x31: /*      LD SP,n16 */
498503
499  cpustate->SP = mem_ReadWord (cpustate, cpustate->PC);
500  cpustate->PC += 2;
504  m_SP = mem_read_word( m_PC );
505  m_PC += 2;
501506  break;
502507case 0x32: /*      LD (HL-),A */
503508
504509#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
505  if (cpustate->H == 0xFE)
510  if (m_H == 0xFE)
506511  {
507512    trash_sprites (state);
508513  }
509514#endif
510   mem_WriteByte (cpustate, ( cpustate->H << 8 ) | cpustate->L, cpustate->A);
511   cpustate->L--;
512   if ( cpustate->L == 0xFF )
515   mem_write_byte( ( m_H << 8 ) | m_L, m_A );
516   m_L--;
517   if ( m_L == 0xFF )
513518   {
514      cpustate->H--;
519      m_H--;
515520   }
516521   break;
517522case 0x33: /*      INC SP */
518   cpustate->SP += 1;
519   CYCLES_PASSED( 4 );
523   m_SP += 1;
524   cycles_passed( 4 );
520525   break;
521526case 0x34: /*      INC (HL) */
522527   {
523      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
528      UINT16 addr = ( m_H << 8 ) | m_L;
524529      register UINT8 r, f;
525530
526      f = (UINT8) (cpustate->F & FLAG_C);
527      r = mem_ReadByte (cpustate, addr);
531      f = (UINT8) (m_F & FLAG_C);
532      r = mem_read_byte( addr );
528533      r += 1;
529      mem_WriteByte (cpustate, addr, r);
534      mem_write_byte( addr, r );
530535
531536      if (r == 0)
532537         f |= FLAG_Z;
r14642r14643
534539      if ((r & 0xF) == 0)
535540         f |= FLAG_H;
536541
537      cpustate->F = f;
542      m_F = f;
538543   }
539544   break;
540545case 0x35: /*      DEC (HL) */
541546   {
542      UINT16 addr = ( cpustate->H << 8 ) | cpustate->L;
547      UINT16 addr = ( m_H << 8 ) | m_L;
543548      register UINT8 r, f;
544549
545      f = (UINT8) ((cpustate->F & FLAG_C) | FLAG_N);
546      r = mem_ReadByte (cpustate, addr);
550      f = (UINT8) ((m_F & FLAG_C) | FLAG_N);
551      r = mem_read_byte( addr );
547552      r -= 1;
548      mem_WriteByte (cpustate, addr, r);
553      mem_write_byte( addr, r );
549554
550555      if (r == 0)
551556         f |= FLAG_Z;
r14642r14643
553558      if ((r & 0xF) == 0xF)
554559         f |= FLAG_H;
555560
556      cpustate->F = f;
561      m_F = f;
557562   }
558563   break;
559564case 0x36: /*      LD (HL),n8 */
560565   {
561      UINT8 v = mem_ReadByte (cpustate, cpustate->PC++);
562      mem_WriteByte (cpustate, ( cpustate->H << 8 ) | cpustate->L, v);
566      UINT8 v = mem_read_byte( m_PC++ );
567      mem_write_byte( ( m_H << 8 ) | m_L, v );
563568   }
564569   break;
565570case 0x37: /*      SCF */
566571
567  cpustate->F = (UINT8) ((cpustate->F & FLAG_Z) | FLAG_C);
572  m_F = (UINT8) ((m_F & FLAG_Z) | FLAG_C);
568573  break;
569574case 0x38: /*      JR C,n8 */
570575   {
571      INT8 offset = mem_ReadByte (cpustate, cpustate->PC++);
576      INT8 offset = mem_read_byte( m_PC++ );
572577
573      if (cpustate->F & FLAG_C)
578      if (m_F & FLAG_C)
574579      {
575         cpustate->PC += offset;
576         CYCLES_PASSED( 4 );
580         m_PC += offset;
581         cycles_passed( 4 );
577582      }
578583   }
579584   break;
580585case 0x39: /*      ADD HL,SP */
581   ADD_HL_RR (cpustate->SP)
582   CYCLES_PASSED( 4 );
586   ADD_HL_RR (m_SP)
587   cycles_passed( 4 );
583588   break;
584589case 0x3A: /*      LD A,(HL-) */
585590#if 0            /* FIXME ?? do we want to support this? (bug emulation) */
586  if (cpustate->H == 0xFE)
591  if (m_H == 0xFE)
587592  {
588593    trash_sprites (state);
589594  }
590595#endif
591   cpustate->A = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
592   cpustate->L--;
593   if ( cpustate->L == 0xFF )
596   m_A = mem_read_byte( ( m_H << 8 ) | m_L );
597   m_L--;
598   if ( m_L == 0xFF )
594599   {
595      cpustate->H--;
600      m_H--;
596601   }
597602   break;
598603case 0x3B: /*      DEC SP */
599   cpustate->SP -= 1;
600   CYCLES_PASSED( 4 );
604   m_SP -= 1;
605   cycles_passed( 4 );
601606   break;
602607case 0x3C: /*      INC     A */
603608
604  INC_8BIT (cpustate->A);
609  INC_8BIT (m_A);
605610  break;
606611case 0x3D: /*      DEC     A */
607612
608  DEC_8BIT (cpustate->A);
613  DEC_8BIT (m_A);
609614  break;
610615case 0x3E: /*      LD A,n8 */
611616
612  cpustate->A = mem_ReadByte (cpustate, cpustate->PC++);
617  m_A = mem_read_byte( m_PC++ );
613618  break;
614619case 0x3F: /*      CCF */
615620
616  cpustate->F = (UINT8) ((cpustate->F & FLAG_Z) | ((cpustate->F & FLAG_C) ? 0 : FLAG_C));
621  m_F = (UINT8) ((m_F & FLAG_Z) | ((m_F & FLAG_C) ? 0 : FLAG_C));
617622  break;
618623case 0x40: /*      LD B,B */
619624  break;
620625case 0x41: /*      LD B,C */
621626
622  cpustate->B = cpustate->C;
627  m_B = m_C;
623628  break;
624629case 0x42: /*      LD B,D */
625630
626  cpustate->B = cpustate->D;
631  m_B = m_D;
627632  break;
628633case 0x43: /*      LD B,E */
629634
630  cpustate->B = cpustate->E;
635  m_B = m_E;
631636  break;
632637case 0x44: /*      LD B,H */
633638
634  cpustate->B = cpustate->H;
639  m_B = m_H;
635640  break;
636641case 0x45: /*      LD B,L */
637642
638  cpustate->B = cpustate->L;
643  m_B = m_L;
639644  break;
640645case 0x46: /*      LD B,(HL) */
646   m_B = mem_read_byte( ( m_H << 8 ) | m_L) ;
647   break;
641648
642  cpustate->B = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
643  break;
644649case 0x47: /*      LD B,A */
645650
646  cpustate->B = cpustate->A;
651  m_B = m_A;
647652  break;
648653case 0x48: /*      LD C,B */
649654
650  cpustate->C = cpustate->B;
655  m_C = m_B;
651656  break;
652657case 0x49: /*      LD C,C */
653658  break;
654659case 0x4A: /*      LD C,D */
655660
656  cpustate->C = cpustate->D;
661  m_C = m_D;
657662  break;
658663case 0x4B: /*      LD C,E */
659664
660  cpustate->C = cpustate->E;
665  m_C = m_E;
661666  break;
662667case 0x4C: /*      LD C,H */
663668
664  cpustate->C = cpustate->H;
669  m_C = m_H;
665670  break;
666671case 0x4D: /*      LD C,L */
667672
668  cpustate->C = cpustate->L;
673  m_C = m_L;
669674  break;
675
670676case 0x4E: /*      LD C,(HL) */
677   m_C = mem_read_byte( ( m_H << 8 ) | m_L );
678   break;
671679
672  cpustate->C = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
673  break;
674680case 0x4F: /*      LD C,A */
675681
676  cpustate->C = cpustate->A;
682  m_C = m_A;
677683  break;
678684case 0x50: /*      LD D,B */
679685
680  cpustate->D = cpustate->B;
686  m_D = m_B;
681687  break;
682688case 0x51: /*      LD D,C */
683689
684  cpustate->D = cpustate->C;
690  m_D = m_C;
685691  break;
686692case 0x52: /*      LD D,D */
687693  break;
688694case 0x53: /*      LD D,E */
689695
690  cpustate->D = cpustate->E;
696  m_D = m_E;
691697  break;
692698case 0x54: /*      LD D,H */
693699
694  cpustate->D = cpustate->H;
700  m_D = m_H;
695701  break;
696702case 0x55: /*      LD D,L */
697703
698  cpustate->D = cpustate->L;
704  m_D = m_L;
699705  break;
700706case 0x56: /*      LD D,(HL) */
701707
702  cpustate->D = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
708  m_D = mem_read_byte( ( m_H << 8 ) | m_L );
703709  break;
704710case 0x57: /*      LD D,A */
705711
706  cpustate->D = cpustate->A;
712  m_D = m_A;
707713  break;
708714case 0x58: /*      LD E,B */
709715
710  cpustate->E = cpustate->B;
716  m_E = m_B;
711717  break;
712718case 0x59: /*      LD E,C */
713719
714  cpustate->E = cpustate->C;
720  m_E = m_C;
715721  break;
716722case 0x5A: /*      LD E,D */
717723
718  cpustate->E = cpustate->D;
724  m_E = m_D;
719725  break;
720726case 0x5B: /*      LD E,E */
721727  break;
722728case 0x5C: /*      LD E,H */
723729
724  cpustate->E = cpustate->H;
730  m_E = m_H;
725731  break;
726732case 0x5D: /*      LD E,L */
727733
728  cpustate->E = cpustate->L;
734  m_E = m_L;
729735  break;
730736case 0x5E: /*      LD E,(HL) */
731737
732  cpustate->E = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
738  m_E = mem_read_byte( ( m_H << 8 ) | m_L );
733739  break;
734740case 0x5F: /*      LD E,A */
735741
736  cpustate->E = cpustate->A;
742  m_E = m_A;
737743  break;
738744case 0x60: /*      LD H,B */
739745
740  cpustate->H = cpustate->B;
746  m_H = m_B;
741747  break;
742748case 0x61: /*      LD H,C */
743749
744  cpustate->H = cpustate->C;
750  m_H = m_C;
745751  break;
746752case 0x62: /*      LD H,D */
747753
748  cpustate->H = cpustate->D;
754  m_H = m_D;
749755  break;
750756case 0x63: /*      LD H,E */
751757
752  cpustate->H = cpustate->E;
758  m_H = m_E;
753759  break;
754760case 0x64: /*      LD H,H */
755761  break;
756762case 0x65: /*      LD H,L */
757763
758  cpustate->H = cpustate->L;
764  m_H = m_L;
759765  break;
760766case 0x66: /*      LD H,(HL) */
761767
762  cpustate->H = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
768  m_H = mem_read_byte( ( m_H << 8 ) | m_L );
763769  break;
764770case 0x67: /*      LD H,A */
765771
766  cpustate->H = cpustate->A;
772  m_H = m_A;
767773  break;
768774case 0x68: /*      LD L,B */
769775
770  cpustate->L = cpustate->B;
776  m_L = m_B;
771777  break;
772778case 0x69: /*      LD L,C */
773779
774  cpustate->L = cpustate->C;
780  m_L = m_C;
775781  break;
776782case 0x6A: /*      LD L,D */
777  cpustate->L = cpustate->D;
783  m_L = m_D;
778784  break;
779785case 0x6B: /*      LD L,E */
780786
781  cpustate->L = cpustate->E;
787  m_L = m_E;
782788  break;
783789case 0x6C: /*      LD L,H */
784790
785  cpustate->L = cpustate->H;
791  m_L = m_H;
786792  break;
787793case 0x6D: /*      LD L,L */
788794  break;
789795case 0x6E: /*      LD L,(HL) */
790796
791  cpustate->L = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
797  m_L = mem_read_byte( ( m_H << 8 ) | m_L );
792798  break;
793799case 0x6F: /*      LD L,A */
794800
795  cpustate->L = cpustate->A;
801  m_L = m_A;
796802  break;
803
797804case 0x70: /*      LD (HL),B */
805   mem_write_byte( ( m_H << 8 ) | m_L, m_B );
806   break;
798807
799  mem_WriteByte (cpustate, ( cpustate->H << 8 ) | cpustate->L, cpustate->B);
800  break;
801808case 0x71: /*      LD (HL),C */
802
803  mem_WriteByte (cpustate, ( cpustate->H << 8 ) | cpustate->L, cpustate->C);
804  break;
809   mem_write_byte( ( m_H << 8 ) | m_L, m_C );
810   break;
805811case 0x72: /*      LD (HL),D */
806
807  mem_WriteByte (cpustate, ( cpustate->H << 8 ) | cpustate->L, cpustate->D);
808  break;
812   mem_write_byte( ( m_H << 8 ) | m_L, m_D );
813   break;
809814case 0x73: /*      LD (HL),E */
810
811  mem_WriteByte (cpustate, ( cpustate->H << 8 ) | cpustate->L, cpustate->E);
812  break;
815   mem_write_byte( ( m_H << 8 ) | m_L, m_E );
816   break;
813817case 0x74: /*      LD (HL),H */
814
815  mem_WriteByte (cpustate, ( cpustate->H << 8 ) | cpustate->L, cpustate->H);
816  break;
818   mem_write_byte( ( m_H << 8 ) | m_L, m_H );
819   break;
817820case 0x75: /*      LD (HL),L */
818
819  mem_WriteByte (cpustate, ( cpustate->H << 8 ) | cpustate->L, cpustate->L);
820  break;
821   mem_write_byte( ( m_H << 8 ) | m_L, m_L );
822   break;
821823case 0x76: /*      HALT */
822   cpustate->enable |= HALTED;
823   cpustate->PC--;
824  break;
824   m_enable |= HALTED;
825   m_PC--;
826   break;
825827case 0x77: /*      LD (HL),A */
826
827  mem_WriteByte (cpustate, ( cpustate->H << 8 ) | cpustate->L, cpustate->A);
828  break;
828   mem_write_byte( ( m_H << 8 ) | m_L, m_A );
829   break;
829830case 0x78: /*      LD A,B */
830831
831  cpustate->A = cpustate->B;
832  m_A = m_B;
832833  break;
833834case 0x79: /*      LD A,C */
834835
835  cpustate->A = cpustate->C;
836  m_A = m_C;
836837  break;
837838case 0x7A: /*      LD A,D */
838839
839  cpustate->A = cpustate->D;
840  m_A = m_D;
840841  break;
841842case 0x7B: /*      LD A,E */
842843
843  cpustate->A = cpustate->E;
844  m_A = m_E;
844845  break;
845846case 0x7C: /*      LD A,H */
846847
847  cpustate->A = cpustate->H;
848  m_A = m_H;
848849  break;
849850case 0x7D: /*      LD A,L */
850851
851  cpustate->A = cpustate->L;
852  m_A = m_L;
852853  break;
853854case 0x7E: /*      LD A,(HL) */
854855
855  cpustate->A = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
856  m_A = mem_read_byte( ( m_H << 8 ) | m_L );
856857  break;
857858case 0x7F: /*      LD A,A */
858859  break;
859860case 0x80: /*      ADD A,B */
860861
861  ADD_A_X (cpustate->B)
862  ADD_A_X (m_B)
862863  break;
863864case 0x81: /*      ADD A,C */
864865
865  ADD_A_X (cpustate->C)
866  ADD_A_X (m_C)
866867  break;
867868case 0x82: /*      ADD A,D */
868869
869  ADD_A_X (cpustate->D)
870  ADD_A_X (m_D)
870871  break;
871872case 0x83: /*      ADD A,E */
872873
873  ADD_A_X (cpustate->E)
874  ADD_A_X (m_E)
874875  break;
875876case 0x84: /*      ADD A,H */
876877
877  ADD_A_X (cpustate->H)
878  ADD_A_X (m_H)
878879  break;
879880case 0x85: /*      ADD A,L */
880881
881  ADD_A_X (cpustate->L)
882  ADD_A_X (m_L)
882883  break;
883884case 0x86: /*      ADD A,(HL) */
884885
885  x = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
886  x = mem_read_byte( ( m_H << 8 ) | m_L );
886887
887888  ADD_A_X (x)
888889  break;
889890case 0x87: /*      ADD A,A */
890891
891  ADD_A_X (cpustate->A)
892  ADD_A_X (m_A)
892893  break;
893894case 0x88: /*      ADC A,B */
894895
895  ADC_A_X (cpustate->B)
896  ADC_A_X (m_B)
896897  break;
897898case 0x89: /*      ADC A,C */
898899
899  ADC_A_X (cpustate->C)
900  ADC_A_X (m_C)
900901  break;
901902case 0x8A: /*      ADC A,D */
902903
903  ADC_A_X (cpustate->D)
904  ADC_A_X (m_D)
904905  break;
905906case 0x8B: /*      ADC A,E */
906907
907  ADC_A_X (cpustate->E)
908  ADC_A_X (m_E)
908909  break;
909910case 0x8C: /*      ADC A,H */
910911
911  ADC_A_X (cpustate->H)
912  ADC_A_X (m_H)
912913  break;
913914case 0x8D: /*      ADC A,L */
914915
915  ADC_A_X (cpustate->L)
916  ADC_A_X (m_L)
916917  break;
917918case 0x8E: /*      ADC A,(HL) */
918919
919  x = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
920  x = mem_read_byte( ( m_H << 8 ) | m_L );
920921
921922  ADC_A_X (x)
922923  break;
923924case 0x8F: /*      ADC A,A */
924925
925  ADC_A_X (cpustate->A)
926  ADC_A_X (m_A)
926927  break;
927928case 0x90: /*      SUB A,B */
928929
929  SUB_A_X (cpustate->B)
930  SUB_A_X (m_B)
930931  break;
931932case 0x91: /*      SUB A,C */
932933
933  SUB_A_X (cpustate->C)
934  SUB_A_X (m_C)
934935  break;
935936case 0x92: /*      SUB A,D */
936937
937  SUB_A_X (cpustate->D)
938  SUB_A_X (m_D)
938939  break;
939940case 0x93: /*      SUB A,E */
940941
941  SUB_A_X (cpustate->E)
942  SUB_A_X (m_E)
942943  break;
943944case 0x94: /*      SUB A,H */
944945
945  SUB_A_X (cpustate->H)
946  SUB_A_X (m_H)
946947  break;
947948case 0x95: /*      SUB A,L */
948949
949  SUB_A_X (cpustate->L)
950  SUB_A_X (m_L)
950951  break;
951952case 0x96: /*      SUB A,(HL) */
952953
953954
954  x = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
955  x = mem_read_byte( ( m_H << 8 ) | m_L );
955956
956957  SUB_A_X (x)
957958  break;
958959case 0x97: /*      SUB A,A */
959960
960  SUB_A_X (cpustate->A)
961  SUB_A_X (m_A)
961962  break;
962963case 0x98: /*      SBC A,B */
963964
964  SBC_A_X (cpustate->B)
965  SBC_A_X (m_B)
965966  break;
966967case 0x99: /*      SBC A,C */
967968
968  SBC_A_X (cpustate->C)
969  SBC_A_X (m_C)
969970  break;
970971case 0x9A: /*      SBC A,D */
971972
972  SBC_A_X (cpustate->D)
973  SBC_A_X (m_D)
973974  break;
974975case 0x9B: /*      SBC A,E */
975976
976  SBC_A_X (cpustate->E)
977  SBC_A_X (m_E)
977978  break;
978979case 0x9C: /*      SBC A,H */
979980
980  SBC_A_X (cpustate->H)
981  SBC_A_X (m_H)
981982  break;
982983case 0x9D: /*      SBC A,L */
983984
984  SBC_A_X (cpustate->L)
985  SBC_A_X (m_L)
985986  break;
986987case 0x9E: /*      SBC A,(HL) */
987988
988  x = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
989  x = mem_read_byte( ( m_H << 8 ) | m_L );
989990
990991  SBC_A_X (x)
991992  break;
992993case 0x9F: /*      SBC A,A */
993994
994  SBC_A_X (cpustate->A)
995  SBC_A_X (m_A)
995996  break;
996997case 0xA0: /*      AND A,B */
997998
998  AND_A_X (cpustate->B)
999  AND_A_X (m_B)
9991000  break;
10001001case 0xA1: /*      AND A,C */
10011002
1002  AND_A_X (cpustate->C)
1003  AND_A_X (m_C)
10031004  break;
10041005case 0xA2: /*      AND A,D */
10051006
1006  AND_A_X (cpustate->D)
1007  AND_A_X (m_D)
10071008  break;
10081009case 0xA3: /*      AND A,E */
10091010
1010  AND_A_X (cpustate->E)
1011  AND_A_X (m_E)
10111012  break;
10121013case 0xA4: /*      AND A,H */
10131014
1014  AND_A_X (cpustate->H)
1015  AND_A_X (m_H)
10151016  break;
10161017case 0xA5: /*      AND A,L */
10171018
1018  AND_A_X (cpustate->L)
1019  AND_A_X (m_L)
10191020  break;
10201021case 0xA6: /*      AND A,(HL) */
10211022
1022  x = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
1023  x = mem_read_byte( ( m_H << 8 ) | m_L );
10231024
10241025  AND_A_X (x)
10251026  break;
10261027case 0xA7: /*      AND A,A */
10271028
1028  cpustate->F = (cpustate->A == 0) ? (FLAG_H | FLAG_Z) : FLAG_H;
1029  m_F = (m_A == 0) ? (FLAG_H | FLAG_Z) : FLAG_H;
10291030  break;
10301031case 0xA8: /*      XOR A,B */
10311032
1032  XOR_A_X (cpustate->B)
1033  XOR_A_X (m_B)
10331034  break;
10341035case 0xA9: /*      XOR A,C */
10351036
1036  XOR_A_X (cpustate->C)
1037  XOR_A_X (m_C)
10371038  break;
10381039case 0xAA: /*      XOR A,D */
10391040
1040  XOR_A_X (cpustate->D)
1041  XOR_A_X (m_D)
10411042  break;
10421043case 0xAB: /*      XOR A,E */
10431044
1044  XOR_A_X (cpustate->E)
1045  XOR_A_X (m_E)
10451046  break;
10461047case 0xAC: /*      XOR A,H */
10471048
1048  XOR_A_X (cpustate->H)
1049  XOR_A_X (m_H)
10491050  break;
10501051case 0xAD: /*      XOR A,L */
10511052
1052  XOR_A_X (cpustate->L)
1053  XOR_A_X (m_L)
10531054  break;
10541055case 0xAE: /*      XOR A,(HL) */
10551056
1056  x = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
1057  x = mem_read_byte( ( m_H << 8 ) | m_L );
10571058
10581059  XOR_A_X (x)
10591060  break;
10601061case 0xAF: /*      XOR A,A */
10611062
1062  XOR_A_X (cpustate->A)
1063  XOR_A_X (m_A)
10631064  break;
10641065case 0xB0: /*      OR A,B */
10651066
1066  OR_A_X (cpustate->B)
1067  OR_A_X (m_B)
10671068  break;
10681069case 0xB1: /*      OR A,C */
10691070
1070  OR_A_X (cpustate->C)
1071  OR_A_X (m_C)
10711072  break;
10721073case 0xB2: /*      OR A,D */
10731074
1074  OR_A_X (cpustate->D)
1075  OR_A_X (m_D)
10751076  break;
10761077case 0xB3: /*      OR A,E */
10771078
1078  OR_A_X (cpustate->E)
1079  OR_A_X (m_E)
10791080  break;
10801081case 0xB4: /*      OR A,H */
10811082
1082  OR_A_X (cpustate->H)
1083  OR_A_X (m_H)
10831084  break;
10841085case 0xB5: /*      OR A,L */
10851086
1086  OR_A_X (cpustate->L)
1087  OR_A_X (m_L)
10871088  break;
10881089case 0xB6: /*      OR A,(HL) */
10891090
1090  x = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
1091  x = mem_read_byte( ( m_H << 8 ) | m_L );
10911092
10921093  OR_A_X (x)
10931094  break;
10941095case 0xB7: /*      OR A,A */
10951096
1096  OR_A_X (cpustate->A)
1097  OR_A_X (m_A)
10971098  break;
10981099case 0xB8: /*      CP A,B */
10991100
1100  CP_A_X (cpustate->B)
1101  CP_A_X (m_B)
11011102  break;
11021103case 0xB9: /*      CP A,C */
11031104
1104  CP_A_X (cpustate->C)
1105  CP_A_X (m_C)
11051106  break;
11061107case 0xBA: /*      CP A,D */
11071108
1108  CP_A_X (cpustate->D)
1109  CP_A_X (m_D)
11091110  break;
11101111case 0xBB: /*      CP A,E */
11111112
1112  CP_A_X (cpustate->E)
1113  CP_A_X (m_E)
11131114  break;
11141115case 0xBC: /*      CP A,H */
11151116
1116  CP_A_X (cpustate->H)
1117  CP_A_X (m_H)
11171118  break;
11181119case 0xBD: /*      CP A,L */
11191120
1120  CP_A_X (cpustate->L)
1121  CP_A_X (m_L)
11211122  break;
11221123case 0xBE: /*      CP A,(HL) */
11231124
1124  x = mem_ReadByte (cpustate, ( cpustate->H << 8 ) | cpustate->L);
1125  x = mem_read_byte( ( m_H << 8 ) | m_L );
11251126
11261127  CP_A_X (x)
11271128  break;
11281129case 0xBF: /*      CP A,A */
11291130
1130  CP_A_X (cpustate->A)
1131  CP_A_X (m_A)
11311132  break;
11321133case 0xC0: /*      RET NZ */
1133   CYCLES_PASSED( 4 );
1134   if (!(cpustate->F & FLAG_Z))
1134   cycles_passed( 4 );
1135   if (!(m_F & FLAG_Z))
11351136   {
1136      cpustate->PC = mem_ReadWord (cpustate, cpustate->SP);
1137      cpustate->SP += 2;
1138      CYCLES_PASSED( 4 );
1137      m_PC = mem_read_word( m_SP );
1138      m_SP += 2;
1139      cycles_passed( 4 );
11391140   }
11401141   break;
11411142case 0xC1: /*      POP BC */
1142   POP( cpustate->B, cpustate->C );
1143   POP( m_B, m_C );
11431144   break;
11441145case 0xC2: /*      JP NZ,n16 */
11451146   {
1146      UINT16 addr = mem_ReadWord (cpustate, cpustate->PC);
1147      cpustate->PC += 2;
1147      UINT16 addr = mem_read_word( m_PC );
1148      m_PC += 2;
11481149
1149      if ( ! (cpustate->F & FLAG_Z) )
1150      if ( ! (m_F & FLAG_Z) )
11501151      {
1151         cpustate->PC = addr;
1152         CYCLES_PASSED( 4 );
1152         m_PC = addr;
1153         cycles_passed( 4 );
11531154      }
11541155   }
11551156   break;
11561157case 0xC3: /*      JP n16 */
1157   cpustate->PC = mem_ReadWord (cpustate, cpustate->PC);
1158   CYCLES_PASSED( 4 );
1158   m_PC = mem_read_word( m_PC );
1159   cycles_passed( 4 );
11591160   break;
11601161case 0xC4: /*      CALL NZ,n16 */
11611162   {
1162      UINT16 addr = mem_ReadWord (cpustate, cpustate->PC);
1163      cpustate->PC += 2;
1163      UINT16 addr = mem_read_word( m_PC );
1164      m_PC += 2;
11641165
1165      if ( ! (cpustate->F & FLAG_Z) )
1166      if ( ! (m_F & FLAG_Z) )
11661167      {
1167         cpustate->SP -= 2;
1168         mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1169         cpustate->PC = addr;
1170         CYCLES_PASSED( 4 );
1168         m_SP -= 2;
1169         mem_write_word( m_SP, m_PC );
1170         m_PC = addr;
1171         cycles_passed( 4 );
11711172      }
11721173   }
11731174   break;
11741175case 0xC5: /*      PUSH BC */
1175   PUSH( cpustate->B, cpustate->C );
1176   CYCLES_PASSED( 4 );
1176   PUSH( m_B, m_C );
1177   cycles_passed( 4 );
11771178   break;
11781179case 0xC6: /*      ADD A,n8 */
11791180
1180  x = mem_ReadByte (cpustate, cpustate->PC++);
1181  x = mem_read_byte( m_PC++ );
11811182  ADD_A_X (x)
11821183  break;
11831184case 0xC7: /*      RST 0 */
1184   cpustate->SP -= 2;
1185   mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1186   cpustate->PC = 0;
1187   CYCLES_PASSED( 4 );
1185   m_SP -= 2;
1186   mem_write_word( m_SP, m_PC );
1187   m_PC = 0;
1188   cycles_passed( 4 );
11881189   break;
11891190case 0xC8: /*      RET Z */
1190   CYCLES_PASSED( 4 );
1191   if (cpustate->F & FLAG_Z)
1191   cycles_passed( 4 );
1192   if (m_F & FLAG_Z)
11921193   {
1193      cpustate->PC = mem_ReadWord (cpustate, cpustate->SP);
1194      cpustate->SP += 2;
1195      CYCLES_PASSED( 4 );
1194      m_PC = mem_read_word( m_SP );
1195      m_SP += 2;
1196      cycles_passed( 4 );
11961197   }
11971198   break;
11981199case 0xC9: /*      RET */
1199   cpustate->PC = mem_ReadWord (cpustate, cpustate->SP);
1200   cpustate->SP += 2;
1201   CYCLES_PASSED( 4 );
1200   m_PC = mem_read_word( m_SP );
1201   m_SP += 2;
1202   cycles_passed( 4 );
12021203   break;
12031204case 0xCA: /*      JP Z,n16 */
12041205   {
1205      UINT16 addr = mem_ReadWord (cpustate, cpustate->PC);
1206      cpustate->PC += 2;
1206      UINT16 addr = mem_read_word( m_PC );
1207      m_PC += 2;
12071208
1208      if (cpustate->F & FLAG_Z)
1209      if (m_F & FLAG_Z)
12091210      {
1210         cpustate->PC = addr;
1211         CYCLES_PASSED( 4 );
1211         m_PC = addr;
1212         cycles_passed( 4 );
12121213      }
12131214   }
12141215   break;
12151216case 0xCB: /*      PREFIX! */
1216  x = mem_ReadByte (cpustate, cpustate->PC++);
1217  x = mem_read_byte( m_PC++ );
12171218  switch (x)
12181219  {
12191220    #include "opc_cb.h"
r14642r14643
12211222  break;
12221223case 0xCC: /*      CALL Z,n16 */
12231224   {
1224      UINT16 addr = mem_ReadWord (cpustate, cpustate->PC);
1225      cpustate->PC += 2;
1225      UINT16 addr = mem_read_word( m_PC );
1226      m_PC += 2;
12261227
1227      if (cpustate->F & FLAG_Z)
1228      if (m_F & FLAG_Z)
12281229      {
1229         cpustate->SP -= 2;
1230         mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1231         cpustate->PC = addr;
1232         CYCLES_PASSED( 4 );
1230         m_SP -= 2;
1231         mem_write_word( m_SP, m_PC );
1232         m_PC = addr;
1233         cycles_passed( 4 );
12331234      }
12341235   }
12351236   break;
12361237case 0xCD: /*      CALL n16 */
12371238   {
1238      UINT16 addr = mem_ReadWord (cpustate, cpustate->PC);
1239      cpustate->PC += 2;
1239      UINT16 addr = mem_read_word( m_PC );
1240      m_PC += 2;
12401241
1241      cpustate->SP -= 2;
1242      mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1243      cpustate->PC = addr;
1244      CYCLES_PASSED( 4 );
1242      m_SP -= 2;
1243      mem_write_word( m_SP, m_PC );
1244      m_PC = addr;
1245      cycles_passed( 4 );
12451246   }
12461247   break;
12471248case 0xCE: /*      ADC A,n8 */
12481249
1249  x = mem_ReadByte (cpustate, cpustate->PC++);
1250  x = mem_read_byte( m_PC++ );
12501251  ADC_A_X (x)
12511252  break;
12521253case 0xCF: /*      RST 8 */
1253   cpustate->SP -= 2;
1254   mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1255   cpustate->PC = 8;
1256   CYCLES_PASSED( 4 );
1254   m_SP -= 2;
1255   mem_write_word( m_SP, m_PC );
1256   m_PC = 8;
1257   cycles_passed( 4 );
12571258   break;
12581259case 0xD0: /*      RET NC */
1259   CYCLES_PASSED( 4 );
1260   if (!(cpustate->F & FLAG_C))
1260   cycles_passed( 4 );
1261   if (!(m_F & FLAG_C))
12611262   {
1262      cpustate->PC = mem_ReadWord (cpustate, cpustate->SP);
1263      cpustate->SP += 2;
1264      CYCLES_PASSED( 4 );
1263      m_PC = mem_read_word( m_SP );
1264      m_SP += 2;
1265      cycles_passed( 4 );
12651266   }
12661267   break;
12671268case 0xD1: /*      POP DE */
1268   POP( cpustate->D, cpustate->E );
1269   POP( m_D, m_E );
12691270   break;
12701271case 0xD2: /*      JP NC,n16 */
12711272   {
1272      UINT16 addr = mem_ReadWord (cpustate, cpustate->PC);
1273      cpustate->PC += 2;
1273      UINT16 addr = mem_read_word( m_PC );
1274      m_PC += 2;
12741275
1275      if ( ! (cpustate->F & FLAG_C) )
1276      if ( ! (m_F & FLAG_C) )
12761277      {
1277         cpustate->PC = addr;
1278         CYCLES_PASSED( 4 );
1278         m_PC = addr;
1279         cycles_passed( 4 );
12791280      }
12801281   }
12811282   break;
r14642r14643
12831284  break;
12841285case 0xD4: /*      CALL NC,n16 */
12851286   {
1286      UINT16 addr = mem_ReadWord (cpustate, cpustate->PC);
1287      cpustate->PC += 2;
1287      UINT16 addr = mem_read_word( m_PC );
1288      m_PC += 2;
12881289
1289      if ( ! (cpustate->F & FLAG_C) )
1290      if ( ! (m_F & FLAG_C) )
12901291      {
1291         cpustate->SP -= 2;
1292         mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1293         cpustate->PC = addr;
1294         CYCLES_PASSED( 4 );
1292         m_SP -= 2;
1293         mem_write_word( m_SP, m_PC );
1294         m_PC = addr;
1295         cycles_passed( 4 );
12951296      }
12961297   }
12971298   break;
12981299case 0xD5: /*      PUSH DE */
1299   PUSH( cpustate->D, cpustate->E );
1300   CYCLES_PASSED( 4 );
1300   PUSH( m_D, m_E );
1301   cycles_passed( 4 );
13011302   break;
13021303case 0xD6: /*      SUB A,n8 */
13031304
1304  x = mem_ReadByte (cpustate, cpustate->PC++);
1305  x = mem_read_byte( m_PC++ );
13051306  SUB_A_X (x)
13061307  break;
13071308case 0xD7: /*      RST     $10 */
1308   cpustate->SP -= 2;
1309   mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1310   cpustate->PC = 0x10;
1311   CYCLES_PASSED( 4 );
1309   m_SP -= 2;
1310   mem_write_word( m_SP, m_PC );
1311   m_PC = 0x10;
1312   cycles_passed( 4 );
13121313   break;
13131314case 0xD8: /*      RET C */
1314   CYCLES_PASSED( 4 );
1315   if (cpustate->F & FLAG_C)
1315   cycles_passed( 4 );
1316   if (m_F & FLAG_C)
13161317   {
1317      cpustate->PC = mem_ReadWord (cpustate, cpustate->SP);
1318      cpustate->SP += 2;
1319      CYCLES_PASSED( 4 );
1318      m_PC = mem_read_word( m_SP );
1319      m_SP += 2;
1320      cycles_passed( 4 );
13201321   }
13211322   break;
13221323case 0xD9: /*      RETI */
1323   cpustate->PC = mem_ReadWord (cpustate, cpustate->SP);
1324   cpustate->SP += 2;
1325   cpustate->enable |= IME;
1326   CYCLES_PASSED( 4 );
1324   m_PC = mem_read_word( m_SP );
1325   m_SP += 2;
1326   m_enable |= IME;
1327   cycles_passed( 4 );
13271328   break;
13281329case 0xDA: /*      JP C,n16 */
13291330   {
1330      UINT16 addr = mem_ReadWord (cpustate, cpustate->PC);
1331      cpustate->PC += 2;
1331      UINT16 addr = mem_read_word( m_PC );
1332      m_PC += 2;
13321333
1333      if (cpustate->F & FLAG_C)
1334      if (m_F & FLAG_C)
13341335      {
1335         cpustate->PC = addr;
1336         CYCLES_PASSED( 4 );
1336         m_PC = addr;
1337         cycles_passed( 4 );
13371338      }
13381339   }
13391340   break;
r14642r14643
13411342  break;
13421343case 0xDC: /*      CALL C,n16 */
13431344   {
1344      UINT16 addr = mem_ReadWord (cpustate, cpustate->PC);
1345      cpustate->PC += 2;
1345      UINT16 addr = mem_read_word( m_PC );
1346      m_PC += 2;
13461347
1347      if (cpustate->F & FLAG_C)
1348      if (m_F & FLAG_C)
13481349      {
1349         cpustate->SP -= 2;
1350         mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1351         cpustate->PC = addr;
1352         CYCLES_PASSED( 4 );
1350         m_SP -= 2;
1351         mem_write_word( m_SP, m_PC );
1352         m_PC = addr;
1353         cycles_passed( 4 );
13531354      }
13541355   }
13551356   break;
r14642r14643
13571358  break;
13581359case 0xDE: /*      SBC A,n8 */
13591360
1360  x = mem_ReadByte (cpustate, cpustate->PC++);
1361  x = mem_read_byte( m_PC++ );
13611362  SBC_A_X (x)
13621363  break;
13631364case 0xDF: /*      RST     $18 */
1364   cpustate->SP -= 2;
1365   mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1366   cpustate->PC = 0x18;
1367   CYCLES_PASSED( 4 );
1365   m_SP -= 2;
1366   mem_write_word( m_SP, m_PC );
1367   m_PC = 0x18;
1368   cycles_passed( 4 );
13681369   break;
13691370case 0xE0: /*      LD      ($FF00+n8),A */
13701371  {
1371   UINT8 v = mem_ReadByte (cpustate, cpustate->PC++);
1372   mem_WriteByte (cpustate, 0xFF00 + v, cpustate->A);
1372   UINT8 v = mem_read_byte( m_PC++ );
1373   mem_write_byte( 0xFF00 + v, m_A );
13731374  }
13741375  break;
13751376case 0xE1: /*      POP HL */
1376   POP( cpustate->H, cpustate->L );
1377   POP( m_H, m_L );
13771378   break;
13781379case 0xE2: /*      LD ($FF00+C),A */
13791380
1380  mem_WriteByte (cpustate, (UINT16) (0xFF00 + cpustate->C), cpustate->A);
1381  mem_write_byte( 0xFF00 + m_C, m_A );
13811382  break;
13821383case 0xE3: /*      EH? */
13831384  break;
13841385case 0xE4: /*      EH? */
13851386  break;
13861387case 0xE5: /*      PUSH HL */
1387   PUSH( cpustate->H, cpustate->L );
1388   CYCLES_PASSED( 4 );
1388   PUSH( m_H, m_L );
1389   cycles_passed( 4 );
13891390   break;
13901391case 0xE6: /*      AND A,n8 */
13911392
1392  x = mem_ReadByte (cpustate, cpustate->PC++);
1393  x = mem_read_byte( m_PC++ );
13931394  AND_A_X (x)
13941395  break;
13951396case 0xE7: /*      RST $20 */
1396   cpustate->SP -= 2;
1397   mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1398   cpustate->PC = 0x20;
1399   CYCLES_PASSED( 4 );
1397   m_SP -= 2;
1398   mem_write_word( m_SP, m_PC );
1399   m_PC = 0x20;
1400   cycles_passed( 4 );
14001401   break;
14011402case 0xE8: /*      ADD SP,n8 */
14021403/*
r14642r14643
14091410  {
14101411   register INT32 n;
14111412
1412   n = (INT8) mem_ReadByte (cpustate, cpustate->PC++);
1413   n = (INT8) mem_read_byte( m_PC++ );
14131414
1414   if ( ( cpustate->SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF )
1415   if ( ( m_SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF )
14151416    {
1416      cpustate->F = FLAG_C;
1417      m_F = FLAG_C;
14171418    }
14181419    else
14191420    {
1420      cpustate->F = 0;
1421      m_F = 0;
14211422    }
14221423
1423    if ( ( cpustate->SP & 0x0F ) + ( n & 0x0F ) > 0x0F )
1424    if ( ( m_SP & 0x0F ) + ( n & 0x0F ) > 0x0F )
14241425    {
1425      cpustate->F |= FLAG_H;
1426      m_F |= FLAG_H;
14261427    }
14271428
1428   cpustate->SP = (UINT16) ( cpustate->SP + n );
1429   m_SP = (UINT16) ( m_SP + n );
14291430  }
1430  CYCLES_PASSED( 8 );
1431  cycles_passed( 8 );
14311432  break;
14321433case 0xE9: /*      JP (HL) */
1433   cpustate->PC = ( cpustate->H << 8 ) | cpustate->L;
1434   m_PC = ( m_H << 8 ) | m_L;
14341435   break;
14351436case 0xEA: /*      LD (n16),A */
14361437
1437  mem_WriteByte (cpustate, mem_ReadWord (cpustate, cpustate->PC), cpustate->A);
1438  cpustate->PC += 2;
1438  mem_write_byte( mem_read_word( m_PC ), m_A );
1439  m_PC += 2;
14391440  break;
14401441case 0xEB: /*      EH? */
14411442  break;
r14642r14643
14451446  break;
14461447case 0xEE: /*      XOR A,n8 */
14471448
1448  x = mem_ReadByte (cpustate, cpustate->PC++);
1449  x = mem_read_byte( m_PC++ );
14491450  XOR_A_X (x)
14501451  break;
14511452case 0xEF: /*      RST $28 */
1452   cpustate->SP -= 2;
1453   mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1454   cpustate->PC = 0x28;
1455   CYCLES_PASSED( 4 );
1453   m_SP -= 2;
1454   mem_write_word( m_SP, m_PC );
1455   m_PC = 0x28;
1456   cycles_passed( 4 );
14561457   break;
14571458case 0xF0: /*      LD A,($FF00+n8) */
14581459  {
1459   UINT8 v = mem_ReadByte (cpustate, cpustate->PC++);
1460   cpustate->A = mem_ReadByte (cpustate, 0xFF00 + v);
1460   UINT8 v = mem_read_byte( m_PC++ );
1461   m_A = mem_read_byte( 0xFF00 + v );
14611462  }
14621463  break;
14631464case 0xF1: /*      POP AF */
1464   POP( cpustate->A, cpustate->F );
1465   cpustate->F &= 0xF0;
1465   POP( m_A, m_F );
1466   m_F &= 0xF0;
14661467   break;
14671468case 0xF2: /*      LD A,($FF00+C) */
14681469
1469  cpustate->A = mem_ReadByte (cpustate, (UINT16) (0xFF00 + cpustate->C));
1470  m_A = mem_read_byte( 0xFF00 + m_C );
14701471  break;
14711472case 0xF3: /*      DI */
1472  cpustate->ei_delay = 0;
1473  cpustate->enable &= ~IME;
1473  m_ei_delay = 0;
1474  m_enable &= ~IME;
14741475  break;
14751476case 0xF4: /*      EH? */
14761477  break;
14771478case 0xF5: /*      PUSH AF */
1478   cpustate->F &= 0xF0;
1479   PUSH( cpustate->A, cpustate->F );
1480   CYCLES_PASSED( 4 );
1479   m_F &= 0xF0;
1480   PUSH( m_A, m_F );
1481   cycles_passed( 4 );
14811482   break;
14821483case 0xF6: /*      OR A,n8 */
14831484
1484  x = mem_ReadByte (cpustate, cpustate->PC++);
1485  x = mem_read_byte( m_PC++ );
14851486  OR_A_X (x)
14861487  break;
14871488case 0xF7: /*      RST $30 */
1488   cpustate->SP -= 2;
1489   mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1490   cpustate->PC = 0x30;
1491   CYCLES_PASSED( 4 );
1489   m_SP -= 2;
1490   mem_write_word( m_SP, m_PC );
1491   m_PC = 0x30;
1492   cycles_passed( 4 );
14921493   break;
14931494case 0xF8: /*      LD HL,SP+n8 */
14941495/*
r14642r14643
15041505  {
15051506   register INT32 n;
15061507
1507   n = (INT8) mem_ReadByte (cpustate, cpustate->PC++);
1508   n = (INT8) mem_read_byte( m_PC++ );
15081509
1509   if ( ( cpustate->SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF )
1510   if ( ( m_SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF )
15101511    {
1511      cpustate->F = FLAG_C;
1512      m_F = FLAG_C;
15121513    }
15131514    else
15141515    {
1515      cpustate->F = 0;
1516      m_F = 0;
15161517    }
15171518
1518   if ( ( cpustate->SP & 0x0F ) + ( n & 0x0F ) > 0x0F )
1519   if ( ( m_SP & 0x0F ) + ( n & 0x0F ) > 0x0F )
15191520    {
1520      cpustate->F |= FLAG_H;
1521      m_F |= FLAG_H;
15211522    }
15221523
1523   UINT16 res = cpustate->SP + n;
1524   UINT16 res = m_SP + n;
15241525
1525   cpustate->L = res & 0xFF;
1526   cpustate->H = res >> 8;
1526   m_L = res & 0xFF;
1527   m_H = res >> 8;
15271528  }
1528  CYCLES_PASSED( 4 );
1529  cycles_passed( 4 );
15291530  break;
15301531case 0xF9: /*      LD SP,HL */
1531   cpustate->SP = ( cpustate->H << 8 ) | cpustate->L;
1532   CYCLES_PASSED( 4 );
1532   m_SP = ( m_H << 8 ) | m_L;
1533   cycles_passed( 4 );
15331534   break;
15341535case 0xFA: /*      LD A,(n16) */
1535   cpustate->A = mem_ReadByte (cpustate, mem_ReadWord (cpustate, cpustate->PC));
1536   cpustate->PC += 2;
1536   m_A = mem_read_byte( mem_read_word( m_PC ) );
1537   m_PC += 2;
15371538   break;
15381539case 0xFB: /*      EI */
1539   cpustate->enable |= IME;
1540   cpustate->ei_delay = 1;
1540   m_enable |= IME;
1541   m_ei_delay = 1;
15411542   break;
15421543case 0xFC: /*      EH? */
15431544   break;
15441545case 0xFD: /*      EH? */
15451546   break;
15461547case 0xFE: /*      CP A,n8 */
1547   x = mem_ReadByte (cpustate, cpustate->PC++);
1548   x = mem_read_byte( m_PC++ );
15481549   CP_A_X (x)
15491550   break;
15501551case 0xFF: /*      RST $38 */
1551   cpustate->SP -= 2;
1552   mem_WriteWord (cpustate, cpustate->SP, cpustate->PC);
1553   cpustate->PC = 0x38;
1554   CYCLES_PASSED( 4 );
1552   m_SP -= 2;
1553   mem_write_word( m_SP, m_PC );
1554   m_PC = 0x38;
1555   cycles_passed( 4 );
15551556   break;
src/mess/machine/gb.c
r14642r14643
864864      break;
865865   case 0x0F:                  /* IF - Interrupt flag */
866866      data &= 0x1F;
867      cpu_set_reg( space->machine().device("maincpu"), LR35902_IF, data );
867      space->machine().device<lr35902_cpu_device>(":maincpu")->set_if( data );
868868      break;
869869   }
870870
r14642r14643
14171417/* Interrupt Enable register */
14181418READ8_HANDLER( gb_ie_r )
14191419{
1420   return cpu_get_reg( space->machine().device("maincpu"), LR35902_IE );
1420   return space->machine().device<lr35902_cpu_device>(":maincpu")->get_ie();
14211421}
14221422
14231423WRITE8_HANDLER ( gb_ie_w )
14241424{
1425   cpu_set_reg( space->machine().device("maincpu"), LR35902_IE, data & 0x1F );
1425   space->machine().device<lr35902_cpu_device>(":maincpu")->set_ie( data & 0x1F );
14261426}
14271427
14281428/* IO read */
r14642r14643
14431443         return state->m_gb_io[offset];
14441444      case 0x0F:
14451445         /* Make sure the internal states are up to date */
1446         return 0xE0 | cpu_get_reg( space->machine().device("maincpu"), LR35902_IF );
1446         return 0xE0 | space->machine().device<lr35902_cpu_device>(":maincpu")->get_if();
14471447      default:
14481448         /* It seems unsupported registers return 0xFF */
14491449         return 0xFF;
r14642r14643
19671967   }
19681968}
19691969
1970void gb_timer_callback(device_t *device, int cycles)
1970void gb_timer_callback(lr35902_cpu_device *device, int cycles)
19711971{
19721972   gb_state *state = device->machine().driver_data<gb_state>();
19731973   UINT16 old_gb_divcount = state->m_divcount;
r14642r14643
20012001   switch( offset )
20022002   {
20032003      case 0x0D:   /* KEY1 - Prepare speed switch */
2004         cpu_set_reg( space->machine().device("maincpu"), LR35902_SPEED, data );
2004         space->machine().device<lr35902_cpu_device>(":maincpu")->set_speed( data );
20052005         return;
20062006      case 0x10:   /* BFF - Bios disable */
20072007         gb_rom16_0000( space->machine(), state->m_ROMMap[state->m_ROMBank00] );
r14642r14643
20262026   switch( offset )
20272027   {
20282028   case 0x0D:   /* KEY1 */
2029      return cpu_get_reg( space->machine().device("maincpu"), LR35902_SPEED );
2029      space->machine().device<lr35902_cpu_device>(":maincpu")->get_speed();
20302030   case 0x16:   /* RP - Infrared port */
20312031      break;
20322032   case 0x30:   /* SVBK - RAM bank select */
src/mess/includes/gb.h
r14642r14643
195195DEVICE_START(gb_cart);
196196DEVICE_IMAGE_LOAD(gb_cart);
197197INTERRUPT_GEN( gb_scanline_interrupt );
198void gb_timer_callback(device_t *device, int cycles);
198void gb_timer_callback(lr35902_cpu_device *device, int cycles);
199199WRITE8_HANDLER( gbc_io2_w );
200200READ8_HANDLER( gbc_io2_r );
201201MACHINE_START( gb );
src/mess/drivers/gb.c
r14642r14643
453453static const UINT16 mgb_cpu_regs[6] = { 0xFFB0, 0x0013, 0x00D8, 0x014D, 0xFFFE, 0x0100 };   /* Game Boy Pocket / Super Game Boy 2 */
454454static const UINT16 megaduck_cpu_regs[6] = { 0x0000, 0x0000, 0x0000, 0x0000, 0xFFFE, 0x0000 };   /* Megaduck */
455455
456static const lr35902_cpu_core dmg_cpu_reset = { NULL, LR35902_FEATURE_HALT_BUG, gb_timer_callback };
457static const lr35902_cpu_core sgb_cpu_reset = { NULL, LR35902_FEATURE_HALT_BUG, gb_timer_callback };
458static const lr35902_cpu_core mgb_cpu_reset = { mgb_cpu_regs, LR35902_FEATURE_HALT_BUG, gb_timer_callback };
459static const lr35902_cpu_core cgb_cpu_reset = { NULL, 0, gb_timer_callback };
460static const lr35902_cpu_core megaduck_cpu_reset = { megaduck_cpu_regs, LR35902_FEATURE_HALT_BUG, gb_timer_callback };
456static const struct lr35902_config dmg_cpu_reset = { NULL, LR35902_FEATURE_HALT_BUG, gb_timer_callback };
457static const struct lr35902_config sgb_cpu_reset = { NULL, LR35902_FEATURE_HALT_BUG, gb_timer_callback };
458static const struct lr35902_config mgb_cpu_reset = { mgb_cpu_regs, LR35902_FEATURE_HALT_BUG, gb_timer_callback };
459static const struct lr35902_config cgb_cpu_reset = { NULL, 0, gb_timer_callback };
460static const struct lr35902_config megaduck_cpu_reset = { megaduck_cpu_regs, LR35902_FEATURE_HALT_BUG, gb_timer_callback };
461461
462462static ADDRESS_MAP_START(gb_map, AS_PROGRAM, 8)
463463   ADDRESS_MAP_UNMAP_HIGH
r14642r14643
561561   /* basic machine hardware */
562562   MCFG_CPU_ADD("maincpu", LR35902, 4194304)         /* 4.194304 MHz */
563563   MCFG_CPU_PROGRAM_MAP(gb_map)
564   MCFG_CPU_CONFIG(dmg_cpu_reset)
564   MCFG_LR35902_CONFIG(dmg_cpu_reset)
565565   MCFG_CPU_VBLANK_INT("screen", gb_scanline_interrupt)   /* 1 dummy int each frame */
566566
567567   MCFG_QUANTUM_TIME(attotime::from_hz(60))
r14642r14643
606606   MCFG_CPU_PROGRAM_MAP(sgb_map)
607607
608608   MCFG_CPU_MODIFY("maincpu")
609   MCFG_CPU_CONFIG(sgb_cpu_reset)
609   MCFG_LR35902_CONFIG(sgb_cpu_reset)
610610
611611   MCFG_MACHINE_START( sgb )
612612   MCFG_MACHINE_RESET( sgb )
r14642r14643
622622
623623static MACHINE_CONFIG_DERIVED( gbpocket, gameboy )
624624   MCFG_CPU_MODIFY("maincpu")
625   MCFG_CPU_CONFIG(mgb_cpu_reset)
625   MCFG_LR35902_CONFIG(mgb_cpu_reset)
626626   MCFG_MACHINE_RESET( gbpocket )
627627   MCFG_PALETTE_INIT(gbp)
628628
r14642r14643
633633static MACHINE_CONFIG_DERIVED( gbcolor, gb_common )
634634   MCFG_CPU_MODIFY("maincpu")
635635   MCFG_CPU_PROGRAM_MAP( gbc_map)
636   MCFG_CPU_CONFIG(cgb_cpu_reset)
636   MCFG_LR35902_CONFIG(cgb_cpu_reset)
637637
638638   MCFG_MACHINE_START(gbc)
639639   MCFG_MACHINE_RESET(gbc)
r14642r14643
660660   MCFG_CPU_ADD("maincpu", LR35902, 4194304)         /* 4.194304 MHz */
661661   MCFG_CPU_PROGRAM_MAP( megaduck_map)
662662   MCFG_CPU_VBLANK_INT("screen", gb_scanline_interrupt)   /* 1 int each scanline ! */
663   MCFG_CPU_CONFIG(megaduck_cpu_reset)
663   MCFG_LR35902_CONFIG(megaduck_cpu_reset)
664664
665665   MCFG_SCREEN_ADD("screen", LCD)
666666   MCFG_SCREEN_REFRESH_RATE(DMG_FRAMES_PER_SECOND)

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