src/emu/cpu/lr35902/lr35902.c
| r14619 | r14620 | |
| 129 | 129 | /* Memory functions */ |
| 130 | 130 | /****************************************************************************/ |
| 131 | 131 | |
| 132 | | #define mem_ReadByte(cs,A) ((UINT8)(cs)->w.program->read_byte(A)) |
| 133 | | #define mem_WriteByte(cs,A,V) ((cs)->w.program->write_byte(A,V)) |
| 132 | #define mem_ReadByte(cs,A) ((UINT8)(cs)->w.program->read_byte(A)); CYCLES_PASSED(4); |
| 133 | #define mem_WriteByte(cs,A,V) ((cs)->w.program->write_byte(A,V)); CYCLES_PASSED(4); |
| 134 | 134 | |
| 135 | 135 | INLINE UINT16 mem_ReadWord (lr35902_state *cpustate, UINT32 address) |
| 136 | 136 | { |
| 137 | | UINT16 value = (UINT16) mem_ReadByte (cpustate, (address + 1) & 0xffff) << 8; |
| 137 | UINT16 value = mem_ReadByte (cpustate, (address + 1) & 0xffff); |
| 138 | value <<= 8; |
| 138 | 139 | value |= mem_ReadByte (cpustate, address); |
| 139 | 140 | return value; |
| 140 | 141 | } |
| r14619 | r14620 | |
| 145 | 146 | mem_WriteByte (cpustate, (address + 1) & 0xffff, value >> 8); |
| 146 | 147 | } |
| 147 | 148 | |
| 148 | | static const int Cycles[256] = |
| 149 | | { |
| 150 | | 4,12, 8, 8, 4, 4, 8, 4,20, 8, 8, 8, 4, 4, 8, 4, |
| 151 | | 4,12, 8, 8, 4, 4, 8, 4,12, 8, 8, 8, 4, 4, 8, 4, |
| 152 | | 8,12, 8, 8, 4, 4, 8, 4, 8, 8, 8, 8, 4, 4, 8, 4, |
| 153 | | 8,12, 8, 8,12,12,12, 4, 8, 8, 8, 8, 4, 4, 8, 4, |
| 154 | | 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, |
| 155 | | 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, |
| 156 | | 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, |
| 157 | | 8, 8, 8, 8, 8, 8, 4, 8, 4, 4, 4, 4, 4, 4, 8, 4, |
| 158 | | 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, |
| 159 | | 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, |
| 160 | | 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, |
| 161 | | 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4, |
| 162 | | 8,12,12,16,12,16, 8,16, 8,16,12, 0,12,24, 8,16, |
| 163 | | 8,12,12, 4,12,16, 8,16, 8,16,12, 4,12, 4, 8,16, |
| 164 | | 12,12, 8, 4, 4,16, 8,16,16, 4,16, 4, 4, 4, 8,16, |
| 165 | | 12,12, 8, 4, 4,16, 8,16,12, 8,16, 4, 4, 4, 8,16 |
| 166 | | }; |
| 167 | | |
| 168 | | static const int CyclesCB[256] = |
| 169 | | { |
| 170 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 171 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 172 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 173 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 174 | | 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, |
| 175 | | 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, |
| 176 | | 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, |
| 177 | | 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, |
| 178 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 179 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 180 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 181 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 182 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 183 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 184 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8, |
| 185 | | 8, 8, 8, 8, 8, 8,16, 8, 8, 8, 8, 8, 8, 8,16, 8 |
| 186 | | }; |
| 187 | | |
| 188 | 149 | static CPU_INIT( lr35902 ) |
| 189 | 150 | { |
| 190 | 151 | lr35902_state *cpustate = get_safe_token(device); |
| r14619 | r14620 | |
| 285 | 246 | (*cpustate->w.irq_callback)(cpustate->w.device, irqline); |
| 286 | 247 | cpustate->w.enable &= ~IME; |
| 287 | 248 | cpustate->w.IF &= ~(1 << irqline); |
| 288 | | CYCLES_PASSED( 20 ); |
| 249 | CYCLES_PASSED( 12 ); |
| 289 | 250 | cpustate->w.SP -= 2; |
| 290 | 251 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 291 | 252 | cpustate->w.PC = 0x40 + irqline * 8; |
| r14619 | r14620 | |
| 318 | 279 | lr35902_ProcessInterrupts (cpustate); |
| 319 | 280 | debugger_instruction_hook(device, cpustate->w.PC); |
| 320 | 281 | if ( cpustate->w.enable & HALTED ) { |
| 321 | | CYCLES_PASSED( Cycles[0x76] ); |
| 282 | CYCLES_PASSED( 4 ); |
| 322 | 283 | cpustate->w.execution_state = 1; |
| 323 | 284 | } else { |
| 324 | 285 | cpustate->w.op = mem_ReadByte (cpustate, cpustate->w.PC++); |
| r14619 | r14620 | |
| 326 | 287 | cpustate->w.PC--; |
| 327 | 288 | cpustate->w.doHALTbug = 0; |
| 328 | 289 | } |
| 329 | | CYCLES_PASSED( Cycles[cpustate->w.op] ); |
| 330 | 290 | } |
| 331 | 291 | } |
| 332 | 292 | cpustate->w.execution_state ^= 1; |
src/emu/cpu/lr35902/opc_main.h
| r14619 | r14620 | |
| 147 | 147 | mem_WriteByte (cpustate, cpustate->w.BC, cpustate->b.A); |
| 148 | 148 | break; |
| 149 | 149 | case 0x03: /* INC BC */ |
| 150 | | |
| 151 | 150 | #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ |
| 152 | 151 | if (cpustate->b.B == 0xFE) |
| 153 | 152 | { |
| 154 | 153 | trash_sprites (state); |
| 155 | 154 | } |
| 156 | 155 | #endif |
| 157 | | cpustate->w.BC += 1; |
| 158 | | break; |
| 156 | cpustate->w.BC += 1; |
| 157 | CYCLES_PASSED( 4 ); |
| 158 | break; |
| 159 | 159 | case 0x04: /* INC B */ |
| 160 | 160 | |
| 161 | 161 | INC_8BIT (cpustate->b.B) |
| r14619 | r14620 | |
| 186 | 186 | cpustate->w.PC += 2; |
| 187 | 187 | break; |
| 188 | 188 | case 0x09: /* ADD HL,BC */ |
| 189 | | |
| 190 | | ADD_HL_RR (cpustate->w.BC) |
| 191 | | break; |
| 189 | ADD_HL_RR (cpustate->w.BC) |
| 190 | CYCLES_PASSED( 4 ); |
| 191 | break; |
| 192 | 192 | case 0x0A: /* LD A,(BC) */ |
| 193 | 193 | |
| 194 | 194 | cpustate->b.A = mem_ReadByte (cpustate, cpustate->w.BC); |
| r14619 | r14620 | |
| 201 | 201 | trash_sprites (state); |
| 202 | 202 | } |
| 203 | 203 | #endif |
| 204 | | |
| 205 | | cpustate->w.BC -= 1; |
| 206 | | break; |
| 204 | cpustate->w.BC -= 1; |
| 205 | CYCLES_PASSED( 4 ); |
| 206 | break; |
| 207 | 207 | case 0x0C: /* INC C */ |
| 208 | 208 | |
| 209 | 209 | INC_8BIT (cpustate->b.C) |
| r14619 | r14620 | |
| 248 | 248 | } |
| 249 | 249 | #endif |
| 250 | 250 | |
| 251 | | cpustate->w.DE += 1; |
| 252 | | break; |
| 251 | cpustate->w.DE += 1; |
| 252 | CYCLES_PASSED( 4 ); |
| 253 | break; |
| 253 | 254 | case 0x14: /* INC D */ |
| 254 | 255 | |
| 255 | 256 | INC_8BIT (cpustate->b.D) |
| r14619 | r14620 | |
| 275 | 276 | |
| 276 | 277 | offset = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 277 | 278 | cpustate->w.PC += offset; |
| 279 | CYCLES_PASSED( 4 ); |
| 278 | 280 | } |
| 279 | 281 | break; |
| 280 | 282 | case 0x19: /* ADD HL,DE */ |
| 281 | | |
| 282 | | ADD_HL_RR (cpustate->w.DE) |
| 283 | | break; |
| 283 | ADD_HL_RR (cpustate->w.DE) |
| 284 | CYCLES_PASSED( 4 ); |
| 285 | break; |
| 284 | 286 | case 0x1A: /* LD A,(DE) */ |
| 285 | 287 | |
| 286 | 288 | cpustate->b.A = mem_ReadByte (cpustate, cpustate->w.DE); |
| r14619 | r14620 | |
| 293 | 295 | trash_sprites (state); |
| 294 | 296 | } |
| 295 | 297 | #endif |
| 296 | | |
| 297 | | cpustate->w.DE -= 1; |
| 298 | | break; |
| 298 | cpustate->w.DE -= 1; |
| 299 | CYCLES_PASSED( 4 ); |
| 300 | break; |
| 299 | 301 | case 0x1C: /* INC E */ |
| 300 | 302 | |
| 301 | 303 | INC_8BIT (cpustate->b.E) |
| r14619 | r14620 | |
| 316 | 318 | cpustate->b.F = x; |
| 317 | 319 | break; |
| 318 | 320 | case 0x20: /* JR NZ,n8 */ |
| 319 | | |
| 320 | | if (cpustate->b.F & FLAG_Z) |
| 321 | | { |
| 322 | | cpustate->w.PC++; |
| 323 | | } |
| 324 | | else |
| 325 | | { |
| 326 | | INT8 offset; |
| 327 | | |
| 328 | | offset = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 329 | | cpustate->w.PC += offset; |
| 330 | | CYCLES_PASSED( 4 ); |
| 331 | | } |
| 332 | | break; |
| 321 | { |
| 322 | INT8 offset = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 323 | if (! (cpustate->b.F & FLAG_Z) ) |
| 324 | { |
| 325 | cpustate->w.PC += offset; |
| 326 | CYCLES_PASSED( 4 ); |
| 327 | } |
| 328 | } |
| 329 | break; |
| 333 | 330 | case 0x21: /* LD HL,n16 */ |
| 334 | 331 | |
| 335 | 332 | cpustate->w.HL = mem_ReadWord (cpustate, cpustate->w.PC); |
| r14619 | r14620 | |
| 356 | 353 | } |
| 357 | 354 | #endif |
| 358 | 355 | |
| 359 | | cpustate->w.HL += 1; |
| 360 | | break; |
| 356 | cpustate->w.HL += 1; |
| 357 | CYCLES_PASSED( 4 ); |
| 358 | break; |
| 361 | 359 | case 0x24: /* INC H */ |
| 362 | 360 | |
| 363 | 361 | INC_8BIT (cpustate->b.H); |
| r14619 | r14620 | |
| 397 | 395 | } |
| 398 | 396 | break; |
| 399 | 397 | case 0x28: /* JR Z,n8 */ |
| 398 | { |
| 399 | INT8 offset = mem_ReadByte (cpustate, cpustate->w.PC++);; |
| 400 | 400 | |
| 401 | | if (cpustate->b.F & FLAG_Z) |
| 402 | | { |
| 403 | | INT8 offset; |
| 404 | | |
| 405 | | offset = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 406 | | cpustate->w.PC += offset; |
| 407 | | |
| 408 | | CYCLES_PASSED( 4 ); |
| 409 | | } |
| 410 | | else |
| 411 | | { |
| 412 | | cpustate->w.PC += 1; |
| 413 | | } |
| 414 | | break; |
| 401 | if (cpustate->b.F & FLAG_Z) |
| 402 | { |
| 403 | cpustate->w.PC += offset; |
| 404 | CYCLES_PASSED( 4 ); |
| 405 | } |
| 406 | } |
| 407 | break; |
| 415 | 408 | case 0x29: /* ADD HL,HL */ |
| 416 | | |
| 417 | | ADD_HL_RR (cpustate->w.HL) |
| 418 | | break; |
| 409 | ADD_HL_RR (cpustate->w.HL) |
| 410 | CYCLES_PASSED( 4 ); |
| 411 | break; |
| 419 | 412 | case 0x2A: /* LD A,(HL+) */ |
| 420 | 413 | #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ |
| 421 | 414 | if (cpustate->b.H == 0xFE) |
| r14619 | r14620 | |
| 435 | 428 | trash_sprites (state); |
| 436 | 429 | } |
| 437 | 430 | #endif |
| 438 | | |
| 439 | | cpustate->w.HL -= 1; |
| 440 | | break; |
| 431 | cpustate->w.HL -= 1; |
| 432 | CYCLES_PASSED( 4 ); |
| 433 | break; |
| 441 | 434 | case 0x2C: /* INC L */ |
| 442 | 435 | |
| 443 | 436 | INC_8BIT (cpustate->b.L); |
| r14619 | r14620 | |
| 456 | 449 | cpustate->b.F |= FLAG_N | FLAG_H; |
| 457 | 450 | break; |
| 458 | 451 | case 0x30: /* JR NC,n8 */ |
| 452 | { |
| 453 | INT8 offset = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 459 | 454 | |
| 460 | | if (cpustate->b.F & FLAG_C) |
| 461 | | { |
| 462 | | cpustate->w.PC += 1; |
| 463 | | } |
| 464 | | else |
| 465 | | { |
| 466 | | INT8 offset; |
| 467 | | |
| 468 | | offset = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 469 | | cpustate->w.PC += offset; |
| 470 | | CYCLES_PASSED( 4 ); |
| 471 | | } |
| 472 | | break; |
| 455 | if ( ! (cpustate->b.F & FLAG_C) ) |
| 456 | { |
| 457 | cpustate->w.PC += offset; |
| 458 | CYCLES_PASSED( 4 ); |
| 459 | } |
| 460 | } |
| 461 | break; |
| 473 | 462 | case 0x31: /* LD SP,n16 */ |
| 474 | 463 | |
| 475 | 464 | cpustate->w.SP = mem_ReadWord (cpustate, cpustate->w.PC); |
| r14619 | r14620 | |
| 488 | 477 | cpustate->w.HL -= 1; |
| 489 | 478 | break; |
| 490 | 479 | case 0x33: /* INC SP */ |
| 491 | | |
| 492 | | cpustate->w.SP += 1; |
| 493 | | break; |
| 480 | cpustate->w.SP += 1; |
| 481 | CYCLES_PASSED( 4 ); |
| 482 | break; |
| 494 | 483 | case 0x34: /* INC (HL) */ |
| 495 | 484 | |
| 496 | 485 | { |
| 497 | 486 | register UINT8 r, f; |
| 498 | 487 | |
| 499 | 488 | f = (UINT8) (cpustate->b.F & FLAG_C); |
| 500 | | r = (UINT8) (mem_ReadByte (cpustate, cpustate->w.HL) + 1); |
| 489 | r = mem_ReadByte (cpustate, cpustate->w.HL); |
| 490 | r += 1; |
| 501 | 491 | mem_WriteByte (cpustate, cpustate->w.HL, r); |
| 502 | 492 | |
| 503 | 493 | if (r == 0) |
| r14619 | r14620 | |
| 515 | 505 | register UINT8 r, f; |
| 516 | 506 | |
| 517 | 507 | f = (UINT8) ((cpustate->b.F & FLAG_C) | FLAG_N); |
| 518 | | r = (UINT8) (mem_ReadByte (cpustate, cpustate->w.HL) - 1); |
| 508 | r = mem_ReadByte (cpustate, cpustate->w.HL); |
| 509 | r -= 1; |
| 519 | 510 | mem_WriteByte (cpustate, cpustate->w.HL, r); |
| 520 | 511 | |
| 521 | 512 | if (r == 0) |
| r14619 | r14620 | |
| 529 | 520 | break; |
| 530 | 521 | case 0x36: /* LD (HL),n8 */ |
| 531 | 522 | /* FIXED / broken ? */ |
| 532 | | mem_WriteByte (cpustate, cpustate->w.HL, mem_ReadByte (cpustate, cpustate->w.PC++)); |
| 523 | { |
| 524 | UINT8 v = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 525 | mem_WriteByte (cpustate, cpustate->w.HL, v); |
| 526 | } |
| 533 | 527 | break; |
| 534 | 528 | case 0x37: /* SCF */ |
| 535 | 529 | |
| 536 | 530 | cpustate->b.F = (UINT8) ((cpustate->b.F & FLAG_Z) | FLAG_C); |
| 537 | 531 | break; |
| 538 | 532 | case 0x38: /* JR C,n8 */ |
| 533 | { |
| 534 | INT8 offset = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 539 | 535 | |
| 540 | | if (cpustate->b.F & FLAG_C) |
| 541 | | { |
| 542 | | INT8 offset; |
| 543 | | |
| 544 | | offset = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 545 | | cpustate->w.PC += offset; |
| 546 | | |
| 547 | | CYCLES_PASSED( 4 ); |
| 548 | | } |
| 549 | | else |
| 550 | | { |
| 551 | | cpustate->w.PC += 1; |
| 552 | | } |
| 553 | | break; |
| 536 | if (cpustate->b.F & FLAG_C) |
| 537 | { |
| 538 | cpustate->w.PC += offset; |
| 539 | CYCLES_PASSED( 4 ); |
| 540 | } |
| 541 | } |
| 542 | break; |
| 554 | 543 | case 0x39: /* ADD HL,SP */ |
| 555 | | ADD_HL_RR (cpustate->w.SP) |
| 556 | | break; |
| 544 | ADD_HL_RR (cpustate->w.SP) |
| 545 | CYCLES_PASSED( 4 ); |
| 546 | break; |
| 557 | 547 | case 0x3A: /* LD A,(HL-) */ |
| 558 | 548 | #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ |
| 559 | 549 | if (cpustate->b.H == 0xFE) |
| r14619 | r14620 | |
| 566 | 556 | cpustate->w.HL -= 1; |
| 567 | 557 | break; |
| 568 | 558 | case 0x3B: /* DEC SP */ |
| 569 | | |
| 570 | | cpustate->w.SP -= 1; |
| 571 | | break; |
| 559 | cpustate->w.SP -= 1; |
| 560 | CYCLES_PASSED( 4 ); |
| 561 | break; |
| 572 | 562 | case 0x3C: /* INC A */ |
| 573 | 563 | |
| 574 | 564 | INC_8BIT (cpustate->b.A); |
| r14619 | r14620 | |
| 1100 | 1090 | CP_A_X (cpustate->b.A) |
| 1101 | 1091 | break; |
| 1102 | 1092 | case 0xC0: /* RET NZ */ |
| 1103 | | |
| 1104 | | if (!(cpustate->b.F & FLAG_Z)) |
| 1105 | | { |
| 1106 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1107 | | cpustate->w.SP += 2; |
| 1108 | | CYCLES_PASSED( 12 ); |
| 1109 | | } |
| 1110 | | break; |
| 1093 | CYCLES_PASSED( 4 ); |
| 1094 | if (!(cpustate->b.F & FLAG_Z)) |
| 1095 | { |
| 1096 | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1097 | cpustate->w.SP += 2; |
| 1098 | CYCLES_PASSED( 4 ); |
| 1099 | } |
| 1100 | break; |
| 1111 | 1101 | case 0xC1: /* POP BC */ |
| 1112 | 1102 | |
| 1113 | 1103 | cpustate->w.BC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1114 | 1104 | cpustate->w.SP += 2; |
| 1115 | 1105 | break; |
| 1116 | 1106 | case 0xC2: /* JP NZ,n16 */ |
| 1107 | { |
| 1108 | UINT16 addr = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1109 | cpustate->w.PC += 2; |
| 1117 | 1110 | |
| 1118 | | if (cpustate->b.F & FLAG_Z) |
| 1119 | | { |
| 1120 | | cpustate->w.PC += 2; |
| 1121 | | } |
| 1122 | | else |
| 1123 | | { |
| 1124 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1125 | | CYCLES_PASSED( 4 ); |
| 1126 | | } |
| 1127 | | break; |
| 1111 | if ( ! (cpustate->b.F & FLAG_Z) ) |
| 1112 | { |
| 1113 | cpustate->w.PC = addr; |
| 1114 | CYCLES_PASSED( 4 ); |
| 1115 | } |
| 1116 | } |
| 1117 | break; |
| 1128 | 1118 | case 0xC3: /* JP n16 */ |
| 1129 | | |
| 1130 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1131 | | break; |
| 1119 | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1120 | CYCLES_PASSED( 4 ); |
| 1121 | break; |
| 1132 | 1122 | case 0xC4: /* CALL NZ,n16 */ |
| 1123 | { |
| 1124 | UINT16 addr = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1125 | cpustate->w.PC += 2; |
| 1133 | 1126 | |
| 1134 | | if (cpustate->b.F & FLAG_Z) |
| 1135 | | { |
| 1136 | | cpustate->w.PC += 2; |
| 1137 | | } |
| 1138 | | else |
| 1139 | | { |
| 1140 | | register UINT16 PC; |
| 1141 | | PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1142 | | cpustate->w.PC += 2; |
| 1143 | | |
| 1144 | | cpustate->w.SP -= 2; |
| 1145 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1146 | | cpustate->w.PC = PC; |
| 1147 | | CYCLES_PASSED( 12 ); |
| 1148 | | } |
| 1149 | | break; |
| 1127 | if ( ! (cpustate->b.F & FLAG_Z) ) |
| 1128 | { |
| 1129 | cpustate->w.SP -= 2; |
| 1130 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1131 | cpustate->w.PC = addr; |
| 1132 | CYCLES_PASSED( 4 ); |
| 1133 | } |
| 1134 | } |
| 1135 | break; |
| 1150 | 1136 | case 0xC5: /* PUSH BC */ |
| 1151 | | |
| 1152 | | cpustate->w.SP -= 2; |
| 1153 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.BC); |
| 1154 | | break; |
| 1137 | cpustate->w.SP -= 2; |
| 1138 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.BC); |
| 1139 | CYCLES_PASSED( 4 ); |
| 1140 | break; |
| 1155 | 1141 | case 0xC6: /* ADD A,n8 */ |
| 1156 | 1142 | |
| 1157 | 1143 | x = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1158 | 1144 | ADD_A_X (x) |
| 1159 | 1145 | break; |
| 1160 | 1146 | case 0xC7: /* RST 0 */ |
| 1161 | | |
| 1162 | | { |
| 1163 | | register UINT16 PC; |
| 1164 | | PC = cpustate->w.PC; |
| 1165 | | cpustate->w.PC = 0; |
| 1166 | | |
| 1167 | | cpustate->w.SP -= 2; |
| 1168 | | mem_WriteWord (cpustate, cpustate->w.SP, PC); |
| 1169 | | } |
| 1170 | | break; |
| 1147 | cpustate->w.SP -= 2; |
| 1148 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1149 | cpustate->w.PC = 0; |
| 1150 | CYCLES_PASSED( 4 ); |
| 1151 | break; |
| 1171 | 1152 | case 0xC8: /* RET Z */ |
| 1172 | | |
| 1173 | | if (cpustate->b.F & FLAG_Z) |
| 1174 | | { |
| 1175 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1176 | | cpustate->w.SP += 2; |
| 1177 | | CYCLES_PASSED( 12 ); |
| 1178 | | } |
| 1179 | | break; |
| 1153 | CYCLES_PASSED( 4 ); |
| 1154 | if (cpustate->b.F & FLAG_Z) |
| 1155 | { |
| 1156 | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1157 | cpustate->w.SP += 2; |
| 1158 | CYCLES_PASSED( 4 ); |
| 1159 | } |
| 1160 | break; |
| 1180 | 1161 | case 0xC9: /* RET */ |
| 1181 | | |
| 1182 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1183 | | cpustate->w.SP += 2; |
| 1184 | | break; |
| 1162 | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1163 | cpustate->w.SP += 2; |
| 1164 | CYCLES_PASSED( 4 ); |
| 1165 | break; |
| 1185 | 1166 | case 0xCA: /* JP Z,n16 */ |
| 1167 | { |
| 1168 | UINT16 addr = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1169 | cpustate->w.PC += 2; |
| 1186 | 1170 | |
| 1187 | | if (cpustate->b.F & FLAG_Z) |
| 1188 | | { |
| 1189 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1190 | | CYCLES_PASSED( 4 ); |
| 1191 | | } |
| 1192 | | else |
| 1193 | | { |
| 1194 | | cpustate->w.PC += 2; |
| 1195 | | } |
| 1196 | | break; |
| 1171 | if (cpustate->b.F & FLAG_Z) |
| 1172 | { |
| 1173 | cpustate->w.PC = addr; |
| 1174 | CYCLES_PASSED( 4 ); |
| 1175 | } |
| 1176 | } |
| 1177 | break; |
| 1197 | 1178 | case 0xCB: /* PREFIX! */ |
| 1198 | 1179 | x = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1199 | | CYCLES_PASSED( CyclesCB[x] ); |
| 1200 | 1180 | switch (x) |
| 1201 | 1181 | { |
| 1202 | 1182 | #include "opc_cb.h" |
| 1203 | 1183 | } |
| 1204 | 1184 | break; |
| 1205 | 1185 | case 0xCC: /* CALL Z,n16 */ |
| 1186 | { |
| 1187 | UINT16 addr = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1188 | cpustate->w.PC += 2; |
| 1206 | 1189 | |
| 1207 | | if (cpustate->b.F & FLAG_Z) |
| 1208 | | { |
| 1209 | | register UINT16 PC; |
| 1210 | | PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1211 | | cpustate->w.PC += 2; |
| 1212 | | |
| 1213 | | cpustate->w.SP -= 2; |
| 1214 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1215 | | cpustate->w.PC = PC; |
| 1216 | | CYCLES_PASSED( 12 ); |
| 1217 | | } |
| 1218 | | else |
| 1219 | | { |
| 1220 | | cpustate->w.PC += 2; |
| 1221 | | } |
| 1222 | | break; |
| 1190 | if (cpustate->b.F & FLAG_Z) |
| 1191 | { |
| 1192 | cpustate->w.SP -= 2; |
| 1193 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1194 | cpustate->w.PC = addr; |
| 1195 | CYCLES_PASSED( 4 ); |
| 1196 | } |
| 1197 | } |
| 1198 | break; |
| 1223 | 1199 | case 0xCD: /* CALL n16 */ |
| 1224 | | { |
| 1225 | | register UINT16 PC; |
| 1226 | | PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1227 | | cpustate->w.PC += 2; |
| 1200 | { |
| 1201 | UINT16 addr = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1202 | cpustate->w.PC += 2; |
| 1228 | 1203 | |
| 1229 | | cpustate->w.SP -= 2; |
| 1230 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1231 | | cpustate->w.PC = PC; |
| 1232 | | } |
| 1233 | | break; |
| 1204 | cpustate->w.SP -= 2; |
| 1205 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1206 | cpustate->w.PC = addr; |
| 1207 | CYCLES_PASSED( 4 ); |
| 1208 | } |
| 1209 | break; |
| 1234 | 1210 | case 0xCE: /* ADC A,n8 */ |
| 1235 | 1211 | |
| 1236 | 1212 | x = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1237 | 1213 | ADC_A_X (x) |
| 1238 | 1214 | break; |
| 1239 | 1215 | case 0xCF: /* RST 8 */ |
| 1240 | | |
| 1241 | | cpustate->w.SP -= 2; |
| 1242 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1243 | | cpustate->w.PC = 8; |
| 1244 | | break; |
| 1216 | cpustate->w.SP -= 2; |
| 1217 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1218 | cpustate->w.PC = 8; |
| 1219 | CYCLES_PASSED( 4 ); |
| 1220 | break; |
| 1245 | 1221 | case 0xD0: /* RET NC */ |
| 1246 | | |
| 1247 | | if (!(cpustate->b.F & FLAG_C)) |
| 1248 | | { |
| 1249 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1250 | | cpustate->w.SP += 2; |
| 1251 | | CYCLES_PASSED( 12 ); |
| 1252 | | } |
| 1253 | | break; |
| 1222 | CYCLES_PASSED( 4 ); |
| 1223 | if (!(cpustate->b.F & FLAG_C)) |
| 1224 | { |
| 1225 | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1226 | cpustate->w.SP += 2; |
| 1227 | CYCLES_PASSED( 4 ); |
| 1228 | } |
| 1229 | break; |
| 1254 | 1230 | case 0xD1: /* POP DE */ |
| 1255 | 1231 | |
| 1256 | 1232 | cpustate->w.DE = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1257 | 1233 | cpustate->w.SP += 2; |
| 1258 | 1234 | break; |
| 1259 | 1235 | case 0xD2: /* JP NC,n16 */ |
| 1236 | { |
| 1237 | UINT16 addr = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1238 | cpustate->w.PC += 2; |
| 1260 | 1239 | |
| 1261 | | if (cpustate->b.F & FLAG_C) |
| 1262 | | { |
| 1263 | | cpustate->w.PC += 2; |
| 1264 | | } |
| 1265 | | else |
| 1266 | | { |
| 1267 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1268 | | CYCLES_PASSED( 4 ); |
| 1269 | | } |
| 1270 | | break; |
| 1240 | if ( ! (cpustate->b.F & FLAG_C) ) |
| 1241 | { |
| 1242 | cpustate->w.PC = addr; |
| 1243 | CYCLES_PASSED( 4 ); |
| 1244 | } |
| 1245 | } |
| 1246 | break; |
| 1271 | 1247 | case 0xD3: /* EH? */ |
| 1272 | 1248 | break; |
| 1273 | 1249 | case 0xD4: /* CALL NC,n16 */ |
| 1250 | { |
| 1251 | UINT16 addr = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1252 | cpustate->w.PC += 2; |
| 1274 | 1253 | |
| 1275 | | if (cpustate->b.F & FLAG_C) |
| 1276 | | { |
| 1277 | | cpustate->w.PC += 2; |
| 1278 | | } |
| 1279 | | else |
| 1280 | | { |
| 1281 | | register UINT16 PC; |
| 1282 | | PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1283 | | cpustate->w.PC += 2; |
| 1284 | | |
| 1285 | | cpustate->w.SP -= 2; |
| 1286 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1287 | | cpustate->w.PC = PC; |
| 1288 | | CYCLES_PASSED( 12 ); |
| 1289 | | } |
| 1290 | | break; |
| 1254 | if ( ! (cpustate->b.F & FLAG_C) ) |
| 1255 | { |
| 1256 | cpustate->w.SP -= 2; |
| 1257 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1258 | cpustate->w.PC = addr; |
| 1259 | CYCLES_PASSED( 4 ); |
| 1260 | } |
| 1261 | } |
| 1262 | break; |
| 1291 | 1263 | case 0xD5: /* PUSH DE */ |
| 1292 | | |
| 1293 | | cpustate->w.SP -= 2; |
| 1294 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.DE); |
| 1295 | | break; |
| 1264 | cpustate->w.SP -= 2; |
| 1265 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.DE); |
| 1266 | CYCLES_PASSED( 4 ); |
| 1267 | break; |
| 1296 | 1268 | case 0xD6: /* SUB A,n8 */ |
| 1297 | 1269 | |
| 1298 | 1270 | x = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1299 | 1271 | SUB_A_X (x) |
| 1300 | 1272 | break; |
| 1301 | 1273 | case 0xD7: /* RST $10 */ |
| 1302 | | |
| 1303 | | cpustate->w.SP -= 2; |
| 1304 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1305 | | cpustate->w.PC = 0x10; |
| 1306 | | break; |
| 1274 | cpustate->w.SP -= 2; |
| 1275 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1276 | cpustate->w.PC = 0x10; |
| 1277 | CYCLES_PASSED( 4 ); |
| 1278 | break; |
| 1307 | 1279 | case 0xD8: /* RET C */ |
| 1308 | | |
| 1309 | | if (cpustate->b.F & FLAG_C) |
| 1310 | | { |
| 1311 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1312 | | cpustate->w.SP += 2; |
| 1313 | | CYCLES_PASSED( 12 ); |
| 1314 | | } |
| 1315 | | break; |
| 1280 | CYCLES_PASSED( 4 ); |
| 1281 | if (cpustate->b.F & FLAG_C) |
| 1282 | { |
| 1283 | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1284 | cpustate->w.SP += 2; |
| 1285 | CYCLES_PASSED( 4 ); |
| 1286 | } |
| 1287 | break; |
| 1316 | 1288 | case 0xD9: /* RETI */ |
| 1317 | | |
| 1318 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1319 | | cpustate->w.SP += 2; |
| 1320 | | cpustate->w.enable |= IME; |
| 1321 | | break; |
| 1289 | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); |
| 1290 | cpustate->w.SP += 2; |
| 1291 | cpustate->w.enable |= IME; |
| 1292 | CYCLES_PASSED( 4 ); |
| 1293 | break; |
| 1322 | 1294 | case 0xDA: /* JP C,n16 */ |
| 1295 | { |
| 1296 | UINT16 addr = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1297 | cpustate->w.PC += 2; |
| 1323 | 1298 | |
| 1324 | | if (cpustate->b.F & FLAG_C) |
| 1325 | | { |
| 1326 | | cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1327 | | CYCLES_PASSED( 4 ); |
| 1328 | | } |
| 1329 | | else |
| 1330 | | { |
| 1331 | | cpustate->w.PC += 2; |
| 1332 | | } |
| 1333 | | break; |
| 1299 | if (cpustate->b.F & FLAG_C) |
| 1300 | { |
| 1301 | cpustate->w.PC = addr; |
| 1302 | CYCLES_PASSED( 4 ); |
| 1303 | } |
| 1304 | } |
| 1305 | break; |
| 1334 | 1306 | case 0xDB: /* EH? */ |
| 1335 | 1307 | break; |
| 1336 | 1308 | case 0xDC: /* CALL C,n16 */ |
| 1309 | { |
| 1310 | UINT16 addr = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1311 | cpustate->w.PC += 2; |
| 1337 | 1312 | |
| 1338 | | if (cpustate->b.F & FLAG_C) |
| 1339 | | { |
| 1340 | | register UINT16 PC; |
| 1341 | | PC = mem_ReadWord (cpustate, cpustate->w.PC); |
| 1342 | | cpustate->w.PC += 2; |
| 1343 | | |
| 1344 | | cpustate->w.SP -= 2; |
| 1345 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1346 | | cpustate->w.PC = PC; |
| 1347 | | CYCLES_PASSED( 12 ); |
| 1348 | | } |
| 1349 | | else |
| 1350 | | { |
| 1351 | | cpustate->w.PC += 2; |
| 1352 | | } |
| 1353 | | break; |
| 1313 | if (cpustate->b.F & FLAG_C) |
| 1314 | { |
| 1315 | cpustate->w.SP -= 2; |
| 1316 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1317 | cpustate->w.PC = addr; |
| 1318 | CYCLES_PASSED( 4 ); |
| 1319 | } |
| 1320 | } |
| 1321 | break; |
| 1354 | 1322 | case 0xDD: /* EH? */ |
| 1355 | 1323 | break; |
| 1356 | 1324 | case 0xDE: /* SBC A,n8 */ |
| r14619 | r14620 | |
| 1359 | 1327 | SBC_A_X (x) |
| 1360 | 1328 | break; |
| 1361 | 1329 | case 0xDF: /* RST $18 */ |
| 1362 | | |
| 1363 | | cpustate->w.SP -= 2; |
| 1364 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1365 | | cpustate->w.PC = 0x18; |
| 1366 | | break; |
| 1330 | cpustate->w.SP -= 2; |
| 1331 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1332 | cpustate->w.PC = 0x18; |
| 1333 | CYCLES_PASSED( 4 ); |
| 1334 | break; |
| 1367 | 1335 | case 0xE0: /* LD ($FF00+n8),A */ |
| 1368 | | mem_WriteByte (cpustate, mem_ReadByte (cpustate, cpustate->w.PC++) + 0xFF00, cpustate->b.A); |
| 1336 | { |
| 1337 | UINT8 v = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1338 | mem_WriteByte (cpustate, 0xFF00 + v, cpustate->b.A); |
| 1339 | } |
| 1369 | 1340 | break; |
| 1370 | 1341 | case 0xE1: /* POP HL */ |
| 1371 | 1342 | |
| r14619 | r14620 | |
| 1381 | 1352 | case 0xE4: /* EH? */ |
| 1382 | 1353 | break; |
| 1383 | 1354 | case 0xE5: /* PUSH HL */ |
| 1384 | | |
| 1385 | | cpustate->w.SP -= 2; |
| 1386 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.HL); |
| 1387 | | break; |
| 1355 | cpustate->w.SP -= 2; |
| 1356 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.HL); |
| 1357 | CYCLES_PASSED( 4 ); |
| 1358 | break; |
| 1388 | 1359 | case 0xE6: /* AND A,n8 */ |
| 1389 | 1360 | |
| 1390 | 1361 | x = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1391 | 1362 | AND_A_X (x) |
| 1392 | 1363 | break; |
| 1393 | 1364 | case 0xE7: /* RST $20 */ |
| 1394 | | |
| 1395 | | cpustate->w.SP -= 2; |
| 1396 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1397 | | cpustate->w.PC = 0x20; |
| 1398 | | break; |
| 1365 | cpustate->w.SP -= 2; |
| 1366 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1367 | cpustate->w.PC = 0x20; |
| 1368 | CYCLES_PASSED( 4 ); |
| 1369 | break; |
| 1399 | 1370 | case 0xE8: /* ADD SP,n8 */ |
| 1400 | 1371 | /* |
| 1401 | 1372 | * Z - Reset. |
| r14619 | r14620 | |
| 1407 | 1378 | { |
| 1408 | 1379 | register INT32 n; |
| 1409 | 1380 | |
| 1410 | | n = (INT32) ((INT8) mem_ReadByte (cpustate, cpustate->w.PC++)); |
| 1381 | n = (INT8) mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1411 | 1382 | |
| 1412 | 1383 | if ( ( cpustate->w.SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF ) |
| 1413 | 1384 | { |
| r14619 | r14620 | |
| 1425 | 1396 | |
| 1426 | 1397 | cpustate->w.SP = (UINT16) ( cpustate->w.SP + n ); |
| 1427 | 1398 | } |
| 1399 | CYCLES_PASSED( 8 ); |
| 1428 | 1400 | break; |
| 1429 | 1401 | case 0xE9: /* JP (HL) */ |
| 1430 | 1402 | |
| r14619 | r14620 | |
| 1447 | 1419 | XOR_A_X (x) |
| 1448 | 1420 | break; |
| 1449 | 1421 | case 0xEF: /* RST $28 */ |
| 1450 | | |
| 1451 | | cpustate->w.SP -= 2; |
| 1452 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1453 | | cpustate->w.PC = 0x28; |
| 1454 | | break; |
| 1422 | cpustate->w.SP -= 2; |
| 1423 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1424 | cpustate->w.PC = 0x28; |
| 1425 | CYCLES_PASSED( 4 ); |
| 1426 | break; |
| 1455 | 1427 | case 0xF0: /* LD A,($FF00+n8) */ |
| 1456 | | |
| 1457 | | cpustate->b.A = mem_ReadByte (cpustate, 0xFF00 + mem_ReadByte (cpustate, cpustate->w.PC++)); |
| 1428 | { |
| 1429 | UINT8 v = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1430 | cpustate->b.A = mem_ReadByte (cpustate, 0xFF00 + v); |
| 1431 | } |
| 1458 | 1432 | break; |
| 1459 | 1433 | case 0xF1: /* POP AF */ |
| 1460 | 1434 | |
| r14619 | r14620 | |
| 1472 | 1446 | case 0xF4: /* EH? */ |
| 1473 | 1447 | break; |
| 1474 | 1448 | case 0xF5: /* PUSH AF */ |
| 1475 | | |
| 1476 | | cpustate->w.SP -= 2; |
| 1477 | | mem_WriteWord (cpustate, cpustate->w.SP, (UINT16) (cpustate->w.AF & 0xFFF0)); |
| 1478 | | break; |
| 1449 | cpustate->w.SP -= 2; |
| 1450 | mem_WriteWord (cpustate, cpustate->w.SP, (UINT16) (cpustate->w.AF & 0xFFF0)); |
| 1451 | CYCLES_PASSED( 4 ); |
| 1452 | break; |
| 1479 | 1453 | case 0xF6: /* OR A,n8 */ |
| 1480 | 1454 | |
| 1481 | 1455 | x = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1482 | 1456 | OR_A_X (x) |
| 1483 | 1457 | break; |
| 1484 | 1458 | case 0xF7: /* RST $30 */ |
| 1485 | | |
| 1486 | | cpustate->w.SP -= 2; |
| 1487 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1488 | | cpustate->w.PC = 0x30; |
| 1489 | | break; |
| 1459 | cpustate->w.SP -= 2; |
| 1460 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1461 | cpustate->w.PC = 0x30; |
| 1462 | CYCLES_PASSED( 4 ); |
| 1463 | break; |
| 1490 | 1464 | case 0xF8: /* LD HL,SP+n8 */ |
| 1491 | 1465 | /* |
| 1492 | 1466 | * n = one UINT8 signed immediate value. |
| r14619 | r14620 | |
| 1501 | 1475 | { |
| 1502 | 1476 | register INT32 n; |
| 1503 | 1477 | |
| 1504 | | n = (INT32) ((INT8) mem_ReadByte (cpustate, cpustate->w.PC++)); |
| 1478 | n = (INT8) mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1505 | 1479 | |
| 1506 | 1480 | if ( ( cpustate->w.SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF ) |
| 1507 | 1481 | { |
| r14619 | r14620 | |
| 1519 | 1493 | |
| 1520 | 1494 | cpustate->w.HL = (UINT16) ( cpustate->w.SP + n ); |
| 1521 | 1495 | } |
| 1496 | CYCLES_PASSED( 4 ); |
| 1522 | 1497 | break; |
| 1523 | 1498 | case 0xF9: /* LD SP,HL */ |
| 1524 | | |
| 1525 | | cpustate->w.SP = cpustate->w.HL; |
| 1526 | | break; |
| 1499 | cpustate->w.SP = cpustate->w.HL; |
| 1500 | CYCLES_PASSED( 4 ); |
| 1501 | break; |
| 1527 | 1502 | case 0xFA: /* LD A,(n16) */ |
| 1528 | | |
| 1529 | | cpustate->b.A = mem_ReadByte (cpustate, mem_ReadWord (cpustate, cpustate->w.PC)); |
| 1530 | | cpustate->w.PC += 2; |
| 1531 | | break; |
| 1503 | cpustate->b.A = mem_ReadByte (cpustate, mem_ReadWord (cpustate, cpustate->w.PC)); |
| 1504 | cpustate->w.PC += 2; |
| 1505 | break; |
| 1532 | 1506 | case 0xFB: /* EI */ |
| 1533 | | |
| 1534 | | cpustate->w.enable |= IME; |
| 1535 | | cpustate->w.ei_delay = 1; |
| 1536 | | break; |
| 1507 | cpustate->w.enable |= IME; |
| 1508 | cpustate->w.ei_delay = 1; |
| 1509 | break; |
| 1537 | 1510 | case 0xFC: /* EH? */ |
| 1538 | | break; |
| 1511 | break; |
| 1539 | 1512 | case 0xFD: /* EH? */ |
| 1540 | | break; |
| 1513 | break; |
| 1541 | 1514 | case 0xFE: /* CP A,n8 */ |
| 1542 | | |
| 1543 | | x = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1544 | | CP_A_X (x) |
| 1545 | | break; |
| 1515 | x = mem_ReadByte (cpustate, cpustate->w.PC++); |
| 1516 | CP_A_X (x) |
| 1517 | break; |
| 1546 | 1518 | case 0xFF: /* RST $38 */ |
| 1547 | | |
| 1548 | | cpustate->w.SP -= 2; |
| 1549 | | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1550 | | cpustate->w.PC = 0x38; |
| 1551 | | break; |
| 1519 | cpustate->w.SP -= 2; |
| 1520 | mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); |
| 1521 | cpustate->w.PC = 0x38; |
| 1522 | CYCLES_PASSED( 4 ); |
| 1523 | break; |