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r14487 Thursday 16th February, 2012 at 22:23:34 UTC by MooglyGuy

[N64] Fixed missing text in Super Mario 64 and other games. [Ryan Holtz] [N64] Added skeleton 64DD driver. Boots the 64DD IPL, but does not emulate the hardware yet. [Ryan Holtz] - User Note: You will need an unmodified 64DD IPL dump. NOT one that has had the first 4K replaced with a CIC-6102 or other game's boot block. [N64] Tweaked MI interrupt handling to guard against interrupts getting "lost" [Ryan Holtz] (nw): Historic note, to my knowledge this is the first time a public emulator can boot an unmodified 64DD IPL dump, but I'm not 100% sure.

[src/mame/includes]	n64.h
[src/mame/machine]	n64.c
[src/mame/video]	n64.c n64.h
[src/mess]	mess.lst
[src/mess/drivers]	n64.c

src/mame/machine/n64.c

r14486	r14487
41	41	rspcpu = machine().device("rsp");
42	42	mem_map = maincpu->memory().space(AS_PROGRAM);
43	43
44		mi_version = 0;
	44	mi_version = 0x02020102;
45	45	mi_interrupt = 0;
46	46	mi_intr_mask = 0;
47	47	mi_mode = 0;
r14486	r14487
115	115	boot_checksum += cart[i/4]+i;
116	116	}
117	117
118		if (boot_checksum == U64(0x000000d057e84864))
	118	// CIC-NUS-6102 (default)
	119	pif_ram[0x24] = 0x00;
	120	pif_ram[0x25] = 0x02;
	121	pif_ram[0x26] = 0x3f;
	122	pif_ram[0x27] = 0x3f;
	123	dd_present = false;
	124
	125	if (boot_checksum == U64(0x00000000001ff230))
	126	{
	127	//printf("64DD detected\n");
	128	pif_ram[0x24] = 0x00;
	129	pif_ram[0x25] = 0x0a;
	130	pif_ram[0x26] = 0xdd; // How utterly predictable
	131	pif_ram[0x27] = 0x3f;
	132	dd_present = true;
	133	}
	134	else if (boot_checksum == U64(0x000000cffb830843) || boot_checksum == U64(0x000000d0027fdf31))
119	135	{
120	136	// CIC-NUS-6101
121		printf("CIC-NUS-6102 detected\n");
	137	//printf("CIC-NUS-6101 detected\n");
122	138	pif_ram[0x24] = 0x00;
123		pif_ram[0x25] = 0x02;
124		pif_ram[0x26] = 0x3f;
125		pif_ram[0x27] = 0x3f;
126		// crc_seed = 0x3f;
127		}
128		else if (boot_checksum == U64(0x000000cffb830843) || boot_checksum == U64(0x000000d0027fdf31))
129		{
130		// CIC-NUS-6103
131		printf("CIC-NUS-6101 detected\n");
132		// crc_seed = 0x78;
133		pif_ram[0x24] = 0x00;
134	139	pif_ram[0x25] = 0x06;
135	140	pif_ram[0x26] = 0x3f;
136	141	pif_ram[0x27] = 0x3f;
r14486	r14487
138	143	else if (boot_checksum == U64(0x000000d6499e376b))
139	144	{
140	145	// CIC-NUS-6103
141		printf("CIC-NUS-6103 detected\n");
142		// crc_seed = 0x78;
	146	//printf("CIC-NUS-6103 detected\n");
143	147	pif_ram[0x24] = 0x00;
144	148	pif_ram[0x25] = 0x02;
145	149	pif_ram[0x26] = 0x78;
r14486	r14487
148	152	else if (boot_checksum == U64(0x0000011a4a1604b6))
149	153	{
150	154	// CIC-NUS-6105
151		printf("CIC-NUS-6105 detected\n");
152		// crc_seed = 0x91;
	155	//printf("CIC-NUS-6105 detected\n");
153	156
154		// first_rsp = 0;
155	157	pif_ram[0x24] = 0x00;
156	158	pif_ram[0x25] = 0x02;
157	159	pif_ram[0x26] = 0x91;
r14486	r14487
160	162	else if (boot_checksum == U64(0x000000d6d5de4ba0))
161	163	{
162	164	// CIC-NUS-6106
163		printf("CIC-NUS-6106 detected\n");
164		// crc_seed = 0x85;
	165	//printf("CIC-NUS-6106 detected\n");
165	166	pif_ram[0x24] = 0x00;
166	167	pif_ram[0x25] = 0x02;
167	168	pif_ram[0x26] = 0x85;
r14486	r14487
169	170	}
170	171	else
171	172	{
172		printf("Unknown BootCode Checksum %08X%08X\n", (UINT32)(boot_checksum>>32),(UINT32)(boot_checksum));
	173	//printf("Unknown BootCode Checksum %08X%08X\n", (UINT32)(boot_checksum>>32),(UINT32)(boot_checksum));
173	174	}
174	175	}
175	176
r14486	r14487
188	189
189	190	READ32_MEMBER( n64_periphs::mi_reg_r )
190	191	{
191		//printf("mi_reg_r %08x\n", offset * 4);
	192	UINT32 ret = 0;
192	193	switch (offset)
193	194	{
194	195	case 0x00/4:            // MI_MODE_REG
195		return mi_mode;
	196	ret = mi_mode;
	197	break;
196	198
197	199	case 0x04/4:         // MI_VERSION_REG
198		return mi_version;
	200	ret = mi_version;
	201	break;
199	202
200	203	case 0x08/4:         // MI_INTR_REG
201		return mi_interrupt;
	204	ret = mi_interrupt;
	205	break;
202	206
203	207	case 0x0c/4:         // MI_INTR_MASK_REG
204		return mi_intr_mask;
	208	ret = mi_intr_mask;
	209	break;
205	210
206	211	default:
207	212	logerror("mi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(&mem_map->device()));
208	213	break;
209	214	}
210	215
211		return 0;
	216	//printf("mi_reg_r %08x = %08x\n", offset * 4, ret);
	217	return ret;
212	218	}
213	219
214	220	WRITE32_MEMBER( n64_periphs::mi_reg_w )
r14486	r14487
227	233	{
228	234	clear_rcp_interrupt(DP_INTERRUPT);
229	235	}
	236	mi_mode &= ~0x7f;
	237	mi_mode |= data & 0x7f;
230	238	break;
231	239
232	240	case 0x04/4:      // MI_VERSION_REG
r14486	r14487
283	291	{
284	292	mi_intr_mask |= 0x20;      // set DP mask
285	293	}
	294	check_interrupts();
286	295	break;
287	296	}
288	297
r14486	r14487
297	306	machine.device<n64_periphs>("rcp")->signal_rcp_interrupt(interrupt);
298	307	}
299	308
300		void n64_periphs::signal_rcp_interrupt(int interrupt)
	309	void n64_periphs::check_interrupts()
301	310	{
302		if (mi_intr_mask & interrupt)
	311	if (mi_intr_mask & mi_interrupt)
303	312	{
304		mi_interrupt |= interrupt;
305
306	313	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, ASSERT_LINE);
307	314	}
	315	else
	316	{
	317	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
	318	}
308	319	}
309	320
	321	void n64_periphs::signal_rcp_interrupt(int interrupt)
	322	{
	323	mi_interrupt |= interrupt;
	324
	325	check_interrupts();
	326	}
	327
310	328	void n64_periphs::clear_rcp_interrupt(int interrupt)
311	329	{
312	330	mi_interrupt &= ~interrupt;
313	331
314		if (!mi_interrupt)
315		{
316		cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
317		}
	332	check_interrupts();
318	333	}
319	334
320	335	READ32_MEMBER( n64_periphs::is64_r )
r14486	r14487
350	365	case 0x0014/4:
351	366	for(i = 0x20; i < (0x20 + data); i++)
352	367	{
353		printf( "%c", is64_buffer[i] );
	368	//printf( "%c", is64_buffer[i] );
354	369	if(is64_buffer[i] == 0x0a)
355	370	{
356		printf( "%c", 0x0d );
	371	//printf( "%c", 0x0d );
357	372	}
358	373	is64_buffer[i] = 0;
359	374	}
r14486	r14487
371	386	READ32_MEMBER( n64_periphs::open_r )
372	387	{
373	388	UINT32 retval = (offset << 2) & 0x0000ffff;
374		retval = (retval << 16) | retval;
	389	retval = ((retval + 2) << 16) | retval;
375	390	return retval;
376	391	}
377	392
r14486	r14487
395	410
396	411	READ32_MEMBER( n64_periphs::rdram_reg_r )
397	412	{
398		//printf("rdram_reg_r %08x\n", offset * 4);
	413	//printf("rdram_reg_r %08x = %08x\n", offset * 4, rdram_regs[offset]);
399	414	if(offset > 0x24/4)
400	415	{
401	416	logerror("rdram_reg_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(maincpu));
r14486	r14487
409	424	//printf("rdram_reg_w %08x %08x %08x\n", offset * 4, data, mem_mask);
410	425	if(offset > 0x24/4)
411	426	{
412		logerror("mi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, cpu_get_pc(maincpu));
	427	logerror("rdram_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, cpu_get_pc(maincpu));
413	428	return;
414	429	}
415	430	COMBINE_DATA(&rdram_regs[offset]);
r14486	r14487
436	451
437	452	if ((sp_mem_addr & 0xfff) + (sp_dma_length) > 0x1000)
438	453	{
439		printf("sp_dma: dma out of memory area: %08X, %08X\n", sp_mem_addr, sp_dma_length);
	454	//printf("sp_dma: dma out of memory area: %08X, %08X\n", sp_mem_addr, sp_dma_length);
440	455	//fatalerror("sp_dma: dma out of memory area: %08X, %08X\n", sp_mem_addr, sp_dma_length);
441	456	sp_dma_length = 0x1000 - (sp_mem_addr & 0xfff);
442	457	}
r14486	r14487
508	523
509	524	UINT32 n64_periphs::sp_reg_r(UINT32 offset)
510	525	{
511		//printf("sp_reg_r %08x\n", offset * 4);
	526	UINT32 ret = 0;
512	527	switch (offset)
513	528	{
514	529	case 0x00/4:      // SP_MEM_ADDR_REG
515		return sp_mem_addr;
	530	ret = sp_mem_addr;
	531	break;
516	532
517	533	case 0x04/4:      // SP_DRAM_ADDR_REG
518		return sp_dram_addr;
	534	ret = sp_dram_addr;
	535	break;
519	536
520	537	case 0x08/4:      // SP_RD_LEN_REG
521		return (sp_dma_skip << 20) | (sp_dma_count << 12) | sp_dma_length;
	538	ret = (sp_dma_skip << 20) | (sp_dma_count << 12) | sp_dma_length;
	539	break;
522	540
523	541	case 0x10/4:      // SP_STATUS_REG
524		return cpu_get_reg(rspcpu, RSP_SR);
	542	//machine().scheduler().synchronize();
	543	//machine().scheduler().boost_interleave(attotime::from_msec(1), attotime::from_msec(m));
	544	ret = cpu_get_reg(rspcpu, RSP_SR);
	545	break;
525	546
526	547	case 0x14/4:      // SP_DMA_FULL_REG
527		return 0;
	548	ret = 0;
	549	break;
528	550
529	551	case 0x18/4:      // SP_DMA_BUSY_REG
530		return 0;
	552	ret = 0;
	553	break;
531	554
532	555	case 0x1c/4:      // SP_SEMAPHORE_REG
	556	//machine().scheduler().boost_interleave(attotime::from_usec(1), attotime::from_usec(1));
533	557	if( sp_semaphore )
534	558	{
535		return 1;
	559	ret = 1;
536	560	}
537	561	else
538	562	{
539	563	sp_semaphore = 1;
540		return 0;
	564	ret = 0;
541	565	}
	566	break;
542	567
543	568	case 0x20/4:        // DP_CMD_START
544	569	case 0x24/4:        // DP_CMD_END
r14486	r14487
546	571	case 0x34/4:        // DP_CMD_BUSY
547	572	case 0x38/4:        // DP_CMD_PIPE_BUSY
548	573	case 0x3c/4:        // DP_CMD_TMEM_BUSY
549		return 0;
	574	break;
550	575
551	576	case 0x2c/4:        // DP_CMD_STATUS
552		return 0x88;
	577	ret = 0x88;
	578	break;
553	579
554	580	case 0x30/4:        // DP_CMD_CLOCK
555		return ++dp_clock;
	581	ret = ++dp_clock;
	582	break;
556	583
557	584	case 0x40000/4:     // PC
558		return cpu_get_reg(rspcpu, RSP_PC) & 0x00000fff;
	585	ret = cpu_get_reg(rspcpu, RSP_PC) & 0x00000fff;
	586	break;
559	587
560	588	default:
561	589	logerror("sp_reg_r: %08X at %08X\n", offset, cpu_get_pc(maincpu));
562	590	break;
563	591	}
564	592
565		return 0;
	593	//printf("sp_reg_r %08x = %08x\n", offset * 4, ret);
	594	return ret;
566	595	}
567	596
568	597	READ32_DEVICE_HANDLER( n64_sp_reg_r )
r14486	r14487
573	602	void n64_periphs::sp_reg_w(UINT32 offset, UINT32 data, UINT32 mem_mask)
574	603	{
575	604	//printf("sp_reg_w %08x %08x %08x\n", offset * 4, data, mem_mask);
	605	//device_yield(machine().device("maincpu"));
	606
576	607	if ((offset & 0x10000) == 0)
577	608	{
578	609	switch (offset & 0xffff)
r14486	r14487
716	747	}
717	748
718	749	case 0x1c/4:      // SP_SEMAPHORE_REG
	750	//machine().scheduler().boost_interleave(attotime::from_usec(1), attotime::from_usec(1));
719	751	if(data == 0)
720	752	{
721	753	sp_semaphore = 0;
r14486	r14487
764	796	READ32_DEVICE_HANDLER( n64_dp_reg_r )
765	797	{
766	798	n64_state *state = device->machine().driver_data<n64_state>();
767
768		//printf("dp_reg_r %08x\n", offset);
	799	UINT32 ret = 0;
769	800	switch (offset)
770	801	{
771	802	case 0x00/4:      // DP_START_REG
772		return state->m_rdp->GetStartReg();
	803	ret = state->m_rdp->GetStartReg();
	804	break;
773	805
774	806	case 0x04/4:      // DP_END_REG
775		return state->m_rdp->GetEndReg();
	807	ret = state->m_rdp->GetEndReg();
	808	break;
776	809
777	810	case 0x08/4:      // DP_CURRENT_REG
778		return state->m_rdp->GetCurrentReg();
	811	ret = state->m_rdp->GetCurrentReg();
	812	break;
779	813
780	814	case 0x0c/4:      // DP_STATUS_REG
781		return state->m_rdp->GetStatusReg();
	815	ret = state->m_rdp->GetStatusReg();
	816	break;
782	817
783	818	default:
784	819	logerror("dp_reg_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(device));
785	820	break;
786	821	}
787	822
788		return 0;
	823	//printf("dp_reg_r %08x = %08x\n", offset, ret);
	824	return ret;
789	825	}
790	826
791	827	WRITE32_DEVICE_HANDLER( n64_dp_reg_w )
r14486	r14487
893	929
894	930	READ32_MEMBER( n64_periphs::vi_reg_r )
895	931	{
896		//printf("vi_reg_r %08x\n", offset * 4);
	932	UINT32 ret = 0;
897	933	switch (offset)
898	934	{
899	935	case 0x00/4:      // VI_CONTROL_REG
900		return vi_control;
	936	ret = vi_control;
	937	break;
901	938
902	939	case 0x04/4:      // VI_ORIGIN_REG
903		return vi_origin;
	940	ret = vi_origin;
	941	break;
904	942
905	943	case 0x08/4:      // VI_WIDTH_REG
906		return vi_width;
	944	ret = vi_width;
	945	break;
907	946
908	947	case 0x0c/4:
909		return vi_intr;
	948	ret = vi_intr;
	949	break;
910	950
911	951	case 0x10/4:      // VI_CURRENT_REG
912		return machine().primary_screen->vpos() << 1;
	952	ret = machine().primary_screen->vpos() << 1;
	953	break;
913	954
914	955	case 0x14/4:      // VI_BURST_REG
915		return vi_burst;
	956	ret = vi_burst;
	957	break;
916	958
917	959	case 0x18/4:      // VI_V_SYNC_REG
918		return vi_vsync;
	960	ret = vi_vsync;
	961	break;
919	962
920	963	case 0x1c/4:      // VI_H_SYNC_REG
921		return vi_hsync;
	964	ret = vi_hsync;
	965	break;
922	966
923	967	case 0x20/4:      // VI_LEAP_REG
924		return vi_leap;
	968	ret = vi_leap;
	969	break;
925	970
926	971	case 0x24/4:      // VI_H_START_REG
927		return vi_hstart;
	972	ret = vi_hstart;
	973	break;
928	974
929	975	case 0x28/4:      // VI_V_START_REG
930		return vi_vstart;
	976	ret = vi_vstart;
	977	break;
931	978
932	979	case 0x2c/4:      // VI_V_BURST_REG
933		return vi_vburst;
	980	ret = vi_vburst;
	981	break;
934	982
935	983	case 0x30/4:      // VI_X_SCALE_REG
936		return vi_xscale;
	984	ret = vi_xscale;
	985	break;
937	986
938	987	case 0x34/4:      // VI_Y_SCALE_REG
939		return vi_yscale;
	988	ret = vi_yscale;
	989	break;
940	990
941	991	default:
942	992	logerror("vi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(maincpu));
943	993	break;
944	994	}
945		return 0;
	995
	996	//printf("vi_reg_r %08x = %08x\n", offset * 4, ret);
	997	return ret;
946	998	}
947	999
948	1000	WRITE32_MEMBER( n64_periphs::vi_reg_w )
r14486	r14487
1149	1201
1150	1202	READ32_MEMBER( n64_periphs::ai_reg_r )
1151	1203	{
1152		//printf("ai_reg_r %08x\n", offset * 4);
	1204	UINT32 ret = 0;
1153	1205	switch (offset)
1154	1206	{
1155	1207	case 0x04/4:        // AI_LEN_REG
1156	1208	{
1157	1209	if (ai_status & 0x80000001)
1158	1210	{
1159		return ai_len;
	1211	ret = ai_len;
1160	1212	}
1161	1213	else if (ai_status & 0x40000000)
1162	1214	{
1163	1215	double secs_left = (ai_timer->expire() - machine().time()).as_double();
1164	1216	unsigned int samples_left = secs_left * DACRATE_NTSC / (ai_dacrate + 1);
1165		return samples_left * 4;
	1217	ret = samples_left * 4;
1166	1218	}
1167		else return 0;
	1219	else
	1220	{
	1221	ret = 0;
	1222	}
	1223	break;
1168	1224	}
1169	1225
1170	1226	case 0x0c/4:        // AI_STATUS_REG
1171		return ai_status;
	1227	ret = ai_status;
	1228	break;
1172	1229
1173	1230	default:
1174	1231	logerror("ai_reg_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(maincpu));
1175	1232	break;
1176	1233	}
1177	1234
1178		return 0;
	1235	//printf("ai_reg_r %08x = %08x\n", offset * 4, ret);
	1236	return ret;
1179	1237	}
1180	1238
1181	1239	WRITE32_MEMBER( n64_periphs::ai_reg_w )
r14486	r14487
1230	1288	UINT16 *cart16 = (UINT16*)machine().region("user2")->base();
1231	1289	UINT16 *dram16 = (UINT16*)rdram;
1232	1290
1233		//printf("%08x Cart, %08x Dram\n", pi_cart_addr, pi_dram_addr);
1234
1235	1291	UINT32 cart_addr = (pi_cart_addr & 0x0fffffff) >> 1;
1236	1292	UINT32 dram_addr = (pi_dram_addr & 0x007fffff) >> 1;
1237	1293
1238		if(cart_addr & 0x04000000)
	1294	if((cart_addr & 0x04000000) == 0x04000000)
1239	1295	{
1240	1296	cart16 = (UINT16*)n64_sram;
1241	1297	cart_addr = (pi_cart_addr & 0x0001ffff) >> 1;
1242	1298	}
	1299	else if((cart_addr & 0x03000000) == 0x03000000 && dd_present)
	1300	{
	1301	cart16 = (UINT16*)machine().region("ddipl")->base();
	1302	cart_addr = (pi_cart_addr & 0x003fffff) >> 1;
	1303	}
	1304	else
	1305	{
	1306	cart_addr &= ((machine().region("user2")->bytes() >> 1) - 1);
	1307	}
1243	1308
1244		cart_addr &= ((machine().region("user2")->bytes() >> 1) - 1);
	1309	//printf("%08x Cart, %08x Dram\n", cart_addr << 1, dram_addr << 1);
1245	1310
1246	1311	if(pi_dma_dir == 1)
1247	1312	{
r14486	r14487
1300	1365
1301	1366	READ32_MEMBER( n64_periphs::pi_reg_r )
1302	1367	{
1303		//printf("pi_reg_r %08x\n", offset * 4);
	1368	UINT32 ret = 0;
1304	1369	switch (offset)
1305	1370	{
1306	1371	case 0x00/4:      // PI_DRAM_ADDR_REG
1307		return pi_dram_addr;
	1372	ret = pi_dram_addr;
	1373	break;
1308	1374
1309	1375	case 0x04/4:      // PI_CART_ADDR_REG
1310		return pi_cart_addr;
	1376	ret = pi_cart_addr;
	1377	break;
1311	1378
1312	1379	case 0x10/4:      // PI_STATUS_REG
1313		return pi_status;
	1380	ret = pi_status;
	1381	break;
1314	1382
1315	1383	case 0x14/4:        // PI_BSD_DOM1_LAT
1316		return pi_bsd_dom1_lat;
	1384	ret = pi_bsd_dom1_lat;
	1385	break;
1317	1386
1318	1387	case 0x18/4:        // PI_BSD_DOM1_PWD
1319		return pi_bsd_dom1_pwd;
	1388	ret = pi_bsd_dom1_pwd;
	1389	break;
1320	1390
1321	1391	case 0x1c/4:        // PI_BSD_DOM1_PGS
1322		return pi_bsd_dom1_pgs;
	1392	ret = pi_bsd_dom1_pgs;
	1393	break;
1323	1394
1324	1395	case 0x20/4:        // PI_BSD_DOM1_RLS
1325		return pi_bsd_dom1_rls;
	1396	ret = pi_bsd_dom1_rls;
	1397	break;
1326	1398
1327	1399	case 0x24/4:        // PI_BSD_DOM2_LAT
1328		return pi_bsd_dom2_lat;
	1400	ret = pi_bsd_dom2_lat;
	1401	break;
1329	1402
1330	1403	case 0x28/4:        // PI_BSD_DOM2_PWD
1331		return pi_bsd_dom2_pwd;
	1404	ret = pi_bsd_dom2_pwd;
	1405	break;
1332	1406
1333	1407	case 0x2c/4:        // PI_BSD_DOM2_PGS
1334		return pi_bsd_dom2_pgs;
	1408	ret = pi_bsd_dom2_pgs;
	1409	break;
1335	1410
1336	1411	case 0x30/4:        // PI_BSD_DOM2_RLS
1337		return pi_bsd_dom2_rls;
	1412	ret = pi_bsd_dom2_rls;
	1413	break;
1338	1414
1339	1415	default:
1340	1416	logerror("pi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(maincpu));
1341	1417	break;
1342	1418	}
1343		return 0;
	1419
	1420	//printf("pi_reg_r %08x = %08x\n", offset * 4, ret);
	1421	return ret;
1344	1422	}
1345	1423
1346	1424	WRITE32_MEMBER( n64_periphs::pi_reg_w )
r14486	r14487
1438	1516
1439	1517	READ32_MEMBER( n64_periphs::ri_reg_r )
1440	1518	{
1441		//printf("ri_reg_r %08x\n", offset * 4);
	1519	//printf("ri_reg_r %08x = %08x\n", offset * 4, ri_regs[offset]);
1442	1520	if(offset > 0x1c/4)
1443	1521	{
1444	1522	logerror("ri_reg_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(maincpu));
r14486	r14487
1891	1969
1892	1970	READ32_MEMBER( n64_periphs::si_reg_r )
1893	1971	{
1894		//printf("si_reg_r %08x\n", offset * 4);
	1972	UINT32 ret = 0;
1895	1973	switch (offset)
1896	1974	{
1897	1975	//case 0x00/4:      // SI_DRAM_ADDR_REG
1898	1976	//return si_dram_addr;
1899	1977
1900	1978	case 0x18/4:      // SI_STATUS_REG
1901		return si_status;
	1979	ret = si_status;
1902	1980	}
1903		return 0;
	1981
	1982	//printf("si_reg_r %08x = %08x\n", offset * 4, ret);
	1983	return ret;
1904	1984	}
1905	1985
1906	1986	WRITE32_MEMBER( n64_periphs::si_reg_w )
r14486	r14487
1937	2017	}
1938	2018	}
1939	2019
	2020	READ32_MEMBER( n64_periphs::dd_reg_r )
	2021	{
	2022	logerror("dd_reg_r: %08X\n", offset << 2);
	2023	return 0;
	2024	}
	2025
	2026	WRITE32_MEMBER( n64_periphs::dd_reg_w )
	2027	{
	2028	logerror("dd_reg_w: %08X, %08X, %08X\n", data, offset << 2, mem_mask);
	2029	}
	2030
1940	2031	READ32_MEMBER( n64_periphs::pif_ram_r )
1941	2032	{
1942	2033	if(!space.debugger_access())
r14486	r14487
1980	2071	n64_periphs *periphs = machine.device<n64_periphs>("rcp");
1981	2072
1982	2073	device_image_interface *image = dynamic_cast<device_image_interface *>(periphs->m_nvram_image);
1983		//printf("Saving\n");
	2074	//printf("Saving stuff\n");
1984	2075	UINT8 data[0x30800];
1985	2076	memcpy(data, n64_sram, 0x20000);
1986	2077	memcpy(data + 0x20000, periphs->m_save_data.eeprom, 0x800);

src/mame/includes/n64.h

r14486	r14487
65	65	DECLARE_WRITE32_MEMBER( ri_reg_w );
66	66	DECLARE_READ32_MEMBER( si_reg_r );
67	67	DECLARE_WRITE32_MEMBER( si_reg_w );
	68	DECLARE_READ32_MEMBER( dd_reg_r );
	69	DECLARE_WRITE32_MEMBER( dd_reg_w );
68	70	DECLARE_READ32_MEMBER( pif_ram_r );
69	71	DECLARE_WRITE32_MEMBER( pif_ram_w );
70	72
r14486	r14487
73	75
74	76	void sp_set_status(UINT32 status);
75	77	void signal_rcp_interrupt(int interrupt);
	78	void check_interrupts();
76	79
77	80	void ai_timer_tick();
78	81	void pi_dma_tick();
r14486	r14487
99	102
100	103	n64_savable_data_t m_save_data;
101	104
	105	UINT32 cart_length;
	106
	107	bool dd_present;
	108
102	109	protected:
103	110	// device-level overrides
104	111	virtual void device_start();

src/mame/video/n64.c

r14486	r14487
31	31
32	32	static FILE *rdp_exec;
33	33
	34	bool n64_rdp::rdp_range_check(UINT32 addr)
	35	{
	36	if(MiscState.FBSize == 0) return false;
	37
	38	int fbcount = ((MiscState.FBWidth * Scissor.m_yl) << (MiscState.FBSize - 1)) * 3;
	39	int zbcount = MiscState.FBWidth * Scissor.m_yl * 2;
	40	int fbaddr = MiscState.FBAddress & 0x007fffff;
	41	int zbaddr = MiscState.ZBAddress & 0x007fffff;
	42	if ((addr >= fbaddr) && (addr < (fbaddr + fbcount)))
	43	{
	44	return false;
	45	}
	46	if ((addr >= zbaddr) && (addr < (zbaddr + zbcount)))
	47	{
	48	return false;
	49	}
	50
	51	printf("Check failed: %08x vs. %08x-%08x, %08x-%08x (%d, %d)\n", addr, fbaddr, fbaddr + fbcount, zbaddr, zbaddr + zbcount, MiscState.FBWidth, Scissor.m_yl);
	52	fflush(stdout);
	53	return true;
	54	}
	55
34	56	/*****************************************************************************/
35	57
36	58	// The functions in this file should be moved into the parent Processor class.
r14486	r14487
113	135	hres = 640;
114	136	}
115	137
116		UINT32 pixels = 0;
	138	if (vres > bitmap.height()) // makes Perfect Dark boot w/o crashing
	139	{
	140	vres = bitmap.height();
	141	}
117	142
	143	UINT32 pixels = 0;
	144
118	145	if (frame_buffer)
119	146	{
120	147	for(int j = 0; j < vres; j++)
r14486	r14487
909	936	UINT32 n64_rdp::ZDecompress(UINT32 zcurpixel)
910	937	{
911	938	UINT32 zb = RREADIDX16(zcurpixel);
	939	CHECK16(zcurpixel);
912	940	return z_complete_dec_table[(zb >> 2) & 0x3fff];
913	941	}
914	942
915	943	UINT32 n64_rdp::DZDecompress(UINT32 zcurpixel, UINT32 dzcurpixel)
916	944	{
917	945	UINT16 zval = RREADIDX16(zcurpixel);
	946	CHECK16(zcurpixel);
918	947	UINT8 dzval = (((dzcurpixel) <= 0x7fffff) ? (HiddenBits[(dzcurpixel) ^ BYTE_ADDR_XOR]) : 0);
919	948	UINT32 dz_compressed = ((zval & 3) << 2) | (dzval & 3);
920	949	return (1 << dz_compressed);
r14486	r14487
1018	1047	oz = ZDecompress(zcurpixel);
1019	1048	dzmem = DZDecompress(zcurpixel, dzcurpixel);
1020	1049	zval = RREADIDX16(zcurpixel);
	1050	CHECK16(zcurpixel);
1021	1051	rawdzmem = ((zval & 3) << 2) | ((((dzcurpixel) <= 0x3fffff) ? (HiddenBits[(dzcurpixel) ^ BYTE_ADDR_XOR]) : 0) & 3);
1022	1052	}
1023	1053	else
r14486	r14487
2121	2151
2122	2152	if (spix == 0)
2123	2153	{
2124		Spans[j - (ycur >> 2)].userdata = (void*)((UINT8*)AuxBuf[AuxBufIndex] + AuxBufPtr[AuxBufIndex]);
2125		AuxBufPtr[AuxBufIndex] += sizeof(rdp_span_aux);
	2154	Spans[j - (ycur >> 2)].userdata = (void*)((UINT8*)AuxBuf + AuxBufPtr);
	2155	AuxBufPtr += sizeof(rdp_span_aux);
	2156
	2157	if(AuxBufPtr >= EXTENT_AUX_COUNT)
	2158	{
	2159	fatalerror("n64_rdp::DrawTriangle: span aux buffer overflow\n");
	2160	}
	2161
2126	2162	rdp_span_aux *userdata = (rdp_span_aux*)Spans[j - (ycur >> 2)].userdata;
2127	2163	userdata->m_tmem = object.m_tmem;
2128	2164
r14486	r14487
2273	2309
2274	2310	if (spix == 0)
2275	2311	{
2276		Spans[j - (ycur >> 2)].userdata = (void*)((UINT8*)AuxBuf[AuxBufIndex] + AuxBufPtr[AuxBufIndex]);
2277		AuxBufPtr[AuxBufIndex] += sizeof(rdp_span_aux);
	2312	Spans[j - (ycur >> 2)].userdata = (void*)((UINT8*)AuxBuf + AuxBufPtr);
	2313	AuxBufPtr += sizeof(rdp_span_aux);
2278	2314
	2315	if(AuxBufPtr >= EXTENT_AUX_COUNT)
	2316	{
	2317	fatalerror("n64_rdp::DrawTriangle: span aux buffer overflow\n");
	2318	}
	2319
2279	2320	rdp_span_aux *userdata = (rdp_span_aux*)Spans[j - (ycur >> 2)].userdata;
2280	2321	userdata->m_tmem = object.m_tmem;
2281	2322
r14486	r14487
2409	2450	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2410	2451	{
2411	2452	finalcolor = RREADIDX16(fb) & 0xfffe;
	2453	CHECK16(fb);
2412	2454	}
2413	2455
2414	2456	finalcvg = userdata->CurrentPixCvg + userdata->CurrentMemCvg;
r14486	r14487
2431	2473	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2432	2474	{
2433	2475	finalcolor = RREADIDX16(fb) & 0xfffe;
	2476	CHECK16(fb);
2434	2477	}
2435	2478
2436	2479	finalcvg = (userdata->CurrentPixCvg - 1) & 7;
r14486	r14487
2449	2492	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2450	2493	{
2451	2494	finalcolor = RREADIDX16(fb) & 0xfffe;
	2495	CHECK16(fb);
2452	2496	}
2453	2497
2454	2498	finalcvg = (userdata->CurrentPixCvg + userdata->CurrentMemCvg) & 7;
r14486	r14487
2466	2510	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2467	2511	{
2468	2512	finalcolor = RREADIDX16(fb) & 0xfffe;
	2513	CHECK16(fb);
2469	2514	}
2470	2515
2471	2516	RWRITEIDX16(fb, finalcolor | 1);
r14486	r14487
2482	2527	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2483	2528	{
2484	2529	finalcolor = RREADIDX16(fb) & 0xfffe;
	2530	CHECK16(fb);
2485	2531	}
2486	2532
2487	2533	RWRITEIDX16(fb, finalcolor | ((userdata->CurrentMemCvg >> 2) & 1));
r14486	r14487
2497	2543	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2498	2544	{
2499	2545	finalcolor = RREADIDX32(fb) & 0xffffff00;
	2546	CHECK32(fb);
2500	2547	}
2501	2548
2502	2549	finalcvg = userdata->CurrentPixCvg + userdata->CurrentMemCvg;
r14486	r14487
2516	2563	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2517	2564	{
2518	2565	finalcolor = RREADIDX32(fb) & 0xffffff00;
	2566	CHECK32(fb);
2519	2567	}
2520	2568
2521	2569	finalcvg = (userdata->CurrentPixCvg - 1) & 7;
r14486	r14487
2531	2579	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2532	2580	{
2533	2581	finalcolor = RREADIDX32(fb) & 0xffffff00;
	2582	CHECK32(fb);
2534	2583	}
2535	2584
2536	2585	finalcvg = (userdata->CurrentPixCvg + userdata->CurrentMemCvg) & 7;
r14486	r14487
2546	2595	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2547	2596	{
2548	2597	finalcolor = RREADIDX32(fb) & 0xffffff00;
	2598	CHECK32(fb);
2549	2599	}
2550	2600
2551	2601	RWRITEIDX32(fb, finalcolor | 0xE0);
r14486	r14487
2559	2609	if (object.OtherModes.color_on_cvg && !userdata->PreWrap)
2560	2610	{
2561	2611	finalcolor = RREADIDX32(fb) & 0xffffff00;
	2612	CHECK32(fb);
2562	2613	}
2563	2614
2564	2615	RWRITEIDX32(fb, finalcolor | (userdata->CurrentMemCvg << 5));
r14486	r14487
2568	2619	void n64_rdp::_Read16Bit_ImgRead0(UINT32 curpixel, rdp_span_aux *userdata, const rdp_poly_state &object)
2569	2620	{
2570	2621	UINT16 fword = RREADIDX16((object.MiscState.FBAddress >> 1) + curpixel);
	2622	CHECK16((object.MiscState.FBAddress >> 1) + curpixel);
2571	2623	userdata->MemoryColor.i.r = GETHICOL(fword);
2572	2624	userdata->MemoryColor.i.g = GETMEDCOL(fword);
2573	2625	userdata->MemoryColor.i.b = GETLOWCOL(fword);
r14486	r14487
2578	2630	void n64_rdp::_Read16Bit_ImgRead1(UINT32 curpixel, rdp_span_aux *userdata, const rdp_poly_state &object)
2579	2631	{
2580	2632	UINT16 fword = RREADIDX16((object.MiscState.FBAddress >> 1) + curpixel);
	2633	CHECK16((object.MiscState.FBAddress >> 1) + curpixel);
2581	2634	UINT8 hbyte = HREADADDR8((object.MiscState.FBAddress >> 1) + curpixel);
2582	2635	userdata->MemoryColor.i.r = GETHICOL(fword);
2583	2636	userdata->MemoryColor.i.g = GETMEDCOL(fword);
r14486	r14487
2589	2642	void n64_rdp::_Read32Bit_ImgRead0(UINT32 curpixel, rdp_span_aux *userdata, const rdp_poly_state &object)
2590	2643	{
2591	2644	UINT32 mem = RREADIDX32((object.MiscState.FBAddress >> 2) + curpixel);
	2645	CHECK32((object.MiscState.FBAddress >> 2) + curpixel);
2592	2646	userdata->MemoryColor.i.r = (mem >> 24) & 0xff;
2593	2647	userdata->MemoryColor.i.g = (mem >> 16) & 0xff;
2594	2648	userdata->MemoryColor.i.b = (mem >> 8) & 0xff;
r14486	r14487
2599	2653	void n64_rdp::_Read32Bit_ImgRead1(UINT32 curpixel, rdp_span_aux *userdata, const rdp_poly_state &object)
2600	2654	{
2601	2655	UINT32 mem = RREADIDX32((object.MiscState.FBAddress >> 2) + curpixel);
	2656	CHECK32((object.MiscState.FBAddress >> 2) + curpixel);
2602	2657	userdata->MemoryColor.i.r = (mem >> 24) & 0xff;
2603	2658	userdata->MemoryColor.i.g = (mem >> 16) & 0xff;
2604	2659	userdata->MemoryColor.i.b = (mem >> 8) & 0xff;
r14486	r14487
2611	2666	UINT16 val = ((r >> 3) << 11) | ((g >> 3) << 6) | ((b >> 3) << 1) | ((CurrentPixCvg >> 2) & 1);
2612	2667	RWRITEIDX16((object.MiscState.FBAddress >> 1) + curpixel, val);
2613	2668	HWRITEADDR8((object.MiscState.FBAddress >> 1) + curpixel, CurrentPixCvg & 3);
	2669	CHECK16((object.MiscState.FBAddress >> 1) + curpixel);
2614	2670	}
2615	2671
2616	2672	void n64_rdp::_Copy32Bit(UINT32 curpixel, UINT32 r, UINT32 g, UINT32 b, int CurrentPixCvg, const rdp_poly_state &object)
2617	2673	{
2618	2674	UINT32 val = (r << 24) | (g << 16) | (b << 8) | (CurrentPixCvg << 5);
2619	2675	RWRITEIDX32((object.MiscState.FBAddress >> 2) + curpixel, val);
	2676	CHECK32((object.MiscState.FBAddress >> 2) + curpixel);
2620	2677	}
2621	2678
2622	2679
r14486	r14487
2632	2689	val = (object.FillColor >> 16) & 0xffff;
2633	2690	}
2634	2691	RWRITEIDX16((object.MiscState.FBAddress >> 1) + curpixel, val);
	2692	CHECK16((object.MiscState.FBAddress >> 1) + curpixel);
2635	2693	HWRITEADDR8((object.MiscState.FBAddress >> 1) + curpixel, ((val & 1) << 1) | (val & 1));
2636	2694	}
2637	2695
r14486	r14487
2639	2697	{
2640	2698	UINT32 FillColor = object.FillColor;
2641	2699	RWRITEIDX32((object.MiscState.FBAddress >> 2) + curpixel, FillColor);
	2700	CHECK32((object.MiscState.FBAddress >> 2) + curpixel);
2642	2701	HWRITEADDR8((object.MiscState.FBAddress >> 1) + (curpixel << 1), (FillColor & 0x10000) ? 3 : 0);
2643	2702	HWRITEADDR8((object.MiscState.FBAddress >> 1) + (curpixel << 1) + 1, (FillColor & 0x1) ? 3 : 0);
2644	2703	}
r14486	r14487
2650	2709	{
2651	2710	DrawTriangle(shade, texture, zbuffer, false);
2652	2711	m_pipe_clean = false;
	2712	//wait();
2653	2713	}
2654	2714
2655	2715	void n64_rdp::CmdTriangle(UINT32 w1, UINT32 w2)
r14486	r14487
2831	2891
2832	2892	void n64_rdp::CmdSyncFull(UINT32 w1, UINT32 w2)
2833	2893	{
2834		//wait("SyncFull");
	2894	wait("SyncFull");
2835	2895	dp_full_sync(*m_machine);
2836	2896	}
2837	2897
r14486	r14487
2962	3022	{
2963	3023	if (dststart < 2048)
2964	3024	{
2965		dst[dststart] = RREADIDX16(srcstart);
	3025	dst[dststart] = U_RREADIDX16(srcstart);
2966	3026	dst[dststart + 1] = dst[dststart];
2967	3027	dst[dststart + 2] = dst[dststart];
2968	3028	dst[dststart + 3] = dst[dststart];
r14486	r14487
3048	3108	ptr = tb + (i << 2);
3049	3109	srcptr = src + (i << 2);
3050	3110
3051		tc[(ptr ^ t) & 0x7ff] = RREADIDX16(srcptr);
3052		tc[((ptr + 1) ^ t) & 0x7ff] = RREADIDX16(srcptr + 1);
3053		tc[((ptr + 2) ^ t) & 0x7ff] = RREADIDX16(srcptr + 2);
3054		tc[((ptr + 3) ^ t) & 0x7ff] = RREADIDX16(srcptr + 3);
	3111	tc[(ptr ^ t) & 0x7ff] = U_RREADIDX16(srcptr);
	3112	tc[((ptr + 1) ^ t) & 0x7ff] = U_RREADIDX16(srcptr + 1);
	3113	tc[((ptr + 2) ^ t) & 0x7ff] = U_RREADIDX16(srcptr + 2);
	3114	tc[((ptr + 3) ^ t) & 0x7ff] = U_RREADIDX16(srcptr + 3);
3055	3115	j += dxt;
3056	3116	}
3057	3117	}
r14486	r14487
3069	3129	ptr = ((tb + (i << 1)) ^ t) & 0x3ff;
3070	3130	srcptr = src + (i << 2);
3071	3131
3072		first = RREADIDX16(srcptr);
3073		sec = RREADIDX16(srcptr + 1);
	3132	first = U_RREADIDX16(srcptr);
	3133	sec = U_RREADIDX16(srcptr + 1);
3074	3134	tc[ptr] = ((first >> 8) << 8) | (sec >> 8);
3075	3135	tc[ptr | 0x400] = ((first & 0xff) << 8) | (sec & 0xff);
3076	3136
3077	3137	ptr = ((tb + (i << 1) + 1) ^ t) & 0x3ff;
3078		first = RREADIDX16(srcptr + 2);
3079		sec = RREADIDX16(srcptr + 3);
	3138	first = U_RREADIDX16(srcptr + 2);
	3139	sec = U_RREADIDX16(srcptr + 3);
3080	3140	tc[ptr] = ((first >> 8) << 8) | (sec >> 8);
3081	3141	tc[ptr | 0x400] = ((first & 0xff) << 8) | (sec & 0xff);
3082	3142
r14486	r14487
3094	3154
3095	3155	ptr = ((tb + (i << 1)) ^ t) & 0x3ff;
3096	3156	srcptr = src + (i << 2);
3097		tc[ptr] = RREADIDX16(srcptr);
3098		tc[ptr | 0x400] = RREADIDX16(srcptr + 1);
	3157	tc[ptr] = U_RREADIDX16(srcptr);
	3158	tc[ptr | 0x400] = U_RREADIDX16(srcptr + 1);
3099	3159
3100	3160	ptr = ((tb + (i << 1) + 1) ^ t) & 0x3ff;
3101		tc[ptr] = RREADIDX16(srcptr + 2);
3102		tc[ptr | 0x400] = RREADIDX16(srcptr + 3);
	3161	tc[ptr] = U_RREADIDX16(srcptr + 2);
	3162	tc[ptr | 0x400] = U_RREADIDX16(srcptr + 3);
3103	3163
3104	3164	j += dxt;
3105	3165	}
r14486	r14487
3114	3174	{
3115	3175	ptr = tb + (i << 2);
3116	3176	srcptr = src + (i << 2);
3117		tc[(ptr ^ WORD_ADDR_XOR) & 0x7ff] = RREADIDX16(srcptr);
3118		tc[((ptr + 1) ^ WORD_ADDR_XOR) & 0x7ff] = RREADIDX16(srcptr + 1);
3119		tc[((ptr + 2) ^ WORD_ADDR_XOR) & 0x7ff] = RREADIDX16(srcptr + 2);
3120		tc[((ptr + 3) ^ WORD_ADDR_XOR) & 0x7ff] = RREADIDX16(srcptr + 3);
	3177	tc[(ptr ^ WORD_ADDR_XOR) & 0x7ff] = U_RREADIDX16(srcptr);
	3178	tc[((ptr + 1) ^ WORD_ADDR_XOR) & 0x7ff] = U_RREADIDX16(srcptr + 1);
	3179	tc[((ptr + 2) ^ WORD_ADDR_XOR) & 0x7ff] = U_RREADIDX16(srcptr + 2);
	3180	tc[((ptr + 3) ^ WORD_ADDR_XOR) & 0x7ff] = U_RREADIDX16(srcptr + 3);
3121	3181	}
3122	3182	}
3123	3183	else if (tile[tilenum].format == FORMAT_YUV)
r14486	r14487
3126	3186	{
3127	3187	ptr = ((tb + (i << 1)) ^ WORD_ADDR_XOR) & 0x3ff;
3128	3188	srcptr = src + (i << 2);
3129		first = RREADIDX16(srcptr);
3130		sec = RREADIDX16(srcptr + 1);
	3189	first = U_RREADIDX16(srcptr);
	3190	sec = U_RREADIDX16(srcptr + 1);
3131	3191	tc[ptr] = ((first >> 8) << 8) | (sec >> 8);//UV pair
3132	3192	tc[ptr | 0x400] = ((first & 0xff) << 8) | (sec & 0xff);
3133	3193
3134	3194	ptr = ((tb + (i << 1) + 1) ^ WORD_ADDR_XOR) & 0x3ff;
3135		first = RREADIDX16(srcptr + 2);
3136		sec = RREADIDX16(srcptr + 3);
	3195	first = U_RREADIDX16(srcptr + 2);
	3196	sec = U_RREADIDX16(srcptr + 3);
3137	3197	tc[ptr] = ((first >> 8) << 8) | (sec >> 8);
3138	3198	tc[ptr | 0x400] = ((first & 0xff) << 8) | (sec & 0xff);
3139	3199	}
r14486	r14487
3144	3204	{
3145	3205	ptr = ((tb + (i << 1)) ^ WORD_ADDR_XOR) & 0x3ff;
3146	3206	srcptr = src + (i << 2);
3147		tc[ptr] = RREADIDX16(srcptr);
3148		tc[ptr | 0x400] = RREADIDX16(srcptr + 1);
	3207	tc[ptr] = U_RREADIDX16(srcptr);
	3208	tc[ptr | 0x400] = U_RREADIDX16(srcptr + 1);
3149	3209
3150	3210	ptr = ((tb + (i << 1) + 1) ^ WORD_ADDR_XOR) & 0x3ff;
3151		tc[ptr] = RREADIDX16(srcptr + 2);
3152		tc[ptr | 0x400] = RREADIDX16(srcptr + 3);
	3211	tc[ptr] = U_RREADIDX16(srcptr + 2);
	3212	tc[ptr | 0x400] = U_RREADIDX16(srcptr + 3);
3153	3213	}
3154	3214	}
3155	3215	tile[tilenum].th = tl;
r14486	r14487
3202	3262	int xorval8 = ((j & 1) ? BYTE_XOR_DWORD_SWAP : BYTE_ADDR_XOR);
3203	3263	for (int i = 0; i < width; i++)
3204	3264	{
3205		tc[((tline + i) ^ xorval8) & 0xfff] = RREADADDR8(src + s + i);
	3265	tc[((tline + i) ^ xorval8) & 0xfff] = U_RREADADDR8(src + s + i);
3206	3266	}
3207	3267	}
3208	3268	break;
r14486	r14487
3225	3285	for (int i = 0; i < width; i++)
3226	3286	{
3227	3287	UINT32 taddr = (tline + i) ^ xorval16;
3228		tc[taddr & 0x7ff] = RREADIDX16(src + s + i);
	3288	tc[taddr & 0x7ff] = U_RREADIDX16(src + s + i);
3229	3289	}
3230	3290	}
3231	3291	}
r14486	r14487
3241	3301	for (int i = 0; i < width; i++)
3242	3302	{
3243	3303	UINT32 taddr = ((tline + i) ^ xorval8) & 0x7ff;
3244		yuvword = RREADIDX16(src + s + i);
	3304	yuvword = U_RREADIDX16(src + s + i);
3245	3305	GetTMEM()[taddr] = yuvword >> 8;
3246	3306	GetTMEM()[taddr | 0x800] = yuvword & 0xff;
3247	3307	}
r14486	r14487
3263	3323	int xorval32cur = (j & 1) ? WORD_XOR_DWORD_SWAP : WORD_ADDR_XOR;
3264	3324	for (int i = 0; i < width; i++)
3265	3325	{
3266		UINT32 c = RREADIDX32(src + s + i);
	3326	UINT32 c = U_RREADIDX32(src + s + i);
3267	3327	UINT32 ptr = ((tline + i) ^ xorval32cur) & 0x3ff;
3268	3328	tc16[ptr] = c >> 16;
3269	3329	tc16[ptr | 0x400] = c & 0xffff;
r14486	r14487
3398	3458
3399	3459	void n64_rdp::CmdSetMaskImage(UINT32 w1, UINT32 w2)
3400	3460	{
	3461	wait("SetMaskImage");
	3462
3401	3463	MiscState.ZBAddress = w2 & 0x01ffffff;
3402	3464	}
3403	3465
3404	3466	void n64_rdp::CmdSetColorImage(UINT32 w1, UINT32 w2)
3405	3467	{
	3468	wait("SetColorImage");
	3469
3406	3470	MiscState.FBFormat   = (w1 >> 21) & 0x7;
3407	3471	MiscState.FBSize   = (w1 >> 19) & 0x3;
3408	3472	MiscState.FBWidth      = (w1 & 0x3ff) + 1;
3409	3473	MiscState.FBAddress   = w2 & 0x01ffffff;
3410	3474
3411		if (MiscState.FBFormat && MiscState.FBFormat != 2) // Jet Force Gemini sets the format to 4, Intensity.  Protection?
	3475	if (MiscState.FBFormat < 2 || MiscState.FBFormat > 32) // Jet Force Gemini sets the format to 4, Intensity.  Protection?
3412	3476	{
3413		if (MiscState.FBSize == 1)
3414		{
3415		MiscState.FBFormat = 2;
3416		}
3417		else
3418		{
3419		MiscState.FBFormat = 0;
3420		}
	3477	MiscState.FBFormat = 2;
3421	3478	}
3422
3423		if (MiscState.FBFormat != 0)
3424		{
3425		MiscState.FBFormat = 0;
3426		}
3427	3479	}
3428	3480
3429	3481	UINT32 n64_rdp::AddRightCvg(UINT32 x, UINT32 k)
r14486	r14487
3634	3686
3635	3687	n64_rdp::n64_rdp(n64_state &state) : poly_manager<UINT32, rdp_poly_state, 8, 32000>(state.machine())
3636	3688	{
3637		AuxBufIndex = 0;
3638		AuxBufPtr[0] = AuxBufPtr[1] = 0;
3639		AuxBuf[0] = AuxBuf[1] = NULL;
	3689	AuxBufPtr = 0;
	3690	AuxBuf = NULL;
3640	3691	m_pipe_clean = true;
3641	3692
3642	3693	m_pending_mode_block = false;
r14486	r14487
3753	3804
3754	3805	state->m_rdp->TexPipe.SetMachine(machine);
3755	3806
3756		state->m_rdp->AuxBuf[0] = auto_alloc_array_clear(machine, UINT8, EXTENT_AUX_COUNT);
3757		state->m_rdp->AuxBuf[1] = auto_alloc_array_clear(machine, UINT8, EXTENT_AUX_COUNT);
	3807	state->m_rdp->AuxBuf = auto_alloc_array_clear(machine, UINT8, EXTENT_AUX_COUNT);
3758	3808
3759	3809	if (LOG_RDP_EXECUTION)
3760	3810	{
r14486	r14487
3768	3818	n64_periphs *n64 = screen.machine().device<n64_periphs>("rcp");
3769	3819	state->m_rdp->visarea = screen.visible_area();
3770	3820
3771		int height = state->m_rdp->MiscState.FBHeight;
3772	3821	//UINT16 *frame_buffer = (UINT16*)&rdram[(n64->vi_origin & 0xffffff) >> 2];
3773	3822	//UINT8  *cvg_buffer = &state->m_rdp.HiddenBits[((n64->vi_origin & 0xffffff) >> 2) >> 1];
3774	3823	//int vibuffering = ((n64->vi_control & 2) && fsaa && divot);
r14486	r14487
3808	3857	*/
3809	3858
3810	3859	state->m_rdp->wait();
3811		state->m_rdp->AuxBufPtr[state->m_rdp->AuxBufIndex] = 0;
3812		state->m_rdp->AuxBufIndex ^= 1;
	3860	state->m_rdp->AuxBufPtr = 0;
3813	3861
3814	3862	if (n64->vi_blank)
3815	3863	{
3816		for (int j = 0; j <height; j++)
	3864	for (int j = 0; j < state->m_rdp->visarea.max_y; j++)
3817	3865	{
3818	3866	UINT32 *d = &bitmap.pix32(j);
3819	3867	for (int i = 0; i < state->m_rdp->MiscState.FBWidth; i++)

src/mame/video/n64.h

r14486	r14487
56	56	#define MEM16_LIMIT 0x3fffff
57	57	#define MEM32_LIMIT 0x1fffff
58	58
59		#define RREADADDR8(in) /*(((in) <= MEM8_LIMIT) ?  */(((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR]) /*: 0)*/
60		#define RREADIDX16(in) /*(((in) <= MEM16_LIMIT) ? */(((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR]) /*: 0)*/
61		#define RREADIDX32(in) /*(((in) <= MEM32_LIMIT) ? */(rdram[(in)]) /*: 0)*/
	59	#define RDP_RANGE_CHECK   (0)
62	60
63		#define RWRITEADDR8(in, val)   {/*if ((in) <= MEM8_LIMIT) */((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR] = val;}
64		#define RWRITEIDX16(in, val)   {/*if ((in) <= MEM16_LIMIT)*/ ((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR] = val;}
65		#define RWRITEIDX32(in, val)   {/*if ((in) <= MEM32_LIMIT)*/ rdram[(in)] = val;}
	61	#if RDP_RANGE_CHECK
	62	#define CHECK8(in) if(rdp_range_check((in))) { printf("Check8: Address %08x out of range!\n", (in)); fflush(stdout); fatalerror("Address %08x out of range!\n", (in)); }
	63	#define CHECK16(in) if(rdp_range_check((in) << 1)) { printf("Check16: Address %08x out of range!\n", (in) << 1); fflush(stdout); fatalerror("Address %08x out of range!\n", (in) << 1); }
	64	#define CHECK32(in) if(rdp_range_check((in) << 2)) { printf("Check32: Address %08x out of range!\n", (in) << 2); fflush(stdout); fatalerror("Address %08x out of range!\n", (in) << 2); }
	65	#else
	66	#define CHECK8(in) { }
	67	#define CHECK16(in) { }
	68	#define CHECK32(in) { }
	69	#endif
66	70
	71	#if RDP_RANGE_CHECK
	72	#define RREADADDR8(in) ((rdp_range_check((in))) ? 0 : (((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR]))
	73	#define RREADIDX16(in) ((rdp_range_check((in) << 1)) ? 0 : (((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR]))
	74	#define RREADIDX32(in) ((rdp_range_check((in) << 2)) ? 0 : rdram[(in)])
	75
	76	#define RWRITEADDR8(in, val)   if(rdp_range_check((in))) { printf("Write8: Address %08x out of range!\n", (in)); fflush(stdout); fatalerror("Address %08x out of range!\n", (in)); } else { ((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR] = val;}
	77	#define RWRITEIDX16(in, val)   if(rdp_range_check((in) << 1)) { printf("Write16: Address %08x out of range!\n", (in) << 1); fflush(stdout); fatalerror("Address %08x out of range!\n", (in) << 1); } else { ((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR] = val;}
	78	#define RWRITEIDX32(in, val)   if(rdp_range_check((in) << 2)) { printf("Write32: Address %08x out of range!\n", (in) << 2); fflush(stdout); fatalerror("Address %08x out of range!\n", (in) << 2); } else { rdram[(in)] = val;}
	79	#else
	80	#define RREADADDR8(in) (((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR])
	81	#define RREADIDX16(in) (((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR])
	82	#define RREADIDX32(in) (rdram[(in)])
	83
	84	#define RWRITEADDR8(in, val)   ((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR] = val;
	85	#define RWRITEIDX16(in, val)   ((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR] = val;
	86	#define RWRITEIDX32(in, val)   rdram[(in)] = val
	87	#endif
	88
	89	#define U_RREADADDR8(in) (((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR])
	90	#define U_RREADIDX16(in) (((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR])
	91	#define U_RREADIDX32(in) (rdram[(in)])
	92
	93	#define U_RWRITEADDR8(in, val)   ((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR] = val;
	94	#define U_RWRITEIDX16(in, val)   ((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR] = val;
	95	#define U_RWRITEIDX32(in, val)   rdram[(in)] = val
	96
67	97	#define GETLOWCOL(x)   (((x) & 0x3e) << 2)
68	98	#define GETMEDCOL(x)   (((x) & 0x7c0) >> 3)
69	99	#define GETHICOL(x)      (((x) & 0xf800) >> 8)
r14486	r14487
93	123
94	124	#define RDP_CVG_SPAN_MAX         (1024)
95	125
96		#define EXTENT_AUX_COUNT         (sizeof(rdp_span_aux)*(480*256)) // Screen coverage *128, more or less
	126	#define EXTENT_AUX_COUNT         (sizeof(rdp_span_aux)*(480*192)) // Screen coverage *192, more or less
97	127
98	128	/*****************************************************************************/
99	129
r14486	r14487
307	337	UINT8 *blender2b_a[2];
308	338	};
309	339
	340	// This is enormous and horrible
310	341	struct rdp_span_aux
311	342	{
312	343	UINT32            m_unscissored_rx;
r14486	r14487
568	599	void          compute_cvg_noflip(extent_t *Spans, INT32* majorx, INT32* minorx, INT32* majorxint, INT32* minorxint, INT32 scanline, INT32 yh, INT32 yl, INT32 base);
569	600	void          compute_cvg_flip(extent_t *Spans, INT32* majorx, INT32* minorx, INT32* majorxint, INT32* minorxint, INT32 scanline, INT32 yh, INT32 yl, INT32 base);
570	601
571		void*         AuxBuf[2];
572		UINT32         AuxBufPtr[2];
	602	void*         AuxBuf;
	603	UINT32         AuxBufPtr;
573	604	UINT32         AuxBufIndex;
574	605
575	606	void*         ExtentBuf[2];
576	607	UINT32         ExtentBufPtr[2];
577	608	UINT32         ExtentBufIndex;
578	609
	610	bool          rdp_range_check(UINT32 addr);
579	611	protected:
580	612	CombineModesT   m_combine;
581	613	bool         m_pending_mode_block;

src/mess/mess.lst

r14486	r14487
79	79	snesst    // Nintendo Super Nintendo NTSC w/Sufami Turbo base cart
80	80	snesbsx   // Nintendo Super Nintendo NTSC w/BS-X compatible cart
81	81	n64       // Nintendo N64
	82	n64dd     // Nintendo N64 (64DD Attachment)
82	83	pokemini  // Nintendo Pokemon Mini
83	84
84	85	megaduck  // Megaduck

src/mess/drivers/n64.c

r14486	r14487
28	28	AM_RANGE(0x04600000, 0x046fffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, pi_reg_r, pi_reg_w)   // Peripheral Interface
29	29	AM_RANGE(0x04700000, 0x047fffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, ri_reg_r, ri_reg_w)   // RDRAM Interface
30	30	AM_RANGE(0x04800000, 0x048fffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, si_reg_r, si_reg_w)   // Serial Interface
31		AM_RANGE(0x08000000, 0x0801ffff) AM_RAM AM_BASE(&n64_sram)      // Cartridge SRAM
32		AM_RANGE(0x10000000, 0x13ffffff) AM_ROM AM_REGION("user2", 0)   // Cartridge
33		AM_RANGE(0x1fc00000, 0x1fc007bf) AM_ROM AM_REGION("user1", 0)   // PIF ROM
	31	AM_RANGE(0x08000000, 0x0801ffff) AM_RAM AM_BASE(&n64_sram)                              // Cartridge SRAM
	32	AM_RANGE(0x10000000, 0x13ffffff) AM_ROM AM_REGION("user2", 0)                           // Cartridge
	33	AM_RANGE(0x1fc00000, 0x1fc007bf) AM_ROM AM_REGION("user1", 0)                           // PIF ROM
34	34	AM_RANGE(0x1fc007c0, 0x1fc007ff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, pif_ram_r, pif_ram_w)
35	35	ADDRESS_MAP_END
36	36
	37	static ADDRESS_MAP_START( n64dd_map, AS_PROGRAM, 32 )
	38	AM_RANGE(0x00000000, 0x007fffff) AM_RAM   AM_BASE(&rdram)            // RDRAM
	39	AM_RANGE(0x03f00000, 0x03f00027) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, rdram_reg_r, rdram_reg_w)
	40	AM_RANGE(0x04000000, 0x04000fff) AM_RAM AM_SHARE("dmem")               // RSP DMEM
	41	AM_RANGE(0x04001000, 0x04001fff) AM_RAM AM_SHARE("imem")               // RSP IMEM
	42	AM_RANGE(0x04040000, 0x040fffff) AM_DEVREADWRITE("rsp", n64_sp_reg_r, n64_sp_reg_w)   // RSP
	43	AM_RANGE(0x04100000, 0x041fffff) AM_DEVREADWRITE("rsp", n64_dp_reg_r, n64_dp_reg_w)   // RDP
	44	AM_RANGE(0x04300000, 0x043fffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, mi_reg_r, mi_reg_w)   // MIPS Interface
	45	AM_RANGE(0x04400000, 0x044fffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, vi_reg_r, vi_reg_w)   // Video Interface
	46	AM_RANGE(0x04500000, 0x045fffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, ai_reg_r, ai_reg_w)   // Audio Interface
	47	AM_RANGE(0x04600000, 0x046fffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, pi_reg_r, pi_reg_w)   // Peripheral Interface
	48	AM_RANGE(0x04700000, 0x047fffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, ri_reg_r, ri_reg_w)   // RDRAM Interface
	49	AM_RANGE(0x04800000, 0x048fffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, si_reg_r, si_reg_w)   // Serial Interface
	50	AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, dd_reg_r, dd_reg_w) // 64DD Interface
	51	AM_RANGE(0x06000000, 0x063fffff) AM_ROM AM_REGION("ddipl", 0)                           // 64DD IPL ROM
	52	AM_RANGE(0x08000000, 0x0801ffff) AM_RAM AM_BASE(&n64_sram)                              // Cartridge SRAM
	53	AM_RANGE(0x10000000, 0x13ffffff) AM_ROM AM_REGION("user2", 0)                           // Cartridge
	54	AM_RANGE(0x1fc00000, 0x1fc007bf) AM_ROM AM_REGION("user1", 0)                           // PIF ROM
	55	AM_RANGE(0x1fc007c0, 0x1fc007ff) AM_DEVREADWRITE_MODERN("rcp", n64_periphs, pif_ram_r, pif_ram_w)
	56	ADDRESS_MAP_END
	57
37	58	static ADDRESS_MAP_START( rsp_map, AS_PROGRAM, 32 )
38	59	AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("dmem")
39	60	AM_RANGE(0x00001000, 0x00001fff) AM_RAM AM_SHARE("imem")
r14486	r14487
144	165	length = image.get_software_region_length("rom");
145	166	memcpy(cart, image.get_software_region("rom"), length);
146	167	}
	168	periphs->cart_length = length;
147	169
148	170	if (cart[0] == 0x37 && cart[1] == 0x80)
149	171	{
r14486	r14487
198	220	return IMAGE_INIT_PASS;
199	221	}
200	222
	223	MACHINE_START( n64dd )
	224	{
	225	MACHINE_START_CALL( n64 );
	226
	227	UINT8 *ipl = machine.region("ddipl")->base();
	228
	229	for (int i = 0; i < 0x400000; i += 4)
	230	{
	231	UINT8 b1 = ipl[i + 0];
	232	UINT8 b2 = ipl[i + 1];
	233	UINT8 b3 = ipl[i + 2];
	234	UINT8 b4 = ipl[i + 3];
	235	ipl[i + 0] = b1;
	236	ipl[i + 1] = b2;
	237	ipl[i + 2] = b3;
	238	ipl[i + 3] = b4;
	239	}
	240	}
	241
201	242	static MACHINE_CONFIG_START( n64, n64_state )
202	243
203	244	/* basic machine hardware */
r14486	r14487
246	287	MCFG_SOFTWARE_LIST_ADD("cart_list","n64")
247	288	MACHINE_CONFIG_END
248	289
	290	static MACHINE_CONFIG_DERIVED( n64dd, n64 )
	291	MCFG_CPU_MODIFY("maincpu")
	292	MCFG_CPU_PROGRAM_MAP(n64dd_map)
	293
	294	MCFG_MACHINE_START( n64dd )
	295
	296	MCFG_CARTSLOT_MODIFY("cart")
	297	MCFG_CARTSLOT_NOT_MANDATORY
	298	MACHINE_CONFIG_END
	299
249	300	ROM_START( n64 )
250	301	ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASEFF )      /* dummy region for R4300 */
251	302
r14486	r14487
261	312	ROM_LOAD( "normslp.rom", 0x00, 0x80, CRC(4f2ae525) SHA1(eab43f8cc52c8551d9cff6fced18ef80eaba6f05) )
262	313	ROM_END
263	314
	315	ROM_START( n64dd )
	316	ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASEFF )      /* dummy region for R4300 */
	317
	318	ROM_REGION32_BE( 0x800, "user1", 0 )
	319	ROM_LOAD( "pifdata.bin", 0x0000, 0x0800, CRC(5ec82be9) SHA1(9174eadc0f0ea2654c95fd941406ab46b9dc9bdd) )
	320
	321	ROM_REGION32_BE( 0x4000000, "user2", ROMREGION_ERASEFF)
	322
	323	ROM_REGION32_BE( 0x400000, "ddipl", ROMREGION_ERASEFF)
	324	ROM_LOAD( "64ddipl.bin", 0x000000, 0x400000, CRC(7f933ce2) SHA1(bf861922dcb78c316360e3e742f4f70ff63c9bc3) )
	325
	326	ROM_REGION16_BE( 0x80, "normpoint", 0 )
	327	ROM_LOAD( "normpnt.rom", 0x00, 0x80, CRC(e7f2a005) SHA1(c27b4a364a24daeee6e99fd286753fd6216362b4) )
	328
	329	ROM_REGION16_BE( 0x80, "normslope", 0 )
	330	ROM_LOAD( "normslp.rom", 0x00, 0x80, CRC(4f2ae525) SHA1(eab43f8cc52c8551d9cff6fced18ef80eaba6f05) )
	331	ROM_END
	332
264	333	CONS(1996, n64,    0,      0,      n64,   n64,   0,   "Nintendo", "Nintendo 64", GAME_NOT_WORKING | GAME_IMPERFECT_GRAPHICS )
	334	CONS(1996, n64dd,    n64,   0,      n64dd,   n64,   0,   "Nintendo", "Nintendo 64DD", GAME_NOT_WORKING | GAME_IMPERFECT_GRAPHICS )

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