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r14327 Friday 3rd February, 2012 at 10:43:00 UTC by Miodrag Milanović
rtc65271 updated (nw)

[src/emu/machine]	rtc65271.c rtc65271.h
[src/mess/machine/ti99]	tn_ide.c

src/emu/machine/rtc65271.h

r14326	r14327
5	5	#ifndef __RTC65271_H__
6	6	#define __RTC65271_H__
7	7
8		#include "devlegcy.h"
	8	//**************************************************************************
	9	//  INTERFACE CONFIGURATION MACROS
	10	//**************************************************************************
9	11
10		typedef struct _rtc65271_config rtc65271_config;
11		struct _rtc65271_config
	12	#define MCFG_RTC65271_ADD(_tag, _config) \
	13	MCFG_DEVICE_ADD(_tag, RTC65271, 0) \
	14	MCFG_DEVICE_CONFIG(_config) \
	15
	16	// ======================> rtc65271_interface
	17
	18	struct rtc65271_interface
12	19	{
13		void (*interrupt_callback)(device_t *device, int state);
	20	devcb_write_line   m_interrupt_cb;
14	21	};
15	22
	23	// ======================> rtc65271_device
16	24
17		#define MCFG_RTC65271_ADD(_tag, _callback) \
18		MCFG_DEVICE_ADD(_tag, RTC65271, 0) \
19		MCFG_DEVICE_CONFIG_DATAPTR(rtc65271_config, interrupt_callback, _callback)
	25	class rtc65271_device :   public device_t,
	26	public device_nvram_interface,
	27	public rtc65271_interface
	28	{
	29	public:
	30	// construction/destruction
	31	rtc65271_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	32	protected:
	33	// device-level overrides
	34	virtual void device_config_complete();
	35	virtual void device_start();
	36	// device_nvram_interface overrides
	37	virtual void nvram_default();
	38	virtual void nvram_read(emu_file &file);
	39	virtual void nvram_write(emu_file &file);
	40	public:
	41	DECLARE_READ8_MEMBER( rtc_r );
	42	DECLARE_READ8_MEMBER( xram_r );
	43	DECLARE_WRITE8_MEMBER( rtc_w );
	44	DECLARE_WRITE8_MEMBER( xram_w );
	45	private:
	46	UINT8 read(int xramsel, offs_t offset);
	47	void write(int xramsel, offs_t offset, UINT8 data);
	48	void field_interrupts();
20	49
	50	static TIMER_CALLBACK( rtc_SQW_callback );
	51	static TIMER_CALLBACK( rtc_begin_update_callback );
	52	static TIMER_CALLBACK( rtc_end_update_callback );
	53
	54	void rtc_SQW_cb();
	55	void rtc_begin_update_cb();
	56	void rtc_end_update_cb();
	57	/* 64 8-bit registers (10 clock registers, 4 control/status registers, and
	58	50 bytes of user RAM) */
	59	UINT8 m_regs[64];
	60	UINT8 m_cur_reg;
21	61
22		UINT8 rtc65271_r(device_t *device, int xramsel, offs_t offset);
23		void rtc65271_w(device_t *device, int xramsel, offs_t offset, UINT8 data);
	62	/* extended RAM: 4kbytes of battery-backed RAM (in pages of 32 bytes) */
	63	UINT8 m_xram[4096];
	64	UINT8 m_cur_xram_page;
24	65
25		READ8_DEVICE_HANDLER( rtc65271_rtc_r );
26		READ8_DEVICE_HANDLER( rtc65271_xram_r );
27		WRITE8_DEVICE_HANDLER( rtc65271_rtc_w );
28		WRITE8_DEVICE_HANDLER( rtc65271_xram_w );
	66	/* update timer: called every second */
	67	emu_timer *m_update_timer;
29	68
	69	/* SQW timer: called every periodic clock half-period */
	70	emu_timer *m_SQW_timer;
	71	UINT8 m_SQW_internal_state;
30	72
31		DECLARE_LEGACY_NVRAM_DEVICE(RTC65271, rtc65271);
	73	/* callback called when interrupt pin state changes (may be NULL) */
	74	devcb_resolved_write_line m_interrupt_func;
	75	};
32	76
	77	// device type definition
	78	extern const device_type RTC65271;
	79
33	80	#endif

src/emu/machine/rtc65271.c

r14326	r14327
18	18	#include "emu.h"
19	19	#include "rtc65271.h"
20	20
21		static void field_interrupts(device_t *device);
22		static TIMER_CALLBACK( rtc_SQW_callback );
23		static TIMER_CALLBACK( rtc_begin_update_callback );
24		static TIMER_CALLBACK( rtc_end_update_callback );
25
26	21	/* Delay between the beginning (UIP asserted) and the end (UIP cleared and
27	22	update interrupt asserted) of the update cycle */
28	23	#define UPDATE_CYCLE_TIME attotime::from_usec(1984)
r14326	r14327
30	25	cycle */
31	26	/*#define UPDATE_CYCLE_DELAY attotime::from_usec(244)*/
32	27
33		typedef struct _rtc65271_state rtc65271_state;
34		struct _rtc65271_state
35		{
36		/* 64 8-bit registers (10 clock registers, 4 control/status registers, and
37		50 bytes of user RAM) */
38		UINT8 regs[64];
39		UINT8 cur_reg;
40
41		/* extended RAM: 4kbytes of battery-backed RAM (in pages of 32 bytes) */
42		UINT8 xram[4096];
43		UINT8 cur_xram_page;
44
45		/* update timer: called every second */
46		emu_timer *update_timer;
47
48		/* SQW timer: called every periodic clock half-period */
49		emu_timer *SQW_timer;
50		UINT8 SQW_internal_state;
51
52		/* callback called when interrupt pin state changes (may be NULL) */
53		void (*interrupt_callback)(device_t *device, int state);
54		};
55
56		INLINE rtc65271_state *get_safe_token(device_t *device)
57		{
58		assert(device != NULL);
59		assert(device->type() == RTC65271);
60
61		return (rtc65271_state *)downcast<legacy_device_base *>(device)->token();
62		}
63
64
65	28	enum
66	29	{
67	30	reg_second = 0,
r14326	r14327
189	152	Public functions
190	153	*/
191	154
	155	//-------------------------------------------------
	156	//  nvram_default - called to initialize NVRAM to
	157	//  its default state
	158	//-------------------------------------------------
192	159
193		/*
194		load the SRAM and register contents from file
195		*/
196		static int rtc65271_file_load(device_t *device, emu_file &file)
	160	void rtc65271_device::nvram_default()
197	161	{
198		rtc65271_state *state = get_safe_token(device);
199		UINT8 buf;
	162	memset(m_regs,0, sizeof(m_regs));
	163	memset(m_xram,0, sizeof(m_xram));
	164	}
200	165
	166	//-------------------------------------------------
	167	//  nvram_read - called to read NVRAM from the
	168	//  .nv file
	169	//-------------------------------------------------
201	170
	171	void rtc65271_device::nvram_read(emu_file &file)
	172	{
	173	UINT8 buf;
	174
202	175	/* version flag */
203	176	if (file.read(&buf, 1) != 1)
204		return 1;
	177	return;
205	178	if (buf != 0)
206		return 1;
	179	return;
207	180
208	181	/* control registers */
209	182	if (file.read(&buf, 1) != 1)
210		return 1;
211		state->regs[reg_A] = buf & (reg_A_DV /*| reg_A_RS*/);
	183	return;
	184	m_regs[reg_A] = buf & (reg_A_DV /*| reg_A_RS*/);
212	185	if (file.read(&buf, 1) != 1)
213		return 1;
214		state->regs[reg_B] = buf & (reg_B_SET | reg_B_DM | reg_B_24h | reg_B_DSE);
	186	return;
	187	m_regs[reg_B] = buf & (reg_B_SET | reg_B_DM | reg_B_24h | reg_B_DSE);
215	188
216	189	/* alarm registers */
217		if (file.read(&state->regs[reg_alarm_second], 1) != 1)
218		return 1;
219		if (file.read(&state->regs[reg_alarm_minute], 1) != 1)
220		return 1;
221		if (file.read(&state->regs[reg_alarm_hour], 1) != 1)
222		return 1;
	190	if (file.read(&m_regs[reg_alarm_second], 1) != 1)
	191	return;
	192	if (file.read(&m_regs[reg_alarm_minute], 1) != 1)
	193	return;
	194	if (file.read(&m_regs[reg_alarm_hour], 1) != 1)
	195	return;
223	196
224	197	/* user RAM */
225		if (file.read(state->regs+14, 50) != 50)
226		return 1;
	198	if (file.read(m_regs+14, 50) != 50)
	199	return;
227	200
228	201	/* extended RAM */
229		if (file.read(state->xram, 4096) != 4096)
230		return 1;
	202	if (file.read(m_xram, 4096) != 4096)
	203	return;
231	204
232		state->regs[reg_D] |= reg_D_VRT;   /* the data was backed up successfully */
233		/*state->dirty = FALSE;*/
	205	m_regs[reg_D] |= reg_D_VRT;   /* the data was backed up successfully */
	206	/*m_dirty = FALSE;*/
234	207
235	208	{
236	209	system_time systime;
237	210
238	211	/* get the current date/time from the core */
239		device->machine().current_datetime(systime);
	212	machine().current_datetime(systime);
240	213
241	214	/* set clock registers */
242		state->regs[reg_second] = systime.local_time.second;
243		state->regs[reg_minute] = systime.local_time.minute;
244		if (state->regs[reg_B] & reg_B_24h)
	215	m_regs[reg_second] = systime.local_time.second;
	216	m_regs[reg_minute] = systime.local_time.minute;
	217	if (m_regs[reg_B] & reg_B_24h)
245	218	/* 24-hour mode */
246		state->regs[reg_hour] = systime.local_time.hour;
	219	m_regs[reg_hour] = systime.local_time.hour;
247	220	else
248	221	{   /* 12-hour mode */
249	222	if (systime.local_time.hour >= 12)
250	223	{
251		state->regs[reg_hour] = 0x80;
	224	m_regs[reg_hour] = 0x80;
252	225	systime.local_time.hour -= 12;
253	226	}
254	227	else
255		state->regs[reg_hour] = 0;
256		state->regs[reg_hour] |= systime.local_time.hour ? systime.local_time.hour : 12;
	228	m_regs[reg_hour] = 0;
	229	m_regs[reg_hour] |= systime.local_time.hour ? systime.local_time.hour : 12;
257	230	}
258		state->regs[reg_weekday] = systime.local_time.weekday + 1;
259		state->regs[reg_monthday] = systime.local_time.mday;
260		state->regs[reg_month] = systime.local_time.month + 1;
261		state->regs[reg_year] = systime.local_time.year % 100;
262		if (! (state->regs[reg_B] & reg_B_DM))
	231	m_regs[reg_weekday] = systime.local_time.weekday + 1;
	232	m_regs[reg_monthday] = systime.local_time.mday;
	233	m_regs[reg_month] = systime.local_time.month + 1;
	234	m_regs[reg_year] = systime.local_time.year % 100;
	235	if (! (m_regs[reg_B] & reg_B_DM))
263	236	{   /* BCD mode */
264		state->regs[reg_second] = binary_to_BCD(state->regs[reg_second]);
265		state->regs[reg_minute] = binary_to_BCD(state->regs[reg_minute]);
266		state->regs[reg_hour] = (state->regs[reg_hour] & 0x80) | binary_to_BCD(state->regs[reg_hour] & 0x7f);
267		/*state->regs[reg_weekday] = binary_to_BCD(state->regs[reg_weekday]);*/
268		state->regs[reg_monthday] = binary_to_BCD(state->regs[reg_monthday]);
269		state->regs[reg_month] = binary_to_BCD(state->regs[reg_month]);
270		state->regs[reg_year] = binary_to_BCD(state->regs[reg_year]);
	237	m_regs[reg_second] = binary_to_BCD(m_regs[reg_second]);
	238	m_regs[reg_minute] = binary_to_BCD(m_regs[reg_minute]);
	239	m_regs[reg_hour] = (m_regs[reg_hour] & 0x80) | binary_to_BCD(m_regs[reg_hour] & 0x7f);
	240	/*m_regs[reg_weekday] = binary_to_BCD(m_regs[reg_weekday]);*/
	241	m_regs[reg_monthday] = binary_to_BCD(m_regs[reg_monthday]);
	242	m_regs[reg_month] = binary_to_BCD(m_regs[reg_month]);
	243	m_regs[reg_year] = binary_to_BCD(m_regs[reg_year]);
271	244	}
272	245	}
273
274		return 0;
275	246	}
276	247
277		/*
278		save the SRAM and register contents to file
279		*/
280		static int rtc65271_file_save(device_t *device, emu_file &file)
	248	//-------------------------------------------------
	249	//  nvram_write - called to write NVRAM to the
	250	//  .nv file
	251	//-------------------------------------------------
	252
	253	void rtc65271_device::nvram_write(emu_file &file)
281	254	{
282		rtc65271_state *state = get_safe_token(device);
283	255	UINT8 buf;
284	256
285	257
286	258	/* version flag */
287	259	buf = 0;
288	260	if (file.write(& buf, 1) != 1)
289		return 1;
	261	return;
290	262
291	263	/* control registers */
292		buf = state->regs[reg_A] & (reg_A_DV | reg_A_RS);
	264	buf = m_regs[reg_A] & (reg_A_DV | reg_A_RS);
293	265	if (file.write(&buf, 1) != 1)
294		return 1;
295		buf = state->regs[reg_B] & (reg_B_SET | reg_B_DM | reg_B_24h | reg_B_DSE);
	266	return;
	267	buf = m_regs[reg_B] & (reg_B_SET | reg_B_DM | reg_B_24h | reg_B_DSE);
296	268	if (file.write(&buf, 1) != 1)
297		return 1;
	269	return;
298	270
299	271	/* alarm registers */
300		if (file.write(&state->regs[reg_alarm_second], 1) != 1)
301		return 1;
302		if (file.write(&state->regs[reg_alarm_minute], 1) != 1)
303		return 1;
304		if (file.write(&state->regs[reg_alarm_hour], 1) != 1)
305		return 1;
	272	if (file.write(&m_regs[reg_alarm_second], 1) != 1)
	273	return;
	274	if (file.write(&m_regs[reg_alarm_minute], 1) != 1)
	275	return;
	276	if (file.write(&m_regs[reg_alarm_hour], 1) != 1)
	277	return;
306	278
307	279	/* user RAM */
308		if (file.write(state->regs+14, 50) != 50)
309		return 1;
	280	if (file.write(m_regs+14, 50) != 50)
	281	return;
310	282
311	283	/* extended RAM */
312		if (file.write(state->xram, 4096) != 4096)
313		return 1;
314
315		return 0;
	284	if (file.write(m_xram, 4096) != 4096)
	285	return;
316	286	}
317	287
318	288	/*
r14326	r14327
321	291	xramsel: select RTC register if 0, XRAM if 1
322	292	offset: address (A0-A5 pins)
323	293	*/
324		UINT8 rtc65271_r(device_t *device, int xramsel, offs_t offset)
	294	UINT8 rtc65271_device::read(int xramsel, offs_t offset)
325	295	{
326		rtc65271_state *state = get_safe_token(device);
327	296	int reply;
328	297
329	298	if (xramsel)
330	299	{
331	300	if (offset & 0x20)
332	301	/* XRAM page register */
333		reply = state->cur_xram_page;
	302	reply = m_cur_xram_page;
334	303	else
335	304	/* XRAM data */
336		reply = state->xram[(offset & 0x1f) + 0x0020*state->cur_xram_page];
	305	reply = m_xram[(offset & 0x1f) + 0x0020*m_cur_xram_page];
337	306	}
338	307	else
339	308	{
340	309	if (offset & 0x01)
341	310	/* data register */
342		switch (state->cur_reg)
	311	switch (m_cur_reg)
343	312	{
344	313	case reg_C:
345		reply = state->regs[state->cur_reg];
346		state->regs[state->cur_reg] = 0;
347		field_interrupts(device);
	314	reply = m_regs[m_cur_reg];
	315	m_regs[m_cur_reg] = 0;
	316	field_interrupts();
348	317	break;
349	318	case reg_D:
350		reply = state->regs[state->cur_reg];
351		state->regs[state->cur_reg] = /*0*/reg_D_VRT;   /* set VRT flag so that the computer does not complain that the battery is low */
	319	reply = m_regs[m_cur_reg];
	320	m_regs[m_cur_reg] = /*0*/reg_D_VRT;   /* set VRT flag so that the computer does not complain that the battery is low */
352	321	break;
353	322
354	323	default:
355		reply = state->regs[state->cur_reg];
	324	reply = m_regs[m_cur_reg];
356	325	break;
357	326	}
358	327	else
359	328	/* indirect address register */
360		reply = state->cur_reg;
	329	reply = m_cur_reg;
361	330	}
362	331
363	332	return reply;
364	333	}
365	334
366		READ8_DEVICE_HANDLER( rtc65271_rtc_r )
	335	READ8_MEMBER( rtc65271_device::rtc_r )
367	336	{
368		return rtc65271_r( device, 0, offset );
	337	return read(0, offset );
369	338	}
370	339
371		READ8_DEVICE_HANDLER( rtc65271_xram_r )
	340	READ8_MEMBER( rtc65271_device::xram_r )
372	341	{
373		return rtc65271_r( device, 1, offset );
	342	return read(1, offset );
374	343	}
375	344
376	345	/*
r14326	r14327
379	348	xramsel: select RTC register if 0, XRAM if 1
380	349	offset: address (A0-A5 pins)
381	350	*/
382		void rtc65271_w(device_t *device, int xramsel, offs_t offset, UINT8 data)
	351	void rtc65271_device::write(int xramsel, offs_t offset, UINT8 data)
383	352	{
384		rtc65271_state *state = get_safe_token(device);
385	353	if (xramsel)
386	354	{
387	355	if (offset & 0x20)
388	356	/* XRAM page register */
389		state->cur_xram_page = data & 0x7f;
	357	m_cur_xram_page = data & 0x7f;
390	358	else
391	359	/* XRAM data */
392		state->xram[(offset & 0x1f) + 0x0020*state->cur_xram_page] = data;
	360	m_xram[(offset & 0x1f) + 0x0020*m_cur_xram_page] = data;
393	361	}
394	362	else
395	363	{
396	364	if (offset & 0x01)
397	365	/* data register */
398		switch (state->cur_reg)
	366	switch (m_cur_reg)
399	367	{
400	368	case reg_second:
401	369	/* the data sheet says bit 7 is read-only.  (I have no idea of
402	370	the reason why it is.) */
403		state->regs[reg_second] = data & 0x7f;
	371	m_regs[reg_second] = data & 0x7f;
404	372	break;
405	373
406	374	case reg_A:
407		if ((data & reg_A_RS) != (state->regs[state->cur_reg] & reg_A_RS))
	375	if ((data & reg_A_RS) != (m_regs[m_cur_reg] & reg_A_RS))
408	376	{
409	377	if (data & reg_A_RS)
410	378	{
411	379	attotime period = attotime::from_hz(SQW_freq_table[data & reg_A_RS]);
412	380	attotime half_period = period / 2;
413		attotime elapsed = state->update_timer->elapsed();
	381	attotime elapsed = m_update_timer->elapsed();
414	382
415	383	if (half_period > elapsed)
416		state->SQW_timer->adjust(half_period - elapsed);
	384	m_SQW_timer->adjust(half_period - elapsed);
417	385	else
418		state->SQW_timer->adjust(half_period);
	386	m_SQW_timer->adjust(half_period);
419	387	}
420	388	else
421	389	{
422		state->SQW_internal_state = 0;   /* right??? */
	390	m_SQW_internal_state = 0;   /* right??? */
423	391
424	392	/* Stop the divider used for SQW and periodic interrupts. */
425		state->SQW_timer->adjust(attotime::never);
	393	m_SQW_timer->adjust(attotime::never);
426	394	}
427	395	}
428	396	/* The UIP bit is read-only */
429		state->regs[reg_A] = (data & ~reg_A_UIP) | (state->regs[reg_A] & reg_A_UIP);
	397	m_regs[reg_A] = (data & ~reg_A_UIP) | (m_regs[reg_A] & reg_A_UIP);
430	398	break;
431	399
432	400	case reg_B:
433		state->regs[state->cur_reg] = data;
	401	m_regs[m_cur_reg] = data;
434	402	if (data & reg_B_SET)
435	403	{
436	404	/* if we are in SET mode, clear update cycle */
437		state->regs[reg_A] &= ~reg_A_UIP;
438		state->regs[reg_B] &= ~reg_B_UIE;   /* the data sheet tells this, but I wonder how much sense it makes */
439		field_interrupts(device);
	405	m_regs[reg_A] &= ~reg_A_UIP;
	406	m_regs[reg_B] &= ~reg_B_UIE;   /* the data sheet tells this, but I wonder how much sense it makes */
	407	field_interrupts();
440	408	}
441	409	break;
442	410
r14326	r14327
445	413	break;
446	414
447	415	default:
448		state->regs[state->cur_reg] = data;
	416	m_regs[m_cur_reg] = data;
449	417	break;
450	418	}
451	419	else
452	420	/* indirect address register */
453		state->cur_reg = data & 0x3f;
	421	m_cur_reg = data & 0x3f;
454	422	}
455	423	}
456	424
457		WRITE8_DEVICE_HANDLER( rtc65271_rtc_w )
	425	WRITE8_MEMBER( rtc65271_device::rtc_w )
458	426	{
459		rtc65271_w( device, 0, offset, data );
	427	write(0, offset, data );
460	428	}
461	429
462		WRITE8_DEVICE_HANDLER( rtc65271_xram_w )
	430	WRITE8_MEMBER( rtc65271_device::xram_w )
463	431	{
464		rtc65271_w( device, 1, offset, data );
	432	write(1, offset, data );
465	433	}
466	434
467		static void field_interrupts(device_t *device)
	435	void rtc65271_device::field_interrupts()
468	436	{
469		rtc65271_state *state = get_safe_token(device);
470
471		if (state->regs[reg_C] & state->regs[reg_B] & (reg_C_PF | reg_C_AF | reg_C_UF))
	437	if (m_regs[reg_C] & m_regs[reg_B] & (reg_C_PF | reg_C_AF | reg_C_UF))
472	438	{
473		state->regs[reg_C] |= reg_C_IRQF;
474		if (state->interrupt_callback)
475		state->interrupt_callback(device, 1);
	439	m_regs[reg_C] |= reg_C_IRQF;
	440	if (!m_interrupt_func.isnull())
	441	m_interrupt_func(1);
476	442	}
477	443	else
478	444	{
479		state->regs[reg_C] &= ~reg_C_IRQF;
480		if (state->interrupt_callback)
481		state->interrupt_callback(device, 0);
	445	m_regs[reg_C] &= ~reg_C_IRQF;
	446	if (!m_interrupt_func.isnull())
	447	m_interrupt_func(0);
482	448	}
483	449	}
484	450
r14326	r14327
486	452	/*
487	453	Timer handlers
488	454	*/
	455	TIMER_CALLBACK( rtc65271_device::rtc_SQW_callback )
	456	{
	457	rtc65271_device *rtc = reinterpret_cast<rtc65271_device *>(ptr);
	458	rtc->rtc_SQW_cb();
	459	}
489	460
	461	TIMER_CALLBACK( rtc65271_device::rtc_begin_update_callback )
	462	{
	463	rtc65271_device *rtc = reinterpret_cast<rtc65271_device *>(ptr);
	464	rtc->rtc_begin_update_cb();
	465	}
	466
	467	TIMER_CALLBACK( rtc65271_device::rtc_end_update_callback )
	468	{
	469	rtc65271_device *rtc = reinterpret_cast<rtc65271_device *>(ptr);
	470	rtc->rtc_end_update_cb();
	471	}
490	472	/*
491	473	Update SQW output state each half-period and assert periodic interrupt each
492	474	period.
493	475	*/
494		static TIMER_CALLBACK( rtc_SQW_callback )
	476	void rtc65271_device::rtc_SQW_cb()
495	477	{
496		device_t *device = (device_t *)ptr;
497		rtc65271_state *state = get_safe_token(device);
498	478	attotime half_period;
499	479
500		state->SQW_internal_state = ! state->SQW_internal_state;
501		if (! state->SQW_internal_state)
	480	m_SQW_internal_state = ! m_SQW_internal_state;
	481	if (! m_SQW_internal_state)
502	482	{
503	483	/* high-to-low??? transition -> interrupt (or should it be low-to-high?) */
504		state->regs[reg_C] |= reg_C_PF;
505		field_interrupts(device);
	484	m_regs[reg_C] |= reg_C_PF;
	485	field_interrupts();
506	486	}
507	487
508		half_period = attotime::from_hz(SQW_freq_table[state->regs[reg_A] & reg_A_RS]) / 2;
509		state->SQW_timer->adjust(half_period);
	488	half_period = attotime::from_hz(SQW_freq_table[m_regs[reg_A] & reg_A_RS]) / 2;
	489	m_SQW_timer->adjust(half_period);
510	490	}
511	491
512	492	/*
513	493	Begin update cycle (called every second)
514	494	*/
515		static TIMER_CALLBACK( rtc_begin_update_callback )
	495	void rtc65271_device::rtc_begin_update_cb()
516	496	{
517		device_t *device = (device_t *)ptr;
518		rtc65271_state *state = get_safe_token(device);
519
520		if (((state->regs[reg_A] & reg_A_DV) == 0x20) && ! (state->regs[reg_B] & reg_B_SET))
	497	if (((m_regs[reg_A] & reg_A_DV) == 0x20) && ! (m_regs[reg_B] & reg_B_SET))
521	498	{
522		state->regs[reg_A] |= reg_A_UIP;
	499	m_regs[reg_A] |= reg_A_UIP;
523	500
524	501	/* schedule end of update cycle */
525		device->machine().scheduler().timer_set(UPDATE_CYCLE_TIME, FUNC(rtc_end_update_callback), 0, (void *)device);
	502	machine().scheduler().timer_set(UPDATE_CYCLE_TIME, FUNC(rtc_end_update_callback), 0, (void *)this);
526	503	}
527	504	}
528	505
r14326	r14327
530	507	End update cycle (called UPDATE_CYCLE_TIME = 1948us after start of update
531	508	cycle)
532	509	*/
533		static TIMER_CALLBACK( rtc_end_update_callback )
	510	void rtc65271_device::rtc_end_update_cb()
534	511	{
535	512	static const int days_in_month_table[12] =
536	513	{
537	514	31,28,31, 30,31,30,
538	515	31,31,30, 31,30,31
539	516	};
540		device_t *device = (device_t *)ptr;
541		rtc65271_state *state = get_safe_token(device);
542	517	UINT8 (*increment)(UINT8 data);
543	518	int c59, c23, c12, c11, c29;
544	519
545		if (! (state->regs[reg_A] & reg_A_UIP))
	520	if (! (m_regs[reg_A] & reg_A_UIP))
546	521	/* abort if update cycle has been canceled */
547	522	return;
548	523
549		if (state->regs[reg_B] & reg_B_DM)
	524	if (m_regs[reg_B] & reg_B_DM)
550	525	{
551	526	/* binary mode */
552	527	increment = increment_binary;
r14326	r14327
568	543	}
569	544
570	545	/* increment second */
571		if (state->regs[reg_second] < c59)
572		state->regs[reg_second] = (*increment)(state->regs[reg_second]);
	546	if (m_regs[reg_second] < c59)
	547	m_regs[reg_second] = (*increment)(m_regs[reg_second]);
573	548	else
574	549	{
575		state->regs[reg_second] = 0;
	550	m_regs[reg_second] = 0;
576	551
577	552	/* increment minute */
578		if (state->regs[reg_minute] < c59)
579		state->regs[reg_minute] = (*increment)(state->regs[reg_minute]);
	553	if (m_regs[reg_minute] < c59)
	554	m_regs[reg_minute] = (*increment)(m_regs[reg_minute]);
580	555	else
581	556	{
582		state->regs[reg_minute] = 0;
	557	m_regs[reg_minute] = 0;
583	558
584	559	/* increment hour */
585		if (state->regs[reg_B] & reg_B_24h)
	560	if (m_regs[reg_B] & reg_B_24h)
586	561	{
587	562	/* 24 hour mode */
588		if (state->regs[reg_hour] < c23)
589		state->regs[reg_hour] = (*increment)(state->regs[reg_hour]);
	563	if (m_regs[reg_hour] < c23)
	564	m_regs[reg_hour] = (*increment)(m_regs[reg_hour]);
590	565	else
591		state->regs[reg_hour] = 0;
	566	m_regs[reg_hour] = 0;
592	567	}
593	568	else
594	569	{
595	570	/* 12 hour mode */
596		if (state->regs[reg_hour] < c12)
	571	if (m_regs[reg_hour] < c12)
597	572	{
598		if ((state->regs[reg_hour] & 0x7f) == c11)
599		state->regs[reg_hour] ^= 0x80;
600		state->regs[reg_hour] = ((*increment)(state->regs[reg_hour] & 0x7f) & 0x7f)
601		| (state->regs[reg_hour] & 0x80);
	573	if ((m_regs[reg_hour] & 0x7f) == c11)
	574	m_regs[reg_hour] ^= 0x80;
	575	m_regs[reg_hour] = ((*increment)(m_regs[reg_hour] & 0x7f) & 0x7f)
	576	| (m_regs[reg_hour] & 0x80);
602	577	}
603	578	else
604		state->regs[reg_hour] = 1 | (state->regs[reg_hour] & 0x80);
	579	m_regs[reg_hour] = 1 | (m_regs[reg_hour] & 0x80);
605	580	}
606	581
607	582	/* increment day if needed */
608		if (state->regs[reg_hour] == ((state->regs[reg_B] & reg_B_24h) ? 0 : c12))
	583	if (m_regs[reg_hour] == ((m_regs[reg_B] & reg_B_24h) ? 0 : c12))
609	584	{
610	585	/* increment day */
611	586	int days_in_month;
612	587
613		if (state->regs[reg_weekday] < 7)
614		state->regs[reg_weekday]++;
	588	if (m_regs[reg_weekday] < 7)
	589	m_regs[reg_weekday]++;
615	590	else
616		state->regs[reg_weekday] = 1;
	591	m_regs[reg_weekday] = 1;
617	592
618		if ((state->regs[reg_month] != 2) || (state->regs[reg_year] & 0x03))
	593	if ((m_regs[reg_month] != 2) || (m_regs[reg_year] & 0x03))
619	594	{
620		if (state->regs[reg_B] & reg_B_DM)
	595	if (m_regs[reg_B] & reg_B_DM)
621	596	{
622	597	/* binary mode */
623		days_in_month = days_in_month_table[state->regs[reg_month] - 1];
	598	days_in_month = days_in_month_table[m_regs[reg_month] - 1];
624	599	}
625	600	else
626	601	{
627	602	/* BCD mode */
628		days_in_month = binary_to_BCD(days_in_month_table[BCD_to_binary(state->regs[reg_month]) - 1]);
	603	days_in_month = binary_to_BCD(days_in_month_table[BCD_to_binary(m_regs[reg_month]) - 1]);
629	604	}
630	605	}
631	606	else
632	607	days_in_month = c29;
633	608
634		if (state->regs[reg_monthday] < days_in_month)
635		state->regs[reg_monthday] = (*increment)(state->regs[reg_monthday]);
	609	if (m_regs[reg_monthday] < days_in_month)
	610	m_regs[reg_monthday] = (*increment)(m_regs[reg_monthday]);
636	611	else
637	612	{
638	613	/* increment month */
639		state->regs[reg_monthday] = 1;
	614	m_regs[reg_monthday] = 1;
640	615
641		if (state->regs[reg_month] < c12)
642		state->regs[reg_month] = (*increment)(state->regs[reg_month]);
	616	if (m_regs[reg_month] < c12)
	617	m_regs[reg_month] = (*increment)(m_regs[reg_month]);
643	618	else
644	619	{
645	620	/* increment year */
646		state->regs[reg_month] = 1;
	621	m_regs[reg_month] = 1;
647	622
648		if (state->regs[reg_B] & reg_B_DM)
	623	if (m_regs[reg_B] & reg_B_DM)
649	624	{
650	625	/* binary mode */
651		if (state->regs[reg_year] < 99)
652		state->regs[reg_year]++;
	626	if (m_regs[reg_year] < 99)
	627	m_regs[reg_year]++;
653	628	else
654		state->regs[reg_year] = 0;
	629	m_regs[reg_year] = 0;
655	630	}
656	631	else
657	632	{
658	633	/* BCD mode */
659		state->regs[reg_year] = increment_BCD(state->regs[reg_year]);
	634	m_regs[reg_year] = increment_BCD(m_regs[reg_year]);
660	635	}
661	636	}
662	637	}
r14326	r14327
664	639	}
665	640	}
666	641
667		state->regs[reg_A] &= ~reg_A_UIP;
668		state->regs[reg_C] |= reg_C_UF;
	642	m_regs[reg_A] &= ~reg_A_UIP;
	643	m_regs[reg_C] |= reg_C_UF;
669	644
670	645	/* test for alarm (values in range 0xc0-0xff mean "don't care") */
671		if ((((state->regs[reg_alarm_second] & 0xc0) == 0xc0) || (state->regs[reg_alarm_second] == state->regs[reg_second]))
672		&& (((state->regs[reg_alarm_minute] & 0xc0) == 0xc0) || (state->regs[reg_alarm_minute] == state->regs[reg_minute]))
673		&& (((state->regs[reg_alarm_hour] & 0xc0) == 0xc0) || (state->regs[reg_alarm_hour] == state->regs[reg_hour])))
674		state->regs[reg_C] |= reg_C_AF;
	646	if ((((m_regs[reg_alarm_second] & 0xc0) == 0xc0) || (m_regs[reg_alarm_second] == m_regs[reg_second]))
	647	&& (((m_regs[reg_alarm_minute] & 0xc0) == 0xc0) || (m_regs[reg_alarm_minute] == m_regs[reg_minute]))
	648	&& (((m_regs[reg_alarm_hour] & 0xc0) == 0xc0) || (m_regs[reg_alarm_hour] == m_regs[reg_hour])))
	649	m_regs[reg_C] |= reg_C_AF;
675	650
676		field_interrupts(device);
	651	field_interrupts();
677	652	}
678	653
679		/*
680		Initialize clock
	654	// device type definition
	655	const device_type RTC65271 = &device_creator<rtc65271_device>;
681	656
682		interrupt_callback: callback called when interrupt pin state changes (may
683		be NULL)
684		*/
	657	//-------------------------------------------------
	658	//  rtc65271_device - constructor
	659	//-------------------------------------------------
685	660
686		static DEVICE_START( rtc65271 )
	661	rtc65271_device::rtc65271_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	662	: device_t(mconfig, RTC65271, "RTC65271", tag, owner, clock),
	663	device_nvram_interface(mconfig, *this)
687	664	{
688		rtc65271_config *config = (rtc65271_config *)downcast<const legacy_device_base *>(device)->inline_config();
689		rtc65271_state *state = get_safe_token(device);
690
691		state->update_timer = device->machine().scheduler().timer_alloc(FUNC(rtc_begin_update_callback), (void *)device);
692		state->update_timer->adjust(attotime::from_seconds(1), 0, attotime::from_seconds(1));
693		state->SQW_timer = device->machine().scheduler().timer_alloc(FUNC(rtc_SQW_callback), (void *)device);
694		state->interrupt_callback = config->interrupt_callback;
695
696		device->save_item(NAME(state->regs));
697		device->save_item(NAME(state->cur_reg));
698		device->save_item(NAME(state->xram));
699		device->save_item(NAME(state->cur_xram_page));
700		device->save_item(NAME(state->SQW_internal_state));
701	665	}
702	666
	667	//-------------------------------------------------
	668	//  device_config_complete - perform any
	669	//  operations now that the configuration is
	670	//  complete
	671	//-------------------------------------------------
703	672
704		static DEVICE_NVRAM( rtc65271 )
	673	void rtc65271_device::device_config_complete()
705	674	{
706		if (read_or_write)
707		rtc65271_file_save(device, *file);
708		else if (file)
709		rtc65271_file_load(device, *file);
	675	// inherit a copy of the static data
	676	const rtc65271_interface *intf = reinterpret_cast<const rtc65271_interface *>(static_config());
	677	if (intf != NULL)
	678	*static_cast<rtc65271_interface *>(this) = *intf;
	679
	680	// or initialize to defaults if none provided
	681	else
	682	{
	683	memset(&m_interrupt_cb, 0, sizeof(m_interrupt_cb));
	684	}
710	685	}
711	686
	687	//-------------------------------------------------
	688	//  device_start - device-specific startup
	689	//-------------------------------------------------
	690	void rtc65271_device::device_start()
	691	{
	692	m_update_timer = machine().scheduler().timer_alloc(FUNC(rtc_begin_update_callback), (void *)this);
	693	m_update_timer->adjust(attotime::from_seconds(1), 0, attotime::from_seconds(1));
	694	m_SQW_timer = machine().scheduler().timer_alloc(FUNC(rtc_SQW_callback), (void *)this);
	695	m_interrupt_func.resolve(m_interrupt_cb, *this);
712	696
713		static const char DEVTEMPLATE_SOURCE[] = __FILE__;
	697	save_item(NAME(m_regs));
	698	save_item(NAME(m_cur_reg));
	699	save_item(NAME(m_xram));
	700	save_item(NAME(m_cur_xram_page));
	701	save_item(NAME(m_SQW_internal_state));
	702	}
714	703
715		#define DEVTEMPLATE_ID(p,s)      p##rtc65271##s
716		#define DEVTEMPLATE_FEATURES   DT_HAS_START | DT_HAS_NVRAM | DT_HAS_INLINE_CONFIG
717		#define DEVTEMPLATE_NAME      "RTC65271"
718		#define DEVTEMPLATE_FAMILY      "RTC"
719		#include "devtempl.h"
720
721
722		DEFINE_LEGACY_NVRAM_DEVICE(RTC65271, rtc65271);

src/mess/machine/ti99/tn_ide.c

r14326	r14327
57	57	int      select_mask;
58	58	int      select_value;
59	59
60		device_t      *rtc;
	60	rtc65271_device      *rtc;
61	61	device_t      *ide;
62	62
63	63	int      ide_irq;
r14326	r14327
174	174	case 0:      /* RTC RAM */
175	175	if (addr & 0x80)
176	176	/* RTC RAM page register */
177		reply = rtc65271_xram_r(card->rtc, (addr & 0x1f) | 0x20);
	177	reply = card->rtc->xram_r(*memory_nonspecific_space(device->machine()),(addr & 0x1f) | 0x20);
178	178	else
179	179	/* RTC RAM read */
180		reply = rtc65271_xram_r(card->rtc, addr);
	180	reply = card->rtc->xram_r(*memory_nonspecific_space(device->machine()),addr);
181	181	break;
182	182	case 1:      /* RTC registers */
183	183	if (addr & 0x10)
184	184	/* register data */
185		reply = rtc65271_rtc_r(card->rtc, 1);
	185	reply = card->rtc->rtc_r(*memory_nonspecific_space(device->machine()),1);
186	186	else
187	187	/* register select */
188		reply = rtc65271_rtc_r(card->rtc, 0);
	188	reply = card->rtc->rtc_r(*memory_nonspecific_space(device->machine()),0);
189	189	break;
190	190	case 2:      /* IDE registers set 1 (CS1Fx) */
191	191	if (card->tms9995_mode ? (!(addr & 1)) : (addr & 1))
r14326	r14327
245	245	case 0:      /* RTC RAM */
246	246	if (addr & 0x80)
247	247	/* RTC RAM page register */
248		rtc65271_xram_w(card->rtc, (addr & 0x1f) | 0x20, data);
	248	card->rtc->xram_w(*memory_nonspecific_space(device->machine()),(addr & 0x1f) | 0x20, data);
249	249	else
250	250	/* RTC RAM write */
251		rtc65271_xram_w(card->rtc, addr, data);
	251	card->rtc->xram_w(*memory_nonspecific_space(device->machine()),addr, data);
252	252	break;
253	253	case 1:      /* RTC registers */
254	254	if (addr & 0x10)
255	255	/* register data */
256		rtc65271_rtc_w(card->rtc, 1, data);
	256	card->rtc->rtc_w(*memory_nonspecific_space(device->machine()),1, data);
257	257	else
258	258	/* register select */
259		rtc65271_rtc_w(card->rtc, 0, data);
	259	card->rtc->rtc_w(*memory_nonspecific_space(device->machine()),0, data);
260	260	break;
261	261	case 2:      /* IDE registers set 1 (CS1Fx) */
262	262	/*
r14326	r14327
335	335	clk_interrupt_callback()
336	336	clock interrupt callback
337	337	*/
338		static void clock_interrupt_callback(device_t *device, int state)
	338	static WRITE_LINE_DEVICE_HANDLER(clock_interrupt_callback)
339	339	{
340	340	tn_ide_state *card = get_safe_token(device->owner());
341	341	card->clk_irq = state;
r14326	r14327
346	346	static DEVICE_START( tn_ide )
347	347	{
348	348	tn_ide_state *card = get_safe_token(device);
349		card->rtc = device->subdevice("ide_rtc");
	349	card->rtc = device->subdevice<rtc65271_device>("ide_rtc");
350	350	card->ide = device->subdevice("ide");
351	351
352	352	peb_callback_if *topeb = (peb_callback_if *)device->static_config();
r14326	r14327
388	388	}
389	389	}
390	390
	391	static const rtc65271_interface ide_rtc_cfg =
	392	{
	393	DEVCB_LINE(clock_interrupt_callback)
	394	};
	395
391	396	MACHINE_CONFIG_FRAGMENT( tn_ide )
392		MCFG_RTC65271_ADD( "ide_rtc", clock_interrupt_callback )
	397	MCFG_RTC65271_ADD( "ide_rtc", ide_rtc_cfg )
393	398	MCFG_IDE_CONTROLLER_ADD( "ide", ide_interrupt_callback )
394	399	MCFG_IDE_CONTROLLER_REGIONS(":peribox:idehd0:drive", NULL)
395	400	MACHINE_CONFIG_END

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