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r13745 Tuesday 27th December, 2011 at 16:04:42 UTC by Tim Schuerewegen
s3c24xx: lots of changes, for future Happy Fish 302-in-1 and Palm Z22 drivers

[src/emu/machine]	s3c2400.h s3c2410.c s3c2410.h s3c2440.h s3c24xx.c
[src/mame/drivers]	ghosteo.c
[src/mess/drivers]	gizmondo.c hp49gp.c

src/mame/drivers/ghosteo.c

r13744	r13745
81	81	: driver_device(mconfig, type, tag) { }
82	82
83	83	UINT32 *m_system_memory;
84		UINT32 *m_steppingstone;
85	84	int m_security_count;
86	85	UINT32 m_bballoon_port[20];
87	86	struct nand_t m_nand;
r13744	r13745
111	110	24-ch external interrupts Controller (Wake-up source 16-ch)
112	111	*/
113	112
	113	// GPIO
	114
114	115	static const UINT8 security_data[] = { 0x01, 0xC4, 0xFF, 0x22 };
115	116
116
117		static UINT32 s3c2410_gpio_port_r( device_t *device, int port)
	117	static UINT32 s3c2410_gpio_port_r( device_t *device, int port, UINT32 mask)
118	118	{
119	119	ghosteo_state *state = device->machine().driver_data<ghosteo_state>();
120	120	UINT32 data = state->m_bballoon_port[port];
r13744	r13745
135	135	return data;
136	136	}
137	137
138		static void s3c2410_gpio_port_w( device_t *device, int port, UINT32 data)
	138	static void s3c2410_gpio_port_w( device_t *device, int port, UINT32 mask, UINT32 data)
139	139	{
140	140	ghosteo_state *state = device->machine().driver_data<ghosteo_state>();
141	141	UINT32 old_value = state->m_bballoon_port[port];
r13744	r13745
165	165	}
166	166	}
167	167
	168	// CORE
	169
	170	/*
	171
	172	OM[1:0] = 00b : Enable NAND flash controller auto boot mode
	173
	174	NAND flash memory page size should be 512Bytes.
	175
	176	NCON : NAND flash memory address step selection
	177	0 : 3 Step addressing
	178	1 : 4 Step addressing
	179
	180	*/
	181
	182	static int s3c2410_core_pin_r( device_t *device, int pin)
	183	{
	184	int data = 0;
	185	switch (pin)
	186	{
	187	case S3C2410_CORE_PIN_NCON : data = 1; break;
	188	case S3C2410_CORE_PIN_OM0  : data = 0; break;
	189	case S3C2410_CORE_PIN_OM1  : data = 0; break;
	190	}
	191	return data;
	192	}
	193
	194	// NAND
	195
168	196	static WRITE8_DEVICE_HANDLER( s3c2410_nand_command_w )
169	197	{
170	198	ghosteo_state *state = device->machine().driver_data<ghosteo_state>();
r13744	r13745
276	304	logerror( "s3c2410_nand_data_w %02X\n", data);
277	305	}
278	306
	307	// I2C
	308
279	309	static WRITE_LINE_DEVICE_HANDLER( s3c2410_i2c_scl_w )
280	310	{
281	311	device_t *i2cmem = device->machine().device( "i2cmem");
r13744	r13745
316	346	}
317	347
318	348	static ADDRESS_MAP_START( bballoon_map, AS_PROGRAM, 32 )
319		AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_BASE_MEMBER(ghosteo_state, m_steppingstone) AM_MIRROR(0x40000000)
320	349	AM_RANGE(0x10000000, 0x10000003) AM_READ_PORT("10000000")
321	350	AM_RANGE(0x10100000, 0x10100003) AM_READ_PORT("10100000")
322	351	AM_RANGE(0x10200000, 0x10200003) AM_READ_PORT("10200000")
r13744	r13745
382	411	PORT_BIT( 0xFFFFFF50, IP_ACTIVE_LOW, IPT_UNUSED )
383	412	INPUT_PORTS_END
384	413
385		/*
386		static NAND_INTERFACE( bballoon_nand_intf )
387		{
388		DEVCB_DEVICE_LINE("s3c2410", s3c2410_pin_frnb_w)
389		};
390		*/
391
392	414	static const s3c2410_interface bballoon_s3c2410_intf =
393	415	{
	416	// CORE (pin read / pin write)
	417	{ s3c2410_core_pin_r, NULL },
394	418	// GPIO (port read / port write)
395	419	{ s3c2410_gpio_port_r, s3c2410_gpio_port_w },
396	420	// I2C (scl write / sda read / sda write)
r13744	r13745
399	423	{ NULL },
400	424	// I2S (data write)
401	425	{ NULL },
402		// NAND (command write, address write, data read, data write)
	426	// NAND (command write / address write / data read / data write)
403	427	{ s3c2410_nand_command_w, s3c2410_nand_address_w, s3c2410_nand_data_r, s3c2410_nand_data_w }
404	428	};
405	429
r13744	r13745
549	573
550	574	static DRIVER_INIT( bballoon )
551	575	{
552		ghosteo_state *state = machine.driver_data<ghosteo_state>();
553		memcpy( state->m_steppingstone, machine.region( "user1")->base(), 4 * 1024);
554	576	}
555	577
556	578	GAME( 2003, bballoon, 0, bballoon, bballoon, bballoon, ROT0, "Eolith", "BnB Arcade", GAME_NO_SOUND )

src/emu/machine/s3c2400.h

r13744	r13745
39	39	TYPE DEFINITIONS
40	40	*******************************************************************************/
41	41
42		typedef UINT32 (*s3c24xx_gpio_port_r_func)( device_t *device, int port);
43		typedef void (*s3c24xx_gpio_port_w_func)( device_t *device, int port, UINT32 data);
	42	typedef UINT32 (*s3c24xx_gpio_port_r_func)( device_t *device, int port, UINT32 mask);
	43	typedef void (*s3c24xx_gpio_port_w_func)( device_t *device, int port, UINT32 mask, UINT32 data);
44	44
	45	typedef int (*s3c24xx_core_pin_r_func)( device_t *device, int pin);
	46	typedef void (*s3c24xx_core_pin_w_func)( device_t *device, int pin, int data);
	47
	48	typedef struct _s3c2400_interface_core s3c2400_interface_core;
	49	struct _s3c2400_interface_core
	50	{
	51	s3c24xx_core_pin_r_func pin_r;
	52	s3c24xx_core_pin_w_func pin_w;
	53	};
	54
45	55	typedef struct _s3c2400_interface_gpio s3c2400_interface_gpio;
46	56	struct _s3c2400_interface_gpio
47	57	{
r13744	r13745
78	88	typedef struct _s3c2400_interface s3c2400_interface;
79	89	struct _s3c2400_interface
80	90	{
	91	s3c2400_interface_core core;
81	92	s3c2400_interface_gpio gpio;
82	93	s3c2400_interface_i2c i2c;
83	94	s3c2400_interface_adc adc;
r13744	r13745
380	391	#define S3C24XX_GPIO_PORT_F S3C2400_GPIO_PORT_F
381	392	#define S3C24XX_GPIO_PORT_G S3C2400_GPIO_PORT_G
382	393
	394	#define S3C24XX_UART_COUNT  2
	395	#define S3C24XX_DMA_COUNT   4
	396	#define S3C24XX_SPI_COUNT   1
	397
383	398	/*******************************************************************************
384	399	TYPE DEFINITIONS
385	400	*******************************************************************************/
r13744	r13745
707	722	s3c24xx_memcon_t memcon;
708	723	s3c24xx_usbhost_t usbhost;
709	724	s3c24xx_irq_t irq;
710		s3c24xx_dma_t dma[4];
	725	s3c24xx_dma_t dma[S3C24XX_DMA_COUNT];
711	726	s3c24xx_clkpow_t clkpow;
712	727	s3c24xx_lcd_t lcd;
713	728	s3c24xx_lcdpal_t lcdpal;
714		s3c24xx_uart_t uart[2];
	729	s3c24xx_uart_t uart[S3C24XX_UART_COUNT];
715	730	s3c24xx_pwm_t pwm;
716	731	s3c24xx_usbdev_t usbdev;
717	732	s3c24xx_wdt_t wdt;
r13744	r13745
720	735	s3c24xx_gpio_t gpio;
721	736	s3c24xx_rtc_t rtc;
722	737	s3c24xx_adc_t adc;
723		s3c24xx_spi_t spi[1];
	738	s3c24xx_spi_t spi[S3C24XX_SPI_COUNT];
724	739	s3c24xx_mmc_t mmc;
725	740	} s3c24xx_t;
726	741

src/emu/machine/s3c2410.c

r13744	r13745
104	104
105	105	void s3c2410_nand_calculate_mecc( UINT8 *data, UINT32 size, UINT8 *mecc)
106	106	{
107		mecc[0] = mecc[1] = mecc[2] = mecc[3] = 0;
	107	mecc[0] = mecc[1] = mecc[2] = mecc[3] = 0xFF;
108	108	for (int i = 0; i < size; i++) nand_update_mecc( mecc, i, data[i]);
109	109	}
110	110

src/emu/machine/s3c2410.h

r13744	r13745
34	34	S3C2410_GPIO_PORT_H
35	35	};
36	36
	37	enum
	38	{
	39	S3C2410_CORE_PIN_NCON = 0,
	40	S3C2410_CORE_PIN_OM0,
	41	S3C2410_CORE_PIN_OM1
	42	};
	43
37	44	DECLARE_LEGACY_DEVICE(S3C2410, s3c2410);
38	45
39	46	READ32_DEVICE_HANDLER( s3c2410_lcd_r );
r13744	r13745
42	49	TYPE DEFINITIONS
43	50	*******************************************************************************/
44	51
45		typedef UINT32 (*s3c24xx_gpio_port_r_func)( device_t *device, int port);
46		typedef void (*s3c24xx_gpio_port_w_func)( device_t *device, int port, UINT32 data);
	52	typedef UINT32 (*s3c24xx_gpio_port_r_func)( device_t *device, int port, UINT32 mask);
	53	typedef void (*s3c24xx_gpio_port_w_func)( device_t *device, int port, UINT32 mask, UINT32 data);
47	54
	55	typedef int (*s3c24xx_core_pin_r_func)( device_t *device, int pin);
	56	typedef void (*s3c24xx_core_pin_w_func)( device_t *device, int pin, int data);
	57
	58	typedef struct _s3c2410_interface_core s3c2410_interface_core;
	59	struct _s3c2410_interface_core
	60	{
	61	s3c24xx_core_pin_r_func pin_r;
	62	s3c24xx_core_pin_w_func pin_w;
	63	};
	64
48	65	typedef struct _s3c2410_interface_gpio s3c2410_interface_gpio;
49	66	struct _s3c2410_interface_gpio
50	67	{
r13744	r13745
90	107	typedef struct _s3c2410_interface s3c2410_interface;
91	108	struct _s3c2410_interface
92	109	{
	110	s3c2410_interface_core core;
93	111	s3c2410_interface_gpio gpio;
94	112	s3c2410_interface_i2c i2c;
95	113	s3c2410_interface_adc adc;
r13744	r13745
461	479	#define S3C24XX_GPIO_PORT_G S3C2410_GPIO_PORT_G
462	480	#define S3C24XX_GPIO_PORT_H S3C2410_GPIO_PORT_H
463	481
	482	#define S3C24XX_CORE_PIN_NCON S3C2410_CORE_PIN_NCON
	483	#define S3C24XX_CORE_PIN_OM0  S3C2410_CORE_PIN_OM0
	484	#define S3C24XX_CORE_PIN_OM1  S3C2410_CORE_PIN_OM1
	485
	486	#define S3C24XX_UART_COUNT  3
	487	#define S3C24XX_DMA_COUNT   4
	488	#define S3C24XX_SPI_COUNT   2
	489
464	490	/*******************************************************************************
465	491	TYPE DEFINITIONS
466	492	*******************************************************************************/
r13744	r13745
618	644	UINT32 gpadat;
619	645	UINT32 pad_08;
620	646	UINT32 pad_0c;
621		UINT32 gpbbon;
	647	UINT32 gpbcon;
622	648	UINT32 gpbdat;
623	649	UINT32 gpbup;
624	650	UINT32 pad_1c;
r13744	r13745
765	791	{
766	792	s3c24xx_nand_regs_t regs;
767	793	UINT8 mecc[3];
768		int pos;
	794	int ecc_pos, data_count;
769	795	} s3c24xx_nand_t;
770	796
771	797	typedef struct
r13744	r13745
839	865	typedef struct
840	866	{
841	867	const s3c2410_interface *iface;
	868	UINT8 steppingstone[4*1024];
842	869	s3c24xx_memcon_t memcon;
843	870	s3c24xx_usbhost_t usbhost;
844	871	s3c24xx_irq_t irq;
845		s3c24xx_dma_t dma[4];
	872	s3c24xx_dma_t dma[S3C24XX_DMA_COUNT];
846	873	s3c24xx_clkpow_t clkpow;
847	874	s3c24xx_lcd_t lcd;
848	875	s3c24xx_lcdpal_t lcdpal;
849	876	s3c24xx_nand_t nand;
850		s3c24xx_uart_t uart[3];
	877	s3c24xx_uart_t uart[S3C24XX_UART_COUNT];
851	878	s3c24xx_pwm_t pwm;
852	879	s3c24xx_usbdev_t usbdev;
853	880	s3c24xx_wdt_t wdt;
r13744	r13745
856	883	s3c24xx_gpio_t gpio;
857	884	s3c24xx_rtc_t rtc;
858	885	s3c24xx_adc_t adc;
859		s3c24xx_spi_t spi[2];
	886	s3c24xx_spi_t spi[S3C24XX_SPI_COUNT];
860	887	s3c24xx_sdi_t sdi;
861	888	} s3c24xx_t;
862	889

src/emu/machine/s3c2440.h

r13744	r13745
33	33	S3C2440_GPIO_PORT_J
34	34	};
35	35
	36	enum
	37	{
	38	S3C2440_CORE_PIN_NCON = 0,
	39	S3C2440_CORE_PIN_OM0,
	40	S3C2440_CORE_PIN_OM1
	41	};
	42
36	43	DECLARE_LEGACY_DEVICE(S3C2440, s3c2440);
37	44
38	45	/*******************************************************************************
39	46	TYPE DEFINITIONS
40	47	*******************************************************************************/
41	48
42		typedef UINT32 (*s3c24xx_gpio_port_r_func)( device_t *device, int port);
43		typedef void (*s3c24xx_gpio_port_w_func)( device_t *device, int port, UINT32 data);
	49	typedef UINT32 (*s3c24xx_gpio_port_r_func)( device_t *device, int port, UINT32 mask);
	50	typedef void (*s3c24xx_gpio_port_w_func)( device_t *device, int port, UINT32 mask, UINT32 data);
44	51
	52	typedef int (*s3c24xx_core_pin_r_func)( device_t *device, int pin);
	53	typedef void (*s3c24xx_core_pin_w_func)( device_t *device, int pin, int data);
	54
	55	typedef struct _s3c2440_interface_core s3c2440_interface_core;
	56	struct _s3c2440_interface_core
	57	{
	58	s3c24xx_core_pin_r_func pin_r;
	59	s3c24xx_core_pin_w_func pin_w;
	60	};
	61
45	62	typedef struct _s3c2440_interface_gpio s3c2440_interface_gpio;
46	63	struct _s3c2440_interface_gpio
47	64	{
r13744	r13745
87	104	typedef struct _s3c2440_interface s3c2440_interface;
88	105	struct _s3c2440_interface
89	106	{
	107	s3c2440_interface_core core;
90	108	s3c2440_interface_gpio gpio;
91	109	s3c2440_interface_i2c i2c;
92	110	s3c2440_interface_adc adc;
r13744	r13745
489	507	#define S3C24XX_GPIO_PORT_H S3C2440_GPIO_PORT_H
490	508	#define S3C24XX_GPIO_PORT_J S3C2440_GPIO_PORT_J
491	509
	510	#define S3C24XX_CORE_PIN_NCON S3C2440_CORE_PIN_NCON
	511	#define S3C24XX_CORE_PIN_OM0  S3C2440_CORE_PIN_OM0
	512	#define S3C24XX_CORE_PIN_OM1  S3C2440_CORE_PIN_OM1
	513
	514	#define S3C24XX_UART_COUNT  3
	515	#define S3C24XX_DMA_COUNT   4
	516	#define S3C24XX_SPI_COUNT   2
	517
492	518	/*******************************************************************************
493	519	TYPE DEFINITIONS
494	520	*******************************************************************************/
r13744	r13745
663	689	UINT32 gpadat;
664	690	UINT32 pad_08;
665	691	UINT32 pad_0c;
666		UINT32 gpbbon;
	692	UINT32 gpbcon;
667	693	UINT32 gpbdat;
668	694	UINT32 gpbup;
669	695	UINT32 pad_1c;
r13744	r13745
824	850	s3c24xx_nand_regs_t regs;
825	851	UINT8 mecc[4];
826	852	UINT8 secc[2];
827		int pos;
	853	int ecc_pos, data_count;
828	854	} s3c24xx_nand_t;
829	855
830	856	typedef struct
r13744	r13745
907	933	typedef struct
908	934	{
909	935	const s3c2440_interface *iface;
	936	UINT8 steppingstone[4*1024];
910	937	s3c24xx_memcon_t memcon;
911	938	s3c24xx_usbhost_t usbhost;
912	939	s3c24xx_irq_t irq;
913		s3c24xx_dma_t dma[4];
	940	s3c24xx_dma_t dma[S3C24XX_DMA_COUNT];
914	941	s3c24xx_clkpow_t clkpow;
915	942	s3c24xx_lcd_t lcd;
916	943	s3c24xx_lcdpal_t lcdpal;
917	944	s3c24xx_nand_t nand;
918	945	s3c24xx_cam_t cam;
919		s3c24xx_uart_t uart[3];
	946	s3c24xx_uart_t uart[S3C24XX_UART_COUNT];
920	947	s3c24xx_pwm_t pwm;
921	948	s3c24xx_usbdev_t usbdev;
922	949	s3c24xx_wdt_t wdt;
r13744	r13745
925	952	s3c24xx_gpio_t gpio;
926	953	s3c24xx_rtc_t rtc;
927	954	s3c24xx_adc_t adc;
928		s3c24xx_spi_t spi[2];
	955	s3c24xx_spi_t spi[S3C24XX_SPI_COUNT];
929	956	s3c24xx_sdi_t sdi;
930	957	s3c24xx_ac97_t ac97;
931	958	} s3c24xx_t;

src/emu/machine/s3c24xx.c

r13744	r13745
121	121
122	122	static void s3c24xx_reset( device_t *device)
123	123	{
124		fatalerror( "s3c24xx_reset\n");
	124	device_t *cpu = device->machine().device("maincpu");
	125	verboselog( device->machine(), 1, "reset\n");
	126	cpu->reset();
	127	device->reset();
125	128	}
126	129
	130	INLINE int iface_core_pin_r( device_t *device, int pin)
	131	{
	132	s3c24xx_t *s3c24xx = get_token( device);
	133	if (s3c24xx->iface->core.pin_r)
	134	{
	135	return (s3c24xx->iface->core.pin_r)( device, pin);
	136	}
	137	else
	138	{
	139	return 0;
	140	}
	141	}
	142
127	143	/* LCD Controller */
128	144
	145	static void s3c24xx_lcd_reset( device_t *device)
	146	{
	147	s3c24xx_t *s3c24xx = get_token( device);
	148	s3c24xx_lcd_t *lcd = &s3c24xx->lcd;
	149	memset( &lcd->regs, 0, sizeof( lcd->regs));
	150	#if defined(DEVICE_S3C2410)
	151	lcd->regs.lcdintmsk = 3;
	152	lcd->regs.lpcsel = 4;
	153	#elif defined(DEVICE_S3C2440)
	154	lcd->regs.lcdintmsk = 3;
	155	lcd->regs.tconsel = 0x0F84;
	156	#endif
	157	lcd->vramaddr_cur = lcd->vramaddr_max = 0;
	158	lcd->offsize = 0;
	159	lcd->pagewidth_cur = lcd->pagewidth_max = 0;
	160	lcd->bppmode = 0;
	161	lcd->bswp = lcd->hwswp = 0;
	162	lcd->vpos = lcd->hpos = 0;
	163	lcd->framerate = 0;
	164	lcd->tpal = 0;
	165	lcd->hpos_min = lcd->hpos_max = lcd->vpos_min = lcd->vpos_max = 0;
	166	lcd->dma_data = lcd->dma_bits = 0;
	167	lcd->timer->adjust( attotime::never);
	168	}
	169
129	170	static rgb_t s3c24xx_get_color_tft_16( device_t *device, UINT16 data)
130	171	{
131	172	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
225	266	s3c24xx->lcd.offsize = BITS( s3c24xx->lcd.regs.lcdsaddr3, 21, 11);
226	267	s3c24xx->lcd.pagewidth_cur = 0;
227	268	s3c24xx->lcd.pagewidth_max = BITS( s3c24xx->lcd.regs.lcdsaddr3, 10, 0);
	269	if (s3c24xx->lcd.pagewidth_max == 0)
	270	{
	271	if (s3c24xx->lcd.bppmode == S3C24XX_BPPMODE_STN_12_P)
	272	{
	273	s3c24xx->lcd.pagewidth_max = (s3c24xx->lcd.hpos_max - s3c24xx->lcd.hpos_min + 1) / 16 * 12;
	274	}
	275	}
228	276	verboselog( device->machine(), 3, "LCD - vramaddr %08X %08X offsize %08X pagewidth %08X\n", s3c24xx->lcd.vramaddr_cur, s3c24xx->lcd.vramaddr_max, s3c24xx->lcd.offsize, s3c24xx->lcd.pagewidth_max);
229	277	s3c24xx->lcd.dma_data = 0;
230	278	s3c24xx->lcd.dma_bits = 0;
r13744	r13745
233	281	static void s3c24xx_lcd_dma_init( device_t *device)
234	282	{
235	283	s3c24xx_t *s3c24xx = get_token( device);
	284	s3c24xx->lcd.bppmode = BITS( s3c24xx->lcd.regs.lcdcon1, 4, 1);
236	285	s3c24xx_lcd_dma_reload( device);
237		s3c24xx->lcd.bppmode = BITS( s3c24xx->lcd.regs.lcdcon1, 4, 1);
238	286	s3c24xx->lcd.bswp = BIT( s3c24xx->lcd.regs.lcdcon5, 1);
239	287	s3c24xx->lcd.hwswp = BIT( s3c24xx->lcd.regs.lcdcon5, 0);
240	288	s3c24xx->lcd.tpal = s3c24xx->lcd.regs.tpal;
r13744	r13745
761	809	static UINT32 s3c24xx_video_update( device_t *device, screen_device *screen, bitmap_t *bitmap, const rectangle *cliprect)
762	810	{
763	811	s3c24xx_t *s3c24xx = get_token( device);
764		if (s3c24xx->lcd.framerate >= 1195)
	812	if (s3c24xx->lcd.regs.lcdcon1 & (1 << 0))
765	813	{
766		bitmap_blend( bitmap, s3c24xx->lcd.bitmap[0], s3c24xx->lcd.bitmap[1]);
767		copybitmap( s3c24xx->lcd.bitmap[1], s3c24xx->lcd.bitmap[0], 0, 0, 0, 0, cliprect);
	814	if (s3c24xx->lcd.framerate >= 1195)
	815	{
	816	bitmap_blend( bitmap, s3c24xx->lcd.bitmap[0], s3c24xx->lcd.bitmap[1]);
	817	copybitmap( s3c24xx->lcd.bitmap[1], s3c24xx->lcd.bitmap[0], 0, 0, 0, 0, cliprect);
	818	}
	819	else
	820	{
	821	copybitmap( bitmap, s3c24xx->lcd.bitmap[0], 0, 0, 0, 0, cliprect);
	822	}
	823	s3c24xx_lcd_dma_init( device);
768	824	}
769		else
770		{
771		copybitmap( bitmap, s3c24xx->lcd.bitmap[0], 0, 0, 0, 0, cliprect);
772		}
773		s3c24xx_lcd_dma_init( device);
774	825	return 0;
775	826	}
776	827
r13744	r13745
809	860	return data;
810	861	}
811	862
812		static void s3c24xx_lcd_configure_tft( device_t *device)
	863	static int s3c24xx_lcd_configure_tft( device_t *device)
813	864	{
814	865	s3c24xx_t *s3c24xx = get_token( device);
815	866	screen_device *screen = device->machine().primary_screen;
r13744	r13745
847	898	s3c24xx->lcd.vpos_min = (vspw + 1) + (vbpd + 1);
848	899	s3c24xx->lcd.vpos_max = s3c24xx->lcd.vpos_min + (lineval + 1) - 1;
849	900	screen->configure( width, height, visarea, HZ_TO_ATTOSECONDS( s3c24xx->lcd.framerate));
	901	return TRUE;
850	902	}
851	903
852		static void s3c24xx_lcd_configure_stn( device_t *device)
	904	static int s3c24xx_lcd_configure_stn( device_t *device)
853	905	{
854	906	s3c24xx_t *s3c24xx = get_token( device);
855	907	screen_device *screen = device->machine().primary_screen;
r13744	r13745
868	920	wlh = BITS( s3c24xx->lcd.regs.lcdcon4, 1, 0);
869	921	hclk = s3c24xx_get_hclk( device);
870	922	verboselog( device->machine(), 3, "LCD - pnrmode %d bppmode %d clkval %d lineval %d wdly %d hozval %d lineblank %d wlh %d hclk %d\n", pnrmode, bppmode, clkval, lineval, wdly, hozval, lineblank, wlh, hclk);
	923	if (clkval == 0)
	924	{
	925	return FALSE;
	926	}
871	927	vclk = (double)(hclk / ((clkval + 0) * 2));
872	928	verboselog( device->machine(), 3, "LCD - vclk %f\n", vclk);
873	929	framerate = 1 / (((1 / vclk) * (hozval + 1) + (1 / hclk) * ((1 << (4 + wlh)) + (1 << (4 + wdly)) + (lineblank * 8))) * (lineval + 1));
r13744	r13745
892	948	s3c24xx->lcd.vpos_min = 0;
893	949	s3c24xx->lcd.vpos_max = height - 1;
894	950	screen->configure( width, height, visarea, HZ_TO_ATTOSECONDS( s3c24xx->lcd.framerate));
	951	return TRUE;
895	952	}
896	953
897		static void s3c24xx_lcd_configure( device_t *device)
	954	static int s3c24xx_lcd_configure( device_t *device)
898	955	{
899	956	s3c24xx_t *s3c24xx = get_token( device);
900	957	UINT32 bppmode;
r13744	r13745
902	959	bppmode = BITS( s3c24xx->lcd.regs.lcdcon1, 4, 1);
903	960	if ((bppmode & (1 << 3)) == 0)
904	961	{
905		s3c24xx_lcd_configure_stn( device);
	962	return s3c24xx_lcd_configure_stn( device);
906	963	}
907	964	else
908	965	{
909		s3c24xx_lcd_configure_tft( device);
	966	return s3c24xx_lcd_configure_tft( device);
910	967	}
911	968	}
912	969
r13744	r13745
915	972	s3c24xx_t *s3c24xx = get_token( device);
916	973	screen_device *screen = device->machine().primary_screen;
917	974	verboselog( device->machine(), 1, "LCD start\n");
918		s3c24xx_lcd_configure( device);
919		s3c24xx_lcd_dma_init( device);
920		s3c24xx->lcd.timer->adjust( screen->time_until_pos( s3c24xx->lcd.vpos_min, s3c24xx->lcd.hpos_min));
	975	if (s3c24xx_lcd_configure( device))
	976	{
	977	s3c24xx_lcd_dma_init( device);
	978	s3c24xx->lcd.timer->adjust( screen->time_until_pos( s3c24xx->lcd.vpos_min, s3c24xx->lcd.hpos_min));
	979	}
921	980	}
922	981
923	982	static void s3c24xx_lcd_stop( device_t *device)
r13744	r13745
983	1042
984	1043	/* Clock & Power Management */
985	1044
	1045	static void s3c24xx_clkpow_reset( device_t *device)
	1046	{
	1047	s3c24xx_t *s3c24xx = get_token( device);
	1048	s3c24xx_clkpow_t *clkpow = &s3c24xx->clkpow;
	1049	memset( &clkpow->regs, 0, sizeof( clkpow->regs));
	1050	#if defined(DEVICE_S3C2400)
	1051	clkpow->regs.locktime = 0x00FFFFFF;
	1052	clkpow->regs.mpllcon  = 0x0005C080;
	1053	clkpow->regs.upllcon  = 0x00028080;
	1054	clkpow->regs.clkcon   = 0x0000FFF8;
	1055	#elif defined(DEVICE_S3C2410)
	1056	clkpow->regs.locktime = 0x00FFFFFF;
	1057	clkpow->regs.mpllcon  = 0x0005C080;
	1058	clkpow->regs.upllcon  = 0x00028080;
	1059	clkpow->regs.clkcon   = 0x0007FFF0;
	1060	#elif defined(DEVICE_S3C2440)
	1061	clkpow->regs.locktime = 0xFFFFFFFF;
	1062	clkpow->regs.mpllcon  = 0x00096030;
	1063	clkpow->regs.upllcon  = 0x0004D030;
	1064	clkpow->regs.clkcon   = 0x00FFFFF0;
	1065	#endif
	1066	clkpow->regs.clkslow = 4;
	1067	}
	1068
986	1069	static UINT32 s3c24xx_get_fclk( device_t *device)
987	1070	{
988	1071	s3c24xx_t *s3c24xx = get_token( device);
989		UINT32 data, mdiv, pdiv, sdiv;
990		data = s3c24xx->clkpow.regs.mpllcon;
991		mdiv = BITS( data, 19, 12);
992		pdiv = BITS( data, 9, 4);
993		sdiv = BITS( data, 1, 0);
	1072	UINT32 mpllcon, clkslow, mdiv, pdiv, sdiv, fclk;
	1073	double temp1, temp2;
	1074	mpllcon = s3c24xx->clkpow.regs.mpllcon;
	1075	mdiv = BITS( mpllcon, 19, 12);
	1076	pdiv = BITS( mpllcon, 9, 4);
	1077	sdiv = BITS( mpllcon, 1, 0);
994	1078	#if defined(DEVICE_S3C2400) || defined(DEVICE_S3C2410)
995		return (UINT32)((double)(1 * (mdiv + 8) * device->clock()) / (double)((pdiv + 2) * (1 << sdiv)));
	1079	temp1 = 1 * (mdiv + 8) * (double)device->clock();
996	1080	#else
997		return (UINT32)((double)(2 * (mdiv + 8) * device->clock()) / (double)((pdiv + 2) * (1 << sdiv)));
	1081	temp1 = 2 * (mdiv + 8) * (double)device->clock();
998	1082	#endif
	1083	temp2 = (double)((pdiv + 2) * (1 << sdiv));
	1084	fclk = (UINT32)(temp1 / temp2);
	1085	clkslow = s3c24xx->clkpow.regs.clkslow;
	1086	if (BIT( clkslow, 4) == 1)
	1087	{
	1088	UINT32 slow_val = BITS( clkslow, 2, 0);
	1089	if (slow_val > 0)
	1090	{
	1091	fclk = fclk / (2 * slow_val);
	1092	}
	1093	}
	1094	return fclk;
999	1095	}
1000	1096
1001	1097	static UINT32 s3c24xx_get_hclk( device_t *device)
r13744	r13745
1042	1138	device->machine().device( "maincpu")->set_unscaled_clock(s3c24xx_get_fclk( device) * CLOCK_MULTIPLIER);
1043	1139	}
1044	1140	break;
	1141	case S3C24XX_CLKSLOW :
	1142	{
	1143	verboselog( device->machine(), 5, "CLKPOW - fclk %d hclk %d pclk %d\n", s3c24xx_get_fclk( device), s3c24xx_get_hclk( device), s3c24xx_get_pclk( device));
	1144	device->machine().device( "maincpu")->set_unscaled_clock(s3c24xx_get_fclk( device) * CLOCK_MULTIPLIER);
	1145	}
	1146	break;
1045	1147	}
1046	1148	}
1047	1149
1048	1150	/* Interrupt Controller */
1049	1151
	1152	static void s3c24xx_irq_reset( device_t *device)
	1153	{
	1154	s3c24xx_t *s3c24xx = get_token( device);
	1155	s3c24xx_irq_t *irq = &s3c24xx->irq;
	1156	memset( &irq->regs, 0, sizeof( irq->regs));
	1157	irq->line_irq = irq->line_fiq = CLEAR_LINE;
	1158	irq->regs.intmsk = 0xFFFFFFFF;
	1159	irq->regs.priority = 0x7F;
	1160	#if defined(DEVICE_S3C2410)
	1161	irq->regs.intsubmsk = 0x07FF;
	1162	#elif defined(DEVICE_S3C2440)
	1163	irq->regs.intsubmsk = 0xFFFF;
	1164	#endif
	1165	}
	1166
1050	1167	static void s3c24xx_check_pending_irq( device_t *device)
1051	1168	{
1052	1169	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
1056	1173	if (temp != 0)
1057	1174	{
1058	1175	UINT32 int_type = 0;
	1176	verboselog( device->machine(), 5, "srcpnd %08X intmsk %08X intmod %08X\n", s3c24xx->irq.regs.srcpnd, s3c24xx->irq.regs.intmsk, s3c24xx->irq.regs.intmod);
1059	1177	while ((temp & 1) == 0)
1060	1178	{
1061	1179	int_type++;
1062	1180	temp = temp >> 1;
1063	1181	}
	1182	verboselog( device->machine(), 5, "intpnd set bit %d\n", int_type);
1064	1183	s3c24xx->irq.regs.intpnd |= (1 << int_type);
1065	1184	s3c24xx->irq.regs.intoffset = int_type;
1066	1185	if (s3c24xx->irq.line_irq != ASSERT_LINE)
1067	1186	{
	1187	verboselog( device->machine(), 5, "ARM7_IRQ_LINE -> ASSERT_LINE\n");
1068	1188	cputag_set_input_line( device->machine(), "maincpu", ARM7_IRQ_LINE, ASSERT_LINE);
1069	1189	s3c24xx->irq.line_irq = ASSERT_LINE;
1070	1190	}
r13744	r13745
1073	1193	{
1074	1194	if (s3c24xx->irq.line_irq != CLEAR_LINE)
1075	1195	{
	1196	verboselog( device->machine(), 5, "srcpnd %08X intmsk %08X intmod %08X\n", s3c24xx->irq.regs.srcpnd, s3c24xx->irq.regs.intmsk, s3c24xx->irq.regs.intmod);
	1197	verboselog( device->machine(), 5, "ARM7_IRQ_LINE -> CLEAR_LINE\n");
1076	1198	cputag_set_input_line( device->machine(), "maincpu", ARM7_IRQ_LINE, CLEAR_LINE);
1077	1199	s3c24xx->irq.line_irq = CLEAR_LINE;
1078	1200	}
r13744	r13745
1089	1211	}
1090	1212	if (s3c24xx->irq.line_fiq != ASSERT_LINE)
1091	1213	{
	1214	verboselog( device->machine(), 5, "ARM7_FIRQ_LINE -> ASSERT_LINE\n");
1092	1215	cputag_set_input_line( device->machine(), "maincpu", ARM7_FIRQ_LINE, ASSERT_LINE);
1093	1216	s3c24xx->irq.line_fiq = ASSERT_LINE;
1094	1217	}
r13744	r13745
1097	1220	{
1098	1221	if (s3c24xx->irq.line_fiq != CLEAR_LINE)
1099	1222	{
	1223	verboselog( device->machine(), 5, "ARM7_FIRQ_LINE -> CLEAR_LINE\n");
1100	1224	cputag_set_input_line( device->machine(), "maincpu", ARM7_FIRQ_LINE, CLEAR_LINE);
1101	1225	s3c24xx->irq.line_fiq = CLEAR_LINE;
1102	1226	}
r13744	r13745
1196	1320	case S3C24XX_SRCPND :
1197	1321	{
1198	1322	s3c24xx->irq.regs.srcpnd = (old_value & ~data); // clear only the bit positions of SRCPND corresponding to those set to one in the data
	1323	s3c24xx->irq.regs.intoffset = 0; // "This bit can be cleared automatically by clearing SRCPND and INTPND."
1199	1324	s3c24xx_check_pending_irq( device);
1200	1325	}
1201	1326	break;
r13744	r13745
1207	1332	case S3C24XX_INTPND :
1208	1333	{
1209	1334	s3c24xx->irq.regs.intpnd = (old_value & ~data); // clear only the bit positions of INTPND corresponding to those set to one in the data
	1335	s3c24xx->irq.regs.intoffset = 0; // "This bit can be cleared automatically by clearing SRCPND and INTPND."
1210	1336	}
1211	1337	break;
1212	1338	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
r13744	r13745
1227	1353
1228	1354	/* PWM Timer */
1229	1355
	1356	static void s3c24xx_pwm_reset( device_t *device)
	1357	{
	1358	s3c24xx_t *s3c24xx = get_token( device);
	1359	s3c24xx_pwm_t *pwm = &s3c24xx->pwm;
	1360	memset( &pwm->regs, 0, sizeof( pwm->regs));
	1361	for (int i = 0; i < 5; i++)
	1362	{
	1363	pwm->timer[i]->adjust( attotime::never);
	1364	}
	1365	}
	1366
1230	1367	static UINT16 s3c24xx_pwm_calc_observation( device_t *device, int ch)
1231	1368	{
1232	1369	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
1440	1577
1441	1578	/* DMA */
1442	1579
	1580	static void s3c24xx_dma_reset( device_t *device)
	1581	{
	1582	s3c24xx_t *s3c24xx = get_token( device);
	1583	for (int i = 0; i < S3C24XX_DMA_COUNT; i++)
	1584	{
	1585	s3c24xx_dma_t *dma = &s3c24xx->dma[i];
	1586	memset( &dma->regs, 0, sizeof( dma->regs));
	1587	dma->timer->adjust( attotime::never);
	1588	}
	1589	}
	1590
1443	1591	static void s3c24xx_dma_reload( device_t *device, int ch)
1444	1592	{
1445	1593	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
1683	1831
1684	1832	/* I/O Port */
1685	1833
1686		INLINE UINT32 iface_gpio_port_r( device_t *device, int port)
	1834	static void s3c24xx_gpio_reset( device_t *device)
1687	1835	{
1688	1836	s3c24xx_t *s3c24xx = get_token( device);
	1837	s3c24xx_gpio_t *gpio = &s3c24xx->gpio;
	1838	memset( &gpio->regs, 0, sizeof( gpio->regs));
	1839	#if defined(DEVICE_S3C2400)
	1840	gpio->regs.gpacon = 0x0003FFFF;
	1841	gpio->regs.gpbcon = 0xAAAAAAAA;
	1842	gpio->regs.gpdup = 0x0620;
	1843	gpio->regs.gpeup = 0x0003;
	1844	#elif defined(DEVICE_S3C2410)
	1845	gpio->regs.gpacon = 0x007FFFFF;
	1846	gpio->regs.gpgup = 0xF800;
	1847	gpio->regs.misccr = 0x00010330;
	1848	gpio->regs.eintmask = 0x00FFFFF0;
	1849	gpio->regs.gstatus1 = 0x32410002;
	1850	#elif defined(DEVICE_S3C2440)
	1851	gpio->regs.gpacon = 0x00FFFFFF;
	1852	gpio->regs.gpgup = 0xFC00;
	1853	gpio->regs.misccr = 0x00010020;
	1854	gpio->regs.eintmask = 0x000FFFFF;
	1855	gpio->regs.gstatus1 = 0x32440001;
	1856	#endif
	1857	gpio->regs.gpdup = 0xF000;
	1858	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	1859	gpio->regs.gstatus2 = 1 << 0; // Boot is caused by power on reset
	1860	#endif
	1861	}
	1862
	1863	INLINE UINT32 iface_gpio_port_r( device_t *device, int port, UINT32 mask)
	1864	{
	1865	s3c24xx_t *s3c24xx = get_token( device);
1689	1866	if (s3c24xx->iface->gpio.port_r)
1690	1867	{
1691		return (s3c24xx->iface->gpio.port_r)( device, port);
	1868	return (s3c24xx->iface->gpio.port_r)( device, port, mask);
1692	1869	}
1693	1870	else
1694	1871	{
r13744	r13745
1696	1873	}
1697	1874	}
1698	1875
1699		INLINE void iface_gpio_port_w( device_t *device, int port, UINT32 data)
	1876	INLINE void iface_gpio_port_w( device_t *device, int port, UINT32 mask, UINT32 data)
1700	1877	{
1701	1878	s3c24xx_t *s3c24xx = get_token( device);
1702	1879	if (s3c24xx->iface->gpio.port_w)
1703	1880	{
1704		(s3c24xx->iface->gpio.port_w)( device, port, data);
	1881	(s3c24xx->iface->gpio.port_w)( device, port, mask, data);
1705	1882	}
1706	1883	}
1707	1884
	1885	static UINT16 s3c24xx_gpio_get_mask( UINT32 con, int val)
	1886	{
	1887	UINT16 mask = 0;
	1888	for (int i = 0; i < 16; i++)
	1889	{
	1890	if (((con >> (i << 1)) & 3) == val)
	1891	{
	1892	mask = mask | (1 << i);
	1893	}
	1894	}
	1895	return mask;
	1896	}
	1897
1708	1898	static READ32_DEVICE_HANDLER( s3c24xx_gpio_r )
1709	1899	{
1710	1900	s3c24xx_t *s3c24xx = get_token( device);
	1901	s3c24xx_gpio_t *gpio = &s3c24xx->gpio;
1711	1902	UINT32 data = ((UINT32*)&s3c24xx->gpio.regs)[offset];
1712	1903	switch (offset)
1713	1904	{
1714	1905	case S3C24XX_GPADAT :
1715	1906	{
1716		data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_A) & S3C24XX_GPADAT_MASK;
	1907	data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_A, 0) & S3C24XX_GPADAT_MASK;
1717	1908	}
1718	1909	break;
1719	1910	case S3C24XX_GPBDAT :
1720	1911	{
1721		data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_B) & S3C24XX_GPBDAT_MASK;
	1912	data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_B, s3c24xx_gpio_get_mask( gpio->regs.gpbcon, 0) & S3C24XX_GPBDAT_MASK) & S3C24XX_GPBDAT_MASK;
1722	1913	}
1723	1914	break;
1724	1915	case S3C24XX_GPCDAT :
1725	1916	{
1726		data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_C) & S3C24XX_GPCDAT_MASK;
	1917	data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_C, s3c24xx_gpio_get_mask( gpio->regs.gpccon, 0) & S3C24XX_GPCDAT_MASK) & S3C24XX_GPCDAT_MASK;
1727	1918	}
1728	1919	break;
1729	1920	case S3C24XX_GPDDAT :
1730	1921	{
1731		data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_D) & S3C24XX_GPDDAT_MASK;
	1922	data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_D, s3c24xx_gpio_get_mask( gpio->regs.gpdcon, 0) & S3C24XX_GPDDAT_MASK) & S3C24XX_GPDDAT_MASK;
1732	1923	}
1733	1924	break;
1734	1925	case S3C24XX_GPEDAT :
1735	1926	{
1736		data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_E) & S3C24XX_GPEDAT_MASK;
	1927	data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_E, s3c24xx_gpio_get_mask( gpio->regs.gpecon, 0) & S3C24XX_GPEDAT_MASK) & S3C24XX_GPEDAT_MASK;
1737	1928	}
1738	1929	break;
1739	1930	case S3C24XX_GPFDAT :
1740	1931	{
1741		data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_F) & S3C24XX_GPFDAT_MASK;
	1932	data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_F, s3c24xx_gpio_get_mask( gpio->regs.gpfcon, 0) & S3C24XX_GPFDAT_MASK) & S3C24XX_GPFDAT_MASK;
1742	1933	}
1743	1934	break;
1744	1935	case S3C24XX_GPGDAT :
1745	1936	{
1746		data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_G) & S3C24XX_GPGDAT_MASK;
	1937	data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_G, s3c24xx_gpio_get_mask( gpio->regs.gpgcon, 0) & S3C24XX_GPGDAT_MASK) & S3C24XX_GPGDAT_MASK;
1747	1938	}
1748	1939	break;
1749	1940	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
1750	1941	case S3C24XX_GPHDAT :
1751	1942	{
1752		data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_H) & S3C24XX_GPHDAT_MASK;
	1943	data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_H, s3c24xx_gpio_get_mask( gpio->regs.gphcon, 0) & S3C24XX_GPHDAT_MASK) & S3C24XX_GPHDAT_MASK;
1753	1944	}
1754	1945	break;
1755	1946	#endif
1756	1947	#if defined(DEVICE_S3C2440)
1757	1948	case S3C24XX_GPJDAT :
1758	1949	{
1759		data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_J) & S3C24XX_GPJDAT_MASK;
	1950	data = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_J, s3c24xx_gpio_get_mask( gpio->regs.gpjcon, 0) & S3C24XX_GPJDAT_MASK) & S3C24XX_GPJDAT_MASK;
1760	1951	}
1761	1952	break;
1762	1953	#endif
r13744	r13745
1768	1959	static WRITE32_DEVICE_HANDLER( s3c24xx_gpio_w )
1769	1960	{
1770	1961	s3c24xx_t *s3c24xx = get_token( device);
	1962	s3c24xx_gpio_t *gpio = &s3c24xx->gpio;
1771	1963	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
1772	1964	UINT32 old_value = ((UINT32*)&s3c24xx->gpio.regs)[offset];
1773	1965	#endif
r13744	r13745
1777	1969	{
1778	1970	case S3C24XX_GPADAT :
1779	1971	{
1780		iface_gpio_port_w( device, S3C24XX_GPIO_PORT_A, data & S3C24XX_GPADAT_MASK);
	1972	iface_gpio_port_w( device, S3C24XX_GPIO_PORT_A, gpio->regs.gpacon ^ 0xFFFFFFFF, data & S3C24XX_GPADAT_MASK);
1781	1973	}
1782	1974	break;
1783	1975	case S3C24XX_GPBDAT :
1784	1976	{
1785		iface_gpio_port_w( device, S3C24XX_GPIO_PORT_B, data & S3C24XX_GPBDAT_MASK);
	1977	iface_gpio_port_w( device, S3C24XX_GPIO_PORT_B, s3c24xx_gpio_get_mask( gpio->regs.gpbcon, 1) & S3C24XX_GPBDAT_MASK, data & S3C24XX_GPBDAT_MASK);
1786	1978	}
1787	1979	break;
1788	1980	case S3C24XX_GPCDAT :
1789	1981	{
1790		iface_gpio_port_w( device, S3C24XX_GPIO_PORT_C, data & S3C24XX_GPCDAT_MASK);
	1982	iface_gpio_port_w( device, S3C24XX_GPIO_PORT_C, s3c24xx_gpio_get_mask( gpio->regs.gpccon, 1) & S3C24XX_GPCDAT_MASK, data & S3C24XX_GPCDAT_MASK);
1791	1983	}
1792	1984	break;
1793	1985	case S3C24XX_GPDDAT :
1794	1986	{
1795		iface_gpio_port_w( device, S3C24XX_GPIO_PORT_D, data & S3C24XX_GPDDAT_MASK);
	1987	iface_gpio_port_w( device, S3C24XX_GPIO_PORT_D, s3c24xx_gpio_get_mask( gpio->regs.gpdcon, 1) & S3C24XX_GPDDAT_MASK, data & S3C24XX_GPDDAT_MASK);
1796	1988	}
1797	1989	break;
1798	1990	case S3C24XX_GPEDAT :
1799	1991	{
1800		iface_gpio_port_w( device, S3C24XX_GPIO_PORT_E, data & S3C24XX_GPEDAT_MASK);
	1992	iface_gpio_port_w( device, S3C24XX_GPIO_PORT_E, s3c24xx_gpio_get_mask( gpio->regs.gpecon, 1) & S3C24XX_GPEDAT_MASK, data & S3C24XX_GPEDAT_MASK);
1801	1993	}
1802	1994	break;
1803	1995	case S3C24XX_GPFDAT :
1804	1996	{
1805		iface_gpio_port_w( device, S3C24XX_GPIO_PORT_F, data & S3C24XX_GPFDAT_MASK);
	1997	iface_gpio_port_w( device, S3C24XX_GPIO_PORT_F, s3c24xx_gpio_get_mask( gpio->regs.gpfcon, 1) & S3C24XX_GPFDAT_MASK, data & S3C24XX_GPFDAT_MASK);
1806	1998	}
1807	1999	break;
1808	2000	case S3C24XX_GPGDAT :
1809	2001	{
1810		iface_gpio_port_w( device, S3C24XX_GPIO_PORT_G, data & S3C24XX_GPGDAT_MASK);
	2002	iface_gpio_port_w( device, S3C24XX_GPIO_PORT_G, s3c24xx_gpio_get_mask( gpio->regs.gpgcon, 1) & S3C24XX_GPGDAT_MASK, data & S3C24XX_GPGDAT_MASK);
1811	2003	}
1812	2004	break;
1813	2005	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
1814	2006	case S3C24XX_GPHDAT :
1815	2007	{
1816		iface_gpio_port_w( device, S3C24XX_GPIO_PORT_H, data & S3C24XX_GPHDAT_MASK);
	2008	iface_gpio_port_w( device, S3C24XX_GPIO_PORT_H, s3c24xx_gpio_get_mask( gpio->regs.gphcon, 1) & S3C24XX_GPHDAT_MASK, data & S3C24XX_GPHDAT_MASK);
1817	2009	}
1818	2010	break;
1819	2011	case S3C24XX_EINTPEND :
r13744	r13745
1827	2019	s3c24xx_check_pending_eint( device);
1828	2020	}
1829	2021	break;
	2022	case S3C24XX_GSTATUS2 :
	2023	{
	2024	s3c24xx->gpio.regs.gstatus2 = (old_value & ~data) & 7; // "The setting is cleared by writing '1' to this bit"
	2025	}
	2026	break;
1830	2027	#endif
1831	2028	#if defined(DEVICE_S3C2440)
1832	2029	case S3C24XX_GPJDAT :
1833	2030	{
1834		iface_gpio_port_w( device, S3C24XX_GPIO_PORT_J, data & S3C24XX_GPJDAT_MASK);
	2031	iface_gpio_port_w( device, S3C24XX_GPIO_PORT_J, s3c24xx_gpio_get_mask( gpio->regs.gpjcon, 1) & S3C24XX_GPJDAT_MASK, data & S3C24XX_GPJDAT_MASK);
1835	2032	}
1836	2033	break;
1837	2034	#endif
r13744	r13745
1840	2037
1841	2038	/* Memory Controller */
1842	2039
	2040	static void s3c24xx_memcon_reset( device_t *device)
	2041	{
	2042	s3c24xx_t *s3c24xx = get_token( device);
	2043	s3c24xx_memcon_t *memcon = &s3c24xx->memcon;
	2044	memset( &memcon->regs, 0, sizeof( memcon->regs));
	2045	memcon->regs.data[0x04/4] = 0x00000700;
	2046	memcon->regs.data[0x08/4] = 0x00000700;
	2047	memcon->regs.data[0x0C/4] = 0x00000700;
	2048	memcon->regs.data[0x10/4] = 0x00000700;
	2049	memcon->regs.data[0x14/4] = 0x00000700;
	2050	memcon->regs.data[0x18/4] = 0x00000700;
	2051	memcon->regs.data[0x1C/4] = 0x00018008;
	2052	memcon->regs.data[0x20/4] = 0x00018008;
	2053	memcon->regs.data[0x24/4] = 0x00AC0000;
	2054	}
	2055
1843	2056	static READ32_DEVICE_HANDLER( s3c24xx_memcon_r )
1844	2057	{
1845	2058	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
1857	2070
1858	2071	/* USB Host Controller */
1859	2072
	2073	static void s3c24xx_usb_host_reset( device_t *device)
	2074	{
	2075	s3c24xx_t *s3c24xx = get_token( device);
	2076	s3c24xx_usbhost_t *usbhost = &s3c24xx->usbhost;
	2077	memset( &usbhost->regs, 0, sizeof( usbhost->regs));
	2078	}
	2079
1860	2080	static READ32_DEVICE_HANDLER( s3c24xx_usb_host_r )
1861	2081	{
1862	2082	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
1869	2089	data = data & ~(1 << 0); // [bit 0] HostControllerReset
1870	2090	}
1871	2091	break;
	2092	// HcPeriodStart
	2093	case 0x40 / 4:
	2094	{
	2095	// "After a hardware reset, this field is cleared. This is then set by"
	2096	// "HCD during the HC initialization. The value is calculated"
	2097	// "roughly as 10% off from HcFmInterval.. A typical value will be 3E67h."
	2098	data = (data & ~0x00003FFF) | 0x3E67;
	2099	}
	2100	break;
	2101	// HcRhDescriptorA
	2102	case 0x48 / 4:
	2103	{
	2104	data = (data & ~0xFF) | 2; // number of ports
	2105	}
	2106	break;
	2107	// HcRhStatus
	2108	case 0x50 / 4:
	2109	{
	2110	data = data & ~(1 << 16); // "The Root Hub does not support the local power status feature; thus, this bit is always read as ‘0’."
	2111	}
	2112	break;
1872	2113	}
1873	2114	verboselog( device->machine(), 9, "(USB H) %08X -> %08X\n", S3C24XX_BASE_USBHOST + (offset << 2), data);
1874	2115	return data;
r13744	r13745
1883	2124
1884	2125	/* UART */
1885	2126
	2127	static void s3c24xx_uart_reset( device_t *device)
	2128	{
	2129	s3c24xx_t *s3c24xx = get_token( device);
	2130	for (int i = 0; i < S3C24XX_UART_COUNT; i++)
	2131	{
	2132	s3c24xx_uart_t *uart = &s3c24xx->uart[i];
	2133	memset( &uart->regs, 0, sizeof( uart->regs));
	2134	uart->regs.utrstat = 6;
	2135	}
	2136	}
	2137
1886	2138	static UINT32 s3c24xx_uart_r( device_t *device, UINT32 ch, UINT32 offset)
1887	2139	{
1888	2140	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
1911	2163	COMBINE_DATA(&((UINT32*)&s3c24xx->uart[ch].regs)[offset]);
1912	2164	switch (offset)
1913	2165	{
	2166	case S3C24XX_UFCON :
	2167	{
	2168	s3c24xx->uart[ch].regs.ufcon &= ~((1 << 2) | (1 << 1)); // bits 1 and 2 are auto-cleared after resetting FIFO
	2169	}
	2170	break;
1914	2171	case S3C24XX_UTXH :
1915	2172	{
1916	2173	UINT8 txdata = data & 0xFF;
r13744	r13745
1980	2237
1981	2238	/* USB Device */
1982	2239
	2240	static void s3c24xx_usb_device_reset( device_t *device)
	2241	{
	2242	s3c24xx_t *s3c24xx = get_token( device);
	2243	s3c24xx_usbdev_t *usbdev = &s3c24xx->usbdev;
	2244	memset( &usbdev->regs, 0, sizeof( usbdev->regs));
	2245	#if defined(DEVICE_S3C2400)
	2246	usbdev->regs.data[0x0C/4] = 0x033F;
	2247	usbdev->regs.data[0x14/4] = 0x000A;
	2248	usbdev->regs.data[0x24/4] = 0x0001;
	2249	usbdev->regs.data[0x44/4] = 0x0001;
	2250	usbdev->regs.data[0x54/4] = 0x0001;
	2251	usbdev->regs.data[0x64/4] = 0x0001;
	2252	usbdev->regs.data[0x74/4] = 0x0001;
	2253	usbdev->regs.data[0xB8/4] = 0x00FF;
	2254	#elif defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	2255	usbdev->regs.data[0x1C/4] = 0xFF;
	2256	usbdev->regs.data[0x2C/4] = 0x04;
	2257	usbdev->regs.data[0x40/4] = 0x01;
	2258	usbdev->regs.data[0x48/4] = 0x20;
	2259	#endif
	2260	}
	2261
1983	2262	static READ32_DEVICE_HANDLER( s3c24xx_usb_device_r )
1984	2263	{
1985	2264	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
1997	2276
1998	2277	/* Watchdog Timer */
1999	2278
	2279	static void s3c24xx_wdt_reset( device_t *device)
	2280	{
	2281	s3c24xx_t *s3c24xx = get_token( device);
	2282	s3c24xx_wdt_t *wdt = &s3c24xx->wdt;
	2283	memset( &wdt->regs, 0, sizeof( wdt->regs));
	2284	wdt->regs.wtcon = 0x8021;
	2285	wdt->regs.wtdat = 0x8000;
	2286	wdt->regs.wtcnt = 0x8000;
	2287	wdt->timer->adjust( attotime::never);
	2288	}
	2289
2000	2290	#if defined(DEVICE_S3C2410)
2001	2291
2002	2292	static UINT16 s3c24xx_wdt_calc_current_count( device_t *device)
r13744	r13745
2118	2408	if ((s3c24xx->wdt.regs.wtcon & (1 << 0)) != 0)
2119	2409	{
2120	2410	s3c24xx_reset( device);
	2411	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	2412	s3c24xx->gpio.regs.gstatus2 = 1 << 2; // Watchdog reset
	2413	#endif
2121	2414	}
2122	2415	}
2123	2416
2124	2417	/* IIC */
2125	2418
	2419	static void s3c24xx_iic_reset( device_t *device)
	2420	{
	2421	s3c24xx_t *s3c24xx = get_token( device);
	2422	s3c24xx_iic_t *iic = &s3c24xx->iic;
	2423	memset( &iic->regs, 0, sizeof( iic->regs));
	2424	iic->count = 0;
	2425	iic->timer->adjust( attotime::never);
	2426	}
	2427
2126	2428	INLINE void iface_i2c_scl_w( device_t *device, int state)
2127	2429	{
2128	2430	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
2360	2662
2361	2663	/* IIS */
2362	2664
	2665	static void s3c24xx_iis_reset( device_t *device)
	2666	{
	2667	s3c24xx_t *s3c24xx = get_token( device);
	2668	s3c24xx_iis_t *iis = &s3c24xx->iis;
	2669	memset( &iis->regs, 0, sizeof( iis->regs));
	2670	iis->fifo_index = 0;
	2671	iis->regs.iiscon = 0x0100;
	2672	iis->timer->adjust( attotime::never);
	2673	}
	2674
2363	2675	INLINE void iface_i2s_data_w( device_t *device, int ch, UINT16 data)
2364	2676	{
2365	2677	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
2470	2782
2471	2783	/* RTC */
2472	2784
2473		static void s3c24xx_rtc_init( device_t *device)
	2785	static void s3c24xx_rtc_reset( device_t *device)
2474	2786	{
2475	2787	s3c24xx_t *s3c24xx = get_token( device);
2476		s3c24xx->rtc.regs.bcdsec = dec_2_bcd( 0);
2477		s3c24xx->rtc.regs.bcdmin = dec_2_bcd( 0);
2478		s3c24xx->rtc.regs.bcdhour = dec_2_bcd( 0);
2479		s3c24xx->rtc.regs.bcdday = dec_2_bcd( 1);
2480		s3c24xx->rtc.regs.bcddow = dec_2_bcd( 1);
2481		s3c24xx->rtc.regs.bcdmon = dec_2_bcd( 1);
2482		s3c24xx->rtc.regs.bcdyear = dec_2_bcd( 4);
	2788	s3c24xx_rtc_t *rtc = &s3c24xx->rtc;
	2789	memset( &rtc->regs, 0, sizeof( rtc->regs));
	2790	rtc->regs.almday = 1;
	2791	rtc->regs.almmon = 1;
	2792	rtc->timer_update->adjust( attotime::never);
	2793	rtc->timer_update->adjust( attotime::from_msec( 1000), 0, attotime::from_msec( 1000));
2483	2794	}
2484	2795
2485	2796	static READ32_DEVICE_HANDLER( s3c24xx_rtc_r )
r13744	r13745
2605	2916
2606	2917	/* A/D Converter */
2607	2918
	2919	static void s3c24xx_adc_reset( device_t *device)
	2920	{
	2921	s3c24xx_t *s3c24xx = get_token( device);
	2922	s3c24xx_adc_t *adc = &s3c24xx->adc;
	2923	memset( &adc->regs, 0, sizeof( adc->regs));
	2924	adc->regs.adccon = 0x3FC4;
	2925	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	2926	adc->regs.adctsc = 0x58;
	2927	adc->regs.adcdly = 0xFF;
	2928	#endif
	2929	}
	2930
2608	2931	static UINT32 iface_adc_data_r( device_t *device, int ch)
2609	2932	{
2610	2933	s3c24xx_t *s3c24xx = get_token( device);
2611	2934	if (s3c24xx->iface->adc.data_r)
2612	2935	{
2613		return (s3c24xx->iface->adc.data_r)( device, ch, 0);
	2936	int offs = ch;
	2937	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	2938	if (BIT( s3c24xx->adc.regs.adctsc, 2) != 0)
	2939	{
	2940	offs += 2;
	2941	}
	2942	#endif
	2943	return (s3c24xx->iface->adc.data_r)( device, offs, 0);
2614	2944	}
2615	2945	else
2616	2946	{
r13744	r13745
2688	3018
2689	3019	/* SPI */
2690	3020
	3021	static void s3c24xx_spi_reset( device_t *device)
	3022	{
	3023	s3c24xx_t *s3c24xx = get_token( device);
	3024	for (int i = 0; i < S3C24XX_SPI_COUNT; i++)
	3025	{
	3026	s3c24xx_spi_t *spi = &s3c24xx->spi[i];
	3027	memset( &spi->regs, 0, sizeof( spi->regs));
	3028	spi->regs.spsta = 1;
	3029	#if defined(DEVICE_S3C2400) || defined(DEVICE_S3C2410)
	3030	spi->regs.sppin = 2;
	3031	#endif
	3032	}
	3033	}
	3034
2691	3035	static UINT32 s3c24xx_spi_r( device_t *device, UINT32 ch, UINT32 offset)
2692	3036	{
2693	3037	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
2747	3091
2748	3092	#if defined(DEVICE_S3C2400)
2749	3093
	3094	static void s3c24xx_mmc_reset( device_t *device)
	3095	{
	3096	s3c24xx_t *s3c24xx = get_token( device);
	3097	s3c24xx_mmc_t *mmc = &s3c24xx->mmc;
	3098	memset( &mmc->regs, 0, sizeof( mmc->regs));
	3099	}
	3100
2750	3101	static READ32_DEVICE_HANDLER( s3c24xx_mmc_r )
2751	3102	{
2752	3103	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
2768	3119
2769	3120	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
2770	3121
	3122	static void s3c24xx_sdi_reset( device_t *device)
	3123	{
	3124	s3c24xx_t *s3c24xx = get_token( device);
	3125	s3c24xx_sdi_t *sdi = &s3c24xx->sdi;
	3126	memset( &sdi->regs, 0, sizeof( sdi->regs));
	3127	#if defined(DEVICE_S3C2410)
	3128	sdi->regs.data[0x24/4] = 0x2000;
	3129	#elif defined(DEVICE_S3C2440)
	3130	sdi->regs.data[0x04/4] = 1;
	3131	sdi->regs.data[0x24/4] = 0x10000;
	3132	#endif
	3133	}
	3134
2771	3135	static READ32_DEVICE_HANDLER( s3c24xx_sdi_r )
2772	3136	{
2773	3137	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
2789	3153
2790	3154	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
2791	3155
	3156	static void s3c24xx_nand_reset( device_t *device)
	3157	{
	3158	s3c24xx_t *s3c24xx = get_token( device);
	3159	s3c24xx_nand_t *nand = &s3c24xx->nand;
	3160	memset( &nand->regs, 0, sizeof( nand->regs));
	3161	#if defined(DEVICE_S3C2440)
	3162	nand->regs.nfconf = 0x1000;
	3163	nand->regs.nfcont = 0x0384;
	3164	#endif
	3165	}
	3166
2792	3167	INLINE void iface_nand_command_w( device_t *device, UINT8 data)
2793	3168	{
2794	3169	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
2897	3272	static void s3c24xx_nand_update_ecc( device_t *device, UINT8 data)
2898	3273	{
2899	3274	s3c24xx_t *s3c24xx = get_token( device);
	3275	s3c24xx_nand_t *nand = &s3c24xx->nand;
2900	3276	UINT8 temp[4];
2901	3277	#if defined(DEVICE_S3C2410)
2902		temp[0] = s3c24xx->nand.mecc[0];
2903		temp[1] = s3c24xx->nand.mecc[1];
2904		temp[2] = s3c24xx->nand.mecc[2];
2905		nand_update_mecc( s3c24xx->nand.mecc, s3c24xx->nand.pos++, data);
2906		verboselog( device->machine(), 5, "NAND - MECC %03X - %02X %02X %02X ->  %02X %02X %02X\n", s3c24xx->nand.pos - 1, temp[0], temp[1], temp[2], s3c24xx->nand.mecc[0], s3c24xx->nand.mecc[1], s3c24xx->nand.mecc[2]);
2907		if (s3c24xx->nand.pos == 512) s3c24xx->nand.pos = 0;
	3278	temp[0] = nand->mecc[0];
	3279	temp[1] = nand->mecc[1];
	3280	temp[2] = nand->mecc[2];
	3281	nand_update_mecc( nand->mecc, nand->ecc_pos++, data);
	3282	verboselog( device->machine(), 5, "NAND - MECC %03X - %02X %02X %02X -> %02X %02X %02X\n", nand->ecc_pos - 1, temp[0], temp[1], temp[2], nand->mecc[0], nand->mecc[1], nand->mecc[2]);
	3283	if (nand->ecc_pos == 512) nand->ecc_pos = 0;
2908	3284	#else
2909		if ((s3c24xx->nand.regs.nfcont & (1 << 5)) == 0)
	3285	if ((nand->regs.nfcont & (1 << 5)) == 0)
2910	3286	{
2911		temp[0] = s3c24xx->nand.mecc[0];
2912		temp[1] = s3c24xx->nand.mecc[1];
2913		temp[2] = s3c24xx->nand.mecc[2];
2914		temp[3] = s3c24xx->nand.mecc[3];
2915		nand_update_mecc( s3c24xx->nand.mecc, s3c24xx->nand.pos++, data);
2916		verboselog( device->machine(), 5, "NAND - MECC %03X - %02X %02X %02X %02X ->  %02X %02X %02X %02X\n", s3c24xx->nand.pos - 1, temp[0], temp[1], temp[2], temp[3], s3c24xx->nand.mecc[0], s3c24xx->nand.mecc[1], s3c24xx->nand.mecc[2], s3c24xx->nand.mecc[3]);
2917		if (s3c24xx->nand.pos == 2048) s3c24xx->nand.pos = 0;
	3287	temp[0] = nand->mecc[0];
	3288	temp[1] = nand->mecc[1];
	3289	temp[2] = nand->mecc[2];
	3290	temp[3] = nand->mecc[3];
	3291	nand_update_mecc( nand->mecc, nand->ecc_pos++, data);
	3292	verboselog( device->machine(), 5, "NAND - MECC %03X - %02X %02X %02X %02X -> %02X %02X %02X %02X\n", nand->ecc_pos - 1, temp[0], temp[1], temp[2], temp[3], nand->mecc[0], nand->mecc[1], nand->mecc[2], nand->mecc[3]);
	3293	if (nand->ecc_pos == 2048) nand->ecc_pos = 0;
2918	3294	}
2919		if ((s3c24xx->nand.regs.nfcont & (1 << 6)) == 0)
	3295	if ((nand->regs.nfcont & (1 << 6)) == 0)
2920	3296	{
2921		temp[0] = s3c24xx->nand.secc[0];
2922		temp[1] = s3c24xx->nand.secc[1];
2923		nand_update_secc( s3c24xx->nand.secc, s3c24xx->nand.pos++, data);
2924		verboselog( device->machine(), 5, "NAND - SECC %02X - %02X %02X ->  %02X %02X\n", s3c24xx->nand.pos - 1, temp[0], temp[1], s3c24xx->nand.secc[0], s3c24xx->nand.secc[1]);
2925		if (s3c24xx->nand.pos == 16) s3c24xx->nand.pos = 0;
	3297	temp[0] = nand->secc[0];
	3298	temp[1] = nand->secc[1];
	3299	nand_update_secc( nand->secc, nand->ecc_pos++, data);
	3300	verboselog( device->machine(), 5, "NAND - SECC %02X - %02X %02X -> %02X %02X\n", nand->ecc_pos - 1, temp[0], temp[1], nand->secc[0], nand->secc[1]);
	3301	if (nand->ecc_pos == 16) nand->ecc_pos = 0;
2926	3302	}
2927	3303	#endif
2928	3304	}
2929	3305
2930	3306	static void s3c24xx_nand_command_w( device_t *device, UINT8 data)
2931	3307	{
	3308	s3c24xx_t *s3c24xx = get_token( device);
2932	3309	verboselog( device->machine(), 5, "NAND write command %02X\n", data);
	3310	s3c24xx->nand.data_count = 0;
2933	3311	iface_nand_command_w( device, data);
2934	3312	}
2935	3313
2936	3314	static void s3c24xx_nand_address_w( device_t *device, UINT8 data)
2937	3315	{
	3316	s3c24xx_t *s3c24xx = get_token( device);
2938	3317	verboselog( device->machine(), 5, "NAND write address %02X\n", data);
	3318	s3c24xx->nand.data_count = 0;
2939	3319	iface_nand_address_w( device, data);
2940	3320	}
2941	3321
2942	3322	static UINT8 s3c24xx_nand_data_r( device_t *device)
2943	3323	{
	3324	s3c24xx_t *s3c24xx = get_token( device);
2944	3325	UINT8 data = iface_nand_data_r( device);
2945		verboselog( device->machine(), 5, "NAND data read %02X\n", data);
	3326	verboselog( device->machine(), 5, "NAND read data %02X [%04X]\n", data, s3c24xx->nand.data_count++);
2946	3327	s3c24xx_nand_update_ecc( device, data);
2947	3328	return data;
2948	3329	}
2949	3330
2950	3331	static void s3c24xx_nand_data_w( device_t *device, UINT8 data)
2951	3332	{
2952		verboselog( device->machine(), 5, "NAND write data %02X\n", data);
	3333	s3c24xx_t *s3c24xx = get_token( device);
	3334	verboselog( device->machine(), 5, "NAND write data %02X [%04X]\n", data, s3c24xx->nand.data_count++);
2953	3335	iface_nand_data_w( device, data);
2954	3336	s3c24xx_nand_update_ecc( device, data);
2955	3337	}
r13744	r13745
2963	3345	case S3C24XX_NFDATA :
2964	3346	{
2965	3347	data = 0;
	3348	#if defined(DEVICE_S3C2410)
	3349	data = data | s3c24xx_nand_data_r( device);
	3350	#elif defined(DEVICE_S3C2440)
2966	3351	if ((mem_mask & 0x000000FF) != 0) data = data | (s3c24xx_nand_data_r( device) <<  0);
2967	3352	if ((mem_mask & 0x0000FF00) != 0) data = data | (s3c24xx_nand_data_r( device) <<  8);
2968	3353	if ((mem_mask & 0x00FF0000) != 0) data = data | (s3c24xx_nand_data_r( device) << 16);
2969	3354	if ((mem_mask & 0xFF000000) != 0) data = data | (s3c24xx_nand_data_r( device) << 24);
	3355	#endif
2970	3356	}
2971	3357	break;
2972	3358	#if defined(DEVICE_S3C2410)
2973	3359	case S3C24XX_NFECC :
2974	3360	{
2975		data = (s3c24xx->nand.mecc[2] << 16) | (s3c24xx->nand.mecc[1] << 8) | (s3c24xx->nand.mecc[0] << 0);
2976		//data = 0xFFFFFFFF;
	3361	data = ((s3c24xx->nand.mecc[2] << 16) | (s3c24xx->nand.mecc[1] << 8) | (s3c24xx->nand.mecc[0] << 0));
2977	3362	}
2978	3363	break;
2979	3364	#endif
r13744	r13745
3009	3394	{
3010	3395	s3c24xx_t *s3c24xx = get_token( device);
3011	3396	verboselog( device->machine(), 5, "NAND - init ecc\n");
3012		#if defined(DEVICE_S3C2410)
3013		s3c24xx->nand.mecc[0] = 0;
3014		s3c24xx->nand.mecc[1] = 0;
3015		s3c24xx->nand.mecc[2] = 0;
3016		#else
3017		s3c24xx->nand.mecc[0] = 0;
3018		s3c24xx->nand.mecc[1] = 0;
3019		s3c24xx->nand.mecc[2] = 0;
3020		s3c24xx->nand.mecc[3] = 0;
	3397	s3c24xx->nand.mecc[0] = 0xFF;
	3398	s3c24xx->nand.mecc[1] = 0xFF;
	3399	s3c24xx->nand.mecc[2] = 0xFF;
	3400	#if defined(DEVICE_S3C2440)
	3401	s3c24xx->nand.mecc[3] = 0xFF;
3021	3402	s3c24xx->nand.secc[0] = 0;
3022	3403	s3c24xx->nand.secc[1] = 0;
3023		#endif
3024		s3c24xx->nand.pos = 0;
	3404	#endif
	3405	s3c24xx->nand.ecc_pos = 0;
3025	3406	}
3026	3407
3027	3408	static WRITE32_DEVICE_HANDLER( s3c24xx_nand_w )
3028	3409	{
3029	3410	s3c24xx_t *s3c24xx = get_token( device);
3030	3411	UINT32 old_value = ((UINT32*)&s3c24xx->nand.regs)[offset];
3031		verboselog( device->machine(), 9, "(NAND) %08X <- %08X\n", S3C24XX_BASE_NAND + (offset << 2), data);
	3412	verboselog( device->machine(), 9, "(NAND) %08X <- %08X (%08X)\n", S3C24XX_BASE_NAND + (offset << 2), data, mem_mask);
3032	3413	COMBINE_DATA(&((UINT32*)&s3c24xx->nand.regs)[offset]);
3033	3414	switch (offset)
3034	3415	{
r13744	r13745
3054	3435	#endif
3055	3436	case S3C24XX_NFSTAT :
3056	3437	{
3057		s3c24xx->nand.regs.nfstat = (s3c24xx->nand.regs.nfstat & ~0x03) | (old_value & 0x03);
	3438	s3c24xx->nand.regs.nfstat = (s3c24xx->nand.regs.nfstat & ~0x03) | (old_value & 0x03); // read-only
3058	3439	#if defined(DEVICE_S3C2440)
3059	3440	if ((data & (1 << 2)) != 0)
3060	3441	{
r13744	r13745
3075	3456	break;
3076	3457	case S3C24XX_NFDATA :
3077	3458	{
	3459	#if defined(DEVICE_S3C2410)
	3460	s3c24xx_nand_data_w( device, data & 0xFF);
	3461	#elif defined(DEVICE_S3C2440)
3078	3462	if ((mem_mask & 0x000000FF) != 0) s3c24xx_nand_data_w( device, (data >>  0) & 0xFF);
3079	3463	if ((mem_mask & 0x0000FF00) != 0) s3c24xx_nand_data_w( device, (data >>  8) & 0xFF);
3080	3464	if ((mem_mask & 0x00FF0000) != 0) s3c24xx_nand_data_w( device, (data >> 16) & 0xFF);
3081	3465	if ((mem_mask & 0xFF000000) != 0) s3c24xx_nand_data_w( device, (data >> 24) & 0xFF);
	3466	#endif
3082	3467	}
3083	3468	break;
3084	3469	}
r13744	r13745
3087	3472	ATTR_UNUSED static WRITE_LINE_DEVICE_HANDLER( s3c24xx_pin_frnb_w )
3088	3473	{
3089	3474	s3c24xx_t *s3c24xx = get_token( device);
	3475	verboselog( device->machine(), 9, "s3c24xx_pin_frnb_w (%d)\n", state);
3090	3476	#if defined(DEVICE_S3C2440)
3091	3477	if ((BIT( s3c24xx->nand.regs.nfstat, 0) == 0) && (state != 0))
3092	3478	{
r13744	r13745
3113	3499
3114	3500	#if defined(DEVICE_S3C2440)
3115	3501
	3502	static void s3c24xx_cam_reset( device_t *device)
	3503	{
	3504	s3c24xx_t *s3c24xx = get_token( device);
	3505	s3c24xx_cam_t *cam = &s3c24xx->cam;
	3506	memset( &cam->regs, 0, sizeof( cam->regs));
	3507	}
	3508
3116	3509	static READ32_DEVICE_HANDLER( s3c24xx_cam_r )
3117	3510	{
3118	3511	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
3134	3527
3135	3528	#if defined(DEVICE_S3C2440)
3136	3529
	3530	static void s3c24xx_ac97_reset( device_t *device)
	3531	{
	3532	s3c24xx_t *s3c24xx = get_token( device);
	3533	s3c24xx_ac97_t *ac97 = &s3c24xx->ac97;
	3534	memset( &ac97->regs, 0, sizeof( ac97->regs));
	3535	}
	3536
3137	3537	static READ32_DEVICE_HANDLER( s3c24xx_ac97_r )
3138	3538	{
3139	3539	s3c24xx_t *s3c24xx = get_token( device);
r13744	r13745
3153	3553
3154	3554	// ...
3155	3555
	3556	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	3557
	3558	static void s3c24xx_nand_auto_boot( device_t *device)
	3559	{
	3560	int om0 = iface_core_pin_r( device, S3C24XX_CORE_PIN_OM0);
	3561	int om1 = iface_core_pin_r( device, S3C24XX_CORE_PIN_OM1);
	3562	if ((om0 == 0) && (om1 == 0))
	3563	{
	3564	s3c24xx_t *s3c24xx = get_token( device);
	3565	int ncon = iface_core_pin_r( device, S3C24XX_CORE_PIN_NCON);
	3566	UINT8 *ptr = s3c24xx->steppingstone;
	3567	int page_size, address_cycle;
	3568	#if defined(DEVICE_S3C2410)
	3569	page_size = 512;
	3570	if (ncon == 0)
	3571	{
	3572	address_cycle = 3; // byte-page-page
	3573	}
	3574	else
	3575	{
	3576	address_cycle = 4; // byte-page-page-page
	3577	}
	3578	#elif defined(DEVICE_S3C2440)
	3579	UINT32 port_g = iface_gpio_port_r( device, S3C24XX_GPIO_PORT_G, 0);
	3580	if (ncon == 0)
	3581	{
	3582	if (BIT( port_g, 13) == 0)
	3583	{
	3584	page_size = 256;
	3585	address_cycle = 3; // byte-page-page
	3586	}
	3587	else
	3588	{
	3589	page_size = 512;
	3590	address_cycle = 4; // byte-page-page-page
	3591	}
	3592	}
	3593	else
	3594	{
	3595	if (BIT( port_g, 13) == 0)
	3596	{
	3597	page_size = 1024;
	3598	address_cycle = 4; // byte-byte-page-page or byte-page-page-page ??? assume latter
	3599	}
	3600	else
	3601	{
	3602	page_size = 2048;
	3603	address_cycle = 5; // byte-byte-page-page-page
	3604	}
	3605	}
	3606	#endif
	3607	iface_nand_command_w( device, 0xFF);
	3608	for (int page = 0; page < (4 * 1024) / page_size; page++)
	3609	{
	3610	iface_nand_command_w( device, 0x00);
	3611	iface_nand_address_w( device, 0x00);
	3612	if (address_cycle > 4)
	3613	{
	3614	iface_nand_address_w( device, 0x00);
	3615	}
	3616	iface_nand_address_w( device, (page >> 0) & 0xFF);
	3617	iface_nand_address_w( device, (page >> 8) & 0xFF);
	3618	if (address_cycle > 3)
	3619	{
	3620	iface_nand_address_w( device, (page >> 16) & 0xFF);
	3621	}
	3622	for (int i = 0; i < page_size; i++)
	3623	{
	3624	*ptr++ = iface_nand_data_r( device);
	3625	}
	3626	}
	3627	iface_nand_command_w( device, 0xFF);
	3628	}
	3629	}
	3630
	3631	#endif
	3632
3156	3633	static DEVICE_RESET( s3c24xx )
3157	3634	{
3158		s3c24xx_t *s3c24xx = get_token( device);
3159		s3c24xx->iis.fifo_index = 0;
3160		//  s3c24xx->iic.data_index = 0;
3161		#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
3162		s3c24xx->gpio.regs.gstatus2 = 0x00000001; // Boot is caused by power on reset
3163		#endif
3164		s3c24xx->irq.line_irq = s3c24xx->irq.line_fiq = CLEAR_LINE;
	3635	verboselog( device->machine(), 1, "s3c24xx device reset\n");
	3636	s3c24xx_uart_reset( device);
	3637	s3c24xx_pwm_reset( device);
	3638	s3c24xx_dma_reset( device);
	3639	s3c24xx_iic_reset( device);
	3640	s3c24xx_iis_reset( device);
	3641	s3c24xx_lcd_reset( device);
	3642	s3c24xx_rtc_reset( device);
	3643	s3c24xx_wdt_reset( device);
	3644	s3c24xx_irq_reset( device);
	3645	s3c24xx_gpio_reset( device);
	3646	s3c24xx_memcon_reset( device);
	3647	s3c24xx_clkpow_reset( device);
	3648	s3c24xx_usb_host_reset( device);
	3649	s3c24xx_usb_device_reset( device);
	3650	s3c24xx_adc_reset( device);
	3651	s3c24xx_spi_reset( device);
	3652	#if defined(DEVICE_S3C2400)
	3653	s3c24xx_mmc_reset( device);
	3654	#endif
	3655	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	3656	s3c24xx_sdi_reset( device);
	3657	s3c24xx_nand_reset( device);
	3658	#endif
	3659	#if defined(DEVICE_S3C2440)
	3660	s3c24xx_cam_reset( device);
	3661	s3c24xx_ac97_reset( device);
	3662	#endif
	3663	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	3664	s3c24xx_nand_auto_boot( device);
	3665	#endif
3165	3666	}
3166	3667
3167	3668	static DEVICE_START( s3c24xx )
3168	3669	{
3169	3670	s3c24xx_t *s3c24xx = get_token( device);
	3671	verboselog( device->machine(), 1, "s3c24xx device start\n");
3170	3672	s3c24xx->iface = (const s3c24xx_interface *)device->static_config();
3171		for (int i = 0; i < 5; i++) s3c24xx->pwm.timer[i] = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_pwm_timer_exp), (void*)device);
3172		for (int i = 0; i < 4; i++) s3c24xx->dma[i].timer = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_dma_timer_exp), (void*)device);
	3673	for (int i = 0; i < 5; i++)
	3674	{
	3675	s3c24xx->pwm.timer[i] = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_pwm_timer_exp), (void*)device);
	3676	}
	3677	for (int i = 0; i < S3C24XX_DMA_COUNT; i++)
	3678	{
	3679	s3c24xx->dma[i].timer = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_dma_timer_exp), (void*)device);
	3680	}
3173	3681	s3c24xx->iic.timer = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_iic_timer_exp), (void*)device);
3174	3682	s3c24xx->iis.timer = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_iis_timer_exp), (void*)device);
3175	3683	s3c24xx->lcd.timer = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_lcd_timer_exp), (void*)device);
3176	3684	s3c24xx->rtc.timer_tick_count = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_rtc_timer_tick_count_exp), (void*)device);
3177	3685	s3c24xx->rtc.timer_update = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_rtc_timer_update_exp), (void*)device);
3178	3686	s3c24xx->wdt.timer = device->machine().scheduler().timer_alloc( FUNC(s3c24xx_wdt_timer_exp), (void*)device);
3179		s3c24xx->rtc.timer_update->adjust( attotime::from_msec( 1000), 0, attotime::from_msec( 1000));
3180		s3c24xx_rtc_init( device);
	3687	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	3688	int om0 = iface_core_pin_r( device, S3C24XX_CORE_PIN_OM0);
	3689	int om1 = iface_core_pin_r( device, S3C24XX_CORE_PIN_OM1);
	3690	if ((om0 == 0) && (om1 == 0))
	3691	{
	3692	address_space *space = device->machine().device( "maincpu")->memory().space( AS_PROGRAM);
	3693	space->install_ram( 0x00000000, 0x00000fff, s3c24xx->steppingstone);
	3694	space->install_ram( 0x40000000, 0x40000fff, s3c24xx->steppingstone);
	3695	}
	3696	#endif
3181	3697	}
3182	3698
3183	3699	static DEVICE_GET_INFO( s3c24xx )

src/mess/drivers/gizmondo.c

r13744	r13745
68	68
69	69	// I/O PORT
70	70
71		static UINT32 s3c2440_gpio_port_r( device_t *device, int port)
	71	static UINT32 s3c2440_gpio_port_r( device_t *device, int port, UINT32 mask)
72	72	{
73	73	gizmondo_state *gizmondo = device->machine().driver_data<gizmondo_state>();
74	74	UINT32 data = gizmondo->m_port[port];
r13744	r13745
108	108	return data;
109	109	}
110	110
111		static void s3c2440_gpio_port_w( device_t *device, int port, UINT32 data)
	111	static void s3c2440_gpio_port_w( device_t *device, int port, UINT32 mask, UINT32 data)
112	112	{
113	113	gizmondo_state *gizmondo = device->machine().driver_data<gizmondo_state>();
114	114	gizmondo->m_port[port] = data;
r13744	r13745
171	171
172	172	static S3C2440_INTERFACE( gizmondo_s3c2440_intf )
173	173	{
	174	// CORE (pin read / pin write)
	175	{ NULL, NULL },
174	176	// GPIO (port read / port write)
175	177	{ s3c2440_gpio_port_r, s3c2440_gpio_port_w },
176	178	// I2C (scl write / sda read / sda write)
r13744	r13745
179	181	{ NULL },
180	182	// I2S (data write)
181	183	{ NULL },
182		// NAND (command write, address write, data read, data write)
	184	// NAND (command write / address write / data read / data write)
183	185	{ NULL, NULL, NULL, NULL },
184	186	// LCD (flags)
185	187	{ 0 }

src/mess/drivers/hp49gp.c

r13744	r13745
158	158
159	159	// I/O PORT
160	160
161		static UINT32 s3c2410_gpio_port_r( device_t *device, int port)
	161	static UINT32 s3c2410_gpio_port_r( device_t *device, int port, UINT32 mask)
162	162	{
163	163	hp49gp_state *hp49gp = device->machine().driver_data<hp49gp_state>();
164	164	UINT32 data = hp49gp->m_port[port];
r13744	r13745
209	209	return data;
210	210	}
211	211
212		static void s3c2410_gpio_port_w( device_t *device, int port, UINT32 data)
	212	static void s3c2410_gpio_port_w( device_t *device, int port, UINT32 mask, UINT32 data)
213	213	{
214	214	hp49gp_state *hp49gp = device->machine().driver_data<hp49gp_state>();
215	215	hp49gp->m_port[port] = data;
r13744	r13745
273	273
274	274	static S3C2410_INTERFACE( hp49gp_s3c2410_intf )
275	275	{
	276	// CORE (pin read / pin write)
	277	{ NULL, NULL },
276	278	// GPIO (port read / port write)
277	279	{ s3c2410_gpio_port_r, s3c2410_gpio_port_w },
278	280	// I2C (scl write / sda read / sda write)
r13744	r13745
281	283	{ NULL },
282	284	// I2S (data write)
283	285	{ NULL },
284		// NAND (command write, address write, data read, data write)
	286	// NAND (command write / address write / data read / data write)
285	287	{ NULL, NULL, NULL, NULL },
286	288	// LCD (flags)
287	289	{ S3C24XX_INTERFACE_LCD_REVERSE }

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