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r12962 Thursday 29th September, 2011 at 10:30:20 UTC by Robbbert
VII - modernised; BATMANTV connected X key, game is now playable; WALLE added details of alternate dump. [Robbbert]

[src/mess/drivers]

vii.c

src/mess/drivers/vii.c

r12961	r12962
37	37	ND - Likely many more
38	38
39	39	*******************************************************************************/
	40	#define ADDRESS_MAP_MODERN
40	41
41	42	#include "emu.h"
42	43	#include "cpu/unsp/unsp.h"
r12961	r12962
58	59	{
59	60	public:
60	61	vii_state(const machine_config &mconfig, device_type type, const char *tag)
61		: driver_device(mconfig, type, tag) { }
	62	: driver_device(mconfig, type, tag),
	63	m_maincpu(*this, "maincpu")
	64	{ }
62	65
63		UINT16 *m_ram;
64		UINT16 *m_cart;
65		UINT16 *m_rowscroll;
66		UINT16 *m_palette;
67		UINT16 *m_spriteram;
	66	required_device<cpu_device> m_maincpu;
	67	DECLARE_READ16_MEMBER(vii_video_r);
	68	DECLARE_WRITE16_MEMBER(vii_video_w);
	69	DECLARE_READ16_MEMBER(vii_audio_r);
	70	DECLARE_WRITE16_MEMBER(vii_audio_w);
	71	DECLARE_READ16_MEMBER(vii_io_r);
	72	DECLARE_WRITE16_MEMBER(vii_io_w);
	73	DECLARE_WRITE16_MEMBER(vii_rowscroll_w);
	74	DECLARE_WRITE16_MEMBER(vii_spriteram_w);
	75	UINT16 *m_p_ram;
	76	UINT16 *m_p_cart;
	77	UINT16 *m_p_rowscroll;
	78	UINT16 *m_p_palette;
	79	UINT16 *m_p_spriteram;
68	80
69	81	UINT32 m_current_bank;
70	82
r12961	r12962
84	96
85	97	emu_timer *m_tmb1;
86	98	emu_timer *m_tmb2;
	99	void vii_do_dma(UINT32 len);
	100	void vii_do_gpio(UINT32 offset);
	101	void vii_switch_bank(UINT32 bank);
	102	void vii_do_i2c();
	103	void spg_do_dma(UINT32 len);
87	104	};
88	105
89	106	enum
r12961	r12962
96	113	};
97	114
98	115
99		#define VII_CTLR_IRQ_ENABLE      state->m_io_regs[0x21]
100		#define VII_VIDEO_IRQ_ENABLE   state->m_video_regs[0x62]
101		#define VII_VIDEO_IRQ_STATUS   state->m_video_regs[0x63]
	116	#define VII_CTLR_IRQ_ENABLE   m_io_regs[0x21]
	117	#define VII_VIDEO_IRQ_ENABLE   m_video_regs[0x62]
	118	#define VII_VIDEO_IRQ_STATUS   m_video_regs[0x63]
102	119
103	120
104	121	#define VERBOSE_LEVEL   (3)
r12961	r12962
204	221
205	222	if((ctrl & 0x0010) && yy < 240)
206	223	{
207		xx = (xx - (INT16)state->m_rowscroll[yy]) & 0x01ff;
	224	xx = (xx - (INT16)state->m_p_rowscroll[yy]) & 0x01ff;
208	225	}
209	226
210	227	if(xx < 320 && yy < 240)
211	228	{
212		UINT16 rgb = state->m_palette[pal];
	229	UINT16 rgb = state->m_p_palette[pal];
213	230	if(!(rgb & 0x8000))
214	231	{
215	232	if (attr & 0x4000)
r12961	r12962
387	404	*    Machine Hardware    *
388	405	*************************/
389	406
390		static void vii_do_dma(running_machine &machine, UINT32 len)
	407	void vii_state::vii_do_dma(UINT32 len)
391	408	{
392		vii_state *state = machine.driver_data<vii_state>();
393		address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
394		UINT32 src = state->m_video_regs[0x70];
395		UINT32 dst = state->m_video_regs[0x71] + 0x2c00;
	409	address_space *mem = m_maincpu->memory().space(AS_PROGRAM);
	410	UINT32 src = m_video_regs[0x70];
	411	UINT32 dst = m_video_regs[0x71] + 0x2c00;
396	412	UINT32 j;
397	413
398	414	for(j = 0; j < len; j++)
399	415	{
400		space->write_word((dst+j) << 1, space->read_word((src+j) << 1));
	416	mem->write_word((dst+j) << 1, mem->read_word((src+j) << 1));
401	417	}
402	418
403		state->m_video_regs[0x72] = 0;
404		state->m_video_regs[0x63] |= 4;
	419	m_video_regs[0x72] = 0;
	420	m_video_regs[0x63] |= 4;
405	421	}
406	422
407		static READ16_HANDLER( vii_video_r )
	423	READ16_MEMBER( vii_state::vii_video_r )
408	424	{
409		vii_state *state = space->machine().driver_data<vii_state>();
410
411	425	switch(offset)
412	426	{
413	427	case 0x62: // Video IRQ Enable
414		verboselog(space->machine(), 0, "vii_video_r: Video IRQ Enable: %04x\n", VII_VIDEO_IRQ_ENABLE);
	428	verboselog(machine(), 0, "vii_video_r: Video IRQ Enable: %04x\n", VII_VIDEO_IRQ_ENABLE);
415	429	return VII_VIDEO_IRQ_ENABLE;
416	430
417	431	case 0x63: // Video IRQ Status
418		verboselog(space->machine(), 0, "vii_video_r: Video IRQ Status: %04x\n", VII_VIDEO_IRQ_STATUS);
	432	verboselog(machine(), 0, "vii_video_r: Video IRQ Status: %04x\n", VII_VIDEO_IRQ_STATUS);
419	433	return VII_VIDEO_IRQ_STATUS;
420	434
421	435	default:
422		verboselog(space->machine(), 0, "vii_video_r: Unknown register %04x = %04x\n", 0x2800 + offset, state->m_video_regs[offset]);
	436	verboselog(machine(), 0, "vii_video_r: Unknown register %04x = %04x\n", 0x2800 + offset, m_video_regs[offset]);
423	437	break;
424	438	}
425		return state->m_video_regs[offset];
	439	return m_video_regs[offset];
426	440	}
427	441
428		static WRITE16_HANDLER( vii_video_w )
	442	WRITE16_MEMBER( vii_state::vii_video_w )
429	443	{
430		vii_state *state = space->machine().driver_data<vii_state>();
431
432	444	switch(offset)
433	445	{
434	446	case 0x10: case 0x16:   // page 1,2 X scroll
435	447	data &= 0x01ff;
436		COMBINE_DATA(&state->m_video_regs[offset]);
	448	COMBINE_DATA(&m_video_regs[offset]);
437	449	break;
438	450
439	451	case 0x11: case 0x17:   // page 1,2 Y scroll
440	452	data &= 0x00ff;
441		COMBINE_DATA(&state->m_video_regs[offset]);
	453	COMBINE_DATA(&m_video_regs[offset]);
442	454	break;
443	455	case 0x36:      // IRQ pos V
444	456	case 0x37:      // IRQ pos H
445	457	data &= 0x01ff;
446		COMBINE_DATA(&state->m_video_regs[offset]);
	458	COMBINE_DATA(&m_video_regs[offset]);
447	459	break;
448	460	case 0x62: // Video IRQ Enable
449		verboselog(space->machine(), 0, "vii_video_w: Video IRQ Enable = %04x (%04x)\n", data, mem_mask);
	461	verboselog(machine(), 0, "vii_video_w: Video IRQ Enable = %04x (%04x)\n", data, mem_mask);
450	462	COMBINE_DATA(&VII_VIDEO_IRQ_ENABLE);
451	463	break;
452	464
453	465	case 0x63: // Video IRQ Acknowledge
454		verboselog(space->machine(), 0, "vii_video_w: Video IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
	466	verboselog(machine(), 0, "vii_video_w: Video IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
455	467	VII_VIDEO_IRQ_STATUS &= ~data;
456	468	if(!VII_VIDEO_IRQ_STATUS)
457	469	{
458		cputag_set_input_line(space->machine(), "maincpu", UNSP_IRQ0_LINE, CLEAR_LINE);
	470	cputag_set_input_line(machine(), "maincpu", UNSP_IRQ0_LINE, CLEAR_LINE);
459	471	}
460	472	break;
461	473
462	474	case 0x70: // Video DMA Source
463		verboselog(space->machine(), 0, "vii_video_w: Video DMA Source = %04x (%04x)\n", data, mem_mask);
464		COMBINE_DATA(&state->m_video_regs[offset]);
	475	verboselog(machine(), 0, "vii_video_w: Video DMA Source = %04x (%04x)\n", data, mem_mask);
	476	COMBINE_DATA(&m_video_regs[offset]);
465	477	break;
466	478
467	479	case 0x71: // Video DMA Dest
468		verboselog(space->machine(), 0, "vii_video_w: Video DMA Dest = %04x (%04x)\n", data, mem_mask);
469		COMBINE_DATA(&state->m_video_regs[offset]);
	480	verboselog(machine(), 0, "vii_video_w: Video DMA Dest = %04x (%04x)\n", data, mem_mask);
	481	COMBINE_DATA(&m_video_regs[offset]);
470	482	break;
471	483
472	484	case 0x72: // Video DMA Length
473		verboselog(space->machine(), 0, "vii_video_w: Video DMA Length = %04x (%04x)\n", data, mem_mask);
474		vii_do_dma(space->machine(), data);
	485	verboselog(machine(), 0, "vii_video_w: Video DMA Length = %04x (%04x)\n", data, mem_mask);
	486	vii_do_dma(data);
475	487	break;
476	488
477	489	default:
478		verboselog(space->machine(), 0, "vii_video_w: Unknown register %04x = %04x (%04x)\n", 0x2800 + offset, data, mem_mask);
479		COMBINE_DATA(&state->m_video_regs[offset]);
	490	verboselog(machine(), 0, "vii_video_w: Unknown register %04x = %04x (%04x)\n", 0x2800 + offset, data, mem_mask);
	491	COMBINE_DATA(&m_video_regs[offset]);
480	492	break;
481	493	}
482	494	}
483	495
484		static READ16_HANDLER( vii_audio_r )
	496	READ16_MEMBER( vii_state::vii_audio_r )
485	497	{
486	498	switch(offset)
487	499	{
488	500	default:
489		verboselog(space->machine(), 4, "vii_audio_r: Unknown register %04x\n", 0x3000 + offset);
	501	verboselog(machine(), 4, "vii_audio_r: Unknown register %04x\n", 0x3000 + offset);
490	502	break;
491	503	}
492	504	return 0;
493	505	}
494	506
495		static WRITE16_HANDLER( vii_audio_w )
	507	WRITE16_MEMBER( vii_state::vii_audio_w )
496	508	{
497	509	switch(offset)
498	510	{
499	511	default:
500		verboselog(space->machine(), 4, "vii_audio_w: Unknown register %04x = %04x (%04x)\n", 0x3000 + offset, data, mem_mask);
	512	verboselog(machine(), 4, "vii_audio_w: Unknown register %04x = %04x (%04x)\n", 0x3000 + offset, data, mem_mask);
501	513	break;
502	514	}
503	515	}
504	516
505		static void vii_switch_bank(running_machine &machine, UINT32 bank)
	517	void vii_state::vii_switch_bank(UINT32 bank)
506	518	{
507		vii_state *state = machine.driver_data<vii_state>();
508		UINT8 *cart = machine.region("cart")->base();
	519	UINT8 *cart = machine().region("cart")->base();
509	520
510		if(bank == state->m_current_bank)
	521	if(bank != m_current_bank)
511	522	{
512		return;
	523	m_current_bank = bank;
	524
	525	memcpy(m_p_cart, cart + 0x400000 * bank * 2 + 0x4000*2, (0x400000 - 0x4000) * 2);
513	526	}
514
515		state->m_current_bank = bank;
516
517		memcpy(state->m_cart, cart + 0x400000 * bank * 2 + 0x4000*2, (0x400000 - 0x4000) * 2);
518	527	}
519	528
520		static void vii_do_gpio(running_machine &machine, UINT32 offset)
	529	void vii_state::vii_do_gpio(UINT32 offset)
521	530	{
522		vii_state *state = machine.driver_data<vii_state>();
523	531	UINT32 index  = (offset - 1) / 5;
524		UINT16 buffer = state->m_io_regs[5*index + 2];
525		UINT16 dir    = state->m_io_regs[5*index + 3];
526		UINT16 attr   = state->m_io_regs[5*index + 4];
527		UINT16 special= state->m_io_regs[5*index + 5];
	532	UINT16 buffer = m_io_regs[5*index + 2];
	533	UINT16 dir    = m_io_regs[5*index + 3];
	534	UINT16 attr   = m_io_regs[5*index + 4];
	535	UINT16 special= m_io_regs[5*index + 5];
528	536
529	537	UINT16 push   = dir;
530	538	UINT16 pull   = (~dir) & (~attr);
r12961	r12962
532	540	what ^= (dir & ~attr);
533	541	what &= ~special;
534	542
535		if(state->m_spg243_mode == SPG243_VII)
	543	if(m_spg243_mode == SPG243_VII)
536	544	{
537	545	if(index == 1)
538	546	{
539	547	UINT32 bank = ((what & 0x80) >> 7) | ((what & 0x20) >> 4);
540		vii_switch_bank(machine, bank);
	548	vii_switch_bank(bank);
541	549	}
542	550	}
543		else if(state->m_spg243_mode == SPG243_BATMAN)
	551	else if(m_spg243_mode == SPG243_BATMAN)
544	552	{
545	553	if(index == 0)
546	554	{
547		UINT16 temp = input_port_read(machine, "P1");
	555	UINT16 temp = input_port_read(machine(), "P1");
548	556	what |= (temp & 0x0001) ? 0x8000 : 0;
549	557	what |= (temp & 0x0002) ? 0x4000 : 0;
550	558	what |= (temp & 0x0004) ? 0x2000 : 0;
r12961	r12962
552	560	what |= (temp & 0x0010) ? 0x0800 : 0;
553	561	what |= (temp & 0x0020) ? 0x0400 : 0;
554	562	what |= (temp & 0x0040) ? 0x0200 : 0;
555		what |= (temp & 0x0040) ? 0x0100 : 0;
	563	what |= (temp & 0x0080) ? 0x0100 : 0;
556	564	}
557	565
558	566	if(index == 2)
r12961	r12962
560	568	}
561	569	}
562	570
563		state->m_io_regs[5*index + 1] = what;
	571	m_io_regs[5*index + 1] = what;
564	572	}
565	573
566		static void vii_do_i2c(running_machine &machine)
	574	void vii_state::vii_do_i2c()
567	575	{
568	576	}
569	577
570		static void spg_do_dma(running_machine &machine, UINT32 len)
	578	void vii_state::spg_do_dma(UINT32 len)
571	579	{
572		vii_state *state = machine.driver_data<vii_state>();
573		address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
	580	address_space *mem = m_maincpu->memory().space(AS_PROGRAM);
574	581
575		UINT32 src = ((state->m_io_regs[0x101] & 0x3f) << 16) | state->m_io_regs[0x100];
576		UINT32 dst = state->m_io_regs[0x103] & 0x3fff;
	582	UINT32 src = ((m_io_regs[0x101] & 0x3f) << 16) | m_io_regs[0x100];
	583	UINT32 dst = m_io_regs[0x103] & 0x3fff;
577	584	UINT32 j;
578	585
579	586	for(j = 0; j < len; j++)
580		{
581		space->write_word((dst+j) << 1, space->read_word((src+j) << 1));
582		}
	587	mem->write_word((dst+j) << 1, mem->read_word((src+j) << 1));
583	588
584		state->m_io_regs[0x102] = 0;
	589	m_io_regs[0x102] = 0;
585	590	}
586	591
587		static READ16_HANDLER( vii_io_r )
	592	READ16_MEMBER( vii_state::vii_io_r )
588	593	{
589	594	static const char *const gpioregs[] = { "GPIO Data Port", "GPIO Buffer Port", "GPIO Direction Port", "GPIO Attribute Port", "GPIO IRQ/Latch Port" };
590	595	static const char gpioports[] = { 'A', 'B', 'C' };
591	596
592		vii_state *state = space->machine().driver_data<vii_state>();
593	597	offset -= 0x500;
594	598
595		UINT16 val = state->m_io_regs[offset];
	599	UINT16 val = m_io_regs[offset];
596	600
597	601	switch(offset)
598	602	{
599	603	case 0x01: case 0x06: case 0x0b: // GPIO Data Port A/B/C
600		vii_do_gpio(space->machine(), offset);
601		verboselog(space->machine(), 3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], state->m_io_regs[offset], mem_mask);
602		val = state->m_io_regs[offset];
	604	vii_do_gpio(offset);
	605	verboselog(machine(), 3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
	606	val = m_io_regs[offset];
603	607	break;
604	608
605	609	case 0x02: case 0x03: case 0x04: case 0x05:
606	610	case 0x07: case 0x08: case 0x09: case 0x0a:
607	611	case 0x0c: case 0x0d: case 0x0e: case 0x0f: // Other GPIO regs
608		verboselog(space->machine(), 3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], state->m_io_regs[offset], mem_mask);
	612	verboselog(machine(), 3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
609	613	break;
610	614
611	615	case 0x1c: // Random
612		val = space->machine().rand() & 0x00ff;
613		verboselog(space->machine(), 3, "vii_io_r: Random = %04x (%04x)\n", val, mem_mask);
	616	val = machine().rand() & 0x00ff;
	617	verboselog(machine(), 3, "vii_io_r: Random = %04x (%04x)\n", val, mem_mask);
614	618	break;
615	619
616	620	case 0x21: // IRQ Control
617		verboselog(space->machine(), 3, "vii_io_r: Controller IRQ Control = %04x (%04x)\n", val, mem_mask);
	621	verboselog(machine(), 3, "vii_io_r: Controller IRQ Control = %04x (%04x)\n", val, mem_mask);
618	622	break;
619	623
620	624	case 0x22: // IRQ Status
621		verboselog(space->machine(), 3, "vii_io_r: Controller IRQ Status = %04x (%04x)\n", val, mem_mask);
	625	verboselog(machine(), 3, "vii_io_r: Controller IRQ Status = %04x (%04x)\n", val, mem_mask);
622	626	break;
623	627
624	628	case 0x2c: case 0x2d: // Timers?
625		val = space->machine().rand() & 0x0000ffff;
626		verboselog(space->machine(), 3, "vii_io_r: Unknown Timer %d Register = %04x (%04x)\n", offset - 0x2c, val, mem_mask);
	629	val = machine().rand() & 0x0000ffff;
	630	verboselog(machine(), 3, "vii_io_r: Unknown Timer %d Register = %04x (%04x)\n", offset - 0x2c, val, mem_mask);
627	631	break;
628	632
629	633	case 0x2f: // Data Segment
630		val = cpu_get_reg(space->machine().device("maincpu"), UNSP_SR) >> 10;
631		verboselog(space->machine(), 3, "vii_io_r: Data Segment = %04x (%04x)\n", val, mem_mask);
	634	val = cpu_get_reg(machine().device("maincpu"), UNSP_SR) >> 10;
	635	verboselog(machine(), 3, "vii_io_r: Data Segment = %04x (%04x)\n", val, mem_mask);
632	636	break;
633	637
634	638	case 0x31: // Unknown, UART Status?
635		verboselog(space->machine(), 3, "vii_io_r: Unknown (UART Status?) = %04x (%04x)\n", 3, mem_mask);
	639	verboselog(machine(), 3, "vii_io_r: Unknown (UART Status?) = %04x (%04x)\n", 3, mem_mask);
636	640	val = 3;
637	641	break;
638	642
639	643	case 0x36: // UART RX Data
640		val = state->m_controller_input[state->m_uart_rx_count];
641		state->m_uart_rx_count = (state->m_uart_rx_count + 1) % 8;
642		verboselog(space->machine(), 3, "vii_io_r: UART RX Data = %04x (%04x)\n", val, mem_mask);
	644	val = m_controller_input[m_uart_rx_count];
	645	m_uart_rx_count = (m_uart_rx_count + 1) % 8;
	646	verboselog(machine(), 3, "vii_io_r: UART RX Data = %04x (%04x)\n", val, mem_mask);
643	647	break;
644	648
645	649	case 0x59: // I2C Status
646		verboselog(space->machine(), 3, "vii_io_r: I2C Status = %04x (%04x)\n", val, mem_mask);
	650	verboselog(machine(), 3, "vii_io_r: I2C Status = %04x (%04x)\n", val, mem_mask);
647	651	break;
648	652
649	653	case 0x5e: // I2C Data In
650		verboselog(space->machine(), 3, "vii_io_r: I2C Data In = %04x (%04x)\n", val, mem_mask);
	654	verboselog(machine(), 3, "vii_io_r: I2C Data In = %04x (%04x)\n", val, mem_mask);
651	655	break;
652	656
653	657	default:
654		verboselog(space->machine(), 3, "vii_io_r: Unknown register %04x\n", 0x3d00 + offset);
	658	verboselog(machine(), 3, "vii_io_r: Unknown register %04x\n", 0x3d00 + offset);
655	659	break;
656	660	}
657	661
658	662	return val;
659	663	}
660	664
661		static WRITE16_HANDLER( vii_io_w )
	665	WRITE16_MEMBER( vii_state::vii_io_w )
662	666	{
663	667	static const char *const gpioregs[] = { "GPIO Data Port", "GPIO Buffer Port", "GPIO Direction Port", "GPIO Attribute Port", "GPIO IRQ/Latch Port" };
664	668	static const char gpioports[3] = { 'A', 'B', 'C' };
665	669
666		vii_state *state = space->machine().driver_data<vii_state>();
667	670	UINT16 temp = 0;
668	671
669	672	offset -= 0x500;
r12961	r12962
671	674	switch(offset)
672	675	{
673	676	case 0x00: // GPIO special function select
674		verboselog(space->machine(), 3, "vii_io_w: GPIO Function Select = %04x (%04x)\n", data, mem_mask);
675		COMBINE_DATA(&state->m_io_regs[offset]);
	677	verboselog(machine(), 3, "vii_io_w: GPIO Function Select = %04x (%04x)\n", data, mem_mask);
	678	COMBINE_DATA(&m_io_regs[offset]);
676	679	break;
677	680
678	681	case 0x01: case 0x06: case 0x0b: // GPIO data, port A/B/C
r12961	r12962
682	685	case 0x02: case 0x03: case 0x04: case 0x05: // Port A
683	686	case 0x07: case 0x08: case 0x09: case 0x0a: // Port B
684	687	case 0x0c: case 0x0d: case 0x0e: case 0x0f: // Port C
685		verboselog(space->machine(), 3, "vii_io_w: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], data, mem_mask);
686		COMBINE_DATA(&state->m_io_regs[offset]);
687		vii_do_gpio(space->machine(), offset);
	688	verboselog(machine(), 3, "vii_io_w: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], data, mem_mask);
	689	COMBINE_DATA(&m_io_regs[offset]);
	690	vii_do_gpio(offset);
688	691	break;
689	692
690	693	case 0x10:      // timebase control
691		if ((state->m_io_regs[offset] & 0x0003) != (data & 0x0003)) {
	694	if ((m_io_regs[offset] & 0x0003) != (data & 0x0003)) {
692	695	UINT16 hz = 8 << (data & 0x0003);
693		verboselog(space->machine(), 3, "*** TMB1 FREQ set to %dHz\n", hz);
694		state->m_tmb1->adjust(attotime::zero, 0, attotime::from_hz( hz ));
	696	verboselog(machine(), 3, "*** TMB1 FREQ set to %dHz\n", hz);
	697	m_tmb1->adjust(attotime::zero, 0, attotime::from_hz( hz ));
695	698	}
696		if ((state->m_io_regs[offset] & 0x000c) != (data & 0x000c)) {
	699	if ((m_io_regs[offset] & 0x000c) != (data & 0x000c)) {
697	700	UINT16 hz = 128 << ((data & 0x000c) >> 2);
698		verboselog(space->machine(), 3, "*** TMB2 FREQ set to %dHz\n", hz);
699		state->m_tmb2->adjust(attotime::zero, 0, attotime::from_hz( hz ));
	701	verboselog(machine(), 3, "*** TMB2 FREQ set to %dHz\n", hz);
	702	m_tmb2->adjust(attotime::zero, 0, attotime::from_hz( hz ));
700	703	}
701		COMBINE_DATA(&state->m_io_regs[offset]);
	704	COMBINE_DATA(&m_io_regs[offset]);
702	705	break;
703	706	case 0x21: // IRQ Enable
704		verboselog(space->machine(), 3, "vii_io_w: Controller IRQ Control = %04x (%04x)\n", data, mem_mask);
	707	verboselog(machine(), 3, "vii_io_w: Controller IRQ Control = %04x (%04x)\n", data, mem_mask);
705	708	COMBINE_DATA(&VII_CTLR_IRQ_ENABLE);
706	709	if(!VII_CTLR_IRQ_ENABLE)
707	710	{
708		cputag_set_input_line(space->machine(), "maincpu", UNSP_IRQ3_LINE, CLEAR_LINE);
	711	cputag_set_input_line(machine(), "maincpu", UNSP_IRQ3_LINE, CLEAR_LINE);
709	712	}
710	713	break;
711	714
712	715	case 0x22: // IRQ Acknowledge
713		verboselog(space->machine(), 3, "vii_io_w: Controller IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
714		state->m_io_regs[0x22] &= ~data;
715		if(!state->m_io_regs[0x22])
	716	verboselog(machine(), 3, "vii_io_w: Controller IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
	717	m_io_regs[0x22] &= ~data;
	718	if(!m_io_regs[0x22])
716	719	{
717		cputag_set_input_line(space->machine(), "maincpu", UNSP_IRQ3_LINE, CLEAR_LINE);
	720	cputag_set_input_line(machine(), "maincpu", UNSP_IRQ3_LINE, CLEAR_LINE);
718	721	}
719	722	break;
720	723
721	724	case 0x2f: // Data Segment
722		temp = cpu_get_reg(space->machine().device("maincpu"), UNSP_SR);
723		cpu_set_reg(space->machine().device("maincpu"), UNSP_SR, (temp & 0x03ff) | ((data & 0x3f) << 10));
724		verboselog(space->machine(), 3, "vii_io_w: Data Segment = %04x (%04x)\n", data, mem_mask);
	725	temp = cpu_get_reg(machine().device("maincpu"), UNSP_SR);
	726	cpu_set_reg(machine().device("maincpu"), UNSP_SR, (temp & 0x03ff) | ((data & 0x3f) << 10));
	727	verboselog(machine(), 3, "vii_io_w: Data Segment = %04x (%04x)\n", data, mem_mask);
725	728	break;
726	729
727	730	case 0x31: // Unknown UART
728		verboselog(space->machine(), 3, "vii_io_w: Unknown UART = %04x (%04x)\n", data, mem_mask);
729		COMBINE_DATA(&state->m_io_regs[offset]);
	731	verboselog(machine(), 3, "vii_io_w: Unknown UART = %04x (%04x)\n", data, mem_mask);
	732	COMBINE_DATA(&m_io_regs[offset]);
730	733	break;
731	734
732	735	case 0x32: // UART Reset
733		verboselog(space->machine(), 3, "vii_io_r: UART Reset\n");
	736	verboselog(machine(), 3, "vii_io_r: UART Reset\n");
734	737	break;
735	738
736	739	case 0x33: // UART Baud Rate
737		verboselog(space->machine(), 3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (state->m_io_regs[0x34] << 8) - data));
738		COMBINE_DATA(&state->m_io_regs[offset]);
	740	verboselog(machine(), 3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (m_io_regs[0x34] << 8) - data));
	741	COMBINE_DATA(&m_io_regs[offset]);
739	742	break;
740	743
741	744	case 0x35: // UART TX Data
742		verboselog(space->machine(), 3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (data << 8) - state->m_io_regs[0x33]));
743		COMBINE_DATA(&state->m_io_regs[offset]);
	745	verboselog(machine(), 3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (data << 8) - m_io_regs[0x33]));
	746	COMBINE_DATA(&m_io_regs[offset]);
744	747	break;
745	748
746	749	case 0x5a: // I2C Access Mode
747		verboselog(space->machine(), 3, "vii_io_w: I2C Access Mode = %04x (%04x)\n", data, mem_mask);
748		COMBINE_DATA(&state->m_io_regs[offset]);
	750	verboselog(machine(), 3, "vii_io_w: I2C Access Mode = %04x (%04x)\n", data, mem_mask);
	751	COMBINE_DATA(&m_io_regs[offset]);
749	752	break;
750	753
751	754	case 0x5b: // I2C Device Address
752		verboselog(space->machine(), 3, "vii_io_w: I2C Device Address = %04x (%04x)\n", data, mem_mask);
753		COMBINE_DATA(&state->m_io_regs[offset]);
	755	verboselog(machine(), 3, "vii_io_w: I2C Device Address = %04x (%04x)\n", data, mem_mask);
	756	COMBINE_DATA(&m_io_regs[offset]);
754	757	break;
755	758
756	759	case 0x5c: // I2C Sub-Address
757		verboselog(space->machine(), 3, "vii_io_w: I2C Sub-Address = %04x (%04x)\n", data, mem_mask);
758		COMBINE_DATA(&state->m_io_regs[offset]);
	760	verboselog(machine(), 3, "vii_io_w: I2C Sub-Address = %04x (%04x)\n", data, mem_mask);
	761	COMBINE_DATA(&m_io_regs[offset]);
759	762	break;
760	763
761	764	case 0x5d: // I2C Data Out
762		verboselog(space->machine(), 3, "vii_io_w: I2C Data Out = %04x (%04x)\n", data, mem_mask);
763		COMBINE_DATA(&state->m_io_regs[offset]);
	765	verboselog(machine(), 3, "vii_io_w: I2C Data Out = %04x (%04x)\n", data, mem_mask);
	766	COMBINE_DATA(&m_io_regs[offset]);
764	767	break;
765	768
766	769	case 0x5e: // I2C Data In
767		verboselog(space->machine(), 3, "vii_io_w: I2C Data In = %04x (%04x)\n", data, mem_mask);
768		COMBINE_DATA(&state->m_io_regs[offset]);
	770	verboselog(machine(), 3, "vii_io_w: I2C Data In = %04x (%04x)\n", data, mem_mask);
	771	COMBINE_DATA(&m_io_regs[offset]);
769	772	break;
770	773
771	774	case 0x5f: // I2C Controller Mode
772		verboselog(space->machine(), 3, "vii_io_w: I2C Controller Mode = %04x (%04x)\n", data, mem_mask);
773		COMBINE_DATA(&state->m_io_regs[offset]);
	775	verboselog(machine(), 3, "vii_io_w: I2C Controller Mode = %04x (%04x)\n", data, mem_mask);
	776	COMBINE_DATA(&m_io_regs[offset]);
774	777	break;
775	778
776	779	case 0x58: // I2C Command
777		verboselog(space->machine(), 3, "vii_io_w: I2C Command = %04x (%04x)\n", data, mem_mask);
778		COMBINE_DATA(&state->m_io_regs[offset]);
779		vii_do_i2c(space->machine());
	780	verboselog(machine(), 3, "vii_io_w: I2C Command = %04x (%04x)\n", data, mem_mask);
	781	COMBINE_DATA(&m_io_regs[offset]);
	782	vii_do_i2c();
780	783	break;
781	784
782	785	case 0x59: // I2C Status / IRQ Acknowledge(?)
783		verboselog(space->machine(), 3, "vii_io_w: I2C Status / Ack = %04x (%04x)\n", data, mem_mask);
784		state->m_io_regs[offset] &= ~data;
	786	verboselog(machine(), 3, "vii_io_w: I2C Status / Ack = %04x (%04x)\n", data, mem_mask);
	787	m_io_regs[offset] &= ~data;
785	788	break;
786	789
787	790	case 0x100: // DMA Source (L)
788	791	case 0x101: // DMA Source (H)
789	792	case 0x103: // DMA Destination
790		COMBINE_DATA(&state->m_io_regs[offset]);
	793	COMBINE_DATA(&m_io_regs[offset]);
791	794	break;
792	795
793	796	case 0x102: // DMA Length
794		spg_do_dma(space->machine(), data);
	797	spg_do_dma(data);
795	798	break;
796	799
797	800	default:
798		verboselog(space->machine(), 3, "vii_io_w: Unknown register %04x = %04x (%04x)\n", 0x3d00 + offset, data, mem_mask);
799		COMBINE_DATA(&state->m_io_regs[offset]);
	801	verboselog(machine(), 3, "vii_io_w: Unknown register %04x = %04x (%04x)\n", 0x3d00 + offset, data, mem_mask);
	802	COMBINE_DATA(&m_io_regs[offset]);
800	803	break;
801	804	}
802	805	}
803	806
804	807	/*
805		static WRITE16_HANDLER( vii_rowscroll_w )
	808	WRITE16_MEMBER( vii_state::vii_rowscroll_w )
806	809	{
807	810	switch(offset)
808	811	{
809	812	default:
810		verboselog(space->machine(), 0, "vii_rowscroll_w: %04x = %04x (%04x)\n", 0x2900 + offset, data, mem_mask);
	813	verboselog(machine(), 0, "vii_rowscroll_w: %04x = %04x (%04x)\n", 0x2900 + offset, data, mem_mask);
811	814	break;
812	815	}
813	816	}
814	817
815		static WRITE16_HANDLER( vii_spriteram_w )
	818	WRITE16_MEMBER( vii_state::vii_spriteram_w )
816	819	{
817	820	switch(offset)
818	821	{
819	822	default:
820		verboselog(space->machine(), 0, "vii_spriteram_w: %04x = %04x (%04x)\n", 0x2c00 + offset, data, mem_mask);
	823	verboselog(machine(), 0, "vii_spriteram_w: %04x = %04x (%04x)\n", 0x2c00 + offset, data, mem_mask);
821	824	break;
822	825	}
823	826	}
824	827	*/
825	828
826		static ADDRESS_MAP_START( vii_mem, AS_PROGRAM, 16 )
827		AM_RANGE( 0x000000, 0x004fff ) AM_RAM AM_BASE_MEMBER(vii_state,m_ram)
	829	static ADDRESS_MAP_START( vii_mem, AS_PROGRAM, 16, vii_state )
	830	AM_RANGE( 0x000000, 0x004fff ) AM_RAM AM_BASE(m_p_ram)
828	831	AM_RANGE( 0x005000, 0x0051ff ) AM_READWRITE(vii_video_r, vii_video_w)
829		AM_RANGE( 0x005200, 0x0055ff ) AM_RAM AM_BASE_MEMBER(vii_state,m_rowscroll)
830		AM_RANGE( 0x005600, 0x0057ff ) AM_RAM AM_BASE_MEMBER(vii_state,m_palette)
831		AM_RANGE( 0x005800, 0x005fff ) AM_RAM AM_BASE_MEMBER(vii_state,m_spriteram)
	832	AM_RANGE( 0x005200, 0x0055ff ) AM_RAM AM_BASE(m_p_rowscroll)
	833	AM_RANGE( 0x005600, 0x0057ff ) AM_RAM AM_BASE(m_p_palette)
	834	AM_RANGE( 0x005800, 0x005fff ) AM_RAM AM_BASE(m_p_spriteram)
832	835	AM_RANGE( 0x006000, 0x006fff ) AM_READWRITE(vii_audio_r, vii_audio_w)
833	836	AM_RANGE( 0x007000, 0x007fff ) AM_READWRITE(vii_io_r,    vii_io_w)
834		AM_RANGE( 0x008000, 0x7fffff ) AM_ROM AM_BASE_MEMBER(vii_state,m_cart)
	837	AM_RANGE( 0x008000, 0x7fffff ) AM_ROM AM_BASE(m_p_cart)
835	838	ADDRESS_MAP_END
836	839
837	840	static INPUT_PORTS_START( vii )
r12961	r12962
843	846	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )        PORT_PLAYER(1) PORT_NAME("Button A")
844	847	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 )        PORT_PLAYER(1) PORT_NAME("Button B")
845	848	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON3 )        PORT_PLAYER(1) PORT_NAME("Button C")
846		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON4 )      PORT_PLAYER(1) PORT_NAME("Button D")
	849	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON4 )        PORT_PLAYER(1) PORT_NAME("Button D")
847	850	INPUT_PORTS_END
848	851
849	852	static INPUT_PORTS_START( batman )
r12961	r12962
855	858	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )        PORT_PLAYER(1) PORT_NAME("A Button")
856	859	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 )        PORT_PLAYER(1) PORT_NAME("Menu")
857	860	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON3 )        PORT_PLAYER(1) PORT_NAME("B Button")
858		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON4 )      PORT_PLAYER(1) PORT_NAME("X Button")
	861	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON4 )        PORT_PLAYER(1) PORT_NAME("X Button")
859	862	INPUT_PORTS_END
860	863
861	864	static INPUT_PORTS_START( vsmile )
r12961	r12962
867	870	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )        PORT_PLAYER(1) PORT_NAME("A Button")
868	871	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 )        PORT_PLAYER(1) PORT_NAME("Menu")
869	872	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON3 )        PORT_PLAYER(1) PORT_NAME("B Button")
870		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON4 )      PORT_PLAYER(1) PORT_NAME("X Button")
	873	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON4 )        PORT_PLAYER(1) PORT_NAME("X Button")
871	874	INPUT_PORTS_END
872	875
873	876	static INPUT_PORTS_START( walle )
r12961	r12962
898	901	memcpy(cart, image.get_software_region("rom"), filesize);
899	902	}
900	903
901		memcpy(state->m_cart, cart + 0x4000*2, (0x400000 - 0x4000) * 2);
	904	memcpy(state->m_p_cart, cart + 0x4000*2, (0x400000 - 0x4000) * 2);
902	905
903	906	if( cart[0x3cd808] == 0x99 &&
904	907	cart[0x3cd809] == 0x99 &&
r12961	r12962
933	936	int filesize = image.get_software_region_length("rom");
934	937	memcpy(cart, image.get_software_region("rom"), filesize);
935	938	}
936		memcpy(state->m_cart, cart + 0x4000*2, (0x400000 - 0x4000) * 2);
	939	memcpy(state->m_p_cart, cart + 0x4000*2, (0x400000 - 0x4000) * 2);
937	940	return IMAGE_INIT_PASS;
938	941	}
939	942
r12961	r12962
963	966	state->m_controller_input[7] = 0;
964	967
965	968	UINT8 *rom = machine.region( "cart" )->base();
966		if (rom) { // to prevent batman crash
967		memcpy(state->m_cart, rom + 0x4000*2, (0x400000 - 0x4000) * 2);
	969	if (rom)
	970	{ // to prevent batman crash
	971	memcpy(state->m_p_cart, rom + 0x4000*2, (0x400000 - 0x4000) * 2);
968	972	}
969	973
970	974	state->m_video_regs[0x36] = 0xffff;
r12961	r12962
1002	1006
1003	1007	state->m_uart_rx_count = 0;
1004	1008
1005		VII_VIDEO_IRQ_STATUS = VII_VIDEO_IRQ_ENABLE & 1;
1006		if(VII_VIDEO_IRQ_STATUS)
	1009	state->VII_VIDEO_IRQ_STATUS = state->VII_VIDEO_IRQ_ENABLE & 1;
	1010	if(state->VII_VIDEO_IRQ_STATUS)
1007	1011	{
1008	1012	verboselog(device->machine(), 0, "Video IRQ\n");
1009	1013	cputag_set_input_line(device->machine(), "maincpu", UNSP_IRQ0_LINE, ASSERT_LINE);
r12961	r12962
1021	1025
1022	1026	//if(state->m_io_regs[0x22] & state->m_io_regs[0x22] & 0x2100)
1023	1027	// For now trigger always if any enabled
1024		if(VII_CTLR_IRQ_ENABLE)
	1028	if(state->VII_CTLR_IRQ_ENABLE)
1025	1029	{
1026	1030	verboselog(device->machine(), 0, "UART, ADC IRQ\n");
1027	1031	cputag_set_input_line(device->machine(), "maincpu", UNSP_IRQ3_LINE, ASSERT_LINE);
r12961	r12962
1105	1109
1106	1110	static const i2cmem_interface i2cmem_interface =
1107	1111	{
1108		I2CMEM_SLAVE_ADDRESS, 0, 0x200
	1112	I2CMEM_SLAVE_ADDRESS, 0, 0x200
1109	1113	};
1110	1114
1111	1115	static MACHINE_CONFIG_START( batman, vii_state )
r12961	r12962
1186	1190	ROM_START( walle )
1187	1191	ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASEFF )      /* dummy region for u'nSP */
1188	1192	ROM_LOAD16_WORD_SWAP( "walle.bin", 0x000000, 0x400000, BAD_DUMP CRC(bd554cba) SHA1(6cd06a036ab12e7b0e1fd8003db873b0bb783868) )
	1193	// This is another dump, seems to be better, you can move around the playfield for example.
	1194	//ROM_LOAD16_WORD_SWAP( "walle.bin", 0x000000, 0x400000, CRC(6bc90b16) SHA1(184d72de059057aae7800da510fcf05ed1da9ec9))
1189	1195	ROM_END
1190	1196
1191		/*    YEAR  NAME     PARENT    COMPAT    MACHINE   INPUT     INIT      COMPANY                                              FULLNAME      FLAGS */
1192		CONS( 2004, batmantv, 0,        0,        batman,   batman,   batman,   "JAKKS Pacific Inc / HotGen Ltd",                "The Batman", GAME_NO_SOUND )
1193		CONS( 2005, vsmile,  0,        0,        vsmile,   vsmile,   vsmile,   "V-Tech",                                            "V-Smile",    GAME_NO_SOUND | GAME_NOT_WORKING )
1194		CONS( 2007, vii,     0,        0,        vii,      vii,      vii,      "Jungle Soft / KenSingTon / Chintendo / Siatronics", "Vii",        GAME_NO_SOUND )
1195		CONS( 2008, walle,  0,        0,        batman,   walle,   walle,   "JAKKS Pacific Inc",                                            "Wall-E",    GAME_NO_SOUND | GAME_NOT_WORKING )
	1197	/*    YEAR  NAME      PARENT    COMPAT    MACHINE   INPUT     INIT      COMPANY                                              FULLNAME      FLAGS */
	1198	CONS( 2004, batmantv, vii,      0,        batman,   batman,   batman,   "JAKKS Pacific Inc / HotGen Ltd",                    "The Batman", GAME_NO_SOUND )
	1199	CONS( 2005, vsmile,   vii,      0,        vsmile,   vsmile,   vsmile,   "V-Tech",                                            "V-Smile",    GAME_NO_SOUND | GAME_NOT_WORKING )
	1200	CONS( 2007, vii,      0,        0,        vii,      vii,      vii,      "Jungle Soft / KenSingTon / Chintendo / Siatronics", "Vii",        GAME_NO_SOUND )
	1201	CONS( 2008, walle,    vii,      0,        batman,   walle,    walle,    "JAKKS Pacific Inc",                                 "Wall-E",     GAME_NO_SOUND | GAME_NOT_WORKING )

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