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r12905 Wednesday 21st September, 2011 at 06:59:01 UTC by Miodrag Milanović
Source cleanup (no whatsnew)

[src/emu/machine]	z8536.c z8536.h
[src/mess/drivers]	abc1600.c apple2gs.c at.c bml3.c comx35.c einstein.c intv.c mac.c nakajies.c tdv2324.c vt100.c vt240.c
[src/mess/includes]	einstein.h tdv2324.h
[src/mess/machine]	dp8390.c intv.c nubus.c nubus_asntmc3b.c tms9902.c wd1772.c wd1772.h x68kexp.h
[src/mess/tools/floptool]	main.c
[src/mess/video]	nubus_radiustpd.c

src/emu/machine/z8536.c

r12904	r12905
271	271	if ((m_register[COUNTER_TIMER_3_COMMAND_AND_STATUS] & (CTCS_IP | CTCS_IE)) == (CTCS_IP | CTCS_IE))
272	272	{
273	273	vector = m_register[COUNTER_TIMER_INTERRUPT_VECTOR];
274
	274
275	275	if (m_register[MASTER_INTERRUPT_CONTROL] & MICR_CT_VIS)
276	276	{
277	277	vector = (vector & 0xf9) | 0;
r12904	r12905
296	296	else if ((m_register[COUNTER_TIMER_2_COMMAND_AND_STATUS] & (CTCS_IP | CTCS_IE)) == (CTCS_IP | CTCS_IE))
297	297	{
298	298	vector = m_register[COUNTER_TIMER_INTERRUPT_VECTOR];
299
	299
300	300	if (m_register[MASTER_INTERRUPT_CONTROL] & MICR_CT_VIS)
301	301	{
302	302	vector = (vector & 0xf9) | 1;
r12904	r12905
321	321	else if ((m_register[COUNTER_TIMER_1_COMMAND_AND_STATUS] & (CTCS_IP | CTCS_IE)) == (CTCS_IP | CTCS_IE))
322	322	{
323	323	vector = m_register[COUNTER_TIMER_INTERRUPT_VECTOR];
324
	324
325	325	if (m_register[MASTER_INTERRUPT_CONTROL] & MICR_CT_VIS)
326	326	{
327	327	vector = (vector & 0xf9) | 2;
r12904	r12905
331	331	{
332	332	state = CLEAR_LINE;
333	333	}
334
	334
335	335	m_register[CURRENT_VECTOR] = vector;
336
	336
337	337	if (m_int != state)
338	338	{
339	339	if (LOG) logerror("Z8536 '%s' Interrupt: %u\n", tag(), state);
r12904	r12905
405	405	{
406	406	m_state = STATE_0;
407	407	}
408
	408
409	409	if (LOG)
410	410	{
411	411	logerror("Z8536 '%s' Master Interrupt Enable: %u\n", tag(), (data & MICR_MIE) ? 1 : 0);
r12904	r12905
421	421	check_interrupt();
422	422	}
423	423	break;
424
	424
425	425	case MASTER_CONFIGURATION_CONTROL:
426	426	if (LOG)
427	427	{
r12904	r12905
433	433	logerror("Z8536 '%s' Port Link Control: %u\n", tag(), (data & MCCR_PLC) ? 1 : 0);
434	434	logerror("Z8536 '%s' Counter/Timer Link Controls: %u\n", tag(), data & MCCR_LC_MASK);
435	435	}
436
	436
437	437	m_register[offset] = data;
438	438	break;
439
	439
440	440	case PORT_A_INTERRUPT_VECTOR:
441	441	if (LOG) logerror("Z8536 '%s' Port A Interrupt Vector: %02x\n", tag(), data);
442	442	m_register[offset] = data;
443	443	break;
444
	444
445	445	case PORT_B_INTERRUPT_VECTOR:
446	446	if (LOG) logerror("Z8536 '%s' Port B Interrupt Vector: %02x\n", tag(), data);
447	447	m_register[offset] = data;
r12904	r12905
451	451	if (LOG) logerror("Z8536 '%s' Counter/Timer Interrupt Vector: %02x\n", tag(), data);
452	452	m_register[offset] = data;
453	453	break;
454
	454
455	455	case PORT_C_DATA_DIRECTION:
456	456	if (LOG) logerror("Z8536 '%s' Port C Data Direction: %02x\n", tag(), data);
457	457	m_register[offset] = data;
458	458	break;
459
	459
460	460	case PORT_A_COMMAND_AND_STATUS:
461	461	case PORT_B_COMMAND_AND_STATUS:
462	462	{
463	463	char port = 'A' + offset - PORT_A_COMMAND_AND_STATUS;
464
	464
465	465	if (LOG) logerror("Z8536 '%s' Port %c Interrupt on Error: %u\n", tag(), port, (data & PCS_IOE) ? 1 : 0);
466
	466
467	467	switch (data >> 5)
468	468	{
469	469	case IC_CLEAR_IP_IUS:   m_register[offset] &= ~(PCS_IP | PCS_IUS);   if (LOG) logerror("Z8536 '%s' Port %c Clear IP/IUS\n", tag(), port);   break;
r12904	r12905
476	476	}
477	477
478	478	m_register[offset] = (m_register[offset] & 0xfe) | (data & 0x01);
479
	479
480	480	check_interrupt();
481	481	}
482	482	break;
483
	483
484	484	case PORT_A_DATA:
485	485	m_out_pa_func(0, data);
486	486	break;
r12904	r12905
498	498	m_out_pc_func(0, m_output[PORT_C]);
499	499	}
500	500	break;
501
	501
502	502	case COUNTER_TIMER_1_MODE_SPECIFICATION:
503	503	case COUNTER_TIMER_2_MODE_SPECIFICATION:
504	504	case COUNTER_TIMER_3_MODE_SPECIFICATION:
505	505	if (LOG)
506	506	{
507	507	int counter = offset - COUNTER_TIMER_1_MODE_SPECIFICATION;
508
	508
509	509	logerror("Z8536 '%s' Counter/Timer %u Mode: %s\n", tag(), counter, (data & CTMS_CSC) ? "Continuous" : "Single Cycle");
510	510	logerror("Z8536 '%s' Counter/Timer %u External Output Enable: %u\n", tag(), counter, (data & CTMS_EOE) ? 1 : 0);
511	511	logerror("Z8536 '%s' Counter/Timer %u External Count Enable: %u\n", tag(), counter, (data & CTMS_ECE) ? 1 : 0);
r12904	r12905
543	543	inline void z8536_device::count(device_timer_id id)
544	544	{
545	545	if (!m_gate[id]) return;
546
	546
547	547	// count down
548	548	m_counter[id]--;
549
	549
550	550	if (m_counter == 0)
551	551	{
552	552	// clear count in progress bit
r12904	r12905
557	557	// set interrupt error bit
558	558	m_register[COUNTER_TIMER_1_COMMAND_AND_STATUS + id] |= CTCS_ERR;
559	559	}
560
	560
561	561	// set interrupt pending bit
562	562	m_register[COUNTER_TIMER_1_COMMAND_AND_STATUS + id] |= CTCS_IP;
563
	563
564	564	check_interrupt();
565	565	}
566	566	}
r12904	r12905
574	574	{
575	575	// load counter with time constant
576	576	m_counter[id] = (m_register[COUNTER_TIMER_1_TIME_CONSTANT_MS_BYTE + (id << 1)] << 8) | m_register[COUNTER_TIMER_1_TIME_CONSTANT_LS_BYTE + (id << 1)];
577
	577
578	578	// set count in progress bit
579	579	m_register[COUNTER_TIMER_1_COMMAND_AND_STATUS + id] |= CTCS_CIP;
580	580	}
r12904	r12905
672	672	m_register[PORT_A_COMMAND_AND_STATUS] = PCS_ORE;
673	673	m_register[PORT_B_COMMAND_AND_STATUS] = PCS_ORE;
674	674	m_register[CURRENT_VECTOR] = 0xff;
675
	675
676	676	m_pointer = 0;
677
	677
678	678	check_interrupt();
679	679	}
680	680
r12904	r12905
690	690	{
691	691	count(TIMER_1);
692	692	}
693
	693
694	694	if ((m_register[MASTER_CONFIGURATION_CONTROL] & MCCR_CT2E) &&
695	695	!(m_register[COUNTER_TIMER_2_MODE_SPECIFICATION] & CTMS_ECE))
696	696	{
697	697	count(TIMER_2);
698	698	}
699
	699
700	700	if ((m_register[MASTER_CONFIGURATION_CONTROL] & MCCR_PCE_CT3E) &&
701	701	!(m_register[COUNTER_TIMER_3_MODE_SPECIFICATION] & CTMS_ECE))
702	702	{
r12904	r12905
846	846	UINT8 z8536_device::intack_r()
847	847	{
848	848	UINT8 data = m_register[CURRENT_VECTOR];
849
	849
850	850	if (LOG) logerror("Z8536 '%s' Interrupt Acknowledge: %02x\n", tag(), data);
851
	851
852	852	if (m_register[MASTER_INTERRUPT_CONTROL] & MICR_NV)
853	853	{
854	854	data = 0;
855	855	}
856
	856
857	857	return data;
858	858	}
859	859

src/emu/machine/z8536.h

r12904	r12905
154	154	UINT8 m_input[3];
155	155	UINT8 m_output[3];
156	156	UINT8 m_buffer[3];
157
	157
158	158	int m_int;
159	159
160	160	// timers

src/mess/tools/floptool/main.c

r12904	r12905
31	31
32	32	FLOPPY_ST_FORMAT,
33	33	FLOPPY_MSA_FORMAT,
34
	34
35	35	FLOPPY_DSK_FORMAT
36	36	};
37	37
r12904	r12905
106	106	return 1;
107	107	}
108	108
109		for(int i=2; i<argc; i++) {
	109	for(int i=2; i<argc; i++) {
110	110	char msg[4096];
111	111	sprintf(msg, "Error opening %s for reading", argv[i]);
112	112	FILE *f = fopen(argv[i], "rb");
r12904	r12905
163	163	if(!source_format) {
164	164	fprintf(stderr, "Error: Format '%s' unknown\n", argv[2]);
165	165	return 1;
166		}
	166	}
167	167	}
168	168
169	169	dest_format = find_format_by_name(argv[3]);

src/mess/machine/wd1772.c

r12904	r12905
116	116	status &= ~S_BUSY;
117	117	intrq = true;
118	118	motor_timeout = 0;
119		//   fprintf(stderr, "%s: command status %02x\n", ttsn().cstr(), status);
	119	//  fprintf(stderr, "%s: command status %02x\n", ttsn().cstr(), status);
120	120	if(!intrq_cb.isnull())
121	121	intrq_cb(intrq);
122	122	}
r12904	r12905
188	188	done = true;
189	189	break;
190	190	}
191
	191
192	192	if(done || counter == 255) {
193	193	switch(main_state) {
194	194	case RESTORE:
195	195	track = 0;
196	196	break;
197		case STEP:
	197	case STEP:
198	198	if(command & 0x10)
199	199	track += last_dir ? -1 : 1;
200	200	break;
201	201	}
202
	202
203	203	if(command & 0x04) {
204	204	sub_state = SEEK_WAIT_STABILIZATION_TIME;
205	205	delay_cycles(t_gen, 120000);
r12904	r12905
252	252	logerror("%s: seek unknown sub-state %d\n", ttsn().cstr(), sub_state);
253	253	return;
254	254	}
255		}
	255	}
256	256	}
257	257
258	258	void wd1772_t::read_sector_start()
r12904	r12905
268	268	void wd1772_t::read_sector_continue()
269	269	{
270	270	static int size_codes[4] = { 128, 256, 512, 1024 };
271
	271
272	272	for(;;) {
273	273	switch(sub_state) {
274	274	case SPINUP:
r12904	r12905
382	382	case SEEK_WAIT_STABILIZATION_TIME:
383	383	sub_state = SEEK_WAIT_STABILIZATION_TIME_DONE;
384	384	break;
385
	385
386	386	default:
387		if(cur_live.tm.is_never())
	387	if(cur_live.tm.is_never())
388	388	logerror("%s: do_generic on unknown sub-state %d\n", ttsn().cstr(), sub_state);
389	389	break;
390	390	}
r12904	r12905
392	392
393	393	void wd1772_t::do_cmd_w()
394	394	{
395		//   fprintf(stderr, "%s: command %02x\n", ttsn().cstr(), cmd_buffer);
	395	//  fprintf(stderr, "%s: command %02x\n", ttsn().cstr(), cmd_buffer);
396	396
397	397	// Only available command when busy is interrupt
398	398	if(main_state != IDLE && (cmd_buffer & 0xf0) != 0xd0) {
r12904	r12905
665	665	{
666	666	if(!cur_live.tm.is_never()) {
667	667	if(cur_live.tm > machine().time()) {
668		//         fprintf(stderr, "%s: Rolling back and replaying (%s)\n", ttsn().cstr(), tts(cur_live.tm).cstr());
	668	//          fprintf(stderr, "%s: Rolling back and replaying (%s)\n", ttsn().cstr(), tts(cur_live.tm).cstr());
669	669	rollback();
670	670	live_run(machine().time());
671	671	} else {
672		//         fprintf(stderr, "%s: Committing (%s)\n", ttsn().cstr(), tts(cur_live.tm).cstr());
	672	//          fprintf(stderr, "%s: Committing (%s)\n", ttsn().cstr(), tts(cur_live.tm).cstr());
673	673	if(cur_live.next_state != -1)
674	674	cur_live.state = cur_live.next_state;
675	675	if(cur_live.state == IDLE)
r12904	r12905
714	714	limit = machine().time() + attotime::from_msec(1);
715	715	t_gen->adjust(attotime::from_msec(1));
716	716	}
717		}
718
719		//   fprintf(stderr, "%s: live_run(%s)\n", ttsn().cstr(), tts(limit).cstr());
	717	}
720	718
	719	//  fprintf(stderr, "%s: live_run(%s)\n", ttsn().cstr(), tts(limit).cstr());
	720
721	721	for(;;) {
722	722	switch(cur_live.state) {
723	723	case SEARCH_ADDRESS_MARK:
r12904	r12905
831	831	return;
832	832	}
833	833	}
834
	834
835	835	break;
836	836	}
837	837
r12904	r12905
897	897	#endif
898	898
899	899	for(;;) {
900		//      fprintf(stderr, "slot=%2d, counter=%03x\n", slot, counter);
	900	//      fprintf(stderr, "slot=%2d, counter=%03x\n", slot, counter);
901	901	attotime etime = ctime+delays[slot];
902		//      fprintf(stderr, "etime=%s\n", tts(etime).cstr());
	902	//      fprintf(stderr, "etime=%s\n", tts(etime).cstr());
903	903	if(etime > limit)
904	904	return -1;
905	905	if(transition_time == 0xffff && !when.is_never() && etime >= when)
r12904	r12905
925	925	if(counter & 0x800)
926	926	break;
927	927	}
928		//   fprintf(stderr, "first transition, time=%03x, inc=%3d\n", transition_time, increment);
	928	//  fprintf(stderr, "first transition, time=%03x, inc=%3d\n", transition_time, increment);
929	929	int bit = transition_time != 0xffff;
930	930
931	931	if(transition_time != 0xffff) {

src/mess/machine/wd1772.h

r12904	r12905
35	35
36	36	bool intrq_r();
37	37	bool drq_r();
38
	38
39	39	DECLARE_READ8_MEMBER( read ) { return gen_r(offset);}
40	40	DECLARE_WRITE8_MEMBER( write ) { gen_w(offset,data); }
41	41

src/mess/machine/x68kexp.h

r12904	r12905
5	5	*
6	6	* Pinout: (from http://www.amy.hi-ho.ne.jp/shimada/neptune/x68k.html)
7	7	+-----+
8		GND       B1  |[] []| A1      GND
9		10MHz   B2  |[] []| A2      20MHz
10		#10MHz  B3  |[] []| A3      GND
11		E       B4  |[] []| A4      DB0
12		AB1     B5  |[] []| A5      DB1
13		AB2     B6  |[] []| A6      DB2
14		AB3     B7  |[] []| A7      DB3
15		AB4     B8  |[] []| A8      DB4
16		AB5     B9  |[] []| A9      DB5
17		AB6     B10 |[] []| A10      DB6
18		GND     B11 |[] []| A11      GND
19		AB7     B12 |[] []| A12      DB7
20		AB8     B13 |[] []| A13      DB8
21		AB9     B14 |[] []| A14      DB9
22		AB10    B15 |[] []| A15      DB10
23		AB11    B16 |[] []| A16      DB11
24		AB12    B17 |[] []| A17      DB12
25		AB13    B18 |[] []| A18      DB13
26		AB14    B19 |[] []| A19      DB14
27		AB15    B20 |[] []| A20      DB15
28		GND     B21 |[] []| A21      GND
29		AB16    B22 |[] []| A22      +12V
30		AB17    B23 |[] []| A23      +12V
31		AB18    B24 |[] []| A24      FC0
32		AB19    B25 |[] []| A25      FC1
33		AB20    B26 |[] []| A26      FC2
34		AB21    B27 |[] []| A27      #AS
35		AB22    B28 |[] []| A28      #LDS
36		AB23    B29 |[] []| A29      #UDS
37		IDDIR   B30 |[] []| A30      R/#W
38		N.C.    B31 |[] []| A31      N.C.
39		HSYNC   B32 |[] []| A32      -12V
40		VSYNC   B33 |[] []| A33      -12V
41		#DONE   B34 |[] []| A34      #VMA
42		#DTC    B35 |[] []| A35      #EXVPA
43		#EXREQ  B36 |[] []| A36      #DTACK
44		#EXACK  B37 |[] []| A37      #EXRESET
45		#EXPCL  B38 |[] []| A38      #HALT
46		#EXOWN  B39 |[] []| A39      #EXBERR
47		#EXNMI  B40 |[] []| A40      #EXPWON
48		GND     B41 |[] []| A41      GND
49		#IRQ2   B42 |[] []| A42      Vcc2
50		#IRQ4   B43 |[] []| A43      Vcc2
51		#IACK2  B44 |[] []| A44      SELEN
52		#IACK4  B45 |[] []| A45      CASRDEN
53		#BR     B46 |[] []| A46      CASWRL
54		#BG     B47 |[] []| A47      CASWRU
55		#BGACK  B48 |[] []| A48      INH2
56		Vcc1    B49 |[] []| A49      Vcc1
57		Vcc1    B50 |[] []| A50      Vcc1
	8	GND     B1  |[] []| A1      GND
	9	10MHz   B2  |[] []| A2      20MHz
	10	#10MHz  B3  |[] []| A3      GND
	11	E       B4  |[] []| A4      DB0
	12	AB1     B5  |[] []| A5      DB1
	13	AB2     B6  |[] []| A6      DB2
	14	AB3     B7  |[] []| A7      DB3
	15	AB4     B8  |[] []| A8      DB4
	16	AB5     B9  |[] []| A9      DB5
	17	AB6     B10 |[] []| A10     DB6
	18	GND     B11 |[] []| A11     GND
	19	AB7     B12 |[] []| A12     DB7
	20	AB8     B13 |[] []| A13     DB8
	21	AB9     B14 |[] []| A14     DB9
	22	AB10    B15 |[] []| A15     DB10
	23	AB11    B16 |[] []| A16     DB11
	24	AB12    B17 |[] []| A17     DB12
	25	AB13    B18 |[] []| A18     DB13
	26	AB14    B19 |[] []| A19     DB14
	27	AB15    B20 |[] []| A20     DB15
	28	GND     B21 |[] []| A21     GND
	29	AB16    B22 |[] []| A22     +12V
	30	AB17    B23 |[] []| A23     +12V
	31	AB18    B24 |[] []| A24     FC0
	32	AB19    B25 |[] []| A25     FC1
	33	AB20    B26 |[] []| A26     FC2
	34	AB21    B27 |[] []| A27     #AS
	35	AB22    B28 |[] []| A28     #LDS
	36	AB23    B29 |[] []| A29     #UDS
	37	IDDIR   B30 |[] []| A30     R/#W
	38	N.C.    B31 |[] []| A31     N.C.
	39	HSYNC   B32 |[] []| A32     -12V
	40	VSYNC   B33 |[] []| A33     -12V
	41	#DONE   B34 |[] []| A34     #VMA
	42	#DTC    B35 |[] []| A35     #EXVPA
	43	#EXREQ  B36 |[] []| A36     #DTACK
	44	#EXACK  B37 |[] []| A37     #EXRESET
	45	#EXPCL  B38 |[] []| A38     #HALT
	46	#EXOWN  B39 |[] []| A39     #EXBERR
	47	#EXNMI  B40 |[] []| A40     #EXPWON
	48	GND     B41 |[] []| A41     GND
	49	#IRQ2   B42 |[] []| A42     Vcc2
	50	#IRQ4   B43 |[] []| A43     Vcc2
	51	#IACK2  B44 |[] []| A44     SELEN
	52	#IACK4  B45 |[] []| A45     CASRDEN
	53	#BR     B46 |[] []| A46     CASWRL
	54	#BG     B47 |[] []| A47     CASWRU
	55	#BGACK  B48 |[] []| A48     INH2
	56	Vcc1    B49 |[] []| A49     Vcc1
	57	Vcc1    B50 |[] []| A50     Vcc1
58	58	+-----+
59	59	*
60	60	*/

src/mess/machine/tms9902.c

r12904	r12905
66	66	bool LRDR;         // Load receive data register
67	67	bool LXDR;         // Load transmit data register
68	68	bool TSTMD;         // Test mode
69
	69
70	70	/* output pin */
71	71	bool RTSON;         // RTS-on request
72	72
r12904	r12905
75	75	bool BRKout;      // indicates the current BRK state
76	76
77	77	UINT8 XBR;         // transmit buffer register
78		UINT8 XSR;         // transmit shift register
	78	UINT8 XSR;         // transmit shift register
79	79
80	80	/* receiver registers */
81		UINT8 RBR;         // Receive buffer register
	81	UINT8 RBR;         // Receive buffer register
82	82
83	83	/* Interrupt enable flags */
84	84	bool DSCENB;      // Data set change interrupt enable
r12904	r12905
200	200	tms9902->DSCH = true;
201	201	field_interrupts(device);
202	202
203		// If CTS becomes asserted and we have been sending
	203	// If CTS becomes asserted and we have been sending
204	204	if (state==ASSERT_LINE && tms9902->RTSout)
205	205	{
206	206	// and if the byte buffer is empty
207	207	if (tms9902->XBRE)
208	208	{
209	209	// and we want to have a BRK, send it
210		if (tms9902->BRKON)
	210	if (tms9902->BRKON)
211	211	send_break(device, true);
212	212	}
213	213	else
r12904	r12905
660	660	tms9902->RTSout = true;      // Note we are doing this to ensure the state is sent to the interface
661	661	set_rts(device, CLEAR_LINE);
662	662	tms9902->RTSout = false;   // what we actually want
663
	663
664	664	/* set all register load flags to 1 */
665	665	tms9902->LDCTRL = true;
666	666	tms9902->LDIR = true;
667	667	tms9902->LRDR = true;
668	668	tms9902->LXDR = true;
669
	669
670	670	/* clear break condition */
671	671	tms9902->BRKON = false;
672	672	tms9902->BRKout = false;
r12904	r12905
691	691	UINT16 mask = (1 << offset);
692	692
693	693	if (tms9902->LDCTRL)
694		{   // Control Register mode. Values written to bits 0-7 are copied
	694	{   // Control Register mode. Values written to bits 0-7 are copied
695	695	// into the control register.
696	696	switch (offset)
697	697	{
r12904	r12905
733	733	}
734	734	else if (tms9902->LDIR)
735	735	{   // Interval Register mode. Values written to bits 0-7 are copied
736		// into the interval register.
	736	// into the interval register.
737	737	if (offset <= 7)
738	738	{
739	739	set_bits8(&tms9902->TMR, mask, (data!=0));
r12904	r12905
746	746	}
747	747	}
748	748	}
749		else if (tms9902->LRDR || tms9902->LXDR)
750		{
	749	else if (tms9902->LRDR || tms9902->LXDR)
	750	{
751	751	if (tms9902->LRDR)
752	752	{   // Receive rate register mode. Values written to bits 0-10 are copied
753	753	// into the receive rate register.
r12904	r12905
755	755	{
756	756	set_bits16(&tms9902->RDR, mask, (data!=0));
757	757	}
758		else
	758	else
759	759	{
760	760	// When bit 10 is written the receive register mode is automatically terminated.
761	761	tms9902->RDV8 = (data!=0);
r12904	r12905
792	792	// Spec: When the transmitter is active, the contents of the Transmit
793	793	// Buffer Register are transferred to the Transmit Shift Register
794	794	// each time the previous character has been completely transmitted
795		// We need to check XSRE=true as well, as the implementation
	795	// We need to check XSRE=true as well, as the implementation
796	796	// makes use of a timed transmission, during which XSRE=false
797	797	if (tms9902->XSRE && tms9902->RTSout && tms9902->CTSin && !tms9902->BRKout)
798	798	{
r12904	r12905
813	813	break;
814	814	case 13:
815	815	tms9902->LDIR = (data!=0);
816		// Spec: Each time LDIR is reset the contents of the Interval
	816	// Spec: Each time LDIR is reset the contents of the Interval
817	817	// Register are loaded into the Interval Timer, thus restarting
818	818	// the timer.
819		if (data==0)
	819	if (data==0)
820	820	reload_interval_timer(device);
821	821	break;
822	822	case 14:
r12904	r12905
869	869	{
870	870	send_break(device, (data!=0));
871	871	}
872		return;
	872	return;
873	873	case 18:
874	874	// Receiver Interrupt Enable
875	875	// According to spec, (re)setting this flag clears the RBRL flag

src/mess/machine/nubus_asntmc3b.c

r12904	r12905
180	180	}
181	181	}
182	182
183		READ8_MEMBER( nubus_asntm3b_device::dp_mem_read )
	183	READ8_MEMBER( nubus_asntm3b_device::dp_mem_read )
184	184	{
185		if(offset < 32)
	185	if(offset < 32)
186	186	{
187	187	return m_prom[offset>>1];
188	188	}
189	189
190		if((offset < (16*1024)) || (offset >= ((16+64)*1024)))
	190	if((offset < (16*1024)) || (offset >= ((16+64)*1024)))
191	191	{
192	192	logerror("asntmc3b: invalid memory read %04X\n", offset);
193	193	return 0xff;
r12904	r12905
195	195	return m_ram[offset - (16*1024)];
196	196	}
197	197
198		WRITE8_MEMBER( nubus_asntm3b_device::dp_mem_write )
	198	WRITE8_MEMBER( nubus_asntm3b_device::dp_mem_write )
199	199	{
200	200	if((offset < (16*1024)) || (offset >= ((16+64)*1024)))
201	201	{

src/mess/machine/dp8390.c

r12904	r12905
193	193	return data;
194	194	}
195	195	}
196
	196
197	197	switch((offset & 0x0f)|(m_regs.cr & 0xc0)) {
198	198	case 0x00:
199	199	case 0x40:
r12904	r12905
362	362	}
363	363	return;
364	364	}
365
	365
366	366	data &= 0xff;
367	367	switch((offset & 0x0f)|(m_regs.cr & 0xc0)) {
368	368	case 0x00:

src/mess/machine/intv.c

r12904	r12905
478	478	else
479	479	{
480	480	UINT16 offset[] = {0x4800, 0x5000, 0x6000, 0x7000, 0x9000, 0xa000, 0xc000, 0xd000, 0xf000};
481		const char* region_name[] = {"4800", "5000", "6000", "7000", "9000", "A000", "C000", "D000", "F000"};
	481	const char* region_name[] = {"4800", "5000", "6000", "7000", "9000", "A000", "C000", "D000", "F000"};
482	482	UINT8 *memory = image.device().machine().region("maincpu")->base();
483	483	UINT32 size=0;
484	484	UINT16 address;

src/mess/machine/nubus.c

r12904	r12905
3	3	nubus.c - NuBus bus and card emulation
4	4
5	5	by R. Belmont, based heavily on Miodrag Milanovic's ISA8/16 implementation
6
	6
7	7	***************************************************************************/
8	8
9	9	#include "emu.h"

src/mess/video/nubus_radiustpd.c

r12904	r12905
1	1	/***************************************************************************
2	2
3	3	Radius Two Page Display (1280x960?)
4
	4
5	5	Fsx8000a = DAC data
6	6	Fsx8000e = DAC control
7	7	Fsx00000 = VRAM (offset 0x200, stride 0x1b0)
8
	8
9	9	***************************************************************************/
10	10
11	11	#include "emu.h"
r12904	r12905
15	15	#define RADIUSTPD_ROM_REGION  "tpd_rom"
16	16
17	17	#define VRAM_SIZE   (0x40000)   // 256k.  1152x880 1 bit per pixel fits nicely.
18
	18
19	19	static SCREEN_UPDATE( radiustpd );
20	20
21	21	MACHINE_CONFIG_FRAGMENT( radiustpd )
r12904	r12905
183	183
184	184	WRITE32_MEMBER( nubus_radiustpd_device::radiustpd_w )
185	185	{
186		//   printf("TPD: write %08x to %x, mask %08x\n", data, offset, mem_mask);
	186	//  printf("TPD: write %08x to %x, mask %08x\n", data, offset, mem_mask);
187	187	}
188	188
189	189	READ32_MEMBER( nubus_radiustpd_device::radiustpd_r )
190	190	{
191		//   printf("TPD: read @ %x, mask %08x\n", offset, mem_mask);
	191	//  printf("TPD: read @ %x, mask %08x\n", offset, mem_mask);
192	192
193	193	if (offset == 0)
194	194	{

src/mess/includes/einstein.h

r12904	r12905
66	66	UINT8 *m_crtc_ram;
67	67	UINT8   m_de;
68	68
69		static const floppy_format_type floppy_formats[];
	69	static const floppy_format_type floppy_formats[];
70	70	};
71	71
72	72

src/mess/includes/tdv2324.h

r12904	r12905
67	67	required_device<device_t> m_pic;
68	68	required_device<device_t> m_pit0;
69	69	required_device<device_t> m_pit1;
70
	70
71	71	virtual void video_start();
72	72	virtual bool screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect);
73	73
74	74	DECLARE_READ8_MEMBER( tdv2324_main_io_30 );
75	75	DECLARE_READ8_MEMBER( tdv2324_main_io_e6 );
76	76	DECLARE_WRITE8_MEMBER( tdv2324_main_io_e2 );
77
	77
78	78	UINT8 m_sub_status;
79	79	UINT8 m_sub_data;
80
	80
81	81	// video state
82	82	UINT8 *m_video_ram;
83	83	};

src/mess/drivers/nakajies.c

r12904	r12905
102	102	0015 - unknown
103	103	0x1c written during boot sequence
104	104
105		0012-0015 - banking?
	105	0012-0015 - banking?
106	106	T200:
107	107	Time: 15 - 02; call ADxxx
108	108	Database: 15 - 02; call B3xxx

src/mess/drivers/at.c

r12904	r12905
566	566	MCFG_ISA16_SLOT_ADD("isabus","isa2", pc_isa16_cards, "ide", NULL)
567	567	MCFG_ISA8_SLOT_ADD("isabus","isa3", pc_isa8_cards, "comat", NULL)
568	568	MCFG_ISA16_SLOT_ADD("isabus","isa4", pc_isa16_cards, "ne2000", NULL)
569
	569
570	570	MCFG_FRAGMENT_ADD( pcvideo_vga )
571	571
572	572	/* internal ram */
r12904	r12905
912	912	ROMX_LOAD( "2hlm003l.bin",   0xf0000, 0x8000, CRC(317cbcbf) SHA1(1adad6280d8b07c2921fc5fc13ecaa10e6bfebdc),ROM_SKIP(1) | ROM_BIOS(12) )
913	913	ROM_SYSTEM_BIOS(12, "at", "PC 286") /*(Motherboard Manufacturer: Unknown.) (BIOS release date:: 03-11-1987)*/
914	914	ROMX_LOAD("at110387.1", 0xf0001, 0x8000, CRC(679296a7) SHA1(ae891314cac614dfece686d8e1d74f4763cf40e3),ROM_SKIP(1) | ROM_BIOS(13) )
915		ROMX_LOAD("at110387.0", 0xf0000, 0x8000, CRC(65ae1f97) SHA1(91a29c7deecf7a9afbba330e64e0eee9aafee4d1),ROM_SKIP(1) | ROM_BIOS(13) )
	915	ROMX_LOAD("at110387.0", 0xf0000, 0x8000, CRC(65ae1f97) SHA1(91a29c7deecf7a9afbba330e64e0eee9aafee4d1),ROM_SKIP(1) | ROM_BIOS(13) )
916	916	ROM_END
917	917
918	918	ROM_START( xb42639 )

src/mess/drivers/einstein.c

r12904	r12905
460	460	einstein->m_ctc_trigger = 0;
461	461
462	462	/* configure floppy drives */
463		/*   floppy_type_t type_80 = FLOPPY_STANDARD_5_25_DSHD;
464		floppy_type_t type_40 = FLOPPY_STANDARD_5_25_SSDD_40;
465		floppy = machine.device("floppy0");
466		floppy_drive_set_geometry(floppy, config & 0x01 ? type_80 : type_40);
467		floppy = machine.device("floppy1");
468		floppy_drive_set_geometry(floppy, config & 0x02 ? type_80 : type_40);
469		floppy = machine.device("floppy2");
470		floppy_drive_set_geometry(floppy, config & 0x04 ? type_80 : type_40);
471		floppy = machine.device("floppy3");
472		floppy_drive_set_geometry(floppy, config & 0x08 ? type_80 : type_40);*/
	463	/*  floppy_type_t type_80 = FLOPPY_STANDARD_5_25_DSHD;
	464	floppy_type_t type_40 = FLOPPY_STANDARD_5_25_SSDD_40;
	465	floppy = machine.device("floppy0");
	466	floppy_drive_set_geometry(floppy, config & 0x01 ? type_80 : type_40);
	467	floppy = machine.device("floppy1");
	468	floppy_drive_set_geometry(floppy, config & 0x02 ? type_80 : type_40);
	469	floppy = machine.device("floppy2");
	470	floppy_drive_set_geometry(floppy, config & 0x04 ? type_80 : type_40);
	471	floppy = machine.device("floppy3");
	472	floppy_drive_set_geometry(floppy, config & 0x08 ? type_80 : type_40);*/
473	473	}
474	474
475	475	static MACHINE_RESET( einstein2 )

src/mess/drivers/bml3.c

r12904	r12905
273	273	{
274	274	if(offset == 0x19)
275	275	m_io_latch = data; //???
276		//   else
	276	//  else
277	277	if(offset == 0xc4)
278	278	{/* system latch, writes 0x53 -> 0x51 when a tape is loaded */}
279	279	else

src/mess/drivers/comx35.c

r12904	r12905
465	465	// clear the RAM since DOS card will go crazy if RAM is not all zeroes
466	466	UINT8 *ram = ram_get_ptr(m_ram);
467	467	memset(ram, 0, 0x8000);
468
	468
469	469	// register for state saving
470	470	save_item(NAME(m_clear));
471	471	save_item(NAME(m_q));

src/mess/drivers/abc1600.c

r12904	r12905
10	10
11	11	TODO:
12	12
13		- keyboard
14		- "Bad command" on first enter after boot
	13	- keyboard
	14	- "Bad command" on first enter after boot
15	15	- floppy
16	16	- internal floppy is really drive 2, but wd17xx.c doesn't like having NULL drives
17	17	- BUS0I/0X/1/2
r12904	r12905
389	389	int t1 = !(BIT(m_task, 1) | force_task0);
390	390	int t2 = !(BIT(m_task, 2) | force_task0);
391	391	int t3 = !(BIT(m_task, 3) | force_task0);
392
	392
393	393	return (t3 << 3) | (t2 << 2) | (t1 << 1) | t0;
394	394	}
395	395
r12904	r12905
402	402	{
403	403	int sega19 = !(!(A8 | m_ifc2) | !A19);
404	404	int task = get_current_task(offset);
405
	405
406	406	return (task << 5) | (sega19 << 4) | ((offset >> 15) & 0x0f);
407	407	}
408	408
r12904	r12905
426	426	// segment
427	427	offs_t sega = get_segment_address(offset);
428	428	UINT8 segd = m_segment_ram[sega];
429
	429
430	430	// page
431	431	offs_t pga = get_page_address(offset, segd);
432	432	UINT16 page_data = m_page_ram[pga];
433
	433
434	434	offs_t virtual_offset = ((page_data & 0x3ff) << 11) | (offset & 0x7ff);
435
	435
436	436	if (PAGE_NONX)
437	437	{
438	438	logerror("Bus error %06x : %06x\n", offset, virtual_offset);
r12904	r12905
772	772	// segment
773	773	offs_t sega = get_segment_address(offset);
774	774	UINT8 segd = m_segment_ram[sega];
775
	775
776	776	// page
777	777	offs_t pga = get_page_address(offset, segd);
778	778	UINT16 data = m_page_ram[pga];
r12904	r12905
814	814	// segment
815	815	offs_t sega = get_segment_address(offset);
816	816	UINT8 segd = m_segment_ram[sega];
817
	817
818	818	// page
819	819	offs_t pga = get_page_address(offset, segd);
820	820
r12904	r12905
1470	1470	data = state->m_cio->intack_r();
1471	1471	break;
1472	1472	}
1473
	1473
1474	1474	return data;
1475	1475	}
1476	1476

src/mess/drivers/tdv2324.c

r12904	r12905
5	5	Skeleton driver
6	6	By Curt Coder with some work by Lord Nightmare
7	7
8		Status:
9		* Main cpu is currently hacked to read i/o port 0xE6 as 0x10;
10		it then seems to copy code to a ram area then jumps there
11		(there may be some sort of overlay/banking mess going on to allow full 64kb of ram)
12		The cpu gets stuck reading i/o port 0x30 in a loop.
13		- interrupts and sio lines are not hooked up
14		* Sub cpu does a bunch of unknown i/o accesses and also tries to
15		sequentially read chunk of address space which it never writes to;
16		this seems likely to be a shared ram or i/o mapped area especially since it seems
17		to write to i/o port 0x60 before trying to read there.
18		- interrupts and sio lines are not hooked up
19		* Fdc cpu starts, does a rom checksum (which passes) and tests a ram area
20
21
22		Board Notes:
23		Mainboard (pictures P1010036 & P1010038)
24		*28-pin: D27128, L4267096S,...(eprom, occluded by sticker: "965268 1", character set)
25		*40-pin: TMS9937NL, DB 336, ENGLAND (VTAC Video Chip)
26		*40-pin: P8085AH-2, F4265030, C INTEL '80 (cpus, there are 2 of these)
27		*28-pin: JAPAN 8442, 00009SS0, HN4827128G-25 (eprom, sticker: "962107")
28		*22-pin: ER3400, GI 8401HHA (EAROM)
29		*  -pin: MOSTEK C 8424, MK3887N-4 (Z80 Serial I/O Controller)
30		*20-pin: (pal, sticker: "961420 0")
31		*24-pin: D2716, L3263271, INTEL '77 (eprom, sticker: "962058 1")
32		*3 tiny 16-pins which look socketed (proms)
33		*+B8412, DMPAL10L8NC
34		*PAL... (can't remove the sticker to read the rest since there's electrical components soldered above the chip)
35		*Am27S21DC, 835IDmm
36		*AM27S13DC, 8402DM (x2)
37		*TBP28L22N, GERMANY 406 A (x2)
38		*PAL16L6CNS, 8406
	8	Status:
	9	* Main cpu is currently hacked to read i/o port 0xE6 as 0x10;
	10	it then seems to copy code to a ram area then jumps there
	11	(there may be some sort of overlay/banking mess going on to allow full 64kb of ram)
	12	The cpu gets stuck reading i/o port 0x30 in a loop.
	13	- interrupts and sio lines are not hooked up
	14	* Sub cpu does a bunch of unknown i/o accesses and also tries to
	15	sequentially read chunk of address space which it never writes to;
	16	this seems likely to be a shared ram or i/o mapped area especially since it seems
	17	to write to i/o port 0x60 before trying to read there.
	18	- interrupts and sio lines are not hooked up
	19	* Fdc cpu starts, does a rom checksum (which passes) and tests a ram area
39	20
40		FD/HD Interface Board P/N 962013 Rev14 (pictures P1010031 & P1010033)
41		*28-pin: TMS, 2764JL-25, GHP8414 (@U15, labeled "962014 // -4-", fdc cpu rom)
42		*40-pin: MC68B02P, R1H 8340 (fdc cpu)
43		*40-pin: WDC '79, FD1797PL-02, 8342 16 (fdc chip)
44		*14-pin: MC4024P, MG 8341 (dual voltage controlled multivibrator)
45		*24-pin: TMM2016AP-12 (@U14 and @U80, 120ns 2kx8 SRAM)
46	21
47		Keyboard:
48		*40-pin: NEC D8035LC (mcs-48 cpu)
49		*24-pin: NEC D2716 (eprom)
	22	Board Notes:
	23	Mainboard (pictures P1010036 & P1010038)
	24	*28-pin: D27128, L4267096S,...(eprom, occluded by sticker: "965268 1", character set)
	25	*40-pin: TMS9937NL, DB 336, ENGLAND (VTAC Video Chip)
	26	*40-pin: P8085AH-2, F4265030, C INTEL '80 (cpus, there are 2 of these)
	27	*28-pin: JAPAN 8442, 00009SS0, HN4827128G-25 (eprom, sticker: "962107")
	28	*22-pin: ER3400, GI 8401HHA (EAROM)
	29	*  -pin: MOSTEK C 8424, MK3887N-4 (Z80 Serial I/O Controller)
	30	*20-pin: (pal, sticker: "961420 0")
	31	*24-pin: D2716, L3263271, INTEL '77 (eprom, sticker: "962058 1")
	32	*3 tiny 16-pins which look socketed (proms)
	33	*+B8412, DMPAL10L8NC
	34	*PAL... (can't remove the sticker to read the rest since there's electrical components soldered above the chip)
	35	*Am27S21DC, 835IDmm
	36	*AM27S13DC, 8402DM (x2)
	37	*TBP28L22N, GERMANY 406 A (x2)
	38	*PAL16L6CNS, 8406
50	39
51		Main CPU:
52		- PIT, SIO
53
54		Sub CPU:
55		- PIC, PIT, VTAC
56
	40	FD/HD Interface Board P/N 962013 Rev14 (pictures P1010031 & P1010033)
	41	*28-pin: TMS, 2764JL-25, GHP8414 (@U15, labeled "962014 // -4-", fdc cpu rom)
	42	*40-pin: MC68B02P, R1H 8340 (fdc cpu)
	43	*40-pin: WDC '79, FD1797PL-02, 8342 16 (fdc chip)
	44	*14-pin: MC4024P, MG 8341 (dual voltage controlled multivibrator)
	45	*24-pin: TMM2016AP-12 (@U14 and @U80, 120ns 2kx8 SRAM)
	46
	47	Keyboard:
	48	*40-pin: NEC D8035LC (mcs-48 cpu)
	49	*24-pin: NEC D2716 (eprom)
	50
	51	Main CPU:
	52	- PIT, SIO
	53
	54	Sub CPU:
	55	- PIC, PIT, VTAC
	56
57	57	*/
58	58	/*
59	59	'subcpu' (17CD): unmapped i/o memory write to 23 = 36 & FF
r12904	r12905
129	129	static ADDRESS_MAP_START( tdv2324_mem, AS_PROGRAM, 8, tdv2324_state )
130	130	AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0x0800) AM_ROM AM_REGION(P8085AH_0_TAG, 0)
131	131	/* when copying code to 4000 area it runs right off the end of rom;
132		* I'm not sure if its supposed to mirror or read as open bus */
133		//   AM_RANGE(0x4000, 0x5fff) AM_RAM // 0x4000 has the boot code copied to it, 5fff and down are the stack
134		//   AM_RANGE(0x6000, 0x6fff) AM_RAM // used by the relocated boot code; shared?
	132	* I'm not sure if its supposed to mirror or read as open bus */
	133	//  AM_RANGE(0x4000, 0x5fff) AM_RAM // 0x4000 has the boot code copied to it, 5fff and down are the stack
	134	//  AM_RANGE(0x6000, 0x6fff) AM_RAM // used by the relocated boot code; shared?
135	135	AM_RANGE(0x0800, 0xffff) AM_RAM
136	136	ADDRESS_MAP_END
137	137
r12904	r12905
146	146	/* e0, e2, e8, ea are written to */
147	147	/* 30, e6 and e2 are readable */
148	148	AM_RANGE(0x30, 0x30) AM_READ(tdv2324_main_io_30)
149		//   AM_RANGE(0xe2, 0xe2) AM_WRITE(tdv2324_main_io_e2) console output
	149	//  AM_RANGE(0xe2, 0xe2) AM_WRITE(tdv2324_main_io_e2) console output
150	150	AM_RANGE(0xe6, 0xe6) AM_READ(tdv2324_main_io_e6)
151		//   AM_RANGE(0x, 0x) AM_DEVREADWRITE_LEGACY(P8253_5_0_TAG, pit8253_r, pit8253_w)
152		//   AM_RANGE(0x, 0x) AM_DEVREADWRITE_LEGACY(MK3887N4_TAG, z80dart_ba_cd_r, z80dart_ba_cd_w)
153		//   AM_RANGE(0x, 0x) AM_DEVREADWRITE_LEGACY(P8259A_TAG, pic8259_r, pic8259_w)
	151	//  AM_RANGE(0x, 0x) AM_DEVREADWRITE_LEGACY(P8253_5_0_TAG, pit8253_r, pit8253_w)
	152	//  AM_RANGE(0x, 0x) AM_DEVREADWRITE_LEGACY(MK3887N4_TAG, z80dart_ba_cd_r, z80dart_ba_cd_w)
	153	//  AM_RANGE(0x, 0x) AM_DEVREADWRITE_LEGACY(P8259A_TAG, pic8259_r, pic8259_w)
154	154	ADDRESS_MAP_END
155	155
156	156
r12904	r12905
424	424
425	425	MCFG_PALETTE_LENGTH(2)
426	426	MCFG_PALETTE_INIT(monochrome_green)
427
	427
428	428	MCFG_TMS9927_ADD(TMS9937NL_TAG, XTAL_25_39836MHz, vtac_intf)
429	429
430	430	// devices

src/mess/drivers/apple2gs.c

r12904	r12905
277	277	ROM_REGION(0x400, "kmcu", 0)
278	278	// from early-production ROM 00 Woz Limited Edition IIgs.  keyboard "Part Number 658-4081  825-1301-A"
279	279	// ROM is marked "NEC Japan  8626XD 341-0232A  543" so 26th week of 1986
280		ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
	280	ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
281	281	// from later non-Woz ROM 01.  keyboard "Model A9M0330"
282	282	// ROM is marked "NEC Japan 8806HD  8048HC610  341-0124-A  (c) APPLE 87" so 6th week of 1988
283		ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
	283	ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
284	284
285	285	ROM_REGION(0x1000,"gfx1",0)
286	286	ROM_LOAD ( "apple2gs.chr", 0x0000, 0x1000, CRC(91e53cd8) SHA1(34e2443e2ef960a36c047a09ed5a93f471797f89)) /* need label/part number */
r12904	r12905
297	297	ROM_LOAD( "341s0632-2.bin", 0x000000, 0x001000, CRC(e1c11fb0) SHA1(141d18c36a617ab9dce668445440d34354be0672) )
298	298
299	299	ROM_REGION(0x400, "kmcu", 0)
300		ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
301		ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
	300	ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
	301	ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
302	302
303	303	ROM_REGION(0x1000,"gfx1",0)
304	304	ROM_LOAD ( "apple2gs.chr", 0x0000, 0x1000, CRC(91e53cd8) SHA1(34e2443e2ef960a36c047a09ed5a93f471797f89)) /* need label/part number */
r12904	r12905
315	315	ROM_LOAD( "341s0632-2.bin", 0x000000, 0x001000, CRC(e1c11fb0) SHA1(141d18c36a617ab9dce668445440d34354be0672) )
316	316
317	317	ROM_REGION(0x400, "kmcu", 0)
318		ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
319		ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
	318	ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
	319	ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
320	320
321	321	ROM_REGION(0x1000,"gfx1",0)
322	322	ROM_LOAD ( "apple2gs.chr", 0x0000, 0x1000, CRC(91e53cd8) SHA1(34e2443e2ef960a36c047a09ed5a93f471797f89)) /* need label/part number */
r12904	r12905
333	333	ROM_LOAD( "341s0345.bin", 0x000000, 0x000c00, CRC(48cd5779) SHA1(97e421f5247c00a0ca34cd08b6209df573101480) )
334	334
335	335	ROM_REGION(0x400, "kmcu", 0)
336		ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
337		ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
	336	ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
	337	ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
338	338
339	339	ROM_REGION(0x1000,"gfx1",0)
340	340	ROM_LOAD ( "apple2gs.chr", 0x0000, 0x1000, CRC(91e53cd8) SHA1(34e2443e2ef960a36c047a09ed5a93f471797f89)) /* need label/part number */
r12904	r12905
350	350	ROM_LOAD( "341s0345.bin", 0x000000, 0x000c00, CRC(48cd5779) SHA1(97e421f5247c00a0ca34cd08b6209df573101480) )
351	351
352	352	ROM_REGION(0x400, "kmcu", 0)
353		ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
354		ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
	353	ROM_LOAD( "341-0232a.bin", 0x000000, 0x000400, CRC(6a158b9f) SHA1(e8744180075182849d431fd8023a52a062a6da76) )
	354	ROM_LOAD( "341-0124a.bin", 0x000000, 0x000400, CRC(2a3576bf) SHA1(58fbf770d3801a02d0944039829f9241b5279013) )
355	355
356	356	ROM_REGION(0x1000,"gfx1",0)
357	357	ROM_LOAD ( "apple2gs.chr", 0x0000, 0x1000, CRC(91e53cd8) SHA1(34e2443e2ef960a36c047a09ed5a93f471797f89))

src/mess/drivers/mac.c

r12904	r12905
831	831	SLOT_INTERFACE("specpdq", NUBUS_SPECPDQ)   /* SuperMac Spectrum PDQ */
832	832	SLOT_INTERFACE("m2hires", NUBUS_M2HIRES)   /* Apple Macintosh II Hi-Resolution Card */
833	833	SLOT_INTERFACE("spec8s3", NUBUS_SPEC8S3)   /* SuperMac Spectrum/8 Series III */
834		//   SLOT_INTERFACE("thundergx", NUBUS_THUNDERGX)      /* Radius Thunder GX (not yet) */
	834	//  SLOT_INTERFACE("thundergx", NUBUS_THUNDERGX)        /* Radius Thunder GX (not yet) */
835	835	SLOT_INTERFACE("radiustpd", NUBUS_RADIUSTPD)      /* Radius Two Page Display */
836	836	SLOT_INTERFACE("asmc3b", NUBUS_ASNTMC3B)   /* Asante MC3B Ethernet card */
837	837	SLOT_INTERFACE_END

src/mess/drivers/vt100.c

r12904	r12905
594	594	// This is the standard vt100 cpu board, but with the rom set included with the VT1xx-AC kit
595	595	// which is only used when the STP 'printer port expansion' card is installed into the terminal board.
596	596	// This romset adds the Set-up C page to the setup menu (press keypad 5 twice once you hit set-up)
597		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
598		ROM_LOAD( "23-095e2-00.e56", 0x0000, 0x0800, NO_DUMP)
599		ROM_LOAD( "23-096e2-00.e52", 0x0800, 0x0800, NO_DUMP)
600		ROM_LOAD( "23-139e2-00.e45", 0x1000, 0x0800, NO_DUMP) // revision 2?; revision 1 is 23-097e2
601		ROM_LOAD( "23-140e2-00.e40", 0x1800, 0x0800, NO_DUMP) // revision 2?; revision 1 is 23-098e2
602		ROM_REGION(0x1000, "chargen",0)
603		ROM_LOAD( "23-018e2-00.e4", 0x0000, 0x0800, BAD_DUMP CRC(6958458b) SHA1(103429674fc01c215bbc2c91962ae99231f8ae53)) // probably correct but needs redump
604		ROM_LOAD_OPTIONAL( "23-094e2-00.e9", 0x0800, 0x0800, NO_DUMP) // optional ?word processing? alternate character set rom
605		ROM_REGION(0x10000, "stpcpu",ROMREGION_ERASEFF)
	597	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
	598	ROM_LOAD( "23-095e2-00.e56", 0x0000, 0x0800, NO_DUMP)
	599	ROM_LOAD( "23-096e2-00.e52", 0x0800, 0x0800, NO_DUMP)
	600	ROM_LOAD( "23-139e2-00.e45", 0x1000, 0x0800, NO_DUMP) // revision 2?; revision 1 is 23-097e2
	601	ROM_LOAD( "23-140e2-00.e40", 0x1800, 0x0800, NO_DUMP) // revision 2?; revision 1 is 23-098e2
	602	ROM_REGION(0x1000, "chargen",0)
	603	ROM_LOAD( "23-018e2-00.e4", 0x0000, 0x0800, BAD_DUMP CRC(6958458b) SHA1(103429674fc01c215bbc2c91962ae99231f8ae53)) // probably correct but needs redump
	604	ROM_LOAD_OPTIONAL( "23-094e2-00.e9", 0x0800, 0x0800, NO_DUMP) // optional ?word processing? alternate character set rom
	605	ROM_REGION(0x10000, "stpcpu",ROMREGION_ERASEFF)
606	606	// expansion board for a vt100 with a processor on it and dma, intended to act as a ram/send buffer for the STP printer board.
607	607	// It can be populated with two banks of two eproms each, each bank either contains 2k or 4k eproms depending on the w2/w3 and w4/w5 jumpers.
608	608	// It also has two proms on the cpu board. I don't know if it is technically necessary to have this board installed if an STP module is installed, but due to the alt stp romset, it probably is.
609		ROM_LOAD( "23-003e3-00.e10", 0x0000, 0x1000, NO_DUMP) // "EPROM 0" bank 0
610		ROM_LOAD( "23-004e3-00.e4", 0x1000, 0x1000, NO_DUMP) // "EPROM 1" bank 0
611		ROM_LOAD( "23-005e3-00.e9", 0x2000, 0x1000, NO_DUMP) // "EPROM 2" bank 1
612		ROM_LOAD( "23-006e3-00.e3", 0x3000, 0x1000, NO_DUMP) // "EPROM 3" bank 1
613		//ROM_REGION(0x0800, "chargen",0)
614		//ROM_LOAD( "23-???e2-00.e34", 0x0000, 0x0800, NO_DUMP) // ? second gfx rom?
615		ROM_REGION(0x0400, "proms",0)
616		ROM_LOAD( "23-312a1-07.e26", 0x0000, 0x0200, NO_DUMP) // "PROM A"; handles 8085 i/o? mapping (usart, timer, dma, comm, etc)
617		ROM_LOAD( "23-313a1-07.e15", 0x0200, 0x0200, NO_DUMP) // "PROM B"; handles firmware rom mapping and memory size/page select; bit 0 = ram page, bits 1-3 unused, bits 4-7 select one eprom each
	609	ROM_LOAD( "23-003e3-00.e10", 0x0000, 0x1000, NO_DUMP) // "EPROM 0" bank 0
	610	ROM_LOAD( "23-004e3-00.e4", 0x1000, 0x1000, NO_DUMP) // "EPROM 1" bank 0
	611	ROM_LOAD( "23-005e3-00.e9", 0x2000, 0x1000, NO_DUMP) // "EPROM 2" bank 1
	612	ROM_LOAD( "23-006e3-00.e3", 0x3000, 0x1000, NO_DUMP) // "EPROM 3" bank 1
	613	//ROM_REGION(0x0800, "chargen",0)
	614	//ROM_LOAD( "23-???e2-00.e34", 0x0000, 0x0800, NO_DUMP) // ? second gfx rom?
	615	ROM_REGION(0x0400, "proms",0)
	616	ROM_LOAD( "23-312a1-07.e26", 0x0000, 0x0200, NO_DUMP) // "PROM A"; handles 8085 i/o? mapping (usart, timer, dma, comm, etc)
	617	ROM_LOAD( "23-313a1-07.e15", 0x0200, 0x0200, NO_DUMP) // "PROM B"; handles firmware rom mapping and memory size/page select; bit 0 = ram page, bits 1-3 unused, bits 4-7 select one eprom each
618	618	ROM_END
619	619	*/
620	620
r12904	r12905
731	731	ROM_START( vt132 ) // This is from anecdotal evidence and vt100.net, as the vt132 schematics are not scanned
732	732	// VT100 board with ? roms, AVO, STP, custom firmware with block serial mode; dunnington insists these roms
733	733	// should be the 23-180e2/181e2/182e2/183e2 set, but I'm not convinced.
734		ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
735		ROM_LOAD( "23-???e2-00.e56", 0x0000, 0x0800, NO_DUMP)
736		ROM_LOAD( "23-???e2-00.e52", 0x0800, 0x0800, NO_DUMP)
737		ROM_LOAD( "23-???e2-00.e45", 0x1000, 0x0800, NO_DUMP)
738		ROM_LOAD( "23-???e2-00.e40", 0x1800, 0x0800, NO_DUMP)
	734	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
	735	ROM_LOAD( "23-???e2-00.e56", 0x0000, 0x0800, NO_DUMP)
	736	ROM_LOAD( "23-???e2-00.e52", 0x0800, 0x0800, NO_DUMP)
	737	ROM_LOAD( "23-???e2-00.e45", 0x1000, 0x0800, NO_DUMP)
	738	ROM_LOAD( "23-???e2-00.e40", 0x1800, 0x0800, NO_DUMP)
739	739
740		ROM_REGION(0x1000, "chargen", 0)
741		ROM_LOAD( "23-018e2-00.e4", 0x0000, 0x0800, BAD_DUMP CRC(6958458b) SHA1(103429674fc01c215bbc2c91962ae99231f8ae53)) // probably correct but needs redump
742		ROM_LOAD_OPTIONAL( "23-094e2-00.e9", 0x0800, 0x0800, NO_DUMP) // optional (comes default with some models) alternate character set rom
	740	ROM_REGION(0x1000, "chargen", 0)
	741	ROM_LOAD( "23-018e2-00.e4", 0x0000, 0x0800, BAD_DUMP CRC(6958458b) SHA1(103429674fc01c215bbc2c91962ae99231f8ae53)) // probably correct but needs redump
	742	ROM_LOAD_OPTIONAL( "23-094e2-00.e9", 0x0800, 0x0800, NO_DUMP) // optional (comes default with some models) alternate character set rom
743	743	ROM_END
744	744	*/
745	745	ROM_START( vt180 )

src/mess/drivers/vt240.c

r12904	r12905
4	4
5	5	31/03/2010 Skeleton driver.
6	6
7		TODO:
8		- understand how PCG works, it should be a funky i/o $30 to uPD7220 DMA
9		transfer;
10		- hook-up T11, rst65 irq + $20 reads are latches for that
	7	TODO:
	8	- understand how PCG works, it should be a funky i/o $30 to uPD7220 DMA
	9	transfer;
	10	- hook-up T11, rst65 irq + $20 reads are latches for that
11	11
12		ROM POST notes:
13		0x0139: ROM test
14		0x015f: RAM test
15		0x0071: RAM fill to 0x00
16		0x1c8f: UPD7220
	12	ROM POST notes:
	13	0x0139: ROM test
	14	0x015f: RAM test
	15	0x0071: RAM fill to 0x00
	16	0x1c8f: UPD7220
17	17
18	18	****************************************************************************/
19	19	#define ADDRESS_MAP_MODERN
r12904	r12905
130	130	ADDRESS_MAP_GLOBAL_MASK(0xff)
131	131	AM_RANGE(0x00, 0x01) AM_DEVREADWRITE("upd7220", upd7220_device, read, write)
132	132	AM_RANGE(0x20, 0x20) AM_READ(test_r)
133		//AM_RANGE(0x30, 0x30) AM_READWRITE(pcg_r,pcg_w) //   0x30 PCG
	133	//AM_RANGE(0x30, 0x30) AM_READWRITE(pcg_r,pcg_w) // 0x30 PCG
134	134	ADDRESS_MAP_END
135	135
136	136
r12904	r12905
193	193	MCFG_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
194	194	MCFG_SCREEN_SIZE(640, 480)
195	195	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
196		//   MCFG_VIDEO_START(vt240)
197		//   MCFG_SCREEN_UPDATE(vt240)
	196	//  MCFG_VIDEO_START(vt240)
	197	//  MCFG_SCREEN_UPDATE(vt240)
198	198	MCFG_PALETTE_LENGTH(2)
199	199	MCFG_PALETTE_INIT(black_and_white)
200	200	MCFG_GFXDECODE(vt240)

src/mess/drivers/intv.c

r12904	r12905
487	487	MCFG_CARTSLOT_LOAD(intv_cart)
488	488	MCFG_CARTSLOT_INTERFACE("intv_cart")
489	489	/* software lists */
490		MCFG_SOFTWARE_LIST_ADD("cart_list","intv")
	490	MCFG_SOFTWARE_LIST_ADD("cart_list","intv")
491	491	MACHINE_CONFIG_END
492	492
493	493

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