MESS SVN History

15994 Revisions

r12349 Wednesday 27th July, 2011 at 08:13:12 UTC by Miodrag Milanović
Source cleanup (no whatsnew)

[src/mess]	mess.lst
[src/mess/devices]	appldriv.h
[src/mess/drivers]	acrnsys1.c amstrad.c at.c c64.c coco.c comx35.c imds.c lisa.c mac.c ng_aes.c pc.c pc1512.c prof80.c sdk86.c slc1.c tdv2324.c tsispch.c z100.c z88.c
[src/mess/includes]	at.h comx35.h pc1512.h
[src/mess/machine]	amigafdc.c c64_std.c c64_xl80.c c64exp.c c64exp.h coco.c coco_232.h coco_fdc.c coco_fdc.h coco_multi.c coco_multi.h coco_pak.h coco_vhd.h cococart.c cococart.h comx_clm.c comx_clm.h comx_eb.c comx_eb.h comx_epr.c comx_fd.c comx_joy.c comx_prn.c comx_ram.c comx_thm.c comxexp.c comxexp.h cpc_ssa1.c cpc_ssa1.h cpcexp.c cpcexp.h ecb_grip.c ecb_grip.h ecbbus.c ecbbus.h egret.c isa.c isa.h isa_ide.c mac.c nubus.c nubus.h pc1512kb.c pc1512kb.h s100_dj2db.c s100_dj2db.h
[src/mess/tools/floptool]	main.c
[src/mess/tools/imgtool]	main.c
[src/mess/video]	comx35.c intv.c isa_mda.h mac.c nubus_48gc.c nubus_48gc.h stic.h
[src/osd/winui]	datafile.c

src/osd/winui/datafile.c
r12348	r12349
346	346	{
347	347	return FALSE;
348	348	}
349
	349
350	350	file_error err = fp->open(pszFilename);
351	351	if (err != FILERR_NONE)
352	352	{
r12348	r12349
354	354	fp = NULL;
355	355	return FALSE;
356	356	}
357
	357
358	358	/* Otherwise, prepare! */
359	359	dwFilePos = 0;
360	360	return TRUE;

src/mess/devices/appldriv.h
r12348	r12349
55	55	MCFG_DEVICE_CONFIG(_config) \
56	56	MCFG_LEGACY_FLOPPY_APPLE_PARAMS(_dividend,_divisor)
57	57
58		#define MCFG_LEGACY_FLOPPY_APPLE_2_DRIVES_REMOVE() \
	58	#define MCFG_LEGACY_FLOPPY_APPLE_2_DRIVES_REMOVE() \
59	59	MCFG_DEVICE_REMOVE(FLOPPY_0) \
60	60	MCFG_DEVICE_REMOVE(FLOPPY_1)
61	61

src/mess/tools/imgtool/main.c
r12348	r12349
794	794	for (i = 0; range[i].max >= 0; i++)
795	795	{
796	796	if (range[i].min == range[i].max)
797		snprintf(buf, ARRAY_LENGTH(buf), "%i", range[i].min);
	797	snprintf(buf, ARRAY_LENGTH(buf), "%i", range[i].min);
798	798	else
799		snprintf(buf, ARRAY_LENGTH(buf), "%i-%i", range[i].min, range[i].max);
	799	snprintf(buf, ARRAY_LENGTH(buf), "%i-%i", range[i].min, range[i].max);
800	800
801	801	if (i > 0)
802	802	strncatz(range_buffer, "/", sizeof(range_buffer));

src/mess/tools/floptool/main.c
r12348	r12349
36	36	for (i = 0; floppyoptions_supported[i].name; i++) {
37	37	fprintf(stderr, "%15s - %s\n",floppyoptions_supported[i].name,floppyoptions_supported[i].description);
38	38	fprintf(stderr, "%20s [%s]\n","",floppyoptions_supported[i].extensions);
39		}
	39	}
40	40	}
41	41
42	42	int CLIB_DECL main(int argc, char *argv[])
43	43	{
44	44	FILE *f;
45
	45
46	46	if (argc > 1)
47	47	{
48	48	if (!core_stricmp("identify", argv[1]))

src/mess/machine/comx_clm.c
r12348	r12349
165	165	MCFG_SCREEN_VISIBLE_AREA(0, 808-1, 0, 248-1)
166	166	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
167	167	MCFG_SCREEN_REFRESH_RATE(50)
168
	168
169	169	//MCFG_GFXDECODE(comx_clm)
170	170
171	171	MCFG_MC6845_ADD(MC6845_TAG, MC6845, XTAL_14_31818MHz, crtc_intf)
r12348	r12349
248	248	address_space *space = machine().firstcpu->memory().space(AS_PROGRAM);
249	249
250	250	UINT8 data = 0xff;
251
	251
252	252	if (offset >= 0xc000 && offset < 0xc800)
253	253	{
254	254	data = m_rom[offset & 0x7ff];
r12348	r12349
261	261	{
262	262	data = m_crtc->register_r(*space, 0);
263	263	}
264
	264
265	265	return data;
266	266	}
267	267
r12348	r12349
273	273	void comx_clm_device::comx_mwr_w(offs_t offset, UINT8 data)
274	274	{
275	275	address_space *space = machine().firstcpu->memory().space(AS_PROGRAM);
276
	276
277	277	if (offset >= 0xd000 && offset < 0xd800)
278	278	{
279	279	m_video_ram[offset & 0x7ff] = data;

src/mess/machine/cococart.h
r12348	r12349
45	45	struct _coco_cartridge_line
46	46	{
47	47	emu_timer *timer[TIMER_POOL];
48		int timer_index;
49		int delay;
50		cococart_line_value value;
51		int line;
52		int q_count;
	48	int timer_index;
	49	int delay;
	50	cococart_line_value value;
	51	int line;
	52	int q_count;
53	53	devcb_resolved_write_line callback;
54	54	};
55	55
r12348	r12349
74	74	// construction/destruction
75	75	cococart_slot_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
76	76	virtual ~cococart_slot_device();
77
	77
78	78	// device-level overrides
79	79	virtual void device_start();
80	80	virtual void device_config_complete();
81
	81
82	82	// image-level overrides
83	83	virtual bool call_load();
84	84	virtual bool call_softlist_load(char swlist, char swname, rom_entry *start_entry);
r12348	r12349
93	93	virtual const char *image_interface() const { return "coco_cart"; }
94	94	virtual const char *file_extensions() const { return "ccc,rom"; }
95	95	virtual const option_guide *create_option_guide() const { return NULL; }
96
	96
97	97	// slot interface overrides
98	98	virtual const char * get_default_card(const device_list &devlist, emu_options &options) const;
99
	99
100	100	/* reading and writing to $FF40-$FF7F */
101	101	DECLARE_READ8_MEMBER(read);
102	102	DECLARE_WRITE8_MEMBER(write);
r12348	r12349
105	105	void cart_set_line(cococart_line line, cococart_line_value value);
106	106
107	107	/* hack to support twiddling the Q line */
108		void twiddle_q_lines();
109
	108	void twiddle_q_lines();
	109
110	110	UINT8* get_cart_base();
111	111	protected:
112	112	static TIMER_CALLBACK( cart_timer_callback );
r12348	r12349
116	116	void set_line(const char line_name, coco_cartridge_line line, cococart_line_value value);
117	117	void set_line_timer(coco_cartridge_line *line, cococart_line_value value);
118	118	void twiddle_line_if_q(coco_cartridge_line *line);
119
	119
120	120	// configuration
121	121	coco_cartridge_line m_cart_line;
122	122	coco_cartridge_line m_nmi_line;
123		coco_cartridge_line m_halt_line;
124
	123	coco_cartridge_line m_halt_line;
	124
125	125	device_cococart_interface *m_cart;
126	126	};
127	127
r12348	r12349
139	139
140	140	virtual DECLARE_READ8_MEMBER(read);
141	141	virtual DECLARE_WRITE8_MEMBER(write);
142
	142
143	143	virtual UINT8* get_cart_base();
144	144	};
145	145

src/mess/machine/comx_clm.h
r12348	r12349
57	57	private:
58	58	// internal state
59	59	comx_expansion_slot_device *m_slot;
60
	60
61	61	required_device<mc6845_device> m_crtc;
62	62
63	63	int m_ds; // device select

src/mess/machine/isa_ide.c
r12348	r12349
28	28
29	29	static MACHINE_CONFIG_FRAGMENT( ide )
30	30	MCFG_HARDDISK_ADD("harddisk")
31
	31
32	32	MCFG_IDE_CONTROLLER_ADD("ide", ide_interrupt)
33	33	MACHINE_CONFIG_END
34	34

src/mess/machine/coco.c
r12348	r12349
1167	1167	new_state = CASSETTE_SPEAKER_MUTED;
1168	1168	break;
1169	1169	}
1170
	1170
1171	1171	cococart_device(machine)->cart_set_line(
1172	1172	COCOCART_LINE_SOUND_ENABLE,
1173	1173	(soundmux_status == (SOUNDMUX_STATUS_ENABLE\|SOUNDMUX_STATUS_SEL2)
r12348	r12349
2083	2083	/* If we are in the BASIC rom area $8000-$BFFF, then we map to the bas_rom_bank */
2084	2084	/* as this may be in a different block of coco_rom, in the Dragon 64 and Alpha */
2085	2085	/* as these machines have mutiple bios roms that can ocupy this area */
2086		if (block_index < 4)
	2086	if (block_index < 4)
2087	2087	offset = &state->m_bas_rom_bank[0x1000*block_index];
2088		else {
	2088	else {
2089	2089	if (cart_rom) {
2090	2090	offset = &cart_rom[(0x1000*(block_index-4)) % 0x4000];
2091	2091	} else {
r12348	r12349
2735	2735	-------------------------------------------------*/
2736	2736
2737	2737	WRITE_LINE_DEVICE_HANDLER(coco3_cart_w)
2738		{
	2738	{
2739	2739	coco3_raise_interrupt(device->machine(), COCO3_INT_EI0, state ? ASSERT_LINE : CLEAR_LINE);
2740	2740	coco_cart_w(device, state);
2741	2741	}

src/mess/machine/s100_dj2db.c
r12348	r12349
9	9
10	10	/*
11	11
12		TODO:
13
14		- stall logic (read from fdc data register halts CPU until intrq/drq from FDC)
	12	TODO:
15	13
	14	- stall logic (read from fdc data register halts CPU until intrq/drq from FDC)
	15
16	16	*/
17	17
18	18	#include "s100_dj2db.h"
r12348	r12349
81	81	WRITE_LINE_MEMBER( s100_dj2db_device::fdc_intrq_w )
82	82	{
83	83	if (state) m_s100->rdy_w(CLEAR_LINE);
84
	84
85	85	switch (input_port_read(this, "J1A"))
86	86	{
87	87	case 0: m_s100->vi0_w(state); break;
r12348	r12349
208	208	PORT_DIPNAME( 0x01, 0x01, "Generate PHANTOM Signal" )
209	209	PORT_DIPSETTING( 0x01, "Disabled" )
210	210	PORT_DIPSETTING( 0x00, "Enabled" )
211
	211
212	212	PORT_START("J3A")
213	213	PORT_DIPNAME( 0xff, 0x00, "Bank Select" )
214	214	PORT_DIPSETTING( 0x00, "Disabled" )
r12348	r12349
220	220	PORT_DIPSETTING( 0x20, "DATA 4" )
221	221	PORT_DIPSETTING( 0x40, "DATA 6" )
222	222	PORT_DIPSETTING( 0x80, "DATA 7" )
223
	223
224	224	PORT_START("J1A")
225	225	PORT_DIPNAME( 0x0f, 0x09, "Interrupt" )
226	226	PORT_DIPSETTING( 0x09, "Disabled")
r12348	r12349
281	281
282	282	m_rom = subregion("dj2db")->base();
283	283	m_ram = auto_alloc_array(machine(), UINT8, 0x400);
284
	284
285	285	// find floppy devices
286	286	m_floppy0 = machine().device(FLOPPY_0);
287	287	m_floppy1 = machine().device(FLOPPY_1);
r12348	r12349
308	308	UINT8 s100_dj2db_device::s100_smemr_r(offs_t offset)
309	309	{
310	310	UINT8 data = 0;
311
312		// if (!(m_board_enbl & m_phantom)) return 0;
313	311
	312	// if (!(m_board_enbl & m_phantom)) return 0;
	313
314	314	if ((offset >= 0xf800) && (offset < 0xfbf8))
315	315	{
316	316	data = m_rom[offset & 0x3ff] ^ 0xff;
r12348	r12349
322	322	else if (offset == 0xfbf9) // SERIAL STAT
323	323	{
324	324	/*
325
326		bit description
327
328		0 PE
329		1 OE
330		2 DR
331		3 TBRE
332		4 FE
333		5
334		6
335		7
336
337		*/
	325
	326	bit description
	327
	328	0 PE
	329	1 OE
	330	2 DR
	331	3 TBRE
	332	4 FE
	333	5
	334	6
	335	7
	336
	337	*/
338	338	}
339	339	else if (offset == 0xfbfa) // DISK STAT
340	340	{
341	341	/*
342
343		bit description
344
345		0 HEAD
346		1 DATA RQ
347		2 INT RQ
348		3 _TWO SIDED
349		4 _INDEX
350		5
351		6
352		7 _READY
353
354		*/
355
	342
	343	bit description
	344
	345	0 HEAD
	346	1 DATA RQ
	347	2 INT RQ
	348	3 _TWO SIDED
	349	4 _INDEX
	350	5
	351	6
	352	7 _READY
	353
	354	*/
	355
356	356	data \|= !m_head;
357	357	data \|= !wd17xx_drq_r(m_fdc) << 1;
358	358	data \|= !wd17xx_intrq_r(m_fdc) << 2;
359
	359
360	360	device_t *floppy = m_drive ? m_floppy1 : m_floppy0;
361	361	data \|= floppy_twosid_r(floppy) << 3;
362	362	data \|= floppy_index_r(floppy) << 4;
r12348	r12349
365	365	else if ((offset >= 0xfbfc) && (offset < 0xfc00))
366	366	{
367	367	m_s100->rdy_w(ASSERT_LINE);
368
	368
369	369	data = wd17xx_r(m_fdc, offset & 0x03);
370	370	}
371	371	else if ((offset >= 0xfc00) && (offset < 0x10000))
r12348	r12349
376	376	{
377	377	return 0;
378	378	}
379
	379
380	380	// LS241 inverts data
381	381	return data ^ 0xff;
382	382	}
r12348	r12349
388	388
389	389	void s100_dj2db_device::s100_mwrt_w(offs_t offset, UINT8 data)
390	390	{
391		// if (!(m_board_enbl & m_phantom)) return;
	391	// if (!(m_board_enbl & m_phantom)) return;
392	392
393	393	// LS96 inverts data
394	394	data ^= 0xff;
r12348	r12349
400	400	else if (offset == 0xfbf9) // DRIVE SEL
401	401	{
402	402	/*
403
404		bit description
405
406		0 DRIVE 1
407		1 DRIVE 2
408		2 DRIVE 3
409		3 DRIVE 4
410		4 IN USE / SIDE SELECT
411		5 INT ENBL
412		6 _ACCESS ENBL
413		7 START
414
415		*/
416
	403
	404	bit description
	405
	406	0 DRIVE 1
	407	1 DRIVE 2
	408	2 DRIVE 3
	409	3 DRIVE 4
	410	4 IN USE / SIDE SELECT
	411	5 INT ENBL
	412	6 _ACCESS ENBL
	413	7 START
	414
	415	*/
	416
417	417	// drive select
418	418	if (BIT(data, 0)) m_drive = 0;
419	419	if (BIT(data, 1)) m_drive = 1;
r12348	r12349
422	422	wd17xx_set_drive(m_fdc, m_drive);
423	423	floppy_mon_w(m_floppy0, CLEAR_LINE);
424	424	floppy_mon_w(m_floppy1, CLEAR_LINE);
425
	425
426	426	// side select
427	427	wd17xx_set_side(m_fdc, BIT(data, 4));
428
	428
429	429	// interrupt enable
430	430	m_int_enbl = BIT(data, 5);
431
	431
432	432	// access enable
433	433	m_access_enbl = BIT(data, 6);
434
	434
435	435	// master reset
436	436	wd17xx_mr_w(m_fdc, BIT(data, 7));
437	437	}
438	438	else if (offset == 0xfbfa) // FUNCTION SEL
439	439	{
440	440	/*
441
442		bit description
443
444		0 DOUBLE
445		1 8A SET
446		2 8A CLEAR
447		3 LEDOFF
448		4
449		5
450		6
451		7
452
453		*/
454
	441
	442	bit description
	443
	444	0 DOUBLE
	445	1 8A SET
	446	2 8A CLEAR
	447	3 LEDOFF
	448	4
	449	5
	450	6
	451	7
	452
	453	*/
	454
455	455	// density select
456	456	wd17xx_dden_w(m_fdc, BIT(data, 0));
457	457	}

src/mess/machine/coco_vhd.h
r12348	r12349
49	49	virtual void device_start();
50	50
51	51	void coco_vhd_readwrite(UINT8 data);
52
	52
53	53	UINT32 m_logical_record_number;
54	54	UINT32 m_buffer_address;
55	55	UINT8 m_status;

src/mess/machine/s100_dj2db.h
r12348	r12349
72	72	int m_drive; // selected drive
73	73	int m_head; // head loaded
74	74	int m_int_enbl; // interrupt enable
75
	75
76	76	// S-100 bus state
77	77	UINT8 *m_rom; // ROM
78	78	UINT8 *m_ram; // RAM

src/mess/machine/ecbbus.c
r12348	r12349
35	35
36	36
37	37	//-------------------------------------------------
38		// static_set_ecbbus_slot -
	38	// static_set_ecbbus_slot -
39	39	//-------------------------------------------------
40	40
41	41	void ecbbus_slot_device::static_set_ecbbus_slot(device_t &device, const char *tag, int num)
r12348	r12349
178	178	READ8_MEMBER( ecbbus_device::mem_r )
179	179	{
180	180	UINT8 data = 0;
181
	181
182	182	for (int i = 0; i < MAX_ECBBUS_SLOTS; i++)
183	183	{
184	184	if (m_ecbbus_device[i] != NULL)
r12348	r12349
190	190	return data;
191	191	}
192	192
193
	193
194	194	//-------------------------------------------------
195	195	// mem_w -
196	196	//-------------------------------------------------
r12348	r12349
214	214	READ8_MEMBER( ecbbus_device::io_r )
215	215	{
216	216	UINT8 data = 0;
217
	217
218	218	for (int i = 0; i < MAX_ECBBUS_SLOTS; i++)
219	219	{
220	220	if (m_ecbbus_device[i] != NULL)
r12348	r12349
226	226	return data;
227	227	}
228	228
229
	229
230	230	//-------------------------------------------------
231	231	// io_w -
232	232	//-------------------------------------------------
r12348	r12349
270	270	bool ecbbus_device::screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect)
271	271	{
272	272	bool value = false;
273
	273
274	274	for (int i = 0; i < MAX_ECBBUS_SLOTS; i++)
275	275	{
276	276	if (m_ecbbus_device[i] != NULL)
r12348	r12349
281	281	}
282	282	}
283	283	}
284
	284
285	285	return value;
286	286	}

src/mess/machine/ecbbus.h
r12348	r12349
64	64	public:
65	65	// construction/destruction
66	66	ecbbus_slot_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
67
	67
68	68	// device-level overrides
69	69	virtual void device_start();
70	70
r12348	r12349
115	115
116	116	DECLARE_WRITE_LINE_MEMBER( int_w );
117	117	DECLARE_WRITE_LINE_MEMBER( nmi_w );
118
	118
119	119	bool screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect);
120	120
121	121	protected:
r12348	r12349
130	130
131	131	devcb_resolved_write_line m_out_int_func;
132	132	devcb_resolved_write_line m_out_nmi_func;
133
	133
134	134	device_ecbbus_card_interface *m_ecbbus_device[MAX_ECBBUS_SLOTS];
135	135	const char *m_cputag;
136	136	};
r12348	r12349
146	146	class device_ecbbus_card_interface : public device_interface
147	147	{
148	148	friend class ecbbus_device;
149
	149
150	150	public:
151	151	// construction/destruction
152	152	device_ecbbus_card_interface(const machine_config &mconfig, device_t &device);

src/mess/machine/coco_pak.h
r12348	r12349
21	21	// construction/destruction
22	22	coco_pak_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
23	23	coco_pak_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
24
	24
25	25	// optional information overrides
26	26	virtual machine_config_constructor device_mconfig_additions() const;
27	27	virtual const rom_entry *device_rom_region() const;
28
	28
29	29	virtual UINT8* get_cart_base();
30	30	protected:
31	31	// device-level overrides
r12348	r12349
34	34	virtual void device_config_complete();
35	35
36	36	// internal state
37		device_image_interface *m_cart;
	37	device_image_interface *m_cart;
38	38	cococart_slot_device *m_owner;
39	39	};
40	40
r12348	r12349
55	55	// device-level overrides
56	56	virtual void device_reset();
57	57	virtual DECLARE_WRITE8_MEMBER(write);
58		private:
	58	private:
59	59	void banked_pak_set_bank(UINT32 bank);
60	60	};
61	61

src/mess/machine/coco_fdc.c
r12348	r12349
153	153
154	154
155	155	//**************************************************************************
156		// COCO FDC
	156	// COCO FDC
157	157	//**************************************************************************
158	158
159	159	static const wd17xx_interface coco_wd17xx_interface =
r12348	r12349
168	168	MCFG_WD1773_ADD(WD_TAG, coco_wd17xx_interface)
169	169	MCFG_MSM6242_ADD(DISTO_TAG)
170	170	MCFG_DS1315_ADD(CLOUD9_TAG)
171
	171
172	172	MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(coco_floppy_interface)
173	173	MACHINE_CONFIG_END
174	174
r12348	r12349
428	428
429	429
430	430	//**************************************************************************
431		// DRAGON FDC
	431	// DRAGON FDC
432	432	//**************************************************************************
433	433
434	434	static MACHINE_CONFIG_FRAGMENT(dragon_fdc)
435		MCFG_WD2797_ADD(WD_TAG, coco_wd17xx_interface)
	435	MCFG_WD2797_ADD(WD_TAG, coco_wd17xx_interface)
436	436	MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(coco_floppy_interface)
437	437	MACHINE_CONFIG_END
438	438
r12348	r12349
608	608	}
609	609
610	610	//**************************************************************************
611		// SDTANDY FDC
	611	// SDTANDY FDC
612	612	//**************************************************************************
613	613
614	614	ROM_START( sdtandy_fdc )
r12348	r12349
648	648	}
649	649
650	650	//**************************************************************************
651		// COCO FDC v1.1
	651	// COCO FDC v1.1
652	652	//**************************************************************************
653	653
654	654	ROM_START( coco_fdc_v11 )
r12348	r12349
691	691	}
692	692
693	693	//**************************************************************************
694		// CP400 FDC
	694	// CP400 FDC
695	695	//**************************************************************************
696	696
697	697	ROM_START( cp400_fdc )
r12348	r12349
728	728	const rom_entry *cp400_fdc_device::device_rom_region() const
729	729	{
730	730	return ROM_NAME( cp400_fdc );
731		}
		No newline at end of file
	731	}

src/mess/machine/coco_fdc.h
r12348	r12349
31	31	// construction/destruction
32	32	coco_fdc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
33	33	coco_fdc_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
34
	34
35	35	// optional information overrides
36	36	virtual machine_config_constructor device_mconfig_additions() const;
37	37	virtual const rom_entry *device_rom_region() const;
38
	38
39	39	virtual UINT8* get_cart_base();
40
	40
41	41	virtual void update_lines();
42	42	virtual void dskreg_w(UINT8 data);
43
	43
44	44	void set_intrq(UINT8 val) { m_intrq = val; }
45	45	void set_drq(UINT8 val) { m_drq = val; }
46	46	protected:
r12348	r12349
48	48	virtual void device_start();
49	49	virtual void device_config_complete();
50	50	virtual DECLARE_READ8_MEMBER(read);
51		virtual DECLARE_WRITE8_MEMBER(write);
	51	virtual DECLARE_WRITE8_MEMBER(write);
52	52
53	53	coco_rtc_type_t real_time_clock();
54
	54
55	55	// internal state
56	56	cococart_slot_device *m_owner;
57
	57
58	58	UINT8 m_dskreg;
59	59	UINT8 m_drq : 1;
60	60	UINT8 m_intrq : 1;
r12348	r12349
64	64
65	65	/* Disto RTC */
66	66	device_t m_disto_msm6242; / 6242 RTC on Disto interface */
67		offs_t m_msm6242_rtc_address;
	67	offs_t m_msm6242_rtc_address;
68	68	};
69	69
70	70
r12348	r12349
125	125	virtual machine_config_constructor device_mconfig_additions() const;
126	126	virtual const rom_entry *device_rom_region() const;
127	127	virtual void update_lines();
128		virtual void dskreg_w(UINT8 data);
	128	virtual void dskreg_w(UINT8 data);
129	129	protected:
130	130	// device-level overrides
131	131	virtual void device_start();
132	132	virtual void device_config_complete();
133	133	virtual DECLARE_READ8_MEMBER(read);
134		virtual DECLARE_WRITE8_MEMBER(write);
135		private:
	134	virtual DECLARE_WRITE8_MEMBER(write);
	135	private:
136	136	};
137	137
138	138

src/mess/machine/egret.c
r12348	r12349
1	1	/*
2		Apple "Egret" ADB/system controller MCU
3		Emulation by R. Belmont
	2	Apple "Egret" ADB/system controller MCU
	3	Emulation by R. Belmont
4	4
5		Port definitions, primarily from the schematics.
	5	Port definitions, primarily from the schematics.
6	6
7		Port A:
	7	Port A:
8	8
9		x------- O ADB data line out
10		-x------ I ADB data line in
11		--x----- I System type. 0 = hardware power switch, 1 = Egret controls power on/off
12		---x---- O DFAC latch
13		----x--- O ? (asserted briefly when resetting 680x0)
14		-----x-- I Keyboard power switch
15		------x- ? PSU enable OUT for system type 0, otherwise chassis power switch IN
16		-------x ? Control panel enable IN for system type 0 (e.g. LC), power supply enable OUT for type 1
	9	x------- O ADB data line out
	10	-x------ I ADB data line in
	11	--x----- I System type. 0 = hardware power switch, 1 = Egret controls power on/off
	12	---x---- O DFAC latch
	13	----x--- O ? (asserted briefly when resetting 680x0)
	14	-----x-- I Keyboard power switch
	15	------x- ? PSU enable OUT for system type 0, otherwise chassis power switch IN
	16	-------x ? Control panel enable IN for system type 0 (e.g. LC), power supply enable OUT for type 1
17	17
18		Port B:
	18	Port B:
19	19
20		x------- O DFAC bit clock
21		-x------ ? DFAC data I/O (used in both directions)
22		--x----- ? VIA shift register data (used in both directions)
23		---x---- O VIA clock
24		----x--- I VIA SYS_SESSION
25		-----x-- I VIA VIA_FULL
26		------x- O VIA XCEIVER SESSION
27		-------x I +5v sense
	20	x------- O DFAC bit clock
	21	-x------ ? DFAC data I/O (used in both directions)
	22	--x----- ? VIA shift register data (used in both directions)
	23	---x---- O VIA clock
	24	----x--- I VIA SYS_SESSION
	25	-----x-- I VIA VIA_FULL
	26	------x- O VIA XCEIVER SESSION
	27	-------x I +5v sense
28	28
29		Port C:
30		x--- O 680x0 reset
31		-x-- ? 680x0 IPL 2 (used in both directions)
32		--xx ? IPL 1/0 for hardware power switch, trickle sense (bit 1) and pulled up to +5v (bit 0) if Egret controls the PSU
	29	Port C:
	30	x--- O 680x0 reset
	31	-x-- ? 680x0 IPL 2 (used in both directions)
	32	--xx ? IPL 1/0 for hardware power switch, trickle sense (bit 1) and pulled up to +5v (bit 0) if Egret controls the PSU
33	33	*/
34	34
35	35	#define ADDRESS_MAP_MODERN
r12348	r12349
110	110	switch (offset)
111	111	{
112	112	case 0: // port A
113		/* printf("ADB:%d DFAC:%d PowerEnable:%d\n",
114		(data & 0x80) ? 1 : 0,
115		(data & 0x10) ? 1 : 0,
116		(data & 0x02) ? 1 : 0);*/
	113	/* printf("ADB:%d DFAC:%d PowerEnable:%d\n",
	114	(data & 0x80) ? 1 : 0,
	115	(data & 0x10) ? 1 : 0,
	116	(data & 0x02) ? 1 : 0);*/
117	117
118	118	if ((data & 0x80) != last_adb)
119	119	{
120		/* if (data & 0x80)
121		{
122		printf("EG ADB: 1->0 time %lld\n", m_maincpu->total_cycles()-last_adb_time);
123		}
124		else
125		{
126		printf("EG ADB: 0->1 time %lld\n", m_maincpu->total_cycles()-last_adb_time);
127		}*/
	120	/* if (data & 0x80)
	121	{
	122	printf("EG ADB: 1->0 time %lld\n", m_maincpu->total_cycles()-last_adb_time);
	123	}
	124	else
	125	{
	126	printf("EG ADB: 0->1 time %lld\n", m_maincpu->total_cycles()-last_adb_time);
	127	}*/
128	128	last_adb = data & 0x80;
129	129	last_adb_time = m_maincpu->total_cycles();
130	130	}
r12348	r12349
196	196
197	197	WRITE8_MEMBER( egret_device::ddr_w )
198	198	{
199		/* printf("%02x to DDR %c\n", data, 'A' + offset);*/
	199	/* printf("%02x to DDR %c\n", data, 'A' + offset);*/
200	200
201	201	send_port(space, offset, ports[offset] & data);
202	202
r12348	r12349
209	209
210	210	switch (offset)
211	211	{
212		case 0: // port A
213		// incoming \|= adb_in ? 0x40 : 0;
	212	case 0: // port A
	213	// incoming \|= adb_in ? 0x40 : 0;
214	214
215	215	if (egret_controls_power)
216	216	{
r12348	r12349
218	218	}
219	219	else
220	220	{
221		//incoming \|= 0x01; // enable control panel enabled
	221	//incoming \|= 0x01; // enable control panel enabled
222	222	}
223	223	break;
224	224
r12348	r12349
238	238	break;
239	239	}
240	240
241		// apply data direction registers
	241	// apply data direction registers
242	242	incoming &= (ddrs[offset] ^ 0xff);
243	243	// add in ddr-masked version of port writes
244	244	incoming \|= (ports[offset] & ddrs[offset]);
r12348	r12349
282	282
283	283	WRITE8_MEMBER( egret_device::timer_ctrl_w )
284	284	{
285		// printf("%02x to timer control\n", data);
	285	// printf("%02x to timer control\n", data);
286	286	timer_ctrl = data;
287	287	}
288	288
r12348	r12349
293	293
294	294	WRITE8_MEMBER( egret_device::timer_counter_w )
295	295	{
296		// printf("%02x to timer/counter\n", data);
	296	// printf("%02x to timer/counter\n", data);
297	297	timer_counter = data;
298	298	}
299	299
r12348	r12349
306	306	{
307	307	static const float rates[4] = { 0.5f, 1.0f, 2.0f, 4.0f };
308	308
309		// printf("%02x to one-second control\n", data);
	309	// printf("%02x to one-second control\n", data);
310	310
311	311	m_timer->adjust(attotime::from_hz(rates[data&3]), 0, attotime::from_hz(rates[data&3]));
312	312

src/mess/machine/pc1512kb.c
r12348	r12349
203	203
204	204	PORT_START("Y10")
205	205	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad Enter") PORT_CODE(KEYCODE_ENTER_PAD)
206		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
	206	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
207	207	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad -") PORT_CODE(KEYCODE_MINUS_PAD)
208		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
	208	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
209	209	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 6 "UTF8_RIGHT) PORT_CODE(KEYCODE_6_PAD)
210		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
	210	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
211	211	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 3 Pg Dn") PORT_CODE(KEYCODE_3_PAD)
212	212	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Del "UTF8_RIGHT) PORT_CODE(KEYCODE_DEL) PORT_CHAR(UCHAR_MAMEKEY(DEL))
213	213
r12348	r12349
220	220	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 0 Ins") PORT_CODE(KEYCODE_0_PAD)
221	221	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad . Del") PORT_CODE(KEYCODE_DEL_PAD)
222	222	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad +") PORT_CODE(KEYCODE_PLUS_PAD)
223
	223
224	224	PORT_START("COM")
225		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
226		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
227		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
228		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
229		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
230		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
231		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
232		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
	225	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
	226	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
	227	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
	228	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
	229	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
	230	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
	231	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
	232	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
233	233	INPUT_PORTS_END
234	234
235	235
r12348	r12349
343	343	{
344	344	/*
345	345
346		bit description
	346	bit description
347	347
348		0 X1
349		1 X2
350		2 X3
351		3 X4
352		4 X5
353		5 X6
354		6 X7
355		7 X8
	348	0 X1
	349	1 X2
	350	2 X3
	351	3 X4
	352	4 X5
	353	5 X6
	354	6 X7
	355	7 X8
356	356
357		*/
	357	*/
358	358
359	359	UINT8 data = 0xff;
360
	360
361	361	if (!BIT(m_kb_y, 0)) data &= input_port_read(this, "Y1");
362	362	if (!BIT(m_kb_y, 1)) data &= input_port_read(this, "Y2");
363	363	if (!BIT(m_kb_y, 2)) data &= input_port_read(this, "Y3");
r12348	r12349
370	370	if (!BIT(m_kb_y, 9)) data &= input_port_read(this, "Y10");
371	371	if (!BIT(m_kb_y, 10)) data &= input_port_read(this, "Y11");
372	372	if (!m_joy_com) data &= input_port_read(this, "COM");
373
	373
374	374	return data;
375	375	}
376	376
r12348	r12349
383	383	{
384	384	/*
385	385
386		bit description
	386	bit description
387	387
388		0 Y1
389		1 Y2
390		2 Y3
391		3 Y4
392		4 Y5
393		5 Y6
394		6 Y7
395		7 Y8
	388	0 Y1
	389	1 Y2
	390	2 Y3
	391	3 Y4
	392	4 Y5
	393	5 Y6
	394	6 Y7
	395	7 Y8
396	396
397		*/
	397	*/
398	398
399	399	m_kb_y = (m_kb_y & 0xff00) \| data;
400	400	}
r12348	r12349
408	408	{
409	409	/*
410	410
411		bit description
	411	bit description
412	412
413		0 SERIAL DATA
414		1 SERIAL CLOCK
415		2
416		3
417		4
418		5
419		6
420		7
	413	0 SERIAL DATA
	414	1 SERIAL CLOCK
	415	2
	416	3
	417	4
	418	5
	419	6
	420	7
421	421
422		*/
423
	422	*/
	423
424	424	UINT8 data = 0;
425	425
426	426	data \|= m_data_in;
427	427	data \|= m_clock_in << 1;
428
	428
429	429	return data;
430	430	}
431	431
r12348	r12349
438	438	{
439	439	/*
440	440
441		bit description
	441	bit description
442	442
443		0 SERIAL DATA
444		1 SERIAL CLOCK
445		2 CAPS LED
446		3 NUM LED
447		4 Y9
448		5 Y10
449		6 Y11
450		7 joystick COM
	443	0 SERIAL DATA
	444	1 SERIAL CLOCK
	445	2 CAPS LED
	446	3 NUM LED
	447	4 Y9
	448	5 Y10
	449	6 Y11
	450	7 joystick COM
451	451
452		*/
453
	452	*/
	453
454	454	// keyboard data
455	455	m_out_data_func(BIT(data, 0));
456	456
457	457	// keyboard clock
458	458	m_out_clock_func(BIT(data, 1));
459
	459
460	460	// CAPS LOCK
461	461	output_set_led_value(LED_CAPS, BIT(data, 2));
462
	462
463	463	// NUM LOCK
464	464	output_set_led_value(LED_NUM, BIT(data, 3));
465
	465
466	466	// keyboard row
467	467	m_kb_y = (((data >> 4) & 0x07) << 8) \| (m_kb_y & 0xff);
468	468

src/mess/machine/amigafdc.c
r12348	r12349
145	145	int bytes;
146	146	int pos;
147	147	amiga_fdc_t *fdc = get_safe_token(device);
148
	148
149	149	elapsed = fdc->fdc_status[drive].f->get_pos();
150	150	speed = ( CUSTOM_REG(REG_ADKCON) & 0x100 ) ? 2 : 4;
151	151
r12348	r12349
347	347	static void setup_fdc_buffer( device_t *device,int drive )
348	348	{
349	349	amiga_fdc_t *fdc = get_safe_token(device);
350		fdc->fdc_status[drive].mfm = fdc->fdc_status[drive].f->get_buffer();
	350	fdc->fdc_status[drive].mfm = fdc->fdc_status[drive].f->get_buffer();
351	351	}
352	352
353	353
r12348	r12349
373	373	amiga_fdc_t *fdc = get_safe_token(device);
374	374
375	375	if ( fdc->fdc_sel != ( ( data >> 3 ) & 15 ) )
376		fdc->fdc_rdy = 0;
	376	fdc->fdc_rdy = 0;
377	377	fdc->fdc_sel = ( data >> 3 ) & 15;
378
	378
379	379	for ( drive = 0; drive < NUM_DRIVES; drive++ ) {
380	380	if ( !( fdc->fdc_sel & ( 1 << drive ) ) ) {
381		fdc->fdc_status[drive].f->ss_w(( data >> 2 ) & 1);
382		fdc->fdc_status[drive].f->dir_w(( data >> 1 ) & 1);
	381	fdc->fdc_status[drive].f->ss_w(( data >> 2 ) & 1);
	382	fdc->fdc_status[drive].f->dir_w(( data >> 1 ) & 1);
383	383	fdc->fdc_status[drive].f->stp_w(data & 1);
384
	384
385	385	fdc->fdc_status[drive].f->mon_w((( data >> 7 ) & 1) );
386	386	fdc_setup_leds( device,drive );
387	387	}
r12348	r12349
411	411
412	412	if ( fdc->fdc_status[drive].f->dskchg_r() == 0)
413	413	ret &= ~0x04;
414
	414
415	415	return ret;
416	416	}
417	417	}
r12348	r12349
420	420	}
421	421
422	422	WRITE_LINE_DEVICE_HANDLER(amiga_index_callback)
423		{
	423	{
424	424	/* Issue a index pulse when a disk revolution completes */
425	425	device_t *cia = device->machine().device("cia_1");
426	426	mos6526_flag_w(cia, state);

src/mess/machine/pc1512kb.h
r12348	r12349
82	82	devcb_resolved_write_line m_out_clock_func;
83	83
84	84	required_device<cpu_device> m_maincpu;
85
	85
86	86	int m_data_in;
87	87	int m_clock_in;
88	88	int m_kb_y;

src/mess/machine/cpc_ssa1.h
r12348	r12349
3	3	*
4	4	* Created on: 16/07/2011
5	5	*
6		* Amstrad SSA-1 - SP0256-AL2 based Speech Synthesiser and Sound Amplifier
	6	* Amstrad SSA-1 - SP0256-AL2 based Speech Synthesiser and Sound Amplifier
7	7	*
8	8	* Uses on-board resonator, clocked at 3.12MHz
9	9	*

src/mess/machine/comx_fd.c
r12348	r12349
138	138	//**************************************************************************
139	139
140	140	//-------------------------------------------------
141		// update_ef4 -
	141	// update_ef4 -
142	142	//-------------------------------------------------
143	143
144	144	inline void comx_fd_device::update_ef4()
r12348	r12349
239	239	UINT8 comx_fd_device::comx_mrd_r(offs_t offset, int *extrom)
240	240	{
241	241	UINT8 data = 0xff;
242
	242
243	243	if (offset >= 0x0dd0 && offset < 0x0de0)
244	244	{
245	245	data = m_rom[offset & 0x1fff];
r12348	r12349
249	249	{
250	250	data = m_rom[offset & 0x1fff];
251	251	}
252
	252
253	253	return data;
254	254	}
255	255
r12348	r12349
290	290	{
291	291	/*
292	292
293		bit description
	293	bit description
294	294
295		0 A0
296		1 A1
297		2 DRIVE0
298		3 DRIVE1
299		4 F9 DISB
300		5 SIDE SELECT
	295	0 A0
	296	1 A1
	297	2 DRIVE0
	298	3 DRIVE1
	299	4 F9 DISB
	300	5 SIDE SELECT
301	301
302		*/
	302	*/
303	303
304	304	// latch data to F3
305	305	m_addr = data & 0x03;
r12348	r12349
315	315
316	316	m_disb = !BIT(data, 4);
317	317	update_ef4();
318
	318
319	319	wd17xx_set_side(m_fdc, BIT(data, 5));
320	320	}
321	321	else

src/mess/machine/c64_xl80.c
r12348	r12349
6	6	PCB Layout
7	7	----------
8	8
9		\|==================================\|
10		\| LS175 LS20 LS139 \|
11		\| LS157 \|
	9	\|==================================\|
	10	\| LS175 LS20 LS139 \|
	11	\| LS157 \|
12	12	\|=======\| \|
13	13	\|=\| RAM \|
14	14	\|=\| LS157 LS157 LS165 \|
r12348	r12349
19	19	\|=\| ROM0 LS245 LS151 \|
20	20	\|=\| 14.31818MHz\|
21	21	\|=======\| LS174 LS00 \|
22		\| HCU04 \|
23		\| LS74 LS161 LS74 \|
24		\|==================================\|
	22	\| HCU04 \|
	23	\| LS74 LS161 LS74 \|
	24	\|==================================\|
25	25
26	26	Notes:
27	27	All IC's shown.
28	28
29		CRTC - Hitachi HD46505SP
30		RAM - Toshiba TMM2016AP-12 2Kx8 Static RAM
31		ROM0 - GI 9433CS-0090 8Kx8 ROM?
32		ROM1 - GI 9316CS-F67 2Kx8 ROM? "DTC"
33		CN1 - RCA video output
	29	CRTC - Hitachi HD46505SP
	30	RAM - Toshiba TMM2016AP-12 2Kx8 Static RAM
	31	ROM0 - GI 9433CS-0090 8Kx8 ROM?
	32	ROM1 - GI 9316CS-F67 2Kx8 ROM? "DTC"
	33	CN1 - RCA video output
34	34
35	35	*/
36	36
r12348	r12349
148	148	MCFG_SCREEN_VISIBLE_AREA(0, 808-1, 0, 248-1)
149	149	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
150	150	MCFG_SCREEN_REFRESH_RATE(50)
151
	151
152	152	//MCFG_GFXDECODE(c64_xl80)
153	153
154	154	MCFG_MC6845_ADD(HD46505SP_TAG, H46505, XTAL_14_31818MHz, crtc_intf)
r12348	r12349
217	217	UINT8 c64_xl80_device::c64_cd_r(offs_t offset, int roml, int romh, int io1, int io2)
218	218	{
219	219	UINT8 data = 0;
220
	220
221	221	if (!io2 && BIT(offset, 1))
222	222	{
223	223	address_space *space = machine().firstcpu->memory().space(AS_PROGRAM);
224
	224
225	225	if (offset & 0x01)
226	226	{
227	227	data = m_crtc->register_r(*space, 0);
r12348	r12349
249	249	if (!io2 && BIT(offset, 1))
250	250	{
251	251	address_space *space = machine().firstcpu->memory().space(AS_PROGRAM);
252
	252
253	253	if (offset & 0x01)
254	254	{
255	255	m_crtc->register_w(*space, 0, data);

src/mess/machine/comx_thm.c
r12348	r12349
79	79	UINT8 comx_thm_device::comx_mrd_r(offs_t offset, int *extrom)
80	80	{
81	81	UINT8 data = 0;
82
	82
83	83	if (offset >= 0xc000 && offset < 0xd000)
84	84	{
85	85	data = m_rom[offset & 0xfff];
86	86	}
87
	87
88	88	return data;
89	89	}
90	90
r12348	r12349
96	96	UINT8 comx_thm_device::comx_io_r(offs_t offset)
97	97	{
98	98	/*
99		INP 2 is used for the printer status, where:
100		b0=1: Printer Not Ready
101		b1=1: Energizing Head
102		b2=1: Head At Position 0
103		*/
	99	INP 2 is used for the printer status, where:
	100	b0=1: Printer Not Ready
	101	b1=1: Energizing Head
	102	b2=1: Head At Position 0
	103	*/
104	104
105	105	return 0;
106	106	}
r12348	r12349
113	113	void comx_thm_device::comx_io_w(offs_t offset, UINT8 data)
114	114	{
115	115	/*
116		OUT 2 is used to control the thermal printer where:
117		Q = 0, b0-7: Pixel 1 to 8
118		Q = 1, b7: Pixel 9 (if b0-6=#21)
119		Q = 1, b3=1: Move head right
120		Q = 1, b0-7=#12: Move head left
121		*/
	116	OUT 2 is used to control the thermal printer where:
	117	Q = 0, b0-7: Pixel 1 to 8
	118	Q = 1, b7: Pixel 9 (if b0-6=#21)
	119	Q = 1, b3=1: Move head right
	120	Q = 1, b0-7=#12: Move head left
	121	*/
122	122	}

src/mess/machine/comx_prn.c
r12348	r12349
85	85	UINT8 comx_prn_device::comx_mrd_r(offs_t offset, int *extrom)
86	86	{
87	87	UINT8 data = 0;
88
	88
89	89	if (offset >= 0xc000 && offset < 0xd000)
90	90	{
91	91	data = m_rom[offset & 0xfff];
92	92	}
93
	93
94	94	return data;
95	95	}
96	96
r12348	r12349
102	102	UINT8 comx_prn_device::comx_io_r(offs_t offset)
103	103	{
104	104	/*
105		Parallel:
106
107		INP 2 for the printer status, where:
108		b0=1: Acknowledge Fault
109		b1=0: Device Busy
110		b2=0: Paper Empty
111		b3=1: Device Not Selected
112
113		Serial:
114
115		INP 2 for the printer status and to start a new range of bits for the next byte.
116		*/
	105	Parallel:
117	106
	107	INP 2 for the printer status, where:
	108	b0=1: Acknowledge Fault
	109	b1=0: Device Busy
	110	b2=0: Paper Empty
	111	b3=1: Device Not Selected
	112
	113	Serial:
	114
	115	INP 2 for the printer status and to start a new range of bits for the next byte.
	116	*/
	117
118	118	return 0;
119	119	}
120	120
r12348	r12349
126	126	void comx_prn_device::comx_io_w(offs_t offset, UINT8 data)
127	127	{
128	128	/*
129		Parallel:
130
131		OUT 2 is used to send a byte to the printer
132
133		Serial:
134
135		OUT 2 is used to send a bit to the printer
136		*/
	129	Parallel:
	130
	131	OUT 2 is used to send a byte to the printer
	132
	133	Serial:
	134
	135	OUT 2 is used to send a bit to the printer
	136	*/
137	137	}

src/mess/machine/mac.c
r12348	r12349
100	100	#define ADB_IS_PM ((mac->m_model >= MODEL_MAC_PORTABLE && mac->m_model <= MODEL_MAC_PB100) \|\| (mac->m_model >= MODEL_MAC_PB140 && mac->m_model <= MODEL_MAC_PBDUO_270c))
101	101	#define ADB_IS_PM_VIA1 (mac->m_model >= MODEL_MAC_PORTABLE && mac->m_model <= MODEL_MAC_PB100)
102	102	#define ADB_IS_PM_VIA2 (mac->m_model >= MODEL_MAC_PB140 && mac->m_model <= MODEL_MAC_PBDUO_270c)
103		#define ADB_IS_PM_CLASS ((m_model >= MODEL_MAC_PORTABLE && m_model <= MODEL_MAC_PB100) \|\| (m_model >= MODEL_MAC_PB140 && m_model <= MODEL_MAC_PBDUO_270c))
	103	#define ADB_IS_PM_CLASS ((m_model >= MODEL_MAC_PORTABLE && m_model <= MODEL_MAC_PB100) \|\| (m_model >= MODEL_MAC_PB140 && m_model <= MODEL_MAC_PBDUO_270c))
104	104
105	105	#define AUDIO_IS_CLASSIC (mac->m_model <= MODEL_MAC_CLASSIC)
106	106	#define MAC_HAS_VIA2 ((m_model >= MODEL_MAC_II) && (m_model != MODEL_MAC_IIFX))
r12348	r12349
351	351	}
352	352	else if ((mac->m_model == MODEL_MAC_PORTABLE) \|\| (mac->m_model == MODEL_MAC_PB100))
353	353	{
354		// m_asc_interrupt = state;
355		// mac->field_interrupts();
	354	// m_asc_interrupt = state;
	355	// mac->field_interrupts();
356	356	}
357	357	else if ((mac->m_model >= MODEL_MAC_II) && (mac->m_model != MODEL_MAC_IIFX))
358	358	{
r12348	r12349
413	413	is_rom = FALSE;
414	414	}
415	415
416		// printf("mac_v8_resize: memory_size = %x, ctrl bits %02x (overlay %d = %s)\n", memory_size, m_rbv_regs[1] & 0xe0, m_overlay, is_rom ? "ROM" : "RAM");
	416	// printf("mac_v8_resize: memory_size = %x, ctrl bits %02x (overlay %d = %s)\n", memory_size, m_rbv_regs[1] & 0xe0, m_overlay, is_rom ? "ROM" : "RAM");
417	417
418	418	if (is_rom)
419	419	{
r12348	r12349
2119	2119
2120	2120	case 0x20: // send ADB command (PMU must issue an IRQ on completion)
2121	2121	#if 0
2122		printf("PMU: Send ADB %02x %02x cmd %02x flag %02x data %02x\n",
	2122	printf("PMU: Send ADB %02x %02x cmd %02x flag %02x data %02x\n",
2123	2123	mac->m_pm_cmd[0],
2124	2124	mac->m_pm_cmd[1],
2125	2125	mac->m_pm_cmd[2],
r12348	r12349
2129	2129
2130	2130	if (((mac->m_pm_cmd[2] == 0xfc) \|\| (mac->m_pm_cmd[2] == 0x2c)) && (mac->m_pm_cmd[3] == 4))
2131	2131	{
2132		// printf("PMU: request to poll ADB, returning nothing\n");
	2132	// printf("PMU: request to poll ADB, returning nothing\n");
2133	2133	mac->m_pm_slen = 0;
2134	2134	mac->m_pmu_int_status = 0;
2135	2135	}
r12348	r12349
2289	2289	{
2290	2290	mac->m_pm_out[0] = mac->m_pm_out[1] = 2;
2291	2291	mac->m_pm_out[2] = mac->m_pmu_int_status; // ADB status in low nibble
2292		mac->m_pm_out[3] = mac->m_pmu_last_adb_command; // ADB command that was sent OR 0x80 for extra error-ness
	2292	mac->m_pm_out[3] = mac->m_pmu_last_adb_command; // ADB command that was sent OR 0x80 for extra error-ness
2293	2293	mac->m_pm_out[4] = 0; // return data
2294	2294	mac->m_pm_slen = 4;
2295	2295	mac->m_pmu_send_timer->adjust(attotime(0, ATTOSECONDS_IN_USEC(1500)));
r12348	r12349
2326	2326	int i;
2327	2327
2328	2328	mac->m_pm_out[0] = mac->m_pm_out[1] = mac->m_pm_cmd[4];
2329		// printf("PMU read at %x\n", mac->m_pm_cmd[2] \| (mac->m_pm_cmd[3]<<8));
	2329	// printf("PMU read at %x\n", mac->m_pm_cmd[2] \| (mac->m_pm_cmd[3]<<8));
2330	2330
2331	2331	// note: read at 0xEE00 0 = target disk mode, 0xff = normal bootup
2332	2332
r12348	r12349
2536	2536	case MODEL_MAC_IICX:
2537	2537	return 0x81 \| PA6;
2538	2538
2539		case MODEL_MAC_PB140: // since the ASICs are different, these are allowed to "collide"
	2539	case MODEL_MAC_PB140: // since the ASICs are different, these are allowed to "collide"
2540	2540	case MODEL_MAC_PB160:
2541	2541	case MODEL_MAC_CLASSIC_II:
2542	2542	case MODEL_MAC_QUADRA_800:
r12348	r12349
3033	3033	m_6015_timer->adjust(attotime::from_hz(60.15), 0, attotime::from_hz(60.15));
3034	3034	}
3035	3035
3036		// we use the CPU clock divided by the VIA clock (783360 Hz) rounded up as
	3036	// we use the CPU clock divided by the VIA clock (783360 Hz) rounded up as
3037	3037	// an approximation for the right number of wait states. this yields good
3038	3038	// results - it's towards the end of the worst-case delay on h/w.
3039	3039	switch (m_maincpu->clock())
r12348	r12349
3469	3469	WRITE_LINE_MEMBER(mac_state::nubus_irq_e_w)
3470	3470	{
3471	3471	nubus_slot_interrupt(0xe, state);
3472		}
	3472	}
3473	3473
3474	3474	/* *************************************************************************
3475	3475	* Trap Tracing

src/mess/machine/coco_232.h
r12348	r12349
30	30	virtual DECLARE_WRITE8_MEMBER(write);
31	31	private:
32	32	// internal state
33		device_t *m_uart;
	33	device_t *m_uart;
34	34	};
35	35
36	36

src/mess/machine/comx_ram.c
r12348	r12349
64	64	UINT8 comx_ram_device::comx_mrd_r(offs_t offset, int *extrom)
65	65	{
66	66	UINT8 data = 0;
67
	67
68	68	if (offset >= 0xc000 && offset < 0xd000)
69	69	{
70	70	data = (m_ram_bank << 12) \| m_ram[offset & 0xfff];
71	71	}
72
	72
73	73	return data;
74	74	}
75	75

src/mess/machine/c64_std.c
r12348	r12349
93	93	UINT8 c64_standard_cartridge_device::c64_cd_r(offs_t offset, int roml, int romh, int io1, int io2)
94	94	{
95	95	UINT8 data = 0;
96
	96
97	97	if (offset >= 0x8000 && offset < 0xc000)
98	98	{
99	99	data = m_rom[offset & 0x3fff];

src/mess/machine/isa.c
r12348	r12349
144	144	isa8_device::isa8_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
145	145	device_t(mconfig, ISA8, "ISA8", tag, owner, clock)
146	146	{
147		}
	147	}
148	148
149	149	isa8_device::isa8_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock) :
150	150	device_t(mconfig, type, name, tag, owner, clock)
r12348	r12349
371	371	memset(&(isa8bus_interface::m_out_irq5_cb), 0, sizeof(isa8bus_interface::m_out_irq5_cb));
372	372	memset(&(isa8bus_interface::m_out_irq6_cb), 0, sizeof(isa8bus_interface::m_out_irq6_cb));
373	373	memset(&(isa8bus_interface::m_out_irq7_cb), 0, sizeof(isa8bus_interface::m_out_irq7_cb));
374
	374
375	375	memset(&m_out_irq10_cb, 0, sizeof(m_out_irq10_cb));
376	376	memset(&m_out_irq11_cb, 0, sizeof(m_out_irq11_cb));
377	377	memset(&m_out_irq12_cb, 0, sizeof(m_out_irq12_cb));
r12348	r12349
382	382	memset(&(isa8bus_interface::m_out_drq1_cb), 0, sizeof(isa8bus_interface::m_out_drq1_cb));
383	383	memset(&(isa8bus_interface::m_out_drq2_cb), 0, sizeof(isa8bus_interface::m_out_drq2_cb));
384	384	memset(&(isa8bus_interface::m_out_drq3_cb), 0, sizeof(isa8bus_interface::m_out_drq3_cb));
385
	385
386	386	memset(&m_out_drq5_cb, 0, sizeof(m_out_drq5_cb));
387	387	memset(&m_out_drq6_cb, 0, sizeof(m_out_drq6_cb));
388	388	memset(&m_out_drq7_cb, 0, sizeof(m_out_drq7_cb));
r12348	r12349
403	403	m_out_irq12_func.resolve(m_out_irq12_cb, *this);
404	404	m_out_irq14_func.resolve(m_out_irq14_cb, *this);
405	405	m_out_irq15_func.resolve(m_out_irq15_cb, *this);
406
	406
407	407	m_out_drq0_func.resolve(m_out_drq0_cb, *this);
408	408	m_out_drq5_func.resolve(m_out_drq5_cb, *this);
409	409	m_out_drq6_func.resolve(m_out_drq6_cb, *this);

src/mess/machine/isa.h
r12348	r12349
36	36	A29 IO A2 B29 +5V
37	37	A30 IO A1 B30 I OSC
38	38	A31 IO A0 B31 GND
39
40		16 bit ISA bus extension
41
	39
	40	16 bit ISA bus extension
	41
42	42	C1 I SBHE D1 I /MEM CS 16
43	43	C2 IO A23 D2 I /I/O CS 16
44	44	C3 IO A22 D3 O IRQ10
r12348	r12349
49	49	C8 IO A17 D8 I /DACK0
50	50	C9 I /MEMR D9 O DRQ0
51	51	C10 I /MEMW D10 I /DACK5
52		C11 IO D8 D11 O DRQ5
	52	C11 IO D8 D11 O DRQ5
53	53	C12 IO D9 D12 I /DACK6
54	54	C13 IO D10 D13 O DRQ6
55	55	C14 IO D11 D14 I /DACK7
r12348	r12349
85	85	#define MCFG_ISA_ONBOARD_ADD(_isatag, _tag, _dev_type, _def_inp) \
86	86	MCFG_DEVICE_ADD(_tag, _dev_type, 0) \
87	87	MCFG_DEVICE_INPUT_DEFAULTS(_def_inp) \
88		device_isa8_card_interface::static_set_isabus_tag(*device, _isatag);
	88	device_isa8_card_interface::static_set_isabus_tag(*device, _isatag);
89	89
90	90
91	91	#define MCFG_ISA16_BUS_ADD(_tag, _cputag, _config) \
r12348	r12349
97	97	MCFG_DEVICE_ADD(_tag, ISA16_SLOT, 0) \
98	98	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _def_inp) \
99	99	isa16_slot_device::static_set_isa16_slot(*device, _isatag); \
100
	100
101	101	//**************************************************************************
102	102	// TYPE DEFINITIONS
103	103	//**************************************************************************
r12348	r12349
111	111	// construction/destruction
112	112	isa8_slot_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
113	113	isa8_slot_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
114
115		// device-level overrides
	114
	115	// device-level overrides
116	116	virtual void device_start();
117	117
118	118	// inline configuration
r12348	r12349
212	212	virtual ~device_isa8_card_interface();
213	213
214	214	device_isa8_card_interface *next() const { return m_next; }
215
	215
216	216	void set_isa_device();
217	217	// configuration access
218	218	virtual UINT8 dack_r(int line);
r12348	r12349
238	238	devcb_write_line m_out_irq5_cb;
239	239	devcb_write_line m_out_irq6_cb;
240	240	devcb_write_line m_out_irq7_cb;
241
	241
242	242	devcb_write_line m_out_irq10_cb;
243	243	devcb_write_line m_out_irq11_cb;
244	244	devcb_write_line m_out_irq12_cb;
245	245	devcb_write_line m_out_irq14_cb;
246	246	devcb_write_line m_out_irq15_cb;
247
	247
248	248	devcb_write_line m_out_drq0_cb;
249	249	devcb_write_line m_out_drq1_cb;
250	250	devcb_write_line m_out_drq2_cb;
r12348	r12349
261	261	public:
262	262	// construction/destruction
263	263	isa16_slot_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
264		// device-level overrides
	264	// device-level overrides
265	265	virtual void device_start();
266	266
267	267	// inline configuration
268		static void static_set_isa16_slot(device_t &device, const char *tag);
	268	static void static_set_isa16_slot(device_t &device, const char *tag);
269	269	};
270	270
271	271
r12348	r12349
279	279	public:
280	280	// construction/destruction
281	281	isa16_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
282
	282
283	283	void install16_device(device_t dev, offs_t start, offs_t end, offs_t mask, offs_t mirror, read16_device_func rhandler, const char rhandler_name, write16_device_func whandler, const char *whandler_name);
284	284
285	285	DECLARE_WRITE_LINE_MEMBER( irq10_w );
r12348	r12349
292	292	DECLARE_WRITE_LINE_MEMBER( drq5_w );
293	293	DECLARE_WRITE_LINE_MEMBER( drq6_w );
294	294	DECLARE_WRITE_LINE_MEMBER( drq7_w );
295
	295
296	296	protected:
297	297	// device-level overrides
298	298	virtual void device_start();
299	299	virtual void device_config_complete();
300
	300
301	301	private:
302	302	// internal state
303	303	devcb_resolved_write_line m_out_irq10_func;
r12348	r12349
328	328	virtual ~device_isa16_card_interface();
329	329
330	330	void set_isa_device();
331		isa16_device *m_isa;
	331	isa16_device *m_isa;
332	332	};
333	333
334	334	#endif /* __ISA_H__ */

src/mess/machine/coco_multi.c
r12348	r12349
4	4
5	5	Code for emulating CoCo's Multi-Pak Interface
6	6
7		The Multi-Pak interface multiplexes all I/O lines from the Color
8		Computer's expansion port to four identical ports. All I/O lines
9		are continuously multiplexed except:
10
11		Pin 36 - *SCS
12		Pin 32 - *CTS
13		Pin 8 - *CART
14
15		These I/O lines are switched in one of two ways. First, is the front
16		panel, four position switch. When adjusted the switch will direct the
17		MPI to target these three I/O lines to the selected slot.
18
19		Second, the MPI will listen to writes to 0xff7f and respond accordingly:
20
21		bit 0 --\___ Target *SCS to this slot number
22		bit 1 --/
23		bit 2 ------ Ignore
24		bit 3 ------ Ignore
25		bit 4 --\___ Target CTS and CART to this slot number
26		bit 5 --/
27		bit 6 ------ Ignore
28		bit 7 ------ Ignore
29
30		After writing to 0xff7f, the position of the physical switch has no
31		effect until reset.
32
33		Reading is supported on 0xff7f. It will reflect the position of the
34		physical switch. Until data is written to 0xff7f, then it will only
35		reflect what has been written until a reset.
36
37		A common modification users of the OS-9 operating system made was to
38		tie all of the CART pins together on the MPI motherboard. The CART
39		line is connected to the 6809's IRQ line. This allowed any hardware
40		device in any slot to signal an IRQ to the CPU, no matter what the
41		switch position was. OS-9 was designed from the very start to poll
42		each device attached on every IQR signal.
43
44		Because of sloppy address decoding the original MPI also responds to
45		0xff9f. No software is known to take advantage of this. After the
46		introduction of the CoCo 3, which uses 0xff9f internally, Tandy provided
47		free upgrades to any MPI to fix this problem.
48
49
	7	The Multi-Pak interface multiplexes all I/O lines from the Color
	8	Computer's expansion port to four identical ports. All I/O lines
	9	are continuously multiplexed except:
	10
	11	Pin 36 - *SCS
	12	Pin 32 - *CTS
	13	Pin 8 - *CART
	14
	15	These I/O lines are switched in one of two ways. First, is the front
	16	panel, four position switch. When adjusted the switch will direct the
	17	MPI to target these three I/O lines to the selected slot.
	18
	19	Second, the MPI will listen to writes to 0xff7f and respond accordingly:
	20
	21	bit 0 --\___ Target *SCS to this slot number
	22	bit 1 --/
	23	bit 2 ------ Ignore
	24	bit 3 ------ Ignore
	25	bit 4 --\___ Target CTS and CART to this slot number
	26	bit 5 --/
	27	bit 6 ------ Ignore
	28	bit 7 ------ Ignore
	29
	30	After writing to 0xff7f, the position of the physical switch has no
	31	effect until reset.
	32
	33	Reading is supported on 0xff7f. It will reflect the position of the
	34	physical switch. Until data is written to 0xff7f, then it will only
	35	reflect what has been written until a reset.
	36
	37	A common modification users of the OS-9 operating system made was to
	38	tie all of the CART pins together on the MPI motherboard. The CART
	39	line is connected to the 6809's IRQ line. This allowed any hardware
	40	device in any slot to signal an IRQ to the CPU, no matter what the
	41	switch position was. OS-9 was designed from the very start to poll
	42	each device attached on every IQR signal.
	43
	44	Because of sloppy address decoding the original MPI also responds to
	45	0xff9f. No software is known to take advantage of this. After the
	46	introduction of the CoCo 3, which uses 0xff9f internally, Tandy provided
	47	free upgrades to any MPI to fix this problem.
	48
	49
50	50	***************************************************************************/
51	51
52	52	#include "emu.h"
r12348	r12349
142	142	m_slot3 = dynamic_cast<cococart_slot_device *>(subdevice(SLOT3_TAG));
143	143	m_slot4 = dynamic_cast<cococart_slot_device *>(subdevice(SLOT4_TAG));
144	144	m_owner = dynamic_cast<cococart_slot_device *>(owner());
145
146		m_active = m_slot4;
	145
	146	m_active = m_slot4;
147	147	}
148	148
149	149	//-------------------------------------------------

src/mess/machine/coco_multi.h
r12348	r12349
20	20	public:
21	21	// construction/destruction
22	22	coco_multipak_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
23
	23
24	24	// optional information overrides
25	25	virtual machine_config_constructor device_mconfig_additions() const;
26
	26
27	27	virtual UINT8* get_cart_base();
28	28	protected:
29	29	// device-level overrides
r12348	r12349
33	33
34	34	// internal state
35	35	cococart_slot_device *m_owner;
36
	36
37	37	cococart_slot_device *m_slot1;
38	38	cococart_slot_device *m_slot2;
39	39	cococart_slot_device *m_slot3;
40	40	cococart_slot_device *m_slot4;
41
	41
42	42	cococart_slot_device *m_active;
43	43	};
44	44

src/mess/machine/c64exp.c
r12348	r12349
124	124
125	125
126	126	//-------------------------------------------------
127		// call_load -
	127	// call_load -
128	128	//-------------------------------------------------
129	129
130		bool c64_expansion_slot_device::call_load()
131		{
	130	bool c64_expansion_slot_device::call_load()
	131	{
132	132	if (m_cart)
133	133	{
134	134	offs_t read_length = 0;
135
	135
136	136	if (software_entry() == NULL)
137	137	{
138	138	read_length = fread(m_cart->get_cart_base(), 0x4000);
139		}
	139	}
140	140	else
141	141	{
142	142	read_length = get_software_region_length("roml");
143
	143
144	144	if (read_length > 0)
145	145	{
146	146	memcpy(m_cart->get_cart_base(), get_software_region("roml"), read_length);
r12348	r12349
156	156	}
157	157	}
158	158	}
159
	159
160	160	return IMAGE_INIT_PASS;
161	161	}
162	162
163	163
164	164	//-------------------------------------------------
165		// call_softlist_load -
	165	// call_softlist_load -
166	166	//-------------------------------------------------
167	167
168	168	bool c64_expansion_slot_device::call_softlist_load(char swlist, char swname, rom_entry *start_entry)
169	169	{
170	170	load_software_part_region(this, swlist, swname, start_entry);
171
	171
172	172	return true;
173	173	}
174	174
175	175
176	176	//-------------------------------------------------
177		// get_default_card -
	177	// get_default_card -
178	178	//-------------------------------------------------
179	179
180	180	const char * c64_expansion_slot_device::get_default_card(const device_list &devlist, emu_options &options) const
r12348	r12349
184	184
185	185
186	186	//-------------------------------------------------
187		// get_cart_base -
	187	// get_cart_base -
188	188	//-------------------------------------------------
189	189
190	190	UINT8* c64_expansion_slot_device::get_cart_base()
r12348	r12349
200	200	READ8_MEMBER( c64_expansion_slot_device::roml_r )
201	201	{
202	202	UINT8 data = 0;
203
	203
204	204	if (m_cart != NULL)
205	205	{
206	206	data = m_cart->c64_cd_r(offset, 0, 1, 1, 1);
207	207	}
208
	208
209	209	return data;
210	210	}
211	211
r12348	r12349
217	217	READ8_MEMBER( c64_expansion_slot_device::romh_r )
218	218	{
219	219	UINT8 data = 0;
220
	220
221	221	if (m_cart != NULL)
222	222	{
223	223	data = m_cart->c64_cd_r(offset, 1, 0, 1, 1);
224	224	}
225
	225
226	226	return data;
227	227	}
228	228
r12348	r12349
234	234	READ8_MEMBER( c64_expansion_slot_device::io1_r )
235	235	{
236	236	UINT8 data = 0;
237
	237
238	238	if (m_cart != NULL)
239	239	{
240	240	data = m_cart->c64_cd_r(offset, 1, 1, 0, 1);
241	241	}
242
	242
243	243	return data;
244	244	}
245	245
r12348	r12349
264	264	READ8_MEMBER( c64_expansion_slot_device::io2_r )
265	265	{
266	266	UINT8 data = 0;
267
	267
268	268	if (m_cart != NULL)
269	269	{
270	270	data = m_cart->c64_cd_r(offset, 1, 1, 1, 0);
271	271	}
272
	272
273	273	return data;
274	274	}
275	275
r12348	r12349
294	294	READ_LINE_MEMBER( c64_expansion_slot_device::game_r )
295	295	{
296	296	int state = 1;
297
	297
298	298	if (m_cart != NULL)
299	299	{
300	300	state = m_cart->c64_game_r();
301	301	}
302
	302
303	303	return state;
304	304	}
305	305
r12348	r12349
311	311	READ_LINE_MEMBER( c64_expansion_slot_device::exrom_r )
312	312	{
313	313	int state = 1;
314
	314
315	315	if (m_cart != NULL)
316	316	{
317	317	state = m_cart->c64_exrom_r();
318	318	}
319
	319
320	320	return state;
321	321	}
322	322
r12348	r12349
328	328	bool c64_expansion_slot_device::screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect)
329	329	{
330	330	bool value = false;
331
	331
332	332	if (m_cart != NULL)
333	333	{
334	334	value = m_cart->c64_screen_update(screen, bitmap, cliprect);
335	335	}
336
	336
337	337	return value;
338	338	}
339	339

src/mess/machine/c64exp.h
r12348	r12349
7	7
8	8	**********************************************************************
9	9
10		GND 1 A GND
11		+5V 2 B _ROMH
12		+5V 3 C _RESET
13		_IRQ 4 D _NMI
14		_CR/W 5 E Sphi2
15		DOTCLK 6 F CA15
16		_I/O1 7 H CA14
17		_GAME 8 J CA13
18		_EXROM 9 K CA12
19		_I/O2 10 L CA11
20		_ROML 11 M CA10
21		BA 12 N CA9
22		_DMA 13 P CA8
23		CD7 14 R CA7
24		CD6 15 S CA6
25		CD5 16 T CA5
26		CD4 17 U CA4
27		CD3 18 V CA3
28		CD2 19 W CA2
29		CD1 20 X CA1
30		CD0 21 Y CA0
31		GND 22 Z GND
	10	GND 1 A GND
	11	+5V 2 B _ROMH
	12	+5V 3 C _RESET
	13	_IRQ 4 D _NMI
	14	_CR/W 5 E Sphi2
	15	DOTCLK 6 F CA15
	16	_I/O1 7 H CA14
	17	_GAME 8 J CA13
	18	_EXROM 9 K CA12
	19	_I/O2 10 L CA11
	20	_ROML 11 M CA10
	21	BA 12 N CA9
	22	_DMA 13 P CA8
	23	CD7 14 R CA7
	24	CD6 15 S CA6
	25	CD5 16 T CA5
	26	CD4 17 U CA4
	27	CD3 18 V CA3
	28	CD2 19 W CA2
	29	CD1 20 X CA1
	30	CD0 21 Y CA0
	31	GND 22 Z GND
32	32
33	33	**********************************************************************/
34	34
r12348	r12349
94	94	// memory access
95	95	virtual UINT8 c64_cd_r(offs_t offset, int roml, int romh, int io1, int io2) { return 0; };
96	96	virtual void c64_cd_w(offs_t offset, UINT8 data, int roml, int romh, int io1, int io2) { };
97
	97
98	98	// memory banking
99	99	virtual int c64_game_r() { return 1; };
100	100	virtual int c64_exrom_r() { return 1; };
r12348	r12349
104	104
105	105	// video
106	106	virtual bool c64_screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect) { return false; }
107
	107
108	108	virtual UINT8* get_cart_base() { return NULL; }
109	109	};
110	110
r12348	r12349
144	144	virtual void device_start();
145	145	virtual void device_reset();
146	146	virtual void device_config_complete();
147
	147
148	148	// image-level overrides
149	149	virtual bool call_load();
150	150	virtual bool call_softlist_load(char swlist, char swname, rom_entry *start_entry);
r12348	r12349
159	159	virtual const char *image_interface() const { return "c64_cart"; }
160	160	virtual const char *file_extensions() const { return "bin,rom,80"; }
161	161	virtual const option_guide *create_option_guide() const { return NULL; }
162
	162
163	163	// slot interface overrides
164	164	virtual const char * get_default_card(const device_list &devlist, emu_options &options) const;
165
	165
166	166	virtual UINT8* get_cart_base();
167
	167
168	168	devcb_resolved_write_line m_out_irq_func;
169	169	devcb_resolved_write_line m_out_nmi_func;
170	170	devcb_resolved_write_line m_out_dma_func;

src/mess/machine/comxexp.c
r12348	r12349
125	125	UINT8 comx_expansion_slot_device::mrd_r(offs_t offset, int *extrom)
126	126	{
127	127	UINT8 data = 0;
128
	128
129	129	if (m_card != NULL)
130	130	{
131	131	data = m_card->comx_mrd_r(offset, extrom);
132	132	}
133
	133
134	134	return data;
135	135	}
136	136
r12348	r12349
155	155	UINT8 comx_expansion_slot_device::io_r(offs_t offset)
156	156	{
157	157	UINT8 data = 0;
158
	158
159	159	if (m_card != NULL)
160	160	{
161	161	data = m_card->comx_io_r(offset);
162	162	}
163
	163
164	164	return data;
165	165	}
166	166
r12348	r12349
211	211	bool comx_expansion_slot_device::screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect)
212	212	{
213	213	bool value = false;
214
	214
215	215	if (m_card != NULL)
216	216	{
217	217	value = m_card->comx_screen_update(screen, bitmap, cliprect);
218	218	}
219
	219
220	220	return value;
221	221	}
222	222

src/mess/machine/comx_joy.c
r12348	r12349
101	101	{
102	102	data = input_port_read(this, "JOY2");
103	103	}
104
	104
105	105	return data;
106	106	}

src/mess/machine/comxexp.h
r12348	r12349
7	7
8	8	**********************************************************************
9	9
10		GND 1 A GND
11		NC 2 B DS
12		+5V 3 C V+
13		D0 4 D D1
14		D2 5 E D3
15		D4 6 F D5
16		D6 7 H D7
17		_DP 8 J Q
18		_CLEAR 9 K _MRD
19		TPA 10 L N0
20		N1 11 M N2
21		_RAS 12 N _INT
22		_WAIT 13 P CLOCK
23		SC1 14 R SC0
24		_EF4 15 S _CASE
25		TPB 16 T _A15
26		_MWR 17 U A14
27		MA7 18 V _A14
28		MA5 19 W MA6
29		MA4 20 X MA3
30		MA2 21 Y _EXTROM
31		MA1 22 Z MA0
	10	GND 1 A GND
	11	NC 2 B DS
	12	+5V 3 C V+
	13	D0 4 D D1
	14	D2 5 E D3
	15	D4 6 F D5
	16	D6 7 H D7
	17	_DP 8 J Q
	18	_CLEAR 9 K _MRD
	19	TPA 10 L N0
	20	N1 11 M N2
	21	_RAS 12 N _INT
	22	_WAIT 13 P CLOCK
	23	SC1 14 R SC0
	24	_EF4 15 S _CASE
	25	TPB 16 T _A15
	26	_MWR 17 U A14
	27	MA7 18 V _A14
	28	MA5 19 W MA6
	29	MA4 20 X MA3
	30	MA2 21 Y _EXTROM
	31	MA1 22 Z MA0
32	32
33	33	**********************************************************************/
34	34

src/mess/machine/nubus.c
r12348	r12349
1	1	/***************************************************************************
2	2
3	3	nubus.c - NuBus bus and card emulation
4
5		by R. Belmont, based heavily on Miodrag Milanovic's ISA8/16 implementation
6
	4
	5	by R. Belmont, based heavily on Miodrag Milanovic's ISA8/16 implementation
	6
7	7	***************************************************************************/
8	8
9	9	#include "emu.h"
r12348	r12349
105	105	nubus_device::nubus_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
106	106	device_t(mconfig, NUBUS, "NUBUS", tag, owner, clock)
107	107	{
108		}
	108	}
109	109
110	110	nubus_device::nubus_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock) :
111	111	device_t(mconfig, type, name, tag, owner, clock)

src/mess/machine/nubus.h
r12348	r12349
1	1	/***************************************************************************
2
	2
3	3	nubus.h - NuBus bus and card emulation
4
5		by R. Belmont, based heavily on Miodrag Milanovic's ISA8/16 implementation
6	4
	5	by R. Belmont, based heavily on Miodrag Milanovic's ISA8/16 implementation
	6
7	7	***************************************************************************/
8	8
9	9	#pragma once
r12348	r12349
31	31	#define MCFG_NUBUS_ONBOARD_ADD(_nbtag, _tag, _dev_type, _def_inp) \
32	32	MCFG_DEVICE_ADD(_tag, _dev_type, 0) \
33	33	MCFG_DEVICE_INPUT_DEFAULTS(_def_inp) \
34		device_nubus_card_interface::static_set_nubus_tag(*device, _nbtag, _tag);
35
	34	device_nubus_card_interface::static_set_nubus_tag(*device, _nbtag, _tag);
	35
36	36	#define MCFG_NUBUS_BUS_REMOVE(_tag) \
37	37	MCFG_DEVICE_REMOVE(_tag)
38	38
r12348	r12349
49	49	// construction/destruction
50	50	nubus_slot_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
51	51	nubus_slot_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
52
53		// device-level overrides
	52
	53	// device-level overrides
54	54	virtual void device_start();
55	55
56	56	// inline configuration
r12348	r12349
135	135	virtual ~device_nubus_card_interface();
136	136
137	137	device_nubus_card_interface *next() const { return m_next; }
138
	138
139	139	void set_nubus_device();
140	140
141	141	void install_declaration_rom(const char *romregion);

src/mess/machine/comx_epr.c
r12348	r12349
26	26	ROM_REGION( 0x10000, "eprom", 0 )
27	27	ROM_LOAD( "f&m.basic.bin", 0x0000, 0x2000, CRC(22ab7b61) SHA1(68b5770bca37b1ba94083f944086884e612b5a1b) )
28	28	ROM_LOAD( "disk.utilities.bin", 0x2000, 0x2000, CRC(2576c945) SHA1(e80481054c6997a5f418d8a5872ac0110ae7b75a) )
29		ROM_LOAD( "tennismania.bin", 0x4000, 0x2000, CRC(a956cc74) SHA1(8bc914f52f0dd2cf792da74ec4e9e333365619ef) )
	29	ROM_LOAD( "tennismania.bin", 0x4000, 0x2000, CRC(a956cc74) SHA1(8bc914f52f0dd2cf792da74ec4e9e333365619ef) )
30	30	ROM_END
31	31
32	32
r12348	r12349
67	67
68	68	m_rom = subregion("f800")->base();
69	69	m_eprom = subregion("eprom")->base();
70
	70
71	71	// state saving
72	72	save_item(NAME(m_select));
73	73	}
r12348	r12349
89	89	UINT8 comx_epr_device::comx_mrd_r(offs_t offset, int *extrom)
90	90	{
91	91	UINT8 data = 0;
92
	92
93	93	if (offset >= 0xc000 && offset < 0xe000)
94	94	{
95	95	offs_t address = (m_select << 13) \| (offset & 0x1fff);
r12348	r12349
99	99	{
100	100	data = m_rom[offset & 0x7ff];
101	101	}
102
	102
103	103	return data;
104	104	}
105	105

src/mess/machine/ecb_grip.c
r12348	r12349
1	1	/***************************************************************************
2	2
3		GRIP - Grafik Interface Prozessor
	3	GRIP - Grafik Interface Prozessor
4	4
5	5	***************************************************************************/
6	6
r12348	r12349
173	173	//-------------------------------------------------
174	174
175	175	static ADDRESS_MAP_START( grip5_io, AS_IO, 8, grip5_device )
176		ADDRESS_MAP_GLOBAL_MASK(0xff)
177		AM_RANGE(0x00, 0x00) AM_READWRITE(cxstb_r, cxstb_w)
178		AM_RANGE(0x10, 0x10) AM_WRITE(eprom_w)
179		AM_RANGE(0x11, 0x11) AM_WRITE(vol0_w)
	176	ADDRESS_MAP_GLOBAL_MASK(0xff)
	177	AM_RANGE(0x00, 0x00) AM_READWRITE(cxstb_r, cxstb_w)
	178	AM_RANGE(0x10, 0x10) AM_WRITE(eprom_w)
	179	AM_RANGE(0x11, 0x11) AM_WRITE(vol0_w)
180	180	// AM_RANGE(0x12, 0x12) AM_WRITE(rts_w)
181		AM_RANGE(0x13, 0x13) AM_WRITE(page_w)
	181	AM_RANGE(0x13, 0x13) AM_WRITE(page_w)
182	182	// AM_RANGE(0x14, 0x14) AM_WRITE(str_w)
183	183	// AM_RANGE(0x15, 0x15) AM_WRITE(intl_w)
184		AM_RANGE(0x16, 0x16) AM_WRITE(dpage_w)
185		AM_RANGE(0x17, 0x17) AM_WRITE(vol1_w)
186		AM_RANGE(0x20, 0x2f) AM_DEVREADWRITE_LEGACY(Z80STI_TAG, z80sti_r, z80sti_w)
187		AM_RANGE(0x30, 0x30) AM_READWRITE(lrs_r, lrs_w)
188		AM_RANGE(0x40, 0x40) AM_READ(stat_r)
189		AM_RANGE(0x50, 0x50) AM_DEVWRITE(HD6345_TAG, hd6345_device, address_w)
190		AM_RANGE(0x52, 0x52) AM_DEVWRITE(HD6345_TAG, hd6345_device, register_w)
191		AM_RANGE(0x53, 0x53) AM_DEVREAD(HD6345_TAG, hd6345_device, register_r)
192		AM_RANGE(0x60, 0x60) AM_DEVWRITE_LEGACY(CENTRONICS_TAG, centronics_data_w)
193		AM_RANGE(0x70, 0x73) AM_DEVREADWRITE(I8255A_TAG, i8255_device, read, write)
	184	AM_RANGE(0x16, 0x16) AM_WRITE(dpage_w)
	185	AM_RANGE(0x17, 0x17) AM_WRITE(vol1_w)
	186	AM_RANGE(0x20, 0x2f) AM_DEVREADWRITE_LEGACY(Z80STI_TAG, z80sti_r, z80sti_w)
	187	AM_RANGE(0x30, 0x30) AM_READWRITE(lrs_r, lrs_w)
	188	AM_RANGE(0x40, 0x40) AM_READ(stat_r)
	189	AM_RANGE(0x50, 0x50) AM_DEVWRITE(HD6345_TAG, hd6345_device, address_w)
	190	AM_RANGE(0x52, 0x52) AM_DEVWRITE(HD6345_TAG, hd6345_device, register_w)
	191	AM_RANGE(0x53, 0x53) AM_DEVREAD(HD6345_TAG, hd6345_device, register_r)
	192	AM_RANGE(0x60, 0x60) AM_DEVWRITE_LEGACY(CENTRONICS_TAG, centronics_data_w)
	193	AM_RANGE(0x70, 0x73) AM_DEVREADWRITE(I8255A_TAG, i8255_device, read, write)
194	194
195	195	// AM_RANGE(0x80, 0x80) AM_WRITE(xrflgs_w)
196	196	// AM_RANGE(0xc0, 0xc0) AM_WRITE(xrclrg_w)
r12348	r12349
241	241	static MC6845_UPDATE_ROW( grip_update_row )
242	242	{
243	243	grip_device grip = downcast<grip_device >(device->owner());
244
	244
245	245	grip->crtc_update_row(device,bitmap,cliprect,ma,ra,y,x_count,cursor_x,param);
246	246	}
247	247	/*
248	248	static MC6845_UPDATE_ROW( grip5_update_row )
249	249	{
250		grip5_state *state = device->machine().driver_data<grip5_state>();
251		int column, bit;
	250	grip5_state *state = device->machine().driver_data<grip5_state>();
	251	int column, bit;
252	252
253		for (column = 0; column < x_count; column++)
254		{
255		UINT16 address = (state->m_dpage << 12) \| (((ma + column) & 0xfff) << 3) \| (ra & 0x07);
256		UINT8 data = state->m_video_ram[address];
	253	for (column = 0; column < x_count; column++)
	254	{
	255	UINT16 address = (state->m_dpage << 12) \| (((ma + column) & 0xfff) << 3) \| (ra & 0x07);
	256	UINT8 data = state->m_video_ram[address];
257	257
258		for (bit = 0; bit < 8; bit++)
259		{
260		int x = (column * 8) + bit;
261		int color = state->m_flash ? 0 : BIT(data, bit);
	258	for (bit = 0; bit < 8; bit++)
	259	{
	260	int x = (column * 8) + bit;
	261	int color = state->m_flash ? 0 : BIT(data, bit);
262	262
263		*BITMAP_ADDR16(bitmap, y, x) = color;
264		}
265		}
	263	*BITMAP_ADDR16(bitmap, y, x) = color;
	264	}
	265	}
266	266	}
267	267
268	268	static MC6845_ON_UPDATE_ADDR_CHANGED( grip5_update_addr_changed )
r12348	r12349
294	294	/*
295	295	static const mc6845_interface grip5_crtc_intf =
296	296	{
297		SCREEN_TAG,
298		8,
299		NULL,
300		grip5_update_row,
301		NULL,
302		DEVCB_DEVICE_LINE(Z80STI_TAG, z80sti_i1_w),
303		DEVCB_DEVICE_LINE(Z80STI_TAG, z80sti_i2_w),
304		DEVCB_NULL,
305		DEVCB_NULL,
306		grip5_update_addr_changed
	297	SCREEN_TAG,
	298	8,
	299	NULL,
	300	grip5_update_row,
	301	NULL,
	302	DEVCB_DEVICE_LINE(Z80STI_TAG, z80sti_i1_w),
	303	DEVCB_DEVICE_LINE(Z80STI_TAG, z80sti_i2_w),
	304	DEVCB_NULL,
	305	DEVCB_NULL,
	306	grip5_update_addr_changed
307	307	};
308	308	*/
309	309
r12348	r12349
514	514
515	515	// devices
516	516	MCFG_MC6845_ADD(MC6845_TAG, MC6845, XTAL_16MHz/4, crtc_intf)
517		// MCFG_MC6845_ADD(HD6345_TAG, HD6345, XTAL_16MHz/4, grip5_crtc_intf)
	517	// MCFG_MC6845_ADD(HD6345_TAG, HD6345, XTAL_16MHz/4, grip5_crtc_intf)
518	518	MCFG_I8255A_ADD(I8255A_TAG, ppi_intf)
519	519	MCFG_Z80STI_ADD(Z80STI_TAG, XTAL_16MHz/4, sti_intf)
520	520	MCFG_CENTRONICS_ADD(CENTRONICS_TAG, standard_centronics)
r12348	r12349
754	754	// allocate keyboard scan timer
755	755	m_kb_timer = timer_alloc();
756	756	m_kb_timer->adjust(attotime::zero, 0, attotime::from_hz(2500));
757
	757
758	758	// register for state saving
759	759	save_item(NAME(m_vol0));
760	760	save_item(NAME(m_vol1));
r12348	r12349
769	769	/*
770	770	void grip5_state::machine_start()
771	771	{
772		grip_device::machine_start();
	772	grip_device::machine_start();
773	773
774		// setup ROM banking
775		memory_configure_bank(machine(), "eprom", 0, 2, machine().region(Z80_TAG)->base(), 0x4000);
776		memory_set_bank(this, "eprom", 0);
	774	// setup ROM banking
	775	memory_configure_bank(machine(), "eprom", 0, 2, machine().region(Z80_TAG)->base(), 0x4000);
	776	memory_set_bank(this, "eprom", 0);
777	777
778		// register for state saving
779		save_item(NAME(m_dpage));
	778	// register for state saving
	779	save_item(NAME(m_dpage));
780	780	}
781	781	*/
782	782
r12348	r12349
824	824
825	825
826	826	//-------------------------------------------------
827		// flash_w -
	827	// flash_w -
828	828	//-------------------------------------------------
829	829
830	830	WRITE8_MEMBER( grip_device::flash_w )
r12348	r12349
955	955
956	956	WRITE8_MEMBER( grip5_state::eprom_w )
957	957	{
958		memory_set_bank(machine(), "eprom", BIT(data, 0));
	958	memory_set_bank(machine(), "eprom", BIT(data, 0));
959	959	}
960	960
961	961
r12348	r12349
965	965
966	966	WRITE8_MEMBER( grip5_state::dpage_w )
967	967	{
968		m_dpage = BIT(data, 7);
	968	m_dpage = BIT(data, 7);
969	969	}
970	970	*/
971	971
r12348	r12349
977	977	UINT8 grip_device::ecbbus_io_r(offs_t offset)
978	978	{
979	979	UINT8 data = 0;
980
	980
981	981	if ((offset & 0xfe) == m_base)
982	982	{
983	983	if (BIT(offset, 0))
r12348	r12349
993	993	data = m_ppi_pc;
994	994	}
995	995	}
996
997		return data;
	996
	997	return data;
998	998	};
999	999
1000	1000

src/mess/machine/comx_eb.c
r12348	r12349
169	169	void comx_eb_device::set_int(const char *tag, int state)
170	170	{
171	171	int slot = 0;
172
	172
173	173	for (slot = 0; slot < MAX_EB_SLOTS; slot++)
174	174	{
175	175	if (!strcmp(tag, m_slot[slot]->tag())) break;
176	176	}
177	177
178	178	assert(slot < MAX_EB_SLOTS);
179
	179
180	180	m_int[slot] = state;
181	181
182	182	int irq = CLEAR_LINE;
183
	183
184	184	for (slot = 0; slot < MAX_EB_SLOTS; slot++)
185	185	{
186	186	irq \|= m_int[slot];
r12348	r12349
197	197	void comx_eb_device::set_ef4(const char *tag, int state)
198	198	{
199	199	int slot = 0;
200
	200
201	201	for (slot = 0; slot < MAX_EB_SLOTS; slot++)
202	202	{
203	203	if (!strcmp(tag, m_slot[slot]->tag())) break;
204	204	}
205	205
206	206	assert(slot < MAX_EB_SLOTS);
207
	207
208	208	m_ef4[slot] = state;
209
	209
210	210	int ef4 = CLEAR_LINE;
211
	211
212	212	for (slot = 0; slot < MAX_EB_SLOTS; slot++)
213	213	{
214	214	ef4 \|= m_ef4[slot];
r12348	r12349
248	248	m_slot[1] = dynamic_cast<comx_expansion_slot_device *>(subdevice(SLOT2_TAG));
249	249	m_slot[2] = dynamic_cast<comx_expansion_slot_device *>(subdevice(SLOT3_TAG));
250	250	m_slot[3] = dynamic_cast<comx_expansion_slot_device *>(subdevice(SLOT4_TAG));
251
	251
252	252	for (int slot = 0; slot < MAX_EB_SLOTS; slot++)
253	253	{
254	254	m_int[slot] = CLEAR_LINE;
255	255	m_ef4[slot] = CLEAR_LINE;
256	256	}
257
	257
258	258	m_rom = subregion("e000")->base();
259	259	}
260	260
r12348	r12349
291	291	UINT8 comx_eb_device::comx_mrd_r(offs_t offset, int *extrom)
292	292	{
293	293	UINT8 data = 0;
294
	294
295	295	if (offset >= 0x1000 && offset < 0x1800)
296	296	{
297	297	data = m_rom[offset & 0x7ff];
r12348	r12349
311	311	}
312	312	}
313	313	}
314
	314
315	315	return data;
316	316	}
317	317
r12348	r12349
339	339	UINT8 comx_eb_device::comx_io_r(offs_t offset)
340	340	{
341	341	UINT8 data = 0;
342
	342
343	343	for (int slot = 0; slot < MAX_EB_SLOTS; slot++)
344	344	{
345	345	if (BIT(m_select, slot) && m_slot[slot] != NULL)
r12348	r12349
361	361	if (offset == 1)
362	362	{
363	363	m_select = data >> 1;
364
	364
365	365	for (int slot = 0; slot < MAX_EB_SLOTS; slot++)
366	366	{
367	367	if (m_slot[slot] != NULL)
r12348	r12349
370	370	}
371	371	}
372	372	}
373
	373
374	374	for (int slot = 0; slot < MAX_EB_SLOTS; slot++)
375	375	{
376	376	if (BIT(m_select, slot) && m_slot[slot] != NULL)
r12348	r12349
388	388	bool comx_eb_device::comx_screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect)
389	389	{
390	390	bool value = false;
391
	391
392	392	for (int slot = 0; slot < MAX_EB_SLOTS; slot++)
393	393	{
394	394	if (BIT(m_select, slot) && m_slot[slot] != NULL)

src/mess/machine/ecb_grip.h
r12348	r12349
35	35	virtual const rom_entry *device_rom_region() const;
36	36	virtual machine_config_constructor device_mconfig_additions() const;
37	37	virtual ioport_constructor device_input_ports() const;
38
	38
39	39	// not really public
40	40	DECLARE_WRITE8_MEMBER( vol0_w );
41	41	DECLARE_WRITE8_MEMBER( vol1_w );
r12348	r12349
91	91	int m_lps; // light pen sense
92	92	int m_page; // video page
93	93	int m_flash; // flash
94
	94
95	95	// ECB bus state
96	96	UINT8 m_base; // ECB base address
97	97	UINT8 m_ppi_pa; // PPI port A data
r12348	r12349
103	103
104	104
105	105	/*
106		required_device<hd6345_device> m_crtc;
107		DECLARE_WRITE8_MEMBER( eprom_w );
108		DECLARE_WRITE8_MEMBER( dpage_w );
	106	required_device<hd6345_device> m_crtc;
	107	DECLARE_WRITE8_MEMBER( eprom_w );
	108	DECLARE_WRITE8_MEMBER( dpage_w );
109	109
110		// video state
111		int m_dpage; // displayed video page
112		*/
113
	110	// video state
	111	int m_dpage; // displayed video page
	112	*/
114	113
115	114
	115
116	116	// device type definition
117	117	extern const device_type ECB_GRIP21;
118	118

src/mess/machine/comx_eb.h
r12348	r12349
69	69	virtual UINT8 comx_io_r(offs_t offset);
70	70	virtual void comx_io_w(offs_t offset, UINT8 data);
71	71	virtual bool comx_screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect);
72
	72
73	73	// internal state
74	74	comx_expansion_slot_device *m_owner_slot;
75	75
76	76	UINT8 *m_rom; // program ROM
77
	77
78	78	comx_expansion_slot_device *m_slot[MAX_EB_SLOTS];
79	79	int m_int[MAX_EB_SLOTS];
80	80	int m_ef4[MAX_EB_SLOTS];
81
	81
82	82	UINT8 m_select;
83	83	};
84	84

src/mess/machine/cococart.c
r12348	r12349
58	58	}
59	59
60	60	m_cart_line.timer_index = 0;
61		m_cart_line.delay = 0;
	61	m_cart_line.delay = 0;
62	62	m_cart_line.value = COCOCART_LINE_VALUE_CLEAR;
63	63	m_cart_line.q_count = 0;
64	64	m_cart_line.callback.resolve(m_cart_callback, *this);
r12348	r12349
76	76	m_halt_line.value = COCOCART_LINE_VALUE_CLEAR;
77	77	m_halt_line.q_count = 0;
78	78	m_halt_line.callback.resolve(m_halt_callback, *this);
79
	79
80	80	m_cart = dynamic_cast<device_cococart_interface *>(get_card_device());
81	81	}
82	82
r12348	r12349
102	102	memset(&m_nmi_callback, 0, sizeof(m_nmi_callback));
103	103	memset(&m_halt_callback, 0, sizeof(m_halt_callback));
104	104	}
105
	105
106	106	// set brief and instance name
107	107	update_names();
108	108	}
r12348	r12349
307	307	}
308	308
309	309
310		bool cococart_slot_device::call_load()
311		{
	310	bool cococart_slot_device::call_load()
	311	{
312	312	if (m_cart) {
313	313	offs_t read_length = 0;
314	314	if (software_entry() == NULL)
315	315	{
316	316	read_length = fread(m_cart->get_cart_base(), 0x8000);
317		}
	317	}
318	318	else
319	319	{
320	320	read_length = get_software_region_length("rom");
321	321	memcpy(m_cart->get_cart_base(), get_software_region("rom"), read_length);
322		}
	322	}
323	323	while(read_length < 0x8000)
324	324	{
325	325	offs_t len = MIN(read_length, 0x8000 - read_length);

src/mess/includes/pc1512.h
r12348	r12349
102	102	void update_fdc_tc();
103	103	void update_ack();
104	104	void set_fdc_dsr(UINT8 data);
105
106		// DECLARE_READ8_MEMBER( videoram_r );
107		// DECLARE_WRITE8_MEMBER( videoram_w );
	105
	106	// DECLARE_READ8_MEMBER( videoram_r );
	107	// DECLARE_WRITE8_MEMBER( videoram_w );
108	108	DECLARE_READ8_MEMBER( system_r );
109	109	DECLARE_WRITE8_MEMBER( system_w );
110	110	DECLARE_READ8_MEMBER( mouse_r );
r12348	r12349
115	115	DECLARE_WRITE8_MEMBER( printer_w );
116	116	DECLARE_READ8_MEMBER( fdc_r );
117	117	DECLARE_WRITE8_MEMBER( fdc_w );
118		// DECLARE_READ8_MEMBER( vdu_r );
119		// DECLARE_WRITE8_MEMBER( vdu_w );
	118	// DECLARE_READ8_MEMBER( vdu_r );
	119	// DECLARE_WRITE8_MEMBER( vdu_w );
120	120	DECLARE_WRITE_LINE_MEMBER( kbdata_w );
121	121	DECLARE_WRITE_LINE_MEMBER( kbclk_w );
122	122	DECLARE_WRITE_LINE_MEMBER( pit1_w );
r12348	r12349
135	135	DECLARE_WRITE_LINE_MEMBER( dack1_w );
136	136	DECLARE_WRITE_LINE_MEMBER( dack2_w );
137	137	DECLARE_WRITE_LINE_MEMBER( dack3_w );
138
	138
139	139	// system status register
140	140	int m_pit1;
141	141	int m_pit2;
142	142	UINT8 m_status1;
143	143	UINT8 m_status2;
144	144	UINT8 m_port61;
145
	145
146	146	// interrupt state
147	147	int m_nmi_enable;
148	148
r12348	r12349
151	151	int m_kb_bits;
152	152	int m_kbclk;
153	153	int m_kbdata;
154
	154
155	155	// mouse state
156	156	UINT8 m_mouse_x;
157	157	UINT8 m_mouse_y;
r12348	r12349
160	160	UINT8 m_dma_page[4];
161	161	int m_dma_channel;
162	162	int m_dreq0;
163
	163
164	164	// floppy state
165	165	int m_nden;
166	166	int m_dint;
167	167	int m_ddrq;
168	168	UINT8 m_fdc_dsr;
169	169	int m_neop;
170
	170
171	171	// printer state
172	172	int m_ack_int_enable;
173	173	int m_ack;
174	174	UINT8 m_printer_data;
175	175	UINT8 m_printer_control;
176
	176
177	177	// video state
178	178	UINT8 *m_video_ram;
179	179	UINT8 *m_char_rom;
180	180	int m_toggle;
181
	181
182	182	// sound state
183	183	int m_speaker_drive;
184	184	};

src/mess/includes/at.h
r12348	r12349
26	26	device_t *m_pit8254;
27	27	device_t *m_speaker;
28	28	isa16_device *m_isabus;
29
	29
30	30	int m_poll_delay;
31	31	UINT8 m_at_spkrdata;
32	32	UINT8 m_at_speaker_input;

src/mess/includes/comx35.h
r12348	r12349
66	66	virtual bool screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect);
67	67
68	68	void check_interrupt();
69
	69
70	70	DECLARE_READ8_MEMBER( mem_r );
71	71	DECLARE_WRITE8_MEMBER( mem_w );
72	72	DECLARE_READ8_MEMBER( io_r );

src/mess/video/stic.h
r12348	r12349
67	67	};
68	68
69	69	/****************************************************************************
70		* *
71		* MXR 0000[..0007] MOB X REGISTER RW *
72		* *
73		* (MSB) (LSB) *
74		* +-+-+-+-+-+-----+---+---+--+--+--+--+--+--+--+--+ *
75		* \| \| \| \| \| \|XSIZE\|VIS\|COL\|X7\|X6\|X5\|X4\|X3\|X2\|X1\|X0\| *
76		* +-+-+-+-+-+-----+---+---+--+--+--+--+--+--+--+--+ *
77		* *
78		* Xn x-position [0..255] *
79		* COL collision detection [1=enable] *
80		* VIS visibility [1=visible] *
81		* XSIZE double width [1=double] *
82		* *
	70	* *
	71	* MXR 0000[..0007] MOB X REGISTER RW *
	72	* *
	73	* (MSB) (LSB) *
	74	* +-+-+-+-+-+-----+---+---+--+--+--+--+--+--+--+--+ *
	75	* \| \| \| \| \| \|XSIZE\|VIS\|COL\|X7\|X6\|X5\|X4\|X3\|X2\|X1\|X0\| *
	76	* +-+-+-+-+-+-----+---+---+--+--+--+--+--+--+--+--+ *
	77	* *
	78	* Xn x-position [0..255] *
	79	* COL collision detection [1=enable] *
	80	* VIS visibility [1=visible] *
	81	* XSIZE double width [1=double] *
	82	* *
83	83	****************************************************************************
84		* *
85		* NOTES *
86		* *
87		* 1. If X=0, the sprite is not visible and does not register collisions. *
88		* 2. The horizontal handle is 8 pixels from the left of the sprite, *
89		* regardless of width. *
90		* *
	84	* *
	85	* NOTES *
	86	* *
	87	* 1. If X=0, the sprite is not visible and does not register collisions. *
	88	* 2. The horizontal handle is 8 pixels from the left of the sprite, *
	89	* regardless of width. *
	90	* *
91	91	****************************************************************************/
92	92	#define STIC_MXR 0x0000
93	93
r12348	r12349
97	97	#define STIC_MXR_X 0x00FF
98	98
99	99	/****************************************************************************
100		* *
101		* MYR 0008[..000F] MOB Y REGISTER RW *
102		* *
103		* (MSB) (LSB) *
104		* +-+-+-+-+-----+-----+-----+-----+----+--+--+--+--+--+--+--+ *
105		* \| \| \| \| \|YFLIP\|XFLIP\|YSIZE\|YFULL\|YRES\|Y6\|Y5\|Y4\|Y3\|Y2\|Y1\|Y0\| *
106		* +-+-+-+-+-----+-----+-----+-----+----+--+--+--+--+--+--+--+ *
107		* *
108		* Yn y-position [0..127] *
109		* YRES y-resolution [0=8 scanlines,1=16 scanlines] *
110		* YFULL double scanline height [1=double] *
111		* YSIZE quadruple scanline height [1=quadruple] *
112		* XFLIP horizontally flip image [1=flip] *
113		* YFLIP vertically flip image [1=flip] *
114		* *
	100	* *
	101	* MYR 0008[..000F] MOB Y REGISTER RW *
	102	* *
	103	* (MSB) (LSB) *
	104	* +-+-+-+-+-----+-----+-----+-----+----+--+--+--+--+--+--+--+ *
	105	* \| \| \| \| \|YFLIP\|XFLIP\|YSIZE\|YFULL\|YRES\|Y6\|Y5\|Y4\|Y3\|Y2\|Y1\|Y0\| *
	106	* +-+-+-+-+-----+-----+-----+-----+----+--+--+--+--+--+--+--+ *
	107	* *
	108	* Yn y-position [0..127] *
	109	* YRES y-resolution [0=8 scanlines,1=16 scanlines] *
	110	* YFULL double scanline height [1=double] *
	111	* YSIZE quadruple scanline height [1=quadruple] *
	112	* XFLIP horizontally flip image [1=flip] *
	113	* YFLIP vertically flip image [1=flip] *
	114	* *
115	115	****************************************************************************
116		* *
117		* NOTES *
118		* *
119		* 1. A sprite with YRES=1 will display two cards. *
120		* 2. A sprite with YFULL=0 and YSIZE=0 will have scanlines half the *
121		* height of a background card. *
122		* 3, The minimum size of a sprite is 8x8 (XSIZE=YRES=YSIZE=YFULL=0). *
123		* 4. The maximum size of a sprite is 16x128 (XSIZE=YRES=YSIZE=YFULL=1). *
124		* 5. The Y-position is measured in double height scanlines. *
125		* 6. The vertical handle is 8 double height scanlines from the top of the *
126		* sprite, regardless of height. *
127		* *
	116	* *
	117	* NOTES *
	118	* *
	119	* 1. A sprite with YRES=1 will display two cards. *
	120	* 2. A sprite with YFULL=0 and YSIZE=0 will have scanlines half the *
	121	* height of a background card. *
	122	* 3, The minimum size of a sprite is 8x8 (XSIZE=YRES=YSIZE=YFULL=0). *
	123	* 4. The maximum size of a sprite is 16x128 (XSIZE=YRES=YSIZE=YFULL=1). *
	124	* 5. The Y-position is measured in double height scanlines. *
	125	* 6. The vertical handle is 8 double height scanlines from the top of the *
	126	* sprite, regardless of height. *
	127	* *
128	128	****************************************************************************/
129	129	#define STIC_MYR 0x0008
130	130
r12348	r12349
136	136	#define STIC_MYR_Y 0x007F
137	137
138	138	/****************************************************************************
139		* *
140		* SAR 0010[..0017] MOB ATTRIBUTE REGISTER RW *
141		* *
142		* (MSB) (LSB) *
143		* +-+-+---+---+---+-+-+--+--+--+--+--+--+---+---+---+ *
144		* \| \| \|PRI\|FG3\|SEL\| \| \|C5\|C4\|C3\|C2\|C1\|C0\|FG2\|FG1\|FG0\| *
145		* +-+-+---+---+---+-+-+--+--+--+--+--+--+---+---+---+ *
146		* *
147		* FGn foreground color [0..15] *
148		* Cn card # [0..63] *
149		* SEL card memory select [0=GROM, 1=GRAM] *
150		* PRI sprite priority [1=behind set background bit] *
151		* *
	139	* *
	140	* SAR 0010[..0017] MOB ATTRIBUTE REGISTER RW *
	141	* *
	142	* (MSB) (LSB) *
	143	* +-+-+---+---+---+-+-+--+--+--+--+--+--+---+---+---+ *
	144	* \| \| \|PRI\|FG3\|SEL\| \| \|C5\|C4\|C3\|C2\|C1\|C0\|FG2\|FG1\|FG0\| *
	145	* +-+-+---+---+---+-+-+--+--+--+--+--+--+---+---+---+ *
	146	* *
	147	* FGn foreground color [0..15] *
	148	* Cn card # [0..63] *
	149	* SEL card memory select [0=GROM, 1=GRAM] *
	150	* PRI sprite priority [1=behind set background bit] *
	151	* *
152	152	****************************************************************************/
153	153	#define STIC_MAR 0x0010
154	154
r12348	r12349
159	159	#define STIC_MAR_FG20 0x0007
160	160
161	161	/****************************************************************************
162		* *
163		* SCR 0018[..001F] MOB COLLISION REGISTER RW *
164		* *
165		* (MSB) (LSB) *
166		* +-+-+-+-+-+-+----+----+----+----+----+----+----+----+----+----+ *
167		* \| \| \| \| \| \| \|BRDR\|BKGD\|SPR7\|SPR6\|SPR5\|SPR4\|SPR3\|SPR2\|SPR1\|SPR0\| *
168		* +-+-+-+-+-+-+----+----+----+----+----+----+----+----+----+----+ *
169		* *
170		* SPRn 1=collision with sprite #n *
171		* BKGD 1=collsion with set background bit *
172		* BRDR 1=collision with screen border *
173		* *
	162	* *
	163	* SCR 0018[..001F] MOB COLLISION REGISTER RW *
	164	* *
	165	* (MSB) (LSB) *
	166	* +-+-+-+-+-+-+----+----+----+----+----+----+----+----+----+----+ *
	167	* \| \| \| \| \| \| \|BRDR\|BKGD\|SPR7\|SPR6\|SPR5\|SPR4\|SPR3\|SPR2\|SPR1\|SPR0\| *
	168	* +-+-+-+-+-+-+----+----+----+----+----+----+----+----+----+----+ *
	169	* *
	170	* SPRn 1=collision with sprite #n *
	171	* BKGD 1=collsion with set background bit *
	172	* BRDR 1=collision with screen border *
	173	* *
174	174	****************************************************************************
175		* *
176		* NOTES *
177		* *
178		* 1. All collisions are latched. Successive reads read from the latch. *
179		* A write will reset the latch. *
180		* 2. Sprites with VIS=0 register collisions. *
181		* 3. Sprites with X=0 do not register collisions. *
182		* 4. Two overlapping sprites with different priorities, one completely *
183		* hidden behind the background, still register a collision. *
184		* *
	175	* *
	176	* NOTES *
	177	* *
	178	* 1. All collisions are latched. Successive reads read from the latch. *
	179	* A write will reset the latch. *
	180	* 2. Sprites with VIS=0 register collisions. *
	181	* 3. Sprites with X=0 do not register collisions. *
	182	* 4. Two overlapping sprites with different priorities, one completely *
	183	* hidden behind the background, still register a collision. *
	184	* *
185	185	****************************************************************************/
186	186	#define STIC_MCR 0x0018
187	187
r12348	r12349
197	197	#define STIC_MCR_SPR0 0x0001
198	198
199	199	/****************************************************************************
200		* *
201		* DER 0021 DISPLAY ENABLE REGISTER W *
202		* *
203		* (MSB) (LSB) *
204		* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ *
205		* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| *
206		* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ *
207		* *
	200	* *
	201	* DER 0021 DISPLAY ENABLE REGISTER W *
	202	* *
	203	* (MSB) (LSB) *
	204	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ *
	205	* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| *
	206	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ *
	207	* *
208	208	****************************************************************************
209		* *
210		* NOTES *
211		* *
212		* 1. Any write during VBLANK enables STIC output. *
213		* *
	209	* *
	210	* NOTES *
	211	* *
	212	* 1. Any write during VBLANK enables STIC output. *
	213	* *
214	214	****************************************************************************/
215	215	#define STIC_DER 0x0020
216	216
217	217	/****************************************************************************
218		* *
219		* GMR 0021 GRAPHICS MODE REGISTER RW *
220		* *
221		* (MSB) (LSB) *
222		* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ *
223		* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| *
224		* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ *
225		* *
	218	* *
	219	* GMR 0021 GRAPHICS MODE REGISTER RW *
	220	* *
	221	* (MSB) (LSB) *
	222	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ *
	223	* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| *
	224	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ *
	225	* *
226	226	****************************************************************************
227		* *
228		* NOTES *
229		* *
230		* 1. Any write during VBLANK enables FOREGROUND/BACKGROUND mode. *
231		* 2. Any read during VBLANK enables COLOR STACK/COLORED SQUARES mode. *
232		* *
	227	* *
	228	* NOTES *
	229	* *
	230	* 1. Any write during VBLANK enables FOREGROUND/BACKGROUND mode. *
	231	* 2. Any read during VBLANK enables COLOR STACK/COLORED SQUARES mode. *
	232	* *
233	233	****************************************************************************/
234	234	#define STIC_GMR 0x0021
235	235
236	236	/****************************************************************************
237		* *
238		* CSR 0028 COLOR STACK REGISTER RW *
239		* *
240		* (MSB) (LSB) *
241		* +-+-+-+-+-+-+-+-+-+-+-+-+---+---+---+---+ *
242		* \| \| \| \| \| \| \| \| \| \| \| \| \|BG3\|BG2\|BG1\|BG0\| *
243		* +-+-+-+-+-+-+-+-+-+-+-+-+---+---+---+---+ *
244		* *
245		* BGn background color [0..15] *
246		* *
	237	* *
	238	* CSR 0028 COLOR STACK REGISTER RW *
	239	* *
	240	* (MSB) (LSB) *
	241	* +-+-+-+-+-+-+-+-+-+-+-+-+---+---+---+---+ *
	242	* \| \| \| \| \| \| \| \| \| \| \| \| \|BG3\|BG2\|BG1\|BG0\| *
	243	* +-+-+-+-+-+-+-+-+-+-+-+-+---+---+---+---+ *
	244	* *
	245	* BGn background color [0..15] *
	246	* *
247	247	****************************************************************************/
248	248	#define STIC_CSR 0x0028
249	249
250	250	#define STIC_CSR_BG 0x000F
251	251
252	252	/****************************************************************************
253		* *
254		* BCR 002C BORDER COLOR REGISTER RW *
255		* *
256		* (MSB) (LSB) *
257		* +-+-+-+-+-+-+-+-+-+-+-+-+---+---+---+---+ *
258		* \| \| \| \| \| \| \| \| \| \| \| \| \|BC3\|BC2\|BC1\|BC0\| *
259		* +-+-+-+-+-+-+-+-+-+-+-+-+---+---+---+---+ *
260		* *
261		* BCn border color [0..15] *
262		* *
	253	* *
	254	* BCR 002C BORDER COLOR REGISTER RW *
	255	* *
	256	* (MSB) (LSB) *
	257	* +-+-+-+-+-+-+-+-+-+-+-+-+---+---+---+---+ *
	258	* \| \| \| \| \| \| \| \| \| \| \| \| \|BC3\|BC2\|BC1\|BC0\| *
	259	* +-+-+-+-+-+-+-+-+-+-+-+-+---+---+---+---+ *
	260	* *
	261	* BCn border color [0..15] *
	262	* *
263	263	****************************************************************************
264		* *
265		* NOTES *
266		* *
267		* 1. Affects overscan, and column and row blockouts. *
268		* *
	264	* *
	265	* NOTES *
	266	* *
	267	* 1. Affects overscan, and column and row blockouts. *
	268	* *
269	269	****************************************************************************/
270	270	#define STIC_BCR 0x002C
271	271
272	272	#define STIC_BCR_BC 0x000F
273	273
274	274	/****************************************************************************
275		* *
276		* HDR 0030 HORIZONTAL DELAY REGISTER RW *
277		* *
278		* (MSB) (LSB) *
279		* +-+-+-+-+-+-+-+-+-+-+-+-+-+----+----+----+ *
280		* \| \| \| \| \| \| \| \| \| \| \| \| \| \|DEL2\|DEL1\|DEL0\| *
281		* +-+-+-+-+-+-+-+-+-+-+-+-+-+----+----+----+ *
282		* *
283		* DELn horizontal delay [0..7] *
284		* *
	275	* *
	276	* HDR 0030 HORIZONTAL DELAY REGISTER RW *
	277	* *
	278	* (MSB) (LSB) *
	279	* +-+-+-+-+-+-+-+-+-+-+-+-+-+----+----+----+ *
	280	* \| \| \| \| \| \| \| \| \| \| \| \| \| \|DEL2\|DEL1\|DEL0\| *
	281	* +-+-+-+-+-+-+-+-+-+-+-+-+-+----+----+----+ *
	282	* *
	283	* DELn horizontal delay [0..7] *
	284	* *
285	285	****************************************************************************
286		* *
287		* NOTES *
288		* *
289		* 1. Affects both BACKTAB and MOBs. *
290		* *
	286	* *
	287	* NOTES *
	288	* *
	289	* 1. Affects both BACKTAB and MOBs. *
	290	* *
291	291	****************************************************************************/
292	292	#define STIC_HDR 0x0030
293	293
294	294	#define STIC_HDR_DEL 0x0007
295	295
296	296	/****************************************************************************
297		* *
298		* STIC_VDR 0030 VERTICAL DELAY REGISTER RW *
299		* *
300		* (MSB) (LSB) *
301		* +-+-+-+-+-+-+-+-+-+-+-+-+-+----+----+----+ *
302		* \| \| \| \| \| \| \| \| \| \| \| \| \| \|DEL2\|DEL1\|DEL0\| *
303		* +-+-+-+-+-+-+-+-+-+-+-+-+-+----+----+----+ *
304		* *
305		* DELn vertical delay [0..7] *
306		* *
	297	* *
	298	* STIC_VDR 0030 VERTICAL DELAY REGISTER RW *
	299	* *
	300	* (MSB) (LSB) *
	301	* +-+-+-+-+-+-+-+-+-+-+-+-+-+----+----+----+ *
	302	* \| \| \| \| \| \| \| \| \| \| \| \| \| \|DEL2\|DEL1\|DEL0\| *
	303	* +-+-+-+-+-+-+-+-+-+-+-+-+-+----+----+----+ *
	304	* *
	305	* DELn vertical delay [0..7] *
	306	* *
307	307	****************************************************************************
308		* *
309		* NOTES *
310		* *
311		* 1. Affects both BACKTAB and MOBs. *
312		* *
	308	* *
	309	* NOTES *
	310	* *
	311	* 1. Affects both BACKTAB and MOBs. *
	312	* *
313	313	****************************************************************************/
314	314	#define STIC_VDR 0x0031
315	315
316	316	#define STIC_VDR_DEL 0x0007
317	317
318	318	/****************************************************************************
319		* *
320		* STIC_CBR 0032 CARD BLOCKOUT REGISTER RW *
321		* *
322		* (MSB) (LSB) *
323		* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+---+---+ *
324		* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|ROW\|COL\| *
325		* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+---+---+ *
326		* *
327		* COL blockout first card column [1=blockout] *
328		* ROW blockout first card row [1=blockout] *
329		* *
	319	* *
	320	* STIC_CBR 0032 CARD BLOCKOUT REGISTER RW *
	321	* *
	322	* (MSB) (LSB) *
	323	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+---+---+ *
	324	* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|ROW\|COL\| *
	325	* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+---+---+ *
	326	* *
	327	* COL blockout first card column [1=blockout] *
	328	* ROW blockout first card row [1=blockout] *
	329	* *
330	330	****************************************************************************
331		* *
332		* NOTES *
333		* *
334		* 1. Generally used in conjunction with HDR and VDR registers, to achieve *
335		* smooth scrolling. *
336		* *
	331	* *
	332	* NOTES *
	333	* *
	334	* 1. Generally used in conjunction with HDR and VDR registers, to achieve *
	335	* smooth scrolling. *
	336	* *
337	337	****************************************************************************/
338	338	#define STIC_CBR 0x0032
339	339
r12348	r12349
348	348	#define STIC_BACKTAB_HEIGHT 12
349	349
350	350	/****************************************************************************
351		* *
352		* FOREGROUND/BACKGROUND MODE *
353		* *
354		* (MSB) (LSB) *
355		* +-+-+---+---+---+---+---+--+--+--+--+--+--+---+---+---+ *
356		* \| \| \|BG2\|BG3\|SEL\|BG1\|BG0\|C5\|C4\|C3\|C2\|C1\|C0\|FG2\|FG1\|FG0\| *
357		* +-+-+---+---+---+---+---+--+--+--+--+--+--+---+---+---+ *
358		* *
359		* FGn foreground color [0..7] *
360		* Cn card # [0..63] *
361		* SEL card memory select [0=GROM, 1=GRAM] *
362		* BGn background color [0..15] *
363		* *
	351	* *
	352	* FOREGROUND/BACKGROUND MODE *
	353	* *
	354	* (MSB) (LSB) *
	355	* +-+-+---+---+---+---+---+--+--+--+--+--+--+---+---+---+ *
	356	* \| \| \|BG2\|BG3\|SEL\|BG1\|BG0\|C5\|C4\|C3\|C2\|C1\|C0\|FG2\|FG1\|FG0\| *
	357	* +-+-+---+---+---+---+---+--+--+--+--+--+--+---+---+---+ *
	358	* *
	359	* FGn foreground color [0..7] *
	360	* Cn card # [0..63] *
	361	* SEL card memory select [0=GROM, 1=GRAM] *
	362	* BGn background color [0..15] *
	363	* *
364	364	****************************************************************************/
365	365	#define STIC_FBM_BG2 0x2000
366	366	#define STIC_FBM_BG310 0x1600
r12348	r12349
369	369	#define STIC_FBM_FG 0x0007
370	370
371	371	/****************************************************************************
372		* *
373		* COLOR STACK MODE *
374		* *
375		* (MSB) (LSB) *
376		* +-+-+---+---+---+--+--+--+--+--+--+--+--+---+---+---+ *
377		* \| \| \|ADV\|FG3\|SEL\|C7\|C6\|C5\|C4\|C3\|C2\|C1\|C0\|FG2\|FG1\|FG0\| *
378		* +-+-+---+---+---+--+--+--+--+--+--+--+--+---+---+---+ *
379		* *
380		* FGn foreground color [0..15] *
381		* Cn card # [GROM=0..212, GRAM=0..63] *
382		* SEL card memory select [0=GROM, 1=GRAM] *
383		* ADV advance color stack index [1=advance] *
384		* *
	372	* *
	373	* COLOR STACK MODE *
	374	* *
	375	* (MSB) (LSB) *
	376	* +-+-+---+---+---+--+--+--+--+--+--+--+--+---+---+---+ *
	377	* \| \| \|ADV\|FG3\|SEL\|C7\|C6\|C5\|C4\|C3\|C2\|C1\|C0\|FG2\|FG1\|FG0\| *
	378	* +-+-+---+---+---+--+--+--+--+--+--+--+--+---+---+---+ *
	379	* *
	380	* FGn foreground color [0..15] *
	381	* Cn card # [GROM=0..212, GRAM=0..63] *
	382	* SEL card memory select [0=GROM, 1=GRAM] *
	383	* ADV advance color stack index [1=advance] *
	384	* *
385	385	****************************************************************************
386		* *
387		* NOTES: *
388		* *
389		* 1. When FG3=1 and SEL=0, COLORED SQUARES MODE is enabled. *
390		* 2. When SEL=1, C7 and C6 can be used as user-defined flags. *
391		* *
	386	* *
	387	* NOTES: *
	388	* *
	389	* 1. When FG3=1 and SEL=0, COLORED SQUARES MODE is enabled. *
	390	* 2. When SEL=1, C7 and C6 can be used as user-defined flags. *
	391	* *
392	392	****************************************************************************/
393	393	#define STIC_CSTM_ADV 0x2000
394	394	#define STIC_CSTM_FG3 0x1000
r12348	r12349
401	401	#define STIC_CSTM_C (STIC_CSTM_C7\|STIC_CSTM_C6\|STIC_CSTM_C50)
402	402
403	403	/****************************************************************************
404		* *
405		* COLORED SQUARES MODE *
406		* *
407		* (MSB) (LSB) *
408		* +-+-+--+-+-+--+--+--+--+--+--+--+--+--+--+--+ *
409		* \| \| \|D2\|1\|0\|D1\|D0\|C2\|C1\|C0\|B2\|B1\|B0\|A2\|A1\|A0\| *
410		* +-+-+--+-+-+--+--+--+--+--+--+--+--+--+--+--+ *
411		* *
412		* An color a [0..7] *
413		* Bn color b [0..7] *
414		* Cn color c [0..7] *
415		* Dn color d [0..7] *
416		* *
	404	* *
	405	* COLORED SQUARES MODE *
	406	* *
	407	* (MSB) (LSB) *
	408	* +-+-+--+-+-+--+--+--+--+--+--+--+--+--+--+--+ *
	409	* \| \| \|D2\|1\|0\|D1\|D0\|C2\|C1\|C0\|B2\|B1\|B0\|A2\|A1\|A0\| *
	410	* +-+-+--+-+-+--+--+--+--+--+--+--+--+--+--+--+ *
	411	* *
	412	* An color a [0..7] *
	413	* Bn color b [0..7] *
	414	* Cn color c [0..7] *
	415	* Dn color d [0..7] *
	416	* *
417	417	****************************************************************************
418		* *
419		* NOTES: *
420		* *
421		* 1. Each color corresponds to one of the following 4 x 4 squares: *
422		* *
423		* +---+---+ *
424		* \| a \| b \| *
425		* +---+---+ *
426		* \| c \| d \| *
427		* +---+---+ *
428		* *
429		* 2. When color 7 is specified, the color is taken from the color stack. *
430		* *
	418	* *
	419	* NOTES: *
	420	* *
	421	* 1. Each color corresponds to one of the following 4 x 4 squares: *
	422	* *
	423	* +---+---+ *
	424	* \| a \| b \| *
	425	* +---+---+ *
	426	* \| c \| d \| *
	427	* +---+---+ *
	428	* *
	429	* 2. When color 7 is specified, the color is taken from the color stack. *
	430	* *
431	431	****************************************************************************/
432	432	#define STIC_CSQM_D2 0x2000
433	433	#define STIC_CSQM_D10 0x0600

src/mess/video/mac.c
r12348	r12349
141	141
142	142	for (x = 0; x < 640; x += 16)
143	143	{
144		word = video_ram[((y * 640)/16) + ((x/16)^1)];
	144	word = video_ram[((y * 640)/16) + ((x/16)^1)];
145	145	for (b = 0; b < 16; b++)
146	146	{
147	147	line[x + b] = (word >> (15 - b)) & 0x0001;

src/mess/video/isa_mda.h
r12348	r12349
24	24	// construction/destruction
25	25	isa8_mda_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
26	26	isa8_mda_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
27
	27
28	28	// optional information overrides
29	29	virtual machine_config_constructor device_mconfig_additions() const;
30	30	virtual const rom_entry *device_rom_region() const;

src/mess/video/nubus_48gc.c
r12348	r12349
23	23
24	24	ROM_START( gc48 )
25	25	ROM_REGION(0x8000, GC48_ROM_REGION, 0)
26		ROM_LOAD( "3410801.bin", 0x0000, 0x8000, CRC(e283da91) SHA1(4ae21d6d7bbaa6fc7aa301bee2b791ed33b1dcf9) )
	26	ROM_LOAD( "3410801.bin", 0x0000, 0x8000, CRC(e283da91) SHA1(4ae21d6d7bbaa6fc7aa301bee2b791ed33b1dcf9) )
27	27	ROM_END
28	28
29	29	//**************************************************************************

src/mess/video/nubus_48gc.h
r12348	r12349
21	21	// construction/destruction
22	22	nubus_48gc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
23	23	nubus_48gc_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
24
	24
25	25	// optional information overrides
26	26	virtual machine_config_constructor device_mconfig_additions() const;
27	27	virtual const rom_entry *device_rom_region() const;

src/mess/video/intv.c
r12348	r12349
780	780	UINT8 *videoram = state->m_videoram;
781	781	int x,y,offs;
782	782	int current_row;
783		// char c;
	783	// char c;
784	784
785	785	/* Draw the underlying INTV screen first */
786	786	SCREEN_UPDATE_CALL(generic_bitmapped);

src/mess/video/comx35.c
r12348	r12349
72	72	m_cr1 = m_iden ? CLEAR_LINE : ASSERT_LINE;
73	73	check_interrupt();
74	74	}
75
	75
76	76	m_prd = state;
77	77
78	78	m_maincpu->set_input_line(COSMAC_INPUT_LINE_EF1, state);

src/mess/mess.lst
r12348	r12349
635	635	dgone // 1984 Data General/One
636	636	pcmda // 1987 PC with MDA
637	637	pcherc // 1987 PC with Hercules (for testing hercules)
638		pc // 1987 PC with CGA
	638	pc // 1987 PC with CGA
639	639	pcega // 1987 PC with EGA
640	640	bw230 // 1985 Bondwell (CGA)
641	641	europc // 1988 Schneider Euro PC (CGA or Hercules)

src/mess/drivers/z100.c
r12348	r12349
1	1	/***************************************************************************
2	2
3		Zenith Z-100
	3	Zenith Z-100
4	4
5		15/07/2011 Skeleton driver.
	5	15/07/2011 Skeleton driver.
6	6
7		TODO:
8		- remove parity check IRQ patch (understand what it really wants there!)
9		- implement S-100 bus features;
10		- irqs needs 8259 "auto-ack"-ing in order to work properly;
11		- vertical scrolling isn't understood;
	7	TODO:
	8	- remove parity check IRQ patch (understand what it really wants there!)
	9	- implement S-100 bus features;
	10	- irqs needs 8259 "auto-ack"-ing in order to work properly;
	11	- vertical scrolling isn't understood;
12	12
13	13	============================================================================
14	14
15		Z207A EQU 0B0H ; Z-207 disk controller base port
	15	Z207A EQU 0B0H ; Z-207 disk controller base port
16	16	; (See DEFZ207 to program controller)
17		Z217A EQU 0AEH ; Z-217 disk controller base port
	17	Z217A EQU 0AEH ; Z-217 disk controller base port
18	18	; (See DEFZ217 to program controller)
19		ZGRNSEG EQU 0E000H ; Segment of green video plane
20		ZREDSEG EQU 0D000H ; Segment of red video plane
21		ZBLUSEG EQU 0C000H ; Segment of blue video plane
22		ZVIDEO EQU 0D8H ; Video 68A21 port
	19	ZGRNSEG EQU 0E000H ; Segment of green video plane
	20	ZREDSEG EQU 0D000H ; Segment of red video plane
	21	ZBLUSEG EQU 0C000H ; Segment of blue video plane
	22	ZVIDEO EQU 0D8H ; Video 68A21 port
23	23	; PA0 -> enable red display
24	24	; PA1 -> enable green display
25	25	; PA2 -> enable blue display
r12348	r12349
34	34	; CB1 - not used
35	35	; CB2 -> value to write (0 or 1) on clear screen
36	36	; (see DEF6821 to program the 6821)
37		ZCRTC EQU 0DCH ; Video 6845 CRT-C port
	37	ZCRTC EQU 0DCH ; Video 6845 CRT-C port
38	38	; (see DEF6845 to program the 6845)
39		ZLPEN EQU 0DEH ; Light pen latch
40		ZLPEN_BIT EQU 00000111B ; Bit hit by pen
41		ZLPEN_ROW EQU 11110000B ; Row hit by pen
42		ZPIA EQU 0E0H ; Parallel printer plus light pen and
	39	ZLPEN EQU 0DEH ; Light pen latch
	40	ZLPEN_BIT EQU 00000111B ; Bit hit by pen
	41	ZLPEN_ROW EQU 11110000B ; Row hit by pen
	42	ZPIA EQU 0E0H ; Parallel printer plus light pen and
43	43	; video vertical retrace 68A21 port
44	44	; PA0 -> PDATA1
45	45	; PA1 -> PDATA2
r12348	r12349
62	62	; CB1 <- not ACKNLG
63	63	; CB2 <- BUSY
64	64	; (See DEF6821 to program the PIA)
65		ZTIMER EQU 0E4H ; Timer 8253 port
66		ZTIMEVAL EQU 2500 ; 100ms divide by N value
	65	ZTIMER EQU 0E4H ; Timer 8253 port
	66	ZTIMEVAL EQU 2500 ; 100ms divide by N value
67	67	; (See DEF8253 to program the 8253)
68		ZTIMERS EQU 0FBH ; Timer interrupt status port
69		ZTIMERS0 EQU 001H ; Timer 0 interrupt
70		ZTIMERS2 EQU 002H ; Timer 2 interrupt
71		ZSERA EQU 0E8H ; First 2661-2 serial port
72		ZSERB EQU 0ECH ; Second 2661-2 serial port
	68	ZTIMERS EQU 0FBH ; Timer interrupt status port
	69	ZTIMERS0 EQU 001H ; Timer 0 interrupt
	70	ZTIMERS2 EQU 002H ; Timer 2 interrupt
	71	ZSERA EQU 0E8H ; First 2661-2 serial port
	72	ZSERB EQU 0ECH ; Second 2661-2 serial port
73	73	; (See DEFEP2 to program 2661-2)
74		ZM8259A EQU 0F2H ; Master 8259A interrupt controller port
75		ZINTEI EQU 0 ; Parity error or S-100 pin 98 interrupt
76		ZINTPS EQU 1 ; Processor swap interrupt
77		ZINTTIM EQU 2 ; Timer interrupt
78		ZINTSLV EQU 3 ; Slave 8259A interrupt
79		ZINTSA EQU 4 ; Serial port A interrupt
80		ZINTSB EQU 5 ; Serial port B interrupt
81		ZINTKD EQU 6 ; Keyboard, Display, or Light pen interrupt
82		ZINTPP EQU 7 ; Parallel port interrupt
	74	ZM8259A EQU 0F2H ; Master 8259A interrupt controller port
	75	ZINTEI EQU 0 ; Parity error or S-100 pin 98 interrupt
	76	ZINTPS EQU 1 ; Processor swap interrupt
	77	ZINTTIM EQU 2 ; Timer interrupt
	78	ZINTSLV EQU 3 ; Slave 8259A interrupt
	79	ZINTSA EQU 4 ; Serial port A interrupt
	80	ZINTSB EQU 5 ; Serial port B interrupt
	81	ZINTKD EQU 6 ; Keyboard, Display, or Light pen interrupt
	82	ZINTPP EQU 7 ; Parallel port interrupt
83	83	; (See DEF8259A to program the 8259A)
84		ZM8259AI EQU 64 ; Base interrupt number for master
85		ZS8259A EQU 0F0H ; Secondary 8259A interrupt controller port
86		ZS8259AI EQU 72 ; Base interrupt number for slave
87		BIOSAI EQU ZS8259AI+8 ; Base of BIOS generated interrupts
88		ZKEYBRD EQU 0F4H ; Keyboard port
89		ZKEYBRDD EQU ZKEYBRD+0 ; Keyboard data port
90		ZKEYBRDC EQU ZKEYBRD+1 ; Keyboard command port
91		ZKEYRES EQU 0 ; Reset command
92		ZKEYARD EQU 1 ; Autorepeat on command
93		ZKEYARF EQU 2 ; Autorepeat off command
94		ZKEYKCO EQU 3 ; Key click on command
95		ZKEYKCF EQU 4 ; Key click off command
96		ZKEYCF EQU 5 ; Clear keyboard FIFO command
97		ZKEYCLK EQU 6 ; Generate a click sound command
98		ZKEYBEP EQU 7 ; Generate a beep sound command
99		ZKEYEK EQU 8 ; Enable keyboard command
100		ZKEYDK EQU 9 ; Disable keyboard command
101		ZKEYUDM EQU 10 ; Enter UP/DOWN mode command
102		ZKEYNSM EQU 11 ; Enter normal scan mode command
103		ZKEYEI EQU 12 ; Enable keyboard interrupts command
104		ZKEYDI EQU 13 ; Disable keyboard interrupts command
105		ZKEYBRDS EQU ZKEYBRD+1 ; Keyboard status port
106		ZKEYOBF EQU 001H ; Output buffer not empty
107		ZKEYIBF EQU 002H ; Input buffer full
108		ZMCL EQU 0FCH ; Memory control latch
109		ZMCLMS EQU 00000011B ; Map select mask
110		ZSM0 EQU 0 ; Map select 0
111		ZSM1 EQU 1 ; Map select 1
112		ZSM2 EQU 2 ; Map select 2
113		ZSM3 EQU 3 ; Map select 3
114		ZMCLRM EQU 00001100B ; Monitor ROM mapping mask
115		ZRM0 EQU 0*4 ; Power up mode - ROM everywhere on reads
116		ZRM1 EQU 1*4 ; ROM at top of every 64K page
117		ZRM2 EQU 2*4 ; ROM at top of 8088's addr space
118		ZRM3 EQU 3*4 ; Disable ROM
119		ZMCLPZ EQU 00010000B ; 0=Set Parity to the zero state
120		ZMCLPK EQU 00100000B ; 0=Disable parity checking circuity
121		ZMCLPF EQU 01000000B ; 0=Disable parity error flag
122		Z205BA EQU 098H ; Base address for Z-205 boards
123		Z205BMC EQU 8 ; Maximum of 8 Z-205 boards installed
124		ZHAL EQU 0FDH ; Hi-address latch
125		ZHAL85 EQU 0FFH ; 8085 Mask
126		ZHAL88 EQU 0F0H ; 8088 Mask
127		ZPSP EQU 0FEH ; Processor swap port
128		ZPSPPS EQU 10000000B ; Processor select (0=8085, 1=8088)
129		ZPSPPS5 EQU 00000000B ; Select 8085
130		ZPSPPS8 EQU 10000000B ; Select 8088
131		ZPSPSI EQU 00000010B ; Generate interrupt on swapping
132		ZPSPI8 EQU 00000001B ; 8088 processes all interrupts
133		ZDIPSW EQU 0FFH ; Configuration dip switches
134		ZDIPSWBOOT EQU 00000111B ; Boot device field
135		ZDIPSWAB EQU 00001000B ; 1=Auto boot(0=Manual boot)
136		ZDIPSWRES EQU 01110000B ; Reserved
137		ZDIPSWHZ EQU 10000000B ; 1=50Hz(0=60HZ)
	84	ZM8259AI EQU 64 ; Base interrupt number for master
	85	ZS8259A EQU 0F0H ; Secondary 8259A interrupt controller port
	86	ZS8259AI EQU 72 ; Base interrupt number for slave
	87	BIOSAI EQU ZS8259AI+8 ; Base of BIOS generated interrupts
	88	ZKEYBRD EQU 0F4H ; Keyboard port
	89	ZKEYBRDD EQU ZKEYBRD+0 ; Keyboard data port
	90	ZKEYBRDC EQU ZKEYBRD+1 ; Keyboard command port
	91	ZKEYRES EQU 0 ; Reset command
	92	ZKEYARD EQU 1 ; Autorepeat on command
	93	ZKEYARF EQU 2 ; Autorepeat off command
	94	ZKEYKCO EQU 3 ; Key click on command
	95	ZKEYKCF EQU 4 ; Key click off command
	96	ZKEYCF EQU 5 ; Clear keyboard FIFO command
	97	ZKEYCLK EQU 6 ; Generate a click sound command
	98	ZKEYBEP EQU 7 ; Generate a beep sound command
	99	ZKEYEK EQU 8 ; Enable keyboard command
	100	ZKEYDK EQU 9 ; Disable keyboard command
	101	ZKEYUDM EQU 10 ; Enter UP/DOWN mode command
	102	ZKEYNSM EQU 11 ; Enter normal scan mode command
	103	ZKEYEI EQU 12 ; Enable keyboard interrupts command
	104	ZKEYDI EQU 13 ; Disable keyboard interrupts command
	105	ZKEYBRDS EQU ZKEYBRD+1 ; Keyboard status port
	106	ZKEYOBF EQU 001H ; Output buffer not empty
	107	ZKEYIBF EQU 002H ; Input buffer full
	108	ZMCL EQU 0FCH ; Memory control latch
	109	ZMCLMS EQU 00000011B ; Map select mask
	110	ZSM0 EQU 0 ; Map select 0
	111	ZSM1 EQU 1 ; Map select 1
	112	ZSM2 EQU 2 ; Map select 2
	113	ZSM3 EQU 3 ; Map select 3
	114	ZMCLRM EQU 00001100B ; Monitor ROM mapping mask
	115	ZRM0 EQU 0*4 ; Power up mode - ROM everywhere on reads
	116	ZRM1 EQU 1*4 ; ROM at top of every 64K page
	117	ZRM2 EQU 2*4 ; ROM at top of 8088's addr space
	118	ZRM3 EQU 3*4 ; Disable ROM
	119	ZMCLPZ EQU 00010000B ; 0=Set Parity to the zero state
	120	ZMCLPK EQU 00100000B ; 0=Disable parity checking circuity
	121	ZMCLPF EQU 01000000B ; 0=Disable parity error flag
	122	Z205BA EQU 098H ; Base address for Z-205 boards
	123	Z205BMC EQU 8 ; Maximum of 8 Z-205 boards installed
	124	ZHAL EQU 0FDH ; Hi-address latch
	125	ZHAL85 EQU 0FFH ; 8085 Mask
	126	ZHAL88 EQU 0F0H ; 8088 Mask
	127	ZPSP EQU 0FEH ; Processor swap port
	128	ZPSPPS EQU 10000000B ; Processor select (0=8085, 1=8088)
	129	ZPSPPS5 EQU 00000000B ; Select 8085
	130	ZPSPPS8 EQU 10000000B ; Select 8088
	131	ZPSPSI EQU 00000010B ; Generate interrupt on swapping
	132	ZPSPI8 EQU 00000001B ; 8088 processes all interrupts
	133	ZDIPSW EQU 0FFH ; Configuration dip switches
	134	ZDIPSWBOOT EQU 00000111B ; Boot device field
	135	ZDIPSWAB EQU 00001000B ; 1=Auto boot(0=Manual boot)
	136	ZDIPSWRES EQU 01110000B ; Reserved
	137	ZDIPSWHZ EQU 10000000B ; 1=50Hz(0=60HZ)
138	138
139	139	****************************************************************************/
140	140
r12348	r12349
263	263	static ADDRESS_MAP_START(z100_mem, AS_PROGRAM, 8)
264	264	ADDRESS_MAP_UNMAP_HIGH
265	265	AM_RANGE(0x00000,0x3ffff) AM_RAM // 128*2 KB RAM
266		// AM_RANGE(0xb0000,0xbffff) AM_ROM // expansion ROM
	266	// AM_RANGE(0xb0000,0xbffff) AM_ROM // expansion ROM
267	267	AM_RANGE(0xc0000,0xeffff) AM_READWRITE(z100_vram_r,z100_vram_w) // Blue / Red / Green
268		// AM_RANGE(0xf0000,0xf0fff) // network card (NET-100)
269		// AM_RANGE(0xf4000,0xf7fff) // MTRET-100 Firmware I expansion ROM
270		// AM_RANGE(0xf8000,0xfbfff) // MTRET-100 Firmware II expansion ROM check ID 0x4550
	268	// AM_RANGE(0xf0000,0xf0fff) // network card (NET-100)
	269	// AM_RANGE(0xf4000,0xf7fff) // MTRET-100 Firmware I expansion ROM
	270	// AM_RANGE(0xf8000,0xfbfff) // MTRET-100 Firmware II expansion ROM check ID 0x4550
271	271	AM_RANGE(0xfc000,0xfffff) AM_ROM AM_REGION("ipl", 0)
272	272	ADDRESS_MAP_END
273	273
r12348	r12349
344	344	{
345	345	z100_state *state = space->machine().driver_data<z100_state>();
346	346	device_t* dev = space->machine().device("z207_fdc");
347		// UINT8 res;
	347	// UINT8 res;
348	348
349		// res = 0;
	349	// res = 0;
350	350
351	351	switch(offset)
352	352	{
r12348	r12349
368	368
369	369	static ADDRESS_MAP_START( z100_io , AS_IO, 8)
370	370	ADDRESS_MAP_UNMAP_HIGH
371		// AM_RANGE (0x00, 0x3f) reserved for non-ZDS vendors
372		// AM_RANGE (0x40, 0x5f) secondary Multiport card (Z-204)
373		// AM_RANGE (0x60, 0x7f) primary Multiport card (Z-204)
374		// AM_RANGE (0x80, 0x83) development board
375		// AM_RANGE (0x98, 0x9f) Z-205 expansion memory boards
376		// AM_RANGE (0xa0, 0xa3) network card (NET-100)
377		// AM_RANGE (0xa4, 0xa7) gateway (reserved)
378		// AM_RANGE (0xac, 0xad) Z-217 secondary disk controller (winchester)
379		// AM_RANGE (0xae, 0xaf) Z-217 primary disk controller (winchester)
	371	// AM_RANGE (0x00, 0x3f) reserved for non-ZDS vendors
	372	// AM_RANGE (0x40, 0x5f) secondary Multiport card (Z-204)
	373	// AM_RANGE (0x60, 0x7f) primary Multiport card (Z-204)
	374	// AM_RANGE (0x80, 0x83) development board
	375	// AM_RANGE (0x98, 0x9f) Z-205 expansion memory boards
	376	// AM_RANGE (0xa0, 0xa3) network card (NET-100)
	377	// AM_RANGE (0xa4, 0xa7) gateway (reserved)
	378	// AM_RANGE (0xac, 0xad) Z-217 secondary disk controller (winchester)
	379	// AM_RANGE (0xae, 0xaf) Z-217 primary disk controller (winchester)
380	380	AM_RANGE (0xb0, 0xb7) AM_READWRITE(z207_fdc_r,z207_fdc_w) // primary (wd1797)
381	381	// z-207 secondary disk controller (wd1797)
382		// AM_RANGE (0xcd, 0xce) ET-100 CRT Controller
383		// AM_RANGE (0xd4, 0xd7) ET-100 Trainer Parallel I/O
	382	// AM_RANGE (0xcd, 0xce) ET-100 CRT Controller
	383	// AM_RANGE (0xd4, 0xd7) ET-100 Trainer Parallel I/O
384	384	AM_RANGE (0xd8, 0xdb) AM_DEVREADWRITE_MODERN("pia0", pia6821_device, read, write) //video board
385	385	AM_RANGE (0xdc, 0xdc) AM_WRITE(z100_6845_address_w)
386	386	AM_RANGE (0xdd, 0xdd) AM_WRITE(z100_6845_data_w)
387		// AM_RANGE (0xde, 0xde) light pen
	387	// AM_RANGE (0xde, 0xde) light pen
388	388	AM_RANGE (0xe0, 0xe3) AM_DEVREADWRITE_MODERN("pia1", pia6821_device, read, write) //main board
389		// AM_RANGE (0xe4, 0xe7) 8253 PIT
390		// AM_RANGE (0xe8, 0xeb) First 2661-2 serial port (printer)
391		// AM_RANGE (0xec, 0xef) Second 2661-2 serial port (modem)
	389	// AM_RANGE (0xe4, 0xe7) 8253 PIT
	390	// AM_RANGE (0xe8, 0xeb) First 2661-2 serial port (printer)
	391	// AM_RANGE (0xec, 0xef) Second 2661-2 serial port (modem)
392	392	AM_RANGE (0xf0, 0xf1) AM_DEVREADWRITE("pic8259_slave", pic8259_r, pic8259_w)
393	393	AM_RANGE (0xf2, 0xf3) AM_DEVREADWRITE("pic8259_master", pic8259_r, pic8259_w)
394	394	AM_RANGE (0xf4, 0xf4) AM_READ(keyb_data_r) // -> 8041 MCU
395	395	AM_RANGE (0xf5, 0xf5) AM_READWRITE(keyb_status_r,keyb_command_w)
396		// AM_RANGE (0xf6, 0xf6) expansion ROM is present (bit 0, active low)
397		// AM_RANGE (0xfb, 0xfb) timer irq status
398		// AM_RANGE (0xfc, 0xfc) memory latch
399		// AM_RANGE (0xfd, 0xfd) Hi-address latch
400		// AM_RANGE (0xfe, 0xfe) Processor swap port
	396	// AM_RANGE (0xf6, 0xf6) expansion ROM is present (bit 0, active low)
	397	// AM_RANGE (0xfb, 0xfb) timer irq status
	398	// AM_RANGE (0xfc, 0xfc) memory latch
	399	// AM_RANGE (0xfd, 0xfd) Hi-address latch
	400	// AM_RANGE (0xfe, 0xfe) Processor swap port
401	401	AM_RANGE (0xff, 0xff) AM_READ_PORT("DSW101")
402	402	ADDRESS_MAP_END
403	403
r12348	r12349
628	628	{
629	629	z100_state *state = device->machine().driver_data<z100_state>();
630	630
631		/*
632		all bits are active low
633		x--- ---- -> disable video RAM
634		-x-- ---- -> not write multiple blue
	631	/*
	632	all bits are active low
	633	x--- ---- -> disable video RAM
	634	-x-- ---- -> not write multiple blue
635	635	--x- ---- -> not write multiple green
636	636	---x ---- -> not write multiple red
637	637	---- x--- -> not flash screen
638	638	---- -x-- -> enable blue display
639		---- --x- -> enable green display
640		---- ---x -> enable red display
	639	---- --x- -> enable green display
	640	---- ---x -> enable red display
641	641	*/
642	642
643	643	state->m_vram_enable = ((data & 0x80) >> 7) ^ 1;
r12348	r12349
820	820	/* Driver */
821	821
822	822	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
823		COMP( 1982, z100, 0, 0, z100, z100, z100, "Zenith", "Z-100", GAME_NOT_WORKING \| GAME_NO_SOUND)
	823	COMP( 1982, z100, 0, 0, z100, z100, z100, "Zenith", "Z-100", GAME_NOT_WORKING \| GAME_NO_SOUND)
824	824

src/mess/drivers/pc1512.c
r12348	r12349
1	1	/*
2	2
3		Amstrad PC1512
	3	Amstrad PC1512
4	4
5		TODO:
	5	TODO:
6	6
7		- rewrite VDU
8
9		http://git.redump.net/cgit.cgi/mess/commit/?id=94fd742c9f51970583806ed37c6b3d9815f73e1a
10		http://www.retroisle.com/amstrad/pcs/OriginalDocs/techmanual.php#1.11.2.2
11		http://www.reenigne.org/blog/crtc-emulation-for-mess/
12		http://www.seasip.info/AmstradXT/pc1512kbd.html
13
	7	- rewrite VDU
	8
	9	http://git.redump.net/cgit.cgi/mess/commit/?id=94fd742c9f51970583806ed37c6b3d9815f73e1a
	10	http://www.retroisle.com/amstrad/pcs/OriginalDocs/techmanual.php#1.11.2.2
	11	http://www.reenigne.org/blog/crtc-emulation-for-mess/
	12	http://www.seasip.info/AmstradXT/pc1512kbd.html
	13
14	14	*/
15	15
16	16	#include "includes/pc1512.h"
r12348	r12349
28	28	READ8_MEMBER( pc1512_state::system_r )
29	29	{
30	30	UINT8 data = 0;
31
	31
32	32	switch (offset)
33	33	{
34	34	case 0:
r12348	r12349
36	36	{
37	37	/*
38	38
39		bit description
	39	bit description
40	40
41		0 1
42		1 8087 NDP installed
43		2 1
44		3 1
45		4 DDM0
46		5 DDM1
47		6 second floppy disk drive installed
48		7 0
	41	0 1
	42	1 8087 NDP installed
	43	2 1
	44	3 1
	45	4 DDM0
	46	5 DDM1
	47	6 second floppy disk drive installed
	48	7 0
49	49
50		*/
51
	50	*/
	51
52	52	data = m_status1;
53	53	}
54	54	else
r12348	r12349
58	58	pic8259_ir1_w(m_pic, CLEAR_LINE);
59	59	}
60	60	break;
61
	61
62	62	case 1:
63	63	data = m_port61;
64	64	break;
65
	65
66	66	case 2:
67	67	/*
68	68
69		bit description
	69	bit description
70	70
71		0 RAM0 / RAM4
72		1 RAM1
73		2 RAM2
74		3 RAM3
75		4 undefined
76		5 8253 PIT OUT2 output
77		6 external parity error (I/OCHCK from expansion bus)
78		7 on-board system RAM parity error
	71	0 RAM0 / RAM4
	72	1 RAM1
	73	2 RAM2
	74	3 RAM3
	75	4 undefined
	76	5 8253 PIT OUT2 output
	77	6 external parity error (I/OCHCK from expansion bus)
	78	7 on-board system RAM parity error
79	79
80		*/
81
	80	*/
	81
82	82	if (BIT(m_port61, 2))
83	83	data = m_status2 & 0x0f;
84	84	else
85	85	data = m_status2 >> 4;
86
	86
87	87	data \|= m_pit2 << 5;
88	88	break;
89	89	}
90
	90
91	91	return data;
92	92	}
93	93
r12348	r12349
103	103	case 1:
104	104	/*
105	105
106		bit description
	106	bit description
107	107
108		0 8253 GATE 2 (speaker modulate)
109		1 speaker drive
110		2 enable port C LSB / disable MSB
111		3 undefined
112		4 disable parity checking of on-board RAM
113		5 prevent external parity errors from causing NMI
114		6 enable incoming Keyboard Clock
115		7 enable Status-1/Disable Keyboard Code on Port A
	108	0 8253 GATE 2 (speaker modulate)
	109	1 speaker drive
	110	2 enable port C LSB / disable MSB
	111	3 undefined
	112	4 disable parity checking of on-board RAM
	113	5 prevent external parity errors from causing NMI
	114	6 enable incoming Keyboard Clock
	115	7 enable Status-1/Disable Keyboard Code on Port A
116	116
117		*/
118
	117	*/
	118
119	119	m_port61 = data;
120
	120
121	121	pit8253_gate2_w(m_pit, BIT(data, 0));
122	122
123	123	m_speaker_drive = BIT(data, 1);
r12348	r12349
125	125
126	126	m_kb->data_w(BIT(data, 6));
127	127	break;
128
	128
129	129	case 4:
130	130	/*
131	131
132		bit description
	132	bit description
133	133
134		0
135		1 PA1 - 8087 NDP installed
136		2
137		3
138		4 PA4 - DDM0
139		5 PA5 - DDM1
140		6 PA6 - Second Floppy disk drive installed
141		7
	134	0
	135	1 PA1 - 8087 NDP installed
	136	2
	137	3
	138	4 PA4 - DDM0
	139	5 PA5 - DDM1
	140	6 PA6 - Second Floppy disk drive installed
	141	7
142	142
143		*/
	143	*/
144	144
145	145	if (BIT(data, 7))
146	146	m_status1 = data ^ 0x8d;
147	147	else
148	148	m_status1 = data;
149	149	break;
150
	150
151	151	case 5:
152	152	/*
153	153
154		bit description
	154	bit description
155	155
156		0 PC0 (LSB) - RAM0
157		1 PC1 (LSB) - RAM1
158		2 PC2 (LSB) - RAM2
159		3 PC3 (LSB) - RAM3
160		4 PC0 (MSB) - RAM4
161		5 PC1 (MSB) - Undefined
162		6 PC2 (MSB) - Undefined
163		7 PC3 (MSB) - Undefined
	156	0 PC0 (LSB) - RAM0
	157	1 PC1 (LSB) - RAM1
	158	2 PC2 (LSB) - RAM2
	159	3 PC3 (LSB) - RAM3
	160	4 PC0 (MSB) - RAM4
	161	5 PC1 (MSB) - Undefined
	162	6 PC2 (MSB) - Undefined
	163	7 PC3 (MSB) - Undefined
164	164
165		*/
	165	*/
166	166
167	167	m_status2 = data;
168	168	break;
169
	169
170	170	case 6:
171	171	machine_reset();
172	172	break;
r12348	r12349
186	186	READ8_MEMBER( pc1512_state::mouse_r )
187	187	{
188	188	UINT8 data = 0;
189
	189
190	190	switch (offset)
191	191	{
192	192	case 0:
193	193	data = m_mouse_x;
194	194	break;
195
	195
196	196	case 2:
197	197	data = m_mouse_y;
198	198	break;
199	199	}
200
	200
201	201	return data;
202	202	}
203	203
r12348	r12349
213	213	case 0:
214	214	m_mouse_x = 0;
215	215	break;
216
	216
217	217	case 2:
218	218	m_mouse_y = 0;
219	219	break;
r12348	r12349
234	234	{
235	235	/*
236	236
237		bit description
	237	bit description
238	238
239		0 Address bit A16
240		1 Address bit A17
241		2 Address bit A18
242		3 Address bit A19
243		4
244		5
245		6
246		7
	239	0 Address bit A16
	240	1 Address bit A17
	241	2 Address bit A18
	242	3 Address bit A19
	243	4
	244	5
	245	6
	246	7
247	247
248		*/
	248	*/
249	249
250	250	switch (offset)
251	251	{
252	252	case 1:
253	253	m_dma_page[2] = data & 0x0f;
254	254	break;
255
	255
256	256	case 2:
257	257	m_dma_page[3] = data & 0x0f;
258	258	break;
r12348	r12349
291	291	READ8_MEMBER( pc1512_state::printer_r )
292	292	{
293	293	UINT8 data = 0;
294
	294
295	295	switch (offset)
296	296	{
297	297	case 0:
298	298	data = m_printer_data;
299	299	break;
300
	300
301	301	case 1:
302	302	/*
303	303
304		bit description
	304	bit description
305	305
306		0 LK1 fitted
307		1 LK2 fitted
308		2 LK3 fitted
309		3 printer error
310		4 printer selected
311		5 paper out
312		6 printer acknowledge
313		7 printer busy
	306	0 LK1 fitted
	307	1 LK2 fitted
	308	2 LK3 fitted
	309	3 printer error
	310	4 printer selected
	311	5 paper out
	312	6 printer acknowledge
	313	7 printer busy
314	314
315		*/
316
	315	*/
	316
317	317	data \|= input_port_read(machine(), "LK") & 0x07;
318
	318
319	319	data \|= centronics_fault_r(m_centronics) << 3;
320	320	data \|= centronics_vcc_r(m_centronics) << 4;
321	321	data \|= centronics_pe_r(m_centronics) << 5;
322	322	data \|= centronics_ack_r(m_centronics) << 6;
323	323	data \|= centronics_busy_r(m_centronics) << 7;
324	324	break;
325
	325
326	326	case 2:
327	327	data = m_printer_control;
328	328	break;
329	329	}
330
	330
331	331	return data;
332	332	}
333	333
r12348	r12349
344	344	m_printer_data = data;
345	345	centronics_data_w(m_centronics, 0, data);
346	346	break;
347
	347
348	348	case 2:
349	349	/*
350	350
351		bit description
	351	bit description
352	352
353		0 Data Strobe
354		1 Select Auto Feed
355		2 Reset Printer
356		3 Select Printer
357		4 Enable Int on ACK
358		5
359		6
360		7
	353	0 Data Strobe
	354	1 Select Auto Feed
	355	2 Reset Printer
	356	3 Select Printer
	357	4 Enable Int on ACK
	358	5
	359	6
	360	7
361	361
362		*/
	362	*/
363	363
364	364	m_printer_control = data;
365
	365
366	366	centronics_strobe_w(m_centronics, BIT(data, 0));
367	367	centronics_autofeed_w(m_centronics, BIT(data, 1));
368	368	centronics_init_w(m_centronics, BIT(data, 2));
369
	369
370	370	m_ack_int_enable = BIT(data, 4);
371	371	update_ack();
372	372	break;
r12348	r12349
386	386	READ8_MEMBER( pc1512_state::fdc_r )
387	387	{
388	388	UINT8 data = 0;
389
	389
390	390	switch (offset)
391	391	{
392	392	case 4:
393	393	data = upd765_status_r(m_fdc, 0);
394	394	break;
395
	395
396	396	case 5:
397	397	data = upd765_data_r(m_fdc, 0);
398	398	break;
399	399	}
400
	400
401	401	return data;
402	402	}
403	403
r12348	r12349
410	410	{
411	411	/*
412	412
413		bit description
	413	bit description
414	414
415		0 Drive Select Bit 0 (DS0)
416		1 Drive Select Bit 1 (DS1)
417		2 765A reset
418		3 Allow 765A FDC to interrupt and request DMA
419		4 Switch motor(s) on and enable drive 0 selection
420		5 Switch motor(s) on and enable drive 1 selection
421		6
422		7
	415	0 Drive Select Bit 0 (DS0)
	416	1 Drive Select Bit 1 (DS1)
	417	2 765A reset
	418	3 Allow 765A FDC to interrupt and request DMA
	419	4 Switch motor(s) on and enable drive 0 selection
	420	5 Switch motor(s) on and enable drive 1 selection
	421	6
	422	7
423	423
424		*/
425
	424	*/
	425
426	426	m_fdc_dsr = data;
427
	427
428	428	m_nden = BIT(data, 3);
429	429	update_fdc_int();
430	430	update_fdc_drq();
431	431	update_fdc_tc();
432
	432
433	433	upd765_reset_w(m_fdc, BIT(data, 2));
434	434
435	435	floppy_mon_w(m_floppy0, BIT(data, 4) ? CLEAR_LINE : ASSERT_LINE);
r12348	r12349
443	443	case 2:
444	444	set_fdc_dsr(data);
445	445	break;
446
	446
447	447	case 5:
448	448	upd765_data_w(m_fdc, 0, data);
449	449	break;
r12348	r12349
462	462
463	463	static ADDRESS_MAP_START( pc1512_mem, AS_PROGRAM, 16, pc1512_state )
464	464	AM_RANGE(0x00000, 0x9ffff) AM_RAM
465		// AM_RANGE(0xb8000, 0xbffff) AM_READWRITE(videoram_r, videoram_w)
	465	// AM_RANGE(0xb8000, 0xbffff) AM_READWRITE(videoram_r, videoram_w)
466	466	AM_RANGE(0xfc000, 0xfffff) AM_ROM AM_REGION(I8086_TAG, 0)
467	467	ADDRESS_MAP_END
468	468
r12348	r12349
482	482	AM_RANGE(0x080, 0x083) AM_WRITE8(dma_page_w, 0xffff)
483	483	AM_RANGE(0x0a0, 0x0a1) AM_WRITE8(nmi_mask_w, 0xff00)
484	484	AM_RANGE(0x378, 0x37b) AM_READWRITE8(printer_r, printer_w, 0xffff)
485		// AM_RANGE(0x3d0, 0x3df) AM_READWRITE8(vdu_r, vdu_w, 0xffff)
	485	// AM_RANGE(0x3d0, 0x3df) AM_READWRITE8(vdu_r, vdu_w, 0xffff)
486	486	AM_RANGE(0x3f0, 0x3f7) AM_READWRITE8(fdc_r, fdc_w, 0xffff)
487	487	AM_RANGE(0x3f8, 0x3ff) AM_DEVREADWRITE8_LEGACY(INS8250_TAG, ins8250_r, ins8250_w, 0xffff)
488	488	ADDRESS_MAP_END
r12348	r12349
500	500	static INPUT_CHANGED( mouse_button_1_changed )
501	501	{
502	502	pc1512_state *state = field.machine().driver_data<pc1512_state>();
503
	503
504	504	state->m_kb->m1_w(newval);
505	505	}
506	506
r12348	r12349
512	512	static INPUT_CHANGED( mouse_button_2_changed )
513	513	{
514	514	pc1512_state *state = field.machine().driver_data<pc1512_state>();
515
	515
516	516	state->m_kb->m2_w(newval);
517	517	}
518	518
r12348	r12349
524	524	static INPUT_CHANGED( mouse_x_changed )
525	525	{
526	526	pc1512_state *state = field.machine().driver_data<pc1512_state>();
527
528		if (newval > oldval)
	527
	528	if (newval > oldval)
529	529	state->m_mouse_x++;
530	530	else
531	531	state->m_mouse_x--;
r12348	r12349
539	539	static INPUT_CHANGED( mouse_y_changed )
540	540	{
541	541	pc1512_state *state = field.machine().driver_data<pc1512_state>();
542
543		if (newval > oldval)
	542
	543	if (newval > oldval)
544	544	state->m_mouse_y++;
545	545	else
546	546	state->m_mouse_y--;
r12348	r12349
578	578	PORT_DIPNAME( 0x10, 0x10, "ROM Size")
579	579	PORT_DIPSETTING( 0x10, "16 KB" )
580	580	PORT_DIPSETTING( 0x00, "32 KB" )
581		/* PORT_DIPNAME( 0x60, 0x60, "Character Set")
582		PORT_DIPSETTING( 0x60, "Default (Codepage 437)" )
583		PORT_DIPSETTING( 0x40, "Portugese (Codepage 865)" )
584		PORT_DIPSETTING( 0x20, "Norwegian (Codepage 860)" )
585		PORT_DIPSETTING( 0x00, "Greek")*/
	581	/* PORT_DIPNAME( 0x60, 0x60, "Character Set")
	582	PORT_DIPSETTING( 0x60, "Default (Codepage 437)" )
	583	PORT_DIPSETTING( 0x40, "Portugese (Codepage 865)" )
	584	PORT_DIPSETTING( 0x20, "Norwegian (Codepage 860)" )
	585	PORT_DIPSETTING( 0x00, "Greek")*/
586	586	PORT_DIPNAME( 0x80, 0x80, "Floppy Ready Line")
587	587	PORT_DIPSETTING( 0x80, "Connected" )
588	588	PORT_DIPSETTING( 0x00, "Not connected" )
r12348	r12349
612	612	m_kbd <<= 1;
613	613	m_kbd \|= m_kbdata;
614	614	m_kb_bits++;
615
	615
616	616	if (m_kb_bits == 8)
617	617	{
618	618	pic8259_ir1_w(m_pic, ASSERT_LINE);
r12348	r12349
644	644	WRITE_LINE_MEMBER( pc1512_state::hrq_w )
645	645	{
646	646	m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
647
	647
648	648	i8237_hlda_w(m_dmac, state);
649	649	}
650	650
r12348	r12349
658	658	{
659	659	address_space *program = m_maincpu->memory().space(AS_PROGRAM);
660	660	offs_t page_offset = m_dma_page[m_dma_channel] << 16;
661
	661
662	662	return program->read_byte(page_offset + offset);
663	663	}
664	664
r12348	r12349
679	679	READ8_MEMBER( pc1512_state::fdc_dack_r )
680	680	{
681	681	UINT8 data = 0;
682
	682
683	683	if (m_nden) data = upd765_dack_r(m_fdc, 0);
684
	684
685	685	return data;
686	686	}
687	687
r12348	r12349
718	718	DEVCB_DRIVER_MEMBER(pc1512_state, memw_w),
719	719	{ DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(pc1512_state, fdc_dack_r), DEVCB_NULL },
720	720	{ DEVCB_DRIVER_MEMBER(pc1512_state, dma0_w), DEVCB_NULL, DEVCB_DRIVER_MEMBER(pc1512_state, fdc_dack_w), DEVCB_NULL },
721		{ DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack0_w), DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack1_w),
	721	{ DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack0_w), DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack1_w),
722	722	DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack2_w), DEVCB_DRIVER_LINE_MEMBER(pc1512_state, dack3_w) }
723	723	};
724	724
r12348	r12349
730	730	static IRQ_CALLBACK( pc1512_irq_callback )
731	731	{
732	732	pc1512_state *state = device->machine().driver_data<pc1512_state>();
733
	733
734	734	return pic8259_acknowledge(state->m_pic);
735	735	}
736	736
r12348	r12349
758	758	m_dreq0 = 1;
759	759	i8237_dreq0_w(m_dmac, m_dreq0);
760	760	}
761
	761
762	762	m_pit1 = state;
763	763	}
764	764
r12348	r12349
944	944
945	945	// set RAM size
946	946	size_t ram_size = ram_get_size(m_ram);
947
	947
948	948	if (ram_size < 640 * 1024)
949	949	{
950	950	address_space *program = m_maincpu->memory().space(AS_PROGRAM);
951	951	program->unmap_readwrite(ram_size, 0x9ffff);
952	952	}
953
	953
954	954	// state saving
955	955	save_item(NAME(m_pit1));
956	956	save_item(NAME(m_pit2));
r12348	r12349
990	990	m_nmi_enable = 0;
991	991	m_toggle = 0;
992	992	m_kb_bits = 0;
993
	993
994	994	set_fdc_dsr(0);
995	995	}
996	996
r12348	r12349
1008	1008	MCFG_CPU_ADD(I8086_TAG, I8086, XTAL_24MHz/3)
1009	1009	MCFG_CPU_PROGRAM_MAP(pc1512_mem)
1010	1010	MCFG_CPU_IO_MAP(pc1512_io)
1011
	1011
1012	1012	// video
1013	1013	MCFG_FRAGMENT_ADD( pcvideo_pc1512 )
1014	1014
r12348	r12349
1016	1016	MCFG_SPEAKER_STANDARD_MONO("mono")
1017	1017	MCFG_SOUND_ADD(SPEAKER_TAG, SPEAKER_SOUND, 0)
1018	1018	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80)
1019
	1019
1020	1020	// devices
1021	1021	MCFG_PC1512_KEYBOARD_ADD(kb_intf)
1022	1022	MCFG_I8237_ADD(I8237A5_TAG, XTAL_24MHz/6, dmac_intf)
r12348	r12349
1027	1027	MCFG_INS8250_ADD(INS8250_TAG, uart_intf)
1028	1028	MCFG_CENTRONICS_ADD(CENTRONICS_TAG, centronics_intf)
1029	1029	MCFG_LEGACY_FLOPPY_2_DRIVES_ADD(floppy_intf)
1030
	1030
1031	1031	// ISA8 bus
1032	1032	MCFG_ISA8_BUS_ADD("isa", I8086_TAG, isabus_intf)
1033	1033	MCFG_ISA8_SLOT_ADD("isa", "isa1", pc1512_isa8_cards, NULL, NULL)
1034	1034	MCFG_ISA8_SLOT_ADD("isa", "isa2", pc1512_isa8_cards, NULL, NULL)
1035	1035	MCFG_ISA8_SLOT_ADD("isa", "isa3", pc1512_isa8_cards, NULL, NULL)
1036
	1036
1037	1037	// internal ram
1038	1038	MCFG_RAM_ADD(RAM_TAG)
1039	1039	MCFG_RAM_DEFAULT_SIZE("512K")

src/mess/drivers/coco.c
r12348	r12349
777	777
778	778	static SLOT_INTERFACE_START(dragon_cart)
779	779	SLOT_INTERFACE("dragon_fdc", DRAGON_FDC)
780		SLOT_INTERFACE("sdtandy_fdc", SDTANDY_FDC)
	780	SLOT_INTERFACE("sdtandy_fdc", SDTANDY_FDC)
781	781	SLOT_INTERFACE("pak", COCO_PAK)
782	782	SLOT_INTERFACE_END
783	783
784	784	static SLOT_INTERFACE_START(coco_cart)
785	785	SLOT_INTERFACE("fdc", COCO_FDC)
786	786	SLOT_INTERFACE("fdcv11", COCO_FDC_V11)
787		SLOT_INTERFACE("cp400_fdc", CP400_FDC)
	787	SLOT_INTERFACE("cp400_fdc", CP400_FDC)
788	788	SLOT_INTERFACE("rs232", COCO_232)
789	789	SLOT_INTERFACE("orch90", COCO_ORCH90)
790	790	SLOT_INTERFACE("banked_16k", COCO_PAK_BANKED)
r12348	r12349
831	831	MCFG_RAM_ADD(RAM_TAG)
832	832	MCFG_RAM_DEFAULT_SIZE("32K")
833	833	MCFG_RAM_EXTRA_OPTIONS("64K")
834
	834
835	835	/* Software lists */
836		MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
	836	MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
837	837	MACHINE_CONFIG_END
838	838
839	839	static MACHINE_CONFIG_START( dragon64, coco_state )
r12348	r12349
877	877	/* internal ram */
878	878	MCFG_RAM_ADD(RAM_TAG)
879	879	MCFG_RAM_DEFAULT_SIZE("64K")
880
	880
881	881	/* Software lists */
882		MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
	882	MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
883	883	MACHINE_CONFIG_END
884	884
885	885	static MACHINE_CONFIG_START( d64plus, coco_state )
r12348	r12349
924	924	/* internal ram */
925	925	MCFG_RAM_ADD(RAM_TAG)
926	926	MCFG_RAM_DEFAULT_SIZE("128K")
927
	927
928	928	/* Software lists */
929		MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
	929	MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
930	930	MACHINE_CONFIG_END
931	931
932	932	static MACHINE_CONFIG_START( dgnalpha, coco_state )
r12348	r12349
981	981	/* internal ram */
982	982	MCFG_RAM_ADD(RAM_TAG)
983	983	MCFG_RAM_DEFAULT_SIZE("64K")
984
	984
985	985	/* Software lists */
986		MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
	986	MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
987	987	MACHINE_CONFIG_END
988	988
989	989	static MACHINE_CONFIG_START( tanodr64, coco_state )
r12348	r12349
1028	1028	/* internal ram */
1029	1029	MCFG_RAM_ADD(RAM_TAG)
1030	1030	MCFG_RAM_DEFAULT_SIZE("64K")
1031
	1031
1032	1032	/* Software lists */
1033		MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
	1033	MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
1034	1034	MACHINE_CONFIG_END
1035	1035
1036	1036	static MACHINE_CONFIG_START( coco, coco_state )
r12348	r12349
1074	1074	MCFG_RAM_ADD(RAM_TAG)
1075	1075	MCFG_RAM_DEFAULT_SIZE("16K")
1076	1076	MCFG_RAM_EXTRA_OPTIONS("4K,32K,64K")
1077
	1077
1078	1078	/* Software lists */
1079		MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
	1079	MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
1080	1080	MACHINE_CONFIG_END
1081	1081
1082	1082	static MACHINE_CONFIG_START( coco2, coco_state )
r12348	r12349
1120	1120	MCFG_RAM_ADD(RAM_TAG)
1121	1121	MCFG_RAM_DEFAULT_SIZE("64K")
1122	1122	MCFG_RAM_EXTRA_OPTIONS("16K")
1123
	1123
1124	1124	/* Software lists */
1125		MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
	1125	MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
1126	1126	MACHINE_CONFIG_END
1127	1127
1128	1128	static MACHINE_CONFIG_START( coco2b, coco_state )
r12348	r12349
1166	1166	MCFG_RAM_ADD(RAM_TAG)
1167	1167	MCFG_RAM_DEFAULT_SIZE("64K")
1168	1168	MCFG_RAM_EXTRA_OPTIONS("16K")
1169
	1169
1170	1170	/* Software lists */
1171		MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
	1171	MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
1172	1172	MACHINE_CONFIG_END
1173	1173
1174	1174	static MACHINE_CONFIG_START( coco3, coco3_state )
r12348	r12349
1224	1224	MCFG_RAM_ADD(RAM_TAG)
1225	1225	MCFG_RAM_DEFAULT_SIZE("512K")
1226	1226	MCFG_RAM_EXTRA_OPTIONS("128K,2M,8M")
1227
	1227
1228	1228	/* Software lists */
1229		MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
	1229	MCFG_SOFTWARE_LIST_ADD("cart_list","coco_cart")
1230	1230	MACHINE_CONFIG_END
1231	1231
1232	1232	static MACHINE_CONFIG_DERIVED( coco3p, coco3 )
r12348	r12349
1286	1286	ROM_START(tanodr64)
1287	1287	ROM_REGION(0x10000,"maincpu",0)
1288	1288	ROM_LOAD("d64_1.rom", 0x0000, 0x4000, CRC(60a4634c) SHA1(f119506eaa3b4b70b9aa0dd83761e8cbe043d042))
1289		ROM_LOAD("d64_2.rom", 0x8000, 0x4000, CRC(17893a42) SHA1(e3c8986bb1d44269c4587b04f1ca27a70b0aaa2e))
	1289	ROM_LOAD("d64_2.rom", 0x8000, 0x4000, CRC(17893a42) SHA1(e3c8986bb1d44269c4587b04f1ca27a70b0aaa2e))
1290	1290	ROM_END
1291	1291
1292	1292	ROM_START(dgnalpha)

src/mess/drivers/imds.c
r12348	r12349
85	85
86	86	//static const ins8250_interface imds_com_interface =
87	87	//{
88		// 1843200,
89		// DEVCB_NULL,
90		// NULL,
91		// NULL,
92		// NULL
	88	// 1843200,
	89	// DEVCB_NULL,
	90	// NULL,
	91	// NULL,
	92	// NULL
93	93	//};
94	94
95	95	static MACHINE_CONFIG_START( imds, imds_state )
r12348	r12349
98	98	MCFG_CPU_PROGRAM_MAP(imds_mem)
99	99	MCFG_CPU_IO_MAP(imds_io)
100	100
101		// MCFG_INS8250_ADD( "ins8250", imds_com_interface )
	101	// MCFG_INS8250_ADD( "ins8250", imds_com_interface )
102	102
103	103	/* video hardware */
104	104	MCFG_FRAGMENT_ADD( generic_terminal )

src/mess/drivers/at.c
r12348	r12349
293	293	PORT_DIPNAME( 0x01, 0x01, "Floppy installed")
294	294	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
295	295	PORT_DIPSETTING( 0x01, DEF_STR( Yes ) )
296
	296
297	297	PORT_INCLUDE( kb_keytronic_at ) /* IN4 - IN11 */
298	298	PORT_INCLUDE( pcvideo_cga )
299	299	INPUT_PORTS_END
r12348	r12349
382	382	DEVCB_DEVICE_LINE("pic8259_master", pic8259_ir5_w),
383	383	DEVCB_DEVICE_LINE("pic8259_master", pic8259_ir6_w),
384	384	DEVCB_DEVICE_LINE("pic8259_master", pic8259_ir7_w),
385
	385
386	386	DEVCB_DEVICE_LINE("pic8259_slave", pic8259_ir3_w),
387	387	DEVCB_DEVICE_LINE("pic8259_slave", pic8259_ir4_w),
388	388	DEVCB_DEVICE_LINE("pic8259_slave", pic8259_ir5_w),
r12348	r12349
390	390	DEVCB_DEVICE_LINE("pic8259_slave", pic8259_ir7_w),
391	391
392	392	// dma request
393		DEVCB_DEVICE_LINE("dma8237_1", i8237_dreq0_w),
	393	DEVCB_DEVICE_LINE("dma8237_1", i8237_dreq0_w),
394	394	DEVCB_DEVICE_LINE("dma8237_1", i8237_dreq1_w),
395	395	DEVCB_DEVICE_LINE("dma8237_1", i8237_dreq2_w),
396	396	DEVCB_DEVICE_LINE("dma8237_1", i8237_dreq3_w),
397
	397
398	398	DEVCB_DEVICE_LINE("dma8237_2", i8237_dreq1_w),
399	399	DEVCB_DEVICE_LINE("dma8237_2", i8237_dreq2_w),
400	400	DEVCB_DEVICE_LINE("dma8237_2", i8237_dreq3_w),
r12348	r12349
431	431	MCFG_KB_KEYTRONIC_ADD("keyboard", at_keytronic_intf)
432	432
433	433	MCFG_MC146818_IRQ_ADD( "rtc", MC146818_STANDARD, at_mc146818_config )
434
	434
435	435	/* sound hardware */
436	436	MCFG_SPEAKER_STANDARD_MONO("mono")
437	437	MCFG_SOUND_ADD(SPEAKER_TAG, SPEAKER_SOUND, 0)
r12348	r12349
451	451	MCFG_ISA16_BUS_ADD("isabus", "maincpu", isabus_intf)
452	452	MCFG_ISA8_SLOT_ADD("isabus","isa1", pc_isa8_cards, "fdc", NULL)
453	453	MCFG_ISA16_SLOT_ADD("isabus","isa2", pc_isa16_cards, "ide", NULL)
454
	454
455	455	MCFG_FRAGMENT_ADD( pcvideo_ega )
456	456
457	457	/* software lists */
r12348	r12349
489	489	MCFG_ISA16_SLOT_ADD("isabus","isa2", pc_isa16_cards, "ide", NULL)
490	490
491	491	MCFG_FRAGMENT_ADD( pcvideo_cga )
492
	492
493	493	/* internal ram */
494	494	MCFG_RAM_ADD(RAM_TAG)
495	495	MCFG_RAM_DEFAULT_SIZE("1664K")
r12348	r12349
502	502	MCFG_CPU_PROGRAM_MAP(at16_map)
503	503	MCFG_CPU_IO_MAP(at16_io)
504	504	MCFG_CPU_CONFIG(i286_address_mask)
505
	505
506	506	MCFG_FRAGMENT_ADD( at_motherboard )
507	507
508	508	MCFG_ISA16_BUS_ADD("isabus", "maincpu", isabus_intf)
r12348	r12349
553	553	MCFG_ISA16_SLOT_ADD("isabus","isa2", pc_isa16_cards, "ide", NULL)
554	554
555	555	MCFG_FRAGMENT_ADD( pcvideo_vga )
556
	556
557	557	/* internal ram */
558	558	MCFG_RAM_ADD(RAM_TAG)
559	559	MCFG_RAM_DEFAULT_SIZE("1664K")
r12348	r12349
906	906	/* actual VGA BIOS not dumped*/
907	907	ROM_REGION(0x1000000, "maincpu", 0)
908	908	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
909
	909
910	910	// XEN-S (Venus I Motherboard)
911	911	ROM_LOAD16_BYTE("3-10-17i.lo", 0xf0000, 0x8000, CRC(3786ca1e) SHA1(c682d7c76f234559d03bcf21010c13c4dbeafb69))
912	912	ROM_RELOAD(0xff0000,0x8000)
r12348	r12349
918	918	/* actual VGA BIOS not dumped*/
919	919	ROM_REGION(0x1000000, "maincpu", 0)
920	920	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
921
	921
922	922	// XEN-S (Venus II Motherboard)
923	923	ROM_LOAD16_BYTE("10217.lo", 0xf0000, 0x8000, CRC(ea53406f) SHA1(2958dfdbda14de4e6b9d6a8c3781131ab1e32bef))
924	924	ROM_RELOAD(0xff0000,0x8000)
r12348	r12349
930	930	/* actual VGA BIOS not dumped */
931	931	ROM_REGION(0x1000000, "maincpu", 0)
932	932	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
933
	933
934	934	// XEN-S (Venus I Motherboard)
935	935	ROM_LOAD16_BYTE("3-10-17i.lo", 0xf0000, 0x8000, CRC(3786ca1e) SHA1(c682d7c76f234559d03bcf21010c13c4dbeafb69))
936	936	ROM_RELOAD(0xff0000,0x8000)
r12348	r12349
942	942	/* actual VGA BIOS not dumped*/
943	943	ROM_REGION(0x1000000, "maincpu", 0)
944	944	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
945
	945
946	946	// XEN-S (Venus II Motherboard)
947	947	ROM_LOAD16_BYTE("10217.lo", 0xf0000, 0x8000, CRC(ea53406f) SHA1(2958dfdbda14de4e6b9d6a8c3781131ab1e32bef))
948	948	ROM_RELOAD(0xff0000,0x8000)
r12348	r12349
1112	1112	ROM_REGION(0x1000000,"maincpu", 0)
1113	1113	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1114	1114
1115		ROM_LOAD16_BYTE( "qi310223.lo", 0xe0000, 0x10000, CRC(53047f49) SHA1(7b38e533f7f27295269549c63e5477d950239167))
1116		ROM_LOAD16_BYTE( "qi310223.hi", 0xe0001, 0x10000, CRC(4852869f) SHA1(98599d4691d40b3fac2936034c70b386ce4caf77))
	1115	ROM_LOAD16_BYTE( "qi310223.lo", 0xe0000, 0x10000, CRC(53047f49) SHA1(7b38e533f7f27295269549c63e5477d950239167))
	1116	ROM_LOAD16_BYTE( "qi310223.hi", 0xe0001, 0x10000, CRC(4852869f) SHA1(98599d4691d40b3fac2936034c70b386ce4caf77))
1117	1117	ROM_END
1118	1118
1119	1119	ROM_START( qi600 )
1120	1120	ROM_REGION(0x1000000,"maincpu", 0)
1121	1121	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1122	1122
1123		ROM_LOAD16_BYTE( "qi610223.lo", 0xe0000, 0x10000, CRC(563114a9) SHA1(62932b3bf0b5502ff708f604c21773f00afda58e))
1124		ROM_LOAD16_BYTE( "qi610223.hi", 0xe0001, 0x10000, CRC(0ae133f6) SHA1(6039c366f7fe0ebf60b34c1a7d6b2d781b664001))
	1123	ROM_LOAD16_BYTE( "qi610223.lo", 0xe0000, 0x10000, CRC(563114a9) SHA1(62932b3bf0b5502ff708f604c21773f00afda58e))
	1124	ROM_LOAD16_BYTE( "qi610223.hi", 0xe0001, 0x10000, CRC(0ae133f6) SHA1(6039c366f7fe0ebf60b34c1a7d6b2d781b664001))
1125	1125	ROM_END
1126	1126
1127	1127	ROM_START( qi900 )
1128	1128	ROM_REGION(0x1000000,"maincpu", 0)
1129	1129	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1130	1130
1131		ROM_LOAD16_BYTE( "qi910224.lo", 0xe0000, 0x10000, CRC(b012ad3c) SHA1(807e788a6bd03f5e983fe503af3d0b202c754b8a))
1132		ROM_LOAD16_BYTE( "qi910224.hi", 0xe0001, 0x10000, CRC(36e66d56) SHA1(0900c5272ec3ced550f18fb08db59ab7f67a621e))
	1131	ROM_LOAD16_BYTE( "qi910224.lo", 0xe0000, 0x10000, CRC(b012ad3c) SHA1(807e788a6bd03f5e983fe503af3d0b202c754b8a))
	1132	ROM_LOAD16_BYTE( "qi910224.hi", 0xe0001, 0x10000, CRC(36e66d56) SHA1(0900c5272ec3ced550f18fb08db59ab7f67a621e))
1133	1133	ROM_END
1134	1134
1135	1135	ROM_START( ftsserv )
1136	1136	ROM_REGION(0x1000000,"maincpu", 0)
1137	1137	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1138	1138
1139		ROM_LOAD16_BYTE( "fts10226.lo", 0xe0000, 0x10000, CRC(efbd738f) SHA1(d5258760bafdaf1bf13c4a49da76d4b5e7b4ccbd))
1140		ROM_LOAD16_BYTE( "fts10226.hi", 0xe0001, 0x10000, CRC(2460853f) SHA1(a6bba8d2f800140afd129c4d5278f7ae8fe7e63a))
	1139	ROM_LOAD16_BYTE( "fts10226.lo", 0xe0000, 0x10000, CRC(efbd738f) SHA1(d5258760bafdaf1bf13c4a49da76d4b5e7b4ccbd))
	1140	ROM_LOAD16_BYTE( "fts10226.hi", 0xe0001, 0x10000, CRC(2460853f) SHA1(a6bba8d2f800140afd129c4d5278f7ae8fe7e63a))
1141	1141	/* FT Server series Front Panel */
1142	1142	ROM_REGION(0x10000,"front", 0)
1143	1143	ROM_LOAD( "fp10009.bin", 0x0000, 0x8000, CRC(8aa7f718) SHA1(9ee6c6a5bb92622ea8d3805196d42ff68887d820))
r12348	r12349
1147	1147	ROM_REGION(0x1000000,"maincpu", 0)
1148	1148	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1149	1149
1150		ROM_LOAD16_BYTE( "31020.lo", 0xf0000, 0x8000, CRC(a19678d2) SHA1(d13c12fa7e94333555eabf58b81bad421e21cd91))
1151		ROM_LOAD16_BYTE( "31020.hi", 0xf0001, 0x8000, CRC(4922e020) SHA1(64e6448323dad2209e004cd93fa181582e768ed5))
	1150	ROM_LOAD16_BYTE( "31020.lo", 0xf0000, 0x8000, CRC(a19678d2) SHA1(d13c12fa7e94333555eabf58b81bad421e21cd91))
	1151	ROM_LOAD16_BYTE( "31020.hi", 0xf0001, 0x8000, CRC(4922e020) SHA1(64e6448323dad2209e004cd93fa181582e768ed5))
1152	1152	ROM_END
1153	1153
1154	1154	ROM_START( aplanst )
1155	1155	ROM_REGION(0x1000000,"maincpu", 0)
1156	1156	ROM_LOAD("et4000.bin", 0x00000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1157
	1157
1158	1158	ROM_SYSTEM_BIOS(0, "31024", "Bios 3-10-24")
1159	1159	ROMX_LOAD("31024.lo", 0xf0000, 0x8000, CRC(e52b59e1) SHA1(cfcaa4d8d658df8df463108ef30695bd4ee7a617), ROM_SKIP(1) \| ROM_BIOS(1) )
1160	1160	ROMX_LOAD("31024.hi", 0xf0001, 0x8000, CRC(7286aefa) SHA1(dfc0e3f4936780fa62ae9ec392ce17aa65e717cd), ROM_SKIP(1) \| ROM_BIOS(1) )
r12348	r12349
1170	1170	ROM_REGION(0x1000000,"maincpu", 0)
1171	1171	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1172	1172
1173		ROM_LOAD16_BYTE( "lsl31025.lo", 0xe0000, 0x10000, CRC(8bb7229b) SHA1(31449d12884ec4e7752e6c1ce7ce9e0d044eadf2))
1174		ROM_LOAD16_BYTE( "lsh31025.hi", 0xe0001, 0x10000, CRC(09e5c1b9) SHA1(d42be83b4181d3733268c29df04a4d2918370f4e))
	1173	ROM_LOAD16_BYTE( "lsl31025.lo", 0xe0000, 0x10000, CRC(8bb7229b) SHA1(31449d12884ec4e7752e6c1ce7ce9e0d044eadf2))
	1174	ROM_LOAD16_BYTE( "lsh31025.hi", 0xe0001, 0x10000, CRC(09e5c1b9) SHA1(d42be83b4181d3733268c29df04a4d2918370f4e))
1175	1175	ROM_END
1176	1176
1177	1177	ROM_START( apvxft )
1178	1178	ROM_REGION(0x1000000,"maincpu", 0)
1179	1179	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1180	1180
1181		ROM_LOAD16_BYTE( "ft10221.lo", 0xe0000, 0x10000, CRC(8f339de0) SHA1(a6542406746eaf1ff7f9e3678c5cbe5522fb314a))
1182		ROM_LOAD16_BYTE( "ft10221.hi", 0xe0001, 0x10000, CRC(3b16bc31) SHA1(0592d1d81e7fd4715b0612083482db122d78c7f2))
	1181	ROM_LOAD16_BYTE( "ft10221.lo", 0xe0000, 0x10000, CRC(8f339de0) SHA1(a6542406746eaf1ff7f9e3678c5cbe5522fb314a))
	1182	ROM_LOAD16_BYTE( "ft10221.hi", 0xe0001, 0x10000, CRC(3b16bc31) SHA1(0592d1d81e7fd4715b0612083482db122d78c7f2))
1183	1183	ROM_END
1184	1184
1185	1185	ROM_START( aplscar )
r12348	r12349
1202	1202	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1203	1203
1204	1204	ROM_SYSTEM_BIOS(0, "p2r02g2", "p2r02g2")
1205		ROMX_LOAD("p2r02g2.bin", 0xe0000, 0x20000, CRC(311bcc5a) SHA1(be6fa144322077dcf66b065e7f4e61aab8c278b4), ROM_BIOS(1))
	1205	ROMX_LOAD("p2r02g2.bin", 0xe0000, 0x20000, CRC(311bcc5a) SHA1(be6fa144322077dcf66b065e7f4e61aab8c278b4), ROM_BIOS(1))
1206	1206	ROM_SYSTEM_BIOS(1, "lep121s", "SCSI-Enabling ROMs")
1207	1207	ROMX_LOAD("p2r01f0.bin", 0xe0000, 0x20000, CRC(bbc68f2e) SHA1(6954a52a7dda5521794151aff7a04225e9c7df77), ROM_BIOS(2))
1208	1208	ROM_END
r12348	r12349
1212	1212	ROM_LOAD("et4000.bin", 0xc0000, 0x8000, CRC(f1e817a8) SHA1(945d405b0fb4b8f26830d495881f8587d90e5ef9) )
1213	1213
1214	1214	ROM_SYSTEM_BIOS(0, "lep121", "Rom Bios 1.2.1")
1215		ROMX_LOAD( "lep121.bin", 0xf8000, 0x8000, CRC(948c1927) SHA1(d06bdbd6292db73c815ad1060daf055293dfddf5), ROM_BIOS(1))
	1215	ROMX_LOAD( "lep121.bin", 0xf8000, 0x8000, CRC(948c1927) SHA1(d06bdbd6292db73c815ad1060daf055293dfddf5), ROM_BIOS(1))
1216	1216	ROM_SYSTEM_BIOS(1, "lep121s", "SCSI-Enabling ROMs")
1217	1217	ROMX_LOAD( "lep121s.bin", 0xf8000, 0x8000, CRC(296118e4) SHA1(d1feaa9704e6ce3bc10c900bdd310d9494b02304), ROM_BIOS(2))
1218	1218	ROM_END
r12348	r12349
1299	1299	COMP ( 1984, ibm5170, 0, ibm5150, ibm5170, atcga, atega, "International Business Machines", "IBM PC/AT 5170", GAME_NOT_WORKING )
1300	1300	COMP ( 1985, ibm5170a, ibm5170, 0, ibm5170a, atcga, atega, "International Business Machines", "IBM PC/AT 5170 8MHz", GAME_NOT_WORKING )
1301	1301	COMP ( 1985, ibm5162, ibm5170, 0, ibm5162, atcga, atcga, "International Business Machines", "IBM PC/XT-286 5162", GAME_NOT_WORKING )
1302		COMP ( 1988, i8530286, ibm5170, 0, ps2m30286, atvga, atvga, "International Business Machines", "IBM PS/2 Model 30-286", GAME_NOT_WORKING )
	1302	COMP ( 1988, i8530286, ibm5170, 0, ps2m30286, atvga, atvga, "International Business Machines", "IBM PS/2 Model 30-286", GAME_NOT_WORKING )
1303	1303	COMP ( 1989, i8555081, ibm5170, 0, at386, atvga, atvga, "International Business Machines", "IBM PS/2 Model 55SX", GAME_NOT_WORKING )
1304	1304	COMP ( 1987, at, ibm5170, 0, ibm5162, atcga, atcga, "<generic>", "PC/AT (CGA, MF2 Keyboard)", GAME_NOT_WORKING )
1305	1305	COMP ( 1987, atvga, ibm5170, 0, atvga, atvga, atvga, "<generic>", "PC/AT (VGA, MF2 Keyboard)" , GAME_NOT_WORKING )

src/mess/drivers/amstrad.c
r12348	r12349
73	73	To get rid of duplicated code the drivers have been changed to use the new mc6845 device
74	74	implementation. As a result the (runtime) selection of CRTC type has been removed.
75	75
76		July 2011 - added basic expansion port interface, with support for both the Amstrad SSA-1 and DK'Tronics
77		speech synthesisers.
	76	July 2011 - added basic expansion port interface, with support for both the Amstrad SSA-1 and DK'Tronics
	77	speech synthesisers.
78	78
79	79
80	80	Some bugs left :

src/mess/drivers/ng_aes.c
r12348	r12349
1935	1935	MCFG_CARTSLOT_LOAD(aes_cartridge)
1936	1936	MCFG_CARTSLOT_INTERFACE("aes_cart")
1937	1937	MCFG_CARTSLOT_MANDATORY
1938
	1938
1939	1939	MCFG_SOFTWARE_LIST_ADD("cart_list","aes")
1940	1940	MACHINE_CONFIG_END
1941	1941

src/mess/drivers/sdk86.c
r12348	r12349
104	104	// FFF0-FFF3 = 8251 serial chip (even -> data, control) AM_MIRROR(4)
105	105	// FFF8-FFFF = 2 x 8255A i/o chips. chip 1 uses the odd addresses, chip 2 uses the even addresses.
106	106	// ports are A,B,C,control in that order.
107
108
	107
	108
109	109	ADDRESS_MAP_END
110	110
111	111	/* Input ports */

src/mess/drivers/comx35.c
r12348	r12349
29	29	int extrom = 1;
30	30
31	31	UINT8 data = m_expansion->mrd_r(offset, &extrom);
32
	32
33	33	if (offset < 0x4000)
34	34	{
35	35	if (extrom) data = rom[offset & 0x3fff];
r12348	r12349
42	42	{
43	43	data = m_vis->char_ram_r(space, offset & 0x3ff);
44	44	}
45
	45
46	46	return data;
47	47	}
48	48
r12348	r12349
79	79	READ8_MEMBER( comx35_state::io_r )
80	80	{
81	81	UINT8 data = m_expansion->io_r(offset);
82
	82
83	83	if (offset == 3)
84	84	{
85	85	data = m_kbe->data_r(space, 0);
86	86	}
87
	87
88	88	return data;
89	89	}
90	90
r12348	r12349
335	335
336	336	// cassette output
337	337	m_cassette->output(state ? +1.0 : -1.0);
338
	338
339	339	// expansion bus
340	340	m_expansion->q_w(state);
341	341	}
r12348	r12349
519	519	MCFG_PRINTER_ADD("printer")
520	520
521	521	MCFG_COMXPL80_ADD()
522
	522
523	523	// expansion bus
524	524	MCFG_COMX_EXPANSION_SLOT_ADD(EXPANSION_TAG, expansion_intf, comx_expansion_cards, "eb", NULL)
525	525
r12348	r12349
550	550	MCFG_PRINTER_ADD("printer")
551	551
552	552	MCFG_COMXPL80_ADD()
553
	553
554	554	// expansion bus
555	555	MCFG_COMX_EXPANSION_SLOT_ADD(EXPANSION_TAG, expansion_intf, comx_expansion_cards, "eb", NULL)
556	556

src/mess/drivers/tdv2324.c
r12348	r12349
1	1	/*
2	2
3	3	Tandberg TDV2324
4
5		Skeleton driver
6	4
	5	Skeleton driver
	6
7	7	*/
8	8
9	9	#define ADDRESS_MAP_MODERN
r12348	r12349
86	86
87	87	MCFG_PALETTE_LENGTH(2)
88	88	MCFG_PALETTE_INIT(monochrome_green)
89
	89
90	90	// devices
91	91	MCFG_S1410_ADD() // 104521-F ROM
92	92	MACHINE_CONFIG_END

src/mess/drivers/slc1.c
r12348	r12349
11	11	1 Kbyte RAM in the address range 5000-53ff
12	12	6-digit 7-segment display
13	13	Busy LED
14		Keyboard with 12 keys
	14	Keyboard with 12 keys
15	15
16	16	ToDo:
17	17	- Everything
r12348	r12349
65	65	WRITE8_MEMBER( slc1_state::io_w )
66	66	{
67	67	UINT8 upper = offset >> 8;
68		// if (upper == 0x2f) return;
	68	// if (upper == 0x2f) return;
69	69
70	70
71	71	speaker_level_w(m_speaker, (upper == 0x29));
72	72
73		// output_set_led_value(0, BIT(data, 4));
	73	// output_set_led_value(0, BIT(data, 4));
74	74
75	75	// This computer sets each segment, one at a time. */
76	76

src/mess/drivers/mac.c
r12348	r12349
76	76	mac->m_rbv_regs[2] &= ~0x40; // set vblank signal
77	77	mac->m_rbv_vbltime = 10;
78	78
79		// printf("RBV: raising VBL!\n");
	79	// printf("RBV: raising VBL!\n");
80	80
81	81	if (mac->m_rbv_regs[0x12] & 0x40)
82	82	{
r12348	r12349
181	181
182	182	WRITE8_MEMBER( mac_state::mac_sonora_vctl_w )
183	183	{
184		// printf("Sonora: %02x to vctl %x\n", data, offset);
	184	// printf("Sonora: %02x to vctl %x\n", data, offset);
185	185	m_sonora_vctl[offset] = data;
186	186	}
187	187
r12348	r12349
191	191	UINT8 slot_irqs = (~m_rbv_regs[2]) & 0x78;
192	192	slot_irqs &= (m_rbv_regs[0x12] & 0x78);
193	193
194		// printf("slot_irqs = %02x\n", slot_irqs);
	194	// printf("slot_irqs = %02x\n", slot_irqs);
195	195	if (slot_irqs)
196	196	{
197	197	m_rbv_regs[3] \|= 2; // any slot
r12348	r12349
203	203
204	204	UINT8 ifr = (m_rbv_regs[3] & m_rbv_ier) & 0x1b; //m_rbv_regs[0x13]);
205	205
206		// printf("ifr = %02x (reg3 %02x reg13 %02x)\n", ifr, m_rbv_regs[3], m_rbv_regs[0x13]);
	206	// printf("ifr = %02x (reg3 %02x reg13 %02x)\n", ifr, m_rbv_regs[3], m_rbv_regs[0x13]);
207	207	if (ifr != 0)
208	208	{
209	209	m_rbv_regs[3] = ifr \| 0x80;
210	210	m_rbv_ifr = ifr \| 0x80;
211	211
212		// printf("VIA2 raise\n");
	212	// printf("VIA2 raise\n");
213	213	this->set_via2_interrupt(1);
214	214	}
215	215	else
216	216	{
217		// printf("VIA2 lower\n");
	217	// printf("VIA2 lower\n");
218	218	this->set_via2_interrupt(0);
219	219	}
220	220	}
r12348	r12349
247	247	switch (offset)
248	248	{
249	249	case 13: // IFR
250		// printf("Read IER = %02x (PC=%x) 2=%02x\n", m_rbv_ier, cpu_get_pc(m_maincpu), m_rbv_regs[2]);
	250	// printf("Read IER = %02x (PC=%x) 2=%02x\n", m_rbv_ier, cpu_get_pc(m_maincpu), m_rbv_regs[2]);
251	251	return m_rbv_ifr;
252	252	break;
253	253
254	254	case 14: // IER
255		// printf("Read IFR = %02x (PC=%x) 2=%02x\n", m_rbv_ifr, cpu_get_pc(m_maincpu), m_rbv_regs[2]);
	255	// printf("Read IFR = %02x (PC=%x) 2=%02x\n", m_rbv_ifr, cpu_get_pc(m_maincpu), m_rbv_regs[2]);
256	256	return m_rbv_ier;
257	257	break;
258	258
r12348	r12349
262	262	}
263	263	}
264	264
265		// printf("rbv_r: %x = %02x (PC=%x)\n", offset, data, cpu_get_pc(m_maincpu));
	265	// printf("rbv_r: %x = %02x (PC=%x)\n", offset, data, cpu_get_pc(m_maincpu));
266	266
267	267	return data;
268	268	}
r12348	r12349
272	272	if (offset < 0x100)
273	273	{
274	274	// if (offset == 0x10)
275		// printf("rbv_w: %02x to offset %x (PC=%x)\n", data, offset, cpu_get_pc(m_maincpu));
	275	// printf("rbv_w: %02x to offset %x (PC=%x)\n", data, offset, cpu_get_pc(m_maincpu));
276	276	switch (offset)
277	277	{
278	278	case 0x00:
r12348	r12349
355	355	switch (offset)
356	356	{
357	357	case 13: // IFR
358		// printf("%02x to IFR (PC=%x)\n", data, cpu_get_pc(m_maincpu));
	358	// printf("%02x to IFR (PC=%x)\n", data, cpu_get_pc(m_maincpu));
359	359	if (data & 0x80)
360	360	{
361	361	data = 0x7f;
r12348	r12349
364	364	break;
365	365
366	366	case 14: // IER
367		// printf("%02x to IER (PC=%x)\n", data, cpu_get_pc(m_maincpu));
	367	// printf("%02x to IER (PC=%x)\n", data, cpu_get_pc(m_maincpu));
368	368	if (data & 0x80) // 1 bits write 1s
369	369	{
370	370	m_rbv_ier \|= data & 0x7f;
r12348	r12349
385	385
386	386	READ32_MEMBER(mac_state::mac_read_id)
387	387	{
388		// printf("Mac read ID reg @ PC=%x\n", cpu_get_pc(m_maincpu));
	388	// printf("Mac read ID reg @ PC=%x\n", cpu_get_pc(m_maincpu));
389	389
390	390	switch (m_model)
391	391	{
r12348	r12349
431	431	// IIfx
432	432	READ32_MEMBER(mac_state::biu_r)
433	433	{
434		// printf("biu_r @ %x, mask %08x\n", offset, mem_mask);
	434	// printf("biu_r @ %x, mask %08x\n", offset, mem_mask);
435	435	return 0;
436	436	}
437	437
438	438	WRITE32_MEMBER(mac_state::biu_w)
439	439	{
440		// printf("biu_w %x @ %x, mask %08x\n", data, offset, mem_mask);
	440	// printf("biu_w %x @ %x, mask %08x\n", data, offset, mem_mask);
441	441	}
442	442
443	443	READ8_MEMBER(mac_state::oss_r)
444	444	{
445		// printf("oss_r @ %x\n", offset);
446		// if (offset <= 0xe) // for interrupt mask registers, we're intended to return something different than is written in the low 3 bits (?)
447		// {
448		// return m_oss_regs[offset]<<4;
449		// }
	445	// printf("oss_r @ %x\n", offset);
	446	// if (offset <= 0xe) // for interrupt mask registers, we're intended to return something different than is written in the low 3 bits (?)
	447	// {
	448	// return m_oss_regs[offset]<<4;
	449	// }
450	450
451	451	return m_oss_regs[offset];
452	452	}
453	453
454	454	WRITE8_MEMBER(mac_state::oss_w)
455	455	{
456		// printf("oss_w %x @ %x\n", data, offset);
	456	// printf("oss_w %x @ %x\n", data, offset);
457	457	m_oss_regs[offset] = data;
458	458	}
459	459
r12348	r12349
466	466
467	467	READ8_MEMBER(mac_state::scciop_r)
468	468	{
469		// printf("scciop_r @ %x (PC=%x)\n", offset, cpu_get_pc(m_maincpu));
	469	// printf("scciop_r @ %x (PC=%x)\n", offset, cpu_get_pc(m_maincpu));
470	470	return 0;
471	471	}
472	472
473	473	WRITE8_MEMBER(mac_state::scciop_w)
474	474	{
475		// printf("scciop_w %x @ %x (PC=%x)\n", data, offset, cpu_get_pc(m_maincpu));
	475	// printf("scciop_w %x @ %x (PC=%x)\n", data, offset, cpu_get_pc(m_maincpu));
476	476	}
477	477
478	478	READ8_MEMBER(mac_state::swimiop_r)
479	479	{
480		// printf("swimiop_r @ %x (PC=%x)\n", offset, cpu_get_pc(m_maincpu));
	480	// printf("swimiop_r @ %x (PC=%x)\n", offset, cpu_get_pc(m_maincpu));
481	481	return 0;
482	482	}
483	483
484	484	WRITE8_MEMBER(mac_state::swimiop_w)
485	485	{
486		// printf("swimiop_w %x @ %x (PC=%x)\n", data, offset, cpu_get_pc(m_maincpu));
	486	// printf("swimiop_w %x @ %x (PC=%x)\n", data, offset, cpu_get_pc(m_maincpu));
487	487	}
488	488
489	489	READ8_MEMBER(mac_state::pmac_diag_r)
r12348	r12349
504	504
505	505	WRITE8_MEMBER(mac_state::amic_dma_w)
506	506	{
507		// printf("amic_dma_w: %02x at %x (PC=%x)\n", data, offset+0x1000, cpu_get_pc(m_maincpu));
	507	// printf("amic_dma_w: %02x at %x (PC=%x)\n", data, offset+0x1000, cpu_get_pc(m_maincpu));
508	508	}
509	509
510	510	// HMC has one register: a 35-bit shift register which is accessed one bit at a time (see pmac6100 code at 4030383c which makes this obvious)
r12348	r12349
709	709
710	710	static ADDRESS_MAP_START(macpb160_map, AS_PROGRAM, 32, mac_state )
711	711	AM_RANGE(0x40000000, 0x400fffff) AM_ROM AM_REGION("bootrom", 0) AM_MIRROR(0x0ff00000)
712
	712
713	713	AM_RANGE(0x50f00000, 0x50f01fff) AM_READWRITE16(mac_via_r, mac_via_w, 0xffffffff)
714	714	AM_RANGE(0x50f02000, 0x50f03fff) AM_READWRITE16(mac_via2_r, mac_via2_w, 0xffffffff)
715	715	AM_RANGE(0x50f04000, 0x50f05fff) AM_READWRITE16(mac_scc_r, mac_scc_2_w, 0xffffffff)
r12348	r12349
725	725	ADDRESS_MAP_END
726	726	/*
727	727	static ADDRESS_MAP_START(macpb165c_map, AS_PROGRAM, 32, mac_state )
728		AM_RANGE(0x40000000, 0x400fffff) AM_ROM AM_REGION("bootrom", 0) AM_MIRROR(0x0ff00000)
729
730		AM_RANGE(0x50f00000, 0x50f01fff) AM_READWRITE16(mac_via_r, mac_via_w, 0xffffffff)
731		AM_RANGE(0x50f02000, 0x50f03fff) AM_READWRITE16(mac_via2_r, mac_via2_w, 0xffffffff)
732		AM_RANGE(0x50f04000, 0x50f05fff) AM_READWRITE16(mac_scc_r, mac_scc_2_w, 0xffffffff)
733		AM_RANGE(0x50f06000, 0x50f07fff) AM_READWRITE(macii_scsi_drq_r, macii_scsi_drq_w)
734		AM_RANGE(0x50f10000, 0x50f11fff) AM_READWRITE16(macplus_scsi_r, macii_scsi_w, 0xffffffff)
735		AM_RANGE(0x50f12060, 0x50f12063) AM_READ(macii_scsi_drq_r)
736		AM_RANGE(0x50f14000, 0x50f15fff) AM_DEVREADWRITE8("asc", asc_device, read, write, 0xffffffff)
737		AM_RANGE(0x50f16000, 0x50f17fff) AM_READWRITE16(mac_iwm_r, mac_iwm_w, 0xffffffff)
738		AM_RANGE(0x50f20000, 0x50f21fff) AM_READ(buserror_r) // bus error here to detect we're not the grayscale 160/165/180
739		AM_RANGE(0x50f24000, 0x50f27fff) AM_READ(buserror_r) // bus error here to make sure we aren't mistaken for another decoder
	728	AM_RANGE(0x40000000, 0x400fffff) AM_ROM AM_REGION("bootrom", 0) AM_MIRROR(0x0ff00000)
740	729
741		AM_RANGE(0xfc040000, 0xfc07ffff) AM_RAM AM_BASE(m_vram)
742		AM_RANGE(0xfcff0000, 0xfcffffff) AM_ROM AM_REGION("bootrom", 0xf0000)
	730	AM_RANGE(0x50f00000, 0x50f01fff) AM_READWRITE16(mac_via_r, mac_via_w, 0xffffffff)
	731	AM_RANGE(0x50f02000, 0x50f03fff) AM_READWRITE16(mac_via2_r, mac_via2_w, 0xffffffff)
	732	AM_RANGE(0x50f04000, 0x50f05fff) AM_READWRITE16(mac_scc_r, mac_scc_2_w, 0xffffffff)
	733	AM_RANGE(0x50f06000, 0x50f07fff) AM_READWRITE(macii_scsi_drq_r, macii_scsi_drq_w)
	734	AM_RANGE(0x50f10000, 0x50f11fff) AM_READWRITE16(macplus_scsi_r, macii_scsi_w, 0xffffffff)
	735	AM_RANGE(0x50f12060, 0x50f12063) AM_READ(macii_scsi_drq_r)
	736	AM_RANGE(0x50f14000, 0x50f15fff) AM_DEVREADWRITE8("asc", asc_device, read, write, 0xffffffff)
	737	AM_RANGE(0x50f16000, 0x50f17fff) AM_READWRITE16(mac_iwm_r, mac_iwm_w, 0xffffffff)
	738	AM_RANGE(0x50f20000, 0x50f21fff) AM_READ(buserror_r) // bus error here to detect we're not the grayscale 160/165/180
	739	AM_RANGE(0x50f24000, 0x50f27fff) AM_READ(buserror_r) // bus error here to make sure we aren't mistaken for another decoder
	740
	741	AM_RANGE(0xfc040000, 0xfc07ffff) AM_RAM AM_BASE(m_vram)
	742	AM_RANGE(0xfcff0000, 0xfcffffff) AM_ROM AM_REGION("bootrom", 0xf0000)
743	743	ADDRESS_MAP_END
744	744	*/
745	745
r12348	r12349
761	761	AM_RANGE(0x50028000, 0x50028007) AM_READWRITE8(mac_sonora_vctl_r, mac_sonora_vctl_w, U64(0xffffffffffffffff)) AM_MIRROR(0x00f00000)
762	762	// 5002a000 = interrupt controller
763	763	// 5002c000 = diagnostic registers
764		AM_RANGE(0x5002c000, 0x5002dfff) AM_READ8(pmac_diag_r, U64(0xffffffffffffffff)) AM_MIRROR(0x00f00000)
765		AM_RANGE(0x50031000, 0x50032fff) AM_READWRITE8(amic_dma_r, amic_dma_w, U64(0xffffffffffffffff)) AM_MIRROR(0x00f00000)
766		AM_RANGE(0x50040000, 0x5004000f) AM_READWRITE8(hmc_r, hmc_w, U64(0xffffffffffffffff)) AM_MIRROR(0x00f00000)
	764	AM_RANGE(0x5002c000, 0x5002dfff) AM_READ8(pmac_diag_r, U64(0xffffffffffffffff)) AM_MIRROR(0x00f00000)
	765	AM_RANGE(0x50031000, 0x50032fff) AM_READWRITE8(amic_dma_r, amic_dma_w, U64(0xffffffffffffffff)) AM_MIRROR(0x00f00000)
	766	AM_RANGE(0x50040000, 0x5004000f) AM_READWRITE8(hmc_r, hmc_w, U64(0xffffffffffffffff)) AM_MIRROR(0x00f00000)
767	767	AM_RANGE(0x5ffffff8, 0x5fffffff) AM_READ32(mac_read_id, U64(0xffffffffffffffff))
768	768
769	769	AM_RANGE(0xffc00000, 0xffffffff) AM_ROM AM_REGION("bootrom", 0)
r12348	r12349
810	810	};
811	811
812	812	static SLOT_INTERFACE_START(mac_nubus_cards)
813		// SLOT_INTERFACE("48gc", NUBUS_48GC)
	813	// SLOT_INTERFACE("48gc", NUBUS_48GC)
814	814	SLOT_INTERFACE_END
815	815
816	816	/***************************************************************************
r12348	r12349
1004	1004
1005	1005	/* devices */
1006	1006	MCFG_NUBUS_BUS_ADD("nubus", "maincpu", nubus_intf)
1007		// MCFG_NUBUS_SLOT_ADD("nubus","nb9", mac_nubus_cards, "48gc", NULL)
	1007	// MCFG_NUBUS_SLOT_ADD("nubus","nb9", mac_nubus_cards, "48gc", NULL)
1008	1008
1009	1009	MCFG_NCR5380_ADD("ncr5380", C7M, macplus_5380intf)
1010	1010
r12348	r12349
1373	1373	MACHINE_CONFIG_END
1374	1374	/*
1375	1375	static MACHINE_CONFIG_DERIVED( macpb180c, macpb160 )
1376		MCFG_CPU_REPLACE("maincpu", M68030, 33000000)
1377		MCFG_CPU_PROGRAM_MAP(macpb165c_map)
	1376	MCFG_CPU_REPLACE("maincpu", M68030, 33000000)
	1377	MCFG_CPU_PROGRAM_MAP(macpb165c_map)
1378	1378
1379		MCFG_RAM_MODIFY(RAM_TAG)
1380		MCFG_RAM_DEFAULT_SIZE("4M")
1381		MCFG_RAM_EXTRA_OPTIONS("8M,12M,16M")
	1379	MCFG_RAM_MODIFY(RAM_TAG)
	1380	MCFG_RAM_DEFAULT_SIZE("4M")
	1381	MCFG_RAM_EXTRA_OPTIONS("8M,12M,16M")
1382	1382	MACHINE_CONFIG_END
1383	1383	*/
1384	1384	static MACHINE_CONFIG_DERIVED( macclas2, maclc )
r12348	r12349
1819	1819	ROM_SYSTEM_BIOS(0, "default", "rev. B")
1820	1820	ROMX_LOAD( "9779d2c4.rom", 0x000000, 0x040000, CRC(4df6d054) SHA1(db6b504744281369794e26ba71a6e385cf6227fa), ROM_BIOS(1) )
1821	1821	ROM_SYSTEM_BIOS(1, "original", "rev. A")
1822		ROMX_LOAD( "97851db6.rom", 0x000000, 0x040000, CRC(8c8b9d03) SHA1(5c264fe976f1e8495d364947c932a5e8309b4300), ROM_BIOS(2) )
	1822	ROMX_LOAD( "97851db6.rom", 0x000000, 0x040000, CRC(8c8b9d03) SHA1(5c264fe976f1e8495d364947c932a5e8309b4300), ROM_BIOS(2) )
1823	1823
1824	1824	// RasterOps "ColorBoard 264" NuBus video card
1825	1825	ROM_REGION32_BE(0x8000, "rops264", 0)
r12348	r12349
1832	1832	ROM_SYSTEM_BIOS(0, "default", "rev. B")
1833	1833	ROMX_LOAD( "9779d2c4.rom", 0x000000, 0x040000, CRC(4df6d054) SHA1(db6b504744281369794e26ba71a6e385cf6227fa), ROM_BIOS(1) )
1834	1834	ROM_SYSTEM_BIOS(1, "original", "rev. A")
1835		ROMX_LOAD( "97851db6.rom", 0x000000, 0x040000, CRC(8c8b9d03) SHA1(5c264fe976f1e8495d364947c932a5e8309b4300), ROM_BIOS(2) )
	1835	ROMX_LOAD( "97851db6.rom", 0x000000, 0x040000, CRC(8c8b9d03) SHA1(5c264fe976f1e8495d364947c932a5e8309b4300), ROM_BIOS(2) )
1836	1836
1837	1837	// RasterOps "ColorBoard 264" NuBus video card
1838	1838	ROM_REGION32_BE(0x8000, "rops264", 0)
r12348	r12349
1880	1880
1881	1881	ROM_START( maciifx )
1882	1882	ROM_REGION32_BE(0x80000, "bootrom", 0)
1883		ROM_LOAD( "4147dd77.rom", 0x000000, 0x080000, CRC(ef441bbd) SHA1(9fba3d4f672a630745d65788b1d1119afa2c6728) )
	1883	ROM_LOAD( "4147dd77.rom", 0x000000, 0x080000, CRC(ef441bbd) SHA1(9fba3d4f672a630745d65788b1d1119afa2c6728) )
1884	1884
1885	1885	// RasterOps "ColorBoard 264" NuBus video card
1886	1886	ROM_REGION32_BE(0x8000, "rops264", 0)
r12348	r12349
1900	1900
1901	1901	ROM_START( maciivx )
1902	1902	ROM_REGION32_BE(0x100000, "bootrom", 0)
1903		ROM_LOAD( "4957eb49.rom", 0x000000, 0x100000, CRC(61be06e5) SHA1(560ce203d65178657ad09d03f532f86fa512bb40) )
	1903	ROM_LOAD( "4957eb49.rom", 0x000000, 0x100000, CRC(61be06e5) SHA1(560ce203d65178657ad09d03f532f86fa512bb40) )
1904	1904	ROM_END
1905	1905
1906	1906	ROM_START( maciivi )
1907	1907	ROM_REGION32_BE(0x100000, "bootrom", 0)
1908		ROM_LOAD( "4957eb49.rom", 0x000000, 0x100000, CRC(61be06e5) SHA1(560ce203d65178657ad09d03f532f86fa512bb40) )
	1908	ROM_LOAD( "4957eb49.rom", 0x000000, 0x100000, CRC(61be06e5) SHA1(560ce203d65178657ad09d03f532f86fa512bb40) )
1909	1909	ROM_END
1910	1910
1911	1911	ROM_START( macclas2 )
r12348	r12349
1943	1943
1944	1944	ROM_START( macpb140 )
1945	1945	ROM_REGION32_BE(0x100000, "bootrom", 0)
1946		ROM_LOAD( "420dbff3.rom", 0x000000, 0x100000, CRC(88ea2081) SHA1(7a8ee468d16e64f2ad10cb8d1a45e6f07cc9e212) )
	1946	ROM_LOAD( "420dbff3.rom", 0x000000, 0x100000, CRC(88ea2081) SHA1(7a8ee468d16e64f2ad10cb8d1a45e6f07cc9e212) )
1947	1947	ROM_END
1948	1948
1949	1949	ROM_START( macpb145 )
1950	1950	ROM_REGION32_BE(0x100000, "bootrom", 0)
1951		ROM_LOAD( "420dbff3.rom", 0x000000, 0x100000, CRC(88ea2081) SHA1(7a8ee468d16e64f2ad10cb8d1a45e6f07cc9e212) )
	1951	ROM_LOAD( "420dbff3.rom", 0x000000, 0x100000, CRC(88ea2081) SHA1(7a8ee468d16e64f2ad10cb8d1a45e6f07cc9e212) )
1952	1952	ROM_END
1953	1953
1954	1954	ROM_START( macpb145b )
1955	1955	ROM_REGION32_BE(0x100000, "bootrom", 0)
1956		ROM_LOAD( "420dbff3.rom", 0x000000, 0x100000, CRC(88ea2081) SHA1(7a8ee468d16e64f2ad10cb8d1a45e6f07cc9e212) )
	1956	ROM_LOAD( "420dbff3.rom", 0x000000, 0x100000, CRC(88ea2081) SHA1(7a8ee468d16e64f2ad10cb8d1a45e6f07cc9e212) )
1957	1957	ROM_END
1958	1958
1959	1959	ROM_START( macpb170 )
1960	1960	ROM_REGION32_BE(0x100000, "bootrom", 0)
1961		ROM_LOAD( "420dbff3.rom", 0x000000, 0x100000, CRC(88ea2081) SHA1(7a8ee468d16e64f2ad10cb8d1a45e6f07cc9e212) )
	1961	ROM_LOAD( "420dbff3.rom", 0x000000, 0x100000, CRC(88ea2081) SHA1(7a8ee468d16e64f2ad10cb8d1a45e6f07cc9e212) )
1962	1962	ROM_END
1963	1963
1964	1964	ROM_START( macpb160 )
1965	1965	ROM_REGION32_BE(0x100000, "bootrom", 0)
1966		ROM_LOAD( "e33b2724.rom", 0x000000, 0x100000, CRC(536c60f4) SHA1(c0510682ae6d973652d7e17f3c3b27629c47afac) )
	1966	ROM_LOAD( "e33b2724.rom", 0x000000, 0x100000, CRC(536c60f4) SHA1(c0510682ae6d973652d7e17f3c3b27629c47afac) )
1967	1967	ROM_END
1968	1968
1969	1969	ROM_START( macpb180 )
1970	1970	ROM_REGION32_BE(0x100000, "bootrom", 0)
1971		ROM_LOAD( "e33b2724.rom", 0x000000, 0x100000, CRC(536c60f4) SHA1(c0510682ae6d973652d7e17f3c3b27629c47afac) )
	1971	ROM_LOAD( "e33b2724.rom", 0x000000, 0x100000, CRC(536c60f4) SHA1(c0510682ae6d973652d7e17f3c3b27629c47afac) )
1972	1972	ROM_END
1973	1973
1974	1974	ROM_START( maccclas )
r12348	r12349
1987	1987	COMP( 1987, maciihmu, macii, 0, maciihmu, macadb, macii, "Apple Computer", "Macintosh II (w/o 68851 MMU)", 0 )
1988	1988	COMP( 1988, mac2fdhd, 0, 0, macii, macadb, maciifdhd, "Apple Computer", "Macintosh II (FDHD)", 0 )
1989	1989	COMP( 1988, maciix, mac2fdhd, 0, maciix, macadb, maciix, "Apple Computer", "Macintosh IIx", 0 )
1990		COMP( 1989, macprtb, 0, 0, macprtb, macadb, macprtb, "Apple Computer", "Macintosh Portable", GAME_NOT_WORKING )
	1990	COMP( 1989, macprtb, 0, 0, macprtb, macadb, macprtb, "Apple Computer", "Macintosh Portable", GAME_NOT_WORKING )
1991	1991	COMP( 1989, macse30, mac2fdhd, 0, macse30, macadb, macse30, "Apple Computer", "Macintosh SE/30", 0 )
1992	1992	COMP( 1989, maciicx, mac2fdhd, 0, maciix, macadb, maciicx, "Apple Computer", "Macintosh IIcx", 0 )
1993	1993	COMP( 1989, maciici, 0, 0, maciici, maciici, maciici, "Apple Computer", "Macintosh IIci", 0 )
r12348	r12349
1995	1995	COMP( 1990, macclasc, 0, 0, macse, macadb, macclassic, "Apple Computer", "Macintosh Classic", 0 )
1996	1996	COMP( 1990, maclc, 0, 0, maclc, maciici, maclc, "Apple Computer", "Macintosh LC", GAME_NOT_WORKING )
1997	1997	COMP( 1990, maciisi, 0, 0, maciisi, maciici, maciisi, "Apple Computer", "Macintosh IIsi", GAME_NOT_WORKING )
1998		COMP( 1991, macpb100, 0, 0, macprtb, macadb, macprtb, "Apple Computer", "Macintosh PowerBook 100", GAME_NOT_WORKING )
1999		COMP( 1991, macpb140, 0, 0, macpb140, macadb, macpb140, "Apple Computer", "Macintosh PowerBook 140", GAME_NOT_WORKING )
2000		COMP( 1991, macpb170, macpb140, 0, macpb170, macadb, macpb140, "Apple Computer", "Macintosh PowerBook 170", GAME_NOT_WORKING )
	1998	COMP( 1991, macpb100, 0, 0, macprtb, macadb, macprtb, "Apple Computer", "Macintosh PowerBook 100", GAME_NOT_WORKING )
	1999	COMP( 1991, macpb140, 0, 0, macpb140, macadb, macpb140, "Apple Computer", "Macintosh PowerBook 140", GAME_NOT_WORKING )
	2000	COMP( 1991, macpb170, macpb140, 0, macpb170, macadb, macpb140, "Apple Computer", "Macintosh PowerBook 170", GAME_NOT_WORKING )
2001	2001	COMP( 1991, macclas2, 0, 0, macclas2, macadb, macclassic2, "Apple Computer", "Macintosh Classic II", GAME_NOT_WORKING )
2002		COMP( 1991, maclc2, 0, 0, maclc2, maciici, maclc2, "Apple Computer", "Macintosh LC II", GAME_NOT_WORKING )
2003		COMP( 1992, macpb145, macpb140, 0, macpb145, macadb, macpb140, "Apple Computer", "Macintosh PowerBook 145", GAME_NOT_WORKING )
2004		COMP( 1992, macpb160, 0, 0, macpb160, macadb, macpb160, "Apple Computer", "Macintosh PowerBook 160", GAME_NOT_WORKING )
2005		COMP( 1992, macpb180, macpb160, 0, macpb180, macadb, macpb160, "Apple Computer", "Macintosh PowerBook 180", GAME_NOT_WORKING )
2006		//COMP( 1992, macp180c, macpb160, 0, macpb180c,macadb, macpb160, "Apple Computer", "Macintosh PowerBook 180c", GAME_NOT_WORKING )
	2002	COMP( 1991, maclc2, 0, 0, maclc2, maciici, maclc2, "Apple Computer", "Macintosh LC II", GAME_NOT_WORKING )
	2003	COMP( 1992, macpb145, macpb140, 0, macpb145, macadb, macpb140, "Apple Computer", "Macintosh PowerBook 145", GAME_NOT_WORKING )
	2004	COMP( 1992, macpb160, 0, 0, macpb160, macadb, macpb160, "Apple Computer", "Macintosh PowerBook 160", GAME_NOT_WORKING )
	2005	COMP( 1992, macpb180, macpb160, 0, macpb180, macadb, macpb160, "Apple Computer", "Macintosh PowerBook 180", GAME_NOT_WORKING )
	2006	//COMP( 1992, macp180c, macpb160, 0, macpb180c,macadb, macpb160, "Apple Computer", "Macintosh PowerBook 180c", GAME_NOT_WORKING )
2007	2007	COMP( 1993, maccclas, 0, 0, maclc2, macadb, maclrcclassic,"Apple Computer", "Macintosh Color Classic", GAME_NOT_WORKING )
2008		COMP( 1992, macpb145b,macpb140, 0, macpb170, macadb, macpb140, "Apple Computer", "Macintosh PowerBook 145B", GAME_NOT_WORKING )
	2008	COMP( 1992, macpb145b,macpb140, 0, macpb170, macadb, macpb140, "Apple Computer", "Macintosh PowerBook 145B", GAME_NOT_WORKING )
2009	2009	COMP( 1993, maclc3, 0, 0, maclc3, maciici, maclc3, "Apple Computer", "Macintosh LC III", GAME_NOT_WORKING )
2010	2010	COMP( 1993, maciivx, 0, 0, maciivx, maciici, maciivx, "Apple Computer", "Macintosh IIvx", GAME_NOT_WORKING )
2011	2011	COMP( 1993, maciivi, maciivx, 0, maciivi, maciici, maciivx, "Apple Computer", "Macintosh IIvi", GAME_NOT_WORKING )

src/mess/drivers/z88.c
r12348	r12349
167	167
168	168	/* special case */
169	169	if (read_addr == NULL) printf("Read Bank is NULL\n");
170		// read_addr = &machine.region("maincpu")->base()[start];
	170	// read_addr = &machine.region("maincpu")->base()[start];
171	171
172	172	/* install the handlers */
173	173	machine().device("maincpu")->memory().space(AS_PROGRAM )->install_read_bank(start, start + size - 1, bank_r);
r12348	r12349
606	606	PORT_START("LINE7")
607	607	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Shift (Right)") PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
608	608	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Square") PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1))
609		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
	609	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
610	610	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Index") PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F2))
611	611	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Caps Lock") PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
612	612	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')

src/mess/drivers/prof80.c
r12348	r12349
43	43	//**************************************************************************
44	44
45	45	//-------------------------------------------------
46		// bankswitch -
	46	// bankswitch -
47	47	//-------------------------------------------------
48	48
49	49	void prof80_state::bankswitch()
r12348	r12349
96	96	//**************************************************************************
97	97
98	98	//-------------------------------------------------
99		// floppy_motor_off -
	99	// floppy_motor_off -
100	100	//-------------------------------------------------
101	101
102	102	void prof80_state::floppy_motor_off()
r12348	r12349
123	123
124	124
125	125	//-------------------------------------------------
126		// ls259_w -
	126	// ls259_w -
127	127	//-------------------------------------------------
128	128
129	129	void prof80_state::ls259_w(int fa, int sa, int fb, int sb)
r12348	r12349
225	225
226	226
227	227	//-------------------------------------------------
228		// flr_w -
	228	// flr_w -
229	229	//-------------------------------------------------
230	230
231	231	WRITE8_MEMBER( prof80_state::flr_w )
r12348	r12349
256	256
257	257
258	258	//-------------------------------------------------
259		// status_r -
	259	// status_r -
260	260	//-------------------------------------------------
261	261
262	262	READ8_MEMBER( prof80_state::status_r )
r12348	r12349
291	291
292	292
293	293	//-------------------------------------------------
294		// status2_r -
	294	// status2_r -
295	295	//-------------------------------------------------
296	296
297	297	READ8_MEMBER( prof80_state::status2_r )
r12348	r12349
349	349
350	350
351	351	//-------------------------------------------------
352		// par_w -
	352	// par_w -
353	353	//-------------------------------------------------
354	354
355	355	WRITE8_MEMBER( prof80_state::par_w )
r12348	r12349
368	368	WRITE8_MEMBER( prof80_state::unio_ctrl_w )
369	369	{
370	370	// int flag = BIT(data, 0);
371		int flad = (data >> 1) & 0x07;
	371	int flad = (data >> 1) & 0x07;
372	372
373		switch (flad)
374		{
375		case 0: // CG1
376		case 1: // CG2
377		case 2: // _STB1
378		case 3: // _STB2
379		case 4: // _INIT
380		case 5: // JSO0
381		case 6: // JSO1
382		case 7: // JSO2
383		break;
384		}
	373	switch (flad)
	374	{
	375	case 0: // CG1
	376	case 1: // CG2
	377	case 2: // _STB1
	378	case 3: // _STB2
	379	case 4: // _INIT
	380	case 5: // JSO0
	381	case 6: // JSO1
	382	case 7: // JSO2
	383	break;
	384	}
385	385	}
386	386	*/
387	387
r12348	r12349
408	408	// AM_RANGE(0x80, 0x8f) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY(UNIO_Z80STI_TAG, z80sti_r, z80sti_w)
409	409	// AM_RANGE(0x94, 0x95) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY(UNIO_Z80SIO_TAG, z80sio_d_r, z80sio_d_w)
410	410	// AM_RANGE(0x96, 0x97) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY(UNIO_Z80SIO_TAG, z80sio_c_r, z80sio_c_w)
411		// AM_RANGE(0x9e, 0x9e) AM_MIRROR(0xff00) AM_WRITE(unio_ctrl_w)
	411	// AM_RANGE(0x9e, 0x9e) AM_MIRROR(0xff00) AM_WRITE(unio_ctrl_w)
412	412	// AM_RANGE(0x9c, 0x9c) AM_MIRROR(0xff00) AM_DEVWRITE_LEGACY(UNIO_CENTRONICS1_TAG, centronics_data_w)
413	413	// AM_RANGE(0x9d, 0x9d) AM_MIRROR(0xff00) AM_DEVWRITE_LEGACY(UNIO_CENTRONICS1_TAG, centronics_data_w)
414	414	// AM_RANGE(0xc0, 0xc0) AM_MIRROR(0xff00) AM_READ(gripc_r)
r12348	r12349
573	573
574	574	static SLOT_INTERFACE_START( prof80_ecb_cards )
575	575	SLOT_INTERFACE("grip21", ECB_GRIP21)
576		/* SLOT_INTERFACE("grip25", ECB_GRIP25)
577		SLOT_INTERFACE("grip26", ECB_GRIP26)
578		SLOT_INTERFACE("grip31", ECB_GRIP31)
579		SLOT_INTERFACE("grip562", ECB_GRIP562)
580		SLOT_INTERFACE("grips115", ECB_GRIPS115)*/
	576	/* SLOT_INTERFACE("grip25", ECB_GRIP25)
	577	SLOT_INTERFACE("grip26", ECB_GRIP26)
	578	SLOT_INTERFACE("grip31", ECB_GRIP31)
	579	SLOT_INTERFACE("grip562", ECB_GRIP562)
	580	SLOT_INTERFACE("grips115", ECB_GRIPS115)*/
581	581	SLOT_INTERFACE_END
582	582
583	583
r12348	r12349
656	656	MCFG_UPD1990A_ADD(UPD1990A_TAG, XTAL_32_768kHz, rtc_intf)
657	657	MCFG_UPD765A_ADD(UPD765_TAG, fdc_intf)
658	658	MCFG_LEGACY_FLOPPY_2_DRIVES_ADD(floppy_intf)
659
	659
660	660	// ECB bus
661	661	MCFG_ECBBUS_ADD(Z80_TAG, ecb_intf)
662	662	MCFG_ECBBUS_SLOT_ADD(1, "ecb_1", prof80_ecb_cards, "grip21", NULL)

src/mess/drivers/lisa.c
r12348	r12349
406	406
407	407	ROM_REGION(0x2000,"fdccpu",0) /* 6504 RAM and ROM */
408	408	/* note: other ?prototype? revisions of this rom for the lisa probably exist as well */
409		ROM_LOAD( "341-0138f.bin", 0x000000, 0x001000, CRC(edd8d560) SHA1(872211d21386cd9625b3735d7682e2b2ecff05b4) )
	409	ROM_LOAD( "341-0138f.bin", 0x000000, 0x001000, CRC(edd8d560) SHA1(872211d21386cd9625b3735d7682e2b2ecff05b4) )
410	410
411	411	ROM_REGION(0x4000,"profile", 0) /* Profile/5 HDD */
412	412	ROM_LOAD_OPTIONAL( "341-0080-b", 0x0000, 0x800, CRC(26df0b8d) SHA1(08f6689afb517e0a2bdaa48433003e62a66ae3c7)) /* 341-0080-B z8 mcu piggyback rom */

src/mess/drivers/acrnsys1.c
r12348	r12349
67	67	for (i = 0; i < 8; i++)
68	68	{
69	69	if (BIT(key_line, i))
70		{
	70	{
71	71	char kbdrow[6];
72	72	sprintf(kbdrow,"X%X",i);
73	73	data = (input_port_read(machine(), kbdrow) & 0x38) \| m_digit;

src/mess/drivers/tsispch.c
r12348	r12349
204	204	WRITE8_MEMBER( tsispch_state::peripheral_w )
205	205	{
206	206	/* This controls the four LEDS, the RESET line for the upd77p20,
207		and (probably) the p0-to-ir0 masking of the upd77p20; there are two
208		unknown and seemingly unused bits as well.
209		see the top of the file for more info.
210		*/
	207	and (probably) the p0-to-ir0 masking of the upd77p20; there are two
	208	unknown and seemingly unused bits as well.
	209	see the top of the file for more info.
	210	*/
211	211	tsispch_state *state = machine().driver_data<tsispch_state>();
212	212	state->m_paramReg = data;
213	213	cputag_set_input_line(machine(), "dsp", INPUT_LINE_RESET, BIT(data,6)?CLEAR_LINE:ASSERT_LINE);

src/mess/drivers/c64.c
r12348	r12349
756	756
757	757	MCFG_FRAGMENT_ADD(c64_cartslot)
758	758	MCFG_SOFTWARE_LIST_ADD("disk_list", "c64_flop")
759
	759
760	760	MCFG_C64_EXPANSION_SLOT_ADD("exp", c64_expansion_intf, c64_expansion_cards, NULL, NULL)
761	761	MACHINE_CONFIG_END
762	762
r12348	r12349
813	813
814	814	MCFG_FRAGMENT_ADD(c64_cartslot)
815	815	MCFG_SOFTWARE_LIST_ADD("disk_list", "c64_flop")
816
	816
817	817	MCFG_C64_EXPANSION_SLOT_ADD("exp", c64_expansion_intf, c64_expansion_cards, NULL, NULL)
818	818	MACHINE_CONFIG_END
819	819

src/mess/drivers/pc.c
r12348	r12349
1591	1591	ROM_START( t1000tl2 )
1592	1592	ROM_REGION(0x100000, "maincpu", 0)
1593	1593	ROM_LOAD( "t10000tl2.bin", 0xf0000, 0x10000, CRC(e288f12c) SHA1(9d54ccf773cd7202c9906323f1b5a68b1b3a3a67))
1594
	1594
1595	1595	ROM_REGION(0x08000,"gfx1", 0)
1596	1596	// expects 8x9 charset!
1597	1597	/* Character rom located at U3 w/label "8079027 // NCR // 609-2495004 // F841030 A9025" */
r12348	r12349
1835	1835	COMP( 1987, t1000sx, ibm5150, 0, t1000hx, tandy1t, t1000hx, "Tandy Radio Shack", "Tandy 1000 SX", GAME_NOT_WORKING)
1836	1836	COMP( 1987, t1000tx, ibm5150, 0, t1000_286, tandy1t, t1000hx, "Tandy Radio Shack", "Tandy 1000 TX", 0)
1837	1837	COMP( 1989, t1000rl, ibm5150, 0, t1000_16, tandy1t, t1000hx, "Tandy Radio Shack", "Tandy 1000 RL", 0)
1838		COMP ( 1989, t1000tl2, ibm5150, 0, t1000_286, tandy1t, t1000hx, "Tandy Radio Shack", "Tandy 1000 TL/2", 0)
	1838	COMP ( 1989, t1000tl2, ibm5150, 0, t1000_286, tandy1t, t1000hx, "Tandy Radio Shack", "Tandy 1000 TL/2", 0)
1839	1839
1840	1840	COMP ( 1989, iskr1031, ibm5150, 0, iskr1031, pccga, pccga, "<unknown>", "Iskra-1031" , GAME_NOT_WORKING)
1841	1841	COMP ( 1989, iskr1030m, ibm5150, 0, iskr1031, pccga, pccga, "<unknown>", "Iskra-1030M" , GAME_NOT_WORKING)

15994 Revisions