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r11630 Monday 23rd May, 2011 at 08:24:06 UTC by Miodrag Milanović
pic8259 and i286 core change enabling win 3.1 to boot done by Carl (no whatsnew, credited in MAME)

[src/emu/cpu/i86]	ea.h
[src/emu/machine]	pic8259.c

src/emu/cpu/i86/ea.h

r11629	r11630
19	19	static unsigned EA_200(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[SI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
20	20	static unsigned EA_201(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[DI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
21	21	static unsigned EA_202(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[SI]; cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
22		static unsigned EA_203(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[DI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
	22	static unsigned EA_203(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[DI]; cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
23	23	static unsigned EA_204(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[SI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
24	24	static unsigned EA_205(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[DI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
25	25	static unsigned EA_206(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]; cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }

src/emu/machine/pic8259.c

r11629	r11630
43	43
44	44	pic8259_state_t state;
45	45
46		UINT8 irq_lines;
47		UINT8 esr;
48	46	UINT8 isr;
49	47	UINT8 irr;
50	48	UINT8 prio;
r11629	r11630
126	124	static void pic8259_set_irq_line(device_t *device, int irq, int state)
127	125	{
128	126	pic8259_t   *pic8259 = get_safe_token(device);
129		UINT8      old_irq_lines = pic8259->irq_lines;
130	127
131	128	if (state)
132	129	{
r11629	r11630
134	131	if (LOG_GENERAL)
135	132	logerror("pic8259_set_irq_line(): PIC set IRQ line #%d\n", irq);
136	133
137		pic8259->irq_lines |= 1 << irq;
138
139		/* Set ESR bit if we see a 0 -> 1 transition */
140		if ( ! ( old_irq_lines & ( 1 << irq ) ) )
141		pic8259->esr |= ( 1 << irq );
	134	pic8259->irr |= 1 << irq;
142	135	}
143	136	else
144	137	{
r11629	r11630
146	139	if (LOG_GENERAL)
147	140	logerror("pic8259_set_irq_line(): PIC cleared IRQ line #%d\n", irq);
148	141
149		pic8259->irq_lines &= ~(1 << irq);
	142	pic8259->irr &= ~(1 << irq);
150	143	}
151	144
152		pic8259->irr = ( pic8259->level_trig_mode ) ? pic8259->esr & pic8259->irq_lines : pic8259->irq_lines;
153	145	pic8259_set_timer(pic8259);
154	146	}
155	147
r11629	r11630
177	169	{
178	170	if (LOG_GENERAL)
179	171	logerror("pic8259_acknowledge(): PIC acknowledge IRQ #%d\n", irq);
180		pic8259->irr &= ~mask;
181		pic8259->esr &= ~mask;
	172	if (!pic8259->level_trig_mode)
	173	pic8259->irr &= ~mask;
182	174
183	175	if (!pic8259->auto_eoi)
184	176	pic8259->isr |= mask;
	177
185	178	pic8259_set_timer(pic8259);
186	179
187	180	if ((pic8259->cascade!=0) && (pic8259->master!=0) && (mask & pic8259->slave)) {
r11629	r11630
272	265	logerror("pic8259_w(): ICW1; data=0x%02X\n", data);
273	266
274	267	pic8259->imr            = 0x00;
275		pic8259->esr            = 0x00;
276	268	pic8259->isr            = 0x00;
277	269	pic8259->irr            = 0x00;
278	270	pic8259->level_trig_mode   = (data & 0x08) ? 1 : 0;
r11629	r11630
281	273	pic8259->icw4_needed      = (data & 0x01) ? 1 : 0;
282	274	pic8259->vector_addr_low   = (data & 0xe0);
283	275	pic8259->state         = STATE_ICW2;
284		pic8259->irq_lines          = 0x00;
285	276	}
286	277	else if (pic8259->state == STATE_READY)
287	278	{
r11629	r11630
430	421	pic8259_t   *pic8259 = get_safe_token(device);
431	422
432	423	pic8259->state = STATE_READY;
433		pic8259->irq_lines = 0;
434	424	pic8259->isr = 0;
435		pic8259->esr = 0;
436	425	pic8259->irr = 0;
437	426	pic8259->prio = 0;
438	427	pic8259->imr = 0;

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