src/mess/machine/8530scc.c
| r11207 | r11208 | |
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| 15 | 15 | PARAMETERS |
| 16 | 16 | ***************************************************************************/ |
| 17 | 17 | |
| 18 | | #define LOG_SCC 0 |
| 18 | #define LOG_SCC (0) |
| 19 | 19 | |
| 20 | 20 | |
| 21 | 21 | |
| r11207 | r11208 | |
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| 196 | 196 | scc8530_t *scc = get_token(device); |
| 197 | 197 | sccChan *pChan = &scc->channel[param]; |
| 198 | 198 | int brconst = pChan->reg_val[13]<<8 | pChan->reg_val[14]; |
| 199 | | int rate = scc->clock / brconst; |
| 199 | int rate |
| 200 | 200 | |
| 201 | if (brconst) |
| 202 | { |
| 203 | rate = scc->clock / brconst; |
| 204 | } |
| 205 | else |
| 206 | { |
| 207 | rate = 0; |
| 208 | } |
| 209 | |
| 201 | 210 | // is baud counter IRQ enabled on this channel? |
| 202 | 211 | // always flag pending in case it's enabled after this |
| 203 | 212 | pChan->baudIRQPending = 1; |
| r11207 | r11208 | |
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| 212 | 221 | } |
| 213 | 222 | |
| 214 | 223 | // reset timer according to current register values |
| 215 | | pChan->baudtimer->adjust(attotime::from_hz(rate), param, attotime::from_hz(rate)); |
| 224 | if (rate) |
| 225 | { |
| 226 | pChan->baudtimer->adjust(attotime::from_hz(rate), param, attotime::from_hz(rate)); |
| 227 | } |
| 228 | else |
| 229 | { |
| 230 | pChan->baudtimer->adjust(attotime::never, param, attotime::never); |
| 231 | } |
| 216 | 232 | } |
| 217 | 233 | |
| 218 | 234 | /*------------------------------------------------- |
| r11207 | r11208 | |
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| 679 | 695 | } |
| 680 | 696 | |
| 681 | 697 | DEFINE_LEGACY_DEVICE(SCC8530, scc8530); |
| 698 | |
| 699 | /* |
| 700 | |
| 701 | AppleTalk check: |
| 702 | |
| 703 | SCC: port B reg 9 write 0x40 Channel Reset B |
| 704 | SCC: port B reg 4 write 0x20 SDLC mode |
| 705 | SCC: port B reg 10 write 0xe0 CRC preset + FM0 |
| 706 | SCC: port B reg 6 write 0x00 SDLC address |
| 707 | SCC: port B reg 7 write 0x7e SDLC flag |
| 708 | SCC: port B reg 12 write 0x06 baud rate low |
| 709 | SCC: port B reg 13 write 0x00 baud rate high |
| 710 | SCC: port B reg 14 write 0xc0 Set FM mode |
| 711 | SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable |
| 712 | SCC: port B reg 2 write 0x00 interrupt vector 0 |
| 713 | SCC: port B reg 15 write 0x08 DCD interrupt enable |
| 714 | SCC: port B reg 1 write 0x09 Rx IRQ on first char or special, ext int enable |
| 715 | SCC: port B reg 9 write 0x0a Master IRQ enable, no-vector mode |
| 716 | SCC: port B reg 11 write 0x70 Rx clock = DPLL output, Tx clock = BR generator |
| 717 | SCC: port B reg 14 write 0x21 Enter search mode, BR generator enable |
| 718 | SCC: port B reg 5 write 0x60 Tx 8 bits/char |
| 719 | SCC: port B reg 6 write 0x2a SDLC address |
| 720 | SCC: port B reg 0 read 0x00 |
| 721 | SCC: port B reg 15 write 0x88 DCD interrupt enable, break/abort interrupt enable |
| 722 | |
| 723 | (repeats) |
| 724 | SCC: port B reg 1 read 0x09 |
| 725 | SCC: port B reg 3 write 0xd0 |
| 726 | SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable |
| 727 | SCC: port B reg 15 write 0x08 DCD interrupt enable |
| 728 | SCC: port B reg 0 read 0x00 |
| 729 | SCC: port B reg 15 write 0x88 |
| 730 | |
| 731 | System 7: |
| 732 | |
| 733 | SCC: port B reg 9 write 0x40 Channel Reset B |
| 734 | SCC: port B reg 4 write 0x20 SDLC mode |
| 735 | SCC: port B reg 10 write 0xe0 CRC preset + FM0 |
| 736 | SCC: port B reg 6 write 0x00 SDLC address |
| 737 | SCC: port B reg 7 write 0x7e SDLC flag |
| 738 | SCC: port B reg 12 write 0x06 baud rate low |
| 739 | SCC: port B reg 13 write 0x00 baud rate high |
| 740 | SCC: port B reg 14 write 0xc0 Set FM mode |
| 741 | SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable |
| 742 | SCC: port B reg 2 write 0x00 interrupt vector 0 |
| 743 | SCC: port B reg 15 write 0x08 DCD interrupt enable |
| 744 | SCC: port B reg 1 write 0x09 Rx IRQ on first char or special, ext int enable |
| 745 | SCC: port B reg 9 write 0x0a Master IRQ enable, no-vector mode |
| 746 | SCC: port B reg 11 write 0x70 Rx clock = DPLL output, Tx clock = BR generator |
| 747 | SCC: port B reg 14 write 0x21 Enter search mode, BR generator enable |
| 748 | SCC: port B reg 5 write 0x60 Tx 8 bits/char |
| 749 | SCC: port B reg 6 write 0x01 SDLC address |
| 750 | SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable |
| 751 | |
| 752 | (repeats) |
| 753 | |
| 754 | SCC: port B reg 0 read 0x00 |
| 755 | SCC: port B reg 15 write 0x88 DCD interrupt enable, break/abort interrupt enable |
| 756 | SCC: port B reg 15 write 0x08 DCD interrupt enable |
| 757 | SCC: port B reg 1 read 0x09 Rx IRQ on first char or special, ext int enable |
| 758 | SCC: port B reg 3 write 0xdd Rx 8 bits, enter hunt mode, CRC enable, address search mode, Rx enable |
| 759 | |
| 760 | */ |