MESS SVN History

15994 Revisions

r1104 Friday 12th October, 2007 at 12:34:59 UTC by Nathan Woods
Updated to 0.119u4 core

[docs]	messnew.txt
[src/emu/cpu]	x64drc.c
[src/emu/cpu/i386]	i386.c i386.h i386ops.c
[src/emu/cpu/i8051]	i8051.c i8051.h
[src/emu/cpu/m6805]	m6805.c
[src/emu/cpu/mb86233]	mb86233.c
[src/emu/cpu/mips]	mdrc64.c mips3drc.c
[src/emu/cpu/z80gb]	opc_main.h
[src/emu/sound]	scsp.c
[src/mame]	mame.mak mamedriv.c
[src/mame/audio]	vicdual.c
[src/mame/drivers]	bnstars.c bublbobl.c cabal.c ddenlovr.c dec8.c dynax.c finalizr.c gijoe.c gpworld.c* gtipoker.c* halleys.c hayaosi1.c* igs_180.c iqblock.c itech32.c jack.c jongkyo.c kyugo.c metro.c mirage.c mitchell.c ms32.c pacman.c parodius.c peplus.c* playch10.c rastan.c seattle.c segas16a.c seibuspi.c srmp2.c srmp6.c tetriunk.c tmnt.c vegas.c zaxxon.c
[src/mame/includes]	dynax.h
[src/mame/machine]	6840ptm.c fd1094.c idectrl.c
[src/mame/video]	dynax.c ms32.c namcos22.c raiden.c segaic16.c tmnt.c vooddefs.h voodoo.c
[src/mess/audio]	pc.h
[src/osd]	osdcore.h
[src/osd/windows]	windows.mak winwork.c

src/mame/audio/vicdual.c
r1103	r1104
221	221
222	222	static const discrete_mixer_desc headon_mixer =
223	223	{DISC_MIXER_IS_RESISTOR,
224		{RES_K(130), RES_K(130), RES_K(100), RES_K(100), RES_K(100), RES_K(100)}, // 130 = 390/3, Bonus Res is dummy
	224	{RES_K(130), RES_K(130), RES_K(100), RES_K(100), RES_K(100), RES_K(10)}, // 130 = 390/3, Bonus Res is dummy
225	225	{0,0,0,0,0}, // no variable resistors
226	226	{0,0,0,0,CAP_N(470),0},
227	227	0, RES_K(100),
r1103	r1104
231	231
232	232	static const discrete_mixer_desc headon_crash_mixer =
233	233	{DISC_MIXER_IS_OP_AMP,
234		{RES_K(50), RES_K(50)}, // Resistors, in fact variable resistors (100k)
	234	{RES_K(50), RES_K(10)}, // Resistors, in fact variable resistors (100k)
235	235	{0,0,0,0,0}, // no variable resistors
236	236	{CAP_N(100),CAP_U(1)},
237	237	0, RES_K(100),
r1103	r1104
404	404	DISCRETE_LOGIC_INVERT(NODE_80, 1, HEADON_CRASH_EN)
405	405	DISCRETE_555_MSTABLE(NODE_81, 1, NODE_80, RES_K(470), CAP_U(1), &headon_555_crash)
406	406	// Mix with noise
407		DISCRETE_MULTIPLY(NODE_85, 1, NODE_81, NODE_51)
	407	DISCRETE_MULTIPLY(NODE_84, 1, NODE_81, NODE_51)
	408	// Taken from simulation
	409	// Center frequency is 500 Hz
	410	// roughly 6db per octave
	411	DISCRETE_FILTER1(NODE_85, 1, NODE_84, 500, DISC_FILTER_BANDPASS)
408	412
	413
409	414	DISCRETE_555_MSTABLE(NODE_86, 1, NODE_80, RES_K(470), CAP_U(2.2), &headon_555_crash)
410	415	// Mix with noise
411	416	DISCRETE_MULTIPLY(NODE_87, 1, NODE_86, NODE_51)
	417	// Sallen Key filter ...
	418	// http://www.t-linespeakers.org/tech/filters/Sallen-Key.html
	419	// f = w / 2 / pi = 1 / ( 2 * pi * 15ksqrt(470n47n)) = 71 Hz
	420	// Q = 1/2 * sqrt(470n/47n)= 1.58
	421	DISCRETE_FILTER2(NODE_88, 1, NODE_87, 71, (1.0/1.58), DISC_FILTER_LOWPASS)
412	422
413		DISCRETE_MIXER2(NODE_89, 1, NODE_85, NODE_87, &headon_crash_mixer)
414		DISCRETE_TRANSFORM2(HEADON_CRASH_OUT, 1, NODE_89, 12, "01/")
	423	DISCRETE_MIXER2(NODE_95, 1, NODE_85, NODE_88, &headon_crash_mixer)
	424	DISCRETE_TRANSFORM2(HEADON_CRASH_OUT, 1, NODE_95, 12, "01/")
415	425
416	426	/************************************************
417	427	* Mixer Stage
r1103	r1104
420	430	DISCRETE_MIXER6(NODE_210, 1, HEADON_PLAYER_CAR_OUT, HEADON_COMP_CAR_OUT,
421	431	HEADON_SCREECH1_OUT, HEADON_SCREECH2_OUT,
422	432	HEADON_BONUS_OUT, HEADON_CRASH_OUT, &headon_mixer)
423		~~//DISCRETE_OUTPUT(NODE_73, 1000)~~
	433
424	434	DISCRETE_OUTPUT(NODE_210, 37000.0 / 12.0)
425	435	//DISCRETE_CSVLOG3(HEADON_CRASH_EN,NODE_81,NODE_80)
426	436

src/mame/machine/idectrl.c
r1103	r1104
565	565
566	566	for (i = 0; i < field_size_in_words * 2 && src[i]; i++)
567	567	dst[i ^ 1] = src[i];
568		for ( ; i < field_size_in_words; i++)
	568	for ( ; i < field_size_in_words * 2; i++)
569	569	dst[i ^ 1] = ' ';
570	570	}
571	571

src/mame/machine/fd1094.c
r1103	r1104
211	211	0096 21 80 11 21 881121 ddux 1988 88/11/21
212	212	0102 AB 80 02 03 04588A wrestwa2 1989 atypical
213	213	0058-04B 27 03 27 14 032714 crkdownj 1989 89/03/27 14:xx
214		0058-04C 19 03 27 05 032705 ??????? 1989 89/03/27 05:xx
215		0058-04D DC 03 27 06 032706 crkdown 1989 89/03/27 06:xx
	214	0058-04C 19 03 27 05 032705 crkdown 1989 89/03/27 05:xx
	215	0058-04D DC 03 27 06 032706 crkdownu 1989 89/03/27 06:xx
216	216	0110 19 81 03 29 032916 goldnax1 1989 89/03/29 16:xx
217	217	0115 12 04 05 11 040511 bayroutj 1989 89/04/05 11:xx
218	218	0116 11 03 30 09 033009 bayroute 1989 89/03/30 09:xx

src/mame/machine/6840ptm.c
r1103	r1104
496	496	{
497	497	idx = (offset == 1) ? 1 : (currptr->control_reg[1] & 0x01) ? 0 : 2;
498	498	diffs = data ^ currptr->control_reg[idx];
499		currptr->t3_divisor = (currptr->control_reg[3] & 0x01) ? 8 : 1;
	499	currptr->t3_divisor = (currptr->control_reg[2] & 0x01) ? 8 : 1;
500	500	currptr->mode[idx] = (data>>3)&0x07;
501	501	currptr->control_reg[idx] = data;
502	502

src/mame/mamedriv.c
r1103	r1104
1613	1613	DRIVER( bublbobr ) /* A78 (c) 1986 Taito America Corporation + Romstar license */
1614	1614	DRIVER( bubbobr1 ) /* A78 (c) 1986 Taito America Corporation + Romstar license */
1615	1615	DRIVER( boblbobl ) /* bootleg */
	1616	DRIVER( sboblboa ) /* bootleg */
1616	1617	DRIVER( sboblbob ) /* bootleg */
1617	1618	DRIVER( bub68705 ) /* bootleg */
1618	1619	DRIVER( missb2 ) /* bootleg on enhanced hardware */
r1103	r1104
2194	2195	DRIVER( fx ) /* bootleg */
2195	2196	DRIVER( legend ) /* no copyright notice [1986 Sega/Coreland?] */
2196	2197	DRIVER( airwolf ) /* (c) 1987 Kyugo */
	2198	DRIVER( airwolfa ) /* (c) 1987 Kyugo */
2197	2199	DRIVER( skywolf ) /* bootleg */
2198	2200	DRIVER( skywolf2 ) /* bootleg */
2199	2201
r1103	r1104
2972	2974	DRIVER( pang ) /* (c) 1989 Mitchell (World) */
2973	2975	DRIVER( pangb ) /* bootleg */
2974	2976	DRIVER( pangbold ) /* bootleg */
	2977	DRIVER( pangba ) /* bootleg */
2975	2978	DRIVER( bbros ) /* (c) 1989 Capcom (US) not listed on Capcom's site */
2976	2979	DRIVER( pompingw ) /* (c) 1989 Mitchell (Japan) */
2977	2980	DRIVER( cbasebal ) /* 10/1989 (c) 1989 Capcom (Japan) (different hardware) */
r1103	r1104
3069	3072	DRIVER( gt97s121 ) /* (c) 1997 Incredible Technologies */
3070	3073	DRIVER( gt97v120 ) /* (c) 1997 Incredible Technologies */
3071	3074	DRIVER( gt97t240 ) /* (c) 1997 Incredible Technologies */
	3075	DRIVER( gt97t243 ) /* (c) 1997 Incredible Technologies */
3072	3076	DRIVER( gt98 ) /* (c) 1998 Incredible Technologies */
3073	3077	DRIVER( gt98v100 ) /* (c) 1998 Incredible Technologies */
3074	3078	DRIVER( gt98s100 ) /* (c) 1998 Incredible Technologies */
r1103	r1104
3213	3217	DRIVER( galaxyrp ) /* (c) 1983 */
3214	3218	DRIVER( sblazerp ) /* (c) 1983 */
3215	3219	DRIVER( cobraseg ) /* (c) ???? */
	3220	DRIVER( gpworld ) /* (c) 1984 */
3216	3221
3217	3222	/* Sega SG1000 based games */
3218	3223	DRIVER( chboxing ) /* (c) 1984 */
r1103	r1104
3332	3337	DRIVER( shangupb ) /* (c) 1992 (but bootleg, hangon hw?) */
3333	3338
3334	3339	/* Pre-16 */
3335		DRIVER( aliensy1 ) /* (c) 1987 (FD1094, decrypted) */
3336		DRIVER( aliensy2 ) /* (c) 1987 (FD1094, decrypted) */
	3340	DRIVER( aliensy1 ) /* (c) 1987 (FD1089A, decrypted) */
	3341	DRIVER( aliensy2 ) /* (c) 1987 (FD1089A, decrypted) */
	3342	DRIVER( aliensy5 ) /* (c) 1987 (FD1089B) */
3337	3343	DRIVER( bodyslam ) /* (c) 1986 (8751) */
3338	3344	DRIVER( dumpmtmt ) /* (c) 1986 (Japan) */
3339	3345	DRIVER( mjleague ) /* (c) 1985 */
r1103	r1104
5872	5878	DRIVER( kakumei2 ) /* (c) 1992 */
5873	5879	DRIVER( suchipi ) /* (c) 1993 */
5874	5880
	5881	DRIVER( hayaosi1 ) /* (c) 1991? */
	5882
5875	5883	/* NMK Double Dealer, Similar Hardware to Jaleco Mahjong games above */
5876	5884	DRIVER( ddealer ) /* (c) 1991 NMK */
5877	5885
r1103	r1104
6280	6288	DRIVER( cybattlr ) /* (c) 1993 */
6281	6289	DRIVER( peekaboo ) /* (c) 1993 */
6282	6290
6283		/* Jaleco Mega System 1 games */
6284		DRIVER( hayaosi1 ) /* (c) 1994 */
	6291	/* Jaleco Mega System 32 games */
	6292	DRIVER( hayaosi2 ) /* (c) 1993 */
	6293	DRIVER( hayaosi3 ) /* (c) 1994 */
6285	6294	DRIVER( bbbxing ) /* (c) 1994 */
6286	6295	DRIVER( 47pie2 ) /* (c) 1994 */
6287	6296	DRIVER( 47pie2o ) /* (c) 1994 */
r1103	r1104
6859	6868	DRIVER( lastforg ) /* (c) 1994 */
6860	6869	DRIVER( toride2g ) /* (c) 1994 */
6861	6870	DRIVER( torid2gg ) /* (c) 1994 */
	6871	DRIVER( toride2j ) /* (c) 1994 */
6862	6872	DRIVER( gunmast ) /* (c) 1994 */
6863	6873	DRIVER( daitorid ) /* (c) 1995 */
6864	6874	DRIVER( dokyusei ) /* (c) 1995 Make Software / Elf / Media Trading */
r1103	r1104
6999	7009	DRIVER( tenkaicb ) /* 1991 Dynax */
7000	7010	DRIVER( tenkaid ) /* 1991 Dynax */
7001	7011	DRIVER( tenkaie ) /* 1991 Dynax */
	7012	DRIVER( htengoku ) /* 1992 Dynax */
7002	7013	DRIVER( mjreach ) /* 1994 Dynax */
7003	7014	DRIVER( mjdialq2 ) /* "52" (c) 1991 Dynax */
7004	7015	DRIVER( yarunara ) /* "55" Mahjong Yarunara 1991 Dynax */
r1103	r1104
7042	7053	DRIVER( pkgnsh ) /* "505" Pachinko Gindama Shoubu 1998 (Japan) */
7043	7054	DRIVER( pkgnshdx ) /* "522" Pachinko Gindama Shoubu DX 1998 (Japan) */
7044	7055
	7056	DRIVER( hjingi ) /* "???" */
	7057	DRIVER( hanayara ) /* "???" */
7045	7058	DRIVER( mjelctrn ) /* "???" Mahjong Electron Base parts 2 & 4 */
7046	7059	DRIVER( mjelct3 ) /* "???" Mahjong Electron Base parts 2 & 3 */
7047	7060	DRIVER( mjelct3a ) /* "???" Mahjong Electron Base parts 2 & 3 */
r1103	r1104
7066	7079	DRIVER( iqblock ) /* (c) 1993 */
7067	7080	DRIVER( grndtour ) /* (c) 1993 */
7068	7081	DRIVER( cabaret )
	7082	DRIVER( pokerigs ) /* (c) 1995 */
7069	7083	DRIVER( lhb ) /* (c) 1995 */
7070	7084	DRIVER( lhba ) /* (c) 1995 */
7071	7085	DRIVER( dbc ) /* (c) 199? */
r1103	r1104
7794	7808	DRIVER( esha ) /* (c) 1984 Funai / Gakken */
7795	7809	DRIVER( eshb ) /* (c) 1984 Funai / Gakken */
7796	7810	DRIVER( comebaby ) /* (c) 2000 ExPotato */
	7811	DRIVER( peplus ) /* (c) 1987 IGT - International Gaming Technology */
7797	7812	DRIVER( mirage ) /* (c) 1994 Mitchell */
7798	7813	DRIVER( dominob ) /* (c) 1990 Wonwoo Systems */
7799	7814	DRIVER( jongkyo ) /* (c) 1985 Kiwako */
	7815	DRIVER( gtipoker ) /* (c) 1983 GTI Inc */
7800	7816
7801	7817	#endif /* DRIVER_RECURSIVE */

src/mame/includes/dynax.h
r1103	r1104
4	4
5	5	***************************************************************************/
6	6
7		/----------- defined in drivers/dynax.c -----------/
	7	//----------- defined in drivers/dynax.c -----------
8	8
9	9	extern UINT8 dynax_blitter_irq, dynax_blitter2_irq;
10	10
r1103	r1104
13	13	void mjelctrn_update_irq(void);
14	14	void neruton_update_irq(void);
15	15
16		/----------- defined in video/dynax.c -----------/
	16	//----------- defined in video/dynax.c -----------
17	17
18	18	WRITE8_HANDLER( dynax_blitter_rev2_w );
19	19	WRITE8_HANDLER( jantouki_blitter_rev2_w );
20	20	WRITE8_HANDLER( jantouki_blitter2_rev2_w );
21	21	WRITE8_HANDLER( tenkai_blitter_rev2_w );
22	22
23
24	23	WRITE8_HANDLER( dynax_blit_pen_w );
25	24	WRITE8_HANDLER( dynax_blit2_pen_w );
26	25	WRITE8_HANDLER( dynax_blit_backpen_w );
r1103	r1104
62	61	VIDEO_START( jantouki );
63	62	VIDEO_START( mjelctrn );
64	63	VIDEO_START( neruton );
	64	VIDEO_START( htengoku );
65	65
66	66	VIDEO_UPDATE( hanamai );
67	67	VIDEO_UPDATE( hnoridur );
68	68	VIDEO_UPDATE( sprtmtch );
69	69	VIDEO_UPDATE( mjdialq2 );
70	70	VIDEO_UPDATE( jantouki );
	71	VIDEO_EOF( htengoku );
71	72
72	73	PALETTE_INIT( sprtmtch );
	74
	75
	76	//----------- defined in drivers/ddenlovr.c -----------
	77
	78	WRITE8_HANDLER( ddenlovr_bgcolor_w );
	79	WRITE8_HANDLER( ddenlovr_bgcolor2_w );
	80	WRITE16_HANDLER( ddenlovr16_bgcolor_w );
	81
	82	WRITE8_HANDLER( ddenlovr_priority_w );
	83	WRITE8_HANDLER( ddenlovr_priority2_w );
	84	WRITE16_HANDLER( ddenlovr16_priority_w );
	85
	86	WRITE8_HANDLER( ddenlovr_layer_enable_w );
	87	WRITE8_HANDLER( ddenlovr_layer_enable2_w );
	88	WRITE16_HANDLER( ddenlovr16_layer_enable_w );
	89
	90	WRITE8_HANDLER( ddenlovr_palette_base_w );
	91	WRITE8_HANDLER( ddenlovr_palette_base2_w );
	92	WRITE16_HANDLER( ddenlovr16_palette_base_w );
	93
	94	WRITE8_HANDLER( ddenlovr_palette_mask_w );
	95	WRITE8_HANDLER( ddenlovr_palette_mask2_w );
	96	WRITE16_HANDLER( ddenlovr16_palette_mask_w );
	97
	98	WRITE8_HANDLER( ddenlovr_transparency_pen_w );
	99	WRITE8_HANDLER( ddenlovr_transparency_pen2_w );
	100	WRITE16_HANDLER( ddenlovr16_transparency_pen_w );
	101
	102	WRITE8_HANDLER( ddenlovr_transparency_mask_w );
	103	WRITE8_HANDLER( ddenlovr_transparency_mask2_w );
	104	WRITE16_HANDLER( ddenlovr16_transparency_mask_w );
	105
	106	extern UINT8 *ddenlovr_pixmap[8];
	107
	108	VIDEO_START(ddenlovr);
	109	VIDEO_UPDATE(ddenlovr);
	110	VIDEO_EOF(ddenlovr);
	111

src/mame/mame.mak
r1103	r1104
825	825	$(DRIVERS)/fcombat.o $(VIDEO)/fcombat.o \
826	826	$(DRIVERS)/ginganin.o $(VIDEO)/ginganin.o \
827	827	$(DRIVERS)/homerun.o $(VIDEO)/homerun.o \
	828	$(DRIVERS)/hayaosi1.o \
828	829	$(DRIVERS)/megasys1.o $(VIDEO)/megasys1.o \
829	830	$(DRIVERS)/momoko.o $(VIDEO)/momoko.o \
830	831	$(DRIVERS)/ms32.o $(VIDEO)/ms32.o \
r1103	r1104
1171	1172	$(DRIVERS)/deniam.o $(VIDEO)/deniam.o \
1172	1173	$(DRIVERS)/dotrikun.o $(VIDEO)/dotrikun.o \
1173	1174	$(DRIVERS)/genesis.o $(VIDEO)/genesis.o \
	1175	$(DRIVERS)/gpworld.o \
1174	1176	$(DRIVERS)/hshavoc.o \
1175	1177	$(DRIVERS)/kopunch.o $(VIDEO)/kopunch.o \
1176	1178	$(DRIVERS)/megadriv.o \
r1103	r1104
1571	1573	$(DRIVERS)/freekick.o $(VIDEO)/freekick.o \
1572	1574	$(DRIVERS)/funworld.o $(VIDEO)/funworld.o \
1573	1575	$(DRIVERS)/gdrawpkr.o $(VIDEO)/gdrawpkr.o \
	1576	$(DRIVERS)/gtipoker.o \
1574	1577	$(DRIVERS)/go2000.o \
1575	1578	$(DRIVERS)/good.o \
1576	1579	$(DRIVERS)/gotcha.o $(VIDEO)/gotcha.o \
r1103	r1104
1616	1619	$(DRIVERS)/pangofun.o \
1617	1620	$(DRIVERS)/pasha2.o \
1618	1621	$(DRIVERS)/pass.o $(VIDEO)/pass.o \
	1622	$(DRIVERS)/peplus.o \
1619	1623	$(DRIVERS)/pipeline.o \
1620	1624	$(DRIVERS)/pkscram.o \
1621	1625	$(DRIVERS)/pmpoker.o \
r1103	r1104
1658	1662	$(DRIVERS)/vroulet.o \
1659	1663	$(DRIVERS)/wldarrow.o \
1660	1664	$(DRIVERS)/xyonix.o $(VIDEO)/xyonix.o \
	1665	$(DRIVERS)/hayaosi1.o
1661	1666
1662	1667
1663	1668	#-------------------------------------------------

src/mame/video/voodoo.c
r1103	r1104
165	165
166	166
167	167
	168
168	169	/*************************************
169	170	*
170	171	* Statics
r1103	r1104
207	208	static UINT32 banshee_rom_r(voodoo_state *v, offs_t offset, UINT32 mem_mask);
208	209
209	210	/* work item management */
210		static void work_item_enqueue(voodoo_state *v);
	211	static void work_item_enqueue(voodoo_state v, work_info work, int numitems);
211	212	static void work_item_wait(voodoo_state *v);
212	213	static void work_item_callback(void param);
213	214
r1103	r1104
228	229	static void dump_rasterizer_stats(voodoo_state *v);
229	230
230	231	/* generic rasterizers */
231		static void raster_fastfill(voodoo_state *v, INT32 scanline);
232		static void raster_generic_0tmu(voodoo_state *v, INT32 y);
233		static void raster_generic_1tmu(voodoo_state *v, INT32 y);
234		static void raster_generic_2tmu(voodoo_state *v, INT32 y);
	232	static void raster_fastfill(work_info *work, INT32 scanline, INT32 startx, INT32 stopx);
	233	static void raster_generic_0tmu(work_info *work, INT32 y, INT32 startx, INT32 stopx);
	234	static void raster_generic_1tmu(work_info *work, INT32 y, INT32 startx, INT32 stopx);
	235	static void raster_generic_2tmu(work_info *work, INT32 y, INT32 startx, INT32 stopx);
235	236
236	237
237	238
r1103	r1104
287	288	voodoo[which] = v;
288	289
289	290	/* create a multiprocessor work queue */
290		v->work.queue = osd_work_queue_alloc(WORK_QUEUE_FLAG_MULTI);
	291	v->work_queue = osd_work_queue_alloc(WORK_QUEUE_FLAG_MULTI);
291	292
292	293	/* create a table of precomputed 1/n and log2(n) values */
293	294	/* n ranges from 1.0000 to 2.0000 */
r1103	r1104
423	424	void voodoo_exit(int which)
424	425	{
425	426	/* release the work queue, ensuring all work is finished */
426		if (voodoo[which] != NULL && voodoo[which]->work.queue != NULL)
427		osd_work_queue_free(voodoo[which]->work.queue);
	427	if (voodoo[which] != NULL && voodoo[which]->work_queue != NULL)
	428	osd_work_queue_free(voodoo[which]->work_queue);
428	429	}
429	430
430	431
r1103	r1104
2183	2184	}
2184	2185
2185	2186	/* wait for any outstanding work to finish */
2186		work_item_wait(v);
	2187	if (regnum < vertexAx \|\| regnum > fdWdY)
	2188	work_item_wait(v);
2187	2189
2188	2190	/* switch off the register */
2189	2191	switch (regnum)
r1103	r1104
2856	2858	int x, y, scry, mask;
2857	2859	int pixel, destbuf;
2858	2860
2859		/* wait for any outstanding work to finish */
2860		work_item_wait(v);
2861
2862	2861	/* statistics */
2863	2862	v->stats.lfb_writes++;
2864	2863
r1103	r1104
3082	3081	depth = v->fbi.aux;
3083	3082	depthmax = v->fbi.auxmax;
3084	3083
	3084	/* wait for any outstanding work to finish */
	3085	work_item_wait(v);
	3086
3085	3087	/* simple case: no pipeline */
3086	3088	if (!LFBMODE_ENABLE_PIXEL_PIPELINE(v->reg[lfbMode].u))
3087	3089	{
r1103	r1104
3202	3204	int tmunum = (offset >> 19) & 0x03;
3203	3205	tmu_state *t;
3204	3206
3205		/* wait for any outstanding work to finish */
3206		work_item_wait(v);
3207
3208	3207	/* statistics */
3209	3208	v->stats.tex_writes++;
3210	3209
r1103	r1104
3216	3215	if (TEXLOD_TDIRECT_WRITE(t->reg[tLOD].u))
3217	3216	fatalerror("Texture direct write!");
3218	3217
	3218	/* wait for any outstanding work to finish */
	3219	work_item_wait(v);
	3220
3219	3221	/* update texture info if dirty */
3220	3222	if (t->regdirty)
3221	3223	recompute_texture_params(t);
r1103	r1104
3811	3813	UINT32 data;
3812	3814	int x, y, scry, destbuf;
3813	3815
3814		/* wait for any outstanding work to finish */
3815		work_item_wait(v);
3816
3817	3816	/* statistics */
3818	3817	v->stats.lfb_reads++;
3819	3818
r1103	r1104
3856	3855	if (bufoffs >= bufmax)
3857	3856	return 0xffffffff;
3858	3857
	3858	/* wait for any outstanding work to finish */
	3859	work_item_wait(v);
	3860
3859	3861	/* compute the data */
3860	3862	data = buffer[bufoffs + 0] \| (buffer[bufoffs + 1] << 16);
3861	3863
r1103	r1104
4459	4461	remembering starting statistics
4460	4462	-------------------------------------------------*/
4461	4463
4462		static void work_item_enqueue(voodoo_state *v)
	4464	static void work_item_enqueue(voodoo_state v, work_info work, int numitems)
4463	4465	{
4464	4466	/* remember the starting statistics values */
4465		v->work.start_pixels_in = v->reg[fbiPixelsIn].u;
4466		v->work.start_pixels_out = v->reg[fbiPixelsOut].u;
4467		v->work.start_chroma_fail = v->reg[fbiChromaFail].u;
4468		v->work.start_zfunc_fail = v->reg[fbiZfuncFail].u;
4469		v->work.start_afunc_fail = v->reg[fbiAfuncFail].u;
	4467	work->start_pixels_in = v->reg[fbiPixelsIn].u;
	4468	work->start_pixels_out = v->reg[fbiPixelsOut].u;
	4469	work->start_chroma_fail = v->reg[fbiChromaFail].u;
	4470	work->start_zfunc_fail = v->reg[fbiZfuncFail].u;
	4471	work->start_afunc_fail = v->reg[fbiAfuncFail].u;
4470	4472
	4473	/* set the state */
	4474	work->state = v;
	4475
4471	4476	/* enqueue the work item */
4472		osd_work_item_queue(v->work.queue, work_item_callback, &v->work, WORK_ITEM_FLAG_AUTO_RELEASE ~~\| WORK_ITEM_FLAG_SHARED~~);
	4477	osd_work_item_queue_multiple(v->work_queue, work_item_callback, numitems, work->unit, sizeof(*work->unit), WORK_ITEM_FLAG_AUTO_RELEASE);
4473	4478	}
4474	4479
4475	4480
r1103	r1104
4480	4485
4481	4486	static void work_item_wait(voodoo_state *v)
4482	4487	{
	4488	work_info *work = &v->work;
	4489
4483	4490	/* wait for the work item to complete */
4484		osd_work_queue_wait(v->work.queue, osd_ticks_per_second());
	4491	osd_work_queue_wait(v->work_queue, osd_ticks_per_second());
4485	4492
4486	4493	/* update our global stats based on the results */
4487		v->stats.total_pixels_in += v->reg[fbiPixelsIn].u - v->work.start_pixels_in;
4488		v->stats.total_pixels_out += v->reg[fbiPixelsOut].u - v->work.start_pixels_out;
4489		v->stats.total_chroma_fail += v->reg[fbiChromaFail].u - v->work.start_chroma_fail;
4490		v->stats.total_zfunc_fail += v->reg[fbiZfuncFail].u - v->work.start_zfunc_fail;
4491		v->stats.total_afunc_fail += v->reg[fbiAfuncFail].u - v->work.start_afunc_fail;
4492		if (v->work.info != NULL)
4493		v->work.info->hits += v->reg[fbiPixelsIn].u - v->work.start_pixels_in;
	4494	v->stats.total_pixels_in += v->reg[fbiPixelsIn].u - work->start_pixels_in;
	4495	v->stats.total_pixels_out += v->reg[fbiPixelsOut].u - work->start_pixels_out;
	4496	v->stats.total_chroma_fail += v->reg[fbiChromaFail].u - work->start_chroma_fail;
	4497	v->stats.total_zfunc_fail += v->reg[fbiZfuncFail].u - work->start_zfunc_fail;
	4498	v->stats.total_afunc_fail += v->reg[fbiAfuncFail].u - work->start_afunc_fail;
	4499	if (work->info != NULL)
	4500	work->info->hits += v->reg[fbiPixelsIn].u - work->start_pixels_in;
4494	4501
4495	4502	/* remember the starting statistics values */
4496		v->work.start_pixels_in = v->reg[fbiPixelsIn].u;
4497		v->work.start_pixels_out = v->reg[fbiPixelsOut].u;
4498		v->work.start_chroma_fail = v->reg[fbiChromaFail].u;
4499		v->work.start_zfunc_fail = v->reg[fbiZfuncFail].u;
4500		v->work.start_afunc_fail = v->reg[fbiAfuncFail].u;
	4503	work->start_pixels_in = v->reg[fbiPixelsIn].u;
	4504	work->start_pixels_out = v->reg[fbiPixelsOut].u;
	4505	work->start_chroma_fail = v->reg[fbiChromaFail].u;
	4506	work->start_zfunc_fail = v->reg[fbiZfuncFail].u;
	4507	work->start_afunc_fail = v->reg[fbiAfuncFail].u;
4501	4508	}
4502	4509
4503	4510
r1103	r1104
4509	4516
4510	4517	static void work_item_callback(void param)
4511	4518	{
4512		/* recover the state pointer and scanline from the param */
4513		work_info *work = param;
4514		voodoo_state *v = work->state;
	4519	work_unit *unit = param;
	4520	work_info *work = unit->work;
	4521	int extnum;
4515	4522
4516		/* render the scanlines and return */
4517		while (1)
4518		{
4519		int scanline = osd_sync_add(&work->curscanline, 1) - 1;
4520
4521		/* stop when we hit the end scanline */
4522		if (scanline >= work->endscanline)
4523		break;
4524
4525		/* handle this scanline then continue */
4526		(*work->callback)(v, scanline);
4527		}
	4523	/* iterate over extents */
	4524	for (extnum = 0; extnum < unit->count; extnum++)
	4525	(*work->callback)(work, unit->scanline + extnum, unit->extent[extnum].startx, unit->extent[extnum].stopx);
4528	4526	return NULL;
4529	4527	}
4530	4528
r1103	r1104
4545	4543	int ex = (v->reg[clipLeftRight].u >> 0) & 0x3ff;
4546	4544	int sy = (v->reg[clipLowYHighY].u >> 16) & 0x3ff;
4547	4545	int ey = (v->reg[clipLowYHighY].u >> 0) & 0x3ff;
	4546	work_info *work = &v->work;
	4547	work_unit *unit = work->unit;
4548	4548	int x, y;
4549	4549
4550	4550	/* if we're not clearing either, take no time */
r1103	r1104
4559	4559	switch (destbuf)
4560	4560	{
4561	4561	case 0: /* front buffer */
4562		~~v->~~work.drawbuf = v->fbi.rgb[v->fbi.frontbuf];
	4562	work->drawbuf = v->fbi.rgb[v->fbi.frontbuf];
4563	4563	break;
4564	4564
4565	4565	case 1: /* back buffer */
4566		~~v->~~work.drawbuf = v->fbi.rgb[v->fbi.backbuf];
	4566	work->drawbuf = v->fbi.rgb[v->fbi.backbuf];
4567	4567	break;
4568	4568
4569	4569	default: /* reserved */
r1103	r1104
4579	4579	int b = RGB_BLUE(v->reg[color1].u);
4580	4580
4581	4581	APPLY_DITHER(v->reg[fbzMode].u, x, y, r, g, b);
4582		~~v->~~work.dither[y*4 + x] = ((r & 0xf8) << 8) \| ((g & 0xfc) << 3) \| ((b & 0xf8) >> 3);
	4582	work->dither[y*4 + x] = ((r & 0xf8) << 8) \| ((g & 0xfc) << 3) \| ((b & 0xf8) >> 3);
4583	4583	}
4584	4584	}
4585	4585
4586	4586	/* create a shared work item to actually perform the fill */
4587		v->work.state = v;
4588		v->work.minx = sx;
4589		v->work.maxx = ex;
4590		v->work.curscanline = sy;
4591		v->work.endscanline = ey;
4592		v->work.callback = raster_fastfill;
4593		v->work.info = NULL;
4594		work_item_enqueue(v);
	4587	work->startscanline = sy;
	4588	work->callback = raster_fastfill;
	4589	work->info = NULL;
	4590	for (y = sy; y < ey; y += SCANLINES_PER_WORK)
	4591	{
	4592	int extnum;
4595	4593
	4594	unit->work = work;
	4595	unit->scanline = y;
	4596	unit->count = MIN(ey - y, SCANLINES_PER_WORK);
	4597	for (extnum = 0; extnum < unit->count; extnum++)
	4598	{
	4599	unit->extent[extnum].startx = sx;
	4600	unit->extent[extnum].stopx = ex;
	4601	}
	4602	unit++;
	4603	}
	4604	work_item_enqueue(v, work, unit - work->unit);
	4605
4596	4606	/* track pixel writes to the frame buffer regardless of mask */
4597	4607	if (FBZMODE_RGB_BUFFER_MASK(v->reg[fbzMode].u))
4598	4608	v->reg[fbiPixelsOut].u += (ey - sy) * (ex - sx);
r1103	r1104
4681	4691	}
4682	4692	}
4683	4693
	4694	/* wait for any outstanding work to finish */
	4695	work_item_wait(v);
	4696
4684	4697	/* set up the textures */
4685	4698	for (texnum = 0; texnum < texcount; texnum++)
4686	4699	{
r1103	r1104
4809	4822	float dx1, dy1, dx2, dy2;
4810	4823	float divisor, tdiv;
4811	4824
4812		/* wait for any outstanding work to finish */
4813		work_item_wait(v);
4814
4815	4825	/* grab the X/Ys at least */
4816	4826	v->fbi.ax = (INT16)(v->fbi.svert[0].x * 16.0);
4817	4827	v->fbi.ay = (INT16)(v->fbi.svert[0].y * 16.0);
r1103	r1104
4937	4947	static INT32 triangle_create_work_item(voodoo_state v, UINT16 drawbuf, int texcount)
4938	4948	{
4939	4949	raster_info *info = find_rasterizer(v, texcount);
	4950	work_info *work = &v->work;
	4951	work_unit *unit = work->unit;
4940	4952	int curscan, pixels = 0;
	4953	INT32 dxdy_minmid;
	4954	INT32 dxdy_minmax;
	4955	INT32 dxdy_midmax;
	4956	INT32 minx, miny;
	4957	INT32 midx, midy;
	4958	INT32 maxx, maxy;
	4959	INT32 endscanline;
4941	4960
4942	4961	/* sort the vertices */
4943	4962	/* note that this is not necessary on the Voodoo 1 as the card assumes the vertices */
r1103	r1104
4946	4965	{
4947	4966	if (v->fbi.by <= v->fbi.cy)
4948	4967	{
4949		v->work.minx = v->fbi.ax; v->work.miny = v->fbi.ay;
4950		v->work.midx = v->fbi.bx; v->work.midy = v->fbi.by;
4951		v->work.maxx = v->fbi.cx; v->work.maxy = v->fbi.cy;
	4968	minx = v->fbi.ax; miny = v->fbi.ay;
	4969	midx = v->fbi.bx; midy = v->fbi.by;
	4970	maxx = v->fbi.cx; maxy = v->fbi.cy;
4952	4971	}
4953	4972	else if (v->fbi.ay <= v->fbi.cy)
4954	4973	{
4955		v->work.minx = v->fbi.ax; v->work.miny = v->fbi.ay;
4956		v->work.midx = v->fbi.cx; v->work.midy = v->fbi.cy;
4957		v->work.maxx = v->fbi.bx; v->work.maxy = v->fbi.by;
	4974	minx = v->fbi.ax; miny = v->fbi.ay;
	4975	midx = v->fbi.cx; midy = v->fbi.cy;
	4976	maxx = v->fbi.bx; maxy = v->fbi.by;
4958	4977	}
4959	4978	else
4960	4979	{
4961		v->work.minx = v->fbi.cx; v->work.miny = v->fbi.cy;
4962		v->work.midx = v->fbi.ax; v->work.midy = v->fbi.ay;
4963		v->work.maxx = v->fbi.bx; v->work.maxy = v->fbi.by;
	4980	minx = v->fbi.cx; miny = v->fbi.cy;
	4981	midx = v->fbi.ax; midy = v->fbi.ay;
	4982	maxx = v->fbi.bx; maxy = v->fbi.by;
4964	4983	}
4965	4984	}
4966	4985	else
4967	4986	{
4968	4987	if (v->fbi.ay <= v->fbi.cy)
4969	4988	{
4970		v->work.minx = v->fbi.bx; v->work.miny = v->fbi.by;
4971		v->work.midx = v->fbi.ax; v->work.midy = v->fbi.ay;
4972		v->work.maxx = v->fbi.cx; v->work.maxy = v->fbi.cy;
	4989	minx = v->fbi.bx; miny = v->fbi.by;
	4990	midx = v->fbi.ax; midy = v->fbi.ay;
	4991	maxx = v->fbi.cx; maxy = v->fbi.cy;
4973	4992	}
4974	4993	else if (v->fbi.by <= v->fbi.cy)
4975	4994	{
4976		v->work.minx = v->fbi.bx; v->work.miny = v->fbi.by;
4977		v->work.midx = v->fbi.cx; v->work.midy = v->fbi.cy;
4978		v->work.maxx = v->fbi.ax; v->work.maxy = v->fbi.ay;
	4995	minx = v->fbi.bx; miny = v->fbi.by;
	4996	midx = v->fbi.cx; midy = v->fbi.cy;
	4997	maxx = v->fbi.ax; maxy = v->fbi.ay;
4979	4998	}
4980	4999	else
4981	5000	{
4982		v->work.minx = v->fbi.cx; v->work.miny = v->fbi.cy;
4983		v->work.midx = v->fbi.bx; v->work.midy = v->fbi.by;
4984		v->work.maxx = v->fbi.ax; v->work.maxy = v->fbi.ay;
	5001	minx = v->fbi.cx; miny = v->fbi.cy;
	5002	midx = v->fbi.bx; midy = v->fbi.by;
	5003	maxx = v->fbi.ax; maxy = v->fbi.ay;
4985	5004	}
4986	5005	}
4987	5006
	5007	/* clamp to full pixels */
	5008	work->startscanline = (miny + 7) >> 4;
	5009	endscanline = (maxy + 7) >> 4;
	5010	if (work->startscanline >= endscanline)
	5011	return 0;
	5012
4988	5013	/* compute the slopes as 16.16 numbers */
4989		v->work.dxdy_minmid = (v->work.miny == v->work.midy) ? 0 : ((v->work.midx - v->work.minx) << 16) / (v->work.midy - v->work.miny);
4990		v->work.dxdy_minmax = (v->work.miny == v->work.maxy) ? 0 : ((v->work.maxx - v->work.minx) << 16) / (v->work.maxy - v->work.miny);
4991		v->work.dxdy_midmax = (v->work.midy == v->work.maxy) ? 0 : ((v->work.maxx - v->work.midx) << 16) / (v->work.maxy - v->work.midy);
	5014	dxdy_minmid = (miny == midy) ? 0 : ((midx - minx) << 16) / (midy - miny);
	5015	dxdy_minmax = (miny == maxy) ? 0 : ((maxx - minx) << 16) / (maxy - miny);
	5016	dxdy_midmax = (midy == maxy) ? 0 : ((maxx - midx) << 16) / (maxy - midy);
4992	5017
4993		/* clamp to full pixels */
4994		v->work.startscanline = v->work.curscanline = (v->work.miny + 7) >> 4;
4995		v->work.endscanline = (v->work.maxy + 7) >> 4;
4996
4997	5018	/* compute the X extents for each scanline */
4998		for (curscan = ~~v->~~work.startscanline; curscan < ~~v->work.~~endscanline; curscan++)
	5019	for (curscan = work->startscanline; curscan < endscanline; curscan += SCANLINES_PER_WORK)
4999	5020	{
5000		INT32 fully = (curscan << 4) + 8;
5001		INT32 startx = v->work.minx + (((fully - v->work.miny) * v->work.dxdy_minmax) >> 16);
5002		INT32 stopx;
	5021	int extnum;
5003	5022
5004		if (fully < v->work.midy)
5005		stopx = v->work.minx + (((fully - v->work.miny) * v->work.dxdy_minmid) >> 16);
5006		else
5007		stopx = v->work.midx + (((fully - v->work.midy) * v->work.dxdy_midmax) >> 16);
	5023	/* fill in the work unit basics */
	5024	unit->work = work;
	5025	unit->scanline = curscan;
	5026	unit->count = MIN(endscanline - curscan, SCANLINES_PER_WORK);
5008	5027
5009		/* clamp to full pixels */
5010		startx = (startx + 7) >> 4;
5011		stopx = (stopx + 7) >> 4;
	5028	/* iterate over extents */
	5029	for (extnum = 0; extnum < unit->count; extnum++)
	5030	{
	5031	INT32 fully = ((curscan + extnum) << 4) + 8;
	5032	INT32 startx = minx + (((fully - miny) * dxdy_minmax) >> 16);
	5033	INT32 stopx;
5012	5034
5013		/* force start < stop */
5014		if (startx > stopx)
	5035	/* compute the ending X based on which part of the triangle we're in */
	5036	if (fully < midy)
	5037	stopx = minx + (((fully - miny) * dxdy_minmid) >> 16);
	5038	else
	5039	stopx = midx + (((fully - midy) * dxdy_midmax) >> 16);
	5040
	5041	/* clamp to full pixels */
	5042	startx = (startx + 7) >> 4;
	5043	stopx = (stopx + 7) >> 4;
	5044
	5045	/* force start < stop */
	5046	if (startx > stopx)
	5047	{
	5048	int temp = startx;
	5049	startx = stopx;
	5050	stopx = temp;
	5051	}
	5052
	5053	/* set the extent and update the total pixel count */
	5054	unit->extent[extnum].startx = startx;
	5055	unit->extent[extnum].stopx = stopx;
	5056	pixels += stopx - startx;
	5057	}
	5058	unit++;
	5059	}
	5060
	5061	/* copy data */
	5062	work->ax = v->fbi.ax;
	5063	work->ay = v->fbi.ay;
	5064	work->startr = v->fbi.startr;
	5065	work->startg = v->fbi.startg;
	5066	work->startb = v->fbi.startb;
	5067	work->starta = v->fbi.starta;
	5068	work->startz = v->fbi.startz;
	5069	work->startw = v->fbi.startw;
	5070	work->drdx = v->fbi.drdx;
	5071	work->dgdx = v->fbi.dgdx;
	5072	work->dbdx = v->fbi.dbdx;
	5073	work->dadx = v->fbi.dadx;
	5074	work->dzdx = v->fbi.dzdx;
	5075	work->dwdx = v->fbi.dwdx;
	5076	work->drdy = v->fbi.drdy;
	5077	work->dgdy = v->fbi.dgdy;
	5078	work->dbdy = v->fbi.dbdy;
	5079	work->dady = v->fbi.dady;
	5080	work->dzdy = v->fbi.dzdy;
	5081	work->dwdy = v->fbi.dwdy;
	5082	if (texcount > 0)
	5083	{
	5084	work->starts0 = v->tmu[0].starts;
	5085	work->startt0 = v->tmu[0].startt;
	5086	work->startw0 = v->tmu[0].startw;
	5087	work->ds0dx = v->tmu[0].dsdx;
	5088	work->dt0dx = v->tmu[0].dtdx;
	5089	work->dw0dx = v->tmu[0].dwdx;
	5090	work->ds0dy = v->tmu[0].dsdy;
	5091	work->dt0dy = v->tmu[0].dtdy;
	5092	work->dw0dy = v->tmu[0].dwdy;
	5093	if (texcount > 1)
5015	5094	{
5016		int temp = startx;
5017		startx = stopx;
5018		stopx = temp;
	5095	work->starts1 = v->tmu[1].starts;
	5096	work->startt1 = v->tmu[1].startt;
	5097	work->startw1 = v->tmu[1].startw;
	5098	work->ds1dx = v->tmu[1].dsdx;
	5099	work->dt1dx = v->tmu[1].dtdx;
	5100	work->dw1dx = v->tmu[1].dwdx;
	5101	work->ds1dy = v->tmu[1].dsdy;
	5102	work->dt1dy = v->tmu[1].dtdy;
	5103	work->dw1dy = v->tmu[1].dwdy;
5019	5104	}
5020
5021		/* set the extent and update the total pixel count */
5022		v->work.extent[curscan - v->work.startscanline].startx = startx;
5023		v->work.extent[curscan - v->work.startscanline].stopx = stopx;
5024		pixels += stopx - startx;
5025	5105	}
5026	5106
5027	5107	/* farm the rasterization out to other threads */
5028		v->work.state = v;
5029		v->work.callback = info->callback;
5030		v->work.drawbuf = drawbuf;
5031		v->work.info = info;
5032		work_item_enqueue(v);
	5108	work->callback = info->callback;
	5109	work->drawbuf = drawbuf;
	5110	work->info = info;
	5111	work_item_enqueue(v, work, unit - work->unit);
5033	5112
5034	5113	/* update statistics */
5035	5114	info->polys++;
r1103	r1104
5188	5267	implementation of the 'fastfill' command
5189	5268	-------------------------------------------------*/
5190	5269
5191		static void raster_fastfill(vo~~odoo~~_~~state~~ *v, INT32 scanline)
	5270	static void raster_fastfill(work_info *work, INT32 scanline, INT32 startx, INT32 stopx)
5192	5271	{
	5272	voodoo_state *v = work->state;
5193	5273	int scry, x;
5194	5274
5195	5275	/* determine the screen Y */
r1103	r1104
5200	5280	/* fill this RGB row */
5201	5281	if (FBZMODE_RGB_BUFFER_MASK(v->reg[fbzMode].u))
5202	5282	{
5203		UINT16 ditherow = &v->work.dither[(scanline & 3) 4];
5204		UINT16 dest = v->work.drawbuf + scry v->fbi.rowpixels;
	5283	UINT16 ditherow = &work->dither[(scanline & 3) 4];
	5284	UINT16 dest = work->drawbuf + scry v->fbi.rowpixels;
5205	5285
5206		for (x = ~~v->wo~~r~~k.min~~x; x < ~~v->w~~o~~rk.max~~x; x++)
	5286	for (x = startx; x < stopx; x++)
5207	5287	dest[x] = ditherow[x & 3];
5208	5288	}
5209	5289
r1103	r1104
5213	5293	UINT16 color = v->reg[zaColor].u;
5214	5294	UINT16 dest = v->fbi.aux + scry v->fbi.rowpixels;
5215	5295
5216		for (x = ~~v->wo~~r~~k.min~~x; x < ~~v->w~~o~~rk.max~~x; x++)
	5296	for (x = startx; x < stopx; x++)
5217	5297	dest[x] = color;
5218	5298	}
5219	5299	}

src/mame/video/dynax.c
r1103	r1104
224	224	/* Which half of the layers to write two (interleaved games only) */
225	225	WRITE8_HANDLER( hanamai_layer_half_w )
226	226	{
227		hanamai_layer_half = data & 1;
	227	hanamai_layer_half = (~data) & 1;
228	228	#if VERBOSE
229	229	logerror("H=%02X ",data);
230	230	#endif
r1103	r1104
352	352	switch (layer_layout)
353	353	{
354	354	case LAYOUT_HANAMAI:
355		if (mask & 0x01) dynax_pixmap[layer+0][hanamai_layer_half][addr] = pen;
356		if (mask & 0x02) dynax_pixmap[layer+1][hanamai_layer_half][addr] = pen;
357		if (mask & 0x04) dynax_pixmap[layer+2][hanamai_layer_half][addr] = pen;
358		if (mask & 0x08) dynax_pixmap[layer+3][hanamai_layer_half][addr] = pen;
	355	if (mask & 0x01) dynax_pixmap[layer+0][hanamai_layer_half^flipscreen][addr] = pen;
	356	if (mask & 0x02) dynax_pixmap[layer+1][hanamai_layer_half^flipscreen][addr] = pen;
	357	if (mask & 0x04) dynax_pixmap[layer+2][hanamai_layer_half^flipscreen][addr] = pen;
	358	if (mask & 0x08) dynax_pixmap[layer+3][hanamai_layer_half^flipscreen][addr] = pen;
359	359	break;
360	360
361	361	case LAYOUT_HNORIDUR:
362		if (mask & 0x01) dynax_pixmap[layer+0][hanamai_layer_half][addr] = pen;
363		if (mask & 0x02) dynax_pixmap[layer+1][hanamai_layer_half][addr] = pen;
364		if (mask & 0x04) dynax_pixmap[layer+2][hanamai_layer_half][addr] = pen;
365		if (mask & 0x08) dynax_pixmap[layer+3][hanamai_layer_half][addr] = pen;
	362	if (mask & 0x01) dynax_pixmap[layer+0][hanamai_layer_half^flipscreen][addr] = pen;
	363	if (mask & 0x02) dynax_pixmap[layer+1][hanamai_layer_half^flipscreen][addr] = pen;
	364	if (mask & 0x04) dynax_pixmap[layer+2][hanamai_layer_half^flipscreen][addr] = pen;
	365	if (mask & 0x08) dynax_pixmap[layer+3][hanamai_layer_half^flipscreen][addr] = pen;
366	366	if (!hnoridur_layer_half2) break;
367		if (mask & 0x01) dynax_pixmap[layer+0][1-hanamai_layer_half][addr] = pen;
368		if (mask & 0x02) dynax_pixmap[layer+1][1-hanamai_layer_half][addr] = pen;
369		if (mask & 0x04) dynax_pixmap[layer+2][1-hanamai_layer_half][addr] = pen;
370		if (mask & 0x08) dynax_pixmap[layer+3][1-hanamai_layer_half][addr] = pen;
	367	if (mask & 0x01) dynax_pixmap[layer+0][1^hanamai_layer_half^flipscreen][addr] = pen;
	368	if (mask & 0x02) dynax_pixmap[layer+1][1^hanamai_layer_half^flipscreen][addr] = pen;
	369	if (mask & 0x04) dynax_pixmap[layer+2][1^hanamai_layer_half^flipscreen][addr] = pen;
	370	if (mask & 0x08) dynax_pixmap[layer+3][1^hanamai_layer_half^flipscreen][addr] = pen;
371	371	break;
372	372
373	373	case LAYOUT_JANTOUKI:
374		if (mask & 0x80) dynax_pixmap[layer+3][1][addr] = pen;
375		if (mask & 0x40) dynax_pixmap[layer+3][0][addr] = pen;
	374	if (mask & 0x80) dynax_pixmap[layer+3][1^flipscreen][addr] = pen;
	375	if (mask & 0x40) dynax_pixmap[layer+3][0^flipscreen][addr] = pen;
376	376	case LAYOUT_DRGPUNCH:
377		if (mask & 0x20) dynax_pixmap[layer+2][1][addr] = pen;
378		if (mask & 0x10) dynax_pixmap[layer+2][0][addr] = pen;
379		if (mask & 0x08) dynax_pixmap[layer+1][1][addr] = pen;
380		if (mask & 0x04) dynax_pixmap[layer+1][0][addr] = pen;
381		if (mask & 0x02) dynax_pixmap[layer+0][1][addr] = pen;
382		if (mask & 0x01) dynax_pixmap[layer+0][0][addr] = pen;
	377	if (mask & 0x20) dynax_pixmap[layer+2][1^flipscreen][addr] = pen;
	378	if (mask & 0x10) dynax_pixmap[layer+2][0^flipscreen][addr] = pen;
	379	if (mask & 0x08) dynax_pixmap[layer+1][1^flipscreen][addr] = pen;
	380	if (mask & 0x04) dynax_pixmap[layer+1][0^flipscreen][addr] = pen;
	381	if (mask & 0x02) dynax_pixmap[layer+0][1^flipscreen][addr] = pen;
	382	if (mask & 0x01) dynax_pixmap[layer+0][0^flipscreen][addr] = pen;
383	383	break;
384	384
385	385	case LAYOUT_MJDIALQ2:
r1103	r1104
946	946	for (dy = 0; dy < 256; dy++)
947	947	{
948	948	UINT16 *dst;
949		UINT16 dstbase = (UINT16 )bitmap~~->base~~ + ((dy - scrolly) & 0xff) * bitmap->rowpixels;
	949	UINT16 *dstbase = BITMAP_ADDR16(bitmap, (dy - scrolly) & 0xff, 0);
950	950
951	951	length = scrollx;
952	952	dst = dstbase + 2*(256 - length);
r1103	r1104
1008	1008	{
1009	1009	int sy = ((dy - scrolly) & 0xff) + y;
1010	1010	UINT16 *dst;
1011		UINT16 dstbase = (UINT16 )bitmap~~->base~~ + sy* ~~bitmap->rowpixels~~;
	1011	UINT16 *dstbase = BITMAP_ADDR16(bitmap, sy, 0);
1012	1012
1013	1013	if ((sy < cliprect->min_y) \|\| (sy > cliprect->max_y))
1014	1014	{
r1103	r1104
1070	1070	for (dy = 0; dy < 256; dy++)
1071	1071	{
1072	1072	UINT16 *dst;
1073		UINT16 dstbase = (UINT16 )bitmap~~->base~~ + ((dy - scrolly) & 0xff) * bitmap->rowpixels;
	1073	UINT16 *dstbase = BITMAP_ADDR16(bitmap, (dy - scrolly) & 0xff, 0);
1074	1074
1075	1075	length = scrollx;
1076	1076	dst = dstbase + 256 - length;
r1103	r1104
1310	1310	if (layers_ctrl & 2) mjdialq2_copylayer( bitmap, cliprect, 1 );
1311	1311	return 0;
1312	1312	}
	1313
	1314	// htengoku uses the mixer chip from ddenlovr
	1315
	1316	static mame_bitmap *framebuffer;
	1317
	1318	VIDEO_START(htengoku)
	1319	{
	1320	video_start_ddenlovr(machine);
	1321	video_start_hnoridur(machine);
	1322	framebuffer = auto_bitmap_alloc(machine->screen[0].width,machine->screen[0].height,machine->screen[0].format);
	1323	}
	1324
	1325	VIDEO_EOF(htengoku)
	1326	{
	1327	int layer,x,y;
	1328
	1329	// render the layers, one by one, "dynax.c" style. Then convert the pixmaps to "ddenlovr.c"
	1330	// format and let video_eof_ddenlovr do the final compositing (priorities + palettes)
	1331	for (layer = 0; layer < 4; layer++)
	1332	{
	1333	fillbitmap(framebuffer,0,&machine->screen[0].visarea);
	1334	hanamai_copylayer( framebuffer, &machine->screen[0].visarea, layer );
	1335
	1336	for (y=0; y < 256; y++)
	1337	for (x=0; x < 512; x++)
	1338	ddenlovr_pixmap[3-layer][y512+x] = (UINT8)(BITMAP_ADDR16(framebuffer, y,x));
	1339	}
	1340	video_eof_ddenlovr(machine);
	1341	}

src/mame/video/ms32.c
r1103	r1104
86	86	if (!strcmp(machine->gamedrv->name,"tp2m32")) ms32_reverse_sprite_order = 0;
87	87	if (!strcmp(machine->gamedrv->name,"47pie2")) ms32_reverse_sprite_order = 0;
88	88	if (!strcmp(machine->gamedrv->name,"47pie2o")) ms32_reverse_sprite_order = 0;
	89	if (!strcmp(machine->gamedrv->name,"hayaosi3")) ms32_reverse_sprite_order = 0;
89	90
90	91	// tp2m32 doesn't set the brightness registers so we need sensible defaults
91	92	brt[0] = brt[1] = 0xffff;
r1103	r1104
486	487	top and bottom of the screen becomes black on black) */
487	488	fillbitmap(bitmap,machine->pens[0],cliprect); /* bg color */
488	489
489		#ifdef MAME_DEBUG
490		if (!input_code_pressed(KEYCODE_Q))
491		#endif
492		tilemap_draw(bitmap,cliprect,ms32_bg_tilemap,0,1);
493	490
494		#ifdef MAME_DEBUG
495		if (!input_code_pressed(KEYCODE_W))
496		#endif
497		draw_roz(bitmap,cliprect,2);
	491	/* priority hack, we really need to figure out what priority ram is I think */
	492	if (!strcmp(machine->gamedrv->name,"hayaosi3"))
	493	{
	494	tilemap_draw(bitmap,cliprect,ms32_bg_tilemap,0,1);
	495	tilemap_draw(bitmap,cliprect,ms32_tx_tilemap,0,4);
	496	draw_roz(bitmap,cliprect,4); // this question text needs to appear over the sprites
	497	draw_sprites(machine,bitmap,cliprect, ms32_spram, 0x40000);
498	498
499		#ifdef MAME_DEBUG
500		if (!input_code_pressed(KEYCODE_E))
501		#endif
502		tilemap_draw(bitmap,cliprect,ms32_tx_tilemap,0,4);
	499	}
	500	else
	501	{
	502	tilemap_draw(bitmap,cliprect,ms32_bg_tilemap,0,1);
	503	draw_roz(bitmap,cliprect,2);
	504	tilemap_draw(bitmap,cliprect,ms32_tx_tilemap,0,4);
	505	draw_sprites(machine,bitmap,cliprect, ms32_spram, 0x40000);
	506	}
503	507
504		#ifdef MAME_DEBUG
505		if (!input_code_pressed(KEYCODE_R))
506		#endif
507		draw_sprites(machine,bitmap,cliprect, ms32_spram, 0x40000);
	508
508	509	return 0;
509	510	}

src/mame/video/tmnt.c
r1103	r1104
513	513	prmrsocr_sprite_bank = (data & 0x40) >> 6;
514	514	K053244_bankselect(0, prmrsocr_sprite_bank << 2);
515	515
	516	/* bit 7 = 53596 region selector for ROM test */
	517	glfgreat_roz_char_bank = (data & 0x80) >> 7;
	518
516	519	/* other bits unknown (unused?) */
517	520	}
518	521	}
519	522
	523	READ16_HANDLER( prmrsocr_rom_r )
	524	{
	525	if(glfgreat_roz_char_bank)
	526	return memory_region(REGION_GFX3)[offset];
	527	else
	528	return 256 * memory_region(REGION_USER1)[offset] + memory_region(REGION_USER1)[offset + 0x020000];
	529	}
520	530
521
522	531	WRITE16_HANDLER( tmnt_priority_w )
523	532	{
524	533	if (ACCESSING_LSB)

src/mame/video/segaic16.c
r1103	r1104
3532	3532	/* fetch the pixel from the source bitmap */
3533	3533	int sx = (tx >> 14) & 0x1ff;
3534	3534	int sy = (ty >> 14) & 0x1ff;
3535		int pix = src[sy * srcbitmap->rowpixels + (sx ~~& 0x1ff)~~];
	3535	int pix = src[sy * srcbitmap->rowpixels + sx];
3536	3536
3537	3537	/* non-zero pixels get written; everything else is the scanline color */
3538	3538	if (pix != 0xffff)

src/mame/video/vooddefs.h
r1103	r1104
24	24	/* maximum number of TMUs */
25	25	#define MAX_TMU 2
26	26
27		/* number of render groups for parallelism */
28		#define RENDER_GROUPS 2
	27	/* scanlines per work item */
	28	#define SCANLINES_PER_WORK 4
29	29
30	30	/* accumulate operations less than this number of clocks */
31	31	#define ACCUMULATE_THRESHOLD 0
r1103	r1104
1334	1334	*************************************/
1335	1335
1336	1336	typedef struct _voodoo_state voodoo_state;
	1337	typedef struct _work_info work_info;
1337	1338
	1339
1338	1340	typedef union _voodoo_reg voodoo_reg;
1339	1341	union _voodoo_reg
1340	1342	{
r1103	r1104
1567	1569	};
1568	1570
1569	1571
1570		typedef void (raster_callback)(vo~~odoo~~_~~state~~ , INT32);
	1572	typedef void (raster_callback)(work_info , INT32, INT32, INT32);
1571	1573
1572	1574
1573	1575	typedef struct _raster_info raster_info;
r1103	r1104
1588	1590	};
1589	1591
1590	1592
1591		typedef struct _work_info work_info;
	1593	typedef struct _work_unit work_unit;
	1594	struct _work_unit
	1595	{
	1596	work_info work; / pointer back to the work info */
	1597	INT16 scanline, count; /* starting scanline and count */
	1598	struct
	1599	{
	1600	INT32 startx, stopx; /* starting/ending X points for each scanline */
	1601	} extent[SCANLINES_PER_WORK];
	1602	};
	1603
	1604
1592	1605	struct _work_info
1593	1606	{
1594		voodoo_state state; / pointer to the state object */
1595		osd_work_queue queue; / work queue for offloading rasterization */
	1607	voodoo_state state; / pointer back to the voodoo state */
1596	1608
1597	1609	raster_callback callback; /* callback to handle a scanline's worth of work */
1598	1610	UINT16 * drawbuf; /* pointer to render buffer */
1599	1611
1600		volatile INT32 curscanline; /* current scanline, shared by all helpers */
1601	1612	INT32 startscanline; /* starting scanline */
1602		INT32 endscanline; /* ending scanline */
1603	1613
1604		INT32 dxdy_minmid; /* dx/dy between the top and middle points */
1605		INT32 dxdy_minmax; /* dx/dy between the top and bottom points */
1606		INT32 dxdy_midmax; /* dx/dy between the middle and bottom points */
1607		INT32 minx, miny; /* x,y of the top point */
1608		INT32 midx, midy; /* x,y of the middle point */
1609		INT32 maxx, maxy; /* x,y of the bottom point */
1610
1611	1614	UINT16 dither[16]; /* dither matrix, for fastfill */
1612	1615
1613	1616	INT32 start_pixels_in; /* starting fbiPixelsIn value */
r1103	r1104
1617	1620	INT32 start_afunc_fail; /* starting fbiAfuncFail value */
1618	1621	raster_info info; / pointer to rasterizer information */
1619	1622
1620		struct
1621		{
1622		INT32 startx, stopx; /* starting/ending X points for each scanline */
1623		} extent[4097];
	1623	INT16 ax, ay; /* vertex A x,y (12.4) */
	1624	INT32 startr, startg, startb, starta; /* starting R,G,B,A (12.12) */
	1625	INT32 startz; /* starting Z (20.12) */
	1626	INT64 startw; /* starting W (16.32) */
	1627	INT32 drdx, dgdx, dbdx, dadx; /* delta R,G,B,A per X */
	1628	INT32 dzdx; /* delta Z per X */
	1629	INT64 dwdx; /* delta W per X */
	1630	INT32 drdy, dgdy, dbdy, dady; /* delta R,G,B,A per Y */
	1631	INT32 dzdy; /* delta Z per Y */
	1632	INT64 dwdy; /* delta W per Y */
	1633
	1634	INT64 starts0, startt0; /* starting S,T (14.18) */
	1635	INT64 startw0; /* starting W (2.30) */
	1636	INT64 ds0dx, dt0dx; /* delta S,T per X */
	1637	INT64 dw0dx; /* delta W per X */
	1638	INT64 ds0dy, dt0dy; /* delta S,T per Y */
	1639	INT64 dw0dy; /* delta W per Y */
	1640
	1641	INT64 starts1, startt1; /* starting S,T (14.18) */
	1642	INT64 startw1; /* starting W (2.30) */
	1643	INT64 ds1dx, dt1dx; /* delta S,T per X */
	1644	INT64 dw1dx; /* delta W per X */
	1645	INT64 ds1dy, dt1dy; /* delta S,T per Y */
	1646	INT64 dw1dy; /* delta W per Y */
	1647
	1648	work_unit unit[4100/SCANLINES_PER_WORK]; /* individual work units */
1624	1649	};
1625	1650
1626	1651
r1103	r1104
1664	1689	banshee_info banshee; /* Banshee state */
1665	1690
1666	1691	work_info work; /* work queue management */
	1692	osd_work_queue work_queue; / work queue for offloading rasterization */
1667	1693
1668	1694	voodoo_stats stats; /* internal statistics */
1669	1695
r1103	r1104
3498	3524
3499	3525	#define RASTERIZER(name, TMUS, FBZCOLORPATH, FBZMODE, ALPHAMODE, FOGMODE, TEXMODE0, TEXMODE1) \
3500	3526	\
3501		static void raster_##name(voodoo_stat~~e *v~~, INT32 y) \
	3527	static void raster_##name(work_info *work, INT32 y, INT32 startx, INT32 stopx) \
3502	3528	{ \
	3529	voodoo_state *v = work->state; \
3503	3530	DECLARE_STATISTICS; \
3504	3531	INT32 iterr, iterg, iterb, itera; \
3505	3532	INT32 iterz; \
3506	3533	INT64 iterw, iterw0 = 0, iterw1 = 0; \
3507	3534	INT64 iters0 = 0, iters1 = 0; \
3508	3535	INT64 itert0 = 0, itert1 = 0; \
3509		INT32 startx, stopx; \
3510	3536	UINT16 *depth; \
3511	3537	UINT16 *dest; \
3512	3538	INT32 dx, dy; \
3513	3539	INT32 scry; \
3514	3540	INT32 x; \
3515	3541	\
3516		/* extract X extents */ \
3517		startx = v->work.extent[y - v->work.startscanline].startx; \
3518		stopx = v->work.extent[y - v->work.startscanline].stopx; \
3519		\
3520	3542	/* determine the screen Y */ \
3521	3543	scry = y; \
3522	3544	if (FBZMODE_Y_ORIGIN(FBZMODE)) \
3523	3545	scry = (v->fbi.yorigin - y) & 0x3ff; \
3524	3546	\
3525	3547	/* get pointers to the target buffer and depth buffer */ \
3526		dest = ~~v->~~work.drawbuf + scry * v->fbi.rowpixels; \
	3548	dest = work->drawbuf + scry * v->fbi.rowpixels; \
3527	3549	depth = v->fbi.aux ? (v->fbi.aux + scry * v->fbi.rowpixels) : NULL; \
3528	3550	\
3529	3551	/* compute the starting parameters */ \
3530		dx = startx - (v->fbi.ax >> 4); \
3531		dy = y - (v->fbi.ay >> 4); \
3532		iterr = v->fbi.startr + dy * v->fbi.drdy + dx * v->fbi.drdx; \
3533		iterg = v->fbi.startg + dy * v->fbi.dgdy + dx * v->fbi.dgdx; \
3534		iterb = v->fbi.startb + dy * v->fbi.dbdy + dx * v->fbi.dbdx; \
3535		itera = v->fbi.starta + dy * v->fbi.dady + dx * v->fbi.dadx; \
3536		iterz = v->fbi.startz + dy * v->fbi.dzdy + dx * v->fbi.dzdx; \
3537		iterw = v->fbi.startw + dy * v->fbi.dwdy + dx * v->fbi.dwdx; \
	3552	dx = startx - (work->ax >> 4); \
	3553	dy = y - (work->ay >> 4); \
	3554	iterr = work->startr + dy * work->drdy + dx * work->drdx; \
	3555	iterg = work->startg + dy * work->dgdy + dx * work->dgdx; \
	3556	iterb = work->startb + dy * work->dbdy + dx * work->dbdx; \
	3557	itera = work->starta + dy * work->dady + dx * work->dadx; \
	3558	iterz = work->startz + dy * work->dzdy + dx * work->dzdx; \
	3559	iterw = work->startw + dy * work->dwdy + dx * work->dwdx; \
3538	3560	if (TMUS >= 1) \
3539	3561	{ \
3540		iterw0 = v->tmu[0].startw + dy * v->tmu[0].dwdy + \
3541		dx * v->tmu[0].dwdx; \
3542		iters0 = v->tmu[0].starts + dy * v->tmu[0].dsdy + \
3543		dx * v->tmu[0].dsdx; \
3544		itert0 = v->tmu[0].startt + dy * v->tmu[0].dtdy + \
3545		dx * v->tmu[0].dtdx; \
	3562	iterw0 = work->startw0 + dy * work->dw0dy + dx * work->dw0dx; \
	3563	iters0 = work->starts0 + dy * work->ds0dy + dx * work->ds0dx; \
	3564	itert0 = work->startt0 + dy * work->dt0dy + dx * work->dt0dx; \
3546	3565	} \
3547	3566	if (TMUS >= 2) \
3548	3567	{ \
3549		iterw1 = v->tmu[1].startw + dy * v->tmu[1].dwdy + \
3550		dx * v->tmu[1].dwdx; \
3551		iters1 = v->tmu[1].starts + dy * v->tmu[1].dsdy + \
3552		dx * v->tmu[1].dsdx; \
3553		itert1 = v->tmu[1].startt + dy * v->tmu[1].dtdy + \
3554		dx * v->tmu[1].dtdx; \
	3568	iterw1 = work->startw1 + dy * work->dw1dy + dx * work->dw1dx; \
	3569	iters1 = work->starts1 + dy * work->ds1dy + dx * work->ds1dx; \
	3570	itert1 = work->startt1 + dy * work->dt1dy + dx * work->dt1dx; \
3555	3571	} \
3556	3572	\
3557	3573	/* loop in X */ \
r1103	r1104
3589	3605	ALPHAMODE, FOGMODE, iterz, iterw, iterargb); \
3590	3606	\
3591	3607	/* update the iterated parameters */ \
3592		iterr += v->fbi.drdx; \
3593		iterg += v->fbi.dgdx; \
3594		iterb += v->fbi.dbdx; \
3595		itera += v->fbi.dadx; \
3596		iterz += v->fbi.dzdx; \
3597		iterw += v->fbi.dwdx; \
	3608	iterr += work->drdx; \
	3609	iterg += work->dgdx; \
	3610	iterb += work->dbdx; \
	3611	itera += work->dadx; \
	3612	iterz += work->dzdx; \
	3613	iterw += work->dwdx; \
3598	3614	if (TMUS >= 1) \
3599	3615	{ \
3600		iterw0 += v->tmu[0].dwdx; \
3601		iters0 += v->tmu[0].dsdx; \
3602		itert0 += v->tmu[0].dtdx; \
	3616	iterw0 += work->dw0dx; \
	3617	iters0 += work->ds0dx; \
	3618	itert0 += work->dt0dx; \
3603	3619	} \
3604	3620	if (TMUS >= 2) \
3605	3621	{ \
3606		iterw1 += v->tmu[1].dwdx; \
3607		iters1 += v->tmu[1].dsdx; \
3608		itert1 += v->tmu[1].dtdx; \
	3622	iterw1 += work->dw1dx; \
	3623	iters1 += work->ds1dx; \
	3624	itert1 += work->dt1dx; \
3609	3625	} \
3610	3626	} \
3611	3627	UPDATE_STATISTICS(v); \

src/mame/video/namcos22.c
r1103	r1104
237	237	return mpTextureTileData[(tile<<8)\|mXYAttrToPixel[mpTextureTileMapAttr[offs]][x&0xf][y&0xf]];
238	238	} /* texel */
239	239
240		typedef void drawscanline_t(
241		mame_bitmap *bitmap,
242		const rectangle *clip,
243		const edge *e1,
244		const edge *e2,
245		int sy );
246
247	240	static void renderscanline_uvi_full(running_machine machine, mame_bitmap bitmap, const rectangle clip, const edge e1, const edge *e2, int sy, int color, int bn, UINT16 flags, int cmode )
248	241	{
249	242	int fadeEnable = (mixer.target&1) && mixer.fadeFactor;

src/mame/video/raiden.c
r1103	r1104
4	4	static tilemap bg_layer,fg_layer,*tx_layer;
5	5	UINT16 raiden_back_data,raiden_fore_data,*raiden_scroll_ram;
6	6
7		static int flipscreen,~~ALTERNATE~~;
	7	static int flipscreen,alternate;
8	8
9	9	/******************************************************************************/
10	10
r1103	r1104
72	72	bg_layer = tilemap_create(get_back_tile_info,tilemap_scan_cols,TILEMAP_TYPE_PEN, 16,16,32,32);
73	73	fg_layer = tilemap_create(get_fore_tile_info,tilemap_scan_cols,TILEMAP_TYPE_PEN,16,16,32,32);
74	74	tx_layer = tilemap_create(get_text_tile_info,tilemap_scan_cols,TILEMAP_TYPE_PEN,8,8,32,32);
75		~~ALTERNATE~~=0;
	75	alternate=0;
76	76
77	77	tilemap_set_transparent_pen(fg_layer,15);
78	78	tilemap_set_transparent_pen(tx_layer,15);
r1103	r1104
83	83	bg_layer = tilemap_create(get_back_tile_info,tilemap_scan_cols,TILEMAP_TYPE_PEN, 16,16,32,32);
84	84	fg_layer = tilemap_create(get_fore_tile_info,tilemap_scan_cols,TILEMAP_TYPE_PEN,16,16,32,32);
85	85	tx_layer = tilemap_create(get_text_tile_info,tilemap_scan_rows,TILEMAP_TYPE_PEN,8,8,32,32);
86		~~ALTERNATE~~=1;
	86	alternate=1;
87	87
88	88	tilemap_set_transparent_pen(fg_layer,15);
89	89	tilemap_set_transparent_pen(tx_layer,15);
r1103	r1104
136	136	VIDEO_UPDATE( raiden )
137	137	{
138	138	/* Setup the tilemaps, alternate version has different scroll positions */
139		if (!~~ALTERNATE~~) {
	139	if (!alternate) {
140	140	tilemap_set_scrollx( bg_layer,0, raiden_scroll_ram[0]);
141	141	tilemap_set_scrolly( bg_layer,0, raiden_scroll_ram[1]);
142	142	tilemap_set_scrollx( fg_layer,0, raiden_scroll_ram[2]);

src/mame/drivers/mitchell.c
r1103	r1104
1690	1690	ROM_LOAD( "bb1.bin", 0x00000, 0x20000, CRC(c52e5b8e) SHA1(933b954bfdd2d67e28b032ffabde192531249c1f) )
1691	1691	ROM_END
1692	1692
	1693
	1694
1693	1695	ROM_START( pangb )
1694	1696	ROM_REGION( 2*0x50000, REGION_CPU1, 0 )
1695	1697	ROM_LOAD( "pang_04.bin", 0x50000, 0x08000, CRC(f68f88a5) SHA1(6f57891d399a46d8d5a531771129552ed420d10a) ) /* Decrypted opcode + data */
r1103	r1104
1741	1743	ROM_LOAD( "1.1a", 0x00000, 0x10000, CRC(b6463907) SHA1(b79e0dca10c639b7f0ea9cbc49300b80708d46fa) )
1742	1744	ROM_END
1743	1745
	1746	/* this bootleg has different sound hardware, the sound program is the same as 'rebus' by microhard
	1747	I suspect it was produced by the same company as 'spangbl' */
	1748	ROM_START( pangba )
	1749	ROM_REGION( 2*0x50000, REGION_CPU1, 0 )
	1750	ROM_LOAD( "pang.3", 0x50000, 0x08000, CRC(2548534f) SHA1(c67964e1d0b51ea7bb62685055dee1910e9f0fb9) )
	1751	ROM_CONTINUE( 0x00000, 0x08000 )
	1752	ROM_LOAD( "pang.2", 0x60000, 0x04000, CRC(8167b646) SHA1(db131cb53e81abd070db83721752a8f5473afbb9) )
	1753	ROM_CONTINUE( 0x10000, 0x04000 )
	1754	ROM_CONTINUE( 0x64000, 0x04000 )
	1755	ROM_CONTINUE( 0x14000, 0x04000 )
	1756	ROM_CONTINUE( 0x68000, 0x04000 )
	1757	ROM_CONTINUE( 0x18000, 0x04000 )
	1758	ROM_CONTINUE( 0x6c000, 0x04000 )
	1759	ROM_CONTINUE( 0x1c000, 0x04000 )
	1760	ROM_LOAD( "pang.1", 0x70000, 0x04000, CRC(5c3afca2) SHA1(130c801495d83e2336b8c5b04ca168e76e9e0da8) )
	1761	ROM_CONTINUE( 0x20000, 0x04000 )
	1762	ROM_CONTINUE( 0x74000, 0x04000 )
	1763	ROM_CONTINUE( 0x24000, 0x04000 )
1744	1764
	1765	ROM_REGION( 0x20000, REGION_CPU2, 0 ) /* Sound Z80 + M5205(?) samples */
	1766	ROM_LOAD( "pang.4", 0x00000, 0x10000, CRC(88a7b1f8) SHA1(b34fa26dbc613bf3b525d19df90fa3ba4efb6e5d) ) // this is the same as the microhard game 'rebus' ...
	1767
	1768	ROM_REGION( 0x100000, REGION_GFX1, ROMREGION_INVERT \| ROMREGION_DISPOSE \| ROMREGION_ERASEFF )
	1769	ROM_LOAD16_BYTE( "pang.14", 0x000001, 0x10000, CRC(c90095ee) SHA1(bf380f289eb42030a9f911aa5f697ba76f5723db) )
	1770	ROM_LOAD16_BYTE( "pang.6", 0x000000, 0x10000, CRC(c0133cf3) SHA1(07916f7ce6bbaea75b68f5d1d2cb4486825fc397) )
	1771	ROM_LOAD16_BYTE( "pang.13", 0x020001, 0x10000, CRC(a49e98ec) SHA1(8a3d13bd755b58b0bc1d1497363409a1eeade129) )
	1772	ROM_LOAD16_BYTE( "pang.5", 0x020000, 0x10000, CRC(5804ae3e) SHA1(33de9aea7aa201aa650b0b6c5347713bf10cc13d) )
	1773
	1774	ROM_LOAD16_BYTE( "pang.16", 0x080001, 0x10000, CRC(bc508935) SHA1(1a11144b563befc11015d75e3867c07329ee6f32) )
	1775	ROM_LOAD16_BYTE( "pang.8", 0x080000, 0x10000, CRC(53a99bb6) SHA1(ffb75c5541d7c1478f05717b2cfa4bfe9b4654cd) )
	1776	ROM_LOAD16_BYTE( "pang.15", 0x0a0001, 0x10000, CRC(bf5c09b9) SHA1(f66a901292b190aa39dc2460363307e94c358d4d) )
	1777	ROM_LOAD16_BYTE( "pang.7", 0x0a0000, 0x10000, CRC(8b718670) SHA1(c22005a665a9e0bcfc3ddbc22ca4a2a261224ce1) )
	1778
	1779	ROM_REGION( 0x040000, REGION_GFX2, ROMREGION_INVERT \| ROMREGION_DISPOSE )
	1780	ROM_LOAD( "pang.11", 0x020000, 0x10000, CRC(07191732) SHA1(7de03ddb07b2afad311b9ed5c84e04bef62d0050) )
	1781	ROM_LOAD( "pang.9", 0x030000, 0x10000, CRC(6496be82) SHA1(9c7ef4c6c3a0361f3118339a0c63b0923045d6c3) )
	1782	ROM_LOAD( "pang.12", 0x000000, 0x10000, CRC(fa247a04) SHA1(b5cab5f65eb3af3deeea6afba955056ca51f39af) )
	1783	ROM_LOAD( "pang.10", 0x010000, 0x10000, CRC(082151ee) SHA1(0857b9f7430e0fc6217eafbaf008ff9da8e7a493) )
	1784	ROM_END
	1785
	1786
1745	1787	ROM_START( bbros )
1746	1788	ROM_REGION( 0x50000, REGION_CPU1, 0 )
1747	1789	ROM_LOAD( "bb6.bin", 0x00000, 0x08000, CRC(a3041ca4) SHA1(2accb2151f621e4802211efe986969ebd3acb6d4) )
r1103	r1104
2371	2413	GAME( 1989, pang, 0, pang, pang, pang, ROT0, "Mitchell", "Pang (World)", 0 )
2372	2414	GAME( 1989, pangb, pang, pang, pang, pangb, ROT0, "[Mitchell] (bootleg)", "Pang (bootleg, set 1)", 0 )
2373	2415	GAME( 1989, pangbold, pang, pang, pang, pangb, ROT0, "[Mitchell] (bootleg)", "Pang (bootleg, set 2)", 0 )
	2416	GAME( 1989, pangba, pang, spangbl, pang, pangb, ROT0, "[Mitchell] (bootleg)", "Pang (bootleg, set 3)", GAME_NO_SOUND )
2374	2417	GAME( 1989, bbros, pang, pang, pang, pang, ROT0, "Capcom", "Buster Bros. (US)", 0 )
2375	2418	GAME( 1989, pompingw, pang, pang, pang, pang, ROT0, "Mitchell", "Pomping World (Japan)", 0 )
2376	2419	GAME( 1989, cworld, 0, pang, qtono1, cworld, ROT0, "Capcom", "Capcom World (Japan)", 0 )

src/mame/drivers/bublbobl.c
r1103	r1104
1203	1203	ROM_LOAD( "pal16l8.u4", 0x0400, 0x0104, CRC(077d20a8) SHA1(8e568ffd6f66c3dd61708dd0f3be9c2ed488ae4b) )
1204	1204	ROM_END
1205	1205
	1206
	1207	ROM_START( sboblboa )
	1208	ROM_REGION( 0x30000, REGION_CPU1, 0 )
	1209	ROM_LOAD( "1c.bin", 0x00000, 0x08000, CRC(f304152a) SHA1(103d9beddccef289ed739d28ebda69bbad3d42f9) )
	1210	/* ROMs banked at 8000-bfff */
	1211	ROM_LOAD( "1a.bin", 0x10000, 0x08000, CRC(0865209c) SHA1(eddd3547ae675b73376e5c284e0b15830f4a6645) )
	1212	ROM_LOAD( "1b.bin", 0x18000, 0x08000, CRC(1f29b5c0) SHA1(c15c84ca11cc10edac6340468bca463ecb2d89e6) )
	1213	/* 20000-2ffff empty */
	1214
	1215	ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* 64k for the second CPU */
	1216	ROM_LOAD( "1e.rom", 0x0000, 0x08000, CRC(ae11a07b) SHA1(af7a335c8da637103103cc274e077f123908ebb7) )
	1217
	1218	ROM_REGION( 0x10000, REGION_CPU3, 0 ) /* 64k for the third CPU */
	1219	ROM_LOAD( "1d.rom", 0x0000, 0x08000, CRC(4f9a26e8) SHA1(3105b34b88a7134493c2b3f584729f8b0407a011) )
	1220
	1221	ROM_REGION( 0x80000, REGION_GFX1, ROMREGION_DISPOSE \| ROMREGION_INVERT )
	1222	ROM_LOAD( "1l.rom", 0x00000, 0x8000, CRC(20358c22) SHA1(2297af6c53d5807bf90a8e081075b8c72a994fc5) ) /* 1st plane */
	1223	ROM_LOAD( "1m.rom", 0x08000, 0x8000, CRC(930168a9) SHA1(fd358c3c3b424bca285f67a1589eb98a345ff670) )
	1224	ROM_LOAD( "1n.rom", 0x10000, 0x8000, CRC(9773e512) SHA1(33c1687ee575d66bf0e98add45d06da827813765) )
	1225	ROM_LOAD( "1o.rom", 0x18000, 0x8000, CRC(d045549b) SHA1(0c12077d3ddc2ce6aa45a0224ad5540f3f218446) )
	1226	ROM_LOAD( "1p.rom", 0x20000, 0x8000, CRC(d0af35c5) SHA1(c5a89f4d73acc0db86654540b3abfd77b3757db5) )
	1227	ROM_LOAD( "1q.rom", 0x28000, 0x8000, CRC(7b5369a8) SHA1(1307b26d80e6f36ebe6c442bebec41d20066eaf9) )
	1228	/* 0x30000-0x3ffff empty */
	1229	ROM_LOAD( "1f.rom", 0x40000, 0x8000, CRC(6b61a413) SHA1(44eddf12fb46fceca2addbe6da929aaea7636b13) ) /* 2nd plane */
	1230	ROM_LOAD( "1g.rom", 0x48000, 0x8000, CRC(b5492d97) SHA1(d5b045e3ebaa44809757a4220cefb3c6815470da) )
	1231	ROM_LOAD( "1h.rom", 0x50000, 0x8000, CRC(d69762d5) SHA1(3326fef4e0bd86681a3047dc11886bb171ecb609) )
	1232	ROM_LOAD( "1i.rom", 0x58000, 0x8000, CRC(9f243b68) SHA1(32dce8d311a4be003693182a999e4053baa6bb0a) )
	1233	ROM_LOAD( "1j.rom", 0x60000, 0x8000, CRC(66e9438c) SHA1(b94e62b6fbe7f4e08086d0365afc5cff6e0ccafd) )
	1234	ROM_LOAD( "1k.rom", 0x68000, 0x8000, CRC(9ef863ad) SHA1(29f91b5a3765e4d6e6c3382db1d8d8297b6e56c8) )
	1235	/* 0x70000-0x7ffff empty */
	1236
	1237	ROM_REGION( 0x0100, REGION_PROMS, 0 )
	1238	ROM_LOAD( "a71-25.41", 0x0000, 0x0100, CRC(2d0f8545) SHA1(089c31e2f614145ef2743164f7b52ae35bc06808) ) /* video timing */
	1239	ROM_END
	1240
1206	1241	ROM_START( sboblbob )
1207	1242	ROM_REGION( 0x30000, REGION_CPU1, 0 )
1208	1243	ROM_LOAD( "bbb-3.rom", 0x00000, 0x08000, CRC(f304152a) SHA1(103d9beddccef289ed739d28ebda69bbad3d42f9) )
r1103	r1104
1237	1272	ROM_LOAD( "a71-25.41", 0x0000, 0x0100, CRC(2d0f8545) SHA1(089c31e2f614145ef2743164f7b52ae35bc06808) ) /* video timing */
1238	1273	ROM_END
1239	1274
	1275
	1276
1240	1277	ROM_START( bub68705 )
1241	1278	ROM_REGION( 0x30000, REGION_CPU1, 0 ) /* Program roms match Bubble Bobble (older) */
1242	1279	ROM_LOAD( "2.bin", 0x00000, 0x08000, CRC(32c8305b) SHA1(6bf69b3edfbefd33cd670a762b4bf0b39629a220) )
r1103	r1104
1311	1348	GAME( 1986, bubbobr1, bublbobl, bublbobl, bublbobl, bublbobl, ROT0, "Taito America Corporation (Romstar license)", "Bubble Bobble (US)", 0 )
1312	1349
1313	1350	GAME( 1986, boblbobl, bublbobl, boblbobl, boblbobl, bublbobl, ROT0, "bootleg", "Bobble Bobble", 0 )
1314		GAME( 1986, sboblbob, bublbobl, boblbobl, sboblbob, bublbobl, ROT0, "bootleg", "Super Bobble Bobble", 0 )
	1351	GAME( 1986, sboblboa, bublbobl, boblbobl, boblbobl, bublbobl, ROT0, "bootleg", "Super Bobble Bobble (set 1)", 0 )
	1352	GAME( 1986, sboblbob, bublbobl, boblbobl, sboblbob, bublbobl, ROT0, "bootleg", "Super Bobble Bobble (set 2)", 0 )
1315	1353	GAME( 1986, bub68705, bublbobl, bub68705, bublbobl, bublbobl, ROT0, "bootleg", "Bubble Bobble (bootleg with 68705)", 0 )

src/mame/drivers/seibuspi.c
r1103	r1104
719	719	static UINT8 fifoout_data[FIFO_SIZE];
720	720	static int fifoout_read_request = 0;
721	721
	722	static UINT8 sb_coin_latch = 0;
	723
722	724	static UINT8 z80_fifoout_pop(void)
723	725	{
724	726	UINT8 r;
r1103	r1104
791	793	fifoin_read_request = 1;
792	794	}
793	795
	796	static READ32_HANDLER( sb_coin_r )
	797	{
	798	UINT8 r = sb_coin_latch;
794	799
	800	sb_coin_latch = 0;
	801	return r;
	802	}
795	803
	804	static WRITE8_HANDLER( sb_coin_w )
	805	{
	806	if (data)
	807	sb_coin_latch = 0xa0 \| data;
	808	else
	809	sb_coin_latch = 0;
	810	}
	811
796	812	static READ32_HANDLER( sound_fifo_r )
797	813	{
798	814	UINT8 r = z80_fifoout_pop();
r1103	r1104
817	833	return r \| 1;
818	834	}
819	835
	836	static READ32_HANDLER( spi_int_r )
	837	{
	838	cpunum_set_input_line( 0, 0,CLEAR_LINE );
	839	return 0xffffffff;
	840	}
820	841
821
822	842	static READ32_HANDLER( spi_unknown_r )
823	843	{
824	844	return 0xffffffff;
r1103	r1104
1019	1039	AM_RANGE(0x00000490, 0x00000493) AM_WRITE(video_dma_length_w)
1020	1040	AM_RANGE(0x00000494, 0x00000497) AM_WRITE(video_dma_address_w)
1021	1041	AM_RANGE(0x0000050c, 0x0000050f) AM_WRITE(sprite_dma_start_w)
1022		AM_RANGE(0x00000600, 0x00000603) AM_READ(spi_un~~known~~_r) /* Un~~known~~ */
	1042	AM_RANGE(0x00000600, 0x00000603) AM_READ(spi_int_r) /* Clear Interrupt */
1023	1043	AM_RANGE(0x00000600, 0x00000603) AM_WRITENOP /* Unknown */
1024	1044	AM_RANGE(0x00000604, 0x00000607) AM_READ(spi_controls1_r) /* Player controls */
1025	1045	AM_RANGE(0x00000608, 0x0000060b) AM_READ(spi_unknown_r) /* Unknown */
r1103	r1104
1041	1061	AM_RANGE(0x0000, 0x3fff) AM_RAMBANK(5)
1042	1062	AM_RANGE(0x4002, 0x4002) AM_WRITENOP /* ack RST 10 */
1043	1063	AM_RANGE(0x4003, 0x4003) AM_WRITENOP /* Unknown */
	1064	AM_RANGE(0x4004, 0x4004) AM_WRITE(sb_coin_w) /* single board systems */
1044	1065	AM_RANGE(0x4008, 0x4008) AM_READWRITE(z80_soundfifo_r, z80_soundfifo_w)
1045	1066	AM_RANGE(0x4009, 0x4009) AM_READ(z80_soundfifo_status_r)
1046	1067	AM_RANGE(0x400a, 0x400a) AM_READ(z80_jp1_r)
r1103	r1104
1111	1132	AM_RANGE(0x00000490, 0x00000493) AM_WRITE(video_dma_length_w)
1112	1133	AM_RANGE(0x00000494, 0x00000497) AM_WRITE(video_dma_address_w)
1113	1134	AM_RANGE(0x0000050c, 0x0000050f) AM_WRITE(sprite_dma_start_w)
	1135	AM_RANGE(0x00000600, 0x00000603) AM_READ(spi_int_r) /* Unknown */
1114	1136	AM_RANGE(0x00000604, 0x00000607) AM_READ(spi_controls1_r) /* Player controls */
1115	1137	AM_RANGE(0x00000608, 0x0000060b) AM_READ(spi_unknown_r)
1116	1138	AM_RANGE(0x0000060c, 0x0000060f) AM_READ(spi_controls2_r) /* Player controls (start) */
r1103	r1104
1704	1726
1705	1727	static INTERRUPT_GEN( spi_interrupt )
1706	1728	{
1707		cpunum_set_input_line( 0, 0, ~~PUL~~SE_LINE );
	1729	cpunum_set_input_line( 0, 0, ASSERT_LINE );
1708	1730	}
1709	1731
1710	1732	static int spi_irq_callback(int irq)
r1103	r1104
1799	1821	memcpy(z80_rom, rom, 0x40000);
1800	1822
1801	1823	memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x0000068c, 0x0000068f, 0, 0, eeprom_w);
	1824	memory_install_read32_handler(0, ADDRESS_SPACE_PROGRAM, 0x00000680, 0x00000683, 0, 0, sb_coin_r);
1802	1825	cpunum_set_irq_callback(0, spi_irq_callback);
	1826
	1827	sb_coin_latch = 0;
1803	1828	}
1804	1829
1805	1830	static MACHINE_DRIVER_START( sxx2f ) /* Intel i386DX @ 25MHz, YMF271 @ 16.9344MHz, Z80 @ 7.159MHz(?) */
r1103	r1104
1822	1847	MDRV_SOUND_REPLACE("audio", YMF271, 16384000) /* 16.3840MHz */
1823	1848	MDRV_SOUND_CONFIG(ymf271_interface)
1824	1849
	1850	MDRV_SOUND_ROUTE(0, "left", 1.0)
	1851	MDRV_SOUND_ROUTE(1, "right", 1.0)
	1852
1825	1853	MDRV_MACHINE_RESET(sxx2f)
1826	1854	MDRV_NVRAM_HANDLER(sxx2f)
1827	1855
r1103	r1104
1934	1962	if (activecpu_get_pc()==0x0206082) cpu_spinuntil_int(); // idle
1935	1963
1936	1964	/* rfjetus */
1937		if (activecpu_get_pc()==0x0205b39) cpu_spinuntil_int(); // idle
	1965	if (activecpu_get_pc()==0x0205b39)
	1966	{
	1967	UINT32 r;
	1968	cpu_spinuntil_int(); // idle
	1969	// Hack to enter test mode
	1970	r = spimainram[(0x002894c-0x800)/4] & (~0x400);
	1971	return r \| (((readinputport(2) ^ 0xFF)<<8) & 0x400);
	1972	}
1938	1973
1939	1974	/* rfjetj */
1940	1975	if (activecpu_get_pc()==0x0205f2e) cpu_spinuntil_int(); // idle
r1103	r1104
3019	3054	/* there is another rf dump rf_spi_asia.zip but it seems strange, 1 program rom, cart pic seems to show others as a different type of rom */
3020	3055
3021	3056	/* SXX2F */
3022		GAME( 1997, rdft2us, rdft2, sxx2f, spi_2button, rdft2us, ROT270, "Seibu Kaihatsu (Fabtek license)", "Raiden Fighters 2.1 (US, Single Board)", GAME_IMPERFECT_GRAPHICS\|GAME_NO_SOUND ) // title screen shows '2.1'
	3057	GAME( 1997, rdft2us, rdft2, sxx2f, spi_2button, rdft2us, ROT270, "Seibu Kaihatsu (Fabtek license)", "Raiden Fighters 2.1 (US, Single Board)", GAME_IMPERFECT_GRAPHICS\|GAME_IMPERFECT_SOUND ) // title screen shows '2.1'
3023	3058
3024	3059	/* SXX2G */
3025	3060	GAME( 1999, rfjetus, rfjet, sxx2g, spi_2button, rfjet, ROT270, "Seibu Kaihatsu (Fabtek license)", "Raiden Fighters Jet (US, Single Board)", GAME_IMPERFECT_GRAPHICS\|GAME_IMPERFECT_SOUND ) // has 1998-99 copyright + planes unlocked

src/mame/drivers/tetriunk.c
r1103	r1104
152	152	int i;
153	153	for(i=0;i<16;i++)
154	154	{
155		palette_set_color(machine,i,tmpcolors[3*i]);
	155	palette_set_color(machine,i,tmpcolors[i]);
156	156	}
157	157	}
158	158

src/mame/drivers/dynax.c
r1103	r1104
10	10	Custom: TC17G032AP-0246 (blitter)
11	11
12	12	---------------------------------------------------------------------------------------------------------------------
13		Year + Game Board~~(s)~~ Sound Clock Palette Notes
	13	Year + Game Main Board Sub Board Sound Clock Palette Notes
14	14	---------------------------------------------------------------------------------------------------------------------
15		88 Hana no Mai D1610088L1 AY8912 YM2203 M5205 PROM
16		88 Hana Kochou D201901L2 + D201901L1-0 AY8912 YM2203 M5205 PROM
17		89 Hana Oriduru D2304268L AY8912 YM2413 M5205 RAM
18		89 Dragon Punch D24? YM2203 PROM
19		89 Mahjong Friday D2607198L1 YM2413 PROM
20		89 Sports Match D31? YM2203 PROM
21		90 Jong Tou Ki D1505178-A + D2711078L-B AY8912 YM2203 M5205 PROM 2 x Z80, 2 x blitter
22		90 Mahjong Campus Hunting D3312108L1-1 + D23SUB1 AY8912 YM2413 M5205 RAM
23		90 7jigen no Youseitachi D3707198L1 + D23SUB1 AY8912 YM2413 M5205 RAM
24		90 Mahjong Electron Base AY8912 YM2413 RAM
25		90 Mahjong X-Tal/Diamond 7 D4005208L1-1 + D23SUB AY8912 YM2413 M5205 RAM
26		90 Neruton Haikujiradan D4005208L1-1 + D4508308L-2 AY8912 YM2413 M5205 RAM
27		91 Mahjong Yarunara D5512068L1-1 + D4508308L-2 AY8912 YM2413 M5205 M6242 RAM NL-001
28		91 Mahjong Angels D5512068L1-1 + D6107068L-1 AY8912 YM2413 M5205 RAM
29		91 Mahjong Comic Gekijou Vol.1 D5512068L1-1 + D6107068L-1 AY8912 YM2413 M5205 M6242 RAM NL-001, Battery
30		91 Mahjong Dial Q2 D5212298L-1 YM2413 PROM
31		91 Mahjong Tenkaigen AY8910 YM2413 M6242 RAM TMP91P640, protecttion, Battery
32		92 Quiz TV Gassyuukoku Q&Q D5512068L1-2 + D6410288L-1 AY8912 YM2413 M5205 RAM
33		94 Mahjong Reach (bootleg) bootleg AY8910 YM2413 M6242 PROM TMP91P640, Battery
34		94 Maya YM2203 PROM
35		96 Mahjong Raijinhai DX D10010318L1 + D10502168 AY8910 M6242 PROM undumped TMP91P640 code, Battery
36		9? Inca YM2203 PROM
	15	88 Hana no Mai D1610088L1 AY8912 YM2203 M5205 PROM
	16	88 Hana Kochou D201901L2 D201901L1-0 AY8912 YM2203 M5205 PROM
	17	89 Hana Oriduru D2304268L AY8912 YM2413 M5205 RAM
	18	89 Dragon Punch D24? YM2203 PROM
	19	89 Mahjong Friday D2607198L1 YM2413 PROM
	20	89 Sports Match D31? YM2203 PROM
	21	90 Jong Tou Ki D1505178-A D2711078L-B AY8912 YM2203 M5205 PROM 2 x Z80, 2 x blitter
	22	90 Mahjong Campus Hunting D3312108L1-1 D23SUB1 AY8912 YM2413 M5205 RAM
	23	90 Hanajingi D3312108L1-2 ? AY8912 YM2413 M5205 ? no dumped code
	24	90 7jigen no Youseitachi D3707198L1 D23SUB1 AY8912 YM2413 M5205 RAM
	25	90 Mahjong Electron Base AY8912 YM2413 RAM
	26	90 Mahjong X-Tal/Diamond 7 D4005208L1-1 D23SUB AY8912 YM2413 M5205 RAM
	27	90 Neruton Haikujiradan D4005208L1-1 D4508308L-2 AY8912 YM2413 M5205 RAM
	28	91 Mahjong Dial Q2 D5212298L-1 YM2413 PROM
	29	91 Mahjong Yarunara D5512068L1-1 D4508308L-2 AY8912 YM2413 M5205 M6242 RAM NL-001
	30	91 Hana wo Yaraneba! D5512068L1-1 D4508308L-2 AY8912 YM2413 M5205 M6242 RAM NL-001, TC17G032AP-0246, Battery
	31	91 Mahjong Angels D5512068L1-1 D6107068L-1 AY8912 YM2413 M5205 RAM
	32	91 Mahjong Comic Gekijou Vol.1 D5512068L1-1 D6107068L-1 AY8912 YM2413 M5205 M6242 RAM NL-001, Battery
	33	91 Mahjong Tenkaigen AY8910 YM2413 M6242 RAM TMP91P640, protection, Battery
	34	92 Quiz TV Gassyuukoku Q&Q D5512068L1-2 D6410288L-1 AY8912 YM2413 M5205 RAM
	35	92 Hanafuda Hana Tengoku D6502208L1 D6107068L-1 AY8910 YM2413 M6242 RAM
	36	94 Mahjong Reach (bootleg) bootleg AY8910 YM2413 M6242 PROM TMP91P640, Battery
	37	94 Maya YM2203 PROM
	38	96 Mahjong Raijinhai DX D10010318L1 D10502168 AY8910 M6242 PROM undumped TMP91P640 code, Battery
	39	9? Inca YM2203 PROM
37	40	---------------------------------------------------------------------------------------------------------------------
38	41
39	42	Notes:
40	43
41		- In some games (drgpunch etc) there's a more complete service mode. To enter
42		it, set the service mode dip switch and reset keeping start1 pressed.
	44	- In some games (drgpunch,hanamai,hnoridur etc) there's a more complete service mode.
	45	To enter it, set the service mode dip switch and reset keeping start1 pressed.
43	46	In hnkochou, keep F2 pressed and reset.
44	47
45	48	- sprtmtch and drgpunch are "clones", but the gfx are very different; sprtmtch
r1103	r1104
53	56
54	57	TODO:
55	58
56		- Inputs are grossly mapped, especially for the card games.
57
58		- In the interleaved games, "reverse write" test in service mode is wrong due to
59		interleaving. Correct behaviour? None of these games has a "flip screen" dip
60		switch, while mjfriday and mjdialq2, which aren't interleaved, have it.
61
62	59	- Palette banking is not correct, see quiztvqq cross hatch test.
63	60
64	61	- Scrolling / wrap enable is not correct in hnoridur type hardware. See the dynax
r1103	r1104
250	247
251	248	static READ8_HANDLER( hanamai_keyboard_1_r )
252	249	{
253		return 0x3f;
	250	int res = 0x3f;
	251
	252	/* the game reads all rows at once (keyb = 0) to check if a key is pressed */
	253	if (~keyb & 0x01) res &= readinputport(8);
	254	if (~keyb & 0x02) res &= readinputport(9);
	255	if (~keyb & 0x04) res &= readinputport(10);
	256	if (~keyb & 0x08) res &= readinputport(11);
	257	if (~keyb & 0x10) res &= readinputport(12);
	258
	259	return res;
254	260	}
255	261
256	262	static WRITE8_HANDLER( hanamai_keyboard_w )
r1103	r1104
443	449	{
444	450	hnoridur_layer_half2_w(0,data >> 1);
445	451	}
446		WRITE8_HANDLER( nanajign_layer_half_w )
447		{
448		hanamai_layer_half_w(0,~data);
449		}
450	452
451
452	453	static ADDRESS_MAP_START( sprtmtch_mem_map, ADDRESS_SPACE_PROGRAM, 8 )
453	454	AM_RANGE( 0x0000, 0x6fff ) AM_ROM
454	455	AM_RANGE( 0x7000, 0x7fff ) AM_RAM AM_BASE(&generic_nvram) AM_SIZE(&generic_nvram_size)
r1103	r1104
554	555	AM_RANGE( 0x22, 0x22 ) AM_READ ( hanamai_keyboard_1_r ) // P2
555	556	AM_RANGE( 0x23, 0x23 ) AM_READ ( hanamai_keyboard_0_r ) // P1
556	557	AM_RANGE( 0x24, 0x24 ) AM_READ ( input_port_1_r ) // DSW2
557		AM_RANGE( 0x25, 0x25 ) AM_READ ( input_port_9_r ) // DSW4
558		AM_RANGE( 0x26, 0x26 ) AM_READ ( input_port_8_r ) // DSW3
	558	AM_RANGE( 0x25, 0x25 ) AM_READ ( input_port_14_r ) // DSW4
	559	AM_RANGE( 0x26, 0x26 ) AM_READ ( input_port_13_r ) // DSW3
559	560	AM_RANGE( 0x30, 0x30 ) AM_WRITE ( adpcm_reset_w ) // MSM5205 reset
560	561	AM_RANGE( 0x32, 0x32 ) AM_WRITE ( adpcm_data_w ) // MSM5205 data
561	562	AM_RANGE( 0x34, 0x34 ) AM_WRITE ( YM2413_register_port_0_w ) // YM2413
r1103	r1104
736	737	AM_RANGE( 0x56, 0x56 ) AM_WRITE ( dynax_vblank_ack_w ) // VBlank IRQ Ack
737	738	AM_RANGE( 0x57, 0x57 ) AM_READ ( ret_ff ) // ?
738	739	AM_RANGE( 0x60, 0x60 ) AM_WRITE ( dynax_flipscreen_w ) // Flip Screen
739		AM_RANGE( 0x61, 0x61 ) AM_WRITE ( nanajign_layer_half_w ) // half of the interleaved layer to write to
	740	AM_RANGE( 0x61, 0x61 ) AM_WRITE ( hanamai_layer_half_w ) // half of the interleaved layer to write to
740	741	AM_RANGE( 0x62, 0x62 ) AM_WRITE ( hnoridur_layer_half2_w ) //
741	742	AM_RANGE( 0x67, 0x67 ) AM_WRITE ( dynax_blitter_ack_w ) // Blitter IRQ Ack
742	743	AM_RANGE( 0x70, 0x70 ) AM_WRITE ( dynax_coincounter_0_w ) // Coin Counters
r1103	r1104
814	815	AM_RANGE( 0x13, 0x13 ) AM_READ ( hanamai_keyboard_0_r ) // P1
815	816	AM_RANGE( 0x14, 0x14 ) AM_READ ( input_port_0_r ) // DSW1
816	817	AM_RANGE( 0x15, 0x15 ) AM_READ ( input_port_1_r ) // DSW2
817		AM_RANGE( 0x16, 0x16 ) AM_READ ( input_port_8_r ) // DSW3
	818	AM_RANGE( 0x16, 0x16 ) AM_READ ( input_port_13_r ) // DSW3
818	819	// AM_RANGE( 0x20, 0x21 ) AM_WRITE ( MWA8_NOP ) // CRT Controller
819	820	AM_RANGE( 0x31, 0x37 ) AM_WRITE ( dynax_blitter_rev2_w ) // Blitter
820	821	AM_RANGE( 0x40, 0x40 ) AM_WRITE ( dynax_coincounter_0_w ) // Coin Counter
r1103	r1104
953	954
954	955	static READ8_HANDLER( mjelctrn_keyboard_1_r )
955	956	{
956		return (hanamai_keyboard_1_r(0) & 0x3f) \| (readinputport(10) ? 0x40 : 0);
	957	return (hanamai_keyboard_1_r(0) & 0x3f) \| (readinputport(15) ? 0x40 : 0);
957	958	}
958	959
959	960	static READ8_HANDLER( mjelctrn_dsw_r )
960	961	{
961	962	int dsw = (keyb & 0xc0) >> 6;
962		if (dsw >= 2) dsw = dsw - 2 + 8; // 0-3 -> IN0,IN1,IN8,IN9
	963	if (dsw >= 2) dsw = dsw - 2 + 13; // 0-3 -> IN0,IN1,IN13,IN14
963	964	return readinputport(dsw);
964	965	}
965	966
r1103	r1104
1009	1010
1010	1011
1011	1012	/***************************************************************************
	1013	Hanafuda Hana Tengoku
	1014	***************************************************************************/
	1015
	1016	static UINT8 htengoku_select, htengoku_dsw, htengoku_ip, htengoku_coins, htengoku_hopper;
	1017	static WRITE8_HANDLER( htengoku_select_w )
	1018	{
	1019	htengoku_select = data;
	1020	htengoku_ip = 0;
	1021	}
	1022
	1023	static WRITE8_HANDLER( htengoku_dsw_w )
	1024	{
	1025	htengoku_dsw = data;
	1026	}
	1027	static READ8_HANDLER( htengoku_dsw_r )
	1028	{
	1029
	1030	if (!(htengoku_dsw & 0x01)) return readinputport(11);
	1031	if (!(htengoku_dsw & 0x02)) return readinputport(12);
	1032	if (!(htengoku_dsw & 0x04)) return readinputport(13);
	1033	if (!(htengoku_dsw & 0x08)) return readinputport(14);
	1034	if (!(htengoku_dsw & 0x10)) return readinputport(15);
	1035	logerror("%06x: warning, unknown bits read, htengoku_dsw = %02x\n", activecpu_get_pc(), htengoku_dsw);
	1036
	1037	return 0xff;
	1038	}
	1039
	1040	static WRITE8_HANDLER( htengoku_coin_w )
	1041	{
	1042	switch ( htengoku_select )
	1043	{
	1044	case 0x0c:
	1045	// bit 0 = coin counter
	1046	// bit 1 = out counter
	1047	// bit 2 = hopper
	1048	coin_counter_w(0, data & 1);
	1049	htengoku_hopper = data & 0x04;
	1050	#ifdef MAME_DEBUG
	1051	// popmessage("COINS %02x",data);
	1052	#endif
	1053	htengoku_coins = data;
	1054
	1055	case 0x0d: break; // ff resets input port sequence?
	1056
	1057	case 0xff: break; // CRT controller?
	1058	default:
	1059	logerror("%04x: coins_w with select = %02x, data = %02x\n",activecpu_get_pc(),htengoku_select,data);
	1060	}
	1061	}
	1062
	1063	static READ8_HANDLER( htengoku_input_r )
	1064	{
	1065	switch( htengoku_select )
	1066	{
	1067	case 0x81: return readinputport(1 + 5 + htengoku_ip++);
	1068	case 0x82: return readinputport(1 + htengoku_ip++);
	1069	case 0x0d: return 0xff; // unused
	1070	}
	1071	logerror("%04x: input_r with select = %02x\n",activecpu_get_pc(),htengoku_select);
	1072	return 0xff;
	1073	}
	1074
	1075	static READ8_HANDLER( htengoku_coin_r )
	1076	{
	1077	switch( htengoku_select )
	1078	{
	1079	case 0x00: return readinputport(0);
	1080	case 0x01: return 0xff; //?
	1081	case 0x02: return 0xbf \| ((htengoku_hopper && !(cpu_getcurrentframe()%10)) ? 0 : (1<<6));; // bit 7 = blitter busy, bit 6 = hopper
	1082	case 0x03: return htengoku_coins;
	1083	}
	1084	logerror("%04x: coin_r with select = %02x\n",activecpu_get_pc(),htengoku_select);
	1085	return 0xff;
	1086	}
	1087
	1088	static WRITE8_HANDLER( htengoku_rombank_w )
	1089	{
	1090	UINT8 rom = memory_region(REGION_CPU1) + 0x10000 + 0x8000 (data & 0x7);
	1091	memory_set_bankptr(1, rom);
	1092
	1093	hnoridur_bank = data;
	1094	}
	1095
	1096	static WRITE8_HANDLER( htengoku_blit_romregion_w )
	1097	{
	1098	switch(data)
	1099	{
	1100	case 0x80: dynax_blit_romregion_w(0,0); return;
	1101	case 0x81: dynax_blit_romregion_w(0,1); return;
	1102	case 0x00: dynax_blit_romregion_w(0,2); return;
	1103	}
	1104	logerror("%04x: unmapped romregion=%02X\n",activecpu_get_pc(),data);
	1105	}
	1106
	1107	static READ8_HANDLER( unk_r )
	1108	{
	1109	return 0x78;
	1110	}
	1111
	1112	static ADDRESS_MAP_START( htengoku_io_map, ADDRESS_SPACE_IO, 8 )
	1113	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
	1114	AM_RANGE( 0x01, 0x07 ) AM_WRITE ( dynax_blitter_rev2_w ) // Blitter
	1115	AM_RANGE( 0x20, 0x20 ) AM_WRITE ( htengoku_select_w ) // Controls
	1116	AM_RANGE( 0x21, 0x21 ) AM_WRITE ( htengoku_coin_w ) //
	1117	AM_RANGE( 0x22, 0x22 ) AM_READ ( htengoku_coin_r ) //
	1118	AM_RANGE( 0x23, 0x23 ) AM_READ ( htengoku_input_r ) //
	1119	AM_RANGE( 0x40, 0x40 ) AM_WRITE ( AY8910_control_port_0_w ) // AY8910
	1120	AM_RANGE( 0x42, 0x42 ) AM_READ ( AY8910_read_port_0_r ) //
	1121	AM_RANGE( 0x44, 0x44 ) AM_WRITE ( AY8910_write_port_0_w ) //
	1122	AM_RANGE( 0x46, 0x46 ) AM_WRITE ( YM2413_register_port_0_w ) // YM2413
	1123	AM_RANGE( 0x47, 0x47 ) AM_WRITE ( YM2413_data_port_0_w ) //
	1124	AM_RANGE( 0x80, 0x8f ) AM_READWRITE( msm6242_r, msm6242_w ) // 6242RTC
	1125	AM_RANGE( 0xa0, 0xa3 ) AM_WRITE ( ddenlovr_palette_base_w ) // ddenlovr mixer chip
	1126	AM_RANGE( 0xa4, 0xa7 ) AM_WRITE ( ddenlovr_palette_mask_w )
	1127	AM_RANGE( 0xa8, 0xab ) AM_WRITE ( ddenlovr_transparency_pen_w )
	1128	AM_RANGE( 0xac, 0xaf ) AM_WRITE ( ddenlovr_transparency_mask_w )
	1129	// b0-b3 ?
	1130	AM_RANGE( 0xb4, 0xb4 ) AM_WRITE ( ddenlovr_bgcolor_w )
	1131	AM_RANGE( 0xb5, 0xb5 ) AM_WRITE ( ddenlovr_priority_w )
	1132	AM_RANGE( 0xb6, 0xb6 ) AM_WRITE ( ddenlovr_layer_enable_w )
	1133	AM_RANGE( 0xb8, 0xb8 ) AM_READ ( unk_r ) // ? must be 78 on startup
	1134	AM_RANGE( 0xc2, 0xc2 ) AM_WRITE ( htengoku_rombank_w ) // BANK ROM Select
	1135	AM_RANGE( 0xc0, 0xc0 ) AM_WRITE ( dynax_extra_scrollx_w ) // screen scroll X
	1136	AM_RANGE( 0xc1, 0xc1 ) AM_WRITE ( dynax_extra_scrolly_w ) // screen scroll Y
	1137	AM_RANGE( 0xc3, 0xc3 ) AM_WRITE ( dynax_vblank_ack_w ) // VBlank IRQ Ack
	1138	AM_RANGE( 0xc4, 0xc4 ) AM_WRITE ( dynax_blit_pen_w ) // Destination Pen
	1139	AM_RANGE( 0xc5, 0xc5 ) AM_WRITE ( dynax_blit_dest_w ) // Destination Layer
	1140	AM_RANGE( 0xc6, 0xc6 ) AM_WRITE ( htengoku_blit_romregion_w ) // Blitter ROM bank
	1141	AM_RANGE( 0xe0, 0xe0 ) AM_WRITE ( yarunara_flipscreen_w )
	1142	AM_RANGE( 0xe1, 0xe1 ) AM_WRITE ( yarunara_layer_half_w ) // half of the interleaved layer to write to
	1143	AM_RANGE( 0xe2, 0xe2 ) AM_WRITE ( yarunara_layer_half2_w ) //
	1144	AM_RANGE( 0xe5, 0xe5 ) AM_WRITE ( dynax_blitter_ack_w ) // Blitter IRQ Ack
	1145	ADDRESS_MAP_END
	1146
	1147
	1148	/***************************************************************************
1012	1149	Mahjong Tenkaigen
1013	1150	***************************************************************************/
1014	1151
r1103	r1104
1217	1354	logerror("%04x: unmapped offset %04X=%02X written with rombank=%02X\n",activecpu_get_pc(),offset,data,rombank);
1218	1355	}
1219	1356
1220		static WRITE8_HANDLER( tenkai_layer_half_w )
1221		{
1222		hanamai_layer_half_w(0,(~data) >> 1);
1223		}
1224
1225		static WRITE8_HANDLER( tenkai_flipscreen_w )
1226		{
1227		dynax_flipscreen_w(0,(data&2)?0:1);
1228		}
1229
1230	1357	static int tenkai_6c, tenkai_70;
1231	1358	static void tenkai_show_6c(void)
1232	1359	{
r1103	r1104
1271	1398	AM_RANGE( 0x10050, 0x10050 ) AM_WRITE( tenkai_priority_w ) // layer priority and enable
1272	1399	AM_RANGE( 0x10054, 0x10054 ) AM_WRITE( dynax_blit_backpen_w ) // Background Color
1273	1400	AM_RANGE( 0x10058, 0x10058 ) AM_WRITE( tenkai_blit_romregion_w ) // Blitter ROM bank
1274		AM_RANGE( 0x10060, 0x10060 ) AM_WRITE( tenkai_flipscreen_w ) // Flip Screen
1275		AM_RANGE( 0x10064, 0x10064 ) AM_WRITE( tenkai_layer_half_w ) // half of the interleaved layer to write to
	1401	AM_RANGE( 0x10060, 0x10060 ) AM_WRITE( yarunara_flipscreen_w ) // Flip Screen
	1402	AM_RANGE( 0x10064, 0x10064 ) AM_WRITE( yarunara_layer_half_w ) // half of the interleaved layer to write to
1276	1403	AM_RANGE( 0x10068, 0x10068 ) AM_WRITE( yarunara_layer_half2_w ) //
1277	1404	AM_RANGE( 0x1006c, 0x1006c ) AM_WRITE( tenkai_6c_w ) // ?
1278	1405	AM_RANGE( 0x10070, 0x10070 ) AM_WRITE( tenkai_70_w ) // ?
r1103	r1104
1293	1420	ADDRESS_MAP_END
1294	1421
1295	1422
	1423
1296	1424	/***************************************************************************
1297	1425
1298	1426
r1103	r1104
1301	1429
1302	1430	***************************************************************************/
1303	1431
1304		#define MAHJONG_PANEL\
1305		PORT_START_TAG("IN3")\
1306		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )\
1307		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )\
1308		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )\
1309		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M )\
1310		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )\
1311		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1)\
1312		PORT_START_TAG("IN4")\
1313		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )\
1314		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )\
1315		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )\
1316		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N )\
1317		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )\
1318		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )\
1319		PORT_START_TAG("IN5")\
1320		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )\
1321		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )\
1322		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )\
1323		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )\
1324		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )\
1325		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )\
1326		PORT_START_TAG("IN6")\
1327		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )\
1328		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )\
1329		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )\
1330		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )\
1331		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )\
1332		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )\
1333		PORT_START_TAG("IN7")\
1334		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )\
1335		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )\
1336		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )\
1337		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) /I would assume, anyway/ \
1338		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )\
	1432	INPUT_PORTS_START( MAHJONG_KEYS )
	1433	// Keyboard 1
	1434	PORT_START
	1435	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(1)
	1436	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(1)
	1437	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(1)
	1438	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(1)
	1439	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(1)
	1440	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
	1441
	1442	PORT_START
	1443	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(1)
	1444	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(1)
	1445	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(1)
	1446	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N ) PORT_PLAYER(1)
	1447	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(1)
	1448	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1449
	1450	PORT_START
	1451	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(1)
	1452	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(1)
	1453	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(1)
	1454	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(1)
	1455	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(1)
	1456	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1457
	1458	PORT_START
	1459	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(1)
	1460	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(1)
	1461	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(1)
	1462	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) PORT_PLAYER(1)
	1463	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1464	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1465
	1466	PORT_START
	1467	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(1) // "l"
	1468	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1469	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1470	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(1) // "f"
	1471	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1472	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1473
	1474	// Keyboard 2
	1475	PORT_START
	1476	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
	1477	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
	1478	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2)
	1479	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(2)
	1480	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
	1481	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
	1482
	1483	PORT_START
	1484	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2)
	1485	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2)
	1486	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
	1487	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N ) PORT_PLAYER(2)
	1488	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
	1489	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1490
	1491	PORT_START
	1492	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
	1493	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
	1494	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
	1495	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(2)
	1496	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
	1497	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1498
	1499	PORT_START
	1500	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
	1501	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
	1502	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
	1503	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) PORT_PLAYER(2)
	1504	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1505	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1506
	1507	PORT_START
	1508	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
	1509	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1510	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1511	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(2) // "f"
	1512	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1513	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1514	INPUT_PORTS_END
	1515
	1516	INPUT_PORTS_START( MAHJONG_KEYS_BET )
	1517	// Keyboard 1
	1518	PORT_START
	1519	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(1)
	1520	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(1)
	1521	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(1)
	1522	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(1)
	1523	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(1)
	1524	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
	1525
	1526	PORT_START
	1527	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(1)
	1528	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(1)
	1529	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(1)
	1530	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N ) PORT_PLAYER(1)
	1531	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(1)
	1532	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(1)
	1533
	1534	PORT_START
	1535	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(1)
	1536	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(1)
	1537	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(1)
	1538	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(1)
	1539	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(1)
	1540	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1541
	1542	PORT_START
	1543	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(1)
	1544	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(1)
	1545	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(1)
	1546	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) PORT_PLAYER(1)
	1547	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1548	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1549
	1550	PORT_START
	1551	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(1) // "l"
	1552	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(1) // "t"
	1553	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(1) // "w"
	1554	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(1) // "f"
	1555	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(1) // "b"
	1556	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(1) // "s"
	1557
	1558	// Keyboard 2
	1559	PORT_START
	1560	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
	1561	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
	1562	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2)
	1563	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(2)
	1564	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
	1565	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
	1566
	1567	PORT_START
	1568	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2)
	1569	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2)
	1570	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
	1571	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N ) PORT_PLAYER(2)
	1572	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
	1573	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2)
	1574
	1575	PORT_START
	1576	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
	1577	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
	1578	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
	1579	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(2)
	1580	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
	1581	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1582
	1583	PORT_START
	1584	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
	1585	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
	1586	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
	1587	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) PORT_PLAYER(2)
	1588	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1589	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1590
	1591	PORT_START
	1592	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
	1593	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
	1594	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
	1595	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(2) // "f"
	1596	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(2) // "b"
	1597	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // "s"
	1598	INPUT_PORTS_END
	1599
	1600	INPUT_PORTS_START( HANAFUDA_KEYS )
	1601	// Keyboard 1
	1602	PORT_START
	1603	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
	1604	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD)
	1605	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1606	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME(DEF_STR( Yes )) PORT_CODE(KEYCODE_M)
	1607	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1608	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
	1609
	1610	PORT_START
	1611	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
	1612	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
	1613	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1614	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME(DEF_STR( No )) PORT_CODE(KEYCODE_N)
	1615	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1616	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1617
	1618	PORT_START
	1619	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD)
	1620	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD)
	1621	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1622	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1623	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1624	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1625
	1626	PORT_START
	1627	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD)
	1628	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("8") PORT_CODE(KEYCODE_8_PAD)
	1629	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1630	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1631	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1632	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1633
	1634	PORT_START
	1635	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
	1636	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1637	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1638	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) // "f"
	1639	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1339	1640	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1340	1641
	1642	// Keyboard 2
	1643	PORT_START
	1644	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
	1645	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
	1646	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2)
	1647	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(2)
	1648	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
	1649	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
	1650
	1651	PORT_START
	1652	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2)
	1653	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2)
	1654	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
	1655	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N ) PORT_PLAYER(2)
	1656	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
	1657	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1658
	1659	PORT_START
	1660	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
	1661	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
	1662	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
	1663	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(2)
	1664	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
	1665	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1666
	1667	PORT_START
	1668	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
	1669	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
	1670	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
	1671	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) PORT_PLAYER(2)
	1672	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1673	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1674
	1675	PORT_START
	1676	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
	1677	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1678	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1679	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(2) // "f"
	1680	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1681	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1682	INPUT_PORTS_END
	1683
	1684	INPUT_PORTS_START( HANAFUDA_KEYS_BET )
	1685	// Keyboard 1
	1686	PORT_START
	1687	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
	1688	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD)
	1689	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1690	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME(DEF_STR( Yes )) PORT_CODE(KEYCODE_M)
	1691	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1692	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
	1693
	1694	PORT_START
	1695	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
	1696	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
	1697	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1698	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME(DEF_STR( No )) PORT_CODE(KEYCODE_N)
	1699	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1700	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
	1701
	1702	PORT_START
	1703	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD)
	1704	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD)
	1705	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1706	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1707	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1708	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1709
	1710	PORT_START
	1711	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD)
	1712	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("8") PORT_CODE(KEYCODE_8_PAD)
	1713	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1714	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1715	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1716	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1717
	1718	PORT_START
	1719	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(1) // "l"
	1720	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(1) // "t"
	1721	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(1) // "w"
	1722	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(1) // "f"
	1723	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(1) // "b"
	1724	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(1) // "s"
	1725
	1726	// Keyboard 2
	1727	PORT_START
	1728	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
	1729	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
	1730	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2)
	1731	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(2)
	1732	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
	1733	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
	1734
	1735	PORT_START
	1736	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2)
	1737	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2)
	1738	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
	1739	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N ) PORT_PLAYER(2)
	1740	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
	1741	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2)
	1742
	1743	PORT_START
	1744	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
	1745	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
	1746	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
	1747	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(2)
	1748	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
	1749	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1750
	1751	PORT_START
	1752	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
	1753	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
	1754	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
	1755	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) PORT_PLAYER(2)
	1756	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1757	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1758
	1759	PORT_START
	1760	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2) // "l"
	1761	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2) // "t"
	1762	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2) // "w"
	1763	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(2) // "f"
	1764	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(2) // "b"
	1765	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2) // "s"
	1766	INPUT_PORTS_END
	1767
	1768
1341	1769	INPUT_PORTS_START( hanamai )
1342	1770	PORT_START_TAG("DSW0")
1343	1771	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
r1103	r1104
1355	1783	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1356	1784	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1357	1785	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1358		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1359		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1360		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1786	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) )
	1787	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	1788	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
1361	1789	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1362	1790	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1363	1791	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r1103	r1104
1390	1818	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1391	1819
1392	1820	PORT_START_TAG("IN2")
1393		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1394		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1395		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) // Test
1396		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Analyzer
1397		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Memory Reset
1398		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1399		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
1400		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
	1821	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1822	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1823	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
	1824	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Analyzer
	1825	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Memory Reset
	1826	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1827	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
	1828	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
1401	1829
1402		PORT_START_TAG("IN3")
1403		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
1404		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD)
1405		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1406		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y)
1407		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1408		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
1409
1410		PORT_START_TAG("IN4")
1411		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
1412		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
1413		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1414		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("N") PORT_CODE(KEYCODE_N)
1415		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1416		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1417
1418		PORT_START_TAG("IN5")
1419		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD)
1420		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD)
1421		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1422		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1423		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1424		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1425
1426		PORT_START_TAG("IN6")
1427		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD)
1428		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("8") PORT_CODE(KEYCODE_8_PAD)
1429		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1430		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1431		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1432		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1433
1434		PORT_START_TAG("IN7")
1435		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1436		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1437		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1438		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
1439		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1440		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1830	PORT_INCLUDE( HANAFUDA_KEYS )
1441	1831	INPUT_PORTS_END
1442	1832
1443	1833	INPUT_PORTS_START( hnkochou )
r1103	r1104
1503	1893	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
1504	1894	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1505	1895
1506		MAHJONG_PANEL
1507
	1896	PORT_INCLUDE( HANAFUDA_KEYS_BET )
1508	1897	INPUT_PORTS_END
1509	1898
1510	1899
1511	1900	INPUT_PORTS_START( hnoridur )
1512	1901	PORT_START_TAG("DSW0") /* note that these are in reverse order wrt the others */
1513		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1514		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1515		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1516		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1517		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1518		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1519		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1520		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1521		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1522		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1523		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1524		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1902	PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coinage ) )
	1903	PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) )
	1904	PORT_DIPSETTING( 0x40, DEF_STR( 1C_2C ) )
	1905	PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) )
	1906	PORT_DIPSETTING( 0x00, DEF_STR( 1C_5C ) )
	1907	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Difficulty ) )
	1908	PORT_DIPSETTING( 0x30, DEF_STR( Easy ) )
	1909	PORT_DIPSETTING( 0x10, DEF_STR( Normal ) )
	1910	PORT_DIPSETTING( 0x20, DEF_STR( Hard ) )
	1911	PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
1525	1912	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Flip_Screen ) )
1526	1913	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1527	1914	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1528	1915	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Demo_Sounds ) )
1529	1916	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1530	1917	PORT_DIPSETTING( 0x04, DEF_STR( On ) )
1531		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
1532		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1533		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1918	PORT_DIPNAME( 0x02, 0x02, "Select Stage" )
	1919	PORT_DIPSETTING( 0x02, DEF_STR( No ) )
	1920	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
1534	1921	PORT_SERVICE( 0x01, IP_ACTIVE_LOW )
1535	1922
1536	1923	PORT_START_TAG("DSW1")
r1103	r1104
1560	1947	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1561	1948
1562	1949	PORT_START_TAG("IN2")
1563		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1564		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1565		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) // Test
1566		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Analyzer
1567		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Memory Reset
1568		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1569		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
1570		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
	1950	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1951	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1952	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
	1953	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Analyzer
	1954	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Memory Reset
	1955	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1956	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
	1957	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
1571	1958
1572		PORT_START_TAG("IN3")
1573		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
1574		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD)
1575		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1576		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y)
1577		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1578		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
	1959	PORT_INCLUDE( HANAFUDA_KEYS )
1579	1960
1580		PORT_START_TAG("IN4")
1581		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
1582		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
1583		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1584		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("N") PORT_CODE(KEYCODE_N)
1585		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1586		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1587
1588		PORT_START_TAG("IN5")
1589		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD)
1590		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("7") PORT_CODE(KEYCODE_7_PAD)
1591		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1592		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1593		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1594		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1595
1596		PORT_START_TAG("IN6")
1597		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD)
1598		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("8") PORT_CODE(KEYCODE_8_PAD)
1599		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1600		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1601		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1602		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1603
1604		PORT_START_TAG("IN7")
1605		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1606		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1607		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1608		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
1609		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1610		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1611
1612		PORT_START_TAG("IN8")
	1961	PORT_START_TAG("IN13")
1613	1962	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1614	1963	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1615	1964	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r1103	r1104
1635	1984	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1636	1985	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1637	1986
1638		PORT_START_TAG("IN9")
	1987	PORT_START_TAG("IN14")
1639	1988	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1640	1989	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1641	1990	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r1103	r1104
1784	2133	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1785	2134	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1786	2135	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1787		PORT_DIPNAME( 0x20, 0x20, "~~Gfx~~ test" )
	2136	PORT_DIPNAME( 0x20, 0x20, "Full Test" )
1788	2137	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1789	2138	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1790	2139	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
r1103	r1104
1804	2153	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
1805	2154	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "18A"
1806	2155
1807		MAHJONG_~~PAN~~EL
	2156	PORT_INCLUDE( MAHJONG_KEYS )
1808	2157	INPUT_PORTS_END
1809	2158
1810	2159
r1103	r1104
1871	2220	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
1872	2221	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "18A"
1873	2222
1874		MAHJONG_~~PAN~~EL
	2223	PORT_INCLUDE( MAHJONG_KEYS )
1875	2224	INPUT_PORTS_END
1876	2225
1877		#define MAHJONG_BOARD\
1878		PORT_START_TAG("IN3")\
1879		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )\
1880		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )\
1881		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )\
1882		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M )\
1883		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )\
1884		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )\
1885		PORT_START_TAG("IN4")\
1886		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )\
1887		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )\
1888		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )\
1889		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N )\
1890		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )\
1891		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )\
1892		PORT_START_TAG("IN5")\
1893		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )\
1894		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )\
1895		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )\
1896		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )\
1897		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )\
1898		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )\
1899		PORT_START_TAG("IN6")\
1900		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )\
1901		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )\
1902		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )\
1903		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )\
1904		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )\
1905		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1906	2226
1907	2227	INPUT_PORTS_START( yarunara )
1908	2228	PORT_START_TAG("DSW0")
r1103	r1104
1922	2242	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) )
1923	2243	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1924	2244	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
1925		PORT_DIPNAME( 0x40, 0x40, "Scrambled comm.?" )
	2245	PORT_DIPNAME( 0x40, 0x40, "Use Password" )
	2246	PORT_DIPSETTING( 0x40, DEF_STR( No ) )
	2247	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
	2248	PORT_DIPNAME( 0x80, 0x80, "Set Date" )
	2249	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	2250	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	2251
	2252	PORT_START_TAG("DSW1")
	2253	PORT_DIPNAME( 0x01, 0x01, "PINFU with TSUMO" )
	2254	PORT_DIPSETTING( 0x01, DEF_STR( No ) )
	2255	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
	2256	PORT_DIPNAME( 0x02, 0x02, "Unknown 2-1" )
	2257	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	2258	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	2259	PORT_DIPNAME( 0x04, 0x04, "Unknown 2-2" )
	2260	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	2261	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	2262	PORT_DIPNAME( 0x08, 0x08, "Unknown 2-3*" )
	2263	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	2264	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	2265	PORT_DIPNAME( 0x10, 0x10, "Unknown 2-4" )
	2266	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	2267	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	2268	PORT_DIPNAME( 0x20, 0x20, "Choose Bonus (Cheat)")
	2269	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	2270	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	2271	PORT_DIPNAME( 0x40, 0x40, "Unknown 2-6" )
1926	2272	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1927	2273	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	2274	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
	2275
	2276	PORT_START_TAG("IN2")
	2277	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "17B"
	2278	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "18B"
	2279	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
	2280	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Analyzer
	2281	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Memory Reset
	2282	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "06B"
	2283	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
	2284	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
	2285
	2286	PORT_INCLUDE( MAHJONG_KEYS )
	2287	INPUT_PORTS_END
	2288
	2289	INPUT_PORTS_START( hanayara )
	2290	PORT_START_TAG("DSW0")
	2291	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
	2292	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
	2293	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
	2294	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
	2295	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
	2296	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Difficulty ) )
	2297	PORT_DIPSETTING( 0x08, DEF_STR( Easy ) ) // 1,6
	2298	PORT_DIPSETTING( 0x0c, DEF_STR( Normal ) ) // 3,4
	2299	PORT_DIPSETTING( 0x04, DEF_STR( Hard ) ) // 5,2
	2300	PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) ) // 7,0
	2301	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Flip_Screen ) )
	2302	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	2303	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	2304	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) )
	2305	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	2306	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
	2307	PORT_DIPNAME( 0x40, 0x40, "Use Password" )
	2308	PORT_DIPSETTING( 0x40, DEF_STR( No ) )
	2309	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
1928	2310	PORT_DIPNAME( 0x80, 0x80, "Set Date" )
1929	2311	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1930	2312	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r1103	r1104
1956	2338	PORT_START_TAG("IN2")
1957	2339	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "17B"
1958	2340	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "18B"
1959		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) ~~// Test~~
	2341	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
1960	2342	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Analyzer
1961	2343	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Memory Reset
1962	2344	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // "06B"
1963	2345	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
1964	2346	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
1965	2347
1966		MAHJONG_BOARD
1967		PORT_START_TAG("IN7")
1968		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD)
1969		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("2") PORT_CODE(KEYCODE_2_PAD)
1970		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("3") PORT_CODE(KEYCODE_3_PAD)
1971		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("4") PORT_CODE(KEYCODE_4_PAD)
1972		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("5") PORT_CODE(KEYCODE_5_PAD)
1973		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("6") PORT_CODE(KEYCODE_6_PAD)
1974
1975		// Keyboard 2
1976		PORT_START_TAG("IN8")
1977		PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
1978		PORT_START_TAG("IN9")
1979		PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
1980		PORT_START_TAG("IN10")
1981		PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
1982		PORT_START_TAG("IN11")
1983		PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
1984		PORT_START_TAG("IN12")
1985		PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2348	PORT_INCLUDE( HANAFUDA_KEYS )
1986	2349	INPUT_PORTS_END
1987	2350
1988	2351	INPUT_PORTS_START( quiztvqq )
r1103	r1104
2034	2397	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
2035	2398
2036	2399	PORT_START_TAG("IN2")
2037		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2038		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2039		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // Test, during boot
2040		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
2041		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2042		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
2043		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
2044		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2400	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2401	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2402	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // Test, during boot
	2403	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2404	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2405	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
	2406	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
	2407	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2045	2408
2046	2409	PORT_START_TAG("IN3")
2047	2410	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
r1103	r1104
2139	2502	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
2140	2503	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
2141	2504
2142		MAHJONG_BOARD
2143
2144		PORT_START_TAG("IN7")
2145		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2146		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2147		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
2148		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
2149		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2150		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2505	PORT_INCLUDE( MAHJONG_KEYS )
2151	2506	INPUT_PORTS_END
2152	2507
2153	2508
r1103	r1104
2210	2565	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
2211	2566	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
2212	2567	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
2213		MAHJONG_BOARD
2214	2568
2215		PORT_START_TAG("IN7")
2216		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
2217		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
2218		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
2219		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
2220		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2221		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	2569	PORT_INCLUDE( MAHJONG_KEYS )
2222	2570
2223	2571	PORT_START_TAG("IN8")
2224	2572	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
r1103	r1104
2311	2659	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
2312	2660
2313	2661	PORT_START_TAG("IN3")
2314		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
2315		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
2316		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
2317		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M )
2318		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
	2662	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_A )
	2663	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_E )
	2664	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_I )
	2665	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_M )
	2666	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
2319	2667	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN)
2320	2668
2321	2669	PORT_START_TAG("IN4")
2322		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
2323		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
2324		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
2325		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N )
2326		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
2327		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
	2670	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_B )
	2671	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_F )
	2672	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_J )
	2673	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_N )
	2674	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
	2675	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
2328	2676
2329	2677	PORT_START_TAG("IN5")
2330		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
2331		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
2332		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
2333		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
2334		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
	2678	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_C )
	2679	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_G )
	2680	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_K )
	2681	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
	2682	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
2335	2683	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
2336	2684
2337	2685	PORT_START_TAG("IN6")
2338		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
2339		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
2340		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
2341		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
	2686	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_D )
	2687	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_H )
	2688	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_L )
	2689	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
2342	2690	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
2343	2691	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
2344	2692
r1103	r1104
2416	2764	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) // Coin
2417	2765	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) // Service
2418	2766
2419		MAHJONG_B~~OARD~~
	2767	PORT_INCLUDE( MAHJONG_KEYS_BET )
2420	2768
2421		PORT_START // IN7
2422		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE )
2423		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE )
2424		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP )
2425		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
2426		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG )
2427		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL )
2428
2429	2769	PORT_START_TAG("DSW3") // 7c22 (select = 80)
2430	2770	PORT_DIPNAME( 0x07, 0x07, "YAKUMAN Bonus" )
2431	2771	PORT_DIPSETTING( 0x07, "Cut" )
r1103	r1104
2549	2889	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) // Coin
2550	2890	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) // Service
2551	2891
2552		MAHJONG_B~~OARD~~
	2892	PORT_INCLUDE( MAHJONG_KEYS_BET )
2553	2893
2554		PORT_START_TAG("IN7")
2555		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE )
2556		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE )
2557		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP )
2558		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
2559		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG )
2560		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL )
2561
2562	2894	PORT_START_TAG("DSW3") // 7c22 (select = 80)
2563	2895	PORT_DIPNAME( 0x07, 0x07, "YAKUMAN Bonus" )
2564	2896	PORT_DIPSETTING( 0x07, "Cut" )
r1103	r1104
2682	3014	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) // Coin
2683	3015	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) // Service
2684	3016
2685		MAHJONG_B~~OARD~~
	3017	PORT_INCLUDE( MAHJONG_KEYS_BET )
2686	3018
2687		PORT_START_TAG("IN7")
2688		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE )
2689		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE )
2690		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP )
2691		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
2692		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG )
2693		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL )
2694
2695	3019	PORT_START_TAG("DSW3") // select = 80
2696	3020	PORT_DIPNAME( 0x07, 0x07, "YAKUMAN Bonus" )
2697	3021	PORT_DIPSETTING( 0x07, "Cut" )
r1103	r1104
2801	3125	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2802	3126
2803	3127	PORT_START_TAG("IN2")
2804		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 17B
2805		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18B
2806		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // Test
2807		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Analyzer
2808		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Memory Reset
2809		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 06B
2810		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) // Coin
2811		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18A
	3128	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 17B
	3129	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18B
	3130	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1) // Test
	3131	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) // Analyzer
	3132	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) // Memory Reset
	3133	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 06B
	3134	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) // Coin
	3135	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) // 18A
2812	3136
2813		MAHJONG_~~PAN~~EL
	3137	PORT_INCLUDE( MAHJONG_KEYS )
2814	3138	INPUT_PORTS_END
2815	3139
2816	3140
r1103	r1104
2956	3280	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) // Coin
2957	3281	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) // Service
2958	3282
2959		MAHJONG_BOARD
2960
2961		PORT_START
2962		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
2963		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
2964		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
2965		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) // Flip Flop
2966		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
2967		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
	3283	PORT_INCLUDE( MAHJONG_KEYS_BET )
2968	3284	INPUT_PORTS_END
2969	3285
2970	3286
r1103	r1104
3109	3425	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) // Coin
3110	3426	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) // Service
3111	3427
3112		MAHJONG_BOARD
	3428	PORT_INCLUDE( MAHJONG_KEYS_BET )
	3429	INPUT_PORTS_END
3113	3430
3114		PORT_START
3115		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) // "l"
3116		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) // "t"
3117		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) // "w"
3118		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) // Flip Flop
3119		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) // "b"
3120		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) // "s"
	3431	INPUT_PORTS_START( htengoku )
	3432	PORT_START // IN0
	3433	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE4 ) // medal out
	3434	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	3435	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
	3436	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE2 ) // analyzer
	3437	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) // data clear
	3438	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) // note
	3439	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
	3440	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
3121	3441
	3442	PORT_INCLUDE( HANAFUDA_KEYS_BET )
	3443
	3444	PORT_START // IN11 - DSW1
	3445	PORT_DIPNAME( 0x01, 0x01, "Show Girls" )
	3446	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	3447	PORT_DIPSETTING( 0x01, DEF_STR( Yes ) )
	3448	PORT_DIPNAME( 0x02, 0x02, "Select Stage" )
	3449	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	3450	PORT_DIPSETTING( 0x02, DEF_STR( Yes ) )
	3451	PORT_DIPNAME( 0x04, 0x04, "Secret Trick" )
	3452	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	3453	PORT_DIPSETTING( 0x04, DEF_STR( Yes ) )
	3454	PORT_DIPNAME( 0x08, 0x08, "Secret Character" )
	3455	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	3456	PORT_DIPSETTING( 0x08, DEF_STR( Yes ) )
	3457	PORT_DIPNAME( 0x10, 0x10, "In Game Sounds" )
	3458	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	3459	PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
	3460	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) )
	3461	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	3462	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
	3463	PORT_DIPNAME( 0x40, 0x40, "Guide" )
	3464	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	3465	PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
	3466	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Flip_Screen ) )
	3467	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	3468	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3469
	3470	PORT_START // IN12 - DSW2
	3471	PORT_DIPNAME( 0x07, 0x05, "Payout Rate" )
	3472	PORT_DIPSETTING( 0x00, "Lowest" )
	3473	PORT_DIPSETTING( 0x01, "Lower" )
	3474	PORT_DIPSETTING( 0x02, DEF_STR( Low ) )
	3475	PORT_DIPSETTING( 0x03, "Bit Low" )
	3476	PORT_DIPSETTING( 0x04, DEF_STR( Medium ) )
	3477	PORT_DIPSETTING( 0x05, DEF_STR( High ) )
	3478	PORT_DIPSETTING( 0x06, DEF_STR( Higher ) )
	3479	PORT_DIPSETTING( 0x07, DEF_STR( Highest ) )
	3480	PORT_DIPNAME( 0x08, 0x08, "Payout Wave" )
	3481	PORT_DIPSETTING( 0x00, "Small" )
	3482	PORT_DIPSETTING( 0x08, "Big" )
	3483	PORT_DIPNAME( 0x10, 0x10, "Goko Yaku" )
	3484	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	3485	PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
	3486	PORT_DIPNAME( 0x60, 0x60, "Double-Up Win Rate" )
	3487	PORT_DIPSETTING( 0x00, "65%" )
	3488	PORT_DIPSETTING( 0x20, "70%" )
	3489	PORT_DIPSETTING( 0x40, "75%" )
	3490	PORT_DIPSETTING( 0x60, "80%" )
	3491	PORT_DIPNAME( 0x80, 0x80, "Unknown 2-7" )
	3492	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	3493	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3494
	3495	PORT_START // IN13 - DSW3
	3496	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
	3497	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
	3498	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
	3499	PORT_DIPSETTING( 0x01, DEF_STR( 1C_5C ) )
	3500	PORT_DIPSETTING( 0x00, "1 Coin/10 Credits" )
	3501	PORT_DIPNAME( 0x04, 0x04, "Credits Per Note" )
	3502	PORT_DIPSETTING( 0x00, "5" )
	3503	PORT_DIPSETTING( 0x04, "10" )
	3504	PORT_DIPNAME( 0x08, 0x08, "Max Bet" )
	3505	PORT_DIPSETTING( 0x08, "5" )
	3506	PORT_DIPSETTING( 0x00, "10" )
	3507	PORT_DIPNAME( 0x30, 0x30, "Min Rate To Start" )
	3508	PORT_DIPSETTING( 0x30, "1" )
	3509	PORT_DIPSETTING( 0x20, "2" )
	3510	PORT_DIPSETTING( 0x10, "3" )
	3511	PORT_DIPSETTING( 0x00, "5" )
	3512	PORT_DIPNAME( 0xc0, 0xc0, "Credits Limit" )
	3513	PORT_DIPSETTING( 0xc0, "1000" )
	3514	PORT_DIPSETTING( 0x80, "2000" )
	3515	PORT_DIPSETTING( 0x40, "3000" )
	3516	PORT_DIPSETTING( 0x00, "5000" )
	3517
	3518	PORT_START // IN14 - DSW4
	3519	PORT_DIPNAME( 0x03, 0x03, "Odds For Goko" )
	3520	PORT_DIPSETTING( 0x03, "100" )
	3521	PORT_DIPSETTING( 0x02, "200" )
	3522	PORT_DIPSETTING( 0x01, "250" )
	3523	PORT_DIPSETTING( 0x00, "300" )
	3524	PORT_DIPNAME( 0x0c, 0x0c, "Odds For Shiko" )
	3525	PORT_DIPSETTING( 0x0c, "50" )
	3526	PORT_DIPSETTING( 0x08, "60" )
	3527	PORT_DIPSETTING( 0x04, "70" )
	3528	PORT_DIPSETTING( 0x00, "80" )
	3529	PORT_DIPNAME( 0x30, 0x30, "Odds For Ameshiko" )
	3530	PORT_DIPSETTING( 0x30, "20" )
	3531	PORT_DIPSETTING( 0x20, "30" )
	3532	PORT_DIPSETTING( 0x10, "40" )
	3533	PORT_DIPSETTING( 0x00, "50" )
	3534	PORT_DIPNAME( 0x40, 0x40, "Unknown 4-6" )
	3535	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	3536	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3537	PORT_DIPNAME( 0x80, 0x80, "Unknown 4-7" )
	3538	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	3539	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3540
	3541	PORT_START // IN15 - DSWs top bits
	3542	PORT_SERVICE( 0x01, IP_ACTIVE_LOW )
	3543	PORT_DIPNAME( 0x02, 0x02, "Set Clock" )
	3544	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	3545	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3546	PORT_DIPNAME( 0x04, 0x04, "Unknown 2-8" )
	3547	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	3548	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3549	PORT_DIPNAME( 0x08, 0x08, "Unknown 2-9" )
	3550	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	3551	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3552	PORT_DIPNAME( 0x10, 0x10, "Pay Out Type" )
	3553	PORT_DIPSETTING( 0x10, "Credit" )
	3554	PORT_DIPSETTING( 0x00, "Hopper" )
	3555	PORT_DIPNAME( 0x20, 0x20, "Hopper Switch" )
	3556	PORT_DIPSETTING( 0x20, "Active Low" )
	3557	PORT_DIPSETTING( 0x00, "Active High" )
	3558	PORT_DIPNAME( 0x40, 0x40, "Unknown 4-8" )
	3559	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	3560	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3561	PORT_DIPNAME( 0x80, 0x80, "Unknown 4-9" )
	3562	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	3563	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3122	3564	INPUT_PORTS_END
3123	3565
3124	3566
r1103	r1104
3169	3611	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
3170	3612	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
3171	3613	MDRV_SCREEN_SIZE(512, 256)
3172		MDRV_SCREEN_VISIBLE_AREA(0, 512-1, 16+8, 255-8)
	3614	MDRV_SCREEN_VISIBLE_AREA(0, 512-1-4, 16+8, 255-8)
3173	3615	MDRV_PALETTE_LENGTH(512)
3174	3616
3175	3617	MDRV_PALETTE_INIT(sprtmtch) // static palette
r1103	r1104
3223	3665	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
3224	3666	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
3225	3667	MDRV_SCREEN_SIZE(512, 256)
3226		MDRV_SCREEN_VISIBLE_AREA(0, 512-1, 16, 256-1)
	3668	MDRV_SCREEN_VISIBLE_AREA(0, 512-1-4, 16, 256-1)
3227	3669	MDRV_PALETTE_LENGTH(16*256)
3228	3670
3229	3671	MDRV_VIDEO_START(hnoridur)
r1103	r1104
3588	4030
3589	4031
3590	4032	/***************************************************************************
	4033	Hanafuda Hana Tengoku
	4034	***************************************************************************/
	4035
	4036	static struct AY8910interface htengoku_ay8910_interface =
	4037	{
	4038	// A B
	4039	htengoku_dsw_r, 0, // R
	4040	0, htengoku_dsw_w // W
	4041	};
	4042
	4043	static MACHINE_DRIVER_START( htengoku )
	4044
	4045	/* basic machine hardware */
	4046	MDRV_CPU_ADD_TAG("main",Z80,20000000 / 4)
	4047	MDRV_CPU_PROGRAM_MAP(yarunara_mem_map,0)
	4048	MDRV_CPU_IO_MAP(htengoku_io_map,0)
	4049	MDRV_CPU_VBLANK_INT(sprtmtch_vblank_interrupt,1) /* IM 0 needs an opcode on the data bus */
	4050	MDRV_CPU_PERIODIC_INT(yarunara_clock_interrupt, 60) // RTC
	4051
	4052	MDRV_NVRAM_HANDLER(generic_0fill)
	4053
	4054	MDRV_SCREEN_REFRESH_RATE(60)
	4055	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
	4056
	4057	/* video hardware */
	4058	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
	4059	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
	4060	MDRV_SCREEN_SIZE(512, 256)
	4061	MDRV_SCREEN_VISIBLE_AREA(0, 336-1, 0+8, 256-1-8)
	4062	MDRV_PALETTE_LENGTH(16*256)
	4063
	4064	MDRV_VIDEO_START(htengoku)
	4065	MDRV_VIDEO_UPDATE(ddenlovr)
	4066	MDRV_VIDEO_EOF(htengoku)
	4067
	4068	/* sound hardware */
	4069	MDRV_SPEAKER_STANDARD_MONO("mono")
	4070
	4071	MDRV_SOUND_ADD(AY8910, 20000000 / 16)
	4072	MDRV_SOUND_CONFIG(htengoku_ay8910_interface)
	4073	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.20)
	4074
	4075	MDRV_SOUND_ADD(YM2413, 3579545)
	4076	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	4077	MACHINE_DRIVER_END
	4078
	4079
	4080	/***************************************************************************
3591	4081	Mahjong Tenkaigen
3592	4082	***************************************************************************/
3593	4083
r1103	r1104
3762	4252	ROM_LOAD( "2302.21", 0x000000, 0x20000, CRC(9dde2d59) SHA1(96df4ba97ee9611d9a3c7bcaae9cd97815a7b8a5) )
3763	4253	ROM_LOAD( "2303.22", 0x020000, 0x20000, CRC(1ac59443) SHA1(e70fe6184e7090cf7229d83b87db65f7715de2a8) )
3764	4254	ROM_LOAD( "2301.20", 0x040000, 0x20000, CRC(24391ddc) SHA1(6a2e3fae4b6d0b1d8073306f37c9fdaa04b69eb8) )
3765		ROM_LOAD( "2304.1", 0x060000, 0x20000, ~~BAD_DUMP~~ CRC(97~~92d9fa~~) SHA1(~~5835d3d9~~7a5b0a6~~594654~~010c8061238cd0514f6) )
	4255	ROM_LOAD( "2304.1", 0x060000, 0x20000, CRC(3756c745) SHA1(f275a72d6e07f21148900d24a8018d03504f249f) )
3766	4256	ROM_LOAD( "2305.2", 0x080000, 0x20000, CRC(249d360a) SHA1(688fced1298c345a18314d2c88664c757a2de35c) )
3767	4257	ROM_LOAD( "2306.3", 0x0a0000, 0x20000, CRC(014a4945) SHA1(0cd747787a81226fd4937616a6ce45af731a4049) )
3768	4258	ROM_LOAD( "2307.4", 0x0c0000, 0x20000, CRC(8b6f8a2d) SHA1(c5f3ec64a7ea3edc556182f42e6da4842d88e0ba) )
r1103	r1104
4060	4550
4061	4551	/***************************************************************************
4062	4552
	4553	Hana wo Yaraneba!
	4554	(c)1991 Dynax
	4555
	4556	D5512068L1-1
	4557	CPU: Z80B
	4558	Sound: AY38912A/P YM2413 M5205
	4559	OSC: 20.0000MHz 14.31818MHz ?(near 6242)
	4560	Others: Battery, M6242B
	4561	Custom: NL-001
	4562	TC17G032AP-0246
	4563
	4564	ROMs:
	4565	5501H.2D
	4566	5502H.4D
	4567
	4568	5503H.8C
	4569	5504H.9C
	4570	5505H.10C
	4571	5506H.11C
	4572	5507H.13C
	4573	5508H.16C
	4574	5509H.17C
	4575
	4576	on Subboard D4508308L-2
	4577	5510H.2A
	4578	5511H.3A
	4579	5512H.4A
	4580	5513H.1B
	4581	5514H.2B
	4582	5515H.4B
	4583
	4584	dumped by sayu
	4585	--- Team Japump!!! ---
	4586
	4587	***************************************************************************/
	4588
	4589	ROM_START( hanayara )
	4590	ROM_REGION( 0x50000, REGION_CPU1, 0 ) // Z80 Code
	4591	ROM_LOAD( "5501h.2d", 0x00000, 0x20000, CRC(124860b7) SHA1(205459d95f876433a9ca329fe31cfe9b08023baf) )
	4592	ROM_RELOAD( 0x10000, 0x20000 )
	4593	ROM_LOAD( "5502h.4d", 0x30000, 0x20000, CRC(93407801) SHA1(63dc3419f97d86221dbdd67b5be41d713364496b) )
	4594
	4595	ROM_REGION( 0xd0000, REGION_GFX1, 0 ) // blitter data
	4596	ROM_LOAD( "5507h.13c", 0x00000, 0x80000, CRC(7de17b26) SHA1(326667063ab045ac50e850f2f7821a65317879ad) )
	4597
	4598	ROM_REGION( 0xc0000, REGION_GFX2, 0 ) // blitter data
	4599	ROM_LOAD( "5508h.16c", 0x00000, 0x20000, CRC(ced3155b) SHA1(658e3947781f1be2ee87b43952999281c66683a6) )
	4600	ROM_LOAD( "5509h.17c", 0x20000, 0x20000, CRC(ca46ed48) SHA1(0769ac0b211181b7b57033f09f72828c885186cc) )
	4601	ROM_LOAD( "5506h.11c", 0x40000, 0x20000, CRC(161058fd) SHA1(cfc21abdc036e874d34bfa3c60486a5ab87cf9cd) )
	4602	ROM_LOAD( "5505h.10c", 0x60000, 0x20000, CRC(b2ca9838) SHA1(7104697802a0466fab40414a467146a224eb6a74) )
	4603	ROM_LOAD( "5504h.9c", 0x80000, 0x20000, CRC(6ac42304) SHA1(ce822da6d61e68578c08c9f1d0af1557c64ac5ae) )
	4604	ROM_LOAD( "5503h.8c", 0xa0000, 0x20000, CRC(9276a10a) SHA1(5a68fff20631a2002509d6cace06b5a9fa0e75d2) )
	4605
	4606	ROM_REGION( 0x80000, REGION_GFX3, 0 ) // blitter data
	4607	ROM_LOAD( "5515h.4b", 0x00000, 0x80000, CRC(ca742acc) SHA1(0aab6b3bbd0a229a0d6843849704f4faf27c8f72) )
	4608
	4609	ROM_REGION( 0xa0000, REGION_GFX4, 0 ) // blitter data
	4610	ROM_LOAD( "5514h.2b", 0x00000, 0x20000, CRC(ac714bb7) SHA1(64056cbed9d0c4f68611921754c3e6a9bb14f7cc) )
	4611	ROM_LOAD( "5513h.1b", 0x20000, 0x20000, CRC(32b7bcbd) SHA1(13277ae3f158da332e69c6f4f8828dfabbf3ea0a) )
	4612	ROM_LOAD( "5512h.4a", 0x40000, 0x20000, CRC(b4220316) SHA1(b0797c9c6ab226520d29c780ea709f62e02dd268) )
	4613	ROM_LOAD( "5511h.3a", 0x60000, 0x20000, CRC(40ee77d8) SHA1(e0dd9750d8b7b7dd9695a8365bdc926bd6d9f886) )
	4614	ROM_LOAD( "5510h.2a", 0x80000, 0x20000, CRC(bb9c71e1) SHA1(21f2977196aaa27b76ee6547a08aba8da7aba76c) )
	4615	ROM_END
	4616
	4617
	4618	/***************************************************************************
	4619
4063	4620	Quiz TV Gassyuukoku Q&Q (JPN ver.)
4064	4621	(c)1992 Dynax
4065	4622
r1103	r1104
5332	5889	ROM_LOAD( "6104.1a", 0x00000, 0x80000, CRC(04eb1ce0) SHA1(670b213db190bb845c0a99e0a8b166ebff8a7ea1) )
5333	5890	ROM_END
5334	5891
	5892
5335	5893	/***************************************************************************
5336	5894
	5895	Hanajingi
	5896	(c)1990 Dynax
5337	5897
	5898	D3312108L1-2
	5899	CPU: (surface scrached SDIP64, TLCS-90?)
	5900	Sound: AY38912A/P YM2413 M5205
	5901	OSC: 22MHz 358-100(3.579545?) 384KHz
	5902	VDP: HD46505SP
	5903
	5904	ROMs:
	5905	H01.20
	5906	H02.21
	5907	H03.22
	5908	H04.1
	5909	H05.2
	5910	H06.3
	5911	H07.4
	5912	H08.5
	5913	H09.6
	5914
	5915	H10B.4A (on subboard)
	5916
	5917	dumped by sayu
	5918	--- Team Japump!!! ---
	5919
	5920	H01.20 = 2301.20 Hana Oriduru (Japan)
	5921	H02.21 = 2302.21 Hana Oriduru (Japan)
	5922	H03.22 = 2303.22 Hana Oriduru (Japan)
	5923	H04.1 = 2304.1 Hana Oriduru (Japan)
	5924	H05.2 = 2305.2 Hana Oriduru (Japan)
	5925	H06.3 = 2306.3 Hana Oriduru (Japan)
	5926	H07.4 = 2307.4 Hana Oriduru (Japan)
	5927	H08.5 = 2308.5 Hana Oriduru (Japan)
	5928	H09.6 NO MATCH
	5929	H10B.4A = 5509m.17c Mahjong Yarunara (Japan)
	5930	= 6508.6c Hanafuda Hana Tengoku (Japan)
	5931	= 5509h.17c Hana wo Yaraneba! (Japan)
	5932
	5933	***************************************************************************/
	5934
	5935	ROM_START( hjingi )
	5936	ROM_REGION( 0x30000, REGION_CPU1, 0 )
	5937	ROM_LOAD( "hanajngi.code", 0x00000, 0x20000, NO_DUMP )
	5938	ROM_RELOAD( 0x10000, 0x20000 )
	5939
	5940	ROM_REGION( 0x100000, REGION_GFX1, 0 ) // blitter data
	5941	ROM_LOAD( "h02.21", 0x00000, 0x20000, CRC(9dde2d59) SHA1(96df4ba97ee9611d9a3c7bcaae9cd97815a7b8a5) )
	5942	ROM_LOAD( "h03.22", 0x20000, 0x20000, CRC(1ac59443) SHA1(e70fe6184e7090cf7229d83b87db65f7715de2a8) )
	5943	ROM_LOAD( "h01.20", 0x40000, 0x20000, CRC(24391ddc) SHA1(6a2e3fae4b6d0b1d8073306f37c9fdaa04b69eb8) )
	5944	ROM_LOAD( "h04.1", 0x60000, 0x20000, CRC(3756c745) SHA1(f275a72d6e07f21148900d24a8018d03504f249f) )
	5945	ROM_LOAD( "h05.2", 0x80000, 0x20000, CRC(249d360a) SHA1(688fced1298c345a18314d2c88664c757a2de35c) )
	5946	ROM_LOAD( "h06.3", 0xa0000, 0x20000, CRC(014a4945) SHA1(0cd747787a81226fd4937616a6ce45af731a4049) )
	5947	ROM_LOAD( "h07.4", 0xc0000, 0x20000, CRC(8b6f8a2d) SHA1(c5f3ec64a7ea3edc556182f42e6da4842d88e0ba) )
	5948	ROM_LOAD( "h08.5", 0xe0000, 0x20000, CRC(6f996e6e) SHA1(c2b916afbfd257417f0383ad261f3720a027fdd9) )
	5949
	5950	ROM_REGION( 0x40000, REGION_GFX2, 0 ) // blitter data
	5951	ROM_LOAD( "h09.6", 0x00000, 0x20000, CRC(86bde64d) SHA1(d9b79184697044ae8a4d04ea22deca2e14162065) )
	5952	ROM_LOAD( "h10b.4a",0x20000, 0x20000, CRC(ca46ed48) SHA1(0769ac0b211181b7b57033f09f72828c885186cc) )
	5953	ROM_END
	5954
	5955
	5956	/***************************************************************************
	5957
	5958	Hanafuda Hana Tengoku
	5959	(c)1992 Dynax
	5960
	5961	D6502208L1
	5962	CPU : TMP91P640? (surface scratched)
	5963	Sound : AY38910A/P(YM2149F version exists), YM2413
	5964	OSC : 20.00000MHz, 14.31818MHz, ?(near 6242)
	5965	Others: M6242B(RTC), battery
	5966	DIPs : 10 position (x4), 4 position (x1)
	5967	ROMs : 6501.4B
	5968	6509.10B
	5969	6510.11B
	5970
	5971	D6107068L-1
	5972	ROMs : 6502.1A
	5973	6503.2A
	5974	6504.1B
	5975	6505.2B
	5976	6506.4C
	5977	6507.5C
	5978	6508.6C
	5979
	5980	dumped by sayu
	5981	--- Team Japump!!! ---
	5982
	5983
	5984	Daughterboard number - D6107068L-1
	5985	Top daughterboard has most of the ROMs
	5986	Mainboard has roms labelled 6501, 6509, 6510
	5987	The main board is almost like a few other Dynax Mahjong PCB's I've
	5988	documented, so most of the details should be the same. The layout is
	5989	similar to Mysterious World.
	5990
	5991	Mainboard number - D6502208L1
	5992	Mainboard main parts include.....
	5993	AY3-8910
	5994	YM2413
	5995	RAM TC5563 x1
	5996	RAM 2018 x1
	5997	RAM HM53461 x6 (plus 2 empty spaces for 2 more)
	5998	RAM TC524256 x2
	5999	M6242 RTC + BATTERY
	6000	Two scratched SDIP64 chips (possibly NL-001 and NL-002 or similar)
	6001	Another scratched chip QFP64.... should be another known Dynax IC.
	6002	DIP40 chip near ROM 6501... surface scratched too. Probably Z80
	6003	XTALs - 20Mz, 14.31818MHz
	6004	DSWs - 4x 10-position, 1x 4-position
	6005
	6006	***************************************************************************/
	6007
	6008	ROM_START( htengoku )
	6009	ROM_REGION( 0x50000, REGION_CPU1, 0 ) // Z80 Code
	6010	ROM_LOAD( "6501.4b", 0x00000, 0x40000, CRC(29a7fc83) SHA1(5d3cf0a72918e58b5b60f7c978e559c7c1306bce) )
	6011	ROM_RELOAD( 0x10000, 0x40000 )
	6012
	6013	ROM_REGION( 0x80000, REGION_GFX1, 0 ) // blitter data
	6014	ROM_LOAD( "6506.4c", 0x00000, 0x80000, CRC(7de17b26) SHA1(326667063ab045ac50e850f2f7821a65317879ad) )
	6015
	6016	ROM_REGION( 0xc0000, REGION_GFX2, 0 ) // blitter data
	6017	ROM_LOAD( "6507.5c", 0x00000, 0x20000, CRC(ced3155b) SHA1(658e3947781f1be2ee87b43952999281c66683a6) )
	6018	ROM_LOAD( "6508.6c", 0x20000, 0x20000, CRC(ca46ed48) SHA1(0769ac0b211181b7b57033f09f72828c885186cc) )
	6019	ROM_LOAD( "6505.2b", 0x40000, 0x20000, CRC(161058fd) SHA1(cfc21abdc036e874d34bfa3c60486a5ab87cf9cd) )
	6020	ROM_LOAD( "6504.1b", 0x60000, 0x20000, CRC(b2ca9838) SHA1(7104697802a0466fab40414a467146a224eb6a74) )
	6021	ROM_LOAD( "6503.2a", 0x80000, 0x20000, CRC(6ac42304) SHA1(ce822da6d61e68578c08c9f1d0af1557c64ac5ae) )
	6022	ROM_LOAD( "6502.1a", 0xa0000, 0x20000, CRC(9276a10a) SHA1(5a68fff20631a2002509d6cace06b5a9fa0e75d2) )
	6023
	6024	ROM_REGION( 0xa0000, REGION_GFX3, 0 ) // blitter data
	6025	ROM_LOAD( "6509.10b", 0x00000, 0x80000, CRC(f8524c28) SHA1(d50b99664c9f0735838adb55aa7db53e58a43f99) )
	6026	ROM_LOAD( "6510.11b", 0x80000, 0x20000, CRC(0fdd6edf) SHA1(c6870ab538987110337e6e154cba98391c68fb98) )
	6027	ROM_END
	6028
	6029
	6030	/***************************************************************************
	6031
	6032
5338	6033	Game Drivers
5339	6034
5340	6035
r1103	r1104
5342	6037
5343	6038	GAME( 1988, hanamai, 0, hanamai, hanamai, 0, ROT180, "Dynax", "Hana no Mai (Japan)", 0 )
5344	6039	GAME( 1989, hnkochou, hanamai, hanamai, hnkochou, 0, ROT180, "Dynax", "Hana Kochou [BET] (Japan)", 0 )
5345		GAME( 1989, hnoridur, 0, hnoridur, hnoridur, 0, ROT180, "Dynax", "Hana Oriduru (Japan)", ~~GAME_IMPERFECT_GRAPHICS~~ ) ~~// 1 rom is bad~~
	6040	GAME( 1989, hnoridur, 0, hnoridur, hnoridur, 0, ROT180, "Dynax", "Hana Oriduru (Japan)", 0 )
5346	6041	GAME( 1989, drgpunch, 0, sprtmtch, sprtmtch, 0, ROT0, "Dynax", "Dragon Punch (Japan)", 0 )
5347	6042	GAME( 1989, sprtmtch, drgpunch, sprtmtch, sprtmtch, 0, ROT0, "Dynax (Fabtek license)", "Sports Match", 0 )
5348	6043	GAME( 1989, mjfriday, 0, mjfriday, mjfriday, 0, ROT180, "Dynax", "Mahjong Friday (Japan)", 0 )
r1103	r1104
5358	6053	GAME( 1993, mjelctrn, 0, mjelctrn, mjelctrn, mjelct3, ROT180, "Dynax", "Mahjong Electron Base (parts 2 & 4, Japan)", 0 )
5359	6054	GAME( 1990, mjelct3, mjelctrn, mjelctrn, mjelct3, mjelct3, ROT180, "Dynax", "Mahjong Electron Base (parts 2 & 3, Japan)", 0 )
5360	6055	GAME( 1990, mjelct3a, mjelctrn, mjelctrn, mjelct3, mjelct3a, ROT180, "Dynax", "Mahjong Electron Base (parts 2 & 3, alt., Japan)", 0 )
	6056	GAME( 1990, hjingi, 0, majxtal7, majxtal7, 0, ROT0, "Dynax", "Hanajingi", GAME_NOT_WORKING )
5361	6057	GAME( 1990, majxtal7, 0, majxtal7, majxtal7, mjelct3, ROT180, "Dynax", "Mahjong X-Tal 7 - Crystal Mahjong / Mahjong Diamond 7 (Japan)",GAME_IMPERFECT_GRAPHICS )
5362	6058	GAME( 1990, neruton, 0, neruton, neruton, mjelct3, ROT180, "Dynax / Yukiyoshi Tokoro", "Mahjong Neruton Haikujirada (Japan)", GAME_IMPERFECT_GRAPHICS )
	6059	GAME( 1991, hanayara, 0, yarunara, hanayara, 0, ROT180, "Dynax", "Hana wo Yaraneba! (Japan)", 0 )
5363	6060	GAME( 1991, mjcomv1, 0, yarunara, yarunara, 0, ROT180, "Dynax", "Mahjong Comic Gekijou Vol.1 (Japan)", 0 )
5364		GAME( 1991, tenkai, 0, tenkai, tenkai, 0, ROT0, "Dynax", "Mahjong Tenkaigen", GAME_NOT_WORKING )
5365		GAME( 1991, tenkai2b, tenkai, tenkai, tenkai, 0, ROT0, "Dynax", "Mahjong Tenkaigen Part 2 (bootleg)", GAME_NOT_WORKING )
5366		GAME( 1991, tenkaibb, tenkai, tenkai, tenkai, 0, ROT0, "Dynax", "Mahjong Tenkaigen (bootleg b)", 0 )
5367		GAME( 1991, tenkaicb, tenkai, tenkai, tenkai, 0, ROT0, "Dynax", "Mahjong Tenkaigen (bootleg c)", GAME_NOT_WORKING )
5368		GAME( 1991, tenkaid, tenkai, tenkai, tenkai, 0, ROT0, "Dynax", "Mahjong Tenkaigen (set 1)", GAME_NOT_WORKING )
5369		GAME( 1991, tenkaie, tenkai, tenkai, tenkai, 0, ROT0, "Dynax", "Mahjong Tenkaigen (set 2)", GAME_NOT_WORKING )
	6061	GAME( 1991, tenkai, 0, tenkai, tenkai, 0, ROT180, "Dynax", "Mahjong Tenkaigen", GAME_NOT_WORKING )
	6062	GAME( 1991, tenkai2b, tenkai, tenkai, tenkai, 0, ROT180, "Dynax", "Mahjong Tenkaigen Part 2 (bootleg)", GAME_NOT_WORKING )
	6063	GAME( 1991, tenkaibb, tenkai, tenkai, tenkai, 0, ROT180, "Dynax", "Mahjong Tenkaigen (bootleg b)", 0 )
	6064	GAME( 1991, tenkaicb, tenkai, tenkai, tenkai, 0, ROT180, "Dynax", "Mahjong Tenkaigen (bootleg c)", GAME_NOT_WORKING )
	6065	GAME( 1991, tenkaid, tenkai, tenkai, tenkai, 0, ROT180, "Dynax", "Mahjong Tenkaigen (set 1)", GAME_NOT_WORKING )
	6066	GAME( 1991, tenkaie, tenkai, tenkai, tenkai, 0, ROT180, "Dynax", "Mahjong Tenkaigen (set 2)", GAME_NOT_WORKING )
	6067	GAME( 1992, htengoku, 0, htengoku, htengoku, 0, ROT180, "Dynax", "Hanafuda Hana Tengoku (Japan)", 0 )
5370	6068	GAME( 1994, mjreach, 0, tenkai, mjreach, mjreach, ROT0, "Dynax", "Mahjong Reach (bootleg)", 0 )
5371	6069	GAME( 1995, shpeng, 0, sprtmtch, sprtmtch, 0, ROT0, "WSAC Systems?", "Sea Hunter Penguin", GAME_WRONG_COLORS ) // not a dynax board. proms?
5372		GAME( 1996, majrjhdx, 0, majrjhdx, tenkai, 0, ROT0, "Dynax", "Mahjong Raijinhai DX", 0 )
	6070	GAME( 1996, majrjhdx, 0, majrjhdx, tenkai, 0, ROT0, "Dynax", "Mahjong Raijinhai DX", GAME_NOT_WORKING )

src/mame/drivers/itech32.c
r1103	r1104
16	16	* Street Fighter: The Movie (4 sets)
17	17	* Shuffleshot (3 sets)
18	18	* Golden Tee 3D Golf (11 sets)
19		* Golden Tee Golf '97 (6 sets)
	19	* Golden Tee Golf '97 (7 sets)
20	20	* Golden Tee Golf '98 (4 sets)
21	21	* Golden Tee Golf '99 (4 Sets)
22	22	* Golden Tee Golf 2K (4 Sets)
r1103	r1104
1400	1400	PORT_INCLUDE(gt3d)
1401	1401
1402	1402	PORT_MODIFY("DIPS")
1403		PORT_DIPNAME( 0x0010, 0x0000, "Freeze Screen" ) PORT_DIPLOCATION("SW1:1")
	1403	PORT_DIPNAME( 0x0010, 0x0000, "Freeze Screen" ) PORT_DIPLOCATION("SW1:4")
1404	1404	PORT_DIPSETTING( 0x0000, DEF_STR( Off ))
1405	1405	PORT_DIPSETTING( 0x0010, DEF_STR( On ))
1406	1406	INPUT_PORTS_END
r1103	r1104
3052	3052	ROM_END
3053	3053
3054	3054
	3055	ROM_START( gt97t243 ) /* Version 2.43 Tournament Edition (PCB P/N 1082 Rev 2) */
	3056	ROM_REGION32_BE( CODE_SIZE, REGION_USER1, 0 )
	3057	ROM_LOAD32_BYTE( "gt97prm0.243", 0x00000, 0x100000, CRC(b8de60f1) SHA1(06b1f8b9d0b878d5a19e6756957e2df19e013ad6) )
	3058	ROM_LOAD32_BYTE( "gt97prm1.243", 0x00001, 0x100000, CRC(8152e5d3) SHA1(2a4f8acc6a4e33864c97d5974e2230b1cf3632ea) )
	3059	ROM_LOAD32_BYTE( "gt97prm2.243", 0x00002, 0x100000, CRC(b80061be) SHA1(9a6a6281690b3bd2eabb081467bfda074639fa6a) )
	3060	ROM_LOAD32_BYTE( "gt97prm3.243", 0x00003, 0x100000, CRC(d184968d) SHA1(eecd4e9d060e4b8feabca715d3d7f9738641cfcc) )
	3061
	3062	ROM_REGION( 0x28000, REGION_CPU2, 0 )
	3063	ROM_LOAD( "gt_nr.u88", 0x10000, 0x18000, CRC(2cee9e98) SHA1(02edac7abab2335c1cd824d1d9b26aa32238a2de) )
	3064	ROM_CONTINUE( 0x08000, 0x08000 )
	3065
	3066	ROM_REGION( 0x600000, REGION_GFX1, 0 )
	3067	ROM_LOAD32_BYTE( "gt97_grm.0_0", 0x000000, 0x80000, CRC(81784aaf) SHA1(9544ed2087ca5f71c747e3b782513614937a51ed) )
	3068	ROM_LOAD32_BYTE( "gt97_grm.0_1", 0x000001, 0x80000, CRC(345bda44) SHA1(b6d66c99bd68396e1e94ece76989a6190571ae14) )
	3069	ROM_LOAD32_BYTE( "gt97_grm.0_2", 0x000002, 0x80000, CRC(b2beb40d) SHA1(2b955919e7e5f9093eb3a856f93c39684437b371) )
	3070	ROM_LOAD32_BYTE( "gt97_grm.0_3", 0x000003, 0x80000, CRC(7cef32ff) SHA1(614c6aa26398d054a087dfe5e75cef78e6096f30) )
	3071	ROM_LOAD32_BYTE( "gt97_grm.1_0", 0x200000, 0x80000, CRC(1cc4c309) SHA1(ef15f663ad1ea14c25f08fb6c1d5a58a38834ae6) )
	3072	ROM_LOAD32_BYTE( "gt97_grm.1_1", 0x200001, 0x80000, CRC(512cea45) SHA1(03b229317c8f357fa2d2ead93bf519251edc6605) )
	3073	ROM_LOAD32_BYTE( "gt97_grm.1_2", 0x200002, 0x80000, CRC(0599b505) SHA1(13078eae4051b3a4c1955cc246e58ef51ee2e53a) )
	3074	ROM_LOAD32_BYTE( "gt97_grm.1_3", 0x200003, 0x80000, CRC(257eacc9) SHA1(2d03c38965930c4c1da4aa86583bb19c5f135100) )
	3075	ROM_LOAD32_BYTE( "gt97_grm.2_0", 0x400000, 0x80000, CRC(95b6e7ee) SHA1(c27f69f69927e75ec8cba0df5c12e10418a53bbc) )
	3076	ROM_LOAD32_BYTE( "gt97_grm.2_1", 0x400001, 0x80000, CRC(afd558b4) SHA1(0571bfc2b0131cdd62f92641dd1acf7b10ae09d8) )
	3077	ROM_LOAD32_BYTE( "gt97_grm.2_2", 0x400002, 0x80000, CRC(5b7a8733) SHA1(e0a947ebabc8e6ab23b375afef49cd4be7d6d570) )
	3078	ROM_LOAD32_BYTE( "gt97_grm.2_3", 0x400003, 0x80000, CRC(72e8ae60) SHA1(410da9970c50021f1724c8c51678691322eece92) )
	3079
	3080	ROM_REGION16_BE( 0x400000, REGION_SOUND1, ROMREGION_ERASE00 )
	3081	ROM_LOAD16_BYTE( "gt_srom0.nr", 0x000000, 0x100000, CRC(44983bd7) SHA1(a6ac966ec113b079434d7f871e4ce7266206d234) )
	3082	ROM_LOAD16_BYTE( "gt_srom1.nr", 0x200000, 0x080000, CRC(1b3f18b6) SHA1(3b65de6a90c5ede183b5f8ca1875736bc1425772) )
	3083	ROM_END
	3084
	3085
3055	3086	ROM_START( gt98 ) /* Version 1.10 */
3056	3087	ROM_REGION32_BE( CODE_SIZE, REGION_USER1, 0 )
3057	3088	ROM_LOAD32_BYTE( "gt98prm0.110", 0x00000, 0x80000, CRC(dd93ab2a) SHA1(b7eb6331f781422d6d46babcc24a85ae36b25914) )
r1103	r1104
3895	3926	GAME( 1997, gt97s121, gt97, sftm, gt97s, s_ver, ROT0, "Incredible Technologies", "Golden Tee '97 (v1.21S)" , 0) /* PIC 16C54 labeled as ITGFM-3 */
3896	3927	GAME( 1997, gt97v120, gt97, sftm, gt97o, aama, ROT0, "Incredible Technologies", "Golden Tee '97 (v1.20)" , 0) /* PIC 16C54 labeled as ITGFS-3 */
3897	3928	GAME( 1997, gt97t240, gt97, gt3dt, gt97o, aamat, ROT0, "Incredible Technologies", "Golden Tee '97 Tournament (v2.40)" , 0) /* PIC 16C54 labeled as ITGFS-3 */
	3929	GAME( 1997, gt97t243, gt97, gt3dt, gt97o, aamat, ROT0, "Incredible Technologies", "Golden Tee '97 Tournament (v2.43)" , 0) /* PIC 16C54 labeled as ITGFS-3 */
3898	3930
3899	3931	GAME( 1998, gt98, 0, sftm, aama, aama, ROT0, "Incredible Technologies", "Golden Tee '98 (v1.10)" , 0) /* PIC 16C54 labeled as ITGF98 */
3900	3932	GAME( 1998, gt98v100, gt98, sftm, gt98, aama, ROT0, "Incredible Technologies", "Golden Tee '98 (v1.00)" , 0) /* PIC 16C54 labeled as ITGF98 */

src/mame/drivers/hayaosi1.c
r0	r1104
	1	/*
	2
	3	Hayaoshi Quiz Ouza Ketteisen
	4	(c)1991 Jaleco
	5
	6	JALECO ED9075
	7	EB90004-20027
	8
	9	CPU: HD68000PS8 x2
	10	MCU: M50747? (labeled "MO-91044")
	11	Sound: YM2151 YM3012 M6295x2
	12	Custom: GS-9000401 (44pin QFP)
	13	GS-9000403 (44pin QFP, x2)
	14	GS-9000404 (44pin QFP)
	15	GS-9000405 (80pin QFP, x3)
	16	GS-9000406 (80pin QFP, x3)
	17	GS-9000407 (80pin QFP)
	18
	19	ROMs:
	20	1 - near 68000 (actual label is ???????N?C?Y[1])
	21	2 / (actual label is ???????N?C?Y[2])
	22
	23	3 - near 6295 (actual label is ???????N?C?Y[3])
	24	4 / (actual label is ???????N?C?Y[4])
	25
	26	5 - near 68000 (actual label is ???????N?C?Y[5] Ver1.1)
	27	6 / (actual label is ???????N?C?Y[6] Ver1.1)
	28
	29	7 - near customs (actual label is ???????N?C?Y[7])
	30	8 \| (actual label is ???????N?C?Y[8])
	31	9 \| (actual label is ???????N?C?Y[9])
	32	10 / (actual label is ???????N?C?Y[10])
	33
	34	PR-91044 (82S131N, not dumped)
	35
	36	*/
	37
	38	#include "driver.h"
	39	#include "sound/okim6295.h"
	40
	41
	42	VIDEO_START( hayaosi1 )
	43	{
	44
	45	}
	46
	47	VIDEO_UPDATE( hayaosi1 )
	48	{
	49	return 0;
	50	}
	51
	52	static ADDRESS_MAP_START( hayaosi1_mainmap, ADDRESS_SPACE_PROGRAM, 16 )
	53	AM_RANGE(0x000000, 0x07ffff) AM_ROM
	54	ADDRESS_MAP_END
	55
	56	static ADDRESS_MAP_START( hayaosi1_submap, ADDRESS_SPACE_PROGRAM, 16 )
	57	AM_RANGE(0x000000, 0x03ffff) AM_ROM
	58	ADDRESS_MAP_END
	59
	60	INPUT_PORTS_START( hayaosi1 )
	61	INPUT_PORTS_END
	62
	63	static const gfx_layout hayaosi1_16x16_layout =
	64	{
	65	16,16,
	66	RGN_FRAC(1,1),
	67	4,
	68	{ 0,1,2,3 },
	69	{ 04,14,24,34,44,54,64,74,
	70	512+04,512+14,512+24,512+34,512+44,512+54,512+64,512+74},
	71	{ 032,132, 232, 332,432,532,632,732,832,932,1032,1132,1232,1332,1432,1532 },
	72	32*32
	73	};
	74
	75	static const gfx_layout hayaosi1_layout =
	76	{
	77	8,8,
	78	RGN_FRAC(1,1),
	79	4,
	80	{ 0,1,2,3 },
	81	{ 04,14,24,34,44,54,64,74 },
	82	{ 032,132, 232, 332,432,532,632,732 },
	83	8*32
	84	};
	85
	86	static GFXDECODE_START( hayaosi1 )
	87	GFXDECODE_ENTRY( REGION_GFX1, 0, hayaosi1_16x16_layout, 0, 0 )
	88	GFXDECODE_ENTRY( REGION_GFX2, 0, hayaosi1_16x16_layout, 0, 0 )
	89	GFXDECODE_ENTRY( REGION_GFX3, 0, hayaosi1_layout, 0, 0 )
	90	GFXDECODE_ENTRY( REGION_GFX4, 0, hayaosi1_layout, 0, 0 )
	91	GFXDECODE_END
	92
	93
	94	static MACHINE_DRIVER_START( hayaosi1 )
	95	MDRV_CPU_ADD_TAG("main", M68000, 8000000 ) // CPU rated 8mhz, clocks unknown
	96	MDRV_CPU_PROGRAM_MAP(hayaosi1_mainmap,0)
	97
	98	MDRV_CPU_ADD_TAG("main", M68000, 8000000 ) // CPU rated 8mhz, clocks unknown
	99	MDRV_CPU_PROGRAM_MAP(hayaosi1_submap,0)
	100
	101	MDRV_SCREEN_REFRESH_RATE(60)
	102	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
	103
	104	MDRV_GFXDECODE(hayaosi1)
	105
	106	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
	107	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
	108	MDRV_SCREEN_SIZE(328, 328)
	109	MDRV_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
	110	MDRV_PALETTE_LENGTH(0x200)
	111
	112	MDRV_VIDEO_START(hayaosi1)
	113	MDRV_VIDEO_UPDATE(hayaosi1)
	114
	115	MDRV_SPEAKER_STANDARD_STEREO("left", "right")
	116
	117	MDRV_SOUND_ADD(OKIM6295, 8000000/8)
	118	MDRV_SOUND_CONFIG(okim6295_interface_region_1_pin7high) // clock frequency & pin 7 not verified
	119	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "left", 0.25)
	120	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "right", 0.25)
	121
	122	MDRV_SOUND_ADD(OKIM6295, 8000000/8)
	123	MDRV_SOUND_CONFIG(okim6295_interface_region_1_pin7high) // clock frequency & pin 7 not verified
	124	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "left", 0.25)
	125	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "right", 0.25)
	126
	127	/* YM2151 */
	128
	129	MACHINE_DRIVER_END
	130
	131
	132
	133	ROM_START( hayaosi1 )
	134	ROM_REGION( 0x80000, REGION_CPU1, 0 ) /* 68000 Code */
	135	ROM_LOAD16_BYTE( "5", 0x00001, 0x40000, CRC(eaf38fab) SHA1(0f9cd6e674668a86d2bb54228b50217c934e96af) )
	136	ROM_LOAD16_BYTE( "6", 0x00000, 0x40000, CRC(341f8057) SHA1(958d9fc870bc13a9c1720d21776b5239db771ce2) )
	137
	138	ROM_REGION( 0x40000, REGION_CPU2, 0 ) /* 68000 Code */
	139	ROM_LOAD16_BYTE( "1", 0x00001, 0x20000, CRC(b088b27e) SHA1(198e2520ce4f9b19ea108e09ff00f7e27768f290) )
	140	ROM_LOAD16_BYTE( "2", 0x00000, 0x20000, CRC(cebc7b16) SHA1(18b166560ffff7c43cec3d52e4b2da79256dfb2e) )
	141
	142	ROM_REGION( 0x40000, REGION_CPU3, 0 ) /* MCU Internal Code (no dump) */
	143	ROM_LOAD( "mo-91044.mcu", 0x000000, 0x40000, NO_DUMP )
	144
	145	ROM_REGION( 0x40000, REGION_SOUND1, 0 ) /* M6295 Samples #1 */
	146	ROM_LOAD( "3", 0x000000, 0x40000, CRC(f3f5787a) SHA1(5e0416726de7b78583c9e1eb7944a41d307a9308) )
	147
	148	ROM_REGION( 0x40000, REGION_SOUND2, 0 ) /* M6295 Samples #2 */
	149	ROM_LOAD( "4", 0x000000, 0x40000, CRC(ac3f9bd2) SHA1(7856f40daa30de9077e68a5ea977ec39c044c2f8) )
	150
	151	ROM_REGION( 0x80000, REGION_GFX1, 0 )
	152	ROM_LOAD( "7", 0x000000, 0x80000, CRC(3629c455) SHA1(c216b600750861b073062c165f36e6949db10d78) )
	153
	154	ROM_REGION( 0x80000, REGION_GFX2, 0 )
	155	ROM_LOAD( "8", 0x000000, 0x80000, CRC(15f0b2a3) SHA1(48080de7818bd1c4ac6a7cd81aa86b69bdda2668) )
	156
	157	ROM_REGION( 0x20000, REGION_GFX3, 0 )
	158	ROM_LOAD( "9", 0x000000, 0x20000, CRC(64d5b95e) SHA1(793714b2b049afd1cb66c888545cb8379c702010) )
	159
	160	ROM_REGION( 0x80000, REGION_GFX4, 0 )
	161	ROM_LOAD( "10", 0x000000, 0x80000, CRC(593e93d6) SHA1(db449b45301e3f7c26e0dfe1f4cf8293ae7dfdaa) )
	162
	163	ROM_REGION( 0x80000, REGION_PROMS, 0 )
	164	ROM_LOAD( "pr-91044", 0x000, 0x100, NO_DUMP )
	165	ROM_END
	166
	167	GAME( 1991, hayaosi1, 0, hayaosi1, hayaosi1, 0, ROT0, "Jaleco", "Hayaoshi Quiz Ouza Ketteisen", GAME_NOT_WORKING )
	168

src/mame/drivers/zaxxon.c
r1103	r1104
636	636	PORT_INCLUDE(zaxxon)
637	637
638	638	PORT_MODIFY("SW00")
	639	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY
	640	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY
639	641	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 )
640	642	PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
641	643

src/mame/drivers/vegas.c
r1103	r1104
295	295	#define LOG_TIMEKEEPER (0)
296	296	#define LOG_SIO (0)
297	297	#define LOG_DYNAMIC (0)
298		#define PRINTF_SERIAL (0)
	298	#define PRINTF_SERIAL (1)
299	299
300	300
301	301
r1103	r1104
448	448	static UINT32 rambase, rombase;
449	449	static size_t ramsize;
450	450
	451	static int speedup_index;
	452
451	453	static UINT32 *nile_regs;
452	454	static UINT16 nile_irq_state;
453	455	static UINT16 ide_irq_state;
r1103	r1104
2225	2227	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
2226	2228	MDRV_SCREEN_SIZE(640, 480)
2227	2229	MDRV_SCREEN_VISIBLE_AREA(0, 639, 0, 479)
2228		MDRV_PALETTE_LENGTH(65536)
2229	2230
2230	2231	MDRV_VIDEO_START(vegas_voodoo2)
2231	2232	MDRV_VIDEO_UPDATE(vegas)
r1103	r1104
2453	2454	/* allocate RAM for the timekeeper */
2454	2455	timekeeper_nvram_size = 0x8000;
2455	2456	timekeeper_nvram = auto_malloc(timekeeper_nvram_size);
	2457
	2458	/* reset speedups */
	2459	speedup_index = 0;
2456	2460	}
2457	2461
	2462	static void add_speedup(offs_t pc, UINT32 op)
	2463	{
	2464	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_SELECT, speedup_index++);
	2465	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_PC, pc);
	2466	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, op);
	2467	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 250);
	2468	}
2458	2469
	2470
2459	2471	static DRIVER_INIT( gauntleg )
2460	2472	{
2461	2473	dcs2_init(4, 0x0b5d);
2462	2474	init_common(MIDWAY_IOASIC_CALSPEED, 340/* 340=39", 322=27", others? */);
2463	2475
2464	2476	/* speedups */
2465		cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_SELECT, 0);
2466		cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_PC, 0x80015438);
2467		cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, 0x1462fffd);
2468		cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 1000);
2469
2470		cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_SELECT, 1);
2471		cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_PC, 0x80015478);
2472		cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, 0x1440fffa);
2473		cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 1000);
	2477	add_speedup(0x80015430, 0x8CC38060); /* confirmed */
	2478	add_speedup(0x80015464, 0x3C09801E); /* confirmed */
	2479	add_speedup(0x800C8918, 0x8FA2004C); /* confirmed */
	2480	add_speedup(0x800C8890, 0x8FA20024); /* confirmed */
2474	2481	}
2475	2482
2476	2483
r1103	r1104
2478	2485	{
2479	2486	dcs2_init(4, 0x0b5d);
2480	2487	init_common(MIDWAY_IOASIC_GAUNTDL, 346/* 347, others? */);
	2488
	2489	/* speedups */
	2490	add_speedup(0x800158B8, 0x8CC3CC40); /* confirmed */
	2491	add_speedup(0x800158EC, 0x3C0C8022); /* confirmed */
	2492	add_speedup(0x800D40C0, 0x8FA2004C); /* confirmed */
	2493	add_speedup(0x800D4038, 0x8FA20024); /* confirmed */
2481	2494	}
2482	2495
2483	2496
r1103	r1104
2485	2498	{
2486	2499	dcs2_init(4, 0x0b5d);
2487	2500	init_common(MIDWAY_IOASIC_MACE, 337/* others? */);
	2501
	2502	/* speedups */
	2503	add_speedup(0x8009436C, 0x0C031663); /* confirmed */
2488	2504	}
2489	2505
2490	2506
r1103	r1104
2492	2508	{
2493	2509	dcs2_init(4, 0x0afb);
2494	2510	init_common(MIDWAY_IOASIC_GAUNTDL, 330/* others? */);
	2511
	2512	/* speedups */
	2513	add_speedup(0x80051CD8, 0x0C023C15); /* confirmed */
	2514	add_speedup(0x8005E674, 0x3C028017); /* confirmed */
	2515	add_speedup(0x8002DBCC, 0x8FA2002C); /* confirmed */
	2516	add_speedup(0x80015930, 0x8FC20244); /* confirmed */
2495	2517	}
2496	2518
2497	2519
r1103	r1104
2556	2578	/* Vegas + Vegas SIO + Voodoo 2 */
2557	2579	GAME( 1998, gauntleg, 0, vegas, gauntleg, gauntleg, ROT0, "Atari Games", "Gauntlet Legends (version 1.6)", 0 )
2558	2580	GAME( 1998, gauntl12, gauntleg, vegas, gauntleg, gauntleg, ROT0, "Atari Games", "Gauntlet Legends (version 1.2)", GAME_NO_SOUND )
2559		GAME( 1998, tenthdeg, 0, vegas, tenthdeg, tenthdeg, ROT0, "Atari Games", "Tenth Degree", 0 )
	2581	GAME( 1998, tenthdeg, 0, vegas, tenthdeg, tenthdeg, ROT0, "Atari Games", "Tenth Degree (prototype)", 0 )
2560	2582
2561	2583	/* Durango + Vegas SIO + Voodoo 2 */
2562	2584	GAME( 1999, gauntdl, 0, vegas, gauntdl, gauntdl, ROT0, "Midway Games", "Gauntlet Dark Legacy (version DL 2.52)", 0 )

src/mame/drivers/finalizr.c
r1103	r1104
158	158	PORT_START /* IN2 */
159	159	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
160	160	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
161		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
	161	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
162	162	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
163	163	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
164	164	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
r1103	r1104
219	219	PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
220	220	PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
221	221	PORT_DIPSETTING( 0x90, DEF_STR( 1C_7C ) )
222		/* PORT_DIPSETTING( 0x00, "Invalid" ) */
	222	PORT_DIPSETTING( 0x00, "Invalid" )
223	223
224	224	PORT_START /* DSW */
225	225	PORT_DIPNAME( 0x03, 0x02, DEF_STR( Lives ) )
r1103	r1104
235	235	PORT_DIPSETTING( 0x10, "50000 300000" )
236	236	PORT_DIPSETTING( 0x08, "30000" )
237	237	PORT_DIPSETTING( 0x00, "50000" )
238		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
239		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
240		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
241		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
242		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
243		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	238	PORT_DIPNAME( 0x60, 0x40, DEF_STR( Difficulty ) )
	239	PORT_DIPSETTING( 0x60, DEF_STR( Easy ) )
	240	PORT_DIPSETTING( 0x40, DEF_STR( Normal ) )
	241	PORT_DIPSETTING( 0x20, DEF_STR( Hard ) )
	242	PORT_DIPSETTING( 0x00, DEF_STR( Very_Hard ) )
244	243	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) )
245	244	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
246	245	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r1103	r1104
252	251	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Controls ) )
253	252	PORT_DIPSETTING( 0x02, DEF_STR( Single ) )
254	253	PORT_DIPSETTING( 0x00, DEF_STR( Dual ) )
255		PORT_DIPNAME( 0x04, 0x04, DEF_STR( ~~Unkn~~own ) )
	254	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Service_Mode ) )
256	255	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
257	256	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
258		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Un~~known~~ ) )
	257	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unused ) )
259	258	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
260	259	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
261	260	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )

src/mame/drivers/ddenlovr.c
r1103	r1104
10	10	Other: Real Time Clock (Oki MSM6242B or 72421B)
11	11
12	12	-----------------------------------------------------------------------------------------------------------------------------
13		Year + Game Board CPU Sound Custom Notes
	13	Year + Game Board CPU Sound Custom Other
14	14	-----------------------------------------------------------------------------------------------------------------------------
15		92 Monkey Mole Panic 2xZ80 AY8910 + YM2413 + M6295 NL-001 1108(x2) 1427(x2) 8251
16		93 Animalandia Jr. 2xZ80 AY8910 + YM2413 + M6295 NL-001 NL-003(x2) NL-004(x2) TMP82C51
	15	92 Monkey Mole Panic 2xZ80 AY8910 + YM2413 + M6295 NL-001 1108(x2) 1427(x2) 8251
	16	93 Animalandia Jr. 2xZ80 AY8910 + YM2413 + M6295 NL-001 NL-003(x2) NL-004(x2) 8251
17	17	93 Quiz Channel Question N7311208L1-2 Z80 YM2413 + M6295 NL-002 1108F0405 1427F0071
18	18	93 First Funky Fighter N7403208L-2 2xZ80 YM2149 + YM2413 + M6295 NL-001 NL-002 NL-005
19	19	94 Mysterious World D7107058L1-1 Z80 YM2149 + YM2413 + M6295 NL-002 1108F0405 1427F0071 4L02?
r1103	r1104
100	100	#include "machine/msm6242.h"
101	101	#include "profiler.h"
102	102
103		~~static~~ UINT8 *pixmap[8];
	103	UINT8 *ddenlovr_pixmap[8];
104	104	static mame_bitmap *framebuffer;
105	105	static int extra_layers;
106	106
r1103	r1104
127	127	110 Followed by 3 bits: change pen size
128	128	111 Stop.
129	129
130		The drawing operation is verified (quiz365) to modify dynax_blit_y.
	130	The drawing operation is verified (quiz365) to modify ddenlovr_blit_y.
131	131
132	132	***************************************************************************/
133	133
134		static int dynax_dest_layer;
135		static int dynax_blit_flip;
136		static int dynax_blit_x;
137		static int dynax_blit_y;
138		static int dynax_blit_address;
139		static int dynax_blit_pen,dynax_blit_pen_mode;
140		static int dynax_blitter_irq_flag,dynax_blitter_irq_enable;
141		static int dynax_rect_width, dynax_rect_height;
142		static int dynax_clip_width, dynax_clip_height;
143		static int dynax_line_length;
144		static int dynax_clip_ctrl = 0xf,dynax_clip_x,dynax_clip_y;
145		static int dynax_scroll[8*2];
146		static int dynax_priority, dynax_priority2;
147		static int dynax_bgcolor, dynax_bgcolor2;
148		static int dynax_layer_enable=0x0f, dynax_layer_enable2=0x0f;
149		static int dynax_palette_base[8], dynax_palette_mask[8];
150		static int dynax_transparency_pen[8], dynax_transparency_mask[8];
151		static int dynax_blit_reg;
152		static int dynax_blit_pen_mask = 0xff; // not implemented
153		static int dynax_blit_rom_bits; // usually 8, 16 in hanakanz
154		static const int *dynax_blit_commands;
	134	static int ddenlovr_dest_layer;
	135	static int ddenlovr_blit_flip;
	136	static int ddenlovr_blit_x;
	137	static int ddenlovr_blit_y;
	138	static int ddenlovr_blit_address;
	139	static int ddenlovr_blit_pen,ddenlovr_blit_pen_mode;
	140	static int ddenlovr_blitter_irq_flag,ddenlovr_blitter_irq_enable;
	141	static int ddenlovr_rect_width, ddenlovr_rect_height;
	142	static int ddenlovr_clip_width, ddenlovr_clip_height;
	143	static int ddenlovr_line_length;
	144	static int ddenlovr_clip_ctrl = 0xf,ddenlovr_clip_x,ddenlovr_clip_y;
	145	static int ddenlovr_scroll[8*2];
	146	static int ddenlovr_priority, ddenlovr_priority2;
	147	static int ddenlovr_bgcolor, ddenlovr_bgcolor2;
	148	static int ddenlovr_layer_enable=0x0f, ddenlovr_layer_enable2=0x0f;
	149	static int ddenlovr_palette_base[8], ddenlovr_palette_mask[8];
	150	static int ddenlovr_transparency_pen[8], ddenlovr_transparency_mask[8];
	151	static int ddenlovr_blit_reg;
	152	static int ddenlovr_blit_pen_mask = 0xff; // not implemented
	153	static int ddenlovr_blit_rom_bits; // usually 8, 16 in hanakanz
	154	static const int *ddenlovr_blit_commands;
155	155
156	156	enum { BLIT_NEXT = 0, BLIT_LINE, BLIT_COPY, BLIT_SKIP, BLIT_CHANGE_NUM, BLIT_CHANGE_PEN, BLIT_UNKNOWN, BLIT_STOP };
157		// 0 1 2 3 4 5 6 7
158		static const int ddenlovr_blit_commands[8] = { BLIT_NEXT, BLIT_LINE, BLIT_COPY, BLIT_SKIP, BLIT_UNKNOWN, BLIT_CHANGE_NUM, BLIT_CHANGE_PEN, BLIT_STOP };
159		static const int hanakanz_blit_commands[8] = { BLIT_NEXT, BLIT_CHANGE_PEN, BLIT_CHANGE_NUM, BLIT_UNKNOWN, BLIT_SKIP, BLIT_COPY, BLIT_LINE, BLIT_STOP };
160		static const int mjflove_blit_commands[8] = { BLIT_STOP, BLIT_CHANGE_PEN, BLIT_CHANGE_NUM, BLIT_UNKNOWN, BLIT_SKIP, BLIT_COPY, BLIT_LINE, BLIT_NEXT };
	157	// 0 1 2 3 4 5 6 7
	158	static const int ddenlovr_commands[8] = { BLIT_NEXT, BLIT_LINE, BLIT_COPY, BLIT_SKIP, BLIT_UNKNOWN, BLIT_CHANGE_NUM, BLIT_CHANGE_PEN, BLIT_STOP };
	159	static const int hanakanz_commands[8] = { BLIT_NEXT, BLIT_CHANGE_PEN, BLIT_CHANGE_NUM, BLIT_UNKNOWN, BLIT_SKIP, BLIT_COPY, BLIT_LINE, BLIT_STOP };
	160	static const int mjflove_commands[8] = { BLIT_STOP, BLIT_CHANGE_PEN, BLIT_CHANGE_NUM, BLIT_UNKNOWN, BLIT_SKIP, BLIT_COPY, BLIT_LINE, BLIT_NEXT };
161	161
162	162	VIDEO_START(ddenlovr)
163	163	{
164	164	int i;
165	165	for (i = 0; i < 8; i++)
166		pixmap[i] = auto_malloc(512*512);
	166	{
	167	ddenlovr_pixmap[i] = auto_malloc(512*512);
	168	ddenlovr_scroll[i2+0] = ddenlovr_scroll[i2+1] = 0;
	169	}
167	170
168	171	framebuffer = auto_bitmap_alloc(machine->screen[0].width,machine->screen[0].height,machine->screen[0].format);
169	172
170	173	extra_layers = 0;
171	174
172	175	// older games do not set these !?
173		dynax_clip_width = 0x400;
174		dynax_clip_height = 0x400;
	176	ddenlovr_clip_width = 0x400;
	177	ddenlovr_clip_height = 0x400;
175	178
176		dynax_blit_rom_bits = 8;
177		dynax_blit_commands = ddenlovr_blit_commands;
	179	ddenlovr_blit_rom_bits = 8;
	180	ddenlovr_blit_commands = ddenlovr_commands;
178	181	}
179	182
180	183	VIDEO_START(mmpanic)
r1103	r1104
188	191	{
189	192	video_start_ddenlovr(machine);
190	193
191		dynax_blit_rom_bits = 16;
192		dynax_blit_commands = hanakanz_blit_commands;
	194	ddenlovr_blit_rom_bits = 16;
	195	ddenlovr_blit_commands = hanakanz_commands;
193	196	}
194	197
195	198	VIDEO_START(mjflove)
196	199	{
197	200	video_start_ddenlovr(machine);
198	201
199		dynax_blit_commands = mjflove~~_blit~~_commands;
	202	ddenlovr_blit_commands = mjflove_commands;
200	203	}
201	204
202		static void dynax_flipscreen_w( UINT8 data )
	205	static void ddenlovr_flipscreen_w( UINT8 data )
203	206	{
204	207	logerror("flipscreen = %02x (%s)\n",data,(data&1)?"off":"on");
205	208	}
206	209
207		static void dynax_blit_flip_w( UINT8 data )
	210	static void ddenlovr_blit_flip_w( UINT8 data )
208	211	{
209		if ((data ^ dynax_blit_flip) & 0xec)
	212	if ((data ^ ddenlovr_blit_flip) & 0xec)
210	213	{
211	214	#ifdef MAME_DEBUG
212		popmessage("warning dynax_blit_flip = %02x",data);
	215	popmessage("warning ddenlovr_blit_flip = %02x",data);
213	216	#endif
214		logerror("warning dynax_blit_flip = %02x\n",data);
	217	logerror("warning ddenlovr_blit_flip = %02x\n",data);
215	218	}
216	219
217		dynax_blit_flip = data;
	220	ddenlovr_blit_flip = data;
218	221	}
219	222
220		~~static~~ WRITE8_HANDLER( dynax_bgcolor_w )
	223	WRITE8_HANDLER( ddenlovr_bgcolor_w )
221	224	{
222		dynax_bgcolor = data;
	225	ddenlovr_bgcolor = data;
223	226	}
224	227
225		~~static~~ WRITE8_HANDLER( dynax_bgcolor2_w )
	228	WRITE8_HANDLER( ddenlovr_bgcolor2_w )
226	229	{
227		dynax_bgcolor2 = data;
	230	ddenlovr_bgcolor2 = data;
228	231	}
229	232
230		~~static~~ WRITE16_HANDLER( ddenlovr_bgcolor_w )
	233	WRITE16_HANDLER( ddenlovr16_bgcolor_w )
231	234	{
232	235	if (ACCESSING_LSB)
233		dynax_bgcolor_w(offset,data);
	236	ddenlovr_bgcolor_w(offset,data);
234	237	}
235	238
236	239
237		~~static~~ WRITE8_HANDLER( dynax_priority_w )
	240	WRITE8_HANDLER( ddenlovr_priority_w )
238	241	{
239		dynax_priority = data;
	242	ddenlovr_priority = data;
240	243	}
241	244
242		~~static~~ WRITE8_HANDLER( dynax_priority2_w )
	245	WRITE8_HANDLER( ddenlovr_priority2_w )
243	246	{
244		dynax_priority2 = data;
	247	ddenlovr_priority2 = data;
245	248	}
246	249
247		~~static~~ WRITE16_HANDLER( ddenlovr_priority_w )
	250	WRITE16_HANDLER( ddenlovr16_priority_w )
248	251	{
249	252	if (ACCESSING_LSB)
250		dynax_priority_w(offset,data);
	253	ddenlovr_priority_w(offset,data);
251	254	}
252	255
253	256
254		~~static~~ WRITE8_HANDLER( dynax_layer_enable_w )
	257	WRITE8_HANDLER( ddenlovr_layer_enable_w )
255	258	{
256		dynax_layer_enable = data;
	259	ddenlovr_layer_enable = data;
257	260	}
258	261
259		~~static~~ WRITE8_HANDLER( dynax_layer_enable2_w )
	262	WRITE8_HANDLER( ddenlovr_layer_enable2_w )
260	263	{
261		dynax_layer_enable2 = data;
	264	ddenlovr_layer_enable2 = data;
262	265	}
263	266
264	267
265		~~static~~ WRITE16_HANDLER( ddenlovr_layer_enable_w )
	268	WRITE16_HANDLER( ddenlovr16_layer_enable_w )
266	269	{
267	270	if (ACCESSING_LSB)
268		dynax_layer_enable_w(offset,data);
	271	ddenlovr_layer_enable_w(offset,data);
269	272	}
270	273
271	274
r1103	r1104
280	283	x &= 0x1ff;
281	284
282	285	// swap x & y (see hanakanz gal check)
283		if (dynax_blit_flip & 0x10) { temp = x; x = y; y = temp; }
	286	if (ddenlovr_blit_flip & 0x10) { temp = x; x = y; y = temp; }
284	287
285	288	// clipping rectangle (see hanakanz / hkagerou gal check)
286	289	#if 0
287		xclip = (x < dynax_clip_x) \|\| (x > dynax_clip_x+dynax_clip_width);
288		yclip = (y < dynax_clip_y) \|\| (y > dynax_clip_y+dynax_clip_height);
	290	xclip = (x < ddenlovr_clip_x) \|\| (x > ddenlovr_clip_x+ddenlovr_clip_width);
	291	yclip = (y < ddenlovr_clip_y) \|\| (y > ddenlovr_clip_y+ddenlovr_clip_height);
289	292	#else
290		xclip = (x < dynax_clip_x) \|\| (x > dynax_clip_width);
291		yclip = (y < dynax_clip_y) \|\| (y > dynax_clip_height);
	293	xclip = (x < ddenlovr_clip_x) \|\| (x > ddenlovr_clip_width);
	294	yclip = (y < ddenlovr_clip_y) \|\| (y > ddenlovr_clip_height);
292	295	#endif
293	296
294		if (!(dynax_clip_ctrl & 1) && xclip) return;
295		if (!(dynax_clip_ctrl & 2) && !xclip) return;
296		if (!(dynax_clip_ctrl & 4) && yclip) return;
297		if (!(dynax_clip_ctrl & 8) && !yclip) return;
	297	if (!(ddenlovr_clip_ctrl & 1) && xclip) return;
	298	if (!(ddenlovr_clip_ctrl & 2) && !xclip) return;
	299	if (!(ddenlovr_clip_ctrl & 4) && yclip) return;
	300	if (!(ddenlovr_clip_ctrl & 8) && !yclip) return;
298	301
299	302	addr = 512 * y + x;
300	303
301		if (dynax_dest_layer & 0x0001) pixmap[0][addr] = pen;
302		if (dynax_dest_layer & 0x0002) pixmap[1][addr] = pen;
303		if (dynax_dest_layer & 0x0004) pixmap[2][addr] = pen;
304		if (dynax_dest_layer & 0x0008) pixmap[3][addr] = pen;
	304	if (ddenlovr_dest_layer & 0x0001) ddenlovr_pixmap[0][addr] = pen;
	305	if (ddenlovr_dest_layer & 0x0002) ddenlovr_pixmap[1][addr] = pen;
	306	if (ddenlovr_dest_layer & 0x0004) ddenlovr_pixmap[2][addr] = pen;
	307	if (ddenlovr_dest_layer & 0x0008) ddenlovr_pixmap[3][addr] = pen;
305	308
306	309	if (!extra_layers) return;
307	310
308		if (dynax_dest_layer & 0x0100) pixmap[4][addr] = pen;
309		if (dynax_dest_layer & 0x0200) pixmap[5][addr] = pen;
310		if (dynax_dest_layer & 0x0400) pixmap[6][addr] = pen;
311		if (dynax_dest_layer & 0x0800) pixmap[7][addr] = pen;
	311	if (ddenlovr_dest_layer & 0x0100) ddenlovr_pixmap[4][addr] = pen;
	312	if (ddenlovr_dest_layer & 0x0200) ddenlovr_pixmap[5][addr] = pen;
	313	if (ddenlovr_dest_layer & 0x0400) ddenlovr_pixmap[6][addr] = pen;
	314	if (ddenlovr_dest_layer & 0x0800) ddenlovr_pixmap[7][addr] = pen;
312	315	}
313	316
314	317
r1103	r1104
363	366	{
364	367	UINT8 *src_data = memory_region(REGION_GFX1);
365	368	int src_len = memory_region_length(REGION_GFX1);
366		int bit_addr = (src & 0xffffff) * dynax_blit_rom_bits; /* convert to bit address */
	369	int bit_addr = (src & 0xffffff) * ddenlovr_blit_rom_bits; /* convert to bit address */
367	370	int pen_size, arg_size, cmd;
368	371	int x;
369		int xinc = (dynax_blit_flip & 1) ? -1 : 1;
370		int yinc = (dynax_blit_flip & 2) ? -1 : 1;
	372	int xinc = (ddenlovr_blit_flip & 1) ? -1 : 1;
	373	int yinc = (ddenlovr_blit_flip & 2) ? -1 : 1;
371	374
372	375	pen_size = fetch_word(src_data,src_len,&bit_addr,4) + 1;
373	376	arg_size = fetch_word(src_data,src_len,&bit_addr,4) + 1;
r1103	r1104
382	385	for (;;)
383	386	{
384	387	cmd = fetch_word(src_data,src_len,&bit_addr,3);
385		switch ( dynax_blit_commands[cmd] )
	388	switch ( ddenlovr_blit_commands[cmd] )
386	389	{
387	390	case BLIT_NEXT:
388	391	/* next line */
389		dynax_blit_y += yinc;
	392	ddenlovr_blit_y += yinc;
390	393	x = sx;
391	394	break;
392	395
r1103	r1104
394	397	{
395	398	int length = fetch_word(src_data,src_len,&bit_addr,arg_size);
396	399	int pen = fetch_word(src_data,src_len,&bit_addr,pen_size);
397		if (dynax_blit_pen_mode) pen = (dynax_blit_pen & 0x0f);
398		pen \|= dynax_blit_pen & 0xf0;
	400	if (ddenlovr_blit_pen_mode) pen = (ddenlovr_blit_pen & 0x0f);
	401	pen \|= ddenlovr_blit_pen & 0xf0;
399	402	while (length-- >= 0)
400	403	{
401		do_plot(x,dynax_blit_y,pen);
	404	do_plot(x,ddenlovr_blit_y,pen);
402	405	x += xinc;
403	406	}
404	407	}
r1103	r1104
410	413	while (length-- >= 0)
411	414	{
412	415	int pen = fetch_word(src_data,src_len,&bit_addr,pen_size);
413		if (dynax_blit_pen_mode) pen = (dynax_blit_pen & 0x0f);
414		pen \|= dynax_blit_pen & 0xf0;
415		do_plot(x,dynax_blit_y,pen);
	416	if (ddenlovr_blit_pen_mode) pen = (ddenlovr_blit_pen & 0x0f);
	417	pen \|= ddenlovr_blit_pen & 0xf0;
	418	do_plot(x,ddenlovr_blit_y,pen);
416	419	x += xinc;
417	420	}
418	421	}
r1103	r1104
434	437	log_draw_error(src,cmd);
435	438	// fall through
436	439	case BLIT_STOP:
437		return ((bit_addr + dynax_blit_rom_bits - 1) / dynax_blit_rom_bits) & 0xffffff;
	440	return ((bit_addr + ddenlovr_blit_rom_bits - 1) / ddenlovr_blit_rom_bits) & 0xffffff;
438	441	}
439	442	}
440	443	}
r1103	r1104
448	451	int x,y;
449	452
450	453	#ifdef MAME_DEBUG
451		// if (dynax_clip_ctrl != 0x0f)
452		// popmessage("RECT clipx=%03x clipy=%03x ctrl=%x",dynax_clip_x,dynax_clip_y,dynax_clip_ctrl);
	454	// if (ddenlovr_clip_ctrl != 0x0f)
	455	// popmessage("RECT clipx=%03x clipy=%03x ctrl=%x",ddenlovr_clip_x,ddenlovr_clip_y,ddenlovr_clip_ctrl);
453	456	#endif
454	457
455		for (y = 0; y <= dynax_rect_height; y++)
456		for (x = 0; x <= dynax_rect_width; x++)
457		do_plot( x + dynax_blit_x, y + dynax_blit_y, dynax_blit_pen);
	458	for (y = 0; y <= ddenlovr_rect_height; y++)
	459	for (x = 0; x <= ddenlovr_rect_width; x++)
	460	do_plot( x + ddenlovr_blit_x, y + ddenlovr_blit_y, ddenlovr_blit_pen);
458	461	}
459	462
460	463
r1103	r1104
471	474	*/
472	475	static void blit_rect_yh(void)
473	476	{
474		int start = 512 * dynax_blit_y;
475		int length = 512 * (dynax_rect_height+1);
	477	int start = 512 * ddenlovr_blit_y;
	478	int length = 512 * (ddenlovr_rect_height+1);
476	479
477	480	#ifdef MAME_DEBUG
478		// if (dynax_clip_ctrl != 0x0f)
479		// popmessage("UNK8C clipx=%03x clipy=%03x ctrl=%x",dynax_clip_x,dynax_clip_y,dynax_clip_ctrl);
	481	// if (ddenlovr_clip_ctrl != 0x0f)
	482	// popmessage("UNK8C clipx=%03x clipy=%03x ctrl=%x",ddenlovr_clip_x,ddenlovr_clip_y,ddenlovr_clip_ctrl);
480	483	#endif
481	484
482	485	if (start < 512*512)
r1103	r1104
484	487	if (start + length > 512*512)
485	488	length = 512*512 - start;
486	489
487		if (dynax_dest_layer & 0x0001) memset(pixmap[0] + start,dynax_blit_pen,length);
488		if (dynax_dest_layer & 0x0002) memset(pixmap[1] + start,dynax_blit_pen,length);
489		if (dynax_dest_layer & 0x0004) memset(pixmap[2] + start,dynax_blit_pen,length);
490		if (dynax_dest_layer & 0x0008) memset(pixmap[3] + start,dynax_blit_pen,length);
	490	if (ddenlovr_dest_layer & 0x0001) memset(ddenlovr_pixmap[0] + start,ddenlovr_blit_pen,length);
	491	if (ddenlovr_dest_layer & 0x0002) memset(ddenlovr_pixmap[1] + start,ddenlovr_blit_pen,length);
	492	if (ddenlovr_dest_layer & 0x0004) memset(ddenlovr_pixmap[2] + start,ddenlovr_blit_pen,length);
	493	if (ddenlovr_dest_layer & 0x0008) memset(ddenlovr_pixmap[3] + start,ddenlovr_blit_pen,length);
491	494
492	495	if (!extra_layers) return;
493	496
494		if (dynax_dest_layer & 0x0100) memset(pixmap[4] + start,dynax_blit_pen,length);
495		if (dynax_dest_layer & 0x0200) memset(pixmap[5] + start,dynax_blit_pen,length);
496		if (dynax_dest_layer & 0x0400) memset(pixmap[6] + start,dynax_blit_pen,length);
497		if (dynax_dest_layer & 0x0800) memset(pixmap[7] + start,dynax_blit_pen,length);
	497	if (ddenlovr_dest_layer & 0x0100) memset(ddenlovr_pixmap[4] + start,ddenlovr_blit_pen,length);
	498	if (ddenlovr_dest_layer & 0x0200) memset(ddenlovr_pixmap[5] + start,ddenlovr_blit_pen,length);
	499	if (ddenlovr_dest_layer & 0x0400) memset(ddenlovr_pixmap[6] + start,ddenlovr_blit_pen,length);
	500	if (ddenlovr_dest_layer & 0x0800) memset(ddenlovr_pixmap[7] + start,ddenlovr_blit_pen,length);
498	501	}
499	502	}
500	503
501	504
502	505
503		/* Fill from (X,Y) to end of pixmap
	506	/* Fill from (X,Y) to end of ddenlovr_pixmap
504	507	initialized arguments are
505	508	00 dest layer
506	509	05 unknown, related to layer
r1103	r1104
517	520	// popmessage("FILL command X %03x Y %03x",x,y);
518	521	#endif
519	522
520		if (dynax_dest_layer & 0x0001) memset(pixmap[0] + start,dynax_blit_pen,512*512 - start);
521		if (dynax_dest_layer & 0x0002) memset(pixmap[1] + start,dynax_blit_pen,512*512 - start);
522		if (dynax_dest_layer & 0x0004) memset(pixmap[2] + start,dynax_blit_pen,512*512 - start);
523		if (dynax_dest_layer & 0x0008) memset(pixmap[3] + start,dynax_blit_pen,512*512 - start);
	523	if (ddenlovr_dest_layer & 0x0001) memset(ddenlovr_pixmap[0] + start,ddenlovr_blit_pen,512*512 - start);
	524	if (ddenlovr_dest_layer & 0x0002) memset(ddenlovr_pixmap[1] + start,ddenlovr_blit_pen,512*512 - start);
	525	if (ddenlovr_dest_layer & 0x0004) memset(ddenlovr_pixmap[2] + start,ddenlovr_blit_pen,512*512 - start);
	526	if (ddenlovr_dest_layer & 0x0008) memset(ddenlovr_pixmap[3] + start,ddenlovr_blit_pen,512*512 - start);
524	527
525	528	if (!extra_layers) return;
526	529
527		if (dynax_dest_layer & 0x0100) memset(pixmap[4] + start,dynax_blit_pen,512*512 - start);
528		if (dynax_dest_layer & 0x0200) memset(pixmap[5] + start,dynax_blit_pen,512*512 - start);
529		if (dynax_dest_layer & 0x0400) memset(pixmap[6] + start,dynax_blit_pen,512*512 - start);
530		if (dynax_dest_layer & 0x0800) memset(pixmap[7] + start,dynax_blit_pen,512*512 - start);
	530	if (ddenlovr_dest_layer & 0x0100) memset(ddenlovr_pixmap[4] + start,ddenlovr_blit_pen,512*512 - start);
	531	if (ddenlovr_dest_layer & 0x0200) memset(ddenlovr_pixmap[5] + start,ddenlovr_blit_pen,512*512 - start);
	532	if (ddenlovr_dest_layer & 0x0400) memset(ddenlovr_pixmap[6] + start,ddenlovr_blit_pen,512*512 - start);
	533	if (ddenlovr_dest_layer & 0x0800) memset(ddenlovr_pixmap[7] + start,ddenlovr_blit_pen,512*512 - start);
531	534	}
532	535
533	536
r1103	r1104
540	543	02 Y
541	544	0c line length
542	545	04 blit_pen
543		dynax_blit_x and dynax_blit_y are left pointing to the last pixel at the end of the command
	546	ddenlovr_blit_x and ddenlovr_blit_y are left pointing to the last pixel at the end of the command
544	547	*/
545	548	static void blit_horiz_line(void)
546	549	{
r1103	r1104
549	552	#ifdef MAME_DEBUG
550	553	popmessage("LINE X");
551	554
552		if (dynax_clip_ctrl != 0x0f)
553		popmessage("LINE X clipx=%03x clipy=%03x ctrl=%x",dynax_clip_x,dynax_clip_y,dynax_clip_ctrl);
	555	if (ddenlovr_clip_ctrl != 0x0f)
	556	popmessage("LINE X clipx=%03x clipy=%03x ctrl=%x",ddenlovr_clip_x,ddenlovr_clip_y,ddenlovr_clip_ctrl);
554	557
555		if (dynax_blit_flip)
556		popmessage("LINE X flip=%x",dynax_blit_flip);
	558	if (ddenlovr_blit_flip)
	559	popmessage("LINE X flip=%x",ddenlovr_blit_flip);
557	560	#endif
558	561
559		for (i = 0; i <= dynax_line_length; i++)
560		do_plot(dynax_blit_x++,dynax_blit_y,dynax_blit_pen);
	562	for (i = 0; i <= ddenlovr_line_length; i++)
	563	do_plot(ddenlovr_blit_x++,ddenlovr_blit_y,ddenlovr_blit_pen);
561	564	}
562	565
563	566
r1103	r1104
570	573	02 Y
571	574	0c line length
572	575	04 blit_pen
573		dynax_blit_x and dynax_blit_y are left pointing to the last pixel at the end of the command
	576	ddenlovr_blit_x and ddenlovr_blit_y are left pointing to the last pixel at the end of the command
574	577	*/
575	578	static void blit_vert_line(void)
576	579	{
r1103	r1104
579	582	#ifdef MAME_DEBUG
580	583	popmessage("LINE Y");
581	584
582		if (dynax_clip_ctrl != 0x0f)
583		popmessage("LINE Y clipx=%03x clipy=%03x ctrl=%x",dynax_clip_x,dynax_clip_y,dynax_clip_ctrl);
	585	if (ddenlovr_clip_ctrl != 0x0f)
	586	popmessage("LINE Y clipx=%03x clipy=%03x ctrl=%x",ddenlovr_clip_x,ddenlovr_clip_y,ddenlovr_clip_ctrl);
584	587	#endif
585	588
586		for (i = 0; i <= dynax_line_length; i++)
587		do_plot(dynax_blit_x,dynax_blit_y++,dynax_blit_pen);
	589	for (i = 0; i <= ddenlovr_line_length; i++)
	590	do_plot(ddenlovr_blit_x,ddenlovr_blit_y++,ddenlovr_blit_pen);
588	591	}
589	592
590	593
r1103	r1104
595	598	#if 1
596	599	logerror("%06x: blit src %06x x %03x y %03x flags %02x layer %02x pen %02x penmode %02x w %03x h %03x linelen %03x clip: ctrl %x xy %03x %03x wh %03x %03x\n",
597	600	activecpu_get_pc(),
598		dynax_blit_address,dynax_blit_x,dynax_blit_y,data,
599		dynax_dest_layer,dynax_blit_pen,dynax_blit_pen_mode,dynax_rect_width,dynax_rect_height,dynax_line_length,
600		dynax_clip_ctrl,dynax_clip_x,dynax_clip_y, dynax_clip_width,dynax_clip_height );
	601	ddenlovr_blit_address,ddenlovr_blit_x,ddenlovr_blit_y,data,
	602	ddenlovr_dest_layer,ddenlovr_blit_pen,ddenlovr_blit_pen_mode,ddenlovr_rect_width,ddenlovr_rect_height,ddenlovr_line_length,
	603	ddenlovr_clip_ctrl,ddenlovr_clip_x,ddenlovr_clip_y, ddenlovr_clip_width,ddenlovr_clip_height );
601	604	#endif
602	605	}
603	606
604	607	static void blitter_w(int blitter, offs_t offset,UINT8 data,int irq_vector)
605	608	{
606		static int dynax_blit_reg[2];
	609	static int ddenlovr_blit_reg[2];
607	610	int hi_bits;
608	611
609	612	profiler_mark(PROFILER_VIDEO);
r1103	r1104
611	614	switch(offset)
612	615	{
613	616	case 0:
614		dynax_blit_reg[blitter] = data;
	617	ddenlovr_blit_reg[blitter] = data;
615	618	break;
616	619
617	620	case 1:
618		hi_bits = (dynax_blit_reg[blitter] & 0xc0) << 2;
	621	hi_bits = (ddenlovr_blit_reg[blitter] & 0xc0) << 2;
619	622
620		switch(dynax_blit_reg[blitter] & 0x3f)
	623	switch(ddenlovr_blit_reg[blitter] & 0x3f)
621	624	{
622	625	case 0x00:
623		if (blitter) dynax_dest_layer = (dynax_dest_layer & 0x00ff) \| (data<<8);
624		else dynax_dest_layer = (dynax_dest_layer & 0xff00) \| (data<<0);
	626	if (blitter) ddenlovr_dest_layer = (ddenlovr_dest_layer & 0x00ff) \| (data<<8);
	627	else ddenlovr_dest_layer = (ddenlovr_dest_layer & 0xff00) \| (data<<0);
625	628	break;
626	629
627	630	case 0x01:
628		dynax_flipscreen_w(data);
	631	ddenlovr_flipscreen_w(data);
629	632	break;
630	633
631	634	case 0x02:
632		dynax_blit_y = data \| hi_bits;
	635	ddenlovr_blit_y = data \| hi_bits;
633	636	break;
634	637
635	638	case 0x03:
636		dynax_blit_flip_w(data);
	639	ddenlovr_blit_flip_w(data);
637	640	break;
638	641
639	642	case 0x04:
640		dynax_blit_pen = data;
	643	ddenlovr_blit_pen = data;
641	644	break;
642	645
643	646	case 0x05:
644		dynax_blit_pen_mask = data;
	647	ddenlovr_blit_pen_mask = data;
645	648	break;
646	649
647	650	case 0x06:
648	651	// related to pen, can be 0 or 1 for 0x10 blitter command
649		// 0 = only bits 7-4 of dynax_blit_pen contain data
	652	// 0 = only bits 7-4 of ddenlovr_blit_pen contain data
650	653	// 1 = bits 3-0 contain data as well
651		dynax_blit_pen_mode = data;
	654	ddenlovr_blit_pen_mode = data;
652	655	break;
653	656
654	657	case 0x0a:
655		dynax_rect_width = data \| hi_bits;
	658	ddenlovr_rect_width = data \| hi_bits;
656	659	break;
657	660
658	661	case 0x0b:
659		dynax_rect_height = data \| hi_bits;
	662	ddenlovr_rect_height = data \| hi_bits;
660	663	break;
661	664
662	665	case 0x0c:
663		dynax_line_length = data \| hi_bits;
	666	ddenlovr_line_length = data \| hi_bits;
664	667	break;
665	668
666	669	case 0x0d:
667		dynax_blit_address = (dynax_blit_address & 0xffff00) \| (data <<0);
	670	ddenlovr_blit_address = (ddenlovr_blit_address & 0xffff00) \| (data <<0);
668	671	break;
669	672	case 0x0e:
670		dynax_blit_address = (dynax_blit_address & 0xff00ff) \| (data <<8);
	673	ddenlovr_blit_address = (ddenlovr_blit_address & 0xff00ff) \| (data <<8);
671	674	break;
672	675	case 0x0f:
673		dynax_blit_address = (dynax_blit_address & 0x00ffff) \| (data<<16);
	676	ddenlovr_blit_address = (ddenlovr_blit_address & 0x00ffff) \| (data<<16);
674	677	break;
675	678
676	679	case 0x14:
677		dynax_blit_x = data \| hi_bits;
	680	ddenlovr_blit_x = data \| hi_bits;
678	681	break;
679	682
680	683	case 0x16:
681		dynax_clip_x = data \| hi_bits;
	684	ddenlovr_clip_x = data \| hi_bits;
682	685	break;
683	686
684	687	case 0x17:
685		dynax_clip_y = data \| hi_bits;
	688	ddenlovr_clip_y = data \| hi_bits;
686	689	break;
687	690
688	691	case 0x18:
r1103	r1104
693	696	case 0x1d:
694	697	case 0x1e:
695	698	case 0x1f:
696		dynax_scroll[blitter*8 + (dynax_blit_reg[blitter] & 7)] = data \| hi_bits;
	699	ddenlovr_scroll[blitter*8 + (ddenlovr_blit_reg[blitter] & 7)] = data \| hi_bits;
697	700	break;
698	701
699	702	case 0x20:
700		dynax_clip_ctrl = data;
	703	ddenlovr_clip_ctrl = data;
701	704	break;
702	705
703	706	case 0x24:
r1103	r1104
708	711	{
709	712	case 0x04: blit_fill_xy(0, 0);
710	713	break;
711		case 0x14: blit_fill_xy(dynax_blit_x, dynax_blit_y);
	714	case 0x14: blit_fill_xy(ddenlovr_blit_x, ddenlovr_blit_y);
712	715	break;
713	716
714		case 0x10: dynax_blit_address = blit_draw(dynax_blit_address,dynax_blit_x);
	717	case 0x10: ddenlovr_blit_address = blit_draw(ddenlovr_blit_address,ddenlovr_blit_x);
715	718	break;
716	719
717	720	case 0x13: blit_horiz_line();
r1103	r1104
745	748	else
746	749	{
747	750	/* ddenlovr */
748		if (dynax_blitter_irq_enable)
	751	if (ddenlovr_blitter_irq_enable)
749	752	{
750		dynax_blitter_irq_flag = 1;
	753	ddenlovr_blitter_irq_flag = 1;
751	754	cpunum_set_input_line(0,1,HOLD_LINE);
752	755	}
753	756	}
754	757	break;
755	758
756	759	default:
757		logerror("%06x: Blitter %d reg %02x = %02x\n", activecpu_get_pc(), blitter, dynax_blit_reg[blitter], data);
	760	logerror("%06x: Blitter %d reg %02x = %02x\n", activecpu_get_pc(), blitter, ddenlovr_blit_reg[blitter], data);
758	761	break;
759	762	}
760	763	}
r1103	r1104
768	771	// differences wrt blitter_data_w: slightly different blitter commands
769	772	static void blitter_w_funkyfig(int blitter, offs_t offset,UINT8 data,int irq_vector)
770	773	{
771		static int dynax_blit_reg[2];
	774	static int ddenlovr_blit_reg[2];
772	775	int hi_bits;
773	776
774	777	profiler_mark(PROFILER_VIDEO);
r1103	r1104
776	779	switch(offset)
777	780	{
778	781	case 0:
779		dynax_blit_reg[blitter] = data;
	782	ddenlovr_blit_reg[blitter] = data;
780	783	break;
781	784
782	785	case 1:
783		hi_bits = (dynax_blit_reg[blitter] & 0xc0) << 2;
	786	hi_bits = (ddenlovr_blit_reg[blitter] & 0xc0) << 2;
784	787
785		switch(dynax_blit_reg[blitter] & 0x3f)
	788	switch(ddenlovr_blit_reg[blitter] & 0x3f)
786	789	{
787	790	case 0x00:
788		if (blitter) dynax_dest_layer = (dynax_dest_layer & 0x00ff) \| (data<<8);
789		else dynax_dest_layer = (dynax_dest_layer & 0xff00) \| (data<<0);
	791	if (blitter) ddenlovr_dest_layer = (ddenlovr_dest_layer & 0x00ff) \| (data<<8);
	792	else ddenlovr_dest_layer = (ddenlovr_dest_layer & 0xff00) \| (data<<0);
790	793	break;
791	794
792	795	case 0x01:
793		dynax_flipscreen_w(data);
	796	ddenlovr_flipscreen_w(data);
794	797	break;
795	798
796	799	case 0x02:
797		dynax_blit_y = data \| hi_bits;
	800	ddenlovr_blit_y = data \| hi_bits;
798	801	break;
799	802
800	803	case 0x03:
801		dynax_blit_flip_w(data);
	804	ddenlovr_blit_flip_w(data);
802	805	break;
803	806
804	807	case 0x04:
805		dynax_blit_pen = data;
	808	ddenlovr_blit_pen = data;
806	809	break;
807	810
808	811	case 0x05:
809		dynax_blit_pen_mask = data;
	812	ddenlovr_blit_pen_mask = data;
810	813	break;
811	814
812	815	case 0x06:
813	816	// related to pen, can be 0 or 1 for 0x10 blitter command
814		// 0 = only bits 7-4 of dynax_blit_pen contain data
	817	// 0 = only bits 7-4 of ddenlovr_blit_pen contain data
815	818	// 1 = bits 3-0 contain data as well
816		dynax_blit_pen_mode = data;
	819	ddenlovr_blit_pen_mode = data;
817	820	break;
818	821
819	822	case 0x0a:
820		dynax_rect_width = data \| hi_bits;
	823	ddenlovr_rect_width = data \| hi_bits;
821	824	break;
822	825
823	826	case 0x0b:
824		dynax_rect_height = data \| hi_bits;
	827	ddenlovr_rect_height = data \| hi_bits;
825	828	break;
826	829
827	830	case 0x0c:
828		dynax_line_length = data \| hi_bits;
	831	ddenlovr_line_length = data \| hi_bits;
829	832	break;
830	833
831	834	case 0x0d:
832		dynax_blit_address = (dynax_blit_address & 0xffff00) \| (data <<0);
	835	ddenlovr_blit_address = (ddenlovr_blit_address & 0xffff00) \| (data <<0);
833	836	break;
834	837	case 0x0e:
835		dynax_blit_address = (dynax_blit_address & 0xff00ff) \| (data <<8);
	838	ddenlovr_blit_address = (ddenlovr_blit_address & 0xff00ff) \| (data <<8);
836	839	break;
837	840	case 0x0f:
838		dynax_blit_address = (dynax_blit_address & 0x00ffff) \| (data<<16);
	841	ddenlovr_blit_address = (ddenlovr_blit_address & 0x00ffff) \| (data<<16);
839	842	break;
840	843
841	844	case 0x14:
842		dynax_blit_x = data \| hi_bits;
	845	ddenlovr_blit_x = data \| hi_bits;
843	846	break;
844	847
845	848	case 0x16:
846		dynax_clip_x = data \| hi_bits;
	849	ddenlovr_clip_x = data \| hi_bits;
847	850	break;
848	851
849	852	case 0x17:
850		dynax_clip_y = data \| hi_bits;
	853	ddenlovr_clip_y = data \| hi_bits;
851	854	break;
852	855
853	856	case 0x18:
r1103	r1104
858	861	case 0x1d:
859	862	case 0x1e:
860	863	case 0x1f:
861		dynax_scroll[blitter*8 + (dynax_blit_reg[blitter] & 7)] = data \| hi_bits;
	864	ddenlovr_scroll[blitter*8 + (ddenlovr_blit_reg[blitter] & 7)] = data \| hi_bits;
862	865	break;
863	866
864	867	case 0x20:
865		dynax_clip_ctrl = data;
	868	ddenlovr_clip_ctrl = data;
866	869	break;
867	870
868	871	case 0x24:
r1103	r1104
877	880	break;
878	881
879	882	// unused?
880		// case 0x14: blit_fill_xy(dynax_blit_x, dynax_blit_y);
	883	// case 0x14: blit_fill_xy(ddenlovr_blit_x, ddenlovr_blit_y);
881	884	// break;
882	885
883		case 0x00/0x10/: dynax_blit_address = blit_draw(dynax_blit_address,dynax_blit_x);
	886	case 0x00/0x10/: ddenlovr_blit_address = blit_draw(ddenlovr_blit_address,ddenlovr_blit_x);
884	887	break;
885	888
886	889	case 0x0b: // same as 03? see the drawing of the R in "cRoss hatch" (key test)
r1103	r1104
912	915	break;
913	916
914	917	default:
915		logerror("%06x: Blitter %d reg %02x = %02x\n", activecpu_get_pc(), blitter, dynax_blit_reg[blitter], data);
	918	logerror("%06x: Blitter %d reg %02x = %02x\n", activecpu_get_pc(), blitter, ddenlovr_blit_reg[blitter], data);
916	919	break;
917	920	}
918	921	}
r1103	r1104
925	928
926	929	static WRITE8_HANDLER( hanakanz_blitter_reg_w )
927	930	{
928		dynax_blit_reg = data;
	931	ddenlovr_blit_reg = data;
929	932	}
930	933
931	934	// differences wrt blitter_data_w: registers are shuffled around, hi_bits in the low bits, clip_w/h, includes layers registers
r1103	r1104
935	938
936	939	profiler_mark(PROFILER_VIDEO);
937	940
938		hi_bits = (dynax_blit_reg & 0x03) << 8;
	941	hi_bits = (ddenlovr_blit_reg & 0x03) << 8;
939	942
940		switch(dynax_blit_reg & 0xfe)
	943	switch(ddenlovr_blit_reg & 0xfe)
941	944	{
942	945	case 0x00:
943		dynax_dest_layer = data;
	946	ddenlovr_dest_layer = data;
944	947	break;
945	948
946	949	case 0x04:
947		dynax_flipscreen_w(data);
	950	ddenlovr_flipscreen_w(data);
948	951	break;
949	952
950	953	case 0x08:
951		dynax_blit_y = data \| hi_bits;
	954	ddenlovr_blit_y = data \| hi_bits;
952	955	break;
953	956
954	957	case 0x0c:
955		dynax_blit_flip_w(data);
	958	ddenlovr_blit_flip_w(data);
956	959	break;
957	960
958	961	case 0x10:
959		dynax_blit_pen = data;
	962	ddenlovr_blit_pen = data;
960	963	break;
961	964
962	965	case 0x14:
963		dynax_blit_pen_mask = data;
	966	ddenlovr_blit_pen_mask = data;
964	967	break;
965	968
966	969	case 0x18:
967	970	// related to pen, can be 0 or 1 for 0x10 blitter command
968		// 0 = only bits 7-4 of dynax_blit_pen contain data
	971	// 0 = only bits 7-4 of ddenlovr_blit_pen contain data
969	972	// 1 = bits 3-0 contain data as well
970		dynax_blit_pen_mode = data;
	973	ddenlovr_blit_pen_mode = data;
971	974	break;
972	975
973	976	case 0x28:
974		dynax_rect_width = data \| hi_bits;
	977	ddenlovr_rect_width = data \| hi_bits;
975	978	break;
976	979
977	980	case 0x2c:
978		dynax_rect_height = data \| hi_bits;
	981	ddenlovr_rect_height = data \| hi_bits;
979	982	break;
980	983
981	984	case 0x30:
982		dynax_line_length = data \| hi_bits;
	985	ddenlovr_line_length = data \| hi_bits;
983	986	break;
984	987
985	988	case 0x34:
986		dynax_blit_address = (dynax_blit_address & 0xffff00) \| (data <<0);
	989	ddenlovr_blit_address = (ddenlovr_blit_address & 0xffff00) \| (data <<0);
987	990	break;
988	991	case 0x38:
989		dynax_blit_address = (dynax_blit_address & 0xff00ff) \| (data <<8);
	992	ddenlovr_blit_address = (ddenlovr_blit_address & 0xff00ff) \| (data <<8);
990	993	break;
991	994	case 0x3c:
992		dynax_blit_address = (dynax_blit_address & 0x00ffff) \| (data<<16);
	995	ddenlovr_blit_address = (ddenlovr_blit_address & 0x00ffff) \| (data<<16);
993	996	break;
994	997
995	998	case 0x50:
996		dynax_blit_x = data \| hi_bits;
	999	ddenlovr_blit_x = data \| hi_bits;
997	1000	break;
998	1001
999	1002	case 0x58:
1000		dynax_clip_x = data \| hi_bits;
	1003	ddenlovr_clip_x = data \| hi_bits;
1001	1004	break;
1002	1005
1003	1006	case 0x5c:
1004		dynax_clip_y = data \| hi_bits;
	1007	ddenlovr_clip_y = data \| hi_bits;
1005	1008	break;
1006	1009
1007	1010	case 0x60:
r1103	r1104
1012	1015	case 0x74:
1013	1016	case 0x78:
1014	1017	case 0x7c:
1015		dynax_scroll[(dynax_blit_reg & 0x1c) >> 2] = data \| hi_bits;
	1018	ddenlovr_scroll[(ddenlovr_blit_reg & 0x1c) >> 2] = data \| hi_bits;
1016	1019	break;
1017	1020
1018	1021	case 0x80:
1019		dynax_clip_ctrl = data;
	1022	ddenlovr_clip_ctrl = data;
1020	1023	break;
1021	1024
1022	1025	case 0x88:
1023	1026	case 0x8a: // can be 3ff
1024		dynax_clip_height = data \| hi_bits;
	1027	ddenlovr_clip_height = data \| hi_bits;
1025	1028	break;
1026	1029
1027	1030	case 0x8c:
1028	1031	case 0x8e: // can be 3ff
1029		dynax_clip_width = data \| hi_bits;
	1032	ddenlovr_clip_width = data \| hi_bits;
1030	1033	break;
1031	1034
1032	1035	case 0xc0:
1033	1036	case 0xc2:
1034	1037	case 0xc4:
1035	1038	case 0xc6:
1036		dynax_palette_base[(dynax_blit_reg >> 1) & 3] = data \| (hi_bits & 0x100);
	1039	ddenlovr_palette_base[(ddenlovr_blit_reg >> 1) & 3] = data \| (hi_bits & 0x100);
1037	1040	break;
1038	1041
1039	1042	case 0xc8:
1040	1043	case 0xca:
1041	1044	case 0xcc:
1042	1045	case 0xce:
1043		dynax_palette_mask[(dynax_blit_reg >> 1) & 3] = data;
	1046	ddenlovr_palette_mask[(ddenlovr_blit_reg >> 1) & 3] = data;
1044	1047	break;
1045	1048
1046	1049	case 0xd0:
1047	1050	case 0xd2:
1048	1051	case 0xd4:
1049	1052	case 0xd6:
1050		dynax_transparency_pen[(dynax_blit_reg >> 1) & 3] = data;
	1053	ddenlovr_transparency_pen[(ddenlovr_blit_reg >> 1) & 3] = data;
1051	1054	break;
1052	1055
1053	1056	case 0xd8:
1054	1057	case 0xda:
1055	1058	case 0xdc:
1056	1059	case 0xde:
1057		dynax_transparency_mask[(dynax_blit_reg >> 1) & 3] = data;
	1060	ddenlovr_transparency_mask[(ddenlovr_blit_reg >> 1) & 3] = data;
1058	1061	break;
1059	1062
1060	1063	case 0xe4:
1061		dynax_priority_w(0,data);
	1064	ddenlovr_priority_w(0,data);
1062	1065	break;
1063	1066
1064	1067	case 0xe6:
1065		dynax_layer_enable_w(0,data);
	1068	ddenlovr_layer_enable_w(0,data);
1066	1069	break;
1067	1070
1068	1071	case 0xe8:
1069		dynax_bgcolor = data \| hi_bits;
	1072	ddenlovr_bgcolor = data \| hi_bits;
1070	1073	break;
1071	1074
1072	1075	case 0x90:
r1103	r1104
1077	1080	{
1078	1081	case 0x04: blit_fill_xy(0, 0);
1079	1082	break;
1080		case 0x14: blit_fill_xy(dynax_blit_x, dynax_blit_y);
	1083	case 0x14: blit_fill_xy(ddenlovr_blit_x, ddenlovr_blit_y);
1081	1084	break;
1082	1085
1083		case 0x10: dynax_blit_address = blit_draw(dynax_blit_address,dynax_blit_x);
	1086	case 0x10: ddenlovr_blit_address = blit_draw(ddenlovr_blit_address,ddenlovr_blit_x);
1084	1087	break;
1085	1088
1086	1089	case 0x13: blit_horiz_line();
r1103	r1104
1111	1114	break;
1112	1115
1113	1116	default:
1114		logerror("%06x: Blitter 0 reg %02x = %02x\n", activecpu_get_pc(), dynax_blit_reg, data);
	1117	logerror("%06x: Blitter 0 reg %02x = %02x\n", activecpu_get_pc(), ddenlovr_blit_reg, data);
1115	1118	break;
1116	1119	}
1117	1120
r1103	r1104
1137	1140	{
1138	1141	if (data & 1)
1139	1142	{
1140		dynax_blitter_irq_enable = 1;
	1143	ddenlovr_blitter_irq_enable = 1;
1141	1144	}
1142	1145	else
1143	1146	{
1144		dynax_blitter_irq_enable = 0;
1145		dynax_blitter_irq_flag = 0;
	1147	ddenlovr_blitter_irq_enable = 0;
	1148	ddenlovr_blitter_irq_flag = 0;
1146	1149	}
1147	1150	}
1148	1151	}
r1103	r1104
1152	1155	{
1153	1156	UINT8 *rom = memory_region( REGION_GFX1 );
1154	1157	size_t size = memory_region_length( REGION_GFX1 );
1155		int address = dynax_blit_address;
	1158	int address = ddenlovr_blit_address;
1156	1159
1157	1160	if (address >= size)
1158	1161	{
r1103	r1104
1160	1163	address %= size;
1161	1164	}
1162	1165
1163		dynax_blit_address = (dynax_blit_address + 1) & 0xffffff;
	1166	ddenlovr_blit_address = (ddenlovr_blit_address + 1) & 0xffffff;
1164	1167
1165	1168	return rom[address];
1166	1169	}
r1103	r1104
1175	1178	static void copylayer(mame_bitmap bitmap,const rectangle cliprect,int layer)
1176	1179	{
1177	1180	int x,y;
1178		int scrollx = dynax_scroll[layer/4*8 + (layer%4) + 0];
1179		int scrolly = dynax_scroll[layer/4*8 + (layer%4) + 4];
	1181	int scrollx = ddenlovr_scroll[layer/4*8 + (layer%4) + 0];
	1182	int scrolly = ddenlovr_scroll[layer/4*8 + (layer%4) + 4];
1180	1183
1181		int palbase = dynax_palette_base[layer];
1182		int penmask = dynax_palette_mask[layer];
	1184	int palbase = ddenlovr_palette_base[layer];
	1185	int penmask = ddenlovr_palette_mask[layer];
1183	1186
1184		int transpen = dynax_transparency_pen[layer];
1185		int transmask = dynax_transparency_mask[layer];
	1187	int transpen = ddenlovr_transparency_pen[layer];
	1188	int transmask = ddenlovr_transparency_mask[layer];
1186	1189
1187	1190	palbase &= ~penmask;
1188	1191	transpen &= transmask;
1189	1192
1190		if (((dynax_layer_enable2 << 4) \| dynax_layer_enable) & (1 << layer))
	1193	if (((ddenlovr_layer_enable2 << 4) \| ddenlovr_layer_enable) & (1 << layer))
1191	1194	{
1192	1195	for (y = cliprect->min_y;y <= cliprect->max_y;y++)
1193	1196	{
1194	1197	for (x = cliprect->min_x;x <= cliprect->max_x;x++)
1195	1198	{
1196		int pen = pixmap[layer][512 * ((y + scrolly) & 0x1ff) + ((x + scrollx) & 0x1ff)];
	1199	int pen = ddenlovr_pixmap[layer][512 * ((y + scrolly) & 0x1ff) + ((x + scrollx) & 0x1ff)];
1197	1200	if ( (pen & transmask) != transpen )
1198	1201	{
1199	1202	pen &= penmask;
r1103	r1104
1227	1230
1228	1231	int pri;
1229	1232
1230		int enab = dynax_layer_enable;
1231		int enab2 = dynax_layer_enable2;
	1233	int enab = ddenlovr_layer_enable;
	1234	int enab2 = ddenlovr_layer_enable2;
1232	1235
1233	1236	#if 0
1234	1237	static int base = 0x0;
1235	1238
1236	1239	int next;
1237		memset(pixmap[0],0,512*512);
1238		memset(pixmap[1],0,512*512);
1239		memset(pixmap[2],0,512*512);
1240		memset(pixmap[3],0,512*512);
1241		dynax_dest_layer = 8;
1242		dynax_blit_pen = 0;
1243		dynax_blit_pen_mode = 0;
1244		dynax_blit_y = 5;
1245		dynax_clip_ctrl = 0x0f;
	1240	memset(ddenlovr_pixmap[0],0,512*512);
	1241	memset(ddenlovr_pixmap[1],0,512*512);
	1242	memset(ddenlovr_pixmap[2],0,512*512);
	1243	memset(ddenlovr_pixmap[3],0,512*512);
	1244	ddenlovr_dest_layer = 8;
	1245	ddenlovr_blit_pen = 0;
	1246	ddenlovr_blit_pen_mode = 0;
	1247	ddenlovr_blit_y = 5;
	1248	ddenlovr_clip_ctrl = 0x0f;
1246	1249	next = blit_draw(base,0);
1247	1250	popmessage("GFX %06x",base);
1248	1251	if (input_code_pressed(KEYCODE_S)) base = next;
r1103	r1104
1253	1256	if (input_code_pressed_once(KEYCODE_F)) { base++; while ((memory_region(REGION_GFX1)[base] & 0xf0) != 0x30) base++; }
1254	1257	#endif
1255	1258
1256		fillbitmap(framebuffer,dynax_bgcolor,&machine->screen[0].visarea);
	1259	fillbitmap(framebuffer,ddenlovr_bgcolor,&machine->screen[0].visarea);
1257	1260
1258	1261	#ifdef MAME_DEBUG
1259	1262	if (input_code_pressed(KEYCODE_Z))
r1103	r1104
1279	1282
1280	1283	if (mask \|\| mask2)
1281	1284	{
1282		dynax_layer_enable &= mask;
1283		dynax_layer_enable2 &= mask2;
	1285	ddenlovr_layer_enable &= mask;
	1286	ddenlovr_layer_enable2 &= mask2;
1284	1287	}
1285	1288	}
1286	1289	#endif
1287	1290
1288		pri = dynax_priority;
	1291	pri = ddenlovr_priority;
1289	1292
1290	1293	if (pri >= 24)
1291	1294	{
r1103	r1104
1300	1303
1301	1304	if (extra_layers)
1302	1305	{
1303		pri = dynax_priority2;
	1306	pri = ddenlovr_priority2;
1304	1307
1305	1308	if (pri >= 24)
1306	1309	{
r1103	r1104
1314	1317	copylayer(framebuffer,&machine->screen[0].visarea,order[pri][3]+4);
1315	1318	}
1316	1319
1317		dynax_layer_enable = enab;
1318		dynax_layer_enable2 = enab2;
	1320	ddenlovr_layer_enable = enab;
	1321	ddenlovr_layer_enable2 = enab2;
1319	1322	}
1320	1323
1321	1324	READ16_HANDLER( ddenlovr_special_r )
1322	1325	{
1323		int res = readinputport(2) \| (dynax_blitter_irq_flag << 6);
	1326	int res = readinputport(2) \| (ddenlovr_blitter_irq_flag << 6);
1324	1327
1325	1328	return res;
1326	1329	}
r1103	r1104
1364	1367	}
1365	1368
1366	1369
1367		~~static~~ WRITE8_HANDLER( dynax_palette_base_w )
	1370	WRITE8_HANDLER( ddenlovr_palette_base_w )
1368	1371	{
1369		dynax_palette_base[offset] = data;
	1372	ddenlovr_palette_base[offset] = data;
1370	1373	}
1371		~~static~~ WRITE8_HANDLER( dynax_palette_base2_w )
	1374	WRITE8_HANDLER( ddenlovr_palette_base2_w )
1372	1375	{
1373		dynax_palette_base[offset+4] = data;
	1376	ddenlovr_palette_base[offset+4] = data;
1374	1377	}
1375	1378
1376		~~static~~ WRITE8_HANDLER( dynax_palette_mask_w )
	1379	WRITE8_HANDLER( ddenlovr_palette_mask_w )
1377	1380	{
1378		dynax_palette_mask[offset] = data;
	1381	ddenlovr_palette_mask[offset] = data;
1379	1382	}
1380		~~static~~ WRITE8_HANDLER( dynax_palette_mask2_w )
	1383	WRITE8_HANDLER( ddenlovr_palette_mask2_w )
1381	1384	{
1382		dynax_palette_mask[offset+4] = data;
	1385	ddenlovr_palette_mask[offset+4] = data;
1383	1386	}
1384	1387
1385		~~static~~ WRITE8_HANDLER( dynax_transparency_pen_w )
	1388	WRITE8_HANDLER( ddenlovr_transparency_pen_w )
1386	1389	{
1387		dynax_transparency_pen[offset] = data;
	1390	ddenlovr_transparency_pen[offset] = data;
1388	1391	}
1389		~~static~~ WRITE8_HANDLER( dynax_transparency_pen2_w )
	1392	WRITE8_HANDLER( ddenlovr_transparency_pen2_w )
1390	1393	{
1391		dynax_transparency_pen[offset+4] = data;
	1394	ddenlovr_transparency_pen[offset+4] = data;
1392	1395	}
1393	1396
1394		~~static~~ WRITE8_HANDLER( dynax_transparency_mask_w )
	1397	WRITE8_HANDLER( ddenlovr_transparency_mask_w )
1395	1398	{
1396		dynax_transparency_mask[offset] = data;
	1399	ddenlovr_transparency_mask[offset] = data;
1397	1400	}
1398		~~static~~ WRITE8_HANDLER( dynax_transparency_mask2_w )
	1401	WRITE8_HANDLER( ddenlovr_transparency_mask2_w )
1399	1402	{
1400		dynax_transparency_mask[offset+4] = data;
	1403	ddenlovr_transparency_mask[offset+4] = data;
1401	1404	}
1402	1405
1403	1406
1404		~~static~~ WRITE16_HANDLER( ddenlovr_palette_base_w )
	1407	WRITE16_HANDLER( ddenlovr16_palette_base_w )
1405	1408	{
1406	1409	if (ACCESSING_LSB)
1407		dynax_palette_base[offset] = data & 0xff;
	1410	ddenlovr_palette_base[offset] = data & 0xff;
1408	1411	}
1409	1412
1410		~~static~~ WRITE16_HANDLER( ddenlovr_palette_mask_w )
	1413	WRITE16_HANDLER( ddenlovr16_palette_mask_w )
1411	1414	{
1412	1415	if (ACCESSING_LSB)
1413		dynax_palette_mask[offset] = data & 0xff;
	1416	ddenlovr_palette_mask[offset] = data & 0xff;
1414	1417	}
1415	1418
1416		~~static~~ WRITE16_HANDLER( ddenlovr_transparency_pen_w )
	1419	WRITE16_HANDLER( ddenlovr16_transparency_pen_w )
1417	1420	{
1418	1421	if (ACCESSING_LSB)
1419		dynax_transparency_pen[offset] = data & 0xff;
	1422	ddenlovr_transparency_pen[offset] = data & 0xff;
1420	1423	}
1421	1424
1422		~~static~~ WRITE16_HANDLER( ddenlovr_transparency_mask_w )
	1425	WRITE16_HANDLER( ddenlovr16_transparency_mask_w )
1423	1426	{
1424	1427	if (ACCESSING_LSB)
1425		dynax_transparency_mask[offset] = data & 0xff;
	1428	ddenlovr_transparency_mask[offset] = data & 0xff;
1426	1429	}
1427	1430
1428	1431
r1103	r1104
1471	1474	}
1472	1475
1473	1476
1474		static UINT8 dynax_select, dynax_select2;
	1477	static UINT8 ddenlovr_select, ddenlovr_select2;
1475	1478
1476		WRITE8_HANDLER( dynax_select_w )
	1479	WRITE8_HANDLER( ddenlovr_select_w )
1477	1480	{
1478		dynax_select = data;
	1481	ddenlovr_select = data;
1479	1482	}
1480	1483
1481		WRITE16_HANDLER( dynax_select_16_w )
	1484	WRITE16_HANDLER( ddenlovr_select_16_w )
1482	1485	{
1483	1486	if (ACCESSING_LSB)
1484		dynax_select = data;
	1487	ddenlovr_select = data;
1485	1488	}
1486	1489
1487		WRITE8_HANDLER( dynax_select2_w )
	1490	WRITE8_HANDLER( ddenlovr_select2_w )
1488	1491	{
1489		dynax_select2 = data;
	1492	ddenlovr_select2 = data;
1490	1493	}
1491	1494
1492		WRITE16_HANDLER( dynax_select2_16_w )
	1495	WRITE16_HANDLER( ddenlovr_select2_16_w )
1493	1496	{
1494	1497	if (ACCESSING_LSB)
1495		dynax_select2 = data;
	1498	ddenlovr_select2 = data;
1496	1499	}
1497	1500
1498	1501	READ8_HANDLER( rongrong_input2_r )
1499	1502	{
1500		// logerror("%04x: input2_r offset %d select %x\n",activecpu_get_pc(),offset,dynax_select2 );
	1503	// logerror("%04x: input2_r offset %d select %x\n",activecpu_get_pc(),offset,ddenlovr_select2 );
1501	1504	/* 0 and 1 are read from offset 1, 2 from offset 0... */
1502		switch( dynax_select2 )
	1505	switch( ddenlovr_select2 )
1503	1506	{
1504	1507	case 0x00: return readinputport(0);
1505	1508	case 0x01: return readinputport(1);
r1103	r1104
1511	1514
1512	1515	READ8_HANDLER( quiz365_input_r )
1513	1516	{
1514		if (!(dynax_select & 0x01)) return readinputport(3);
1515		if (!(dynax_select & 0x02)) return readinputport(4);
1516		if (!(dynax_select & 0x04)) return readinputport(5);
1517		if (!(dynax_select & 0x08)) return 0xff;//mame_rand(Machine);
1518		if (!(dynax_select & 0x10)) return 0xff;//mame_rand(Machine);
	1517	if (!(ddenlovr_select & 0x01)) return readinputport(3);
	1518	if (!(ddenlovr_select & 0x02)) return readinputport(4);
	1519	if (!(ddenlovr_select & 0x04)) return readinputport(5);
	1520	if (!(ddenlovr_select & 0x08)) return 0xff;//mame_rand(Machine);
	1521	if (!(ddenlovr_select & 0x10)) return 0xff;//mame_rand(Machine);
1519	1522	return 0xff;
1520	1523	}
1521	1524
1522	1525	READ16_HANDLER( quiz365_input2_r )
1523	1526	{
1524		// logerror("%04x: input2_r offset %d select %x\n",activecpu_get_pc(),offset,dynax_select2 );
	1527	// logerror("%04x: input2_r offset %d select %x\n",activecpu_get_pc(),offset,ddenlovr_select2 );
1525	1528	/* 0 and 1 are read from offset 1, 2 from offset 0... */
1526		switch( dynax_select2 )
	1529	switch( ddenlovr_select2 )
1527	1530	{
1528	1531	case 0x10: return readinputport(0);
1529	1532	case 0x11: return readinputport(1);
1530		case 0x12: return readinputport(2) \| (dynax_blitter_irq_flag << 6);
	1533	case 0x12: return readinputport(2) \| (ddenlovr_blitter_irq_flag << 6);
1531	1534	}
1532	1535	return 0xff;
1533	1536	}
r1103	r1104
1557	1560	{
1558	1561	if (ACCESSING_LSB)
1559	1562	{
1560		if (dynax_select2 == 0x1c)
	1563	if (ddenlovr_select2 == 0x1c)
1561	1564	{
1562	1565	coin_counter_w(0, ~data & 1);
1563	1566	coin_counter_w(1, ~data & 4);
r1103	r1104
1602	1605	AM_RANGE(0x200000, 0x2003ff) AM_WRITE(ddenlovr_palette_w ) // Palette
1603	1606	AM_RANGE(0x200e0a, 0x200e0d) AM_WRITE(quiz365_protection_w ) // Protection
1604	1607	// AM_RANGE(0x201000, 0x2017ff) AM_WRITE(MWA16_RAM ) // ?
1605		AM_RANGE(0x300200, 0x300201) AM_WRITE(dynax_select2_16_w )
	1608	AM_RANGE(0x300200, 0x300201) AM_WRITE(ddenlovr_select2_16_w )
1606	1609	AM_RANGE(0x300202, 0x300203) AM_WRITE(quiz365_coincounter_w ) // Coin Counters + more stuff written on startup
1607		AM_RANGE(0x300240, 0x300247) AM_WRITE(ddenlovr_palette_base_w )
1608		AM_RANGE(0x300248, 0x30024f) AM_WRITE(ddenlovr_palette_mask_w )
1609		AM_RANGE(0x300250, 0x300257) AM_WRITE(ddenlovr_transparency_pen_w )
1610		AM_RANGE(0x300258, 0x30025f) AM_WRITE(ddenlovr_transparency_mask_w )
1611		AM_RANGE(0x300268, 0x300269) AM_WRITE(ddenlovr_bgcolor_w )
1612		AM_RANGE(0x30026a, 0x30026b) AM_WRITE(ddenlovr_priority_w )
1613		AM_RANGE(0x30026c, 0x30026d) AM_WRITE(ddenlovr_layer_enable_w )
	1610	AM_RANGE(0x300240, 0x300247) AM_WRITE(ddenlovr16_palette_base_w )
	1611	AM_RANGE(0x300248, 0x30024f) AM_WRITE(ddenlovr16_palette_mask_w )
	1612	AM_RANGE(0x300250, 0x300257) AM_WRITE(ddenlovr16_transparency_pen_w )
	1613	AM_RANGE(0x300258, 0x30025f) AM_WRITE(ddenlovr16_transparency_mask_w)
	1614	AM_RANGE(0x300268, 0x300269) AM_WRITE(ddenlovr16_bgcolor_w )
	1615	AM_RANGE(0x30026a, 0x30026b) AM_WRITE(ddenlovr16_priority_w )
	1616	AM_RANGE(0x30026c, 0x30026d) AM_WRITE(ddenlovr16_layer_enable_w )
1614	1617	AM_RANGE(0x300280, 0x300283) AM_WRITE(ddenlovr_blitter_w )
1615	1618	AM_RANGE(0x300300, 0x300301) AM_WRITE(YM2413_register_port_0_lsb_w )
1616	1619	AM_RANGE(0x300302, 0x300303) AM_WRITE(YM2413_data_port_0_lsb_w )
r1103	r1104
1648	1651
1649	1652	static READ16_HANDLER( ddenlvrj_blitter_r )
1650	1653	{
1651		return readinputport(2) \| (dynax_blitter_irq_flag ? 0x60 : 0x00 ); // bit 4 = 1 -> blitter busy
	1654	return readinputport(2) \| (ddenlovr_blitter_irq_flag ? 0x60 : 0x00 ); // bit 4 = 1 -> blitter busy
1652	1655	}
1653	1656
1654	1657	static ADDRESS_MAP_START( ddenlvrj_readmem, ADDRESS_SPACE_PROGRAM, 16 )
r1103	r1104
1668	1671	AM_RANGE(0x000000, 0x07ffff) AM_WRITE(MWA16_ROM ) // ROM
1669	1672	AM_RANGE(0x200000, 0x2003ff) AM_WRITE(ddenlovr_palette_w ) // Palette
1670	1673	// AM_RANGE(0x201000, 0x2017ff) AM_WRITE(MWA16_RAM ) // ? B0 on startup, then 00
1671		AM_RANGE(0x300040, 0x300047) AM_WRITE(ddenlovr_palette_base_w )
1672		AM_RANGE(0x300048, 0x30004f) AM_WRITE(ddenlovr_palette_mask_w )
1673		AM_RANGE(0x300050, 0x300057) AM_WRITE(ddenlovr_transparency_pen_w )
1674		AM_RANGE(0x300058, 0x30005f) AM_WRITE(ddenlovr_transparency_mask_w )
1675		AM_RANGE(0x300068, 0x300069) AM_WRITE(ddenlovr_bgcolor_w )
1676		AM_RANGE(0x30006a, 0x30006b) AM_WRITE(ddenlovr_priority_w )
1677		AM_RANGE(0x30006c, 0x30006d) AM_WRITE(ddenlovr_layer_enable_w )
	1674	AM_RANGE(0x300040, 0x300047) AM_WRITE(ddenlovr16_palette_base_w )
	1675	AM_RANGE(0x300048, 0x30004f) AM_WRITE(ddenlovr16_palette_mask_w )
	1676	AM_RANGE(0x300050, 0x300057) AM_WRITE(ddenlovr16_transparency_pen_w )
	1677	AM_RANGE(0x300058, 0x30005f) AM_WRITE(ddenlovr16_transparency_mask_w)
	1678	AM_RANGE(0x300068, 0x300069) AM_WRITE(ddenlovr16_bgcolor_w )
	1679	AM_RANGE(0x30006a, 0x30006b) AM_WRITE(ddenlovr16_priority_w )
	1680	AM_RANGE(0x30006c, 0x30006d) AM_WRITE(ddenlovr16_layer_enable_w )
1678	1681	AM_RANGE(0x300080, 0x300083) AM_WRITE(ddenlovr_blitter_w )
1679	1682	AM_RANGE(0x3000c0, 0x3000c1) AM_WRITE(YM2413_register_port_0_lsb_w )
1680	1683	AM_RANGE(0x3000c2, 0x3000c3) AM_WRITE(YM2413_data_port_0_lsb_w )
r1103	r1104
1709	1712	AM_RANGE(0x300000, 0x300001) AM_WRITE(ddenlovr_oki_bank_w )
1710	1713	AM_RANGE(0xd00000, 0xd003ff) AM_WRITE(ddenlovr_palette_w ) // Palette
1711	1714	// AM_RANGE(0xd01000, 0xd017ff) MWA16_RAM ) // ? B0 on startup, then 00
1712		AM_RANGE(0xe00040, 0xe00047) AM_WRITE(ddenlovr_palette_base_w )
1713		AM_RANGE(0xe00048, 0xe0004f) AM_WRITE(ddenlovr_palette_mask_w )
1714		AM_RANGE(0xe00050, 0xe00057) AM_WRITE(ddenlovr_transparency_pen_w )
1715		AM_RANGE(0xe00058, 0xe0005f) AM_WRITE(ddenlovr_transparency_mask_w )
1716		AM_RANGE(0xe00068, 0xe00069) AM_WRITE(ddenlovr_bgcolor_w )
1717		AM_RANGE(0xe0006a, 0xe0006b) AM_WRITE(ddenlovr_priority_w )
1718		AM_RANGE(0xe0006c, 0xe0006d) AM_WRITE(ddenlovr_layer_enable_w )
	1715	AM_RANGE(0xe00040, 0xe00047) AM_WRITE(ddenlovr16_palette_base_w )
	1716	AM_RANGE(0xe00048, 0xe0004f) AM_WRITE(ddenlovr16_palette_mask_w )
	1717	AM_RANGE(0xe00050, 0xe00057) AM_WRITE(ddenlovr16_transparency_pen_w )
	1718	AM_RANGE(0xe00058, 0xe0005f) AM_WRITE(ddenlovr16_transparency_mask_w)
	1719	AM_RANGE(0xe00068, 0xe00069) AM_WRITE(ddenlovr16_bgcolor_w )
	1720	AM_RANGE(0xe0006a, 0xe0006b) AM_WRITE(ddenlovr16_priority_w )
	1721	AM_RANGE(0xe0006c, 0xe0006d) AM_WRITE(ddenlovr16_layer_enable_w )
1719	1722	AM_RANGE(0xe00080, 0xe00083) AM_WRITE(ddenlovr_blitter_w )
1720	1723	AM_RANGE(0xe00302, 0xe00303) AM_WRITE(ddenlovr_blitter_irq_ack_w ) // Blitter irq acknowledge
1721	1724	AM_RANGE(0xe00308, 0xe00309) AM_WRITE(ddenlovr_coincounter_0_w ) // Coin Counters
r1103	r1104
1733	1736
1734	1737	static READ16_HANDLER( nettoqc_special_r )
1735	1738	{
1736		return readinputport(2) \| (dynax_blitter_irq_flag ? 0x60 : 0x00 );
	1739	return readinputport(2) \| (ddenlovr_blitter_irq_flag ? 0x60 : 0x00 );
1737	1740	}
1738	1741
1739	1742	static READ16_HANDLER( nettoqc_input_r )
1740	1743	{
1741		if (!(dynax_select & 0x01)) return readinputport(3);
1742		if (!(dynax_select & 0x02)) return readinputport(4);
1743		if (!(dynax_select & 0x04)) return readinputport(5);
	1744	if (!(ddenlovr_select & 0x01)) return readinputport(3);
	1745	if (!(ddenlovr_select & 0x02)) return readinputport(4);
	1746	if (!(ddenlovr_select & 0x04)) return readinputport(5);
1744	1747	return 0xffff;
1745	1748	}
1746	1749
r1103	r1104
1797	1800	AM_RANGE(0x200000, 0x2003ff) AM_WRITE(ddenlovr_palette_w ) // Palette
1798	1801	AM_RANGE(0x200e0a, 0x200e0d) AM_WRITE(MWA16_RAM) AM_BASE(&nettoqc_protection_val ) //
1799	1802	AM_RANGE(0x201000, 0x2017ff) AM_WRITE(MWA16_RAM ) // ?
1800		AM_RANGE(0x300040, 0x300047) AM_WRITE(ddenlovr_palette_base_w )
1801		AM_RANGE(0x300048, 0x30004f) AM_WRITE(ddenlovr_palette_mask_w )
1802		AM_RANGE(0x300050, 0x300057) AM_WRITE(ddenlovr_transparency_pen_w )
1803		AM_RANGE(0x300058, 0x30005f) AM_WRITE(ddenlovr_transparency_mask_w )
1804		AM_RANGE(0x300068, 0x300069) AM_WRITE(ddenlovr_bgcolor_w )
1805		AM_RANGE(0x30006a, 0x30006b) AM_WRITE(ddenlovr_priority_w )
1806		AM_RANGE(0x30006c, 0x30006d) AM_WRITE(ddenlovr_layer_enable_w )
	1803	AM_RANGE(0x300040, 0x300047) AM_WRITE(ddenlovr16_palette_base_w )
	1804	AM_RANGE(0x300048, 0x30004f) AM_WRITE(ddenlovr16_palette_mask_w )
	1805	AM_RANGE(0x300050, 0x300057) AM_WRITE(ddenlovr16_transparency_pen_w )
	1806	AM_RANGE(0x300058, 0x30005f) AM_WRITE(ddenlovr16_transparency_mask_w)
	1807	AM_RANGE(0x300068, 0x300069) AM_WRITE(ddenlovr16_bgcolor_w )
	1808	AM_RANGE(0x30006a, 0x30006b) AM_WRITE(ddenlovr16_priority_w )
	1809	AM_RANGE(0x30006c, 0x30006d) AM_WRITE(ddenlovr16_layer_enable_w )
1807	1810	AM_RANGE(0x300080, 0x300083) AM_WRITE(ddenlovr_blitter_w )
1808	1811	AM_RANGE(0x3000c0, 0x3000c1) AM_WRITE(YM2413_register_port_0_lsb_w )
1809	1812	AM_RANGE(0x3000c2, 0x3000c3) AM_WRITE(YM2413_data_port_0_lsb_w )
r1103	r1104
1811	1814	AM_RANGE(0x300140, 0x300141) AM_WRITE(AY8910_control_port_0_lsb_w )
1812	1815	AM_RANGE(0x300142, 0x300143) AM_WRITE(AY8910_write_port_0_lsb_w )
1813	1816	AM_RANGE(0x300188, 0x300189) AM_WRITE(nettoqc_coincounter_w ) // Coin Counters
1814		AM_RANGE(0x30018a, 0x30018b) AM_WRITE(dynax_select_16_w ) //
	1817	AM_RANGE(0x30018a, 0x30018b) AM_WRITE(ddenlovr_select_16_w ) //
1815	1818	AM_RANGE(0x30018c, 0x30018d) AM_WRITE(nettoqc_oki_bank_w )
1816	1819	AM_RANGE(0x3001ca, 0x3001cb) AM_WRITE(ddenlovr_blitter_irq_ack_w ) // Blitter irq acknowledge
1817	1820	AM_RANGE(0x300240, 0x300241) AM_WRITE(OKIM6295_data_0_lsb_w )
r1103	r1104
1825	1828
1826	1829	READ8_HANDLER( rongrong_input_r )
1827	1830	{
1828		if (!(dynax_select & 0x01)) return readinputport(3);
1829		if (!(dynax_select & 0x02)) return readinputport(4);
1830		if (!(dynax_select & 0x04)) return 0xff;//mame_rand(Machine);
1831		if (!(dynax_select & 0x08)) return 0xff;//mame_rand(Machine);
1832		if (!(dynax_select & 0x10)) return readinputport(5);
	1831	if (!(ddenlovr_select & 0x01)) return readinputport(3);
	1832	if (!(ddenlovr_select & 0x02)) return readinputport(4);
	1833	if (!(ddenlovr_select & 0x04)) return 0xff;//mame_rand(Machine);
	1834	if (!(ddenlovr_select & 0x08)) return 0xff;//mame_rand(Machine);
	1835	if (!(ddenlovr_select & 0x10)) return readinputport(5);
1833	1836	return 0xff;
1834	1837	}
1835	1838
r1103	r1104
1840	1843	//logerror("%04x: rongrong_select_w %02x\n",activecpu_get_pc(),data);
1841	1844	/* bits 0-4 = both ROM bank AND input select */
1842	1845	memory_set_bankptr(1, &rom[0x10000 + 0x8000 * (data & 0x1f)]);
1843		dynax_select = data;
	1846	ddenlovr_select = data;
1844	1847
1845	1848	/* bits 5-7 = RAM bank */
1846	1849	memory_set_bankptr(2, &rom[0x110000 + 0x1000 * ((data & 0xe0) >> 5)]);
r1103	r1104
1875	1878	AM_RANGE(0x00, 0x01) AM_WRITE(rongrong_blitter_w )
1876	1879	AM_RANGE(0x1b, 0x1b) AM_WRITE(rongrong_blitter_busy_w )
1877	1880	AM_RANGE(0x1e, 0x1e) AM_WRITE(rongrong_select_w )
1878		AM_RANGE(0x20, 0x20) AM_WRITE(dynax_select2_w )
	1881	AM_RANGE(0x20, 0x20) AM_WRITE(ddenlovr_select2_w )
1879	1882	AM_RANGE(0x40, 0x40) AM_WRITE(OKIM6295_data_0_w )
1880	1883	AM_RANGE(0x60, 0x60) AM_WRITE(YM2413_register_port_0_w )
1881	1884	AM_RANGE(0x61, 0x61) AM_WRITE(YM2413_data_port_0_w )
1882		AM_RANGE(0x80, 0x83) AM_WRITE(dynax_palette_base_w )
1883		AM_RANGE(0x84, 0x87) AM_WRITE(dynax_palette_mask_w )
1884		AM_RANGE(0x88, 0x8b) AM_WRITE(dynax_transparency_pen_w )
1885		AM_RANGE(0x8c, 0x8f) AM_WRITE(dynax_transparency_mask_w )
1886		AM_RANGE(0x94, 0x94) AM_WRITE(dynax_bgcolor_w )
1887		AM_RANGE(0x95, 0x95) AM_WRITE(dynax_priority_w )
1888		AM_RANGE(0x96, 0x96) AM_WRITE(dynax_layer_enable_w )
	1885	AM_RANGE(0x80, 0x83) AM_WRITE(ddenlovr_palette_base_w )
	1886	AM_RANGE(0x84, 0x87) AM_WRITE(ddenlovr_palette_mask_w )
	1887	AM_RANGE(0x88, 0x8b) AM_WRITE(ddenlovr_transparency_pen_w )
	1888	AM_RANGE(0x8c, 0x8f) AM_WRITE(ddenlovr_transparency_mask_w )
	1889	AM_RANGE(0x94, 0x94) AM_WRITE(ddenlovr_bgcolor_w )
	1890	AM_RANGE(0x95, 0x95) AM_WRITE(ddenlovr_priority_w )
	1891	AM_RANGE(0x96, 0x96) AM_WRITE(ddenlovr_layer_enable_w )
1889	1892	AM_RANGE(0xa0, 0xaf) AM_WRITE(msm6242_w ) // 6242RTC
1890	1893	AM_RANGE(0xc0, 0xc0) AM_WRITE(quizchq_oki_bank_w )
1891	1894	AM_RANGE(0xc2, 0xc2) AM_WRITE(MWA8_NOP ) // enables palette RAM at 8000
r1103	r1104
1924	1927	AM_RANGE(0x40, 0x40) AM_WRITE(OKIM6295_data_0_w )
1925	1928	AM_RANGE(0x60, 0x60) AM_WRITE(YM2413_register_port_0_w )
1926	1929	AM_RANGE(0x61, 0x61) AM_WRITE(YM2413_data_port_0_w )
1927		AM_RANGE(0x80, 0x83) AM_WRITE(dynax_palette_base_w )
1928		AM_RANGE(0x84, 0x87) AM_WRITE(dynax_palette_mask_w )
1929		AM_RANGE(0x88, 0x8b) AM_WRITE(dynax_transparency_pen_w )
1930		AM_RANGE(0x8c, 0x8f) AM_WRITE(dynax_transparency_mask_w )
1931		AM_RANGE(0x94, 0x94) AM_WRITE(dynax_bgcolor_w )
1932		AM_RANGE(0x95, 0x95) AM_WRITE(dynax_priority_w )
1933		AM_RANGE(0x96, 0x96) AM_WRITE(dynax_layer_enable_w )
1934		AM_RANGE(0xa0, 0xa0) AM_WRITE(dynax_select2_w )
	1930	AM_RANGE(0x80, 0x83) AM_WRITE(ddenlovr_palette_base_w )
	1931	AM_RANGE(0x84, 0x87) AM_WRITE(ddenlovr_palette_mask_w )
	1932	AM_RANGE(0x88, 0x8b) AM_WRITE(ddenlovr_transparency_pen_w )
	1933	AM_RANGE(0x8c, 0x8f) AM_WRITE(ddenlovr_transparency_mask_w )
	1934	AM_RANGE(0x94, 0x94) AM_WRITE(ddenlovr_bgcolor_w )
	1935	AM_RANGE(0x95, 0x95) AM_WRITE(ddenlovr_priority_w )
	1936	AM_RANGE(0x96, 0x96) AM_WRITE(ddenlovr_layer_enable_w )
	1937	AM_RANGE(0xa0, 0xa0) AM_WRITE(ddenlovr_select2_w )
1935	1938	AM_RANGE(0xc2, 0xc2) AM_WRITE(MWA8_NOP ) // enables palette RAM at f000, and protection device at f705/f706/f601
1936	1939	ADDRESS_MAP_END
1937	1940	/*
r1103	r1104
1998	2001
1999	2002	static WRITE8_HANDLER( mmpanic_lockout_w )
2000	2003	{
2001		if (dynax_select == 0x0c)
	2004	if (ddenlovr_select == 0x0c)
2002	2005	{
2003	2006	coin_counter_w(0,(~data) & 0x01);
2004	2007	coin_lockout_w(0,(~data) & 0x02);
r1103	r1104
2041	2044	static ADDRESS_MAP_START( mmpanic_writeport, ADDRESS_SPACE_IO, 8 ) ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
2042	2045	AM_RANGE(0x00, 0x0f) AM_WRITE(msm6242_w ) // 6242RTC
2043	2046	// Layers 0-3:
2044		AM_RANGE(0x20, 0x23) AM_WRITE(dynax_palette_base_w )
2045		AM_RANGE(0x24, 0x27) AM_WRITE(dynax_palette_mask_w )
2046		AM_RANGE(0x28, 0x2b) AM_WRITE(dynax_transparency_pen_w )
2047		AM_RANGE(0x2c, 0x2f) AM_WRITE(dynax_transparency_mask_w )
2048		AM_RANGE(0x34, 0x34) AM_WRITE(dynax_bgcolor_w )
2049		AM_RANGE(0x35, 0x35) AM_WRITE(dynax_priority_w )
2050		AM_RANGE(0x36, 0x36) AM_WRITE(dynax_layer_enable_w )
	2047	AM_RANGE(0x20, 0x23) AM_WRITE(ddenlovr_palette_base_w )
	2048	AM_RANGE(0x24, 0x27) AM_WRITE(ddenlovr_palette_mask_w )
	2049	AM_RANGE(0x28, 0x2b) AM_WRITE(ddenlovr_transparency_pen_w )
	2050	AM_RANGE(0x2c, 0x2f) AM_WRITE(ddenlovr_transparency_mask_w )
	2051	AM_RANGE(0x34, 0x34) AM_WRITE(ddenlovr_bgcolor_w )
	2052	AM_RANGE(0x35, 0x35) AM_WRITE(ddenlovr_priority_w )
	2053	AM_RANGE(0x36, 0x36) AM_WRITE(ddenlovr_layer_enable_w )
2051	2054	// Layers 4-7:
2052		AM_RANGE(0x40, 0x43) AM_WRITE(dynax_palette_base2_w )
2053		AM_RANGE(0x44, 0x47) AM_WRITE(dynax_palette_mask2_w )
2054		AM_RANGE(0x48, 0x4b) AM_WRITE(dynax_transparency_pen2_w )
2055		AM_RANGE(0x4c, 0x4f) AM_WRITE(dynax_transparency_mask2_w)
2056		AM_RANGE(0x54, 0x54) AM_WRITE(dynax_bgcolor2_w )
2057		AM_RANGE(0x55, 0x55) AM_WRITE(dynax_priority2_w )
2058		AM_RANGE(0x56, 0x56) AM_WRITE(dynax_layer_enable2_w )
	2055	AM_RANGE(0x40, 0x43) AM_WRITE(ddenlovr_palette_base2_w )
	2056	AM_RANGE(0x44, 0x47) AM_WRITE(ddenlovr_palette_mask2_w )
	2057	AM_RANGE(0x48, 0x4b) AM_WRITE(ddenlovr_transparency_pen2_w )
	2058	AM_RANGE(0x4c, 0x4f) AM_WRITE(ddenlovr_transparency_mask2_w)
	2059	AM_RANGE(0x54, 0x54) AM_WRITE(ddenlovr_bgcolor2_w )
	2060	AM_RANGE(0x55, 0x55) AM_WRITE(ddenlovr_priority2_w )
	2061	AM_RANGE(0x56, 0x56) AM_WRITE(ddenlovr_layer_enable2_w )
2059	2062
2060	2063	AM_RANGE(0x60, 0x61) AM_WRITE(mmpanic_blitter_w )
2061	2064	AM_RANGE(0x64, 0x65) AM_WRITE(mmpanic_blitter2_w )
2062		AM_RANGE(0x68, 0x68) AM_WRITE(dynax_select_w )
	2065	AM_RANGE(0x68, 0x68) AM_WRITE(ddenlovr_select_w )
2063	2066	AM_RANGE(0x69, 0x69) AM_WRITE(mmpanic_lockout_w )
2064	2067	AM_RANGE(0x74, 0x74) AM_WRITE(mmpanic_rombank_w )
2065	2068
r1103	r1104
2137	2140	{
2138	2141	UINT8 *rom = memory_region(REGION_CPU1);
2139	2142
2140		dynax_select = data;
	2143	ddenlovr_select = data;
2141	2144
2142	2145	memory_set_bankptr(1, &rom[0x10000 + 0x8000 * (data & 0x0f)]);
2143	2146	// bit 4 selects palette ram at 8000?
r1103	r1104
2146	2149
2147	2150	READ8_HANDLER( funkyfig_dsw_r )
2148	2151	{
2149		if (!(dynax_select & 0x01)) return readinputport(3);
2150		if (!(dynax_select & 0x02)) return readinputport(4);
2151		if (!(dynax_select & 0x04)) return readinputport(5);
2152		logerror("%06x: warning, unknown bits read, dynax_select = %02x\n", activecpu_get_pc(), dynax_select);
	2152	if (!(ddenlovr_select & 0x01)) return readinputport(3);
	2153	if (!(ddenlovr_select & 0x02)) return readinputport(4);
	2154	if (!(ddenlovr_select & 0x04)) return readinputport(5);
	2155	logerror("%06x: warning, unknown bits read, ddenlovr_select = %02x\n", activecpu_get_pc(), ddenlovr_select);
2153	2156	return 0xff;
2154	2157	}
2155	2158
r1103	r1104
2157	2160
2158	2161	READ8_HANDLER( funkyfig_coin_r )
2159	2162	{
2160		switch( dynax_select2 )
	2163	switch( ddenlovr_select2 )
2161	2164	{
2162	2165	case 0x22: return readinputport(2);
2163	2166	case 0x23: return funkyfig_lockout;
2164	2167	}
2165		logerror("%06x: warning, unknown bits read, dynax_select2 = %02x\n", activecpu_get_pc(), dynax_select2);
	2168	logerror("%06x: warning, unknown bits read, ddenlovr_select2 = %02x\n", activecpu_get_pc(), ddenlovr_select2);
2166	2169	return 0xff;
2167	2170	}
2168	2171
2169	2172	READ8_HANDLER( funkyfig_key_r )
2170	2173	{
2171		switch( dynax_select2 )
	2174	switch( ddenlovr_select2 )
2172	2175	{
2173	2176	case 0x20: return readinputport(0);
2174	2177	case 0x21: return readinputport(1);
2175	2178	}
2176		logerror("%06x: warning, unknown bits read, dynax_select2 = %02x\n", activecpu_get_pc(), dynax_select2);
	2179	logerror("%06x: warning, unknown bits read, ddenlovr_select2 = %02x\n", activecpu_get_pc(), ddenlovr_select2);
2177	2180	return 0xff;
2178	2181	}
2179	2182
2180	2183	static WRITE8_HANDLER( funkyfig_lockout_w )
2181	2184	{
2182		switch( dynax_select2 )
	2185	switch( ddenlovr_select2 )
2183	2186	{
2184	2187	case 0x2c:
2185	2188	funkyfig_lockout = data;
r1103	r1104
2192	2195	// case 0xef: 16 bytes on startup
2193	2196
2194	2197	default:
2195		logerror("%06x: warning, unknown bits written, dynax_select2 = %02x, data = %02x\n", activecpu_get_pc(), dynax_select2, data);
	2198	logerror("%06x: warning, unknown bits written, ddenlovr_select2 = %02x, data = %02x\n", activecpu_get_pc(), ddenlovr_select2, data);
2196	2199	}
2197	2200	}
2198	2201
r1103	r1104
2217	2220	AM_RANGE(0x40, 0x4f) AM_WRITE( msm6242_w ) // 6242RTC
2218	2221
2219	2222	// Layers 0-3:
2220		AM_RANGE(0x60, 0x63) AM_WRITE( dynax_palette_base_w )
2221		AM_RANGE(0x64, 0x67) AM_WRITE( dynax_palette_mask_w )
2222		AM_RANGE(0x68, 0x6b) AM_WRITE( dynax_transparency_pen_w )
2223		AM_RANGE(0x6c, 0x6f) AM_WRITE( dynax_transparency_mask_w)
2224		AM_RANGE(0x74, 0x74) AM_WRITE( dynax_bgcolor_w )
2225		AM_RANGE(0x75, 0x75) AM_WRITE( dynax_priority_w )
2226		AM_RANGE(0x76, 0x76) AM_WRITE( dynax_layer_enable_w )
	2223	AM_RANGE(0x60, 0x63) AM_WRITE( ddenlovr_palette_base_w )
	2224	AM_RANGE(0x64, 0x67) AM_WRITE( ddenlovr_palette_mask_w )
	2225	AM_RANGE(0x68, 0x6b) AM_WRITE( ddenlovr_transparency_pen_w )
	2226	AM_RANGE(0x6c, 0x6f) AM_WRITE( ddenlovr_transparency_mask_w)
	2227	AM_RANGE(0x74, 0x74) AM_WRITE( ddenlovr_bgcolor_w )
	2228	AM_RANGE(0x75, 0x75) AM_WRITE( ddenlovr_priority_w )
	2229	AM_RANGE(0x76, 0x76) AM_WRITE( ddenlovr_layer_enable_w )
2227	2230
2228		AM_RANGE(0x80, 0x80) AM_WRITE( dynax_select2_w )
	2231	AM_RANGE(0x80, 0x80) AM_WRITE( ddenlovr_select2_w )
2229	2232	AM_RANGE(0x81, 0x81) AM_WRITE( funkyfig_lockout_w )
2230	2233	AM_RANGE(0xa2, 0xa2) AM_WRITE( mmpanic_leds2_w )
2231	2234	ADDRESS_MAP_END
r1103	r1104
2310	2313	{
2311	2314	UINT8 *rom = memory_region( REGION_GFX1 );
2312	2315	size_t size = memory_region_length( REGION_GFX1 );
2313		int address = (dynax_blit_address & 0xffffff) * 2;
	2316	int address = (ddenlovr_blit_address & 0xffffff) * 2;
2314	2317
2315	2318	static UINT8 romdata[2];
2316	2319
r1103	r1104
2325	2328	romdata[0] = rom[address + 0];
2326	2329	romdata[1] = rom[address + 1];
2327	2330
2328		dynax_blit_address = (dynax_blit_address + 1) & 0xffffff;
	2331	ddenlovr_blit_address = (ddenlovr_blit_address + 1) & 0xffffff;
2329	2332
2330	2333	return romdata[0];
2331	2334	}
r1103	r1104
2357	2360	{
2358	2361	static int palette_index;
2359	2362
2360		if (dynax_blit_reg & 0x80)
	2363	if (ddenlovr_blit_reg & 0x80)
2361	2364	{
2362		palette_index = data \| ((dynax_blit_reg & 1) << 8);
	2365	palette_index = data \| ((ddenlovr_blit_reg & 1) << 8);
2363	2366	}
2364	2367	else
2365	2368	{
2366	2369	// 0bbggggg bbbrrrrr
2367	2370	// 04343210 21043210
2368	2371
2369		int g = dynax_blit_reg & 0x1f;
	2372	int g = ddenlovr_blit_reg & 0x1f;
2370	2373	int r = data & 0x1f;
2371		int b = ((data & 0xe0) >> 5) \| ((dynax_blit_reg & 0x60) >> 2);
	2374	int b = ((data & 0xe0) >> 5) \| ((ddenlovr_blit_reg & 0x60) >> 2);
2372	2375	palette_set_color_rgb(Machine,(palette_index++)&0x1ff,pal5bit(r),pal5bit(g),pal5bit(b));
2373	2376	}
2374	2377	}
r1103	r1104
2509	2512	{
2510	2513	UINT8 *rom = memory_region( REGION_GFX1 );
2511	2514	size_t size = memory_region_length( REGION_GFX1 );
2512		int address = (dynax_blit_address & 0xffffff) * 2;
	2515	int address = (ddenlovr_blit_address & 0xffffff) * 2;
2513	2516
2514	2517	if (address >= size)
2515	2518	{
r1103	r1104
2524	2527	static READ8_HANDLER( mjchuuka_gfxrom_0_r )
2525	2528	{
2526	2529	mjchuuka_get_romdata();
2527		dynax_blit_address++;
	2530	ddenlovr_blit_address++;
2528	2531	return mjchuuka_romdata[0];
2529	2532	}
2530	2533	static READ8_HANDLER( mjchuuka_gfxrom_1_r )
r1103	r1104
2639	2642
2640	2643	static WRITE8_HANDLER( mjmyster_select2_w )
2641	2644	{
2642		dynax_select2 = data;
	2645	ddenlovr_select2 = data;
2643	2646
2644	2647	if (data & 0x80) keyb = 1;
2645	2648	}
2646	2649
2647	2650	static READ8_HANDLER( mjmyster_coins_r )
2648	2651	{
2649		switch( dynax_select2 )
	2652	switch( ddenlovr_select2 )
2650	2653	{
2651	2654	case 0x00: return readinputport(0);
2652	2655	case 0x01: return 0xff;
r1103	r1104
2654	2657	case 0x03: return 0xff;
2655	2658	}
2656	2659
2657		logerror("%06x: warning, unknown bits read, dynax_select2 = %02x\n", activecpu_get_pc(), dynax_select2);
	2660	logerror("%06x: warning, unknown bits read, ddenlovr_select2 = %02x\n", activecpu_get_pc(), ddenlovr_select2);
2658	2661
2659	2662	return 0xff;
2660	2663	}
r1103	r1104
2677	2680
2678	2681	static READ8_HANDLER( mjmyster_dsw_r )
2679	2682	{
2680		if (!(dynax_select & 0x01)) return readinputport(9);
2681		if (!(dynax_select & 0x02)) return readinputport(8);
2682		if (!(dynax_select & 0x04)) return readinputport(7);
2683		if (!(dynax_select & 0x08)) return readinputport(6);
2684		if (!(dynax_select & 0x10)) return readinputport(10);
2685		logerror("%06x: warning, unknown bits read, dynax_select = %02x\n", activecpu_get_pc(), dynax_select);
	2683	if (!(ddenlovr_select & 0x01)) return readinputport(9);
	2684	if (!(ddenlovr_select & 0x02)) return readinputport(8);
	2685	if (!(ddenlovr_select & 0x04)) return readinputport(7);
	2686	if (!(ddenlovr_select & 0x08)) return readinputport(6);
	2687	if (!(ddenlovr_select & 0x10)) return readinputport(10);
	2688	logerror("%06x: warning, unknown bits read, ddenlovr_select = %02x\n", activecpu_get_pc(), ddenlovr_select);
2686	2689	return 0xff;
2687	2690	}
2688	2691
2689	2692	static WRITE8_HANDLER( mjmyster_coincounter_w )
2690	2693	{
2691		switch( dynax_select2 )
	2694	switch( ddenlovr_select2 )
2692	2695	{
2693	2696	case 0x0c:
2694	2697	coin_counter_w(0, (~data) & 0x01); // coin in
r1103	r1104
2700	2703	break;
2701	2704
2702	2705	default:
2703		logerror("%06x: warning, unknown bits written, dynax_select2 = %02x, data = %02x\n", activecpu_get_pc(), dynax_select2, data);
	2706	logerror("%06x: warning, unknown bits written, ddenlovr_select2 = %02x, data = %02x\n", activecpu_get_pc(), ddenlovr_select2, data);
2704	2707	}
2705	2708	}
2706	2709
r1103	r1104
2733	2736	AM_RANGE(0x46, 0x46) AM_WRITE( AY8910_write_port_0_w )
2734	2737	AM_RANGE(0x48, 0x48) AM_WRITE( AY8910_control_port_0_w )
2735	2738	AM_RANGE(0x60, 0x6f) AM_WRITE( msm6242_w ) // 6242RTC
2736		AM_RANGE(0x80, 0x83) AM_WRITE( dynax_palette_base_w )
2737		AM_RANGE(0x84, 0x87) AM_WRITE( dynax_palette_mask_w )
2738		AM_RANGE(0x88, 0x8b) AM_WRITE( dynax_transparency_pen_w )
2739		AM_RANGE(0x8c, 0x8f) AM_WRITE( dynax_transparency_mask_w)
2740		AM_RANGE(0x94, 0x94) AM_WRITE( dynax_bgcolor_w )
2741		AM_RANGE(0x95, 0x95) AM_WRITE( dynax_priority_w )
2742		AM_RANGE(0x96, 0x96) AM_WRITE( dynax_layer_enable_w )
	2739	AM_RANGE(0x80, 0x83) AM_WRITE( ddenlovr_palette_base_w )
	2740	AM_RANGE(0x84, 0x87) AM_WRITE( ddenlovr_palette_mask_w )
	2741	AM_RANGE(0x88, 0x8b) AM_WRITE( ddenlovr_transparency_pen_w )
	2742	AM_RANGE(0x8c, 0x8f) AM_WRITE( ddenlovr_transparency_mask_w)
	2743	AM_RANGE(0x94, 0x94) AM_WRITE( ddenlovr_bgcolor_w )
	2744	AM_RANGE(0x95, 0x95) AM_WRITE( ddenlovr_priority_w )
	2745	AM_RANGE(0x96, 0x96) AM_WRITE( ddenlovr_layer_enable_w )
2743	2746	ADDRESS_MAP_END
2744	2747
2745	2748	/***************************************************************************
r1103	r1104
2780	2783
2781	2784	static READ8_HANDLER( hginga_dsw_r )
2782	2785	{
2783		if (!(dynax_select & 0x01)) return readinputport(11);
2784		if (!(dynax_select & 0x02)) return readinputport(12);
2785		if (!(dynax_select & 0x04)) return readinputport(13);
2786		if (!(dynax_select & 0x08)) return readinputport(14);
2787		if (!(dynax_select & 0x10)) return readinputport(15);
2788		logerror("%06x: warning, unknown bits read, dynax_select = %02x\n", activecpu_get_pc(), dynax_select);
	2786	if (!(ddenlovr_select & 0x01)) return readinputport(11);
	2787	if (!(ddenlovr_select & 0x02)) return readinputport(12);
	2788	if (!(ddenlovr_select & 0x04)) return readinputport(13);
	2789	if (!(ddenlovr_select & 0x08)) return readinputport(14);
	2790	if (!(ddenlovr_select & 0x10)) return readinputport(15);
	2791	logerror("%06x: warning, unknown bits read, ddenlovr_select = %02x\n", activecpu_get_pc(), ddenlovr_select);
2789	2792	return 0xff;
2790	2793	}
2791	2794
r1103	r1104
2861	2864	{
2862	2865	if (offset == 0)
2863	2866	{
2864		dynax_blit_reg = data;
	2867	ddenlovr_blit_reg = data;
2865	2868	}
2866	2869	else
2867	2870	{
2868		switch (dynax_blit_reg & 0x3f)
	2871	switch (ddenlovr_blit_reg & 0x3f)
2869	2872	{
2870	2873	case 0x00:
2871	2874	switch (data & 0xf)
r1103	r1104
2909	2912	AM_RANGE(0x41, 0x41) AM_WRITE( hginga_coins_w )
2910	2913	AM_RANGE(0x60, 0x6f) AM_WRITE( msm6242_w ) // 6242RTC
2911	2914	AM_RANGE(0x80, 0x80) AM_WRITE( hginga_80_w )
2912		AM_RANGE(0xa0, 0xa3) AM_WRITE( dynax_palette_base_w )
2913		AM_RANGE(0xa4, 0xa7) AM_WRITE( dynax_palette_mask_w )
2914		AM_RANGE(0xa8, 0xab) AM_WRITE( dynax_transparency_pen_w )
2915		AM_RANGE(0xac, 0xaf) AM_WRITE( dynax_transparency_mask_w)
2916		AM_RANGE(0xb4, 0xb4) AM_WRITE( dynax_bgcolor_w )
2917		AM_RANGE(0xb5, 0xb5) AM_WRITE( dynax_priority_w )
2918		AM_RANGE(0xb6, 0xb6) AM_WRITE( dynax_layer_enable_w )
	2915	AM_RANGE(0xa0, 0xa3) AM_WRITE( ddenlovr_palette_base_w )
	2916	AM_RANGE(0xa4, 0xa7) AM_WRITE( ddenlovr_palette_mask_w )
	2917	AM_RANGE(0xa8, 0xab) AM_WRITE( ddenlovr_transparency_pen_w )
	2918	AM_RANGE(0xac, 0xaf) AM_WRITE( ddenlovr_transparency_mask_w)
	2919	AM_RANGE(0xb4, 0xb4) AM_WRITE( ddenlovr_bgcolor_w )
	2920	AM_RANGE(0xb5, 0xb5) AM_WRITE( ddenlovr_priority_w )
	2921	AM_RANGE(0xb6, 0xb6) AM_WRITE( ddenlovr_layer_enable_w )
2919	2922	ADDRESS_MAP_END
2920	2923
2921	2924
r1103	r1104
2929	2932	{
2930	2933	UINT8 hopper_bit = ((hgokou_hopper && !(cpu_getcurrentframe()%10)) ? 0 : (1<<6));
2931	2934
2932		if (!(dynax_select2 & 0x01)) return readinputport(player * 5 + 1) \| hopper_bit;
2933		if (!(dynax_select2 & 0x02)) return readinputport(player * 5 + 2) \| hopper_bit;
2934		if (!(dynax_select2 & 0x04)) return readinputport(player * 5 + 3) \| hopper_bit;
2935		if (!(dynax_select2 & 0x08)) return readinputport(player * 5 + 4) \| hopper_bit;
2936		if (!(dynax_select2 & 0x10)) return readinputport(player * 5 + 5) \| hopper_bit;
	2935	if (!(ddenlovr_select2 & 0x01)) return readinputport(player * 5 + 1) \| hopper_bit;
	2936	if (!(ddenlovr_select2 & 0x02)) return readinputport(player * 5 + 2) \| hopper_bit;
	2937	if (!(ddenlovr_select2 & 0x04)) return readinputport(player * 5 + 3) \| hopper_bit;
	2938	if (!(ddenlovr_select2 & 0x08)) return readinputport(player * 5 + 4) \| hopper_bit;
	2939	if (!(ddenlovr_select2 & 0x10)) return readinputport(player * 5 + 5) \| hopper_bit;
2937	2940
2938	2941	return 0x7f; // bit 7 = blitter busy, bit 6 = hopper
2939	2942	}
r1103	r1104
2967	2970	hginga_coins = data;
2968	2971	break;
2969	2972
2970		case 0x2d: dynax_select2 = data; break;
	2973	case 0x2d: ddenlovr_select2 = data; break;
2971	2974
2972	2975	case 0x2f: break; // ? written with 2f
2973	2976
r1103	r1104
3015	3018	AM_RANGE(0x1c, 0x1c) AM_WRITE(mjmyster_rambank_w )
3016	3019	AM_RANGE(0x1e, 0x1e) AM_WRITE(hginga_rombank_w )
3017	3020	AM_RANGE(0x20, 0x2f) AM_WRITE(msm6242_w ) // 6242RTC
3018		AM_RANGE(0x40, 0x43) AM_WRITE(dynax_palette_base_w )
3019		AM_RANGE(0x44, 0x47) AM_WRITE(dynax_palette_mask_w )
3020		AM_RANGE(0x48, 0x4b) AM_WRITE(dynax_transparency_pen_w )
3021		AM_RANGE(0x4c, 0x4f) AM_WRITE(dynax_transparency_mask_w )
3022		AM_RANGE(0x54, 0x54) AM_WRITE(dynax_bgcolor_w )
3023		AM_RANGE(0x55, 0x55) AM_WRITE(dynax_priority_w )
3024		AM_RANGE(0x56, 0x56) AM_WRITE(dynax_layer_enable_w )
	3021	AM_RANGE(0x40, 0x43) AM_WRITE(ddenlovr_palette_base_w )
	3022	AM_RANGE(0x44, 0x47) AM_WRITE(ddenlovr_palette_mask_w )
	3023	AM_RANGE(0x48, 0x4b) AM_WRITE(ddenlovr_transparency_pen_w )
	3024	AM_RANGE(0x4c, 0x4f) AM_WRITE(ddenlovr_transparency_mask_w )
	3025	AM_RANGE(0x54, 0x54) AM_WRITE(ddenlovr_bgcolor_w )
	3026	AM_RANGE(0x55, 0x55) AM_WRITE(ddenlovr_priority_w )
	3027	AM_RANGE(0x56, 0x56) AM_WRITE(ddenlovr_layer_enable_w )
3025	3028	AM_RANGE(0x60, 0x60) AM_WRITE(hginga_input_w )
3026	3029	AM_RANGE(0x61, 0x61) AM_WRITE(hgokou_input_w )
3027	3030	AM_RANGE(0x80, 0x80) AM_WRITE(OKIM6295_data_0_w )
r1103	r1104
3040	3043	{
3041	3044	UINT8 *rom = memory_region(REGION_CPU1);
3042	3045
3043		dynax_select = data;
	3046	ddenlovr_select = data;
3044	3047	hginga_ip = 0;
3045	3048
3046	3049	memory_set_bankptr(1, &rom[0x10000 + 0x8000 * (data & 0x07)]);
r1103	r1104
3065	3068
3066	3069	static READ8_HANDLER( hparadis_dsw_r )
3067	3070	{
3068		if (!(dynax_select & 0x01)) return readinputport(13);
3069		if (!(dynax_select & 0x02)) return readinputport(14);
3070		if (!(dynax_select & 0x04)) return 0xff;
3071		if (!(dynax_select & 0x08)) return 0xff;
3072		if (!(dynax_select & 0x10)) return readinputport(15);
	3071	if (!(ddenlovr_select & 0x01)) return readinputport(13);
	3072	if (!(ddenlovr_select & 0x02)) return readinputport(14);
	3073	if (!(ddenlovr_select & 0x04)) return 0xff;
	3074	if (!(ddenlovr_select & 0x08)) return 0xff;
	3075	if (!(ddenlovr_select & 0x10)) return readinputport(15);
3073	3076	return 0xff;
3074	3077	}
3075	3078
r1103	r1104
3112	3115	AM_RANGE(0x40, 0x40) AM_WRITE(OKIM6295_data_0_w )
3113	3116	AM_RANGE(0x60, 0x60) AM_WRITE(YM2413_register_port_0_w )
3114	3117	AM_RANGE(0x61, 0x61) AM_WRITE(YM2413_data_port_0_w )
3115		AM_RANGE(0x80, 0x83) AM_WRITE(dynax_palette_base_w )
3116		AM_RANGE(0x84, 0x87) AM_WRITE(dynax_palette_mask_w )
3117		AM_RANGE(0x88, 0x8b) AM_WRITE(dynax_transparency_pen_w )
3118		AM_RANGE(0x8c, 0x8f) AM_WRITE(dynax_transparency_mask_w )
3119		AM_RANGE(0x94, 0x94) AM_WRITE(dynax_bgcolor_w )
3120		AM_RANGE(0x95, 0x95) AM_WRITE(dynax_priority_w )
3121		AM_RANGE(0x96, 0x96) AM_WRITE(dynax_layer_enable_w )
	3118	AM_RANGE(0x80, 0x83) AM_WRITE(ddenlovr_palette_base_w )
	3119	AM_RANGE(0x84, 0x87) AM_WRITE(ddenlovr_palette_mask_w )
	3120	AM_RANGE(0x88, 0x8b) AM_WRITE(ddenlovr_transparency_pen_w )
	3121	AM_RANGE(0x8c, 0x8f) AM_WRITE(ddenlovr_transparency_mask_w )
	3122	AM_RANGE(0x94, 0x94) AM_WRITE(ddenlovr_bgcolor_w )
	3123	AM_RANGE(0x95, 0x95) AM_WRITE(ddenlovr_priority_w )
	3124	AM_RANGE(0x96, 0x96) AM_WRITE(ddenlovr_layer_enable_w )
3122	3125	AM_RANGE(0xa0, 0xa0) AM_WRITE(hginga_input_w )
3123	3126	AM_RANGE(0xa1, 0xa1) AM_WRITE(hparadis_coin_w )
3124	3127	AM_RANGE(0xc2, 0xc2) AM_WRITE(MWA8_NOP ) // enables palette RAM at c000
r1103	r1104
3131	3134
3132	3135	static READ8_HANDLER( mjmywrld_coins_r )
3133	3136	{
3134		switch( dynax_select2 )
	3137	switch( ddenlovr_select2 )
3135	3138	{
3136	3139	case 0x80: return readinputport(0);
3137	3140	case 0x81: return 0x00;
r1103	r1104
3139	3142	case 0x83: return 0x00;
3140	3143	}
3141	3144
3142		logerror("%06x: warning, unknown bits read, dynax_select2 = %02x\n", activecpu_get_pc(), dynax_select2);
	3145	logerror("%06x: warning, unknown bits read, ddenlovr_select2 = %02x\n", activecpu_get_pc(), ddenlovr_select2);
3143	3146
3144	3147	return 0xff;
3145	3148	}
r1103	r1104
3168	3171	AM_RANGE(0x46, 0x46) AM_WRITE( AY8910_write_port_0_w )
3169	3172	AM_RANGE(0x48, 0x48) AM_WRITE( AY8910_control_port_0_w )
3170	3173	AM_RANGE(0x60, 0x6f) AM_WRITE( msm6242_w ) // 6242RTC
3171		AM_RANGE(0x80, 0x83) AM_WRITE( dynax_palette_base_w )
3172		AM_RANGE(0x84, 0x87) AM_WRITE( dynax_palette_mask_w )
3173		AM_RANGE(0x88, 0x8b) AM_WRITE( dynax_transparency_pen_w )
3174		AM_RANGE(0x8c, 0x8f) AM_WRITE( dynax_transparency_mask_w)
3175		AM_RANGE(0x94, 0x94) AM_WRITE( dynax_bgcolor_w )
3176		AM_RANGE(0x95, 0x95) AM_WRITE( dynax_priority_w )
3177		AM_RANGE(0x96, 0x96) AM_WRITE( dynax_layer_enable_w )
	3174	AM_RANGE(0x80, 0x83) AM_WRITE( ddenlovr_palette_base_w )
	3175	AM_RANGE(0x84, 0x87) AM_WRITE( ddenlovr_palette_mask_w )
	3176	AM_RANGE(0x88, 0x8b) AM_WRITE( ddenlovr_transparency_pen_w )
	3177	AM_RANGE(0x8c, 0x8f) AM_WRITE( ddenlovr_transparency_mask_w)
	3178	AM_RANGE(0x94, 0x94) AM_WRITE( ddenlovr_bgcolor_w )
	3179	AM_RANGE(0x95, 0x95) AM_WRITE( ddenlovr_priority_w )
	3180	AM_RANGE(0x96, 0x96) AM_WRITE( ddenlovr_layer_enable_w )
3178	3181	ADDRESS_MAP_END
3179	3182
3180	3183
r1103	r1104
3216	3219
3217	3220	static READ16_HANDLER( akamaru_blitter_r )
3218	3221	{
3219		return dynax_blitter_irq_flag << 6; // bit 7 = 1 -> blitter busy
	3222	return ddenlovr_blitter_irq_flag << 6; // bit 7 = 1 -> blitter busy
3220	3223	}
3221	3224
3222	3225	static READ16_HANDLER( akamaru_e0010d_r )
r1103	r1104
3247	3250	AM_RANGE(0x213570, 0x213571) AM_WRITE(akamaru_protection1_w ) // OKI bank
3248	3251	AM_RANGE(0xd00000, 0xd003ff) AM_WRITE(ddenlovr_palette_w ) // Palette
3249	3252	// AM_RANGE(0xd01000, 0xd017ff) AM_WRITE(MWA16_RAM ) // 0
3250		AM_RANGE(0xe00040, 0xe00047) AM_WRITE(ddenlovr_palette_base_w )
3251		AM_RANGE(0xe00048, 0xe0004f) AM_WRITE(ddenlovr_palette_mask_w )
3252		AM_RANGE(0xe00050, 0xe00057) AM_WRITE(ddenlovr_transparency_pen_w )
3253		AM_RANGE(0xe00058, 0xe0005f) AM_WRITE(ddenlovr_transparency_mask_w )
3254		AM_RANGE(0xe00068, 0xe00069) AM_WRITE(ddenlovr_bgcolor_w )
3255		AM_RANGE(0xe0006a, 0xe0006b) AM_WRITE(ddenlovr_priority_w )
3256		AM_RANGE(0xe0006c, 0xe0006d) AM_WRITE(ddenlovr_layer_enable_w )
	3253	AM_RANGE(0xe00040, 0xe00047) AM_WRITE(ddenlovr16_palette_base_w )
	3254	AM_RANGE(0xe00048, 0xe0004f) AM_WRITE(ddenlovr16_palette_mask_w )
	3255	AM_RANGE(0xe00050, 0xe00057) AM_WRITE(ddenlovr16_transparency_pen_w )
	3256	AM_RANGE(0xe00058, 0xe0005f) AM_WRITE(ddenlovr16_transparency_mask_w)
	3257	AM_RANGE(0xe00068, 0xe00069) AM_WRITE(ddenlovr16_bgcolor_w )
	3258	AM_RANGE(0xe0006a, 0xe0006b) AM_WRITE(ddenlovr16_priority_w )
	3259	AM_RANGE(0xe0006c, 0xe0006d) AM_WRITE(ddenlovr16_layer_enable_w )
3257	3260	AM_RANGE(0xe00080, 0xe00083) AM_WRITE(ddenlovr_blitter_w )
3258	3261	AM_RANGE(0xe00108, 0xe0010b) AM_WRITE(MWA16_RAM ) AM_BASE( &akamaru_protection2 )
3259	3262	AM_RANGE(0xe00302, 0xe00303) AM_WRITE(ddenlovr_blitter_irq_ack_w ) // Blitter irq acknowledge
r1103	r1104
3346	3349
3347	3350	static ADDRESS_MAP_START( mjflove_writeport, ADDRESS_SPACE_IO, 8 ) // 16 bit I/O
3348	3351	AM_RANGE(0x001e, 0x001e) AM_WRITE( hanakanz_keyb_w ) AM_MIRROR(0xff00)
3349		AM_RANGE(0x0020, 0x0023) AM_WRITE( dynax_palette_base_w )
3350		AM_RANGE(0x0024, 0x0027) AM_WRITE( dynax_palette_mask_w )
3351		AM_RANGE(0x0028, 0x002b) AM_WRITE( dynax_transparency_pen_w )
3352		AM_RANGE(0x002c, 0x002f) AM_WRITE( dynax_transparency_mask_w)
3353		AM_RANGE(0x0034, 0x0034) AM_WRITE( dynax_bgcolor_w )
3354		AM_RANGE(0x0035, 0x0035) AM_WRITE( dynax_priority_w )
3355		AM_RANGE(0x0036, 0x0036) AM_WRITE( dynax_layer_enable_w )
	3352	AM_RANGE(0x0020, 0x0023) AM_WRITE( ddenlovr_palette_base_w )
	3353	AM_RANGE(0x0024, 0x0027) AM_WRITE( ddenlovr_palette_mask_w )
	3354	AM_RANGE(0x0028, 0x002b) AM_WRITE( ddenlovr_transparency_pen_w )
	3355	AM_RANGE(0x002c, 0x002f) AM_WRITE( ddenlovr_transparency_mask_w)
	3356	AM_RANGE(0x0034, 0x0034) AM_WRITE( ddenlovr_bgcolor_w )
	3357	AM_RANGE(0x0035, 0x0035) AM_WRITE( ddenlovr_priority_w )
	3358	AM_RANGE(0x0036, 0x0036) AM_WRITE( ddenlovr_layer_enable_w )
3356	3359	AM_RANGE(0x0040, 0x0041) AM_WRITE( mjflove_blitter_w ) AM_MIRROR(0xff00)
3357	3360	AM_RANGE(0x00f2, 0x00f2) AM_WRITE( mjmyster_rambank_w ) AM_MIRROR(0xff00)
3358	3361	AM_RANGE(0x00f8, 0x00f8) AM_WRITE( mjflove_rombank_w ) AM_MIRROR(0xff00)
r1103	r1104
6571	6574	quiz365_input_r,
6572	6575	0,
6573	6576	0,
6574		dynax_select_w
	6577	ddenlovr_select_w
6575	6578	};
6576	6579
6577	6580	static MACHINE_DRIVER_START( quiz365 )
r1103	r1104
6911	6914	0,
6912	6915	0,
6913	6916	0,
6914		dynax_select_w
	6917	ddenlovr_select_w
6915	6918	};
6916	6919
6917	6920	static MACHINE_DRIVER_START( mjmyster )
r1103	r1104
6958	6961	{
6959	6962	// A B
6960	6963	hginga_dsw_r, 0, // R
6961		0, dynax_select_w // W
	6964	0, ddenlovr_select_w // W
6962	6965	};
6963	6966
6964	6967	static MACHINE_DRIVER_START( hginga )

src/mame/drivers/ms32.c
r1103	r1104
75	75	Re-Add Priorities
76	76
77	77	Dip switches/inputs in t2m32 and f1superb
78		some games (hayaosi1) don't seeem to have service mode even if it's listed among the dips
	78	some games (hayaosi2) don't seeem to have service mode even if it's listed among the dips
79	79	service mode is still accessible through F1 though
80	80
81	81	Fix Anything Else (Palette etc.)
r1103	r1104
152	152	Mahjong Angel Kiss
153	153	*Vs. Janshi Brand New Stars
154	154
155		Hayaoshi Quiz Ouza Ketteisen (hayaosi1)
	155	Hayaoshi Quiz Ouza Ketteisen (hayaosi2)
156	156	*Hayaoshi Quiz Nettou Namahousou
157	157	*Hayaoshi Quiz Grand Champion Taikai
158	158
r1103	r1104
1031	1031
1032	1032	INPUT_PORTS_END
1033	1033
1034		INPUT_PORTS_START( hayaosi1 )
	1034	INPUT_PORTS_START( hayaosi2 )
1035	1035	MS32_UNKNOWN_INPUTS
1036	1036
1037	1037	MS32_SYSTEM_INPUTS
r1103	r1104
1497	1497	{
1498	1498	if( cpu_getiloops() == 0 ) irq_raise(10);
1499	1499	if( cpu_getiloops() == 1 ) irq_raise(9);
1500		/* hayaosi1 needs at least 12 IRQ 0 per frame to work (see code at FFE02289)
	1500	/* hayaosi2 needs at least 12 IRQ 0 per frame to work (see code at FFE02289)
1501	1501	kirarast needs it too, at least 8 per frame, but waits for a variable amount
1502	1502	47pi2 needs ?? per frame (otherwise it hangs when you lose)
1503	1503	in different points. Could this be a raster interrupt?
r1103	r1104
1929	1929	ROM_LOAD( "mr94041.14", 0x200000, 0x200000, CRC(2d6308bd) SHA1(600b6ccdbb976301075e0b287124a9fd5fe7fc1b) )
1930	1930	ROM_END
1931	1931
1932		ROM_START( hayaosi1 )
	1932	ROM_START( hayaosi2 )
1933	1933	ROM_REGION( 0x200000, REGION_CPU1, 0 ) /* V70 code */
1934	1934	ROM_LOAD32_BYTE( "mb93138a.25", 0x000003, 0x80000, CRC(563c6f2f) SHA1(bc2a61fd2e0adf58256feeef8491b67af6d6eacf) )
1935	1935	ROM_LOAD32_BYTE( "mb93138a.27", 0x000002, 0x80000, CRC(fe8e283a) SHA1(fc6c06ae296110b1f5794187d5208b17541614cb) )
r1103	r1104
1962	1962	ROM_LOAD( "mr93038.01", 0x200000, 0x200000, CRC(b8a38bfc) SHA1(1aa7b69beebceb6f09a1ee006de054cb84002e94) )
1963	1963	ROM_END
1964	1964
	1965	/*
	1966
	1967	Hayaoshi Quiz Nettou Namahousou
	1968	(c)1993 Jaleco
	1969
	1970	MB-93140A EB91022-20079-1 (Motherboard. Mega System 32?)
	1971	MB-93138A EB91022-20078-1 (ROM board)
	1972	SE-93139 EB91022-30056 (extended board on ROM board)
	1973
	1974	CPU : NEC JAPAN D70632GD-20 (V70)
	1975	Sound: Z80 YMF271-F
	1976	OSC : 48.0000MHz (OSC1) 40.0000MHz (OSC2) 16.9344MHz (X1)
	1977
	1978	ROMs:
	1979	MR94027.02 (16M mask, location IC 3( 1)) [59976568]
	1980	MR94027.04 (16M mask, location IC 4( 2)) [6a16d13a]
	1981	MR94027.06 (16M mask, location IC 5( 3)) [1618785a]
	1982	MR94027.08 (16M mask, location IC 6( 4)) [753b05e0]
	1983
	1984	MR94027.09 (16M mask, location IC11( 9)) [32ead437]
	1985	MR94027.11 (16M mask, location IC13(11)) [b65d5096]
	1986
	1987	MR94027.01 (16M mask, location IC20(13)) [c72e5c6e]
	1988	MR94027.03 (16M mask, location IC21(14)) [3ff68f4f]
	1989	MR94027.05 (16M mask, location IC22(15)) [59545977]
	1990	MR94027.07 (16M mask, location IC23(16)) [c66099c4]
	1991
	1992	MB93138.21 (M27C2001, location IC30(21)) [008bc217] Ver1.0
	1993	actual label is "MB-93138 21 Ver1.0"
	1994
	1995	MR92042.01 (16M mask, location IC33(22)) [0fa26f65]
	1996	MR94027.10 (16M mask, locaiton IC34(23)) [e7cabe41]
	1997
	1998	MB93138.25 (M27C4001, location IC36(25)) [ba8cec03] Ver1.5
	1999	MB93138.27 (M27C4001, location IC38(27)) [571725df] Ver1.5
	2000	MB93138.29 (M27C4001, location IC40(29)) [da891976] Ver1.5
	2001	MB93138.31 (M27C4001, location IC42(31)) [2d17bb06] Ver1.5
	2002	actual label is "???????N?C?Y?M?????????IMB-93138-?? Ver.1.5"
	2003
	2004	MB93138.32 (M27C4001, location IC43(32)) [df5d00b4] Ver1.0
	2005	actual label is "MB-93138 32 Ver1.0"
	2006
	2007
	2008	PALs (not dumped):
	2009	91022-01.2 (18CV8, IC83(2))
	2010	91022-02.1 (22CV10, IC62(1))
	2011
	2012	Custom chips:
	2013	SS91022-01 9348 ACBA (IC36, 208pin PQFP)
	2014	SS91022-02 9350 IAHA (IC 9, 100pin PQFP)
	2015	SS91022-03 9343EX006 (IC11, 176pin PQFP)
	2016	SS91022-05 9347EX002 (IC31, 120pin PQFP)
	2017	SS91022-07 9345EV 450881 06440 (IC70, 208pin PQFP)
	2018
	2019	GS91022-01 9340EK002 (IC46, 120pin PQFP)
	2020	GS91022-02 9334EK709 (IC6, 160pin PQFP)
	2021	GS91022-03 9335PP711 (IC7, 100pin PQFP)
	2022	GS91022-04 9334PP712 (IC24, 100pin PQFP)
	2023
	2024	SS92046-01 9338EV 436091 06441 (IC1 of EB91022-30056, 144pin PQFP)
	2025
	2026	Others:
	2027	Lithium battery + LH5168D-10L(SRAM)
	2028
	2029	*/
	2030
	2031
	2032	ROM_START( hayaosi3 )
	2033	ROM_REGION( 0x200000, REGION_CPU1, 0 ) /* V70 code */
	2034	ROM_LOAD32_BYTE( "mb93138.25", 0x000003, 0x80000, CRC(ba8cec03) SHA1(edaa52e0b07307bb21168205ee0d5d6ff8168de9) )
	2035	ROM_LOAD32_BYTE( "mb93138.27", 0x000002, 0x80000, CRC(571725df) SHA1(66575ec1a29d6fc1b50ae5a5ce8025bb1043deaf))
	2036	ROM_LOAD32_BYTE( "mb93138.29", 0x000001, 0x80000, CRC(da891976) SHA1(27e8c395e92ca01b47bffdf766bc95a6c2150815) )
	2037	ROM_LOAD32_BYTE( "mb93138.31", 0x000000, 0x80000, CRC(2d17bb06) SHA1(623b603c4002734427c882424a1e0dc889cf7e02) )
	2038
	2039	ROM_REGION( 0x1000000, REGION_GFX1, 0 ) /* sprites, don't dispose since we use GFX_RAW */
	2040	ROM_LOAD32_WORD( "mr94027.01", 0x000000, 0x200000, CRC(c72e5c6e) SHA1(b98cd656c48c775953d00b5d8bafd4ffde76d8df) )
	2041	ROM_LOAD32_WORD( "mr94027.02", 0x000002, 0x200000, CRC(59976568) SHA1(a280c352d612913834c76b8e23d86c937fd21281) )
	2042	ROM_LOAD32_WORD( "mr94027.03", 0x400000, 0x200000, CRC(3ff68f4f) SHA1(1e367b92560c32c87e27fc0e99be3bdb5eb0510b) )
	2043	ROM_LOAD32_WORD( "mr94027.04", 0x400002, 0x200000, CRC(6a16d13a) SHA1(65a7751c248c966fd01149418ce6bedba7a0d48a) )
	2044	ROM_LOAD32_WORD( "mr94027.05", 0x800000, 0x200000, CRC(59545977) SHA1(2e0a83efd7ae210c0b4360e9572dd7eec38cd974) )
	2045	ROM_LOAD32_WORD( "mr94027.06", 0x800002, 0x200000, CRC(1618785a) SHA1(3f2698d07a52947429313a78ebcedfdae478efd7) )
	2046	ROM_LOAD32_WORD( "mr94027.07", 0xc00000, 0x200000, CRC(c66099c4) SHA1(5a6edffa39a98f38cc3cffbad9191fb2e794a812) )
	2047	ROM_LOAD32_WORD( "mr94027.08", 0xc00002, 0x200000, CRC(753b05e0) SHA1(0424e92b32a73c27ecb549e6e9449446ea938e40) )
	2048
	2049	ROM_REGION( 0x200000, REGION_GFX2, 0 ) /* roz tiles, don't dispose since we use GFX_RAW */
	2050	ROM_LOAD( "mr94027.09", 0x000000, 0x200000, CRC(32ead437) SHA1(b94175cf186b4ebcc180a4c092d2ffcdd9ff3b1d) )
	2051
	2052	ROM_REGION( 0x200000, REGION_GFX3, 0 ) /* bg tiles, don't dispose since we use GFX_RAW */
	2053	ROM_LOAD( "mr94027.11", 0x000000, 0x200000, CRC(b65d5096) SHA1(2c4e1e3e9f96be8369cb2de142a82f94506f85c0) )
	2054
	2055	ROM_REGION( 0x080000, REGION_GFX4, 0 ) /* tx tiles, don't dispose since we use GFX_RAW */
	2056	ROM_LOAD( "mb93138.32", 0x000000, 0x080000, CRC(df5d00b4) SHA1(2bbbcd546d5b5170d81bf33b37b46b70b417c9c7) )
	2057
	2058	ROM_REGION( 0x50000, REGION_CPU2, 0 ) /* z80 program */
	2059	ROM_LOAD( "mb93138.21", 0x000000, 0x040000, CRC(008bc217) SHA1(eec66a86f285ccbc47eba17a4bb83cc1f8a5f425) )
	2060	ROM_RELOAD( 0x010000, 0x40000 )
	2061
	2062	ROM_REGION( 0x400000, REGION_SOUND1, 0 ) /* samples - 8-bit signed PCM */
	2063	ROM_LOAD( "mr92042.01", 0x000000, 0x200000, CRC(0fa26f65) SHA1(e92b14862fbce33ea4ab4567ec48199bfcbbdd84) ) // common samples
	2064	ROM_LOAD( "mr94027.10", 0x200000, 0x200000, CRC(e7cabe41) SHA1(5d903baed690a98856f7581319cf4dbfe1db47bb) )
	2065	ROM_END
	2066
1965	2067	ROM_START( kirarast )
1966	2068	ROM_REGION( 0x200000, REGION_CPU1, 0 ) /* V70 code */
1967	2069	ROM_LOAD32_BYTE( "mr95025.26", 0x000003, 0x80000, CRC(eb7faf5f) SHA1(5b79ff3043db5ef2622ae1665145462d949c9bb8) )
r1103	r1104
2133	2235
2134	2236	/* SS91022-10: desertwr, gratiaa, tp2m32, gametngk */
2135	2237
2136		/* SS92046_01: bbbxing, f1superb, tetrisp, hayaosi1 */
	2238	/* SS92046_01: bbbxing, f1superb, tetrisp, hayaosi2 */
2137	2239
2138	2240	/* SS92047-01: gratia, kirarast */
2139	2241
r1103	r1104
2292	2394	decrypt_ms32_bg(0x00000,0xa3, REGION_GFX3);
2293	2395	}
2294	2396
2295		/* SS92046_01: bbbxing, f1superb, tetrisp, hayaosi1 */
	2397	/* SS92046_01: bbbxing, f1superb, tetrisp, hayaosi2 */
2296	2398	static DRIVER_INIT (ss92046_01)
2297	2399	{
2298	2400	configure_banks();
r1103	r1104
2346	2448
2347	2449	/******** GAME DRIVERS ********/
2348	2450
2349		GAME( 1994, hayaosi1, 0, ms32, hayaosi1, ss92046_01, ROT0, "Jaleco", "Hayaoshi Quiz Ouza Ketteisen", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND )
	2451
	2452
	2453	GAME( 1994, hayaosi2, 0, ms32, hayaosi2, ss92046_01, ROT0, "Jaleco", "Hayaoshi Quiz Grand Champion Taikai", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND )
	2454	GAME( 1994, hayaosi3, 0, ms32, hayaosi2, ss92046_01, ROT0, "Jaleco", "Hayaoshi Quiz Nettou Namahousou", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND )
2350	2455	GAME( 1994, bbbxing, 0, ms32, bbbxing, ss92046_01, ROT0, "Jaleco", "Best Bout Boxing", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND )
2351	2456	GAME( 1994, 47pie2, 0, ms32, akiss, 47pie2, ROT0, "Jaleco", "Idol Janshi Su-Chi-Pie 2 (v1.1)", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND \| GAME_SUPPORTS_SAVE )
2352	2457	GAME( 1994, 47pie2o, 47pie2, ms32, akiss, 47pie2, ROT0, "Jaleco", "Idol Janshi Su-Chi-Pie 2 (v1.0)", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND \| GAME_SUPPORTS_SAVE )

src/mame/drivers/kyugo.c
r1103	r1104
1077	1077	ROM_LOAD( "epl12p6a.9k", 0x0300, 0x0034, CRC(f5acad85) SHA1(ee3caeedf3e91793b12895f109eae5417f5c7631) )
1078	1078	ROM_END
1079	1079
	1080	ROM_START( airwolfa )
	1081	ROM_REGION( 0x10000, REGION_CPU1, 0 )
	1082	ROM_LOAD( "airwolf.2", 0x0000, 0x8000, CRC(bc1a8587) SHA1(5487096621c175759eb4a4a85b76ef32900ca522) )
	1083
	1084	ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* the rom with this set was bad with FIXED BITS (11xxxxxx), but the remaining bits matched */
	1085	ROM_LOAD( "airwolf.1", 0x0000, 0x8000, CRC(a3c7af5c) SHA1(0f70ca94f3d168d38e0e93252e9441973f72441a) )
	1086
	1087	ROM_REGION( 0x02000, REGION_GFX1, ROMREGION_DISPOSE )
	1088	ROM_LOAD( "airwolf.6", 0x00000, 0x2000, CRC(5b0a01e9) SHA1(a2873054caf08fcfa51e2f87556e9529b7d4b865) ) /* chars */
	1089
	1090	ROM_REGION( 0x06000, REGION_GFX2, ROMREGION_DISPOSE )
	1091	ROM_LOAD( "airwolf.9", 0x00000, 0x2000, CRC(25e57e1f) SHA1(bef24bced102cd470e10bd4aa19da3c608211258) ) /* tiles - plane 1 */
	1092	ROM_LOAD( "airwolf.8", 0x02000, 0x2000, CRC(cf0de5e9) SHA1(32f3eb4c9298d59aca1dc2530b0e92f64311946d) ) /* tiles - plane 0 */
	1093	ROM_LOAD( "airwolf.7", 0x04000, 0x2000, CRC(4050c048) SHA1(ca21e0750f01342d9791067160339eec436c9458) ) /* tiles - plane 2 */
	1094
	1095	ROM_REGION( 0x18000, REGION_GFX3, ROMREGION_DISPOSE )
	1096	ROM_LOAD( "airwolf.5", 0x00000, 0x2000, CRC(e8fbc7d2) SHA1(a9a651b4a714f490a051a89fd0327a665353d64b) ) /* sprites - plane 0 */
	1097	ROM_CONTINUE( 0x04000, 0x2000 )
	1098	ROM_CONTINUE( 0x02000, 0x2000 )
	1099	ROM_CONTINUE( 0x06000, 0x2000 )
	1100	ROM_LOAD( "airwolf.4", 0x08000, 0x2000, CRC(c5d4156b) SHA1(f66ec33b67e39f3df016231b00e48c9757e322f3) ) /* sprites - plane 1 */
	1101	ROM_CONTINUE( 0x0c000, 0x2000 )
	1102	ROM_CONTINUE( 0x0a000, 0x2000 )
	1103	ROM_CONTINUE( 0x0e000, 0x2000 )
	1104	ROM_LOAD( "airwolf.3", 0x10000, 0x2000, CRC(de91dfb1) SHA1(9f338542f44905d0b895d99510475113eb860f0d) ) /* sprites - plane 2 */
	1105	ROM_CONTINUE( 0x14000, 0x2000 )
	1106	ROM_CONTINUE( 0x12000, 0x2000 )
	1107	ROM_CONTINUE( 0x16000, 0x2000 )
	1108
	1109	ROM_REGION( 0x0340, REGION_PROMS, 0 )
	1110	ROM_LOAD( "01j.bin", 0x0000, 0x0100, CRC(6a94b2a3) SHA1(b1f9bd97aa26c9fb6377ef32d5dd125583361f48) ) /* red */
	1111	ROM_LOAD( "01h.bin", 0x0100, 0x0100, CRC(ec0923d3) SHA1(26f9eda4260a8b767893b8dea42819f192ef0b20) ) /* green */
	1112	ROM_LOAD( "01f.bin", 0x0200, 0x0100, CRC(ade97052) SHA1(cc1b4cd57d7bc55ce44de6b89a322ff08eabb1a0) ) /* blue */
	1113	/* 0x0300-0x031f empty - looks like there isn't a lookup table PROM */
	1114	ROM_LOAD( "m1.2c", 0x0320, 0x0020, CRC(83a39201) SHA1(4fdc722c9e20ee152c890342ef0dce18e35e2ef8) ) /* timing? not used */
	1115
	1116	ROM_REGION( 0x0400, REGION_PLDS, ROMREGION_DISPOSE )
	1117	ROM_LOAD( "pal16l8a.2j", 0x0000, 0x0104, NO_DUMP ) /* PAL is read protected */
	1118	ROM_LOAD( "epl12p6a.9j", 0x0200, 0x0034, CRC(19808f14) SHA1(d5043237be8857d2cecaf7dec079461f6b53efa9) )
	1119	ROM_LOAD( "epl12p6a.9k", 0x0300, 0x0034, CRC(f5acad85) SHA1(ee3caeedf3e91793b12895f109eae5417f5c7631) )
	1120	ROM_END
	1121
1080	1122	ROM_START( skywolf )
1081	1123	ROM_REGION( 0x10000, REGION_CPU1, 0 )
1082	1124	ROM_LOAD( "02s_03.bin", 0x0000, 0x4000, CRC(a0891798) SHA1(c1b1e1fce529509fb1dd921a0022d5367c3c495c) )
r1103	r1104
1230	1272	GAME( 1986, srdmissn, 0, srdmissn, srdmissn, srdmissn, ROT90, "Taito Corporation", "S.R.D. Mission", 0 )
1231	1273	GAME( 1986, fx, srdmissn, srdmissn, srdmissn, srdmissn, ROT90, "bootleg", "F-X", 0 )
1232	1274	GAME( 1986?,legend, 0, legend, legend, srdmissn, ROT0, "Sega / Coreland ?", "Legend", 0 )
1233		GAME( 1987, airwolf, 0, srdmissn, airwolf, srdmissn, ROT0, "Kyugo", "Airwolf", 0 )
	1275	GAME( 1987, airwolf, 0, srdmissn, airwolf, srdmissn, ROT0, "Kyugo", "Airwolf (set 1)", 0 )
	1276	GAME( 1987, airwolfa, airwolf, srdmissn, airwolf, srdmissn, ROT0, "Kyugo (UA Theatre license)", "Airwolf (US)", 0 )
1234	1277	GAME( 1987, skywolf, airwolf, srdmissn, skywolf, srdmissn, ROT0, "bootleg", "Sky Wolf (set 1)", 0 )
1235	1278	GAME( 1987, skywolf2, airwolf, srdmissn, airwolf, srdmissn, ROT0, "bootleg", "Sky Wolf (set 2)", 0 )

src/mame/drivers/tmnt.c
r1103	r1104
89	89	WRITE16_HANDLER( prmrsocr_122000_w );
90	90	WRITE16_HANDLER( tmnt_priority_w );
91	91	READ16_HANDLER( glfgreat_ball_r );
	92	READ16_HANDLER( prmrsocr_rom_r );
92	93	VIDEO_START( sunsetbl );
93	94	VIDEO_START( cuebrckj );
94	95	VIDEO_START( mia );
r1103	r1104
954	955	AM_RANGE(0x120002, 0x120003) AM_READ(prmrsocr_eeprom_r)
955	956	AM_RANGE(0x121014, 0x121015) AM_READ(prmrsocr_sound_r)
956	957	AM_RANGE(0x200000, 0x207fff) AM_READ(K052109_word_noA12_r)
	958	AM_RANGE(0x300000, 0x33ffff) AM_READ(prmrsocr_rom_r)
957	959	ADDRESS_MAP_END
958	960
959	961	static ADDRESS_MAP_START( prmrsocr_writemem, ADDRESS_SPACE_PROGRAM, 16 )
r1103	r1104
3964	3966	ROM_LOAD( "064e11.12k", 0x080000, 0x080000, CRC(2d8ca8b0) SHA1(7c882f79c2402cf75979c681071007d76e4db9ae) )
3965	3967
3966	3968	ROM_REGION( 0x200000, REGION_GFX2, 0 ) /* graphics (addressable by the main CPU) */
3967		ROM_LOAD( "sunsetb.05", 0x000000, 0x080000, CRC(8a0ff31a) SHA1(fee21d787d1cddd04713e10b1622f3fa231ebc4e) )
3968		ROM_LOAD( "sunsetb.06", 0x080000, 0x080000, CRC(fdf2c887) SHA1(a165c7e6495d870324f59262ad4175a039e199a5) )
3969		ROM_LOAD( "sunsetb.07", 0x100000, 0x080000, CRC(a545b1ed) SHA1(249f1f1a992f05c0dc23bd52785a355a402a0d10) )
3970		ROM_LOAD( "sunsetb.08", 0x180000, 0x080000, CRC(f867cd38) SHA1(633703474010364dc47176965daa873d548da074) )
	3969	ROM_LOAD( "sunsetb.05", 0x000000, 0x080000, BAD_DUMP CRC(8a0ff31a) SHA1(fee21d787d1cddd04713e10b1622f3fa231ebc4e) )
	3970	ROM_LOAD( "sunsetb.06", 0x080000, 0x080000, BAD_DUMP CRC(fdf2c887) SHA1(a165c7e6495d870324f59262ad4175a039e199a5) )
	3971	ROM_LOAD( "sunsetb.07", 0x100000, 0x080000, BAD_DUMP CRC(a545b1ed) SHA1(249f1f1a992f05c0dc23bd52785a355a402a0d10) )
	3972	ROM_LOAD( "sunsetb.08", 0x180000, 0x080000, BAD_DUMP CRC(f867cd38) SHA1(633703474010364dc47176965daa873d548da074) )
3971	3973
3972	3974	ROM_REGION( 0x100000, REGION_SOUND1, 0 ) /* samples */
3973	3975	ROM_LOAD( "sunsetb.01", 0x000000, 0x080000, CRC(1a8b5ca2) SHA1(4101686c7bf3243273a52fca046b252fc3c78721) )
r1103	r1104
4032	4034	ROM_LOAD( "101a09.3l", 0x000000, 0x200000, CRC(b6a1b424) SHA1(4cf7bb4b8176977dea10fb80fcd9d6e24cc6d1b9) ) /* sprites */
4033	4035	ROM_LOAD( "101a10.8l", 0x200000, 0x200000, CRC(bbd58adc) SHA1(ad9bd4df995de6e6290f27c58c7892c7191802e4) )
4034	4036
4035		ROM_REGION( 0x080000, REGION_GFX3, ~~ROMREGION_DISPOSE~~ ) /* 053936 tiles */
	4037	ROM_REGION( 0x080000, REGION_GFX3, 0 ) /* 053936 tiles */
4036	4038	ROM_LOAD( "101a03.18f", 0x000000, 0x080000, CRC(59a1a91c) SHA1(f596a40784a671e97116df6561682eb6c5c44e08) )
4037	4039
4038	4040	ROM_REGION( 0x040000, REGION_USER1, 0 ) /* 053936 tilemaps */
r1103	r1104
4060	4062	ROM_LOAD( "101a09.3l", 0x000000, 0x200000, CRC(b6a1b424) SHA1(4cf7bb4b8176977dea10fb80fcd9d6e24cc6d1b9) ) /* sprites */
4061	4063	ROM_LOAD( "101a10.8l", 0x200000, 0x200000, CRC(bbd58adc) SHA1(ad9bd4df995de6e6290f27c58c7892c7191802e4) )
4062	4064
4063		ROM_REGION( 0x080000, REGION_GFX3, ~~ROMREGION_DISPOSE~~ ) /* 053936 tiles */
	4065	ROM_REGION( 0x080000, REGION_GFX3, 0 ) /* 053936 tiles */
4064	4066	ROM_LOAD( "101a03.18f", 0x000000, 0x080000, CRC(59a1a91c) SHA1(f596a40784a671e97116df6561682eb6c5c44e08) )
4065	4067
4066	4068	ROM_REGION( 0x040000, REGION_USER1, 0 ) /* 053936 tilemaps */

src/mame/drivers/iqblock.c
r1103	r1104
85	85	cpunum_set_input_line(0, 0, CLEAR_LINE);
86	86	}
87	87
	88	static READ8_HANDLER( iqblock_irqack_r )
	89	{
	90	cpunum_set_input_line(0, 0, CLEAR_LINE);
	91	return 0;
	92	}
	93
88	94	static READ8_HANDLER( extrarom_r )
89	95	{
90	96	return memory_region(REGION_USER1)[offset];
r1103	r1104
145	151	AM_RANGE(0x8000, 0xffff) AM_READ(extrarom_r)
146	152	ADDRESS_MAP_END
147	153
	154	static ADDRESS_MAP_START( pokerigs_portmap, ADDRESS_SPACE_IO, 8 )
	155	AM_RANGE(0x2000, 0x23ff) AM_WRITE(paletteram_xBBBBBGGGGGRRRRR_split1_w)
	156	AM_RANGE(0x2800, 0x2bff) AM_WRITE(paletteram_xBBBBBGGGGGRRRRR_split2_w)
	157	// AM_RANGE(0x6000, 0x603f) AM_WRITE(iqblock_fgscroll_w)
	158	// AM_RANGE(0x6800, 0x69ff) AM_WRITE(iqblock_fgvideoram_w)
	159	AM_RANGE(0x7000, 0x7fff) AM_WRITE(iqblock_bgvideoram_w)
	160	AM_RANGE(0x5080, 0x5083) AM_WRITE(ppi8255_0_w)
	161	AM_RANGE(0x5080, 0x5083) AM_READ(ppi8255_0_r)
	162	AM_RANGE(0x5090, 0x5090) AM_READ(input_port_3_r) AM_WRITENOP
	163	AM_RANGE(0x5091, 0x5091) AM_READNOP AM_WRITENOP
	164	AM_RANGE(0x50a0, 0x50a0) AM_READ(input_port_4_r)
	165	AM_RANGE(0x50b0, 0x50b0) AM_WRITE(YM2413_register_port_0_w) // UM3567_register_port_0_w
	166	AM_RANGE(0x50b1, 0x50b1) AM_WRITE(YM2413_data_port_0_w) // UM3567_data_port_0_w
	167	AM_RANGE(0x50c0, 0x50c0) AM_READ(iqblock_irqack_r)
	168	// AM_RANGE(0x7000, 0x7fff) AM_READ(iqblock_bgvideoram_r)
	169	// AM_RANGE(0x8000, 0xffff) AM_READ(extrarom_r)
	170	ADDRESS_MAP_END
148	171
149	172
150	173	INPUT_PORTS_START( iqblock )
r1103	r1104
336	359	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
337	360	MACHINE_DRIVER_END
338	361
	362	static MACHINE_DRIVER_START( pokerigs )
339	363
	364	/* basic machine hardware */
	365	MDRV_CPU_ADD(Z180,12000000/2) /* 6 MHz */
	366	MDRV_CPU_PROGRAM_MAP(main_map,0)
	367	MDRV_CPU_IO_MAP(pokerigs_portmap,0)
	368	MDRV_CPU_VBLANK_INT(iqblock_interrupt,16)
340	369
	370	MDRV_SCREEN_REFRESH_RATE(60)
	371	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
	372	MDRV_MACHINE_RESET(iqblock)
	373
	374	/* video hardware */
	375	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
	376	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
	377	MDRV_SCREEN_SIZE(648, 328)
	378	MDRV_SCREEN_VISIBLE_AREA(08, 648-1, 08, 308-1)
	379	MDRV_GFXDECODE(cabaret)
	380	MDRV_PALETTE_LENGTH(1024)
	381
	382	MDRV_VIDEO_START(iqblock)
	383	MDRV_VIDEO_UPDATE(iqblock)
	384
	385	/* sound hardware */
	386	MDRV_SPEAKER_STANDARD_MONO("mono")
	387
	388	MDRV_SOUND_ADD(YM2413, 3579545)
	389	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	390	MACHINE_DRIVER_END
	391
	392
	393
341	394	/***************************************************************************
342	395
343	396	Game driver(s)
r1103	r1104
396	449	ROM_LOAD( "cg-3.u42", 0x8000, 0x4000, CRC(7e1f821f) SHA1(b709d49f9d1890fe3b8ca7f90affc0017a0ad95e) )
397	450	ROM_END
398	451
	452	/*
399	453
	454	1x ZILOG Z0840006PSC-Z80CPU (main)
	455	1x YM2413 (sound)
	456	1x NEC D8255AC (label: ORIGINAL BY IGS 102986)
	457	1x oscillator 12.000MHz (main)
	458	1x oscillator 3.579545MHz (sound)
400	459
	460	1x custom QFP80 label AMT001
	461	1x custom QFP80 label IGS002
	462	1x custom DIP40 label IGS003 (under chip label 8255)
	463	ROMs 3x MX27C1000DC (4,5,6)
	464	1x NM27C256Q (7)
	465	1x 27C512 (200)
	466	2x PEEL18CV8P (8,9)
	467	1x PAL16L8ACN (31)
	468	2x PEEL18CV8P (12,14) <-> UNREADABLE, protected!
	469
	470	Note 1x 10x2 edge connector (con1) (looks like a coin payout)
	471	1x 36x2 edge connector (con2)
	472	1x pushbutton (sw6)
	473	5x 8 switches dips (sw1-5)
	474	1x trimmer (volume)
	475	----------------------
	476	IGS PCB NO-T0039-8
	477
	478	*/
	479
	480	ROM_START( pokerigs )
	481	// code at 0xf000 looks like startup code
	482	ROM_REGION( 0x20000, REGION_CPU1, 0 ) /* DIP28 Code */
	483	ROM_LOAD( "champingv-200g.u23", 0x00000, 0x10000, CRC(696cb684) SHA1(ce9e5bed83d0bd3b115f556cc89e3293ac6b69c3) )
	484
	485	ROM_REGION( 0x60000, REGION_GFX1, ROMREGION_DISPOSE )
	486	ROM_LOAD( "cpoker4.u4", 0x00000, 0x20000, CRC(860be7c9) SHA1(41bc58713076276aeefc44c7ea903549692b0224) )
	487	ROM_LOAD( "cpoker5.u5", 0x20000, 0x20000, CRC(a68b305f) SHA1(f872d2bf7ab194145dffe6b254ae0ad66aa6a497) )
	488	ROM_LOAD( "cpoker6.u6", 0x40000, 0x20000, CRC(f3e61b24) SHA1(b18998defb6e51daef4ac5a5865674565ffb9029) )
	489
	490	//copy?
	491	ROM_REGION( 0x60000, REGION_GFX2, ROMREGION_DISPOSE )
	492	ROM_COPY( REGION_GFX1, 0, 0, 0x60000 )
	493
	494	ROM_REGION( 0x8000, REGION_USER1, 0 )
	495	ROM_LOAD( "cpoker7.u22", 0x00000, 0x8000, CRC(dae3ecda) SHA1(c881e143ec600c5a931f26cd097da6353e1da7c3) )
	496
	497	// convert them to the pld format
	498	ROM_REGION( 0x2000, REGION_PLDS, ROMREGION_DISPOSE )
	499	ROM_LOAD( "ag-u31.u31", 0x00000, 0x000b60, CRC(fd36baf2) SHA1(caac8bf47bc958395f97b6191569196efe3b3eaa) )
	500	ROM_LOAD( "ag-u8.u8", 0x00000, 0x0015e2, CRC(c0308c63) SHA1(16819a5c147fef38a235675fa4442da9fa8a6618) )
	501	ROM_LOAD( "ag-u9.u9", 0x00000, 0x0015e2, CRC(2e8039a3) SHA1(e39635ee9485a5ccd28526f1af7ec2e3294b0aec) )
	502	ROM_END
	503
401	504	static DRIVER_INIT( iqblock )
402	505	{
403	506	UINT8 *rom = memory_region(REGION_CPU1);
r1103	r1104
462	565	iqblock_video_type=0;
463	566	}
464	567
	568	static DRIVER_INIT( pokerigs )
	569	{
	570	UINT8 *rom = memory_region(REGION_CPU1);
	571	int i;
465	572
	573	/* decrypt the program ROM */
	574	for (i = 0;i < 0x10000;i++)
	575	{
	576	if((i & 0x200) && (i & 0x80))
	577	{
	578	rom[i] ^= ((~i & 2) >> 1);
	579	}
	580	else
	581	{
	582	rom[i] ^= 0x01;
	583	}
466	584
467		GAME( 1993, iqblock, 0, iqblock, iqblock, iqblock, ROT0, "IGS", "IQ-Block", 0 )
468		GAME( 1993, grndtour, 0, iqblock, iqblock, grndtour, ROT0, "IGS", "Grand Tour", 0 )
	585	if((i & 0x30) != 0x10)
	586	{
	587	rom[i] ^= 0x20;
	588	}
469	589
470		GAME( 19??, cabaret, 0, cabaret, iqblock, cabaret, ROT0, "IGS", "Cabaret", GAME_NOT_WORKING \| GAME_NO_SOUND )
	590	if((i & 0x900) == 0x900 && ((i & 0xc0) == 0x40 \|\| (i & 0xc0) == 0xc0))
	591	{
	592	rom[i] ^= 0x02;
	593	}
	594	}
	595
	596
	597	/* initialize pointers for I/O mapped RAM */
	598	paletteram = rom + 0x12000;
	599	paletteram_2 = rom + 0x12800;
	600	iqblock_fgvideoram = rom + 0x16800;
	601	iqblock_bgvideoram = rom + 0x17000;
	602	iqblock_video_type=0;
	603	}
	604
	605
	606	GAME( 1993, iqblock, 0, iqblock, iqblock, iqblock, ROT0, "IGS", "IQ-Block", 0 )
	607	GAME( 1993, grndtour, 0, iqblock, iqblock, grndtour, ROT0, "IGS", "Grand Tour", 0 )
	608
	609	GAME( 19??, cabaret, 0, cabaret, iqblock, cabaret, ROT0, "IGS", "Cabaret", GAME_NOT_WORKING \| GAME_NO_SOUND )
	610	GAME( 1995, pokerigs, 0, pokerigs, iqblock, pokerigs, ROT0, "IGS", "Poker? (IGS)", GAME_NOT_WORKING )

src/mame/drivers/seattle.c
r1103	r1104
453	453	static UINT8 status_leds;
454	454
455	455	static int speedup_index;
456		static UINT32 *generic_speedup;
457		static UINT32 *generic_speedup2;
458	456
459	457	static UINT32 cmos_write_enabled;
460	458
r1103	r1104
1585	1583	{
1586	1584	if (cmos_write_enabled)
1587	1585	COMBINE_DATA(generic_nvram32 + offset);
1588		cmos_write_enabled = 0;
	1586	cmos_write_enabled = FALSE;
1589	1587	}
1590	1588
1591	1589
r1103	r1104
1597	1595
1598	1596	static WRITE32_HANDLER( cmos_protect_w )
1599	1597	{
1600		cmos_write_enabled = 1;
	1598	cmos_write_enabled = TRUE;
1601	1599	}
1602	1600
1603	1601
r1103	r1104
1650	1648
1651	1649	/*************************************
1652	1650	*
1653		* Speedups
1654		*
1655		*************************************/
1656
1657		static READ32_HANDLER( generic_speedup_r )
1658		{
1659		activecpu_eat_cycles(100);
1660		return *generic_speedup;
1661		}
1662
1663
1664		static WRITE32_HANDLER( generic_speedup_w )
1665		{
1666		activecpu_eat_cycles(100);
1667		COMBINE_DATA(generic_speedup);
1668		}
1669
1670
1671		static READ32_HANDLER( generic_speedup2_r )
1672		{
1673		activecpu_eat_cycles(100);
1674		return *generic_speedup2;
1675		}
1676
1677
1678
1679		/*************************************
1680		*
1681	1651	* Memory maps
1682	1652	*
1683	1653	*************************************/
r1103	r1104
2800	2770	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_SELECT, speedup_index++);
2801	2771	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_PC, pc);
2802	2772	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, op);
2803		cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, ~~100~~0);
	2773	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 250);
2804	2774	}
2805	2775
2806	2776
r1103	r1104
2810	2780	init_common(MIDWAY_IOASIC_STANDARD, 310/* others? */, 80, PHOENIX_CONFIG);
2811	2781
2812	2782	/* speedups */
2813		add_speedup(0x80044178, 0x0230102b);
2814		add_speedup(0x8009494c, 0x94820000);
	2783	add_speedup(0x8004413C, 0x0C0054B4); /* confirmed */
	2784	add_speedup(0x80094930, 0x00A2102B); /* confirmed */
	2785	add_speedup(0x80092984, 0x3C028011); /* confirmed */
2815	2786	}
2816	2787
2817	2788
r1103	r1104
2821	2792	init_common(MIDWAY_IOASIC_MACE, 319/* others? */, 80, SEATTLE_CONFIG);
2822	2793
2823	2794	/* speedups */
2824		add_speedup(0x800108f8, 0x8c420000);
	2795	add_speedup(0x800108F8, 0x8C420000); /* confirmed */
2825	2796	}
2826	2797
2827	2798
r1103	r1104
2831	2802	init_common(MIDWAY_IOASIC_STANDARD, 315/* no alternates */, 100, FLAGSTAFF_CONFIG);
2832	2803
2833	2804	/* speedups */
2834		memory_install_read32_handler(0, ADDRESS_SPACE_PROGRAM, 0x0012498c, 0x0012498f, 0, 0, generic_speedup_r);
2835		generic_speedup = &rambase[0x12498c/4];
2836		memory_install_read32_handler(0, ADDRESS_SPACE_PROGRAM, 0x00120000, 0x00120003, 0, 0, generic_speedup2_r);
2837		generic_speedup2 = &rambase[0x120000/4];
	2805	add_speedup(0x80059F34, 0x3C028012); /* confirmed */
	2806	add_speedup(0x800A5AF4, 0x8E300010); /* confirmed */
	2807	add_speedup(0x8004C260, 0x3C028012); /* confirmed */
2838	2808	}
2839	2809
2840	2810
r1103	r1104
2844	2814	init_common(MIDWAY_IOASIC_SFRUSHRK, 331/* unknown */, 100, FLAGSTAFF_CONFIG);
2845	2815
2846	2816	/* speedups */
2847		// memory_install_read32_handler(0, ADDRESS_SPACE_PROGRAM, 0x0012498c, 0x0012498f, 0, 0, generic_speedup_r);
2848		// generic_speedup = &rambase[0x12498c/4];
2849		// memory_install_read32_handler(0, ADDRESS_SPACE_PROGRAM, 0x00120000, 0x00120003, 0, 0, generic_speedup2_r);
2850		// generic_speedup2 = &rambase[0x120000/4];
	2817	add_speedup(0x800343E8, 0x3C028012); /* confirmed */
	2818	add_speedup(0x8008F4F0, 0x3C028012); /* confirmed */
	2819	add_speedup(0x800A365C, 0x8E300014); /* confirmed */
	2820	add_speedup(0x80051DAC, 0x3C028012); /* confirmed */
2851	2821	}
2852	2822
2853	2823
r1103	r1104
2858	2828	midway_ioasic_set_auto_ack(1);
2859	2829
2860	2830	/* speedups */
2861		memory_install_read32_handler(0, ADDRESS_SPACE_PROGRAM, 0x002e6480, 0x002e6483, 0, 0, generic_speedup_r);
2862		generic_speedup = &rambase[0x2e6480/4];
	2831	add_speedup(0x80032534, 0x02221024); /* confirmed */
	2832	add_speedup(0x800B1BE4, 0x8E110014); /* confirmed */
2863	2833	}
2864	2834
2865	2835
r1103	r1104
2869	2839	init_common(MIDWAY_IOASIC_VAPORTRX, 324/* 334? unknown */, 100, SEATTLE_WIDGET_CONFIG);
2870	2840
2871	2841	/* speedups */
	2842	add_speedup(0x80049F14, 0x3C028020); /* confirmed */
	2843	add_speedup(0x8004859C, 0x3C028020); /* confirmed */
	2844	add_speedup(0x8005922C, 0x8E020014); /* confirmed */
2872	2845	}
2873	2846
2874	2847
r1103	r1104
2878	2851	init_common(MIDWAY_IOASIC_STANDARD, 231/* no alternates */, 80, SEATTLE_CONFIG);
2879	2852
2880	2853	/* speedups */
2881		// memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x002502bc, 0x002502bf, 0, 0, generic_speedup_w);
2882		// generic_speedup = &rambase[0x2502bc/4];
2883	2854	}
2884	2855
2885	2856
r1103	r1104
2892	2863	rombase[0x934/4] += 4;
2893	2864
2894	2865	/* main CPU speedups */
2895		add_speedup(0x8013ddbc, 0x1452fff8);
2896		add_speedup(0x80135520, 0x0043102a);
2897
2898		memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x00243d58, 0x00243d5b, 0, 0, generic_speedup_w);
2899		generic_speedup = &rambase[0x243d58/4];
	2866	add_speedup(0x80135510, 0x3C028024); /* confirmed */
	2867	add_speedup(0x800087DC, 0x8E820010); /* confirmed */
2900	2868	}
2901	2869
2902	2870
r1103	r1104
2906	2874	init_common(MIDWAY_IOASIC_BLITZ99, 481/* or 484 or 520 */, 80, SEATTLE_CONFIG);
2907	2875
2908	2876	/* speedups */
2909		memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x002502bc, 0x002502bf, 0, 0, generic_speedup_w);
2910		generic_speedup = &rambase[0x2502bc/4];
	2877	add_speedup(0x8014E41C, 0x3C038025); /* confirmed */
	2878	add_speedup(0x80011F10, 0x8E020018); /* confirmed */
2911	2879	}
2912	2880
2913	2881
r1103	r1104
2917	2885	init_common(MIDWAY_IOASIC_BLITZ99, 494/* or 498 */, 80, SEATTLE_CONFIG);
2918	2886
2919	2887	/* speedups */
2920		memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x0024e8d8, 0x0024e8db, 0, 0, generic_speedup_w);
2921		generic_speedup = &rambase[0x24e8d8/4];
	2888	add_speedup(0x8015773C, 0x3C038025); /* confirmed */
	2889	add_speedup(0x80012CA8, 0x8E020018); /* confirmed */
2922	2890	}
2923	2891
2924	2892
r1103	r1104
2932	2900	memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x16800000, 0x1680001f, 0, 0, carnevil_gun_w);
2933	2901
2934	2902	/* speedups */
2935		add_speedup(0x80151780, 0xac232bac);
	2903	add_speedup(0x8015176C, 0x3C03801A); /* confirmed */
	2904	add_speedup(0x80011FBC, 0x8E020018); /* confirmed */
2936	2905	}
2937	2906
2938	2907
r1103	r1104
2942	2911	init_common(MIDWAY_IOASIC_HYPRDRIV, 469/* unknown */, 80, SEATTLE_WIDGET_CONFIG);
2943	2912
2944	2913	/* speedups */
2945		add_speedup(0x80164424, 0x080590ef);
2946		add_speedup(0x801646fc, 0xc7bfff38);
	2914	add_speedup(0x801643BC, 0x3C03801B); /* confirmed */
	2915	add_speedup(0x80011FB8, 0x8E020018); /* confirmed */
	2916	//add_speedup(0x80136A80, 0x3C02801D); /* potential */
2947	2917	}
2948	2918
2949	2919

src/mame/drivers/metro.c
r1103	r1104
5885	5885	ROM_LOAD( "trii_ja_7", 0x000000, 0x020000, CRC(6ee32315) SHA1(ef4d59576929deab0aa459a67be21d97c2803dea) )
5886	5886	ROM_END
5887	5887
	5888	ROM_START( toride2j )
	5889	ROM_REGION( 0x080000, REGION_CPU1, 0 ) /* 68000 Code */
	5890	ROM_LOAD16_BYTE( "tr2_jk-5.20e", 0x000000, 0x040000, CRC(f2668578) SHA1(1dd18a5597efb25c937697b50fb1262f50580a63) )
	5891	ROM_LOAD16_BYTE( "tr2_jk-6.20c", 0x000001, 0x040000, CRC(4c87629f) SHA1(5fde8580bedb783491ee87ecfe4b1c22d0c9f716) )
	5892
	5893	ROM_REGION( 0x02c000, REGION_CPU2, 0 ) /* NEC78C10 Code */
	5894	ROM_LOAD( "tr2_jb-8.3i", 0x000000, 0x004000, CRC(0168f46f) SHA1(01bf4cc425d72936897c3c572f6c0b1366fe4041) )
	5895	ROM_CONTINUE( 0x010000, 0x01c000 )
	5896
	5897	ROM_REGION( 0x200000, REGION_GFX1, 0 ) /* Gfx + Data (Addressable by CPU & Blitter) */
	5898	ROMX_LOAD( "tr2_jb-2.14i", 0x000000, 0x080000, CRC(b31754dc) SHA1(be2423bafbf07c93c3d222e907190b44616014f0) , ROM_GROUPWORD \| ROM_SKIP(6))
	5899	ROMX_LOAD( "tr2_jb-4.18i", 0x000002, 0x080000, CRC(a855c3fa) SHA1(eca3e235256df7e6ae66ecbe43bc0edb974af503) , ROM_GROUPWORD \| ROM_SKIP(6))
	5900	ROMX_LOAD( "tr2_jb-1.12i", 0x000004, 0x080000, CRC(856f40b7) SHA1(99aca5472b991cd08e9c2128ffdd40675a3b968d) , ROM_GROUPWORD \| ROM_SKIP(6))
	5901	ROMX_LOAD( "tr2_jb-3.16i", 0x000006, 0x080000, CRC(78ba205f) SHA1(1069a362e60747aaa284c0d9bb7718013df347f3) , ROM_GROUPWORD \| ROM_SKIP(6))
	5902
	5903	ROM_REGION( 0x020000, REGION_SOUND1, 0 ) /* Samples */
	5904	ROM_LOAD( "pcm.3g", 0x000000, 0x020000, CRC(6ee32315) SHA1(ef4d59576929deab0aa459a67be21d97c2803dea) )
	5905	ROM_END
	5906
5888	5907	/***************************************************************************
5889	5908
5890	5909
r1103	r1104
5908	5927	GAME( 1994, lastforg, lastfort, lastforg, ladykill, metro, ROT0, "Metro", "Last Fortress - Toride (German)" , 0 )
5909	5928	GAME( 1994, toride2g, 0, toride2g, toride2g, metro, ROT0, "Metro", "Toride II Adauchi Gaiden", GAME_IMPERFECT_GRAPHICS )
5910	5929	GAME( 1994, torid2gg, toride2g, toride2g, toride2g, metro, ROT0, "Metro", "Toride II Adauchi Gaiden (German)", GAME_IMPERFECT_GRAPHICS )
	5930	GAME( 1994, toride2j, toride2g, toride2g, toride2g, metro, ROT0, "Metro", "Toride II Adauchi Gaiden (Japan)", GAME_IMPERFECT_GRAPHICS )
5911	5931	GAME( 1994, gunmast, 0, pururun, gunmast, daitorid, ROT0, "Metro", "Gun Master" , 0 )
5912	5932	GAME( 1995, daitorid, 0, daitorid, daitorid, daitorid, ROT0, "Metro", "Daitoride", GAME_IMPERFECT_GRAPHICS )
5913	5933	GAME( 1995, dokyusei, 0, dokyusei, dokyusei, gakusai, ROT0, "Make Software / Elf / Media Trading", "Mahjong Doukyuusei" , 0 )

src/mame/drivers/jongkyo.c
r1103	r1104
32	32	*/
33	33
34	34
	35	//static UINT8 *videoram;
	36
35	37	static int rom_bank;
	38	static UINT8* videoram2;
36	39
37
38	40	VIDEO_START(jongkyo)
39	41	{
40	42
r1103	r1104
51	53	for (x = 0; x < 256; x += 4)
52	54	{
53	55	int b;
54		UINT8 data;
	56	UINT8 data1;
	57	UINT8 data2;
	58	UINT8 data3;
55	59
56		// bottom layer
57		data = videoram[0x4000 + x/4 + y*64];
58		for (b = 0; b < 4; ++b)
59		{
60		*BITMAP_ADDR16(bitmap, 255-y, 255-(x+b)) = (data & 0x01) + ((data & 0x10) >> 3);
	60	// data3 = videoram2[x/4 + y*64]; // wrong
61	61
62		data >>= 1;
63		}
	62	// good mahjong tiles
	63	// data3 = 0x0f; // we're missing 2 bits.. there must be another piece of video ram somewhere or we can't use all the colours (6bpp).. banked somehow?
	64	// good girl tiles
	65	data3 = 0x00; // we're missing 2 bits.. there must be another piece of video ram somewhere or we can't use all the colours (6bpp).. banked somehow?
64	66
65		// top layer
66		data = videoram[x/4 + y*64];
	67
	68
	69	data1 = videoram[0x4000 + x/4 + y*64];
	70	data2 = videoram[x/4 + y*64];
	71
67	72	for (b = 0; b < 4; ++b)
68	73	{
69		if (data & 0x11)
70		*BITMAP_ADDR16(bitmap, 255-y, 255-(x+b)) = 4 + (data & 0x01) + ((data & 0x10) >> 3);
71
72		data >>= 1;
	74	*BITMAP_ADDR16(bitmap, 255-y, 255-(x+b)) = ((data2 & 0x01)) +
	75	((data2 & 0x10) >> 3) +
	76	((data1 & 0x01) << 2) +
	77	((data1 & 0x10) >> 1) +
	78	((data3 & 0x01) << 4) +
	79	((data3 & 0x10) << 1);
	80	data1 >>= 1;
	81	data2 >>= 1;
	82	data3 >>= 1;
73	83	}
74	84	}
75	85	}
r1103	r1104
80	90
81	91	static WRITE8_HANDLER( bank_select_w )
82	92	{
	93
83	94	int mask = 1 << (offset >> 1);
84	95
85	96	rom_bank &= ~mask;
r1103	r1104
90	101	memory_set_bank(1, rom_bank);
91	102	}
92	103
	104	static UINT8 keyboard_select;
93	105
94	106	static READ8_HANDLER( keyboard1_r )
95	107	{
	108	switch (keyboard_select)
	109	{
	110
	111	default:
	112	printf("keyboard1_r, select %02x\n",keyboard_select);
	113	return 0xff;
	114
	115	case 0xef:
	116	return readinputportbytag("0");
	117
	118	case 0xf7:
	119	return readinputportbytag("1");
	120
	121	case 0xfb:
	122	return readinputportbytag("2");
	123
	124	case 0xfd:
	125	return readinputportbytag("3");
	126
	127	case 0xfe:
	128	return readinputportbytag("4");
	129	}
	130
96	131	return 0xff;
97	132	}
98	133
99	134
100	135	static READ8_HANDLER( keyboard2_r )
101	136	{
	137	switch (keyboard_select)
	138	{
	139
	140	default:
	141	printf("keyboard2_r, select %02x\n",keyboard_select);
	142	return 0xff;
	143
	144	case 0xef:
	145	return readinputportbytag("5");
	146
	147	case 0xf7:
	148	return readinputportbytag("6");
	149
	150	case 0xfb:
	151	return readinputportbytag("7");
	152
	153	case 0xfd:
	154	return readinputportbytag("8");
	155
	156	case 0xfe:
	157	return readinputportbytag("9");
	158	}
	159
102	160	return 0xff;
103	161	}
104	162
105	163
	164	static WRITE8_HANDLER( keyboard_select_w )
	165	{
	166	keyboard_select = data;
	167	}
	168
	169	static WRITE8_HANDLER( videoram2_w )
	170	{
	171	videoram2[offset] = data;
	172	}
	173
106	174	static ADDRESS_MAP_START( jongkyo_memmap, ADDRESS_SPACE_PROGRAM, 8 )
107		AM_RANGE(0x0000, 0x6bff) AM_ROM AM_WRITENOP // fixed
	175	AM_RANGE(0x0000, 0x3fff) AM_READ(MRA8_ROM) AM_WRITE(videoram2_w) // wrong, this doesn't seem to be video ram on write..
	176	AM_RANGE(0x4000, 0x6bff) AM_READ(MRA8_ROM) // fixed rom
108	177	AM_RANGE(0x6c00, 0x6fff) AM_READ(MRA8_BANK1) // banked (8 banks)
109	178	AM_RANGE(0x7000, 0x77ff) AM_RAM
110	179	AM_RANGE(0x8000, 0xffff) AM_RAM AM_BASE(&videoram)
r1103	r1104
119	188	AM_RANGE(0x03, 0x03) AM_WRITE(AY8910_control_port_0_w)
120	189
121	190	AM_RANGE(0x10, 0x10) AM_READ_PORT("DSW")
122		AM_RANGE(0x11, 0x11) AM_READ_PORT("IN0")
	191	AM_RANGE(0x11, 0x11) AM_READ_PORT("IN0") AM_WRITE(keyboard_select_w)
123	192	// W 11 select keyboard row (fe fd fb f7)
124	193	AM_RANGE(0x40, 0x45) AM_WRITE(bank_select_w)
125	194	ADDRESS_MAP_END
r1103	r1104
162	231
163	232
164	233	INPUT_PORTS_START( jongkyo )
	234	PORT_START_TAG("0")
	235	PORT_DIPNAME( 0x01, 0x01, "0" )
	236	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	237	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	238	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	239	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	240	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	241	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	242	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	243	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	244	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	245	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	246	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	247	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	248	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	249	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	250	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	251	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	252	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	253	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	254	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	255	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	256	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	257	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	258	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	259
	260	PORT_START_TAG("1")
	261	PORT_DIPNAME( 0x01, 0x01, "1" )
	262	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	263	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	264	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	265	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	266	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	267	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	268	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	269	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	270	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	271	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	272	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	273	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	274	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	275	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	276	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	277	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	278	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	279	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	280	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	281	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	282	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	283	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	284	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	285
	286	PORT_START_TAG("2")
	287	PORT_DIPNAME( 0x01, 0x01, "2" )
	288	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	289	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	290	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	291	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	292	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	293	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	294	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	295	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	296	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	297	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	298	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	299	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	300	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	301	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	302	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	303	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	304	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	305	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	306	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	307	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	308	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	309	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	310	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	311
	312	PORT_START_TAG("3")
	313	PORT_DIPNAME( 0x01, 0x01, "3" )
	314	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	315	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	316	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	317	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	318	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	319	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	320	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	321	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	322	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	323	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	324	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	325	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	326	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	327	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	328	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	329	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	330	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	331	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	332	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	333	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	334	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	335	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	336	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	337
	338	PORT_START_TAG("4")
	339	PORT_DIPNAME( 0x01, 0x01, "4" )
	340	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	341	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	342	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	343	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	344	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	345	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	346	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	347	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	348	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	349	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	350	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	351	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	352	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	353	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	354	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	355	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	356	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	357	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	358	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	359	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	360	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	361	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	362	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	363
	364	PORT_START_TAG("5")
	365	PORT_DIPNAME( 0x01, 0x01, "5" )
	366	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	367	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	368	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	369	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	370	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	371	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	372	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	373	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	374	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	375	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	376	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	377	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	378	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	379	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	380	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	381	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	382	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	383	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	384	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	385	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	386	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	387	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	388	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	389
	390	PORT_START_TAG("6")
	391	PORT_DIPNAME( 0x01, 0x01, "6" )
	392	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	393	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	394	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	395	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	396	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	397	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	398	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	399	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	400	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	401	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	402	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	403	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	404	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	405	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	406	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	407	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	408	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	409	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	410	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	411	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	412	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	413	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	414	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	415
	416	PORT_START_TAG("7")
	417	PORT_DIPNAME( 0x01, 0x01, "7" )
	418	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	419	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	420	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	421	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	422	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	423	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	424	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	425	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	426	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	427	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	428	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	429	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	430	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	431	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	432	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	433	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	434	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	435	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	436	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	437	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	438	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	439	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	440	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	441
	442	PORT_START_TAG("8")
	443	PORT_DIPNAME( 0x01, 0x01, "8" )
	444	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	445	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	446	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	447	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	448	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	449	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	450	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	451	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	452	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	453	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	454	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	455	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	456	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	457	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	458	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	459	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	460	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	461	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	462	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	463	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	464	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	465	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	466	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	467
	468	PORT_START_TAG("9")
	469	PORT_DIPNAME( 0x01, 0x01, "9")
	470	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	471	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	472	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	473	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	474	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	475	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	476	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	477	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	478	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	479	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	480	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	481	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	482	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	483	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	484	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	485	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	486	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	487	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	488	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	489	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	490	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	491	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	492	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	493
	494	PORT_START_TAG("10")
	495	PORT_DIPNAME( 0x01, 0x01, "10" )
	496	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	497	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	498	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	499	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	500	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	501	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	502	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	503	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	504	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	505	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	506	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	507	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	508	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	509	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	510	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	511	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	512	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	513	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	514	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	515	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	516	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	517	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	518	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	519
165	520	PORT_START_TAG("IN0")
166	521	PORT_DIPNAME( 0x01, 0x00, "Note" )
167	522	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
r1103	r1104
208	563	INPUT_PORTS_END
209	564
210	565
	566	PALETTE_INIT(jongkyo)
	567	{
	568	int i;
	569	UINT8* proms = memory_region(REGION_PROMS);
	570	for (i=0;i<0x40;i++)
	571	{
	572	int data = proms[i];
	573
	574	int r = (data >> 0) & 0x07;
	575	int g = (data >> 3) & 0x07;
	576	int b = (data >> 6) & 0x03;
	577
	578	palette_set_color_rgb(machine, i, r<<5, g<<5, b<<6 );
	579
	580	}
	581	}
	582
211	583	static struct AY8910interface ay8910_interface =
212	584	{
213	585	keyboard1_r,
r1103	r1104
230	602	MDRV_SCREEN_SIZE(256, 256)
231	603	MDRV_SCREEN_VISIBLE_AREA(0, 256-1, 8, 256-8-1)
232	604	MDRV_PALETTE_LENGTH(0x100)
	605	MDRV_PALETTE_INIT(jongkyo)
233	606
234	607	MDRV_VIDEO_START(jongkyo)
235	608	MDRV_VIDEO_UPDATE(jongkyo)
r1103	r1104
249	622	ROM_LOAD( "epr-6262", 0x06000, 0x01000, CRC(ecf50f34) SHA1(ecfa1a9360d8fbcbed457d46e53bae77f6d78c1d) )
250	623	ROM_LOAD( "epr-6261", 0x07000, 0x02000, CRC(9c475ae1) SHA1(b993c2636dafed9f80fa87e71921c3c85c039e45) ) // banked at 6c00-6fff
251	624
252		ROM_REGION( 0x40000, REGION_PROMS, 0 )
	625	ROM_REGION( 0x300, REGION_PROMS, 0 )
	626	/* colours */
253	627	ROM_LOAD( "pr-6263.6j", 0x00000, 0x00020, CRC(468134d9) SHA1(bb633929df17e448882ee80613fc1dfac3c35d7a) )
254		ROM_LOAD( "pr-6264.0h", 0x00000, 0x00020, CRC(46014727) SHA1(eec451f292ee319fa6bfbbf223aaa12b231692c1) )
255		ROM_LOAD( "pr-6265.0m", 0x00000, 0x00100, CRC(f09d3c4c) SHA1(a9e752d75e7f3ebd05add4ccf2f9f15d8f9a8d15) )
256		ROM_LOAD( "pr-6266.0b", 0x00000, 0x00100, CRC(86aeafd1) SHA1(c4e5c56ce5baf2be3962675ae333e28bd8108a00) )
	628	ROM_LOAD( "pr-6264.0h", 0x00020, 0x00020, CRC(46014727) SHA1(eec451f292ee319fa6bfbbf223aaa12b231692c1) )
	629
	630	/* unknown purpose */
	631	ROM_LOAD( "pr-6265.0m", 0x00100, 0x00100, CRC(f09d3c4c) SHA1(a9e752d75e7f3ebd05add4ccf2f9f15d8f9a8d15) )
	632	ROM_LOAD( "pr-6266.0b", 0x00200, 0x00100, CRC(86aeafd1) SHA1(c4e5c56ce5baf2be3962675ae333e28bd8108a00) )
257	633	ROM_END
258	634
259	635
r1103	r1104
270	646
271	647	/* then do the standard Sega decryption */
272	648	jongkyo_decode();
	649
	650	videoram2 = auto_malloc(0x4000);
	651	state_save_register_global_pointer(videoram2, 0x4000);
	652
273	653	}
274	654
275	655
276		GAME( 1985, jongkyo, 0, jongkyo, jongkyo, jongkyo, ROT0, "Kiwako", "Jongkyo", GAME_~~NOT_~~WORKING )
	656	GAME( 1985, jongkyo, 0, jongkyo, jongkyo, jongkyo, ROT0, "Kiwako", "Jongkyo", GAME_WRONG_COLORS )

src/mame/drivers/bnstars.c
r1103	r1104
5	5	Single board version with Dual Screen output
6	6	(MS32 version also exists)
7	7
	8	for the time being most of this driver is copied
	9	from ms32.c, with some adjustments for dual screen.
	10
	11
8	12	Main PCB
9	13	--------
10	14
r1103	r1104
91	95	extern void decrypt_ms32_tx(int addr_xor,int data_xor, int region);
92	96	extern void decrypt_ms32_bg(int addr_xor,int data_xor, int region);
93	97
	98	static tilemap *ms32_tx_tilemap[2];
	99	static tilemap *ms32_bg_tilemap[2];
	100	static tilemap *ms32_roz_tilemap[2];
	101
	102	static UINT32 ms32_tx0_ram, ms32_tx1_ram;
	103	static UINT32 ms32_bg0_ram, ms32_bg1_ram;
	104	static UINT32 ms32_roz0_ram,ms32_roz1_ram;
	105
	106	static UINT32 *ms32_pal_ram[2];
	107	static UINT32 *ms32_roz_ctrl[2];
	108	static UINT32 *ms32_spram;
	109	static UINT32 ms32_tx0_scroll, ms32_bg0_scroll;
	110	static UINT32 ms32_tx1_scroll, ms32_bg1_scroll;
	111
	112
	113	static UINT32 bnstars1_mahjong_select;
	114
	115	static TILE_GET_INFO( get_ms32_tx0_tile_info )
	116	{
	117	int tileno, colour;
	118
	119	tileno = ms32_tx0_ram[tile_index *2+0] & 0x0000ffff;
	120	colour = ms32_tx0_ram[tile_index *2+1] & 0x000000f0;
	121
	122	SET_TILE_INFO(3,tileno,colour,0);
	123	}
	124
	125	static TILE_GET_INFO( get_ms32_tx1_tile_info )
	126	{
	127	int tileno, colour;
	128
	129	tileno = ms32_tx1_ram[tile_index *2+0] & 0x0000ffff;
	130	colour = ms32_tx1_ram[tile_index *2+1] & 0x000000f0;
	131
	132	SET_TILE_INFO(7,tileno,colour,0);
	133	}
	134
	135	static WRITE32_HANDLER( ms32_tx0_ram_w )
	136	{
	137	COMBINE_DATA(&ms32_tx0_ram[offset]);
	138	tilemap_mark_tile_dirty(ms32_tx_tilemap[0],offset/2);
	139	}
	140
	141	static WRITE32_HANDLER( ms32_tx1_ram_w )
	142	{
	143	COMBINE_DATA(&ms32_tx1_ram[offset]);
	144	tilemap_mark_tile_dirty(ms32_tx_tilemap[1],offset/2);
	145	}
	146
	147	/* BG Layers */
	148
	149	static TILE_GET_INFO( get_ms32_bg0_tile_info )
	150	{
	151	int tileno,colour;
	152
	153	tileno = ms32_bg0_ram[tile_index *2+0] & 0x0000ffff;
	154	colour = ms32_bg0_ram[tile_index *2+1] & 0x000000f0;
	155
	156	SET_TILE_INFO(2,tileno,colour,0);
	157	}
	158
	159	static TILE_GET_INFO( get_ms32_bg1_tile_info )
	160	{
	161	int tileno,colour;
	162
	163	tileno = ms32_bg1_ram[tile_index *2+0] & 0x0000ffff;
	164	colour = ms32_bg1_ram[tile_index *2+1] & 0x000000f0;
	165
	166	SET_TILE_INFO(6,tileno,colour,0);
	167	}
	168
	169	static WRITE32_HANDLER( ms32_bg0_ram_w )
	170	{
	171	COMBINE_DATA(&ms32_bg0_ram[offset]);
	172	tilemap_mark_tile_dirty(ms32_bg_tilemap[0],offset/2);
	173	}
	174
	175	static WRITE32_HANDLER( ms32_bg1_ram_w )
	176	{
	177	COMBINE_DATA(&ms32_bg1_ram[offset]);
	178	tilemap_mark_tile_dirty(ms32_bg_tilemap[1],offset/2);
	179	}
	180
	181	/* ROZ Layers */
	182
	183	static void draw_roz(mame_bitmap bitmap, const rectangle cliprect,int priority, int chip)
	184	{
	185	/* TODO: registers 0x40/4 / 0x44/4 and 0x50/4 / 0x54/4 are used, meaning unknown */
	186
	187	if (ms32_roz_ctrl[chip][0x5c/4] & 1) /* "super" mode */
	188	{
	189	printf("no lineram!\n");
	190	return;
	191	/*
	192	rectangle my_clip;
	193	int y,maxy;
	194
	195	my_clip.min_x = cliprect->min_x;
	196	my_clip.max_x = cliprect->max_x;
	197
	198	y = cliprect->min_y;
	199	maxy = cliprect->max_y;
	200
	201	while (y <= maxy)
	202	{
	203	UINT32 lineaddr = ms32_lineram + 8 (y & 0xff);
	204
	205	int start2x = (lineaddr[0x00/4] & 0xffff) \| ((lineaddr[0x04/4] & 3) << 16);
	206	int start2y = (lineaddr[0x08/4] & 0xffff) \| ((lineaddr[0x0c/4] & 3) << 16);
	207	int incxx = (lineaddr[0x10/4] & 0xffff) \| ((lineaddr[0x14/4] & 1) << 16);
	208	int incxy = (lineaddr[0x18/4] & 0xffff) \| ((lineaddr[0x1c/4] & 1) << 16);
	209	int startx = (ms32_roz_ctrl[0x00/4] & 0xffff) \| ((ms32_roz_ctrl[0x04/4] & 3) << 16);
	210	int starty = (ms32_roz_ctrl[0x08/4] & 0xffff) \| ((ms32_roz_ctrl[0x0c/4] & 3) << 16);
	211	int offsx = ms32_roz_ctrl[0x30/4];
	212	int offsy = ms32_roz_ctrl[0x34/4];
	213
	214	my_clip.min_y = my_clip.max_y = y;
	215
	216	offsx += (ms32_roz_ctrl[0x38/4] & 1) * 0x400; // ??? gratia, hayaosi1...
	217	offsy += (ms32_roz_ctrl[0x3c/4] & 1) * 0x400; // ??? gratia, hayaosi1...
	218
	219	// extend sign
	220	if (start2x & 0x20000) start2x \|= ~0x3ffff;
	221	if (start2y & 0x20000) start2y \|= ~0x3ffff;
	222	if (startx & 0x20000) startx \|= ~0x3ffff;
	223	if (starty & 0x20000) starty \|= ~0x3ffff;
	224	if (incxx & 0x10000) incxx \|= ~0x1ffff;
	225	if (incxy & 0x10000) incxy \|= ~0x1ffff;
	226
	227	tilemap_draw_roz(bitmap, &my_clip, ms32_roz_tilemap,
	228	(start2x+startx+offsx)<<16, (start2y+starty+offsy)<<16,
	229	incxx<<8, incxy<<8, 0, 0,
	230	1, // Wrap
	231	0, priority);
	232
	233	y++;
	234	}
	235	*/
	236	}
	237	else /* "simple" mode */
	238	{
	239	int startx = (ms32_roz_ctrl[chip][0x00/4] & 0xffff) \| ((ms32_roz_ctrl[chip][0x04/4] & 3) << 16);
	240	int starty = (ms32_roz_ctrl[chip][0x08/4] & 0xffff) \| ((ms32_roz_ctrl[chip][0x0c/4] & 3) << 16);
	241	int incxx = (ms32_roz_ctrl[chip][0x10/4] & 0xffff) \| ((ms32_roz_ctrl[chip][0x14/4] & 1) << 16);
	242	int incxy = (ms32_roz_ctrl[chip][0x18/4] & 0xffff) \| ((ms32_roz_ctrl[chip][0x1c/4] & 1) << 16);
	243	int incyy = (ms32_roz_ctrl[chip][0x20/4] & 0xffff) \| ((ms32_roz_ctrl[chip][0x24/4] & 1) << 16);
	244	int incyx = (ms32_roz_ctrl[chip][0x28/4] & 0xffff) \| ((ms32_roz_ctrl[chip][0x2c/4] & 1) << 16);
	245	int offsx = ms32_roz_ctrl[chip][0x30/4];
	246	int offsy = ms32_roz_ctrl[chip][0x34/4];
	247
	248	offsx += (ms32_roz_ctrl[chip][0x38/4] & 1) * 0x400; // ??? gratia, hayaosi1...
	249	offsy += (ms32_roz_ctrl[chip][0x3c/4] & 1) * 0x400; // ??? gratia, hayaosi1...
	250
	251	/* extend sign */
	252	if (startx & 0x20000) startx \|= ~0x3ffff;
	253	if (starty & 0x20000) starty \|= ~0x3ffff;
	254	if (incxx & 0x10000) incxx \|= ~0x1ffff;
	255	if (incxy & 0x10000) incxy \|= ~0x1ffff;
	256	if (incyy & 0x10000) incyy \|= ~0x1ffff;
	257	if (incyx & 0x10000) incyx \|= ~0x1ffff;
	258
	259	tilemap_draw_roz(bitmap, cliprect, ms32_roz_tilemap[chip],
	260	(startx+offsx)<<16, (starty+offsy)<<16,
	261	incxx<<8, incxy<<8, incyx<<8, incyy<<8,
	262	1, // Wrap
	263	0, priority);
	264	}
	265	}
	266
	267
	268	static TILE_GET_INFO( get_ms32_roz0_tile_info )
	269	{
	270	int tileno,colour;
	271
	272	tileno = ms32_roz0_ram[tile_index *2+0] & 0x0000ffff;
	273	colour = ms32_roz0_ram[tile_index *2+1] & 0x000000f0;
	274
	275	SET_TILE_INFO(1,tileno,colour,0);
	276	}
	277
	278	static TILE_GET_INFO( get_ms32_roz1_tile_info )
	279	{
	280	int tileno,colour;
	281
	282	tileno = ms32_roz1_ram[tile_index *2+0] & 0x0000ffff;
	283	colour = ms32_roz1_ram[tile_index *2+1] & 0x000000f0;
	284
	285	SET_TILE_INFO(5,tileno,colour,0);
	286	}
	287
	288	static WRITE32_HANDLER( ms32_roz0_ram_w )
	289	{
	290	COMBINE_DATA(&ms32_roz0_ram[offset]);
	291	tilemap_mark_tile_dirty(ms32_roz_tilemap[0],offset/2);
	292	}
	293
	294	static WRITE32_HANDLER( ms32_roz1_ram_w )
	295	{
	296	COMBINE_DATA(&ms32_roz1_ram[offset]);
	297	tilemap_mark_tile_dirty(ms32_roz_tilemap[1],offset/2);
	298	}
	299
	300
	301	static void update_color(int color, int screen)
	302	{
	303	int r,g,b;
	304
	305	r = ((ms32_pal_ram[screen][color*2] & 0xff00) >>8 );
	306	g = ((ms32_pal_ram[screen][color*2] & 0x00ff) >>0 );
	307	b = ((ms32_pal_ram[screen][color*2+1] & 0x00ff) >>0 );
	308
	309	palette_set_color(Machine,color+screen*0x8000,MAKE_RGB(r,g,b));
	310	}
	311
	312	static WRITE32_HANDLER( ms32_pal0_ram_w )
	313	{
	314	COMBINE_DATA(&ms32_pal_ram[0][offset]);
	315	update_color(offset/2, 0);
	316	}
	317
	318	static WRITE32_HANDLER( ms32_pal1_ram_w )
	319	{
	320	COMBINE_DATA(&ms32_pal_ram[1][offset]);
	321	update_color(offset/2, 1);
	322	}
	323
	324	static int ms32_reverse_sprite_order = 0;
	325	static int flipscreen = 0;
	326
	327	/* SPRITES based on tetrisp2 for now, readd priority bits later */
	328	static void draw_sprites(running_machine machine, mame_bitmap bitmap, const rectangle cliprect, UINT32 sprram_top, size_t sprram_size, int region)
	329	{
	330	/***************************************************************************
	331
	332
	333	Sprites Drawing
	334
	335	Offset: Bits: Meaning:
	336
	337	0.w fedc ba98 ---- ----
	338	---- ---- 7654 ---- Priority
	339	---- ---- ---- 3---
	340	---- ---- ---- -2-- Draw this sprite
	341	---- ---- ---- --1- Flip Y
	342	---- ---- ---- ---0 Flip X
	343
	344	1.w fedc ba98 ---- ---- Tile's Y position in the tile page (*)
	345	---- ---- 7654 3210 Tile's X position in the tile page (*)
	346
	347	2.w fedc ---- ---- ---- Color
	348	---- ba98 7654 3210 Tile Page (32x32 tiles = 256x256 pixels each)
	349
	350	3.w fedc ba98 ---- ---- Y Size - 1 (*)
	351	---- ---- 7654 3210 X Size - 1 (*)
	352
	353	4.w fedc ba-- ---- ----
	354	---- --98 7654 3210 Y (Signed)
	355
	356	5.w fedc b--- ---- ----
	357	---- -a98 7654 3210 X (Signed)
	358
	359	6.w fedc ba98 7654 3210 Zoom Y
	360
	361	7.w fedc ba98 7654 3210 Zoom X
	362
	363	(*) 1 pixel granularity
	364
	365	***************************************************************************/
	366
	367	int tx, ty, sx, sy, flipx, flipy;
	368	int xsize, ysize, xzoom, yzoom;
	369	int code, attr, color, size, pri, pri_mask, trans;
	370	gfx_element *gfx = machine->gfx[region];
	371	gfx_element mygfx = *gfx;
	372
	373	UINT32 *source = sprram_top;
	374	const UINT32 *finish = sprram_top + (sprram_size - 0x10) / 4;
	375
	376
	377	if (ms32_reverse_sprite_order == 1)
	378	{
	379	source = sprram_top + (sprram_size - 0x10) / 4;
	380	finish = sprram_top;
	381	}
	382
	383
	384	for (;ms32_reverse_sprite_order ? (source>=finish) : (source<finish); ms32_reverse_sprite_order ? (source-=4) : (source+=4))
	385	{
	386	attr = source[ 0 ];
	387
	388	if ((attr & 0x0004) == 0) continue;
	389
	390	flipx = attr & 1;
	391	flipy = attr & 2;
	392
	393	pri = (attr >> 4)&0xf;
	394
	395	code = source[ 1 ];
	396	color = source[ 2 ];
	397
	398	tx = (code >> 0) & 0xff;
	399	ty = (code >> 8) & 0xff;
	400
	401	code = (color & 0x0fff);
	402
	403	color = (color >> 12) & 0xf;
	404
	405	size = source[ 3 ];
	406
	407	xsize = ((size >> 0) & 0xff) + 1;
	408	ysize = ((size >> 8) & 0xff) + 1;
	409
	410	sy = source[ 4 ];
	411	sx = source[ 5 ];
	412
	413	sx = (sx & 0x3ff) - (sx & 0x400);
	414	sy = (sy & 0x1ff) - (sy & 0x200);
	415
	416	xzoom = (source[ 6 ]&0xffff);
	417	yzoom = (source[ 7 ]&0xffff);
	418
	419	if (!yzoom \|\| !xzoom) continue;
	420
	421	yzoom = 0x1000000/yzoom;
	422	xzoom = 0x1000000/xzoom;
	423
	424	trans = TRANSPARENCY_PEN; // there are surely also shadows (see gametngk) but how they're enabled we don't know
	425
	426	if (flipscreen)
	427	{
	428	sx = 320 - ((xsize*xzoom)>>16) - sx;
	429	sy = 224 - ((ysize*yzoom)>>16) - sy;
	430	flipx = !flipx;
	431	flipy = !flipy;
	432	}
	433
	434	/* change GfxElement parameters to draw only the needed part of the 256x256 tile */
	435	mygfx.width = xsize;
	436	mygfx.height = ysize;
	437	mygfx.gfxdata = gfx->gfxdata + tx + ty * gfx->line_modulo;
	438
	439	/* TODO: priority handling is completely wrong, but better than nothing */
	440	if (pri == 0x0)
	441	pri_mask = 0x00;
	442	else if (pri <= 0xd)
	443	pri_mask = 0xf0;
	444	else if (pri <= 0xe)
	445	pri_mask = 0xfc;
	446	else
	447	pri_mask = 0xfe;
	448
	449	pdrawgfxzoom(bitmap, &mygfx,
	450	code,
	451	color,
	452	flipx, flipy,
	453	sx,sy,
	454	cliprect, trans, 0,
	455	xzoom, yzoom, pri_mask);
	456	} /* end sprite loop */
	457	}
	458
	459
	460
	461	WRITE32_HANDLER( ms32_spramx_w )
	462	{
	463	COMBINE_DATA(&ms32_spram[offset]);
	464	}
	465
	466
94	467	VIDEO_START(bnstars)
95	468	{
	469	ms32_tx_tilemap[0] = tilemap_create(get_ms32_tx0_tile_info,tilemap_scan_rows,TILEMAP_TYPE_PEN, 8, 8,64,64);
	470	ms32_tx_tilemap[1] = tilemap_create(get_ms32_tx1_tile_info,tilemap_scan_rows,TILEMAP_TYPE_PEN, 8, 8,64,64);
	471	tilemap_set_transparent_pen(ms32_tx_tilemap[0],0);
	472	tilemap_set_transparent_pen(ms32_tx_tilemap[1],0);
96	473
	474	ms32_bg_tilemap[0] = tilemap_create(get_ms32_bg0_tile_info,tilemap_scan_rows,TILEMAP_TYPE_PEN,16,16,64,64);
	475	ms32_bg_tilemap[1] = tilemap_create(get_ms32_bg1_tile_info,tilemap_scan_rows,TILEMAP_TYPE_PEN,16,16,64,64);
	476	tilemap_set_transparent_pen(ms32_bg_tilemap[0],0);
	477	tilemap_set_transparent_pen(ms32_bg_tilemap[1],0);
	478
	479	ms32_roz_tilemap[0] = tilemap_create(get_ms32_roz0_tile_info,tilemap_scan_rows,TILEMAP_TYPE_PEN,16,16,128,128);
	480	ms32_roz_tilemap[1] = tilemap_create(get_ms32_roz1_tile_info,tilemap_scan_rows,TILEMAP_TYPE_PEN,16,16,128,128);
	481	tilemap_set_transparent_pen(ms32_roz_tilemap[0],0);
	482	tilemap_set_transparent_pen(ms32_roz_tilemap[1],0);
	483
	484
97	485	}
98	486
	487
	488
	489
	490
99	491	VIDEO_UPDATE(bnstars)
100	492	{
	493
	494	fillbitmap(priority_bitmap,0,cliprect);
	495
	496	if (screen==0)
	497	{
	498	fillbitmap(bitmap,machine->pens[0],cliprect); /* bg color */
	499
	500
	501	tilemap_set_scrollx(ms32_bg_tilemap[0], 0, ms32_bg0_scroll[0x00/4] + ms32_bg0_scroll[0x08/4] + 0x10 );
	502	tilemap_set_scrolly(ms32_bg_tilemap[0], 0, ms32_bg0_scroll[0x0c/4] + ms32_bg0_scroll[0x14/4] );
	503	tilemap_draw(bitmap,cliprect,ms32_bg_tilemap[0],0,1);
	504
	505	draw_roz(bitmap,cliprect,2,0);
	506
	507	tilemap_set_scrollx(ms32_tx_tilemap[0], 0, ms32_tx0_scroll[0x00/4] + ms32_tx0_scroll[0x08/4] + 0x18);
	508	tilemap_set_scrolly(ms32_tx_tilemap[0], 0, ms32_tx0_scroll[0x0c/4] + ms32_tx0_scroll[0x14/4]);
	509	tilemap_draw(bitmap,cliprect,ms32_tx_tilemap[0],0,4);
	510
	511
	512	draw_sprites(machine,bitmap,cliprect, ms32_spram, 0x20000, 0);
	513	}
	514	else
	515	{
	516	fillbitmap(bitmap,machine->pens[0x8000+0],cliprect); /* bg color */
	517
	518
	519	tilemap_set_scrollx(ms32_bg_tilemap[1], 0, ms32_bg1_scroll[0x00/4] + ms32_bg1_scroll[0x08/4] + 0x10 );
	520	tilemap_set_scrolly(ms32_bg_tilemap[1], 0, ms32_bg1_scroll[0x0c/4] + ms32_bg1_scroll[0x14/4] );
	521	tilemap_draw(bitmap,cliprect,ms32_bg_tilemap[1],0,1);
	522
	523	draw_roz(bitmap,cliprect,2,1);
	524
	525	tilemap_set_scrollx(ms32_tx_tilemap[1], 0, ms32_tx1_scroll[0x00/4] + ms32_tx1_scroll[0x08/4] + 0x18);
	526	tilemap_set_scrolly(ms32_tx_tilemap[1], 0, ms32_tx1_scroll[0x0c/4] + ms32_tx1_scroll[0x14/4]);
	527	tilemap_draw(bitmap,cliprect,ms32_tx_tilemap[1],0,4);
	528
	529	draw_sprites(machine,bitmap,cliprect, ms32_spram+(0x20000/4), 0x20000, 4);
	530	}
	531
101	532	return 0;
102	533	}
103	534
104	535	INPUT_PORTS_START( bnstars )
	536	PORT_START
	537	PORT_DIPNAME( 0x00000001, 0x00000001, "MAH0" )
	538	PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
	539	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	540	PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
	541	PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
	542	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	543	PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
	544	PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
	545	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	546	PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
	547	PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
	548	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	549	PORT_DIPNAME( 0x00000010, 0x00000010, DEF_STR( Unknown ) )
	550	PORT_DIPSETTING( 0x00000010, DEF_STR( Off ) )
	551	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	552	PORT_DIPNAME( 0x00000020, 0x00000020, DEF_STR( Unknown ) )
	553	PORT_DIPSETTING( 0x00000020, DEF_STR( Off ) )
	554	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	555	PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
	556	PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
	557	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	558	PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
	559	PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
	560	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	561	PORT_DIPNAME( 0x00000100, 0x00000100, DEF_STR( Unknown ) )
	562	PORT_DIPSETTING( 0x00000100, DEF_STR( Off ) )
	563	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	564	PORT_DIPNAME( 0x00000200, 0x00000200, DEF_STR( Unknown ) )
	565	PORT_DIPSETTING( 0x00000200, DEF_STR( Off ) )
	566	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	567	PORT_DIPNAME( 0x00000400, 0x00000400, DEF_STR( Unknown ) )
	568	PORT_DIPSETTING( 0x00000400, DEF_STR( Off ) )
	569	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	570	PORT_DIPNAME( 0x00000800, 0x00000800, DEF_STR( Unknown ) )
	571	PORT_DIPSETTING( 0x00000800, DEF_STR( Off ) )
	572	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	573	PORT_DIPNAME( 0x00001000, 0x00001000, DEF_STR( Unknown ) )
	574	PORT_DIPSETTING( 0x00001000, DEF_STR( Off ) )
	575	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	576	PORT_DIPNAME( 0x00002000, 0x00002000, DEF_STR( Unknown ) )
	577	PORT_DIPSETTING( 0x00002000, DEF_STR( Off ) )
	578	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	579	PORT_DIPNAME( 0x00004000, 0x00004000, DEF_STR( Unknown ) )
	580	PORT_DIPSETTING( 0x00004000, DEF_STR( Off ) )
	581	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	582	PORT_DIPNAME( 0x00008000, 0x00008000, DEF_STR( Unknown ) )
	583	PORT_DIPSETTING( 0x00008000, DEF_STR( Off ) )
	584	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	585	PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_COIN1 )
	586	PORT_DIPNAME( 0x00020000, 0x00020000, "MAH1" )
	587	PORT_DIPSETTING( 0x00020000, DEF_STR( Off ) )
	588	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	589	PORT_DIPNAME( 0x00040000, 0x00040000, DEF_STR( Unknown ) )
	590	PORT_DIPSETTING( 0x00040000, DEF_STR( Off ) )
	591	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	592	PORT_DIPNAME( 0x00080000, 0x00080000, DEF_STR( Unknown ) )
	593	PORT_DIPSETTING( 0x00080000, DEF_STR( Off ) )
	594	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	595	PORT_DIPNAME( 0x00100000, 0x00100000, DEF_STR( Unknown ) )
	596	PORT_DIPSETTING( 0x00100000, DEF_STR( Off ) )
	597	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	598	PORT_DIPNAME( 0x00200000, 0x00200000, DEF_STR( Unknown ) )
	599	PORT_DIPSETTING( 0x00200000, DEF_STR( Off ) )
	600	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	601	PORT_DIPNAME( 0x00400000, 0x00400000, DEF_STR( Unknown ) )
	602	PORT_DIPSETTING( 0x00400000, DEF_STR( Off ) )
	603	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	604	PORT_DIPNAME( 0x00800000, 0x00800000, DEF_STR( Unknown ) )
	605	PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) )
	606	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	607	PORT_DIPNAME( 0x01000000, 0x01000000, DEF_STR( Unknown ) )
	608	PORT_DIPSETTING( 0x01000000, DEF_STR( Off ) )
	609	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	610	PORT_DIPNAME( 0x02000000, 0x02000000, DEF_STR( Unknown ) )
	611	PORT_DIPSETTING( 0x02000000, DEF_STR( Off ) )
	612	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	613	PORT_DIPNAME( 0x04000000, 0x04000000, DEF_STR( Unknown ) )
	614	PORT_DIPSETTING( 0x04000000, DEF_STR( Off ) )
	615	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	616	PORT_DIPNAME( 0x08000000, 0x08000000, DEF_STR( Unknown ) )
	617	PORT_DIPSETTING( 0x08000000, DEF_STR( Off ) )
	618	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	619	PORT_DIPNAME( 0x10000000, 0x10000000, DEF_STR( Unknown ) )
	620	PORT_DIPSETTING( 0x10000000, DEF_STR( Off ) )
	621	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	622	PORT_DIPNAME( 0x20000000, 0x20000000, DEF_STR( Unknown ) )
	623	PORT_DIPSETTING( 0x20000000, DEF_STR( Off ) )
	624	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	625	PORT_DIPNAME( 0x40000000, 0x40000000, DEF_STR( Unknown ) )
	626	PORT_DIPSETTING( 0x40000000, DEF_STR( Off ) )
	627	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	628	PORT_DIPNAME( 0x80000000, 0x80000000, DEF_STR( Unknown ) )
	629	PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
	630	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	631
	632	PORT_START
	633	PORT_DIPNAME( 0x00000001, 0x00000001, "MAH2" )
	634	PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
	635	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	636	PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
	637	PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
	638	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	639	PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
	640	PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
	641	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	642	PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
	643	PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
	644	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	645	PORT_DIPNAME( 0x00000010, 0x00000010, DEF_STR( Unknown ) )
	646	PORT_DIPSETTING( 0x00000010, DEF_STR( Off ) )
	647	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	648	PORT_DIPNAME( 0x00000020, 0x00000020, DEF_STR( Unknown ) )
	649	PORT_DIPSETTING( 0x00000020, DEF_STR( Off ) )
	650	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	651	PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
	652	PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
	653	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	654	PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
	655	PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
	656	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	657	PORT_DIPNAME( 0x00000100, 0x00000100, DEF_STR( Unknown ) )
	658	PORT_DIPSETTING( 0x00000100, DEF_STR( Off ) )
	659	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	660	PORT_DIPNAME( 0x00000200, 0x00000200, DEF_STR( Unknown ) )
	661	PORT_DIPSETTING( 0x00000200, DEF_STR( Off ) )
	662	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	663	PORT_DIPNAME( 0x00000400, 0x00000400, DEF_STR( Unknown ) )
	664	PORT_DIPSETTING( 0x00000400, DEF_STR( Off ) )
	665	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	666	PORT_DIPNAME( 0x00000800, 0x00000800, DEF_STR( Unknown ) )
	667	PORT_DIPSETTING( 0x00000800, DEF_STR( Off ) )
	668	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	669	PORT_DIPNAME( 0x00001000, 0x00001000, DEF_STR( Unknown ) )
	670	PORT_DIPSETTING( 0x00001000, DEF_STR( Off ) )
	671	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	672	PORT_DIPNAME( 0x00002000, 0x00002000, DEF_STR( Unknown ) )
	673	PORT_DIPSETTING( 0x00002000, DEF_STR( Off ) )
	674	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	675	PORT_DIPNAME( 0x00004000, 0x00004000, DEF_STR( Unknown ) )
	676	PORT_DIPSETTING( 0x00004000, DEF_STR( Off ) )
	677	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	678	PORT_DIPNAME( 0x00008000, 0x00008000, DEF_STR( Unknown ) )
	679	PORT_DIPSETTING( 0x00008000, DEF_STR( Off ) )
	680	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	681	PORT_DIPNAME( 0x00010000, 0x00010000, "MAH3" )
	682	PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
	683	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	684	PORT_DIPNAME( 0x00020000, 0x00020000, DEF_STR( Unknown ) )
	685	PORT_DIPSETTING( 0x00020000, DEF_STR( Off ) )
	686	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	687	PORT_DIPNAME( 0x00040000, 0x00040000, DEF_STR( Unknown ) )
	688	PORT_DIPSETTING( 0x00040000, DEF_STR( Off ) )
	689	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	690	PORT_DIPNAME( 0x00080000, 0x00080000, DEF_STR( Unknown ) )
	691	PORT_DIPSETTING( 0x00080000, DEF_STR( Off ) )
	692	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	693	PORT_DIPNAME( 0x00100000, 0x00100000, DEF_STR( Unknown ) )
	694	PORT_DIPSETTING( 0x00100000, DEF_STR( Off ) )
	695	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	696	PORT_DIPNAME( 0x00200000, 0x00200000, DEF_STR( Unknown ) )
	697	PORT_DIPSETTING( 0x00200000, DEF_STR( Off ) )
	698	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	699	PORT_DIPNAME( 0x00400000, 0x00400000, DEF_STR( Unknown ) )
	700	PORT_DIPSETTING( 0x00400000, DEF_STR( Off ) )
	701	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	702	PORT_DIPNAME( 0x00800000, 0x00800000, DEF_STR( Unknown ) )
	703	PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) )
	704	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	705	PORT_DIPNAME( 0x01000000, 0x01000000, DEF_STR( Unknown ) )
	706	PORT_DIPSETTING( 0x01000000, DEF_STR( Off ) )
	707	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	708	PORT_DIPNAME( 0x02000000, 0x02000000, DEF_STR( Unknown ) )
	709	PORT_DIPSETTING( 0x02000000, DEF_STR( Off ) )
	710	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	711	PORT_DIPNAME( 0x04000000, 0x04000000, DEF_STR( Unknown ) )
	712	PORT_DIPSETTING( 0x04000000, DEF_STR( Off ) )
	713	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	714	PORT_DIPNAME( 0x08000000, 0x08000000, DEF_STR( Unknown ) )
	715	PORT_DIPSETTING( 0x08000000, DEF_STR( Off ) )
	716	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	717	PORT_DIPNAME( 0x10000000, 0x10000000, DEF_STR( Unknown ) )
	718	PORT_DIPSETTING( 0x10000000, DEF_STR( Off ) )
	719	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	720	PORT_DIPNAME( 0x20000000, 0x20000000, DEF_STR( Unknown ) )
	721	PORT_DIPSETTING( 0x20000000, DEF_STR( Off ) )
	722	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	723	PORT_DIPNAME( 0x40000000, 0x40000000, DEF_STR( Unknown ) )
	724	PORT_DIPSETTING( 0x40000000, DEF_STR( Off ) )
	725	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	726	PORT_DIPNAME( 0x80000000, 0x80000000, DEF_STR( Unknown ) )
	727	PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
	728	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	729
	730	PORT_START
	731	PORT_DIPNAME( 0x00000001, 0x00000001, "MAH4" )
	732	PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
	733	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	734	PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
	735	PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
	736	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	737	PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
	738	PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
	739	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	740	PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
	741	PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
	742	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	743	PORT_DIPNAME( 0x00000010, 0x00000010, DEF_STR( Unknown ) )
	744	PORT_DIPSETTING( 0x00000010, DEF_STR( Off ) )
	745	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	746	PORT_DIPNAME( 0x00000020, 0x00000020, DEF_STR( Unknown ) )
	747	PORT_DIPSETTING( 0x00000020, DEF_STR( Off ) )
	748	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	749	PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
	750	PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
	751	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	752	PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
	753	PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
	754	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	755	PORT_DIPNAME( 0x00000100, 0x00000100, DEF_STR( Unknown ) )
	756	PORT_DIPSETTING( 0x00000100, DEF_STR( Off ) )
	757	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	758	PORT_DIPNAME( 0x00000200, 0x00000200, DEF_STR( Unknown ) )
	759	PORT_DIPSETTING( 0x00000200, DEF_STR( Off ) )
	760	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	761	PORT_DIPNAME( 0x00000400, 0x00000400, DEF_STR( Unknown ) )
	762	PORT_DIPSETTING( 0x00000400, DEF_STR( Off ) )
	763	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	764	PORT_DIPNAME( 0x00000800, 0x00000800, DEF_STR( Unknown ) )
	765	PORT_DIPSETTING( 0x00000800, DEF_STR( Off ) )
	766	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	767	PORT_DIPNAME( 0x00001000, 0x00001000, DEF_STR( Unknown ) )
	768	PORT_DIPSETTING( 0x00001000, DEF_STR( Off ) )
	769	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	770	PORT_DIPNAME( 0x00002000, 0x00002000, DEF_STR( Unknown ) )
	771	PORT_DIPSETTING( 0x00002000, DEF_STR( Off ) )
	772	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	773	PORT_DIPNAME( 0x00004000, 0x00004000, DEF_STR( Unknown ) )
	774	PORT_DIPSETTING( 0x00004000, DEF_STR( Off ) )
	775	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	776	PORT_DIPNAME( 0x00008000, 0x00008000, DEF_STR( Unknown ) )
	777	PORT_DIPSETTING( 0x00008000, DEF_STR( Off ) )
	778	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	779	PORT_DIPNAME( 0x00010000, 0x00010000, "MAH5" )
	780	PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
	781	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	782	PORT_DIPNAME( 0x00020000, 0x00020000, DEF_STR( Unknown ) )
	783	PORT_DIPSETTING( 0x00020000, DEF_STR( Off ) )
	784	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	785	PORT_DIPNAME( 0x00040000, 0x00040000, DEF_STR( Unknown ) )
	786	PORT_DIPSETTING( 0x00040000, DEF_STR( Off ) )
	787	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	788	PORT_DIPNAME( 0x00080000, 0x00080000, DEF_STR( Unknown ) )
	789	PORT_DIPSETTING( 0x00080000, DEF_STR( Off ) )
	790	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	791	PORT_DIPNAME( 0x00100000, 0x00100000, DEF_STR( Unknown ) )
	792	PORT_DIPSETTING( 0x00100000, DEF_STR( Off ) )
	793	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	794	PORT_DIPNAME( 0x00200000, 0x00200000, DEF_STR( Unknown ) )
	795	PORT_DIPSETTING( 0x00200000, DEF_STR( Off ) )
	796	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	797	PORT_DIPNAME( 0x00400000, 0x00400000, DEF_STR( Unknown ) )
	798	PORT_DIPSETTING( 0x00400000, DEF_STR( Off ) )
	799	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	800	PORT_DIPNAME( 0x00800000, 0x00800000, DEF_STR( Unknown ) )
	801	PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) )
	802	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	803	PORT_DIPNAME( 0x01000000, 0x01000000, DEF_STR( Unknown ) )
	804	PORT_DIPSETTING( 0x01000000, DEF_STR( Off ) )
	805	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	806	PORT_DIPNAME( 0x02000000, 0x02000000, DEF_STR( Unknown ) )
	807	PORT_DIPSETTING( 0x02000000, DEF_STR( Off ) )
	808	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	809	PORT_DIPNAME( 0x04000000, 0x04000000, DEF_STR( Unknown ) )
	810	PORT_DIPSETTING( 0x04000000, DEF_STR( Off ) )
	811	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	812	PORT_DIPNAME( 0x08000000, 0x08000000, DEF_STR( Unknown ) )
	813	PORT_DIPSETTING( 0x08000000, DEF_STR( Off ) )
	814	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	815	PORT_DIPNAME( 0x10000000, 0x10000000, DEF_STR( Unknown ) )
	816	PORT_DIPSETTING( 0x10000000, DEF_STR( Off ) )
	817	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	818	PORT_DIPNAME( 0x20000000, 0x20000000, DEF_STR( Unknown ) )
	819	PORT_DIPSETTING( 0x20000000, DEF_STR( Off ) )
	820	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	821	PORT_DIPNAME( 0x40000000, 0x40000000, DEF_STR( Unknown ) )
	822	PORT_DIPSETTING( 0x40000000, DEF_STR( Off ) )
	823	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	824	PORT_DIPNAME( 0x80000000, 0x80000000, DEF_STR( Unknown ) )
	825	PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
	826	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	827
	828	PORT_START
	829	PORT_DIPNAME( 0x00000001, 0x00000001, "MAH6" )
	830	PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
	831	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	832	PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
	833	PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
	834	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	835	PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
	836	PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
	837	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	838	PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
	839	PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
	840	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	841	PORT_DIPNAME( 0x00000010, 0x00000010, DEF_STR( Unknown ) )
	842	PORT_DIPSETTING( 0x00000010, DEF_STR( Off ) )
	843	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	844	PORT_DIPNAME( 0x00000020, 0x00000020, DEF_STR( Unknown ) )
	845	PORT_DIPSETTING( 0x00000020, DEF_STR( Off ) )
	846	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	847	PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
	848	PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
	849	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	850	PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
	851	PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
	852	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	853	PORT_DIPNAME( 0x00000100, 0x00000100, DEF_STR( Unknown ) )
	854	PORT_DIPSETTING( 0x00000100, DEF_STR( Off ) )
	855	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	856	PORT_DIPNAME( 0x00000200, 0x00000200, DEF_STR( Unknown ) )
	857	PORT_DIPSETTING( 0x00000200, DEF_STR( Off ) )
	858	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	859	PORT_DIPNAME( 0x00000400, 0x00000400, DEF_STR( Unknown ) )
	860	PORT_DIPSETTING( 0x00000400, DEF_STR( Off ) )
	861	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	862	PORT_DIPNAME( 0x00000800, 0x00000800, DEF_STR( Unknown ) )
	863	PORT_DIPSETTING( 0x00000800, DEF_STR( Off ) )
	864	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	865	PORT_DIPNAME( 0x00001000, 0x00001000, DEF_STR( Unknown ) )
	866	PORT_DIPSETTING( 0x00001000, DEF_STR( Off ) )
	867	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	868	PORT_DIPNAME( 0x00002000, 0x00002000, DEF_STR( Unknown ) )
	869	PORT_DIPSETTING( 0x00002000, DEF_STR( Off ) )
	870	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	871	PORT_DIPNAME( 0x00004000, 0x00004000, DEF_STR( Unknown ) )
	872	PORT_DIPSETTING( 0x00004000, DEF_STR( Off ) )
	873	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	874	PORT_DIPNAME( 0x00008000, 0x00008000, DEF_STR( Unknown ) )
	875	PORT_DIPSETTING( 0x00008000, DEF_STR( Off ) )
	876	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	877	PORT_DIPNAME( 0x00010000, 0x00010000, "MAH7" )
	878	PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
	879	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	880	PORT_DIPNAME( 0x00020000, 0x00020000, DEF_STR( Unknown ) )
	881	PORT_DIPSETTING( 0x00020000, DEF_STR( Off ) )
	882	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	883	PORT_DIPNAME( 0x00040000, 0x00040000, DEF_STR( Unknown ) )
	884	PORT_DIPSETTING( 0x00040000, DEF_STR( Off ) )
	885	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	886	PORT_DIPNAME( 0x00080000, 0x00080000, DEF_STR( Unknown ) )
	887	PORT_DIPSETTING( 0x00080000, DEF_STR( Off ) )
	888	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	889	PORT_DIPNAME( 0x00100000, 0x00100000, DEF_STR( Unknown ) )
	890	PORT_DIPSETTING( 0x00100000, DEF_STR( Off ) )
	891	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	892	PORT_DIPNAME( 0x00200000, 0x00200000, DEF_STR( Unknown ) )
	893	PORT_DIPSETTING( 0x00200000, DEF_STR( Off ) )
	894	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	895	PORT_DIPNAME( 0x00400000, 0x00400000, DEF_STR( Unknown ) )
	896	PORT_DIPSETTING( 0x00400000, DEF_STR( Off ) )
	897	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	898	PORT_DIPNAME( 0x00800000, 0x00800000, DEF_STR( Unknown ) )
	899	PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) )
	900	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	901	PORT_DIPNAME( 0x01000000, 0x01000000, DEF_STR( Unknown ) )
	902	PORT_DIPSETTING( 0x01000000, DEF_STR( Off ) )
	903	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	904	PORT_DIPNAME( 0x02000000, 0x02000000, DEF_STR( Unknown ) )
	905	PORT_DIPSETTING( 0x02000000, DEF_STR( Off ) )
	906	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	907	PORT_DIPNAME( 0x04000000, 0x04000000, DEF_STR( Unknown ) )
	908	PORT_DIPSETTING( 0x04000000, DEF_STR( Off ) )
	909	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	910	PORT_DIPNAME( 0x08000000, 0x08000000, DEF_STR( Unknown ) )
	911	PORT_DIPSETTING( 0x08000000, DEF_STR( Off ) )
	912	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	913	PORT_DIPNAME( 0x10000000, 0x10000000, DEF_STR( Unknown ) )
	914	PORT_DIPSETTING( 0x10000000, DEF_STR( Off ) )
	915	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	916	PORT_DIPNAME( 0x20000000, 0x20000000, DEF_STR( Unknown ) )
	917	PORT_DIPSETTING( 0x20000000, DEF_STR( Off ) )
	918	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	919	PORT_DIPNAME( 0x40000000, 0x40000000, DEF_STR( Unknown ) )
	920	PORT_DIPSETTING( 0x40000000, DEF_STR( Off ) )
	921	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	922	PORT_DIPNAME( 0x80000000, 0x80000000, DEF_STR( Unknown ) )
	923	PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
	924	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	925
	926	PORT_START
	927	PORT_DIPNAME( 0x00000001, 0x00000001, "0" )
	928	PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
	929	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	930	PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
	931	PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
	932	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	933	PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
	934	PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
	935	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	936	PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
	937	PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
	938	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	939	PORT_DIPNAME( 0x00000010, 0x00000010, DEF_STR( Unknown ) )
	940	PORT_DIPSETTING( 0x00000010, DEF_STR( Off ) )
	941	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	942	PORT_DIPNAME( 0x00000020, 0x00000020, DEF_STR( Unknown ) )
	943	PORT_DIPSETTING( 0x00000020, DEF_STR( Off ) )
	944	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	945	PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
	946	PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
	947	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	948	PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
	949	PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
	950	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	951	PORT_DIPNAME( 0x00000100, 0x00000100, DEF_STR( Unknown ) )
	952	PORT_DIPSETTING( 0x00000100, DEF_STR( Off ) )
	953	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	954	PORT_DIPNAME( 0x00000200, 0x00000200, DEF_STR( Unknown ) )
	955	PORT_DIPSETTING( 0x00000200, DEF_STR( Off ) )
	956	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	957	PORT_DIPNAME( 0x00000400, 0x00000400, DEF_STR( Unknown ) )
	958	PORT_DIPSETTING( 0x00000400, DEF_STR( Off ) )
	959	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	960	PORT_DIPNAME( 0x00000800, 0x00000800, DEF_STR( Unknown ) )
	961	PORT_DIPSETTING( 0x00000800, DEF_STR( Off ) )
	962	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	963	PORT_DIPNAME( 0x00001000, 0x00001000, DEF_STR( Unknown ) )
	964	PORT_DIPSETTING( 0x00001000, DEF_STR( Off ) )
	965	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	966	PORT_DIPNAME( 0x00002000, 0x00002000, DEF_STR( Unknown ) )
	967	PORT_DIPSETTING( 0x00002000, DEF_STR( Off ) )
	968	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	969	PORT_DIPNAME( 0x00004000, 0x00004000, DEF_STR( Unknown ) )
	970	PORT_DIPSETTING( 0x00004000, DEF_STR( Off ) )
	971	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	972	PORT_DIPNAME( 0x00008000, 0x00008000, DEF_STR( Unknown ) )
	973	PORT_DIPSETTING( 0x00008000, DEF_STR( Off ) )
	974	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	975	PORT_DIPNAME( 0x00010000, 0x00010000, "1" )
	976	PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
	977	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	978	PORT_DIPNAME( 0x00020000, 0x00020000, DEF_STR( Unknown ) )
	979	PORT_DIPSETTING( 0x00020000, DEF_STR( Off ) )
	980	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	981	PORT_DIPNAME( 0x00040000, 0x00040000, DEF_STR( Unknown ) )
	982	PORT_DIPSETTING( 0x00040000, DEF_STR( Off ) )
	983	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	984	PORT_DIPNAME( 0x00080000, 0x00080000, DEF_STR( Unknown ) )
	985	PORT_DIPSETTING( 0x00080000, DEF_STR( Off ) )
	986	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	987	PORT_DIPNAME( 0x00100000, 0x00100000, DEF_STR( Unknown ) )
	988	PORT_DIPSETTING( 0x00100000, DEF_STR( Off ) )
	989	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	990	PORT_DIPNAME( 0x00200000, 0x00200000, DEF_STR( Unknown ) )
	991	PORT_DIPSETTING( 0x00200000, DEF_STR( Off ) )
	992	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	993	PORT_DIPNAME( 0x00400000, 0x00400000, DEF_STR( Unknown ) )
	994	PORT_DIPSETTING( 0x00400000, DEF_STR( Off ) )
	995	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	996	PORT_DIPNAME( 0x00800000, 0x00800000, DEF_STR( Unknown ) )
	997	PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) )
	998	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	999	PORT_DIPNAME( 0x01000000, 0x01000000, DEF_STR( Unknown ) )
	1000	PORT_DIPSETTING( 0x01000000, DEF_STR( Off ) )
	1001	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1002	PORT_DIPNAME( 0x02000000, 0x02000000, DEF_STR( Unknown ) )
	1003	PORT_DIPSETTING( 0x02000000, DEF_STR( Off ) )
	1004	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1005	PORT_DIPNAME( 0x04000000, 0x04000000, DEF_STR( Unknown ) )
	1006	PORT_DIPSETTING( 0x04000000, DEF_STR( Off ) )
	1007	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1008	PORT_DIPNAME( 0x08000000, 0x08000000, DEF_STR( Unknown ) )
	1009	PORT_DIPSETTING( 0x08000000, DEF_STR( Off ) )
	1010	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1011	PORT_DIPNAME( 0x10000000, 0x10000000, DEF_STR( Unknown ) )
	1012	PORT_DIPSETTING( 0x10000000, DEF_STR( Off ) )
	1013	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1014	PORT_DIPNAME( 0x20000000, 0x20000000, DEF_STR( Unknown ) )
	1015	PORT_DIPSETTING( 0x20000000, DEF_STR( Off ) )
	1016	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1017	PORT_DIPNAME( 0x40000000, 0x40000000, DEF_STR( Unknown ) )
	1018	PORT_DIPSETTING( 0x40000000, DEF_STR( Off ) )
	1019	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1020	PORT_DIPNAME( 0x80000000, 0x80000000, DEF_STR( Unknown ) )
	1021	PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
	1022	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1023	PORT_START
	1024	PORT_DIPNAME( 0x00000001, 0x00000001, "2" )
	1025	PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
	1026	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1027	PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
	1028	PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
	1029	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1030	PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
	1031	PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
	1032	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1033	PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
	1034	PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
	1035	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1036	PORT_DIPNAME( 0x00000010, 0x00000010, DEF_STR( Unknown ) )
	1037	PORT_DIPSETTING( 0x00000010, DEF_STR( Off ) )
	1038	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1039	PORT_DIPNAME( 0x00000020, 0x00000020, DEF_STR( Unknown ) )
	1040	PORT_DIPSETTING( 0x00000020, DEF_STR( Off ) )
	1041	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1042	PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
	1043	PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
	1044	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1045	PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
	1046	PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
	1047	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1048	PORT_DIPNAME( 0x00000100, 0x00000100, DEF_STR( Unknown ) )
	1049	PORT_DIPSETTING( 0x00000100, DEF_STR( Off ) )
	1050	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1051	PORT_DIPNAME( 0x00000200, 0x00000200, DEF_STR( Unknown ) )
	1052	PORT_DIPSETTING( 0x00000200, DEF_STR( Off ) )
	1053	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1054	PORT_DIPNAME( 0x00000400, 0x00000400, DEF_STR( Unknown ) )
	1055	PORT_DIPSETTING( 0x00000400, DEF_STR( Off ) )
	1056	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1057	PORT_DIPNAME( 0x00000800, 0x00000800, DEF_STR( Unknown ) )
	1058	PORT_DIPSETTING( 0x00000800, DEF_STR( Off ) )
	1059	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1060	PORT_DIPNAME( 0x00001000, 0x00001000, DEF_STR( Unknown ) )
	1061	PORT_DIPSETTING( 0x00001000, DEF_STR( Off ) )
	1062	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1063	PORT_DIPNAME( 0x00002000, 0x00002000, DEF_STR( Unknown ) )
	1064	PORT_DIPSETTING( 0x00002000, DEF_STR( Off ) )
	1065	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1066	PORT_DIPNAME( 0x00004000, 0x00004000, DEF_STR( Unknown ) )
	1067	PORT_DIPSETTING( 0x00004000, DEF_STR( Off ) )
	1068	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1069	PORT_DIPNAME( 0x00008000, 0x00008000, DEF_STR( Unknown ) )
	1070	PORT_DIPSETTING( 0x00008000, DEF_STR( Off ) )
	1071	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1072	PORT_DIPNAME( 0x00010000, 0x00010000, "3" )
	1073	PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
	1074	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1075	PORT_DIPNAME( 0x00020000, 0x00020000, DEF_STR( Unknown ) )
	1076	PORT_DIPSETTING( 0x00020000, DEF_STR( Off ) )
	1077	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1078	PORT_DIPNAME( 0x00040000, 0x00040000, DEF_STR( Unknown ) )
	1079	PORT_DIPSETTING( 0x00040000, DEF_STR( Off ) )
	1080	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1081	PORT_DIPNAME( 0x00080000, 0x00080000, DEF_STR( Unknown ) )
	1082	PORT_DIPSETTING( 0x00080000, DEF_STR( Off ) )
	1083	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1084	PORT_DIPNAME( 0x00100000, 0x00100000, DEF_STR( Unknown ) )
	1085	PORT_DIPSETTING( 0x00100000, DEF_STR( Off ) )
	1086	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1087	PORT_DIPNAME( 0x00200000, 0x00200000, DEF_STR( Unknown ) )
	1088	PORT_DIPSETTING( 0x00200000, DEF_STR( Off ) )
	1089	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1090	PORT_DIPNAME( 0x00400000, 0x00400000, DEF_STR( Unknown ) )
	1091	PORT_DIPSETTING( 0x00400000, DEF_STR( Off ) )
	1092	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1093	PORT_DIPNAME( 0x00800000, 0x00800000, DEF_STR( Unknown ) )
	1094	PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) )
	1095	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1096	PORT_DIPNAME( 0x01000000, 0x01000000, DEF_STR( Unknown ) )
	1097	PORT_DIPSETTING( 0x01000000, DEF_STR( Off ) )
	1098	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1099	PORT_DIPNAME( 0x02000000, 0x02000000, DEF_STR( Unknown ) )
	1100	PORT_DIPSETTING( 0x02000000, DEF_STR( Off ) )
	1101	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1102	PORT_DIPNAME( 0x04000000, 0x04000000, DEF_STR( Unknown ) )
	1103	PORT_DIPSETTING( 0x04000000, DEF_STR( Off ) )
	1104	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1105	PORT_DIPNAME( 0x08000000, 0x08000000, DEF_STR( Unknown ) )
	1106	PORT_DIPSETTING( 0x08000000, DEF_STR( Off ) )
	1107	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1108	PORT_DIPNAME( 0x10000000, 0x10000000, DEF_STR( Unknown ) )
	1109	PORT_DIPSETTING( 0x10000000, DEF_STR( Off ) )
	1110	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1111	PORT_DIPNAME( 0x20000000, 0x20000000, DEF_STR( Unknown ) )
	1112	PORT_DIPSETTING( 0x20000000, DEF_STR( Off ) )
	1113	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1114	PORT_DIPNAME( 0x40000000, 0x40000000, DEF_STR( Unknown ) )
	1115	PORT_DIPSETTING( 0x40000000, DEF_STR( Off ) )
	1116	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1117	PORT_DIPNAME( 0x80000000, 0x80000000, DEF_STR( Unknown ) )
	1118	PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
	1119	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1120
	1121	PORT_START
	1122	PORT_DIPNAME( 0x00000001, 0x00000001, "4" )
	1123	PORT_DIPSETTING( 0x00000001, DEF_STR( Off ) )
	1124	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1125	PORT_DIPNAME( 0x00000002, 0x00000002, DEF_STR( Unknown ) )
	1126	PORT_DIPSETTING( 0x00000002, DEF_STR( Off ) )
	1127	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1128	PORT_DIPNAME( 0x00000004, 0x00000004, DEF_STR( Unknown ) )
	1129	PORT_DIPSETTING( 0x00000004, DEF_STR( Off ) )
	1130	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1131	PORT_DIPNAME( 0x00000008, 0x00000008, DEF_STR( Unknown ) )
	1132	PORT_DIPSETTING( 0x00000008, DEF_STR( Off ) )
	1133	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1134	PORT_DIPNAME( 0x00000010, 0x00000010, DEF_STR( Unknown ) )
	1135	PORT_DIPSETTING( 0x00000010, DEF_STR( Off ) )
	1136	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1137	PORT_DIPNAME( 0x00000020, 0x00000020, DEF_STR( Unknown ) )
	1138	PORT_DIPSETTING( 0x00000020, DEF_STR( Off ) )
	1139	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1140	PORT_DIPNAME( 0x00000040, 0x00000040, DEF_STR( Unknown ) )
	1141	PORT_DIPSETTING( 0x00000040, DEF_STR( Off ) )
	1142	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1143	PORT_DIPNAME( 0x00000080, 0x00000080, DEF_STR( Unknown ) )
	1144	PORT_DIPSETTING( 0x00000080, DEF_STR( Off ) )
	1145	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1146	PORT_DIPNAME( 0x00000100, 0x00000100, DEF_STR( Unknown ) )
	1147	PORT_DIPSETTING( 0x00000100, DEF_STR( Off ) )
	1148	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1149	PORT_DIPNAME( 0x00000200, 0x00000200, DEF_STR( Unknown ) )
	1150	PORT_DIPSETTING( 0x00000200, DEF_STR( Off ) )
	1151	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1152	PORT_DIPNAME( 0x00000400, 0x00000400, DEF_STR( Unknown ) )
	1153	PORT_DIPSETTING( 0x00000400, DEF_STR( Off ) )
	1154	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1155	PORT_DIPNAME( 0x00000800, 0x00000800, DEF_STR( Unknown ) )
	1156	PORT_DIPSETTING( 0x00000800, DEF_STR( Off ) )
	1157	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1158	PORT_DIPNAME( 0x00001000, 0x00001000, DEF_STR( Unknown ) )
	1159	PORT_DIPSETTING( 0x00001000, DEF_STR( Off ) )
	1160	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1161	PORT_DIPNAME( 0x00002000, 0x00002000, DEF_STR( Unknown ) )
	1162	PORT_DIPSETTING( 0x00002000, DEF_STR( Off ) )
	1163	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1164	PORT_DIPNAME( 0x00004000, 0x00004000, DEF_STR( Unknown ) )
	1165	PORT_DIPSETTING( 0x00004000, DEF_STR( Off ) )
	1166	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1167	PORT_DIPNAME( 0x00008000, 0x00008000, DEF_STR( Unknown ) )
	1168	PORT_DIPSETTING( 0x00008000, DEF_STR( Off ) )
	1169	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1170	PORT_DIPNAME( 0x00010000, 0x00010000, "5" )
	1171	PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
	1172	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1173	PORT_DIPNAME( 0x00020000, 0x00020000, DEF_STR( Unknown ) )
	1174	PORT_DIPSETTING( 0x00020000, DEF_STR( Off ) )
	1175	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1176	PORT_DIPNAME( 0x00040000, 0x00040000, DEF_STR( Unknown ) )
	1177	PORT_DIPSETTING( 0x00040000, DEF_STR( Off ) )
	1178	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1179	PORT_DIPNAME( 0x00080000, 0x00080000, DEF_STR( Unknown ) )
	1180	PORT_DIPSETTING( 0x00080000, DEF_STR( Off ) )
	1181	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1182	PORT_DIPNAME( 0x00100000, 0x00100000, DEF_STR( Unknown ) )
	1183	PORT_DIPSETTING( 0x00100000, DEF_STR( Off ) )
	1184	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1185	PORT_DIPNAME( 0x00200000, 0x00200000, DEF_STR( Unknown ) )
	1186	PORT_DIPSETTING( 0x00200000, DEF_STR( Off ) )
	1187	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1188	PORT_DIPNAME( 0x00400000, 0x00400000, DEF_STR( Unknown ) )
	1189	PORT_DIPSETTING( 0x00400000, DEF_STR( Off ) )
	1190	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1191	PORT_DIPNAME( 0x00800000, 0x00800000, DEF_STR( Unknown ) )
	1192	PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) )
	1193	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1194	PORT_DIPNAME( 0x01000000, 0x01000000, DEF_STR( Unknown ) )
	1195	PORT_DIPSETTING( 0x01000000, DEF_STR( Off ) )
	1196	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1197	PORT_DIPNAME( 0x02000000, 0x02000000, DEF_STR( Unknown ) )
	1198	PORT_DIPSETTING( 0x02000000, DEF_STR( Off ) )
	1199	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1200	PORT_DIPNAME( 0x04000000, 0x04000000, DEF_STR( Unknown ) )
	1201	PORT_DIPSETTING( 0x04000000, DEF_STR( Off ) )
	1202	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1203	PORT_DIPNAME( 0x08000000, 0x08000000, DEF_STR( Unknown ) )
	1204	PORT_DIPSETTING( 0x08000000, DEF_STR( Off ) )
	1205	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1206	PORT_DIPNAME( 0x10000000, 0x10000000, DEF_STR( Unknown ) )
	1207	PORT_DIPSETTING( 0x10000000, DEF_STR( Off ) )
	1208	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1209	PORT_DIPNAME( 0x20000000, 0x20000000, DEF_STR( Unknown ) )
	1210	PORT_DIPSETTING( 0x20000000, DEF_STR( Off ) )
	1211	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1212	PORT_DIPNAME( 0x40000000, 0x40000000, DEF_STR( Unknown ) )
	1213	PORT_DIPSETTING( 0x40000000, DEF_STR( Off ) )
	1214	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
	1215	PORT_DIPNAME( 0x80000000, 0x80000000, DEF_STR( Unknown ) )
	1216	PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
	1217	PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
105	1218	INPUT_PORTS_END
106	1219
107	1220
r1103	r1104
143	1256
144	1257	static GFXDECODE_START( bnstars )
145	1258	GFXDECODE_ENTRY( REGION_GFX1, 0, spritelayout, 0x0000, 0x10 )
	1259	GFXDECODE_ENTRY( REGION_GFX2, 0, bglayout, 0x5000, 0x10 ) /* Roz scr1 */
	1260	GFXDECODE_ENTRY( REGION_GFX4, 0, bglayout, 0x1000, 0x10 ) /* Bg scr1 */
	1261	GFXDECODE_ENTRY( REGION_GFX5, 0, txlayout, 0x6000, 0x10 ) /* Tx scr1 */
146	1262
147		GFXDECODE_ENTRY( REGION_GFX2, 0, bglayout, 0x0000, 0x10 ) /* Roz scr1 */
148		GFXDECODE_ENTRY( REGION_GFX3, 0, bglayout, 0x0000, 0x10 ) /* Roz scr2 */
	1263	GFXDECODE_ENTRY( REGION_GFX1, 0, spritelayout, 0x8000+0x0000, 0x10 )
	1264	GFXDECODE_ENTRY( REGION_GFX3, 0, bglayout, 0x8000+0x5000, 0x10 ) /* Roz scr2 */
	1265	GFXDECODE_ENTRY( REGION_GFX6, 0, bglayout, 0x8000+0x1000, 0x10 ) /* Bg scr2 */
	1266	GFXDECODE_ENTRY( REGION_GFX7, 0, txlayout, 0x8000+0x6000, 0x10 ) /* Tx scr2 */
149	1267
150		GFXDECODE_ENTRY( REGION_GFX4, 0, bglayout, 0x0000, 0x10 ) /* Bg scr1 */
151		GFXDECODE_ENTRY( REGION_GFX5, 0, txlayout, 0x0000, 0x10 ) /* Tx scr1 */
	1268	GFXDECODE_END
152	1269
153		GFXDECODE_ENTRY( REGION_GFX6, 0, bglayout, 0x0000, 0x10 ) /* Bg scr2 */
154		GFXDECODE_ENTRY( REGION_GFX7, 0, txlayout, 0x0000, 0x10 ) /* Tx scr2 */
	1270	static READ32_HANDLER( bnstars1_r )
	1271	{
	1272	switch (bnstars1_mahjong_select & 0x2080)
	1273	{
	1274	default:
	1275	printf("unk bnstars1_r %08x\n",bnstars1_mahjong_select);
	1276	return 0xffffffff;
155	1277
156		GFXDECODE_END
	1278	case 0x0000:
	1279	return readinputport(0);
157	1280
	1281	case 0x0080:
	1282	return readinputport(1);
158	1283
	1284	case 0x2000:
	1285	return readinputport(2);
159	1286
	1287	case 0x2080:
	1288	return readinputport(3);
	1289
	1290	}
	1291	}
	1292
	1293	static READ32_HANDLER( bnstars2_r )
	1294	{
	1295	return readinputport(4);
	1296	}
	1297
	1298	static READ32_HANDLER( bnstars3_r )
	1299	{
	1300	return readinputport(5);
	1301	}
	1302
	1303	static WRITE32_HANDLER( bnstars1_mahjong_select_w )
	1304	{
	1305	bnstars1_mahjong_select = data;
	1306	// printf("%08x\n",bnstars1_mahjong_select);
	1307	}
	1308
160	1309	static ADDRESS_MAP_START( bnstars_map, ADDRESS_SPACE_PROGRAM, 32 )
161	1310	AM_RANGE(0x00000000, 0x001fffff) AM_ROM
	1311
	1312	AM_RANGE(0xfcc00004, 0xfcc00007) AM_READ( bnstars1_r )
	1313	AM_RANGE(0xfcc00008, 0xfcc0000b) AM_READ( bnstars2_r )
	1314	AM_RANGE(0xfcc00010, 0xfcc00013) AM_READ( bnstars3_r )
	1315
	1316	AM_RANGE(0xfce00034, 0xfce00037) AM_WRITE(MWA32_NOP)
	1317
	1318	AM_RANGE(0xfce00050, 0xfce00053) AM_WRITE(MWA32_NOP)
	1319	AM_RANGE(0xfce00058, 0xfce0005b) AM_WRITE(MWA32_NOP)
	1320	AM_RANGE(0xfce0005c, 0xfce0005f) AM_WRITE(MWA32_NOP)
	1321
	1322	AM_RANGE(0xfce00400, 0xfce0045f) AM_WRITE(MWA32_RAM) AM_BASE(&ms32_roz_ctrl[0])
	1323	AM_RANGE(0xfce00700, 0xfce0075f) AM_WRITE(MWA32_RAM) AM_BASE(&ms32_roz_ctrl[1]) // guess
	1324	AM_RANGE(0xfce00a00, 0xfce00a17) AM_WRITE(MWA32_RAM) AM_BASE(&ms32_tx0_scroll)
	1325	AM_RANGE(0xfce00a20, 0xfce00a37) AM_WRITE(MWA32_RAM) AM_BASE(&ms32_bg0_scroll)
	1326	AM_RANGE(0xfce00c00, 0xfce00c17) AM_WRITE(MWA32_RAM) AM_BASE(&ms32_tx1_scroll)
	1327	AM_RANGE(0xfce00c20, 0xfce00c37) AM_WRITE(MWA32_RAM) AM_BASE(&ms32_bg1_scroll)
	1328
	1329	AM_RANGE(0xfce00e00, 0xfce00e03) AM_WRITE(bnstars1_mahjong_select_w) // ?
	1330
	1331	/* wrote together */
	1332	AM_RANGE(0xfd040000, 0xfd047fff) AM_RAM // priority ram
	1333	AM_RANGE(0xfd080000, 0xfd087fff) AM_RAM
	1334	AM_RANGE(0xfd200000, 0xfd237fff) AM_RAM AM_WRITE(ms32_pal1_ram_w) AM_BASE(&ms32_pal_ram[1])
	1335	AM_RANGE(0xfd400000, 0xfd437fff) AM_RAM AM_WRITE(ms32_pal0_ram_w) AM_BASE(&ms32_pal_ram[0])
	1336	AM_RANGE(0xfe000000, 0xfe01ffff) AM_RAM AM_WRITE(ms32_roz1_ram_w) AM_BASE(&ms32_roz1_ram)
	1337	AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM AM_WRITE(ms32_roz0_ram_w) AM_BASE(&ms32_roz0_ram)
	1338	AM_RANGE(0xfe800000, 0xfe83ffff) AM_RAM AM_WRITE(ms32_spramx_w) AM_BASE(&ms32_spram)
	1339	AM_RANGE(0xfea00000, 0xfea07fff) AM_RAM AM_WRITE(ms32_tx1_ram_w) AM_BASE(&ms32_tx1_ram)
	1340	AM_RANGE(0xfea08000, 0xfea0ffff) AM_RAM AM_WRITE(ms32_bg1_ram_w) AM_BASE(&ms32_bg1_ram)
	1341	AM_RANGE(0xfec00000, 0xfec07fff) AM_RAM AM_WRITE(ms32_tx0_ram_w) AM_BASE(&ms32_tx0_ram)
	1342	AM_RANGE(0xfec08000, 0xfec0ffff) AM_RAM AM_WRITE(ms32_bg0_ram_w) AM_BASE(&ms32_bg0_ram)
	1343
	1344	AM_RANGE(0xfee00000, 0xfee1ffff) AM_RAM
162	1345	AM_RANGE(0xffe00000, 0xffffffff) AM_READWRITE(MRA32_BANK1, MWA32_ROM)
163	1346	ADDRESS_MAP_END
164	1347
	1348	#if 0
165	1349	static ADDRESS_MAP_START( bnstars_z80_map, ADDRESS_SPACE_PROGRAM, 8 )
166	1350	AM_RANGE(0x0000, 0x7fff) AM_ROM
167	1351	ADDRESS_MAP_END
	1352	#endif
168	1353
169	1354	static struct YMF271interface ymf271_interface1 =
170	1355	{
r1103	r1104
176	1361	REGION_SOUND2
177	1362	};
178	1363
	1364	static UINT16 irqreq;
	1365
	1366	static int irq_callback(int irqline)
	1367	{
	1368	int i;
	1369	for(i=15; i>=0 && !(irqreq & (1<<i)); i--);
	1370	irqreq &= ~(1<<i);
	1371	if(!irqreq)
	1372	cpunum_set_input_line(0, 0, CLEAR_LINE);
	1373	return i;
	1374	}
	1375
	1376	static void irq_init(void)
	1377	{
	1378	irqreq = 0;
	1379	cpunum_set_input_line(0, 0, CLEAR_LINE);
	1380	cpunum_set_irq_callback(0, irq_callback);
	1381	}
	1382
	1383	static void irq_raise(int level)
	1384	{
	1385	irqreq \|= (1<<level);
	1386	cpunum_set_input_line(0, 0, ASSERT_LINE);
	1387	}
	1388
	1389
	1390	static INTERRUPT_GEN(ms32_interrupt)
	1391	{
	1392	if( cpu_getiloops() == 0 ) irq_raise(10);
	1393	if( cpu_getiloops() == 1 ) irq_raise(9);
	1394	/* hayaosi1 needs at least 12 IRQ 0 per frame to work (see code at FFE02289)
	1395	kirarast needs it too, at least 8 per frame, but waits for a variable amount
	1396	47pi2 needs ?? per frame (otherwise it hangs when you lose)
	1397	in different points. Could this be a raster interrupt?
	1398	Other games using it but not needing it to work:
	1399	desertwr
	1400	p47aces
	1401	*/
	1402	if( cpu_getiloops() >= 3 && cpu_getiloops() <= 32 ) irq_raise(0);
	1403	}
	1404
	1405	static MACHINE_RESET( ms32 )
	1406	{
	1407	irq_init();
	1408	}
	1409
	1410
179	1411	static MACHINE_DRIVER_START( bnstars )
180	1412
181	1413	/* basic machine hardware */
182	1414	MDRV_CPU_ADD(V70, 20000000) // 20MHz
183	1415	MDRV_CPU_PROGRAM_MAP(bnstars_map,0)
184		// MDRV_CPU_VBLANK_INT(ms32_interrupt,32)
	1416	MDRV_CPU_VBLANK_INT(ms32_interrupt,32)
185	1417
186		MDRV_CPU_ADD(Z80, 4000000) /* audio CPU */
187		MDRV_CPU_PROGRAM_MAP(bnstars_z80_map, 0)
	1418	// MDRV_CPU_ADD(Z80, 4000000) /* audio CPU */
	1419	// MDRV_CPU_PROGRAM_MAP(bnstars_z80_map, 0)
188	1420
189	1421	MDRV_INTERLEAVE(1000)
190	1422
191		// MDRV_MACHINE_RESET(ms32)
	1423	MDRV_MACHINE_RESET(ms32)
192	1424
193	1425	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
194	1426	MDRV_GFXDECODE(bnstars)
195		MDRV_PALETTE_LENGTH(0x8000)
	1427	MDRV_PALETTE_LENGTH(0x8000*2)
196	1428
197	1429	MDRV_DEFAULT_LAYOUT(layout_dualhsxs)
198	1430
r1103	r1104
263	1495	ROM_REGION( 0x080000, REGION_GFX5, 0 ) /* tx tiles, don't dispose since we use GFX_RAW */
264	1496	ROM_LOAD( "vsjanshi6.5", 0x000000, 0x080000, CRC(fdbbac21) SHA1(c77d852e53126cc8ebfe1e79d1134e42b54d1aab) )
265	1497
266		/* BG Tiles #2 (Screen 1?) */
	1498	/* BG Tiles #2 (Screen 2?) */
267	1499	ROM_REGION( 0x200000, REGION_GFX6, 0 ) /* bg tiles, don't dispose since we use GFX_RAW */
268	1500	ROM_LOAD( "mr96004-11.13", 0x000000, 0x200000, CRC(e6da552c) SHA1(69a5af3015883793c7d1343243ccae23db9ef77c) )
269	1501

src/mame/drivers/mirage.c
r1103	r1104
392	392	ROM_LOAD16_BYTE( "mbl-02.12a", 0x000000, 0x200000, CRC(474f6104) SHA1(ff81b32b90192c3d5f27c436a9246aa6caaeeeee) )
393	393
394	394	ROM_REGION( 0x200000, REGION_SOUND1, 0 ) /* M6295 samples (scrambled? bad?) */
395		ROM_LOAD( "mbl-03.10a", 0x000000, 0x200000, CRC(afccbc3c) SHA1(457b7fbd22e723e69b65a989ee9957354b673176) )
	395	ROM_LOAD( "mbl-03.10a", 0x000000, 0x200000, BAD_DUMP CRC(afccbc3c) SHA1(457b7fbd22e723e69b65a989ee9957354b673176) ) // dumped in wrong mode, missing every other byte
396	396
397	397	ROM_REGION( 0x200000, REGION_SOUND2, 0 ) /* M6295 samples */
398	398	ROM_LOAD( "mbl-04.12k", 0x000000, 0x100000, CRC(b533123d) SHA1(2cb2f11331d00c2d282113932ed2836805f4fc6e) )

src/mame/drivers/jack.c
r1103	r1104
683	683	PORT_SERVICE( 0x80, IP_ACTIVE_HIGH )
684	684	INPUT_PORTS_END
685	685
	686	INPUT_PORTS_START( loverboy )
	687	PORT_START
	688	PORT_DIPNAME( 0x0f, 0x00, DEF_STR( Coin_A ) )
	689	PORT_DIPSETTING( 0x0c, DEF_STR( 4C_1C ) )
	690	PORT_DIPSETTING( 0x08, DEF_STR( 3C_1C ) )
	691	PORT_DIPSETTING( 0x0d, DEF_STR( 4C_2C ) )
	692	PORT_DIPSETTING( 0x04, DEF_STR( 2C_1C ) )
	693	PORT_DIPSETTING( 0x09, DEF_STR( 3C_2C ) )
	694	PORT_DIPSETTING( 0x0e, DEF_STR( 4C_3C ) )
	695	PORT_DIPSETTING( 0x0f, DEF_STR( 4C_4C ) )
	696	PORT_DIPSETTING( 0x0a, DEF_STR( 3C_3C ) )
	697	PORT_DIPSETTING( 0x05, DEF_STR( 2C_2C ) )
	698	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
	699	PORT_DIPSETTING( 0x0b, DEF_STR( 3C_4C ) )
	700	PORT_DIPSETTING( 0x06, DEF_STR( 2C_3C ) )
	701	PORT_DIPSETTING( 0x07, DEF_STR( 2C_4C ) )
	702	PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) )
	703	PORT_DIPSETTING( 0x02, DEF_STR( 1C_3C ) )
	704	PORT_DIPSETTING( 0x03, DEF_STR( 1C_4C ) )
	705	PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
	706	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	707	PORT_DIPSETTING( 0x10, DEF_STR( On ) )
	708	PORT_DIPNAME( 0x20, 0x00, "Bonus" )
	709	PORT_DIPSETTING( 0x00, "20.000" )
	710	PORT_DIPSETTING( 0x20, "30.000" )
	711	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Lives ) )
	712	PORT_DIPSETTING( 0x00, "3" )
	713	PORT_DIPSETTING( 0x40, "5" )
	714	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Cabinet ) )
	715	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
	716	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
	717
	718	PORT_START
	719	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ) )
	720	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	721	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
	722	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
	723	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	724	PORT_DIPSETTING( 0x02, DEF_STR( On ) )
	725	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
	726	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	727	PORT_DIPSETTING( 0x04, DEF_STR( On ) )
	728	PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
	729	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	730	PORT_DIPSETTING( 0x08, DEF_STR( On ) )
	731	PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
	732	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	733	PORT_DIPSETTING( 0x10, DEF_STR( On ) )
	734	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
	735	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	736	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
	737	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
	738	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	739	PORT_DIPSETTING( 0x40, DEF_STR( On ) )
	740	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
	741	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	742	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
	743
	744	PORT_START
	745	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY
	746	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY
	747	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY
	748	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY
	749	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )
	750	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	751	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	752	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	753
	754	PORT_START
	755	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
	756	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
	757	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
	758	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
	759	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL
	760	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	761	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	762	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	763
	764	PORT_START
	765	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
	766	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )
	767	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START1 )
	768	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START2 )
	769	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	770	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	771	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SPECIAL ) // otherwise it doesn't boot because the code is buggy
	772	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	773	INPUT_PORTS_END
	774
686	775	INPUT_PORTS_START( striv )
687	776	PORT_START_TAG("DSW1")
688	777	PORT_DIPNAME( 0x02, 0x00, "Monitor" )
r1103	r1104
1385	1474	GAME( 1981, tripool, 0, tripool, tripool, jack, ROT90, "Noma (Casino Tech license)", "Tri-Pool (Casino Tech)", 0 )
1386	1475	GAME( 1981, tripoola, tripool, tripool, tripool, jack, ROT90, "Noma (Costal Games license)", "Tri-Pool (Costal Games)", 0 )
1387	1476	GAME( 1986, joinem, 0, joinem, joinem, zzyzzyxx, ROT90, "Global Corporation", "Joinem", 0 )
1388		GAME( 1983, loverboy, 0, loverboy,joinem, loverboy, ROT90, "G~~lobal~~ Corporation", "Loverboy", 0 )
	1477	GAME( 1983, loverboy, 0, loverboy,loverboy, loverboy, ROT90, "G.T Enterprise Inc", "Lover Boy", 0 )
1389	1478	GAME( 1985, striv, 0, jack, striv, striv, ROT270,"Hara Industries", "Super Triv", GAME_IMPERFECT_SOUND \| GAME_IMPERFECT_COLORS )

src/mame/drivers/gtipoker.c
r0	r1104
	1	/* Has (c)1983 GTI in the roms, and was called 'Poker.zip' GFX roms contain 16x16 tiles of cards */
	2	/* Nothing else is known about this set / game */
	3
	4	#include "driver.h"
	5
	6	static VIDEO_START(gtipoker)
	7	{
	8
	9	}
	10
	11	static VIDEO_UPDATE(gtipoker)
	12	{
	13	return 0;
	14	}
	15
	16	static READ8_HANDLER( gtipoker_unk_r )
	17	{
	18	return mame_rand(Machine);
	19	}
	20
	21	static ADDRESS_MAP_START( gtipoker_memmap, ADDRESS_SPACE_PROGRAM, 8 )
	22	AM_RANGE(0x0000, 0x1fff) AM_ROM
	23	AM_RANGE(0xd000, 0xdfff) AM_RAM
	24	ADDRESS_MAP_END
	25
	26	static ADDRESS_MAP_START( gtipoker_iomap, ADDRESS_SPACE_IO, 8 )
	27	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
	28	AM_RANGE(0xbc, 0xbc) AM_READ(gtipoker_unk_r)
	29	AM_RANGE(0xbe, 0xbe) AM_READ(gtipoker_unk_r)
	30	AM_RANGE(0xde, 0xde) AM_READ(gtipoker_unk_r)
	31	AM_RANGE(0xef, 0xef) AM_READ(gtipoker_unk_r)
	32	AM_RANGE(0xfd, 0xfd) AM_READ(gtipoker_unk_r)
	33	ADDRESS_MAP_END
	34
	35
	36	INPUT_PORTS_START( gtipoker )
	37	INPUT_PORTS_END
	38
	39	static const gfx_layout tiles8x8_layout =
	40	{
	41	16,16,
	42	RGN_FRAC(1,1),
	43	1,
	44	{ 0 },
	45	{ 0, 1, 2, 3, 4, 5, 6, 7,8,9,10,11,12,13,14,15 },
	46	{ 016, 116, 216, 316, 416, 516, 616, 716,816,916,1016,1116,1216,1316,1416,1516 },
	47	16*16
	48	};
	49
	50	static GFXDECODE_START( gtipoker )
	51	GFXDECODE_ENTRY( REGION_GFX1, 0, tiles8x8_layout, 0, 16 )
	52	GFXDECODE_END
	53
	54
	55	static MACHINE_DRIVER_START( gtipoker )
	56	/* basic machine hardware */
	57	MDRV_CPU_ADD(Z80,4000000) /* ? MHz */
	58	MDRV_CPU_PROGRAM_MAP(gtipoker_memmap,0)
	59	MDRV_CPU_IO_MAP(gtipoker_iomap,0)
	60	MDRV_CPU_VBLANK_INT(irq0_line_hold,1)
	61
	62	MDRV_SCREEN_REFRESH_RATE(60)
	63	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
	64
	65	/* video hardware */
	66	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER )
	67	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
	68	MDRV_SCREEN_SIZE(256, 256)
	69	MDRV_SCREEN_VISIBLE_AREA(0, 256-1, 16, 256-16-1)
	70	MDRV_GFXDECODE(gtipoker)
	71	MDRV_PALETTE_LENGTH(0x100)
	72
	73	MDRV_VIDEO_START(gtipoker)
	74	MDRV_VIDEO_UPDATE(gtipoker)
	75	MACHINE_DRIVER_END
	76
	77
	78	ROM_START( gtipoker )
	79	ROM_REGION( 0x10000, REGION_CPU1, 0 )
	80	ROM_LOAD( "u12.rom", 0x0000, 0x1000, CRC(abaa257a) SHA1(f830213ae0aaad5a9a44ec77c5a186e9e02fa041) )
	81	ROM_LOAD( "u18.rom", 0x1000, 0x1000, CRC(1b7e2877) SHA1(717fb70889804baa468203f20b1e7f73b55cc21e) )
	82
	83	ROM_REGION( 0x1000, REGION_GFX1, 0 )
	84	ROM_LOAD( "u31.rom", 0x0000, 0x1000, CRC(2028db2c) SHA1(0f81bb71e88c60df3817f58c28715ce2ea01ad4d) )
	85	ROM_END
	86
	87	GAME( 1983, gtipoker, 0, gtipoker, gtipoker, 0, ROT0, "GTI Inc", "GTI Poker", GAME_NOT_WORKING\|GAME_NO_SOUND )

src/mame/drivers/srmp2.c
r1103	r1104
1229	1229
1230	1230	ROM_START( srmp1 )
1231	1231	ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 68000 Code */
1232		ROM_LOAD16_BYTE( "ub0-2.17", 0x000000, 0x20000, BAD_DUMP CRC(b88dbeba) SHA1(b4120c09aba6b6696148480f55aeee2f4a82b504) ) // 1ST AND 2ND HALF IDENTICAL
1233		ROM_LOAD16_BYTE( "ub0-3.18", 0x000001, 0x20000, BAD_DUMP CRC(6302cfa8) SHA1(214834437c996816e8f63e98f990dc8bce49643a) ) // 1ST AND 2ND HALF IDENTICAL
	1232	ROM_LOAD16_BYTE( "ub0-2.17", 0x000000, 0x20000, CRC(71a00a3d) SHA1(8deb07a4621e0f0f1d6dd503cd7f4f826a63c255) )
	1233	ROM_LOAD16_BYTE( "ub0-3.18", 0x000001, 0x20000, CRC(2950841b) SHA1(1859636602375b4cadbd23457a0d16bc85063ff5) )
1234	1234
1235	1235	ROM_REGION( 0x200000, REGION_GFX1, ROMREGION_DISPOSE ) /* Sprites */
1236		ROM_LOAD ( "ubo-4.60", 0x000000, 0x040000, CRC(cb6f7cce) SHA1(27d7c2f4f998023081fac1bbacfd4b0b56edaee2) )
	1236	ROM_LOAD16_BYTE( "ub0-8.64", 0x000000, 0x008000, CRC(b58024b9) SHA1(d38750fa90c1b14288884a3c2713b90f0b941bfb) )
	1237	ROM_LOAD16_BYTE( "ub0-9.65", 0x000001, 0x008000, CRC(e28c2566) SHA1(91ce9d7138e05f9bcd31dfeaaa558d4431ae9515) )
1237	1238	ROM_LOAD ( "ubo-5.61", 0x040000, 0x040000, CRC(7b48c540) SHA1(06229caec6846581f95409204ea22f0f76684b08) )
1238		ROM_LOAD16_BYTE( "ub0-8.64", 0x080000, 0x008000, CRC(b58024b9) SHA1(d38750fa90c1b14288884a3c2713b90f0b941bfb) )
1239		ROM_LOAD16_BYTE( "ub0-9.65", 0x080001, 0x008000, CRC(e28c2566) SHA1(91ce9d7138e05f9bcd31dfeaaa558d4431ae9515) )
1240		ROM_LOAD ( "ubo-6.62", 0x100000, 0x040000, CRC(6c891ac5) SHA1(eab595bce16e4cdc465a5e2e029c3949a0f28629) )
	1239	ROM_LOAD ( "ubo-4.60", 0x080000, 0x040000, CRC(cb6f7cce) SHA1(27d7c2f4f998023081fac1bbacfd4b0b56edaee2) )
	1240	ROM_LOAD16_BYTE( "ub0-10.66", 0x100000, 0x008000, CRC(d20a935c) SHA1(1d01b0ccfb6c2ea226e16e555796acd10b10e835) )
	1241	ROM_LOAD16_BYTE( "ub0-11.67", 0x100001, 0x008000, CRC(30957ca8) SHA1(02aaa3f2f266e8f4db2d35c177546365d7836004) )
1241	1242	ROM_LOAD ( "ubo-7.63", 0x140000, 0x040000, CRC(60a45755) SHA1(22bbf024bbe2186b621389a23697e55d512b501a) )
1242		ROM_LOAD16_BYTE( "ub0-10.66", 0x180000, 0x008000, CRC(d20a935c) SHA1(1d01b0ccfb6c2ea226e16e555796acd10b10e835) )
1243		ROM_LOAD16_BYTE( "ub0-11.67", 0x180001, 0x008000, CRC(30957ca8) SHA1(02aaa3f2f266e8f4db2d35c177546365d7836004) )
	1243	ROM_LOAD ( "ubo-6.62", 0x180000, 0x040000, CRC(6c891ac5) SHA1(eab595bce16e4cdc465a5e2e029c3949a0f28629) )
1244	1244
1245	1245	ROM_REGION( 0x020000, REGION_SOUND1, 0 ) /* Samples */
1246		ROM_LOAD( "ub0-1.19", 0x000000, 0x20000, CRC(a5~~96066~~1) SHA1(~~76e7a5~~8276a7a~~e245~~b~~be2~~6~~6b50~~c~~efa7d~~0304~~3f77~~) ) ~~// 1ST AND 2ND HALF IDENTICAL~~
	1246	ROM_LOAD( "ub0-1.19", 0x000000, 0x20000, CRC(5f21b48c) SHA1(1838632609c176dbaab1d88f9368c03259a5e954) )
1247	1247
1248	1248	ROM_REGION( 0x800, REGION_PROMS, 0 ) /* Color PROMs */
1249	1249	ROM_LOAD( "ub1.12", 0x000, 0x200, CRC(d2ed93c8) SHA1(334d4fe6fa477758b336b138ffc306e2d6334371) )
r1103	r1104
1377	1377	ROM_END
1378	1378
1379	1379
1380		GAME( 1987, srmp1, 0, srmp2, srmp2, 0, ROT0, "Seta", "Super Real Mahjong Part 1 (Japan)", ~~GAME_NOT_WORKING~~ )
	1380	GAME( 1987, srmp1, 0, srmp2, srmp2, 0, ROT0, "Seta", "Super Real Mahjong Part 1 (Japan)", 0 )
1381	1381	GAME( 1987, srmp2, 0, srmp2, srmp2, srmp2, ROT0, "Seta", "Super Real Mahjong Part 2 (Japan)", 0 )
1382	1382	GAME( 1988, srmp3, 0, srmp3, srmp3, srmp3, ROT0, "Seta", "Super Real Mahjong Part 3 (Japan)", 0 )
1383	1383	GAME( 1990, mjyuugi, 0, mjyuugi, mjyuugi, 0, ROT0, "Visco", "Mahjong Yuugi (Japan set 1)", 0 )

src/mame/drivers/igs_180.c
r1103	r1104
351	351	decrypt_program_rom(0x05, 7, 6, 3, 2, 5, 4, 1, 0);
352	352	}
353	353
354		GAME( 1996, iqblocka, iqblock, igs_180, igs_180, iqblock, ROT0, "IGS", "IQ-Block (V127M)", 0)//GAME_NOT_WORKING )
355		GAME( 1996, iqblockf, iqblock, igs_180, igs_180, iqblock, ROT0, "IGS", "IQ-Block (V113FR)", 0)//GAME_NOT_WORKING )
356		GAME( 1997, tjsb, 0, igs_180, igs_180, tjsb, ROT0, "IGS", "Mahjong Tian Jiang Shen Bing", 0)//GAME_NOT_WORKING )
	354	GAME( 1996, iqblocka, iqblock, igs_180, igs_180, iqblock, ROT0, "IGS", "IQ-Block (V127M)", GAME_NOT_WORKING )
	355	GAME( 1996, iqblockf, iqblock, igs_180, igs_180, iqblock, ROT0, "IGS", "IQ-Block (V113FR)", GAME_NOT_WORKING )
	356	GAME( 1997, tjsb, 0, igs_180, igs_180, tjsb, ROT0, "IGS", "Mahjong Tian Jiang Shen Bing", GAME_NOT_WORKING )

src/mame/drivers/playch10.c
r1103	r1104
666	666	PORT_DIPSETTING( 0x80, DEF_STR( Free_Play ) )
667	667
668	668	PORT_START_TAG("IN0")
669		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P1 Button A")
670		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P1 Button B")
	669	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P1 Button B")
	670	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P1 Button A")
671	671	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START1 ) PORT_NAME("Game Select") PORT_CODE(KEYCODE_1)
672	672	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START2 ) PORT_NAME("Start") PORT_CODE(KEYCODE_2)
673	673	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )

src/mame/drivers/rastan.c
r1103	r1104
511	511	ROM_END
512	512
513	513	ROM_START( rastsaga )
514		ROM_REGION( 0x60000, REGION_CPU1, 0 ) /* 664k for 68000 code /
515		ROM_LOAD16_BYTE( "rs19_38.bin", 0x00000, 0x10000, CRC(a38ac909) SHA1(66d792fee03c6bd87d15060b9d5cae74137c5ebd) )
516		ROM_LOAD16_BYTE( "rs07_37.bin", 0x00001, 0x10000, CRC(bad60872) SHA1(e020f79b3ac3d2abccfcd5d135d2dc49e1335c7d) )
517		ROM_LOAD16_BYTE( "rs20_40.bin", 0x20000, 0x10000, CRC(6bcf70dc) SHA1(3e369548ac01981c503150b44c2747e6c2cec12a) )
518		ROM_LOAD16_BYTE( "rs08_39.bin", 0x20001, 0x10000, CRC(8838ecc5) SHA1(42b43ab77969bbacdf178fbe73a0a27652ccb297) )
519		ROM_LOAD16_BYTE( "rs21_42.bin", 0x40000, 0x10000, CRC(b626c439) SHA1(976e820edc4ba107c5b579edaaee1e354e85fb67) )
520		ROM_LOAD16_BYTE( "rs09_43.bin", 0x40001, 0x10000, CRC(c928a516) SHA1(fe87fdf2d1b7ba93e1986460eb6af648b58f42e4) )
	514	ROM_REGION( 0x60000, REGION_CPU1, 0 ) /* 664k for 68000 code /
	515	ROM_LOAD16_BYTE( "b04-38.19", 0x00000, 0x10000, CRC(a38ac909) SHA1(66d792fee03c6bd87d15060b9d5cae74137c5ebd) )
	516	ROM_LOAD16_BYTE( "b04-37.7", 0x00001, 0x10000, CRC(bad60872) SHA1(e020f79b3ac3d2abccfcd5d135d2dc49e1335c7d) )
	517	ROM_LOAD16_BYTE( "b04-40.20", 0x20000, 0x10000, CRC(6bcf70dc) SHA1(3e369548ac01981c503150b44c2747e6c2cec12a) )
	518	ROM_LOAD16_BYTE( "b04-39.8", 0x20001, 0x10000, CRC(8838ecc5) SHA1(42b43ab77969bbacdf178fbe73a0a27652ccb297) )
	519	ROM_LOAD16_BYTE( "b04-42.21", 0x40000, 0x10000, CRC(b626c439) SHA1(976e820edc4ba107c5b579edaaee1e354e85fb67) )
	520	ROM_LOAD16_BYTE( "b04-43.9", 0x40001, 0x10000, CRC(c928a516) SHA1(fe87fdf2d1b7ba93e1986460eb6af648b58f42e4) )
521	521
522	522	ROM_REGION( 0x1c000, REGION_CPU2, 0 )
523	523	ROM_LOAD( "b04-19.49", 0x00000, 0x4000, CRC(ee81fdd8) SHA1(fa59dac2583a7d2979550dffc6f9c6c2bd67bfd5) )

src/mame/drivers/gijoe.c
r1103	r1104
328	328	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
329	329	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
330	330	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
331		PORT_DIPUNUSED( 0x0080, IP_ACTIVE_LOW )
	331	PORT_DIPUNUSED( 0x8000, IP_ACTIVE_LOW )
332	332	INPUT_PORTS_END
333	333
334	334	static struct K054539interface k054539_interface =

src/mame/drivers/halleys.c
r1103	r1104
201	201	#define CLIP_H (VIS_MAXY - VIS_MINY + 1)
202	202	#define CLIP_BYTEW (CLIP_W << 1)
203	203
204		typedef UINT8 BYTE;
205		typedef UINT16 WORD;
206		typedef UINT32 DWORD;
	204	static UINT16 *render_layer[MAX_LAYERS];
	205	static UINT8 sound_fifo[MAX_SOUNDS];
	206	static UINT8 gfx_plane02, gfx_plane13, *collision_list;
	207	static UINT8 scrolly0, scrollx0, scrolly1, scrollx1;
	208	static UINT32 internal_palette, alpha_table;
207	209
208		static WORD *render_layer[MAX_LAYERS];
209		static BYTE sound_fifo[MAX_SOUNDS];
210		static BYTE gfx_plane02, gfx_plane13, *collision_list;
211		static BYTE scrolly0, scrollx0, scrolly1, scrollx1;
212		static DWORD internal_palette, alpha_table;
213
214		static BYTE cpu1_base, gfx1_base, blitter_ram, io_ram;
	210	static UINT8 cpu1_base, gfx1_base, blitter_ram, io_ram;
215	211	static size_t blitter_ramsize, io_ramsize;
216	212
217	213	static int game_id, blitter_busy, collision_count, stars_enabled, bgcolor, ffcount, ffhead, fftail;
r1103	r1104
291	287	#define XMASK (SCREEN_WIDTH-1)
292	288	#define YMASK (SCREEN_HEIGHT-1)
293	289
294		static BYTE penxlat[16]={0x03,0x07,0x0b,0x0f,0x02,0x06,0x0a,0x0e,0x01,0x05,0x09,0x0d,0x00,0x04,0x08,0x0c};
295		static BYTE rgbmask[16]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0xff,0xff,0xff,0xff};
296		static BYTE tyremap[ 8]={ 0, 5, 9,13,16,20,24,28};
	290	static UINT8 penxlat[16]={0x03,0x07,0x0b,0x0f,0x02,0x06,0x0a,0x0e,0x01,0x05,0x09,0x0d,0x00,0x04,0x08,0x0c};
	291	static UINT8 rgbmask[16]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0xff,0xff,0xff,0xff};
	292	static UINT8 tyremap[ 8]={ 0, 5, 9,13,16,20,24,28};
297	293
298		BYTE param, src_base;
299		WORD *dst_base;
	294	UINT8 param, src_base;
	295	UINT16 *dst_base;
300	296	int stptr, mode, color, code, y, x, h, w, src1, src2;
301	297	int status, flags, group, command, bank, layer, pen0, pen1;
302	298	int yclip, xclip, src_yskip, src_xskip, dst_skip, hclip, wclip, src_dy, src_dx;
303		DWORD *pal_ptr;
304		BYTE src1_ptr, src2_ptr; // esi alias, ebx alias
305		WORD *dst_ptr; // edi alias
	299	UINT32 *pal_ptr;
	300	UINT8 src1_ptr, src2_ptr; // esi alias, ebx alias
	301	UINT16 *dst_ptr; // edi alias
306	302	void *edi; // scratch
307	303	int eax, ebx, ecx, edx; // scratch
308		~~WORD~~ ax; BYTE al, ah; // partial regs
	304	UINT16 ax; UINT8 al, ah; // partial regs
309	305
310	306
311	307	param = blitter_ram + offset;
r1103	r1104
429	425	if (src1 == src2)
430	426	{
431	427	flags \|= SINGLE_PEN;
432		eax = (~~DWORD~~)penxlat[color & PENCOLOR];
	428	eax = (UINT32)penxlat[color & PENCOLOR];
433	429	if (eax) pen1 = pen0 + eax;
434	430	}
435	431	else if (color & PENCOLOR) flags \|= RGB_MASK;
r1103	r1104
441	437	eax = wclip<<1; \
442	438	ecx = hclip; \
443	439	edi = dst_ptr; \
444		do { memset((BYTE)edi, 0, eax); edi = (BYTE)edi + SCREEN_BYTEWIDTH; } while (--ecx); }
	440	do { memset((UINT8)edi, 0, eax); edi = (UINT8)edi + SCREEN_BYTEWIDTH; } while (--ecx); }
445	441
446	442	//--------------------------------------------------------------------------
447	443
r1103	r1104
456	452
457	453	if (flags & PPCD_ON) goto COLLISION_MODE;
458	454
459		al = ah = (BYTE)pen0;
	455	al = ah = (UINT8)pen0;
460	456
461	457	if (!(flags & BACKMODE))
462	458	{
r1103	r1104
466	462	src1_ptr += edx;
467	463	al \|= *src2_ptr;
468	464	src2_ptr += edx;
469		if (al & 0xf) { dst_ptr[ecx] = (~~WORD~~)al; al = ah;}
	465	if (al & 0xf) { dst_ptr[ecx] = (UINT16)al; al = ah;}
470	466	}
471	467	while (++ecx);
472	468	ecx = wclip; src1_ptr += src_dy; src2_ptr += src_dy; dst_ptr += SCREEN_WIDTH;
r1103	r1104
481	477	src1_ptr += edx;
482	478	al \|= *src2_ptr;
483	479	src2_ptr += edx;
484		if (al & 0xf) { dst_ptr[ecx] = (~~WORD~~)al \| SP_2BACK; al = ah; }
	480	if (al & 0xf) { dst_ptr[ecx] = (UINT16)al \| SP_2BACK; al = ah; }
485	481	}
486	482	while (++ecx);
487	483	ecx = wclip; src1_ptr += src_dy; src2_ptr += src_dy; dst_ptr += SCREEN_WIDTH;
r1103	r1104
502	498	src1_ptr += edx;
503	499	al \|= *src2_ptr;
504	500	src2_ptr += edx;
505		if (al & 0xf) { dst_ptr[ecx] = (~~WORD~~)al \| SP_COLLD; } // set collision flag on group one pixels
	501	if (al & 0xf) { dst_ptr[ecx] = (UINT16)al \| SP_COLLD; } // set collision flag on group one pixels
506	502	}
507	503	while (++ecx);
508	504	ecx = wclip; src1_ptr += src_dy; src2_ptr += src_dy; dst_ptr += SCREEN_WIDTH;
r1103	r1104
517	513	src1_ptr += edx;
518	514	al \|= *src2_ptr;
519	515	src2_ptr += edx;
520		if (al & 0xf) { ax \|= dst_ptr[ecx]; dst_ptr[ecx] = (~~WORD~~)al; } // combine collision flags in ax
	516	if (al & 0xf) { ax \|= dst_ptr[ecx]; dst_ptr[ecx] = (UINT16)al; } // combine collision flags in ax
521	517	}
522	518	while (++ecx);
523	519	ecx = wclip; src1_ptr += src_dy; src2_ptr += src_dy; dst_ptr += SCREEN_WIDTH;
r1103	r1104
547	543
548	544	dst_ptr += wclip;
549	545	ecx = wclip = -wclip;
550		al = ah = (BYTE)pen0;
	546	al = ah = (UINT8)pen0;
551	547	ebx = rgbmask[color & PENCOLOR] \| 0xffffff00;
552	548
553	549	do {
r1103	r1104
556	552	src1_ptr += src_dx;
557	553	al \|= *src2_ptr;
558	554	src2_ptr += src_dx;
559		if (al & 0xf) { edx = (~~DWORD~~)al; al = ah; dst_ptr[ecx] = pal_ptr[edx] & ebx; }
	555	if (al & 0xf) { edx = (UINT32)al; al = ah; dst_ptr[ecx] = pal_ptr[edx] & ebx; }
560	556	}
561	557	while (++ecx);
562	558	ecx = wclip; src1_ptr += src_dy; src2_ptr += src_dy; dst_ptr += SCREEN_WIDTH;
r1103	r1104
576	572	ebx = hclip;
577	573	ecx = wclip = -wclip;
578	574	edx = src_dx;
579		ax = (~~WORD~~)pen1;
	575	ax = (UINT16)pen1;
580	576
581	577	do {
582	578	do {
r1103	r1104
746	742	for (yclip=y+h; y<yclip; y+=16)
747	743	for (xclip=x+w; x<xclip; x+=16)
748	744	{
749		edx = (~~DWORD~~)*src2_ptr;
	745	edx = (UINT32)*src2_ptr;
750	746	src2_ptr++;
751	747	if (edx)
752	748	{
753		ax = (WORD)*(src2_ptr-0x100 -1);
754		ebx = (DWORD)ax;
	749	ax = (UINT16)*(src2_ptr-0x100 -1);
	750	ebx = (UINT32)ax;
755	751	ax \|= BG_MONO;
756	752	if (edx & 0x01) { dst_base[C2S(x,y,ebx)] = ax; }
757	753	if (edx & 0x02) { ecx = RORB(ebx,1); dst_base[C2S(x,y,ecx)] = ax; }
r1103	r1104
779	775	edx = SCREEN_WIDTH - x - w;
780	776	w = -w;
781	777
782		ax = (~~WORD~~)(~src_base[src2] & 0xff);
	778	ax = (UINT16)(~src_base[src2] & 0xff);
783	779
784	780	for (yclip=y+h; y<yclip; y++)
785	781	{
r1103	r1104
788	784	if (edx < 0)
789	785	{
790	786	ecx = edx;
791		dst_ptr = (~~WORD~~*)edi - edx;
	787	dst_ptr = (UINT16*)edi - edx;
792	788	do { if (dst_ptr[ecx]) dst_ptr[ecx] ^= ax; } while (++ecx);
793	789	ecx = x - SCREEN_WIDTH;
794	790	} else ecx = w;
795	791
796		dst_ptr = (~~WORD~~*)edi + x - ecx;
	792	dst_ptr = (UINT16*)edi + x - ecx;
797	793	do { if (dst_ptr[ecx]) dst_ptr[ecx] ^= ax; } while (++ecx);
798	794	}
799	795
r1103	r1104
840	836	{
841	837	dst_ptr += x;
842	838	do {
843		ax = (~~WORD~~)src1_ptr[edx];
	839	ax = (UINT16)src1_ptr[edx];
844	840	al = src1_ptr[edx+0x10000];
845	841	ax \|= BG_RGB;
846	842	if (al & 0x01) *dst_ptr = ax;
r1103	r1104
859	855	#define WARPMASK ((SCREEN_WIDTH<<1)-1)
860	856	do {
861	857	ecx = x & WARPMASK;
862		ax = (~~WORD~~)src1_ptr[edx];
	858	ax = (UINT16)src1_ptr[edx];
863	859	al = src1_ptr[edx+0x10000];
864	860	ax \|= BG_RGB;
865	861	if (al & 0x01) dst_ptr[ecx] = ax; ecx++; ecx &= WARPMASK;
r1103	r1104
883	879	if (command == HORIZBAR && flags & COLOR_ON && !(layer & 1))
884	880	{
885	881	#define WARP_LINE_COMMON { \
886		if (ecx & 1) { ecx--; *dst_ptr = (~~WORD~~)eax; dst_ptr++; } \
	882	if (ecx & 1) { ecx--; *dst_ptr = (UINT16)eax; dst_ptr++; } \
887	883	dst_ptr += ecx; ecx = -ecx; \
888		while (ecx) { (~~DWORD~~)(dst_ptr+ecx) = eax; ecx += 2; } }
	884	while (ecx) { (UINT32)(dst_ptr+ecx) = eax; ecx += 2; } }
889	885
890	886	src1_ptr = src_base + src1;
891	887	src2_ptr = src_base + src2;
r1103	r1104
912	908
913	909	for (yclip=y; yclip<hclip; yclip++)
914	910	{
915		eax = (~~DWORD~~)*src1_ptr;
	911	eax = (UINT32)*src1_ptr;
916	912	src1_ptr += src_dx;
917	913	if (!eax) continue;
918	914	eax = eax \| (eax<<16) \| ((BG_RGB<<16)\|BG_RGB);
r1103	r1104
921	917	if (edx > 0)
922	918	{
923	919	ecx = edx;
924		dst_ptr = (~~WORD~~*)edi;
	920	dst_ptr = (UINT16*)edi;
925	921	WARP_LINE_COMMON
926	922	ecx = SCREEN_WIDTH - xclip;
927	923	} else ecx = w;
928	924
929		dst_ptr = (~~WORD~~*)edi + xclip;
	925	dst_ptr = (UINT16*)edi + xclip;
930	926	WARP_LINE_COMMON
931	927	}
932	928
933		edi = src1_ptr; src1_ptr = src2_ptr; src2_ptr = (BYTE*)edi;
	929	edi = src1_ptr; src1_ptr = src2_ptr; src2_ptr = (UINT8*)edi;
934	930	}
935	931
936	932	#undef WARP_LINE_COMMON
r1103	r1104
946	942	static WRITE8_HANDLER( bgtile_w )
947	943	{
948	944	int yskip, xskip, ecx;
949		WORD *edi;
950		WORD ax;
	945	UINT16 *edi;
	946	UINT16 ax;
951	947
952	948	cpu1_base[0x1f00+offset] = data;
953	949	offset -= 0x18;
r1103	r1104
962	958
963	959	edi = render_layer[2] + (yskip<<SCREEN_WIDTH_L2) + xskip + (48<<SCREEN_WIDTH_L2);
964	960	ecx = -(48<<SCREEN_WIDTH_L2);
965		ax = (~~WORD~~)data \| BG_RGB;
	961	ax = (UINT16)data \| BG_RGB;
966	962
967	963	do { edi[ecx] = edi[ecx+1] = edi[ecx+2] = edi[ecx+3] = edi[ecx+4] = ax; } while (ecx += SCREEN_WIDTH);
968	964	}
r1103	r1104
1056	1052
1057	1053	static PALETTE_INIT( halleys )
1058	1054	{
1059		DWORD d, r, g, b, i, j, count;
1060		DWORD *pal_ptr = internal_palette;
	1055	UINT32 d, r, g, b, i, j, count;
	1056	UINT32 *pal_ptr = internal_palette;
1061	1057
1062	1058	for (count=0; count<1024; count++)
1063	1059	{
r1103	r1104
1102	1098	}
1103	1099	}
1104	1100
1105		static void halleys_decode_rgb(~~DWORD~~ r, ~~DWORD~~ g, ~~DWORD~~ *b, int addr, int data)
	1101	static void halleys_decode_rgb(UINT32 r, UINT32 g, UINT32 *b, int addr, int data)
1106	1102	{
1107	1103	/*
1108	1104	proms contain:
r1103	r1104
1149	1145
1150	1146	static WRITE8_HANDLER( halleys_paletteram_IIRRGGBB_w )
1151	1147	{
1152		DWORD d, r, g, b, i, j;
1153		DWORD *pal_ptr = internal_palette;
	1148	UINT32 d, r, g, b, i, j;
	1149	UINT32 *pal_ptr = internal_palette;
1154	1150
1155	1151	paletteram[offset] = data;
1156		d = (~~DWORD~~)data;
	1152	d = (UINT32)data;
1157	1153	j = d \| BG_RGB;
1158	1154	pal_ptr[offset] = j;
1159	1155	pal_ptr[offset+SP_2BACK] = j;
r1103	r1104
1205	1201	}
1206	1202
1207	1203
1208		static void copy_scroll_op(mame_bitmap bitmap, ~~WORD~~ source, int sx, int sy)
	1204	static void copy_scroll_op(mame_bitmap bitmap, UINT16 source, int sx, int sy)
1209	1205	{
1210	1206
1211	1207	//--------------------------------------------------------------------------
1212	1208
1213	1209	#define OPCOPY_COMMON { \
1214	1210	memcpy(edi, esi+sx, rcw); \
1215		memcpy((BYTE*)edi+rcw, esi, CLIP_BYTEW-rcw); \
	1211	memcpy((UINT8*)edi+rcw, esi, CLIP_BYTEW-rcw); \
1216	1212	esi += SCREEN_WIDTH; \
1217	1213	edi += edx; }
1218	1214
1219	1215	//--------------------------------------------------------------------------
1220	1216
1221		~~WORD~~ esi, edi;
	1217	UINT16 esi, edi;
1222	1218	int rcw, bch, ecx, edx;
1223	1219
1224	1220	sx = -sx & 0xff;
r1103	r1104
1243	1239	}
1244	1240
1245	1241
1246		static void copy_scroll_xp(mame_bitmap bitmap, ~~WORD~~ source, int sx, int sy)
	1242	static void copy_scroll_xp(mame_bitmap bitmap, UINT16 source, int sx, int sy)
1247	1243	{
1248	1244
1249	1245	//--------------------------------------------------------------------------
r1103	r1104
1271	1267
1272	1268	int rcw, bch, dst_adv;
1273	1269
1274		~~WORD~~ src_base, esi, *edi;
	1270	UINT16 src_base, esi, *edi;
1275	1271	int ecx, edx;
1276		~~WORD~~ ax, bx;
	1272	UINT16 ax, bx;
1277	1273
1278	1274	sx = -sx & 0xff;
1279	1275	sy = -sy & 0xff;
r1103	r1104
1299	1295
1300	1296
1301	1297
1302		static void copy_fixed_xp(mame_bitmap bitmap, ~~WORD~~ source)
	1298	static void copy_fixed_xp(mame_bitmap bitmap, UINT16 source)
1303	1299	{
1304		~~WORD~~ esi, edi;
	1300	UINT16 esi, edi;
1305	1301	int dst_pitch, ecx, edx;
1306		~~WORD~~ ax, bx;
	1302	UINT16 ax, bx;
1307	1303
1308	1304	esi = source + CLIP_SKIP + CLIP_W;
1309	1305	edi = BITMAP_ADDR16(bitmap, VIS_MINY, VIS_MINX + CLIP_W);
r1103	r1104
1334	1330	}
1335	1331
1336	1332
1337		static void copy_fixed_2b(mame_bitmap bitmap, ~~WORD~~ source)
	1333	static void copy_fixed_2b(mame_bitmap bitmap, UINT16 source)
1338	1334	{
1339		~~WORD~~ esi, edi;
	1335	UINT16 esi, edi;
1340	1336	int dst_pitch, ecx, edx;
1341		~~WORD~~ ax, bx;
	1337	UINT16 ax, bx;
1342	1338
1343	1339	esi = source + CLIP_SKIP + CLIP_W;
1344	1340	edi = BITMAP_ADDR16(bitmap, VIS_MINY, VIS_MINX + CLIP_W);
r1103	r1104
1385	1381	{
1386	1382	int dst_pitch;
1387	1383
1388		~~DWORD~~ pal_ptr, edi;
	1384	UINT32 pal_ptr, edi;
1389	1385	int esi, eax, ebx, ecx, edx;
1390	1386
1391	1387	pal_ptr = internal_palette;
1392	1388	esi = mask \| 0xffffff00;
1393		edi = (~~DWORD~~*)BITMAP_ADDR16(bitmap, VIS_MINY, VIS_MINX + CLIP_W);
	1389	edi = (UINT32*)BITMAP_ADDR16(bitmap, VIS_MINY, VIS_MINX + CLIP_W);
1394	1390	dst_pitch = bitmap->rowpixels >> 1;
1395	1391	ecx = -(CLIP_W>>1);
1396	1392	edx = CLIP_H;
r1103	r1104
1477	1473	static INTERRUPT_GEN( halleys_interrupt )
1478	1474	{
1479	1475	static int latch_delay = 0;
1480		BYTE latch_data;
	1476	UINT8 latch_data;
1481	1477
1482	1478	switch (cpu_getiloops())
1483	1479	{
r1103	r1104
1530	1526	static INTERRUPT_GEN( benberob_interrupt )
1531	1527	{
1532	1528	static int latch_delay = 0;
1533		BYTE latch_data;
	1529	UINT8 latch_data;
1534	1530
1535	1531	switch (cpu_getiloops())
1536	1532	{
r1103	r1104
2148	2144
2149	2145	static void init_common(void)
2150	2146	{
2151		BYTE buf, rom;
	2147	UINT8 buf, rom;
2152	2148	int addr, i;
2153		BYTE al, ah, dl, dh;
	2149	UINT8 al, ah, dl, dh;
2154	2150
2155	2151
2156	2152	// allocate memory for unpacked graphics
r1103	r1104
2161	2157
2162	2158	// allocate memory for render layers
2163	2159	buf = auto_malloc(SCREEN_BYTESIZE * MAX_LAYERS);
2164		for (i=0; i<MAX_LAYERS; buf+=SCREEN_BYTESIZE, i++) render_layer[i] = (~~WORD~~*)buf;
	2160	for (i=0; i<MAX_LAYERS; buf+=SCREEN_BYTESIZE, i++) render_layer[i] = (UINT16*)buf;
2165	2161
2166	2162
2167	2163	// allocate memory for pre-processed ROMs
r1103	r1104
2169	2165
2170	2166
2171	2167	// allocate memory for alpha table
2172		alpha_table = auto_malloc(sizeof(~~DWORD~~) * 0x10000);
	2168	alpha_table = auto_malloc(sizeof(UINT32) * 0x10000);
2173	2169
2174	2170
2175	2171	// allocate memory for internal palette
2176		internal_palette = auto_malloc(sizeof(~~DWORD~~) * PALETTE_SIZE);
	2172	internal_palette = auto_malloc(sizeof(UINT32) * PALETTE_SIZE);
2177	2173
2178	2174
2179	2175	// allocate memory for hardware collision list

src/mame/drivers/peplus.c
r0	r1104
	1	/**********************************************************************************
	2
	3
	4	PLAYER'S EDGE PLUS (PE+)
	5
	6	Driver by Jim Stolis.
	7
	8	--- Technical Notes ---
	9
	10	Name: Player's Edge Plus (PP0516) Double Bonus Draw Poker.
	11	Company: IGT - International Gaming Technology
	12	Year: 1987
	13
	14	Hardware:
	15
	16	CPU = 83c02 ; I8052 compatible
	17	VIDEO = SY6545 ; CRTC6845 compatible
	18	SND = AY-3-8912 ; AY8910 compatible
	19
	20	History:
	21
	22	This form of video poker machine has the ability to use different game roms. The operator
	23	changes the game by placing the rom at U68 on the motherboard. This driver is currently valid
	24	for the PP0516 game rom, but should work with all other compatible game roms as cpu, video,
	25	sound, and inputs is concerned. Some games can share the same color prom and graphic roms,
	26	but this is not always the case. It is best to confirm the game, color and graphic combinations.
	27
	28	The game code runs in two different modes, game mode and operator mode. Game mode is what a
	29	normal player would see when playing. Operator mode is for the machine operator to adjust
	30	machine settings and view coin counts. The upper door must be open in order to enter operator
	31	mode and so it should be mapped to an input bank if you wish to support it. The operator
	32	has two additional inputs (jackpot reset and self-test) to navigate with, along with the
	33	normal buttons available to the player.
	34
	35	A normal machine keeps all coin counts and settings in a battery-backed ram, and will
	36	periodically update an external eeprom for an even more secure backup. This eeprom
	37	also holds the current game state in order to recover the player from a full power failure.
	38
	39	***********************************************************************************/
	40	#include "driver.h"
	41	#include "sound/ay8910.h"
	42	#include "cpu/i8051/i8051.h"
	43
	44	static tilemap *bg_tilemap;
	45
	46	/* Pointers to External RAM */
	47	UINT8 *program_ram;
	48	UINT8 *settings_ram;
	49	UINT8 *set038_ram;
	50
	51	/* Variables used instead of CRTC6845 system */
	52	UINT8 vid_register = 0;
	53	UINT8 vid_low = 0;
	54	UINT8 vid_high = 0;
	55
	56	/* Holds upper video address and palette number */
	57	UINT8 *palette_ram;
	58
	59	UINT8 ramcheck;
	60	/*****************
	61	* Write Handlers *
	62	******************/
	63
	64	WRITE8_HANDLER( peplus_bgcolor_w )
	65	{
	66	int i;
	67
	68	for (i = 0; i < 16; i++)
	69	{
	70	int bit0, bit1, bit2, r, g, b;
	71
	72	/* red component */
	73	bit0 = (~data >> 0) & 0x01;
	74	bit1 = (~data >> 1) & 0x01;
	75	bit2 = (~data >> 2) & 0x01;
	76	r = 0x21 * bit2 + 0x47 * bit1 + 0x97 * bit0;
	77
	78	/* green component */
	79	bit0 = (~data >> 3) & 0x01;
	80	bit1 = (~data >> 4) & 0x01;
	81	bit2 = (~data >> 5) & 0x01;
	82	g = 0x21 * bit2 + 0x47 * bit1 + 0x97 * bit0;
	83
	84	/* blue component */
	85	bit0 = (~data >> 6) & 0x01;
	86	bit1 = (~data >> 7) & 0x01;
	87	bit2 = 0;
	88	b = 0x21 * bit2 + 0x47 * bit1 + 0x97 * bit0;
	89
	90	palette_set_color(Machine, (15 + (i*16)), MAKE_RGB(r, g, b));
	91	}
	92	}
	93
	94	/*
	95	SY6545 - Transparent Memory Addressing
	96	The current CRTC6845 driver does not support these
	97	additional registers (R18, R19, R31)
	98	*/
	99	WRITE8_HANDLER( peplus_crtc_register_w )
	100	{
	101	switch(data) {
	102	case 0x12: /* Update Address High */
	103	case 0x13: /* Update Address Low */
	104	case 0x1f: /* Dummy Location */
	105	vid_register = data;
	106	break;
	107	}
	108	}
	109
	110	WRITE8_HANDLER( peplus_crtc_address_w )
	111	{
	112	switch(vid_register) {
	113	case 0x12: /* Update Address High */
	114	vid_high = data;
	115	break;
	116	case 0x13: /* Update Address Low */
	117	vid_low = data;
	118	break;
	119	}
	120	}
	121
	122	WRITE8_HANDLER( peplus_crtc_display_w )
	123	{
	124	UINT16 vid_address = (vid_high<<8) \| vid_low;
	125
	126	/* P1 holds the following: */
	127	/* high nibble = palette, low nibble = high address */
	128	UINT8 p1 = i8051_get_intram(P1);
	129
	130	videoram[vid_address] = data;
	131	palette_ram[vid_address] = p1;
	132
	133	tilemap_mark_tile_dirty(bg_tilemap, vid_address);
	134
	135	/* Transparent Memory Addressing increments the update address register */
	136	if (vid_low == 0xff) {
	137	vid_high++;
	138	}
	139	vid_low++;
	140	}
	141
	142	WRITE8_HANDLER( peplus_eeprom_w )
	143	{
	144	// EEPROM is a X2404P 4K-bit Serial I2C Bus
	145	}
	146
	147	WRITE8_HANDLER( peplus_ramcheck_w )
	148	{
	149	ramcheck = data;
	150	}
	151
	152
	153	/****************
	154	* Read Handlers *
	155	****************/
	156
	157	/* External RAM Callback for I8052 */
	158	READ32_HANDLER( peplus_external_ram_iaddr )
	159	{
	160	UINT8 p2 = i8051_get_intram(P2);
	161
	162	if (offset < 0x1000) {
	163	return (p2 << 8) \| offset;
	164	} else {
	165	return offset;
	166	}
	167	}
	168
	169	/* Last Color in Every Palette is bgcolor */
	170	READ8_HANDLER( peplus_bgcolor_r )
	171	{
	172	return palette_get_color(Machine, 15); /* Return bgcolor from First Palette */
	173	}
	174
	175
	176	/* Insufficient Code, will need more to handle cmos and coin pulses */
	177	READ8_HANDLER( peplus_input_bank_a_r )
	178	{
	179	/*
	180	Bit 0 = COIN DETECTOR A
	181	Bit 1 = COIN DETECTOR B
	182	Bit 2 = COIN DETECTOR C
	183	Bit 3 = COIN OUT
	184	Bit 4 = HOPPER FULL
	185	Bit 5 = DOOR OPEN
	186	Bit 6 = LOW BATTERY
	187	Bit 7 = CMOS ACK (0=ACK)
	188	*/
	189	return 0x77;
	190	}
	191
	192	READ8_HANDLER( peplus_ramcheck_r )
	193	{
	194	if (ramcheck == 0x3e)
	195	return 0xff;
	196	else
	197	return ramcheck;
	198	}
	199
	200
	201	/*************************
	202	* Temporary Memory Hacks *
	203	*************************/
	204
	205	/* Hack to test coins in */
	206	READ8_HANDLER( peplus_coinsin_r )
	207	{
	208	return 0x05;
	209	}
	210
	211	/* Hack to test credits */
	212	READ8_HANDLER( peplus_credits_r )
	213	{
	214	return 0x20;
	215	}
	216
	217	/****************************
	218	* Video/Character functions *
	219	****************************/
	220
	221	static TILE_GET_INFO( get_bg_tile_info )
	222	{
	223	int pr = palette_ram[tile_index];
	224	int vr = videoram[tile_index];
	225
	226	int code = ((pr & 0x0f)*256) \| vr;
	227	int color = (pr>>4) & 0x0f;
	228
	229	SET_TILE_INFO(0, code, color, 0);
	230	}
	231
	232	VIDEO_START( peplus )
	233	{
	234	bg_tilemap = tilemap_create(get_bg_tile_info, tilemap_scan_rows, TILEMAP_TYPE_PEN, 8, 8, 40, 25);
	235	palette_ram = auto_malloc(0x3000);
	236	memset(palette_ram, 0, 0x3000);
	237	}
	238
	239	VIDEO_UPDATE( peplus )
	240	{
	241	tilemap_draw(bitmap, cliprect, bg_tilemap, 0, 0);
	242
	243	return 0;
	244	}
	245
	246	PALETTE_INIT( peplus )
	247	{
	248	/* prom bits
	249	7654 3210
	250	---- -xxx red component.
	251	--xx x--- green component.
	252	xx-- ---- blue component.
	253	*/
	254	int i;
	255
	256	for (i = 0;i < machine->drv->total_colors;i++)
	257	{
	258	int bit0, bit1, bit2, r, g, b;
	259
	260	/* red component */
	261	bit0 = (color_prom[i] >> 0) & 0x01;
	262	bit1 = (color_prom[i] >> 1) & 0x01;
	263	bit2 = (color_prom[i] >> 2) & 0x01;
	264	r = 0x21 * bit2 + 0x47 * bit1 + 0x97 * bit0;
	265
	266	/* green component */
	267	bit0 = (color_prom[i] >> 3) & 0x01;
	268	bit1 = (color_prom[i] >> 4) & 0x01;
	269	bit2 = (color_prom[i] >> 5) & 0x01;
	270	g = 0x21 * bit2 + 0x47 * bit1 + 0x97 * bit0;
	271
	272	/* blue component */
	273	bit0 = (color_prom[i] >> 6) & 0x01;
	274	bit1 = (color_prom[i] >> 7) & 0x01;
	275	bit2 = 0;
	276	b = 0x21 * bit2 + 0x47 * bit1 + 0x97 * bit0;
	277
	278	/* TODO */
	279	/* Add code to load last color in each palette with bgcolor */
	280	/* Using default in color prom instead for now */
	281
	282	palette_set_color(machine, i, MAKE_RGB(r, g, b));
	283	}
	284	}
	285
	286
	287	/*************************
	288	* Graphics Layouts *
	289	*************************/
	290
	291	static const gfx_layout charlayout =
	292	{
	293	8,8, /* 8x8 characters */
	294	0x1000, /* 4096 characters */
	295	4, /* 4 bitplanes */
	296	{ 0x1000883, 0x1000882, 0x1000881, 0x1000880 }, /* bitplane offsets */
	297	{ 0, 1, 2, 3, 4, 5, 6, 7 },
	298	{ 08, 18, 28, 38, 48, 58, 68, 78 },
	299	8*8
	300	};
	301
	302
	303	/******************************
	304	* Graphics Decode Information *
	305	******************************/
	306
	307	static GFXDECODE_START( peplus )
	308	GFXDECODE_ENTRY( REGION_GFX1, 0x00000, charlayout, 0, 16 )
	309	GFXDECODE_END
	310
	311
	312	/***********************
	313	* Sound Interface *
	314	***********************/
	315
	316	static struct AY8910interface ay8910_interface =
	317	{
	318	input_port_3_r /* SW1 is accessed via sound portA */
	319	};
	320
	321
	322	/**************
	323	* Driver Init *
	324	***************/
	325
	326	static DRIVER_INIT( peplus )
	327	{
	328	/* External RAM callback */
	329	i8051_set_eram_iaddr_callback(peplus_external_ram_iaddr);
	330
	331	// Set038 Chip - For testing only, cannot stay in final driver
	332	//program_ram[0x302] = 0x22; /* disable memory test */
	333	//program_ram[0x289f] = 0x22; /* disable program checksum */
	334	//set038_ram[0x00] = 0xfe;
	335
	336	// PP0516 - For testing only, cannot stay in final driver
	337	program_ram[0x9a24] = 0x22; /* disable memory test */
	338	program_ram[0xd61d] = 0x22; /* disable program checksum */
	339
	340	/* TODO: Machine settings and coin counts need to be loaded using save state system */
	341	/* below are some hardcoded examples of memory to patch */
	342
	343	settings_ram[0x030] = 0x05; /* Maximum Coins - 5 */
	344	settings_ram[0x06b] = 0x03; /* Current Denomination - 25c */
	345	set038_ram[0x2a] = settings_ram[0x06b];
	346	settings_ram[0x197] = 0x00; /* Bill Acceptor - Disabled */
	347	set038_ram[0x2b] = settings_ram[0x197];
	348	}
	349
	350	/*************************
	351	* Memory map information *
	352	*************************/
	353
	354	static ADDRESS_MAP_START( peplus_map, ADDRESS_SPACE_PROGRAM, 8 )
	355	AM_RANGE(0x0000, 0xffff) AM_ROM AM_BASE(&program_ram)
	356	ADDRESS_MAP_END
	357
	358	static ADDRESS_MAP_START( peplus_datamap, ADDRESS_SPACE_DATA, 8 )
	359	AM_RANGE(0x2080, 0x2080) AM_WRITE(peplus_crtc_register_w)
	360	AM_RANGE(0x2081, 0x2081) AM_WRITE(peplus_crtc_address_w)
	361	AM_RANGE(0x2083, 0x2083) AM_WRITE(peplus_crtc_display_w)
	362	AM_RANGE(0x20db, 0x20db) AM_READ(input_port_1_r) /* upper door */
	363	AM_RANGE(0x2100, 0x21ff) AM_RAM AM_BASE(&settings_ram)
	364	AM_RANGE(0x2b8d, 0x2b8d) AM_READ(input_port_2_r) /* lower door */
	365	//AM_RANGE(0x2b9b, 0x2b9b) AM_READ(peplus_coinsin_r) /* hack to test coins in */
	366	//AM_RANGE(0x2b9d, 0x2b9d) AM_READ(peplus_credits_r) /* hack to test credits */
	367	AM_RANGE(0x2e01, 0x2eff) AM_RAM AM_BASE(&set038_ram)
	368	AM_RANGE(0x4000, 0x4000) AM_WRITE(AY8910_control_port_0_w)
	369	AM_RANGE(0x4004, 0x4004) AM_WRITE(AY8910_write_port_0_w)
	370	//AM_RANGE(0x4175, 0x4175) AM_READ(peplus_ramcheck_r) AM_WRITE(peplus_ramcheck_w)
	371
	372	AM_RANGE(0x6000, 0x6000) AM_READ(peplus_bgcolor_r) AM_WRITE(peplus_bgcolor_w)
	373	AM_RANGE(0x7000, 0x73ff) AM_RAM AM_BASE(&videoram)
	374	AM_RANGE(0x8000, 0x8000) AM_READ(peplus_input_bank_a_r)
	375	AM_RANGE(0x9000, 0x9000) AM_WRITE(peplus_eeprom_w)
	376	AM_RANGE(0xa000, 0xa000) AM_READ(input_port_0_r)
	377	AM_RANGE(0x0000, 0xffff) AM_RAM
	378	ADDRESS_MAP_END
	379
	380	/*************************
	381	* Input ports *
	382	*************************/
	383
	384	INPUT_PORTS_START( peplus )
	385	PORT_START_TAG("IN0")
	386	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("Jackpot Reset") PORT_CODE(KEYCODE_L)
	387	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("Self Test") PORT_CODE(KEYCODE_K)
	388	PORT_BIT( 0x03, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("Hold 1") PORT_CODE(KEYCODE_Z)
	389	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("Hold 2") PORT_CODE(KEYCODE_X)
	390	PORT_BIT( 0x05, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("Hold 3") PORT_CODE(KEYCODE_C)
	391	PORT_BIT( 0x06, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("Hold 4") PORT_CODE(KEYCODE_V)
	392	PORT_BIT( 0x07, IP_ACTIVE_LOW, IPT_BUTTON7 ) PORT_NAME("Hold 5") PORT_CODE(KEYCODE_B)
	393	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	394	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON9 ) PORT_NAME("Deal-Spin-Start") PORT_CODE(KEYCODE_Q)
	395	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON10 ) PORT_NAME("Max Bet") PORT_CODE(KEYCODE_W)
	396	PORT_BIT( 0x30, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	397	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON12 ) PORT_NAME("Play Credit") PORT_CODE(KEYCODE_R)
	398	PORT_BIT( 0x50, IP_ACTIVE_HIGH, IPT_BUTTON13 ) PORT_NAME("Cashout") PORT_CODE(KEYCODE_T)
	399	PORT_BIT( 0x60, IP_ACTIVE_HIGH, IPT_BUTTON14 ) PORT_NAME("Change Request") PORT_CODE(KEYCODE_Y)
	400	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_BUTTON15 ) PORT_NAME("Bill Acceptor") PORT_CODE(KEYCODE_U)
	401	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	402
	403	PORT_START_TAG("IN1")
	404	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Upper Door") PORT_CODE(KEYCODE_O)
	405
	406	PORT_START_TAG("IN2")
	407	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Lower Door") PORT_CODE(KEYCODE_I)
	408
	409	PORT_START_TAG("SW1")
	410	PORT_DIPNAME( 0x01, 0x01, "0-60HZ, 1-50HZ" )
	411	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	412	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	413	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	414	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	415	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	416	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	417	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	418	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	419	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	420	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	421	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	422	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	423	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	424	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	425	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	426	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	427	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	428	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	429	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	430	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	431	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	432	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	433	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	434	INPUT_PORTS_END
	435
	436
	437	/*************************
	438	* Machine Driver *
	439	*************************/
	440
	441	static MACHINE_DRIVER_START( peplus )
	442	// basic machine hardware
	443	MDRV_CPU_ADD(I8052, 3686400*2)
	444	MDRV_CPU_PROGRAM_MAP(peplus_map, 0)
	445	MDRV_CPU_DATA_MAP(peplus_datamap, 0)
	446	MDRV_CPU_VBLANK_INT(irq0_line_hold, 1)
	447
	448	MDRV_SCREEN_REFRESH_RATE(60)
	449	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
	450
	451	// video hardware
	452	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
	453	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
	454	MDRV_SCREEN_SIZE((52+1)8, (31+1)8)
	455	MDRV_SCREEN_VISIBLE_AREA(08, 408-1, 08, 258-1)
	456
	457	MDRV_GFXDECODE(peplus)
	458	MDRV_PALETTE_LENGTH(16*16)
	459
	460	MDRV_PALETTE_INIT(peplus)
	461	MDRV_VIDEO_START(peplus)
	462	MDRV_VIDEO_UPDATE(peplus)
	463
	464	// sound hardware
	465	MDRV_SOUND_ADD(AY8912, 20000000/12)
	466	MDRV_SPEAKER_STANDARD_MONO("mono")
	467	MDRV_SOUND_CONFIG(ay8910_interface)
	468	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
	469	MACHINE_DRIVER_END
	470
	471
	472	/*************************
	473	* Rom Load *
	474	*************************/
	475
	476	ROM_START( peplus )
	477	ROM_REGION( 0x10000, REGION_CPU1, 0 )
	478	ROM_LOAD( "pp0516.u68", 0x00000, 0x10000, CRC(d9da6e13) SHA1(421678d9cb42daaf5b21074cc3900db914dd26cf) )
	479
	480	ROM_REGION( 0x100000, REGION_GFX1, ROMREGION_DISPOSE )
	481	ROM_LOAD( "mro-cg740.u72", 0x00000, 0x8000, CRC(72667f6c) SHA1(89843f472cc0329317cfc643c63bdfd11234b194) )
	482	ROM_LOAD( "mgo-cg740.u73", 0x08000, 0x8000, CRC(7437254a) SHA1(bba166dece8af58da217796f81117d0b05752b87) )
	483	ROM_LOAD( "mbo-cg740.u74", 0x10000, 0x8000, CRC(92e8c33e) SHA1(05344664d6fdd3f4205c50fa4ca76fc46c18cf8f) )
	484	ROM_LOAD( "mxo-cg740.u75", 0x18000, 0x8000, CRC(ce4cbe0b) SHA1(4bafcd68be94a5deaae9661584fa0fc940b834bb) )
	485
	486	ROM_REGION( 0x100, REGION_PROMS, 0 )
	487	ROM_LOAD( "cap740.u50", 0x0000, 0x0100, CRC(9cd834bd) SHA1(ad66099d8ed8f784fb20b97df7c9dda51b19ff3f) )
	488	ROM_END
	489
	490
	491	/*************************
	492	* Game Drivers *
	493	*************************/
	494
	495	/* YEAR NAME PARENT MACHINE INPUT INIT ROT COMPANY FULLNAME FLAGS */
	496	GAME( 1987, peplus, 0, peplus, peplus, peplus, ROT0, "IGT - International Gaming Technology", "Player's Edge Plus (PP0516) Double Bonus Poker", 0 )

src/mame/drivers/segas16a.c
r1103	r1104
2023	2023	ROM_LOAD( "10436.2", 0x8000, 0x8000, CRC(96c76613) SHA1(fe3e4e649fd2cb2453eec0c92015bd54b3b9a1b5) )
2024	2024	ROM_END
2025	2025
	2026	/**************************************************************************************************************************
	2027	**************************************************************************************************************************
	2028	**************************************************************************************************************************
	2029	Alien Syndrome, System 16A
	2030	CPU: FD1089B
	2031	*/
2026	2032
	2033	ROM_START( aliensy5 )
	2034	ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 68000 code */
	2035	ROM_LOAD16_BYTE( "epr10804.43", 0x00000, 0x8000, CRC(23f78b83) SHA1(76538663e8f7ffffeea4928e3ebe091dac954dc7) )
	2036	ROM_LOAD16_BYTE( "epr10802.26", 0x00001, 0x8000, CRC(996768bd) SHA1(8c972f0f4120600ecd10ceb3456243d9614924b7) )
	2037	ROM_LOAD16_BYTE( "epr10805.42", 0x10000, 0x8000, CRC(53d7fe50) SHA1(9a4e18f4d11c77ec04a817dca7b618297658113e) )
	2038	ROM_LOAD16_BYTE( "epr10803.25", 0x10001, 0x8000, CRC(0536dd33) SHA1(f094ed25d81dadf15a47c15711e47c3cb5f33227) )
	2039	ROM_LOAD16_BYTE( "epr10732.41", 0x20000, 0x8000, CRC(c5712bfc) SHA1(2f11570784c1fc83cb16dbd1d43e21cf104568ac) )
	2040	ROM_LOAD16_BYTE( "epr10729.24", 0x20001, 0x8000, CRC(3e520e30) SHA1(8eac2640ff8c4944d6cd82421b565f506c480017) )
	2041
	2042	ROM_REGION( 0x30000, REGION_GFX1, ROMREGION_DISPOSE ) /* tiles */
	2043	ROM_LOAD( "10739", 0x00000, 0x10000, CRC(a29ec207) SHA1(c469d2689a7bdc2a59dfff56ce13d34e9fbac263) )
	2044	ROM_LOAD( "10740", 0x10000, 0x10000, CRC(47f93015) SHA1(68247a6bffd1d4d1c450148dd46214d01ce1c668) )
	2045	ROM_LOAD( "10741", 0x20000, 0x10000, CRC(4970739c) SHA1(5bdf4222209ec46e0015bfc0f90578dd9b30bdd1) )
	2046
	2047	ROM_REGION16_BE( 0x080000, REGION_GFX2, 0 ) /* sprites */
	2048	ROM_LOAD16_BYTE( "10709.b1", 0x00001, 0x08000, CRC(addf0a90) SHA1(a92c9531f1817763773471ce63f566b9e88360a0) )
	2049	ROM_CONTINUE( 0x40001, 0x08000 )
	2050	ROM_LOAD16_BYTE( "10713.b5", 0x00000, 0x08000, CRC(ececde3a) SHA1(9c12d4665179bf433c42f5ddc8a043ad592aa90e) )
	2051	ROM_CONTINUE( 0x40000, 0x08000 )
	2052	ROM_LOAD16_BYTE( "10710.b2", 0x10001, 0x08000, CRC(992369eb) SHA1(c6796acf6807e9ba4c3d241903653f91adf4764e) )
	2053	ROM_CONTINUE( 0x50001, 0x08000 )
	2054	ROM_LOAD16_BYTE( "10714.b6", 0x10000, 0x08000, CRC(91bf42fb) SHA1(4b9d3e97768323dee01e92378adafecb26bcc094) )
	2055	ROM_CONTINUE( 0x50000, 0x08000 )
	2056	ROM_LOAD16_BYTE( "10711.b3", 0x20001, 0x08000, CRC(29166ef6) SHA1(99a7cfd7d811537c821412a320beadb5a9c09af3) )
	2057	ROM_CONTINUE( 0x60001, 0x08000 )
	2058	ROM_LOAD16_BYTE( "10715.b7", 0x20000, 0x08000, CRC(a7c57384) SHA1(46f8efa691d7bbb0a18119c0ff12cff7c0d129e1) )
	2059	ROM_CONTINUE( 0x60000, 0x08000 )
	2060	ROM_LOAD16_BYTE( "10712.b4", 0x30001, 0x08000, CRC(876ad019) SHA1(39973ddb5a5746e0e094c759447bff1130c72c84) )
	2061	ROM_CONTINUE( 0x70001, 0x08000 )
	2062	ROM_LOAD16_BYTE( "10716.b8", 0x30000, 0x08000, CRC(40ba1d48) SHA1(e2d4d2689bb9b9bdc85e7f72a6665e5fd4c583aa) )
	2063	ROM_CONTINUE( 0x70000, 0x08000 )
	2064
	2065	ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* sound CPU */
	2066	ROM_LOAD( "10705", 0x00000, 0x8000, CRC(777b749e) SHA1(086b03100064a98228f95db7962b2671121c46ea) )
	2067
	2068	ROM_REGION( 0x1000, REGION_CPU3, 0 ) /* 4k for 7751 onboard ROM */
	2069	ROM_LOAD( "7751.bin", 0x0000, 0x0400, CRC(6a9534fc) SHA1(67ad94674db5c2aab75785668f610f6f4eccd158) ) /* 7751 - U34 */
	2070
	2071	ROM_REGION( 0x18000, REGION_SOUND1, 0 ) /* 7751 sound data */
	2072	ROM_LOAD( "10706", 0x00000, 0x8000, CRC(aa114acc) SHA1(81a2b3586ae90bc7fc55b82478ffe182ac49983e) )
	2073	ROM_LOAD( "10707", 0x08000, 0x8000, CRC(800c1d82) SHA1(aac4123bd35f87da09264649f4cf8326b2ba3cb8) )
	2074	ROM_LOAD( "10708", 0x10000, 0x8000, CRC(5921ef52) SHA1(eff9978361692e6e60a9c6caf5740dd6182cfe4a) )
	2075	ROM_END
	2076
	2077
2027	2078	/**************************************************************************************************************************
2028	2079	**************************************************************************************************************************
2029	2080	**************************************************************************************************************************
r1103	r1104
3054	3105	fd1089_decrypt_0033();
3055	3106	}
3056	3107
	3108	static DRIVER_INIT( aliensy5 )
	3109	{
	3110	// void fd1089_decrypt_0037(void);
	3111	system16a_generic_init(machine);
	3112	// fd1089_decrypt_0037();
	3113	}
3057	3114
3058	3115	static DRIVER_INIT( bodyslam )
3059	3116	{
r1103	r1104
3116	3173	*************************************/
3117	3174
3118	3175	/* "Pre-System 16" */
3119		GAME( 1987, aliensy2, aliensyn, system16a, aliensyn, aliensy1, ROT0, "Sega", "Alien Syndrome (set 2, System 16A, FD1089A 317-0033)", 0 )
3120		GAME( 1987, aliensy1, aliensyn, system16a, aliensy1, aliensy1, ROT0, "Sega", "Alien Syndrome (set 1, System 16A, FD1089A 317-0033)", 0 )
3121	3176	GAME( 1986, bodyslam, 0, system16a_8751, bodyslam, bodyslam, ROT0, "Sega", "Body Slam (8751 317-0015)", 0 )
3122	3177	GAME( 1986, dumpmtmt, bodyslam, system16a_8751, bodyslam, bodyslam, ROT0, "Sega", "Dump Matsumoto (Japan, 8751 317-unknown)", 0 )
3123	3178	GAME( 1985, mjleague, 0, system16a, mjleague, mjleague, ROT270, "Sega", "Major League", 0 )
r1103	r1104
3127	3182	GAME( 1986, quart2, quartet, system16a, quart2, generic_16a, ROT0, "Sega", "Quartet 2 (unprotected)", 0 )
3128	3183
3129	3184	/* System 16A */
	3185	GAME( 1987, aliensy5, aliensyn, system16a, aliensyn, aliensy5, ROT0, "Sega", "Alien Syndrome (set 5, System 16A, FD1089B 317-0037)", GAME_NOT_WORKING )
	3186	GAME( 1987, aliensy2, aliensyn, system16a, aliensyn, aliensy1, ROT0, "Sega", "Alien Syndrome (set 2, System 16A, FD1089A 317-0033)", 0 )
	3187	GAME( 1987, aliensy1, aliensyn, system16a, aliensy1, aliensy1, ROT0, "Sega", "Alien Syndrome (set 1, System 16A, FD1089A 317-0033)", 0 )
3130	3188	GAME( 1988, aceattaa, aceattac, system16a , aceattaa, aceattaa, ROT270, "Sega", "Ace Attacker (Japan, System 16A, FD1094 317-0060)", 0 )
3131	3189	GAME( 1986, afighter, 0, system16a_no7751, afighter, afighter, ROT270, "Sega", "Action Fighter, FD1089A 317-0018", 0 )
3132	3190	GAME( 1986, alexkidd, 0, system16a, alexkidd, generic_16a, ROT0, "Sega", "Alex Kidd: The Lost Stars (set 2, unprotected)", 0 )

src/mame/drivers/parodius.c
r1103	r1104
262	262	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
263	263
264	264	PORT_START /* DSW #3 */
265		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
	265	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
266	266	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE )
267	267	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 )
268	268	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN2 )

src/mame/drivers/gpworld.c
r0	r1104
	1	/*
	2	Sega GP World hardware
	3	Driver by Andrew Gardner with help from Daphne Source.
	4
	5	Notes:
	6	- GP World is a rare game that came in a huge cabinet with two monitors, side by side.
	7	The image from the laserdisc was stretched to an 8x3 aspect and graphics were overlayed
	8	on top.
	9	- The hardware is similar to Astron Belt but somewhat more powerful.
	10
	11
	12	ToDo:
	13	- Hook up start lamp to mame lamp system
	14	- Do the gear shifter right
	15	- What's up with the pedals being tied together?
	16	- Daphne says this game is dual monitor. Is it?
	17	- Finish sprite drawing - looks awfully similar to system1 and suprloco.
	18	- Palette!
	19	- Still some undocumented reads and writes - likely dealing with I/O.
	20	- Convert to tilemaps.
	21
	22	Dumping Notes:
	23	GP World by Sega - Dumped by Matteo Marioni on Dec, 21 2001
	24
	25	834-5515-01
	26	GP WORLD P.
	27	SEGA No. 123743
	28
	29	Chip Label
	30	82S123 PR6146, PR6147
	31	27128 EPR-6162A (the "A" letter is handwritten), EPR-6163, EPR-6164, EPR-6157, EPR-6155, EPR-6153
	32	EPR-6151, EPR-6149, EPR-6158, EPR-6156, EPR-6154, EPR-6152, EPR-6150
	33	2732 EPR-6148
	34	82S129 PR-5501 (located on video overlay pcb)
	35
	36	(not dumped)
	37	DMPAL16R6JC 315-5072.ic9, 315-5071.ic10
	38	DMPAL12H6JC 315-5070.ic97
	39	*/
	40
	41
	42	#include "driver.h"
	43	#include "render.h"
	44	#include "machine/laserdsc.h"
	45
	46	/* Assumed to be the same as segald hardware */
	47	#define GUESSED_CLOCK (5000000)
	48
	49	static UINT8 nmi_enable;
	50	static UINT8 start_lamp;
	51	static UINT8 ldp_read_latch;
	52	static UINT8 ldp_write_latch;
	53
	54	static UINT8* tile_RAM;
	55	static UINT8* sprite_RAM;
	56	static UINT8* palette_RAM;
	57
	58	static laserdisc_info *discinfo;
	59
	60
	61	/* VIDEO GOODS */
	62	void gpworld_draw_tiles(running_machine machine, mame_bitmap bitmap,const rectangle *cliprect)
	63	{
	64	UINT8 characterX, characterY;
	65
	66	/* Temporarily set to 64 wide to accommodate two screens */
	67	for (characterX = 0; characterX < 64; characterX++)
	68	{
	69	for (characterY = 0; characterY < 32; characterY++)
	70	{
	71	int current_screen_character = (characterY*64) + characterX;
	72
	73	drawgfx(bitmap, machine->gfx[0], tile_RAM[current_screen_character],
	74	0, 0, 0, characterX8, characterY8, cliprect, TRANSPARENCY_PEN, 0);
	75	}
	76	}
	77	}
	78
	79	INLINE void draw_pixel(mame_bitmap bitmap,const rectangle cliprect,int x,int y,int color)
	80	{
	81	if (flip_screen)
	82	{
	83	x = bitmap->width - x - 1;
	84	y = bitmap->height - y - 1;
	85	}
	86
	87	if (x < cliprect->min_x \|\|
	88	x > cliprect->max_x \|\|
	89	y < cliprect->min_y \|\|
	90	y > cliprect->max_y)
	91	return;
	92
	93	*BITMAP_ADDR32(bitmap, y, x) = color;
	94	}
	95
	96	void gpworld_draw_sprites(mame_bitmap bitmap, const rectangle cliprect)
	97	{
	98	const int SPR_Y_TOP = 0;
	99	const int SPR_Y_BOTTOM = 1;
	100	const int SPR_X_LO = 2;
	101	const int SPR_X_HI = 3;
	102	const int SPR_SKIP_LO = 4;
	103	const int SPR_SKIP_HI = 5;
	104	const int SPR_GFXOFS_LO = 6;
	105	const int SPR_GFXOFS_HI = 7;
	106
	107	int i;
	108
	109	UINT8 *GFX = memory_region(REGION_GFX2);
	110
	111	/* Heisted from Daphne which heisted it from MAME */
	112	for (i = 0; i < 0x800; i += 8)
	113	{
	114	UINT8 *spr_reg = sprite_RAM + i;
	115
	116	if (spr_reg[SPR_Y_BOTTOM] && spr_reg[SPR_X_LO] != 0xff)
	117	{
	118	int row;
	119
	120	int src = spr_reg[SPR_GFXOFS_LO] + (spr_reg[SPR_GFXOFS_HI] << 8);
	121	int skip = spr_reg[SPR_SKIP_LO] + (spr_reg[SPR_SKIP_HI] << 8);
	122
	123	int height = spr_reg[SPR_Y_BOTTOM] - spr_reg[SPR_Y_TOP];
	124	int sy = spr_reg[SPR_Y_TOP] + 1;
	125	int sx = spr_reg[SPR_X_LO] + ((spr_reg[SPR_X_HI] & 0x01) << 8) ;
	126
	127	int sprite_color = (spr_reg[SPR_X_HI] >> 4) & 0x0f;
	128	int sprite_bank = (spr_reg[SPR_X_HI] >> 1) & 0x07;
	129
	130	/*
	131	logerror("%x - %x = %x\n", spr_reg[SPR_Y_BOTTOM], spr_reg[SPR_Y_TOP], height);
	132	logerror("Draw Sprite #%x with src %x, skip %x, height %x, y %x, x %x\n", i/8, src, skip, height, sy, sx);
	133
	134	logerror("%02x %02x %02x %02x %02x %02x %02x %02x\n", spr_reg[SPR_Y_TOP], spr_reg[SPR_Y_BOTTOM], spr_reg[SPR_X_LO], spr_reg[SPR_X_HI],
	135	spr_reg[SPR_SKIP_LO], spr_reg[SPR_SKIP_HI], spr_reg[SPR_GFXOFS_LO], spr_reg[SPR_GFXOFS_HI]);
	136	draw_pixel(bitmap,cliprect,sx,sy,0xffffffff);
	137	*/
	138
	139	for (row = 0; row < height; row++)
	140	{
	141	int x, y;
	142	int src2;
	143
	144	src = src2 = src + skip;
	145
	146	x = sx;
	147	y = sy+row;
	148
	149	while (1)
	150	{
	151	int data_lo, data_high;
	152	UINT8 pixel1, pixel2, pixel3, pixel4;
	153
	154	data_lo = GFX[(src2 & 0x7fff) \| (sprite_bank << 16)];
	155	data_high = GFX[(src2 & 0x7fff) \| 0x8000 \| (sprite_bank << 16)];
	156
	157	pixel1 = data_high >> 0x04;
	158	pixel2 = data_high & 0x0f;
	159	pixel3 = data_lo >> 0x04;
	160	pixel4 = data_lo & 0x0f;
	161
	162	/* we'll see if this is still applicable */
	163	if (src & 0x8000)
	164	{
	165	UINT8 temp_pixel;
	166	temp_pixel = pixel1;
	167	pixel1 = pixel4;
	168	pixel4 = temp_pixel;
	169
	170	temp_pixel = pixel2;
	171	pixel2 = pixel3;
	172	pixel3 = temp_pixel;
	173
	174	src2--;
	175	}
	176	else
	177	{
	178	src2++;
	179	}
	180
	181	/* Daphne says "don't draw the pixel if it's black". */
	182	draw_pixel(bitmap,cliprect,x+0,y,palette_get_color(Machine, pixel1 + (sprite_color*0x10 + 0x200)));
	183	draw_pixel(bitmap,cliprect,x+1,y,palette_get_color(Machine, pixel2 + (sprite_color*0x10 + 0x200)));
	184	draw_pixel(bitmap,cliprect,x+2,y,palette_get_color(Machine, pixel3 + (sprite_color*0x10 + 0x200)));
	185	draw_pixel(bitmap,cliprect,x+3,y,palette_get_color(Machine, pixel4 + (sprite_color*0x10 + 0x200)));
	186
	187	x += 4;
	188
	189	/* stop drawing when the sprite data is 0xf */
	190	if (((data_lo & 0x0f) == 0x0f) && (!(src & 0x8000)))
	191	{
	192	break;
	193	}
	194	else if ((src & 0x8000) && ((data_high & 0xf0) == 0xf0))
	195	{
	196	break;
	197	}
	198	}
	199	}
	200	}
	201	}
	202	}
	203
	204
	205	VIDEO_UPDATE( gpworld )
	206	{
	207	fillbitmap(bitmap, 0, cliprect);
	208
	209	gpworld_draw_tiles(machine, bitmap, cliprect);
	210	gpworld_draw_sprites(bitmap, cliprect);
	211
	212	/* display disc information */
	213	if (discinfo != NULL)
	214	popmessage("%s", laserdisc_describe_state(discinfo));
	215
	216	return 0;
	217	}
	218
	219
	220
	221	/* MEMORY HANDLERS */
	222	/* READS */
	223	READ8_HANDLER(ldp_read)
	224	{
	225	return ldp_read_latch;
	226	}
	227
	228	/* WRITES */
	229	WRITE8_HANDLER(ldp_write)
	230	{
	231	ldp_write_latch = data;
	232	}
	233
	234	WRITE8_HANDLER(misc_io_write)
	235	{
	236	start_lamp = (data & 0x04) >> 1;
	237	nmi_enable = (data & 0x40) >> 6;
	238	/* dunno = (data & 0x80) >> 7; */
	239
	240	logerror("NMI : %x (0x%x)\n", nmi_enable, data);
	241	}
	242
	243	WRITE8_HANDLER(palette_write)
	244	{
	245	/* This is all just a (bad) guess */
	246	int pal_index, r, g, b;
	247
	248	palette_RAM[offset] = data;
	249
	250	/* "Round down" to the nearest palette entry */
	251	pal_index = offset & 0xffe;
	252
	253	b = (palette_RAM[pal_index] & 0xf0) << 0;
	254	g = (palette_RAM[pal_index] & 0x0f) << 4;
	255	r = (palette_RAM[pal_index+1] & 0x0f) << 4;
	256	/* int dunno = (palette_RAM[pal_index+1] & 0x80) >> 7; */
	257
	258	/* logerror("PAL WRITE index : %x rgb : %d %d %d (real %x) at %x\n", pal_index, r,g,b, data, offset); */
	259
	260	palette_set_color(Machine, pal_index, MAKE_RGB(r, g, b));
	261	}
	262
	263	/* PROGRAM MAP */
	264	static ADDRESS_MAP_START( mainmem, ADDRESS_SPACE_PROGRAM, 8 )
	265	AM_RANGE(0x0000,0xbfff) AM_ROM
	266	AM_RANGE(0xc000,0xc7ff) AM_RAM AM_BASE(&sprite_RAM)
	267	AM_RANGE(0xc800,0xcfff) AM_WRITE(palette_write) AM_BASE(&palette_RAM) /* The memory test reads at 0xc800 */
	268	AM_RANGE(0xd000,0xd7ff) AM_RAM AM_BASE(&tile_RAM)
	269	AM_RANGE(0xd800,0xd800) AM_READWRITE(ldp_read,ldp_write)
	270	/* AM_RANGE(0xd801,0xd801) AM_READ(???) */
	271	AM_RANGE(0xda00,0xda00) AM_READ_PORT("INWHEEL")
	272	/* AM_RANGE(0xda01,0xda01) AM_WRITE(???) / / These inputs are interesting - there are writes and reads all over these addr's */
	273	/* AM_RANGE(0xda02,0xda02) AM_READ_PORT("???") / / Reads here during the input test. */
	274	AM_RANGE(0xda20,0xda20) AM_READ_PORT("INACCEL") /* Seems to control both the brake and accel at once - maybe tied to 0xda02? Or to the writes here... */
	275
	276	AM_RANGE(0xe000,0xffff) AM_RAM /* Potentially not all work RAM? */
	277	ADDRESS_MAP_END
	278
	279
	280	/* I/O MAP */
	281	static ADDRESS_MAP_START( mainport, ADDRESS_SPACE_IO, 8 )
	282	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
	283	AM_RANGE(0x01,0x01) AM_WRITE(misc_io_write)
	284	AM_RANGE(0x80,0x80) AM_READ_PORT("IN0")
	285	AM_RANGE(0x81,0x81) AM_READ_PORT("IN1")
	286	AM_RANGE(0x82,0x82) AM_READ_PORT("DSW1")
	287	AM_RANGE(0x83,0x83) AM_READ_PORT("DSW2")
	288	ADDRESS_MAP_END
	289
	290
	291	/* PORTS */
	292	INPUT_PORTS_START( gpworld )
	293	PORT_START_TAG("IN0")
	294	PORT_BIT ( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
	295	PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	296	PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	297	PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	298	PORT_BIT ( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME( "SHIFT" ) PORT_CODE( KEYCODE_Q )
	299	PORT_BIT ( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	300	PORT_BIT ( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	301	PORT_BIT ( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	302
	303	PORT_START_TAG("IN1")
	304	PORT_BIT ( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
	305	PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) /* maybe? it's not listed in the test screen. */
	306	PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_SERVICE )
	307	PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_SERVICE1 )
	308	PORT_BIT ( 0x10, IP_ACTIVE_LOW, IPT_START1 )
	309	PORT_BIT ( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	310	PORT_BIT ( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	311	PORT_BIT ( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	312
	313	PORT_START_TAG("INWHEEL")
	314	PORT_BIT ( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME( "SLIGHT RIGHT" ) PORT_CODE( KEYCODE_Y )
	315	PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME( "MEDIUM RIGHT" ) PORT_CODE( KEYCODE_U )
	316	PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME( "STRONG RIGHT" ) PORT_CODE( KEYCODE_I )
	317	PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME( "FIERCE RIGHT" ) PORT_CODE( KEYCODE_O )
	318	PORT_BIT ( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME( "SLIGHT LEFT" ) PORT_CODE( KEYCODE_T )
	319	PORT_BIT ( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME( "MEDIUM LEFT" ) PORT_CODE( KEYCODE_R )
	320	PORT_BIT ( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME( "STRONG LEFT" ) PORT_CODE( KEYCODE_E )
	321	PORT_BIT ( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME( "FIERCE LEFT" ) PORT_CODE( KEYCODE_W )
	322
	323	PORT_START_TAG("INACCEL") /* both accelerator & brake right now :P */
	324	PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(30) PORT_KEYDELTA(10) PORT_PLAYER(1)
	325
	326	PORT_START_TAG("DSW1")
	327	PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:1,2,3,4")
	328	PORT_DIPSETTING( 0x70, DEF_STR( 4C_1C ) )
	329	PORT_DIPSETTING( 0x80, DEF_STR( 3C_1C ) )
	330	PORT_DIPSETTING( 0x90, DEF_STR( 2C_1C ) )
	331	PORT_DIPSETTING( 0x40, DEF_STR( 4C_3C ) )
	332	PORT_DIPSETTING( 0x50, "6 Coins/4 Credits" )
	333	PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
	334	PORT_DIPSETTING( 0x00, "1 Coin/1 Credit (again)" )
	335	PORT_DIPSETTING( 0x30, "5 Coins/6 Credits" )
	336	PORT_DIPSETTING( 0x20, DEF_STR( 4C_5C ) )
	337	PORT_DIPSETTING( 0x10, DEF_STR( 2C_3C ) )
	338	PORT_DIPSETTING( 0x60, "2 Coins/3 Credits (again)" )
	339	PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
	340	PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
	341	PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
	342	PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
	343	PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
	344	PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:5,6,7,8")
	345	PORT_DIPSETTING( 0x07, DEF_STR( 4C_1C ) )
	346	PORT_DIPSETTING( 0x08, DEF_STR( 3C_1C ) )
	347	PORT_DIPSETTING( 0x09, DEF_STR( 2C_1C ) )
	348	PORT_DIPSETTING( 0x04, DEF_STR( 4C_3C ) )
	349	PORT_DIPSETTING( 0x05, "6 Coins/4 Credits" )
	350	PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
	351	PORT_DIPSETTING( 0x00, "1 Coin/1 Credit (again)" )
	352	PORT_DIPSETTING( 0x03, "5 Coins/6 Credits" )
	353	PORT_DIPSETTING( 0x02, DEF_STR( 4C_5C ) )
	354	PORT_DIPSETTING( 0x01, DEF_STR( 2C_3C ) )
	355	PORT_DIPSETTING( 0x06, "2 Coins/3 Credits (again)" )
	356	PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
	357	PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
	358	PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
	359	PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
	360	PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) )
	361
	362	PORT_START_TAG("DSW2")
	363	PORT_DIPNAME( 0x10, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:1")
	364	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	365	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	366	PORT_DIPNAME( 0x60, 0x60, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:2,3")
	367	PORT_DIPSETTING( 0x40, DEF_STR( Easy ) )
	368	PORT_DIPSETTING( 0x60, DEF_STR( Medium ) )
	369	PORT_DIPSETTING( 0x20, DEF_STR( Hard ) )
	370	PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
	371	PORT_DIPNAME( 0x80, 0x80, "Start Year #" ) PORT_DIPLOCATION("SW2:4")
	372	PORT_DIPSETTING( 0x80, "1984" )
	373	PORT_DIPSETTING( 0x00, "1985" )
	374	PORT_DIPNAME( 0x01, 0x01, "Steering Difficulty" ) PORT_DIPLOCATION("SW2:5")
	375	PORT_DIPSETTING( 0x01, DEF_STR( Medium ) )
	376	PORT_DIPSETTING( 0x00, DEF_STR( Hard ) )
	377	PORT_DIPNAME( 0x02, 0x02, "Rank to advance" ) PORT_DIPLOCATION("SW2:6")
	378	PORT_DIPSETTING( 0x02, "Fourth" )
	379	PORT_DIPSETTING( 0x00, "Third" )
	380	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:7")
	381	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	382	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	383	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:8")
	384	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	385	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	386	INPUT_PORTS_END
	387
	388	static MACHINE_START( gpworld )
	389	{
	390	discinfo = laserdisc_init(LASERDISC_TYPE_LDV1000, get_disk_handle(0), 0);
	391	return;
	392	}
	393
	394	static TIMER_CALLBACK( irq_stop )
	395	{
	396	cpunum_set_input_line(0, 0, CLEAR_LINE);
	397	}
	398
	399	static INTERRUPT_GEN( vblank_callback_gpworld )
	400	{
	401	/* Do an NMI if the enabled bit is set */
	402	if (nmi_enable)
	403	{
	404	laserdisc_data_w(discinfo,ldp_write_latch);
	405	ldp_read_latch = laserdisc_data_r(discinfo);
	406	cpunum_set_input_line(0, INPUT_LINE_NMI, PULSE_LINE);
	407	}
	408
	409	/* The time the IRQ line stays high is set just long enough to happen after the NMI - hacky? */
	410	cpunum_set_input_line(0, 0, ASSERT_LINE);
	411	mame_timer_set(MAME_TIME_IN_USEC(100), 0, irq_stop);
	412
	413	laserdisc_vsync(discinfo);
	414	}
	415
	416	static const gfx_layout gpworld_tile_layout =
	417	{
	418	8,8,
	419	0x800/8,
	420	2,
	421	{ 0, 0x800*8 },
	422	{ 0,1,2,3,4,5,6,7 },
	423	{ 08, 18, 28, 38, 48, 58, 68, 78 },
	424	8*8
	425	};
	426
	427	static GFXDECODE_START( gpworld )
	428	GFXDECODE_ENTRY(REGION_GFX1, 0, gpworld_tile_layout, 0x0, 0x100)
	429	GFXDECODE_END
	430
	431	/* DRIVER */
	432	static MACHINE_DRIVER_START( gpworld )
	433	/* main cpu */
	434	MDRV_CPU_ADD(Z80, GUESSED_CLOCK)
	435	MDRV_CPU_PROGRAM_MAP(mainmem,0)
	436	MDRV_CPU_IO_MAP(mainport,0)
	437	MDRV_CPU_VBLANK_INT(vblank_callback_gpworld, 1)
	438
	439	MDRV_MACHINE_START(gpworld)
	440
	441	/* video */
	442	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
	443
	444	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
	445	MDRV_SCREEN_REFRESH_RATE(60)
	446	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
	447	MDRV_SCREEN_SIZE(648, 328)
	448	MDRV_SCREEN_VISIBLE_AREA(08, 648-1, 08, 328-1)
	449
	450	MDRV_GFXDECODE(gpworld)
	451	MDRV_PALETTE_LENGTH(1024)
	452	MDRV_VIDEO_UPDATE(gpworld)
	453
	454	MACHINE_DRIVER_END
	455
	456
	457	ROM_START( gpworld )
	458	ROM_REGION( 0xc000, REGION_CPU1, 0 )
	459	ROM_LOAD( "epr6162a.ic51", 0x0000, 0x4000, CRC(70e42574) SHA1(2fa50c7a67a2efb6b2c313850ace40e42d18b0a8) )
	460	ROM_LOAD( "epr6163.ic67", 0x4000, 0x4000, CRC(49539e46) SHA1(7cfd5b6b356c3fa5439e6fe3ac2e6a097b722a2c) )
	461	ROM_LOAD( "epr6164.ic83", 0x8000, 0x4000, CRC(7f0e6853) SHA1(c255ac6e4b61faa8da9b5aa70f12c868b81acfe1) )
	462
	463	/* Tiles */
	464	ROM_REGION( 0x1000, REGION_GFX1, ROMREGION_DISPOSE )
	465	ROM_LOAD( "epr6148.ic18", 0x0000, 0x1000, CRC(a4b11cf5) SHA1(9697494335089b13071d773812eec373ef5b358c) )
	466
	467	/* Sprites */
	468	ROM_REGION( 0x30000, REGION_GFX2, 0 )
	469	ROM_LOAD( "epr6149.ic111", 0x00000, 0x4000, CRC(7e6c4797) SHA1(acf934e1f3f55a0d1cd1630f6a78f9954f1ec53f) )
	470	ROM_LOAD( "epr6151.ic110", 0x04000, 0x4000, CRC(26d72b96) SHA1(759ef85877edfc37f2a1a242bf1c9b0e8d5e9a88) )
	471	ROM_LOAD( "epr6150.ic128", 0x08000, 0x4000, CRC(6837e095) SHA1(b2ac8341fcf0037d186b0759227597643ca0336d) )
	472	ROM_LOAD( "epr6152.ic127", 0x0c000, 0x4000, CRC(86939fe2) SHA1(07527297262297562e052672976fd6f7124f5c7b) )
	473	ROM_LOAD( "epr6153.ic109", 0x10000, 0x4000, CRC(f52b7c1b) SHA1(326c6b46e85ab12b43ae2b6b7a49055fe5c31431) )
	474	ROM_LOAD( "epr6155.ic108", 0x14000, 0x4000, CRC(a020bd03) SHA1(13cd81dc2df185d9ec989e69261d275b46e44075) )
	475	ROM_LOAD( "epr6154.ic126", 0x18000, 0x4000, CRC(bbf5d7db) SHA1(3dc50fa0dfe285cc741d9d6b9bac4a0ff6e3877f) )
	476	ROM_LOAD( "epr6156.ic125", 0x1c000, 0x4000, CRC(2c03c64c) SHA1(fa31e49385e004b6fb81c8d54cc6b64dfe1358d2) )
	477	ROM_LOAD( "epr6157.ic107", 0x20000, 0x4000, CRC(cdd31036) SHA1(722d843a1c524b0a689ab73bb7367c4ca33fc983) )
	478	/* ic106 Unpopulated? */
	479	ROM_LOAD( "epr6158.ic124", 0x28000, 0x4000, CRC(d15ac707) SHA1(170e0a851c3e845330f776a53ca619d16d025dd7) )
	480	/* ic123 Unpopulated? */
	481
	482	/* Misc PROMs */
	483	ROM_REGION( 0x0220, REGION_PROMS, 0 )
	484	ROM_LOAD( "pr6146.ic2", 0x000, 0x020, CRC(d10801a0) SHA1(89e9ac0d9c9eee6efd5455a3416c436ceda8f632) )
	485	ROM_LOAD( "pr6147.ic28", 0x020, 0x100, CRC(b7173df9) SHA1(044beda43cb1793033021a08b3ee3441d5ffe6c3) )
	486	ROM_LOAD( "pr5501.ic14", 0x120, 0x100, CRC(1bdf71d4) SHA1(ac52e948cce6df4abb7543c08e2c6454efd63e79) )
	487	ROM_END
	488
	489
	490	static DRIVER_INIT( gpworld )
	491	{
	492	nmi_enable = 0;
	493	start_lamp = 0;
	494	ldp_write_latch = ldp_read_latch = 0;
	495	}
	496
	497
	498	/* YEAR NAME PARENT MACHINE INPUT INIT MONITOR COMPANY FULLNAME FLAGS) */
	499	GAME( 1984, gpworld, 0, gpworld, gpworld, gpworld, ROT0, "SEGA", "GP World", GAME_NOT_WORKING\|GAME_NO_SOUND)

src/mame/drivers/cabal.c
r1103	r1104
64	64
65	65	/******************************************************************************************/
66	66
67		// we should emulate the z80s, not simulate them
68		#if 0
69		static struct cabalbl_adpcm_state
70		{
71		struct adpcm_state adpcm;
72		sound_stream *stream;
73		UINT32 current, end;
74		UINT8 nibble;
75		UINT8 playing;
76		UINT8 allocated;
77		UINT8 *base;
78		} cabalbl_adpcm[2];
79
80		static void cabalbl_adpcm_callback(void param, stream_sample_t inputs, stream_sample_t *outputs, int samples)
81		{
82		struct cabalbl_adpcm_state *state = param;
83		stream_sample_t *dest = outputs[0];
84
85		while (state->playing && samples > 0)
86		{
87		int val = (state->base[state->current] >> state->nibble) & 15;
88
89		state->nibble ^= 4;
90		if (state->nibble == 4)
91		{
92		state->current++;
93		if (state->current >= state->end)
94		state->playing = 0;
95		}
96
97		*dest++ = clock_adpcm(&state->adpcm, val);
98		samples--;
99		}
100		while (samples > 0)
101		{
102		*dest++ = 0;
103		samples--;
104		}
105		}
106
107		void cabalbl_adpcm_start(int clock, const struct CustomSound_interface config)
108		{
109		int i;
110
111		for (i = 0; i < 2; i++)
112		if (!cabalbl_adpcm[i].allocated)
113		{
114		struct cabalbl_adpcm_state *state = &cabalbl_adpcm[i];
115		state->allocated = 1;
116		state->playing = 0;
117		state->stream = stream_create(0, 1, clock, state, cabalbl_adpcm_callback);
118		state->base = memory_region(REGION_SOUND1);
119		reset_adpcm(&state->adpcm);
120		return state;
121		}
122		return NULL;
123		}
124
125		void cabalbl_adpcm_stop(void *token)
126		{
127		struct cabalbl_adpcm_state *state = token;
128		state->allocated = 0;
129		}
130
131		static void cabalbl_play_adpcm( int channel, int which ){
132		if( which!=0xff ){
133		UINT8 *RAM = memory_region(REGION_SOUND1);
134		int offset = channel*0x10000;
135		int start,len;
136
137		which = which&0x7f;
138		if( which ){
139		which = which*2+0x100;
140		start = RAM[offset+which] + 256*RAM[offset+which+1];
141		len = (RAM[offset+start]256 + RAM[offset+start+1])2;
142		start+=2;
143
144		if (cabalbl_adpcm[channel].stream)
145		stream_update(cabalbl_adpcm[channel].stream);
146		cabalbl_adpcm[channel].current = start + offset;
147		cabalbl_adpcm[channel].end = start + offset + len/2;
148		cabalbl_adpcm[channel].nibble = 4;
149		cabalbl_adpcm[channel].playing = 1;
150		cabalbl_adpcm[channel].base = RAM;
151		}
152		}
153		}
154		#endif
155	67	static WRITE16_HANDLER( cabalbl_sndcmd_w )
156	68	{
157	69	switch (offset)
r1103	r1104
270	182	/*********************************************************************/
271	183
272	184
273		static READ8_HANDLER( cabalbl_snd_r )
	185	static READ8_HANDLER( cabalbl_snd2_r )
274	186	{
275		switch(offset){
276		case 0x06: return input_port_3_r(0);
277		case 0x08: return cabal_sound_command2;
278		case 0x0a: return cabal_sound_command1;
279		default: return(0xff);
280		}
	187	return cabal_sound_command2;
281	188	}
282	189
283		static WRITE8_HANDLER( cabalbl_snd_w )
	190	static READ8_HANDLER( cabalbl_snd1_r )
284	191	{
285		#if 0
286		switch( offset ){
287		case 0x00: cabalbl_play_adpcm( 0, data ); break;
288		case 0x02: cabalbl_play_adpcm( 1, data ); break;
289		}
290		#endif
	192	return cabal_sound_command1;
291	193	}
292	194
	195	static WRITE8_HANDLER( cabalbl_coin_w )
	196	{
	197	coin_counter_w(0, data & 1);
	198	coin_counter_w(1, data & 2);
	199
	200	//data & 0x40? video enable?
	201	}
	202
293	203	static ADDRESS_MAP_START( readmem_sound, ADDRESS_SPACE_PROGRAM, 8 )
294	204	AM_RANGE(0x0000, 0x1fff) AM_READ(MRA8_ROM)
295	205	AM_RANGE(0x2000, 0x27ff) AM_READ(MRA8_RAM)
r1103	r1104
320	230	static ADDRESS_MAP_START( cabalbl_readmem_sound, ADDRESS_SPACE_PROGRAM, 8 )
321	231	AM_RANGE(0x0000, 0x1fff) AM_READ(MRA8_ROM)
322	232	AM_RANGE(0x2000, 0x2fff) AM_READ(MRA8_RAM)
323		AM_RANGE(0x4000, 0x400d) AM_READ(cabalbl_snd_r)
	233	AM_RANGE(0x4008, 0x4008) AM_READ(cabalbl_snd2_r)
	234	AM_RANGE(0x400a, 0x400a) AM_READ(cabalbl_snd1_r)
	235	AM_RANGE(0x4006, 0x4006) AM_READ(input_port_3_r)
324	236	AM_RANGE(0x400f, 0x400f) AM_READ(YM2151_status_port_0_r)
325	237	AM_RANGE(0x8000, 0xffff) AM_READ(MRA8_ROM)
326	238	ADDRESS_MAP_END
r1103	r1104
328	240	static ADDRESS_MAP_START( cabalbl_writemem_sound, ADDRESS_SPACE_PROGRAM, 8 )
329	241	AM_RANGE(0x0000, 0x1fff) AM_WRITE(MWA8_ROM)
330	242	AM_RANGE(0x2000, 0x2fff) AM_WRITE(MWA8_RAM)
331		AM_RANGE(0x4000, 0x4002) AM_WRITE(cabalbl_snd_w)
	243	AM_RANGE(0x4000, 0x4000) AM_WRITE(soundlatch3_w)
	244	AM_RANGE(0x4002, 0x4002) AM_WRITE(soundlatch4_w)
	245	AM_RANGE(0x4004, 0x4004) AM_WRITE(cabalbl_coin_w)
332	246	AM_RANGE(0x400c, 0x400c) AM_WRITE(soundlatch2_w)
333	247	AM_RANGE(0x400e, 0x400e) AM_WRITE(YM2151_register_port_0_w)
334	248	AM_RANGE(0x400f, 0x400f) AM_WRITE(YM2151_data_port_0_w)
335		AM_RANGE(0x6000, 0x6000) AM_WRITE(MWA8_NOP) /???/
	249	AM_RANGE(0x6000, 0x6000) AM_WRITE(MWA8_NOP) /* ??? */
336	250	AM_RANGE(0x8000, 0xffff) AM_WRITE(MWA8_ROM)
337	251	ADDRESS_MAP_END
338	252
339	253	/* the bootleg has 2x z80 sample players */
340	254
341		READ8_HANDLER( cabalbl_ta~~lk1_~~p~~ort~~00_r )
	255	static WRITE8_HANDLER( cabalbl_adpcm_0_w )
342	256	{
343		return mame_rand(Machine);
	257	MSM5205_reset_w(0,(data>>7)&1);
	258	/* ?? bit 6?? */
	259	MSM5205_data_w(0,data);
	260	MSM5205_vclk_w(0,1);
	261	MSM5205_vclk_w(0,0);
344	262	}
345	263
	264	static WRITE8_HANDLER( cabalbl_adpcm_1_w )
	265	{
	266	MSM5205_reset_w(1,(data>>7)&1);
	267	/* ?? bit 6?? */
	268	MSM5205_data_w(1,data);
	269	MSM5205_vclk_w(1,1);
	270	MSM5205_vclk_w(1,0);
	271	}
	272
346	273	static ADDRESS_MAP_START( cabalbl_talk1_map, ADDRESS_SPACE_PROGRAM, 8 )
347		AM_RANGE(0x0000, 0xffff) AM_READWRITE~~(MRA8_ROM, MWA8_~~NOP)
	274	AM_RANGE(0x0000, 0xffff) AM_ROM AM_WRITENOP
348	275	ADDRESS_MAP_END
349	276
350	277	static ADDRESS_MAP_START( cabalbl_talk1_portmap, ADDRESS_SPACE_IO, 8 )
351	278	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
352		AM_RANGE(0x00, 0x00) AM_READ(cabalbl_talk1_port00_r)
353		AM_RANGE(0x01, 0x01) AM_WRITE(MWA8_NOP) // DAC output?
	279	AM_RANGE(0x00, 0x00) AM_READ(soundlatch3_r)
	280	AM_RANGE(0x01, 0x01) AM_WRITE(cabalbl_adpcm_0_w)
354	281	ADDRESS_MAP_END
355	282
356		READ8_HANDLER( cabalbl_talk2_port00_r )
357		{
358		return mame_rand(Machine);
359		}
360
361	283	static ADDRESS_MAP_START( cabalbl_talk2_map, ADDRESS_SPACE_PROGRAM, 8 )
362		AM_RANGE(0x0000, 0xffff) AM_READWRITE~~(MRA8_ROM, MWA8_~~NOP)
	284	AM_RANGE(0x0000, 0xffff) AM_ROM AM_WRITENOP
363	285	ADDRESS_MAP_END
364	286
365	287	static ADDRESS_MAP_START( cabalbl_talk2_portmap, ADDRESS_SPACE_IO, 8 )
366	288	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
367		AM_RANGE(0x00, 0x00) AM_READ(cabalbl_talk2_port00_r)
368		AM_RANGE(0x01, 0x01) AM_WRITE(MWA8_NOP) // DAC output?
	289	AM_RANGE(0x00, 0x00) AM_READ(soundlatch4_r)
	290	AM_RANGE(0x01, 0x01) AM_WRITE(cabalbl_adpcm_1_w)
369	291	ADDRESS_MAP_END
370	292
371	293	/***************************************************************************/
r1103	r1104
582	504	64*16
583	505	};
584	506
	507
	508
585	509	static GFXDECODE_START( cabal )
586		GFXDECODE_ENTRY( REGION_GFX1, 0, text_layout, 0, 1024/4 )
587		GFXDECODE_ENTRY( REGION_GFX2, 0, tile_layout, 32*16, 16 )
588		GFXDECODE_ENTRY( REGION_GFX3, 0, sprite_layout, 16*16, 16 )
	510	GFXDECODE_ENTRY( REGION_GFX1, 0x000000, text_layout, 0, 1024/4 )
	511	GFXDECODE_ENTRY( REGION_GFX2, 0x000000, tile_layout, 32*16, 16 )
	512	GFXDECODE_ENTRY( REGION_GFX3, 0x000000, sprite_layout, 16*16, 16 )
589	513	GFXDECODE_END
590	514
591	515
592
593	516	static struct YM2151interface ym2151_interface =
594	517	{
595	518	seibu_ym3812_irqhandler
r1103	r1104
607	530
608	531	SEIBU_SOUND_SYSTEM_ADPCM_HARDWARE
609	532
	533	static struct MSM5205interface msm5205_interface_1 =
	534	{
	535	0,
	536	MSM5205_SEX_4B
	537	};
610	538
	539	static struct MSM5205interface msm5205_interface_2 =
	540	{
	541	0,
	542	MSM5205_SEX_4B
	543	};
611	544
612	545	static MACHINE_DRIVER_START( cabal )
613	546
r1103	r1104
647	580	MDRV_SOUND_CONFIG(adpcm_interface)
648	581	MDRV_SOUND_ROUTE(ALL_OUTPUTS,"mono", 0.40)
649	582
	583
650	584	MDRV_SOUND_ADD(CUSTOM, 8000)
651	585	MDRV_SOUND_CONFIG(adpcm_interface)
652	586	MDRV_SOUND_ROUTE(ALL_OUTPUTS,"mono", 0.40)
653	587	MACHINE_DRIVER_END
654	588
655		#if 0
656		static struct CustomSound_interface cabalbl_adpcm_interface =
657		{
658		cabalbl_adpcm_start,
659		cabalbl_adpcm_stop
660		};
661		#endif
662	589
663	590	/* the bootleg has different sound hardware (2 extra Z80s for ADPCM playback) */
664	591	static MACHINE_DRIVER_START( cabalbl )
r1103	r1104
675	602	MDRV_CPU_ADD(Z80, 4000000)
676	603	MDRV_CPU_PROGRAM_MAP(cabalbl_talk1_map,0)
677	604	MDRV_CPU_IO_MAP(cabalbl_talk1_portmap,0)
678		MDRV_CPU_~~VBLANK~~_INT(irq0_line_hold,10)
	605	MDRV_CPU_PERIODIC_INT(irq0_line_hold,8000)
679	606
680	607	MDRV_CPU_ADD(Z80, 4000000)
681	608	MDRV_CPU_PROGRAM_MAP(cabalbl_talk2_map,0)
682	609	MDRV_CPU_IO_MAP(cabalbl_talk2_portmap,0)
683		MDRV_CPU_~~VBLANK~~_INT(irq0_line_hold,10)
	610	MDRV_CPU_PERIODIC_INT(irq0_line_hold,8000)
684	611
685
686	612	MDRV_SCREEN_REFRESH_RATE(60)
687	613	MDRV_SCREEN_VBLANK_TIME(DEFAULT_REAL_60HZ_VBLANK_DURATION)
688	614	MDRV_INTERLEAVE(10)
r1103	r1104
707	633	MDRV_SOUND_CONFIG(cabalbl_ym2151_interface)
708	634	MDRV_SOUND_ROUTE(ALL_OUTPUTS,"mono", 0.80)
709	635
710		// MDRV_SOUND_ADD(CUSTOM, 8000)
711		// MDRV_SOUND_CONFIG(cabalbl_adpcm_interface)
712		// MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.40)
	636	MDRV_SOUND_ADD(MSM5205, 384000)
	637	MDRV_SOUND_CONFIG(msm5205_interface_1)
	638	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.60)
713	639
714		// MDRV_SOUND_ADD(CUSTOM, 8000)
715		// MDRV_SOUND_CONFIG(cabalbl_adpcm_interface)
716		// MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.40)
	640	MDRV_SOUND_ADD(MSM5205, 384000)
	641	MDRV_SOUND_CONFIG(msm5205_interface_2)
	642	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.60)
717	643	MACHINE_DRIVER_END
718	644
719	645	ROM_START( cabal )

src/mame/drivers/pacman.c
r1103	r1104
1647	1647	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
1648	1648	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
1649	1649	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
1650		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_~~UNU~~SED ) /* ?? */
	1650	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE2 ) /* Audio Test? */
1651	1651	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
1652	1652	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
1653	1653	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
r1103	r1104
1657	1657	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_COCKTAIL
1658	1658	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_COCKTAIL
1659	1659	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_COCKTAIL
1660		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED ) /* Protection */
	1660	PORT_DIPNAME( 0x10, 0x10, "Teleport Holes" )
	1661	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	1662	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1661	1663	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
1662	1664	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
1663		PORT_BIT( 0x80, IP_ACTIVE_LOW~~, IPT_UNUSED~~ ) ~~/* service mode? */~~
	1665	PORT_SERVICE( 0x80, IP_ACTIVE_LOW)
1664	1666
1665	1667	PORT_START
1666		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ))
1667		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1668		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1669		PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
1670		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1671		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1672		PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
1673		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1674		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1675		PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
1676		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1677		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1678		PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
1679		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1680		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1681		PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
1682		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1683		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1684		PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
1685		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1686		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1687		PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
1688		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1689		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1668	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ) )
	1669	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	1670	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1671	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
	1672	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	1673	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1674	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
	1675	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	1676	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1677	PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
	1678	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	1679	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1680	/* These last dips seems doesn't works in the test input, why? */
	1681	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	1682	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	1683	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1684	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	1685	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	1686	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1687	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	1688	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	1689	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1690	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	1691	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	1692	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1690	1693
1691		/* Coinage dips, more complex than crush? */
1692	1694	PORT_START
1693		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ))
1694		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1695		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1696		PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
1697		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1698		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1699		PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
1700		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1701		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1702		PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
1703		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1704		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1705		PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
1706		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1707		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1708		PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
1709		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1710		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1711		PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
1712		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1713		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1714		PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
1715		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1716		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1695	PORT_DIPNAME( 0x0f, 0x00, DEF_STR( Coin_A ) )
	1696	PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
	1697	PORT_DIPSETTING( 0x09, DEF_STR( 2C_2C ) )
	1698	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
	1699	PORT_DIPSETTING( 0x0a, DEF_STR( 2C_3C ) )
	1700	PORT_DIPSETTING( 0x0b, DEF_STR( 2C_4C ) )
	1701	PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) )
	1702	PORT_DIPSETTING( 0x0c, DEF_STR( 2C_5C ) )
	1703	PORT_DIPSETTING( 0x0d, DEF_STR( 2C_6C ) )
	1704	PORT_DIPSETTING( 0x02, DEF_STR( 1C_3C ) )
	1705	PORT_DIPSETTING( 0x0e, DEF_STR( 2C_7C ) )
	1706	PORT_DIPSETTING( 0x0f, DEF_STR( 2C_8C ) )
	1707	PORT_DIPSETTING( 0x03, DEF_STR( 1C_4C ) )
	1708	PORT_DIPSETTING( 0x04, DEF_STR( 1C_5C ) )
	1709	PORT_DIPSETTING( 0x05, DEF_STR( 1C_6C ) )
	1710	PORT_DIPSETTING( 0x06, DEF_STR( 1C_7C ) )
	1711	PORT_DIPSETTING( 0x07, DEF_STR( 1C_8C ) )
	1712	PORT_DIPNAME( 0xf0, 0x00, DEF_STR( Coin_B ) )
	1713	PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
	1714	PORT_DIPSETTING( 0x90, DEF_STR( 2C_2C ) )
	1715	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
	1716	PORT_DIPSETTING( 0xa0, DEF_STR( 2C_3C ) )
	1717	PORT_DIPSETTING( 0xb0, DEF_STR( 2C_4C ) )
	1718	PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
	1719	PORT_DIPSETTING( 0xc0, DEF_STR( 2C_5C ) )
	1720	PORT_DIPSETTING( 0xd0, DEF_STR( 2C_6C ) )
	1721	PORT_DIPSETTING( 0x20, DEF_STR( 1C_3C ) )
	1722	PORT_DIPSETTING( 0xe0, DEF_STR( 2C_7C ) )
	1723	PORT_DIPSETTING( 0xf0, DEF_STR( 2C_8C ) )
	1724	PORT_DIPSETTING( 0x30, DEF_STR( 1C_4C ) )
	1725	PORT_DIPSETTING( 0x40, DEF_STR( 1C_5C ) )
	1726	PORT_DIPSETTING( 0x50, DEF_STR( 1C_6C ) )
	1727	PORT_DIPSETTING( 0x60, DEF_STR( 1C_7C ) )
	1728	PORT_DIPSETTING( 0x70, DEF_STR( 1C_8C ) )
1717	1729	INPUT_PORTS_END
1718	1730
1719	1731
r1103	r1104
5077	5089	ROM_LOAD( "18.aux", 0x3c000, 0x4000, CRC(feb195fd) SHA1(5677d31e526cc7752254e9af0d694f05bc6bc907) )
5078	5090	ROM_END
5079	5091
	5092	/* Special thanks to Rob Walmsley for dumping his PCB */
5080	5093	ROM_START( cannonbp )
5081	5094	ROM_REGION( 0x10000, REGION_CPU1, 0 )
5082	5095	ROM_LOAD( "n1-6e", 0x0000, 0x0800, CRC(c68878c7) SHA1(4ab69f820e861a33fa7555286459e5953c126d33) )
r1103	r1104
5085	5098	ROM_LOAD( "n4-6m", 0x1800, 0x0800, CRC(fcc57ecb) SHA1(9efafbb7f3d44652aded860e734332f47354e299) )
5086	5099	ROM_LOAD( "n5-6h", 0x2000, 0x0800, CRC(52846c9d) SHA1(4a479ff8961c8865aea12976355d0201a8cb1b48) )
5087	5100	ROM_LOAD( "n6-6n", 0x2800, 0x0800, CRC(59e890dd) SHA1(c148b71d71fb49a138ef1afe771be70bec21ad2b) )
	5101	/* 3000 - 3fff = epoxy protection block */
5088	5102
5089	5103	ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
5090	5104	ROM_LOAD( "z1-5e", 0x0000, 0x0800, CRC(125779e0) SHA1(c1ae7214e3ff1a941ae0c4948ec886bc84b6f040) )
r1103	r1104
5092	5106	ROM_LOAD( "z2-5f", 0x1000, 0x0800, CRC(fbd2c99d) SHA1(135a5d86d59010cc608b099054815dd31d443da7) )
5093	5107	ROM_LOAD( "z4-5j", 0x1800, 0x0800, CRC(8734c904) SHA1(86d9dc72d3cfc863c558967860ac4d2dc8d2c07c) )
5094	5108
5095		ROM_REGION( 0x0120, REGION_PROMS, 0 ) /* these are from crush roller, just so we can see what's going on */
5096		ROM_LOAD( "colorprom_1", 0x0000, 0x0020, BAD_DUMP CRC(2fc650bd) SHA1(8d0268dee78e47c712202b0ec4f1f51109b1f2a5) )
5097		ROM_LOAD( "colorprom_2", 0x0020, 0x0100, BAD_DUMP CRC(63efb927) SHA1(5c144a613fc4960a1dfd7ead89e7fee258a63171) )
	5109	ROM_REGION( 0x0120, REGION_PROMS, 0 ) /* these give some ugly colours, but should be correct */
	5110	ROM_LOAD( "colorprom_1", 0x0000, 0x0020, CRC(08f8ae7e) SHA1(cd1e26da5f214f4d9924a30e6d9cf312f91c2028) )
	5111	ROM_LOAD( "colorprom_2", 0x0020, 0x0100, CRC(359a15dc) SHA1(e57ef15eb3baac70fe9e2db897c4165da3c00e20) )
5098	5112
5099	5113	ROM_REGION( 0x0200, REGION_SOUND1, 0 ) /* sound PROMs */
5100	5114	ROM_LOAD( "82s126.1m", 0x0000, 0x0100, CRC(a9cc86bf) SHA1(bbcec0570aeceb582ff8238a4bc8546a23430081) )

src/mame/drivers/srmp6.c
r1103	r1104
91	91
92	92	void update_palette(void)
93	93	{
94		~~char~~ r, g ,b;
	94	INT8 r, g ,b;
95	95	int brg = brightness - 0x60;
96	96	int i;
97	97
r1103	r1104
545	545
546	546	WRITE16_HANDLER(paletteram_w)
547	547	{
548		~~char~~ r, g, b;
	548	INT8 r, g, b;
549	549	int brg = brightness - 0x60;
550	550
551	551	paletteram16_xBBBBBGGGGGRRRRR_word_w(offset, data, mem_mask);

src/mame/drivers/dec8.c
r1103	r1104
1119	1119	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1120	1120
1121	1121	PORT_START_TAG("IN2")
1122		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
1123		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
1124		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
1125		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
1126		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
1127		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
	1122	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1123	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1124	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1125	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1126	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1127	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1128	1128	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1129	1129	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1130	1130
1131	1131	PORT_START_TAG("DSW0")
1132	1132	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
1133	1133	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
1134		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_~~START3~~ )
	1134	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1135	1135	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_VBLANK )
1136	1136	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1137	1137	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
r1103	r1104
1176	1176	PORT_DIPSETTING( 0x80, DEF_STR( Normal ) )
1177	1177	INPUT_PORTS_END
1178	1178
1179		INPUT_PORTS_START( meikyuh )
1180		PORT_START_TAG("IN0")
1181		PLAYER1_JOYSTICK
1182		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
1183		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
1184		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1185		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1179	INPUT_PORTS_START( ghostb3 )
	1180	PORT_INCLUDE(ghostb)
1186	1181
1187		PORT_START_TAG("IN1")
1188		PLAYER2_JOYSTICK
1189		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
1190		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
1191		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1192		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1193
1194		PORT_START_TAG("IN2")
	1182	PORT_MODIFY("IN2")
1195	1183	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
1196	1184	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
1197	1185	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
1198	1186	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
1199	1187	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
1200	1188	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
1201		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1202		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1203	1189
1204		PORT_START_TAG("DSW0")
1205		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
1206		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
	1190	PORT_MODIFY("DSW0")
1207	1191	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 )
1208		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_VBLANK )
1209		PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
1210		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1211		PORT_DIPSETTING( 0x10, DEF_STR( On ) )
1212		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) )
1213		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1214		PORT_DIPSETTING( 0x20, DEF_STR( On ) )
1215		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) )
1216		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1217		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1218		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1219		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1220		PORT_DIPSETTING( 0x80, DEF_STR( On ) )
1221
1222		PORT_START_TAG("I8571") /* Dummy input for i8751 */
1223		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN4 )
1224		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN3 )
1225		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 )
1226		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 )
1227
1228		PORT_START_TAG("DSW1")
1229		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )
1230		PORT_DIPSETTING( 0x01, "1" )
1231		PORT_DIPSETTING( 0x03, "3" )
1232		PORT_DIPSETTING( 0x02, "5" )
1233		PORT_DIPSETTING( 0x00, "Infinite (Cheat)")
1234		PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Difficulty ) )
1235		PORT_DIPSETTING( 0x04, DEF_STR( Easy ) )
1236		PORT_DIPSETTING( 0x0c, DEF_STR( Normal ) )
1237		PORT_DIPSETTING( 0x08, DEF_STR( Hard ) )
1238		PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
1239		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1240		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1241		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1242		PORT_DIPNAME( 0x40, 0x00, DEF_STR( Allow_Continue ) )
1243		PORT_DIPSETTING( 0x40, DEF_STR( No ) )
1244		PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
1245		PORT_DIPNAME( 0x80, 0x80, "Freeze" )
1246		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1247		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1248	1192	INPUT_PORTS_END
1249	1193
1250	1194	INPUT_PORTS_START( srdarwin )
r1103	r1104
3472	3416	GAME( 1988, cobracom, 0, cobracom, cobracom, 0, ROT0, "Data East Corporation", "Cobra-Command (World revision 5)", 0 )
3473	3417	GAME( 1988, cobracmj, cobracom, cobracom, cobracom, 0, ROT0, "Data East Corporation", "Cobra-Command (Japan)", 0 )
3474	3418	GAME( 1987, ghostb, 0, ghostb, ghostb, ghostb, ROT0, "Data East USA", "The Real Ghostbusters (US 2 Players)", 0 )
3475		GAME( 1987, ghostb3, ghostb, ghostb, ghostb, ghostb, ROT0, "Data East USA", "The Real Ghostbusters (US 3 Players)", 0 )
3476		GAME( 1987, meikyuh, ghostb, ghostb, meikyuh, meikyuh, ROT0, "Data East Corporation", "Meikyuu Hunter G (Japan, set 1)", 0 )
3477		GAME( 1987, meikyuha, ghostb, ghostb, meikyuh, meikyuh, ROT0, "Data East Corporation", "Meikyuu Hunter G (Japan, set 2)", 0 )
	3419	GAME( 1987, ghostb3, ghostb, ghostb, ghostb3, ghostb, ROT0, "Data East USA", "The Real Ghostbusters (US 3 Players)", 0 )
	3420	GAME( 1987, meikyuh, ghostb, ghostb, ghostb, meikyuh, ROT0, "Data East Corporation", "Meikyuu Hunter G (Japan, set 1)", 0 )
	3421	GAME( 1987, meikyuha, ghostb, ghostb, ghostb, meikyuh, ROT0, "Data East Corporation", "Meikyuu Hunter G (Japan, set 2)", 0 )
3478	3422	GAME( 1987, srdarwin, 0, srdarwin, srdarwin, deco222, ROT270, "Data East Corporation", "Super Real Darwin (World)", 0 )
3479	3423	GAME( 1987, srdarwnj, srdarwin, srdarwin, srdarwin, deco222, ROT270, "Data East Corporation", "Super Real Darwin (Japan)", 0 )
3480	3424	GAME( 1987, gondo, 0, gondo, gondo, 0, ROT270, "Data East USA", "Gondomania (US)", 0 )

src/osd/osdcore.h
r1103	r1104
593	593	/* these flags can be set when queueing a work item to indicate how to handle
594	594	its deconstruction */
595	595	#define WORK_ITEM_FLAG_AUTO_RELEASE 0x0001
596		#define WORK_ITEM_FLAG_SHARED 0x0002
597	596
598	597	/* osd_work_queue is an opaque type which represents a queue of work items */
599	598	typedef struct _osd_work_queue osd_work_queue;
r1103	r1104
683	682
684	683
685	684	/*-----------------------------------------------------------------------------
686		osd_work_item_queue: queue a new work item
	685	osd_work_item_queue_multiple: queue a set of work items
687	686
688	687	Parameters:
689	688
r1103	r1104
692	691
693	692	callback - pointer to a function that will do the work
694	693
	694	numitems - number of work items to queue
	695
695	696	param - a void * parameter that can be used to pass data to the
696	697	function
697	698
	699	paramstep - the number of bytes to increment param by for each item
	700	queued; for example, if you have an array of work_unit objects,
	701	you can point param to the base of the array and set paramstep to
	702	sizeof(work_unit)
	703
698	704	flags - one or more of the WORK_ITEM_FLAG_* values ORed together:
699	705
700	706	WORK_ITEM_FLAG_AUTO_RELEASE - indicates that the work item
701	707	should be automatically freed when it is complete
702	708
703		WORK_ITEM_FLAG_SHARED - indicates that the same work item can
704		be simultaneously processed by multiple threads; the item
705		remains at the front of the queue until all threads
706		processing it have returned, which allows other threads to
707		process the same item if they have bandwidth
708
709	709	Return value:
710	710
711		A pointer to an allocated osd_work_item ~~represent~~ing the item.
	711	A pointer to the final allocated osd_work_item in the list.
712	712
713	713	Notes:
714	714
715	715	On single-threaded systems, this function may actually execute the
716	716	work item immediately before returning.
717	717	-----------------------------------------------------------------------------*/
718		osd_work_item osd_work_item_queue(osd_work_queue queue, osd_work_callback callback, void *param, UINT32 flags);
	718	osd_work_item osd_work_item_queue_multiple(osd_work_queue queue, osd_work_callback callback, INT32 numitems, void *parambase, INT32 paramstep, UINT32 flags);
719	719
720	720
	721	/* inline helper to queue a single work item using the same interface */
	722	INLINE osd_work_item osd_work_item_queue(osd_work_queue queue, osd_work_callback callback, void *param, UINT32 flags)
	723	{
	724	return osd_work_item_queue_multiple(queue, callback, 1, param, 0, flags);
	725	}
	726
	727
721	728	/*-----------------------------------------------------------------------------
722	729	osd_work_item_wait: wait for a work item to complete
723	730

src/osd/windows/windows.mak
r1103	r1104
90	90	RC = @$(VCONV) windres
91	91
92	92	# make sure we use the multithreaded runtime
	93	ifdef DEBUG
	94	CC += /MTd
	95	else
93	96	CC += /MT
	97	endif
94	98
95	99	# turn on link-time codegen if the MAXOPT flag is also set
96	100	ifdef MAXOPT

src/osd/windows/winwork.c
r1103	r1104
25	25	// DEBUGGING
26	26	//============================================================
27	27
28		#define KEEP_STATISTICS (0)
	28	#define KEEP_STATISTICS (1)
29	29
30	30
31	31
32	32	//============================================================
	33	// PARAMETERS
	34	//============================================================
	35
	36	#define MAX_THREADS (16)
	37	#define SPIN_LOOP_TIME (osd_ticks_per_second() / 1000)
	38
	39
	40
	41	//============================================================
33	42	// MACROS
34	43	//============================================================
35	44
36	45	#if KEEP_STATISTICS
37		#define add_to_stat(v,x) do { osd_sync_add((v), (x)); } while (0)
	46	#define add_to_stat(v,x) do { interlocked_add((v), (x)); } while (0)
	47	#define begin_timing(v) do { (v) -= osd_profiling_ticks(); } while (0)
	48	#define end_timing(v) do { (v) += osd_profiling_ticks(); } while (0)
38	49	#else
39	50	#define add_to_stat(v,x) do { } while (0)
	51	#define begin_timing(v) do { } while (0)
	52	#define end_timing(v) do { } while (0)
40	53	#endif
41	54
42	55	#ifndef YieldProcessor
r1103	r1104
59	72	// TYPE DEFINITIONS
60	73	//============================================================
61	74
	75	typedef struct _scalable_lock scalable_lock;
	76	struct _scalable_lock
	77	{
	78	struct
	79	{
	80	volatile UINT8 haslock; // do we have the lock?
	81	UINT8 filler[63]; // assumes a 64-bit cache line
	82	} slot[MAX_THREADS]; // one slot per thread
	83	volatile INT32 nextindex; // index of next slot to use
	84	};
	85
	86
62	87	typedef struct _thread_info thread_info;
63	88	struct _thread_info
64	89	{
65	90	osd_work_queue * queue; // pointer back to the queue
66	91	HANDLE handle; // handle to the thread
67	92	HANDLE wakeevent; // wake event for the thread
68		UINT8 active; // are we actively processing work?
	93	volatile UINT8 active; // are we actively processing work?
	94
	95	#if KEEP_STATISTICS
	96	osd_ticks_t runtime;
	97	osd_ticks_t spintime;
	98	osd_ticks_t waittime;
	99	#endif
69	100	};
70	101
71	102
72	103	struct _osd_work_queue
73	104	{
74		~~CRITICAL~~_~~SECTION~~ c~~ritsect~~; // ~~critica~~l section protecting the queue
	105	scalable_lock lock; // lock for protecting the queue
75	106	osd_work_item * volatile list; // list of items in the queue
76	107	osd_work_item ** volatile tailptr; // pointer to the tail pointer of work items in the queue
77	108	osd_work_item * volatile free; // free list of work items
78	109	volatile INT32 items; // items in the queue
79	110	volatile INT32 livethreads; // number of live threads
	111	volatile UINT8 waiting; // is someone waiting on the queue to complete?
	112	volatile UINT8 exiting; // should the threads exit on their next opportunity?
80	113	UINT32 threads; // number of threads in this queue
81	114	UINT32 flags; // creation flags
82	115	thread_info * thread; // array of thread information
83		HANDLE workevent; // shared event signalled when work is available
84	116	HANDLE doneevent; // event signalled when work is complete
85		HANDLE exitevent; // event signalled when thread should exit
86	117
87	118	#if KEEP_STATISTICS
88	119	volatile INT32 itemsqueued; // total items queued
r1103	r1104
102	133	void * result; // callback result
103	134	HANDLE event; // event signalled when complete
104	135	UINT32 flags; // creation flags
105		volatile INT32 ~~refc~~ount; // ~~reference~~ ~~coun~~t of thre~~ads~~ pro~~cessi~~ng
	136	volatile UINT8 done; // is the item done?
106	137	};
107	138
108	139
r1103	r1104
114	145	static int effective_num_processors(void);
115	146	static unsigned __stdcall worker_thread_entry(void *param);
116	147	static void worker_thread_process(osd_work_queue queue, thread_info thread);
117		static void execute_work_item(osd_work_item *item);
118	148
119	149
	150	//============================================================
	151	// INLINE FUNCTIONS
	152	//============================================================
120	153
	154	INLINE void compare_exchange_ptr(void volatile ptr, void compare, void *exchange)
	155	{
	156	#ifdef PTR64
	157	INT64 result = InterlockedCompareExchange64((LONGLONG *)ptr, (LONGLONG)exchange, (LONGLONG)compare);
	158	return (void *)result;
	159	#else
	160	INT32 result = InterlockedCompareExchange((LPLONG)ptr, (LONG)exchange, (LONG)compare);
	161	return (void *)result;
	162	#endif
	163	}
	164
	165
	166	INLINE INT32 interlocked_increment(INT32 volatile *ptr)
	167	{
	168	return InterlockedIncrement((LPLONG)ptr);
	169	}
	170
	171
	172	INLINE INT32 interlocked_decrement(INT32 volatile *ptr)
	173	{
	174	return InterlockedDecrement((LPLONG)ptr);
	175	}
	176
	177
	178	INLINE INT32 interlocked_add(INT32 volatile *ptr, INT32 add)
	179	{
	180	return InterlockedExchangeAdd((LPLONG)ptr, add) + add;
	181	}
	182
	183
	184	INLINE void scalable_lock_init(scalable_lock *lock)
	185	{
	186	memset(lock, 0, sizeof(*lock));
	187	lock->slot[0].haslock = TRUE;
	188	}
	189
	190
	191	INT32 scalable_lock_acquire(scalable_lock *lock)
	192	{
	193	INT32 myslot = (interlocked_increment(&lock->nextindex) - 1) & (MAX_THREADS - 1);
	194	INT32 backoff = 1;
	195
	196	while (!lock->slot[myslot].haslock)
	197	{
	198	INT32 backcount;
	199	for (backcount = 0; backcount < backoff; backcount++)
	200	YieldProcessor();
	201	backoff <<= 1;
	202	}
	203	lock->slot[myslot].haslock = FALSE;
	204	return myslot;
	205	}
	206
	207	void scalable_lock_release(scalable_lock *lock, INT32 myslot)
	208	{
	209	lock->slot[(myslot + 1) & (MAX_THREADS - 1)].haslock = TRUE;
	210	}
	211
	212
121	213	//============================================================
122	214	// osd_work_queue_alloc
123	215	//============================================================
r1103	r1104
139	231	queue->flags = flags;
140	232
141	233	// allocate events for the queue
142		queue->workevent = CreateEvent(NULL, FALSE, FALSE, NULL); // auto-reset, not signalled
143	234	queue->doneevent = CreateEvent(NULL, TRUE, TRUE, NULL); // manual reset, signalled
144		queue->exitevent = CreateEvent(NULL, TRUE, FALSE, NULL); // manual reset, not signalled
145		if (queue->workevent == NULL \|\| queue->doneevent == NULL \|\| queue->exitevent == NULL)
	235	if (queue->doneevent == NULL)
146	236	goto error;
147	237
148	238	// initialize the critical section
149		~~Initi~~al~~izeCritic~~alSection(&queue->c~~ritsect~~);
	239	scalable_lock_init(&queue->lock);
150	240
151	241	// determine how many threads to create...
152	242	// on a single-CPU system, create 1 thread for I/O queues, and 0 threads for everything else
r1103	r1104
157	247	else
158	248	queue->threads = (flags & WORK_QUEUE_FLAG_MULTI) ? (numprocs - 1) : 1;
159	249
160		// if we have threads, create them
161		if (queue->threads > 0)
	250	// clamp to the maximum
	251	queue->threads = MIN(queue->threads, MAX_THREADS);
	252
	253	// allocate memory for thread array (+1 to count the calling thread)
	254	queue->thread = malloc((queue->threads + 1) * sizeof(queue->thread[0]));
	255	if (queue->thread == NULL)
	256	goto error;
	257	memset(queue->thread, 0, (queue->threads + 1) * sizeof(queue->thread[0]));
	258
	259	// iterate over threads
	260	for (threadnum = 0; threadnum < queue->threads; threadnum++)
162	261	{
163		// allocate memory for thread array
164		queue->thread = malloc(queue->threads * sizeof(queue->thread[0]));
165		if (queue->thread == NULL)
166		goto error;
167		memset(queue->thread, 0, queue->threads * sizeof(queue->thread[0]));
	262	thread_info *thread = &queue->thread[threadnum];
	263	uintptr_t handle;
168	264
169		// iterate over threads
170		for (threadnum = 0; threadnum < queue->threads; threadnum++)
171		{
172		thread_info *thread = &queue->thread[threadnum];
173		uintptr_t handle;
	265	// set a pointer back to the queue
	266	thread->queue = queue;
174	267
175		// set a pointer back to the queue
176		thread->queue = queue;
	268	// create the per-thread wake event
	269	thread->wakeevent = CreateEvent(NULL, FALSE, FALSE, NULL); // auto-reset, not signalled
	270	if (thread->wakeevent == NULL)
	271	goto error;
177	272
178		// create the per-thread wake event
179		thread->wakeevent = CreateEvent(NULL, FALSE, FALSE, NULL); // auto-reset, not signalled
180		if (thread->wakeevent == NULL)
181		goto error;
	273	// create the thread
	274	handle = _beginthreadex(NULL, 0, worker_thread_entry, thread, 0, NULL);
	275	thread->handle = (HANDLE)handle;
	276	if (thread->handle == NULL)
	277	goto error;
182	278
183		// create the thread
184		handle = _beginthreadex(NULL, 0, worker_thread_entry, thread, 0, NULL);
185		thread->handle = (HANDLE)handle;
186		if (thread->handle == NULL)
187		goto error;
	279	// set its priority: I/O threads get high priority because they are assumed to be
	280	// blocked most of the time; other threads just match the creator's priority
	281	if (flags & WORK_QUEUE_FLAG_IO)
	282	SetThreadPriority(thread->handle, THREAD_PRIORITY_ABOVE_NORMAL);
	283	else
	284	SetThreadPriority(thread->handle, GetThreadPriority(GetCurrentThread()));
	285	}
188	286
189		// set its priority: I/O threads get high priority because they are assumed to be
190		// blocked most of the time; other threads just match the creator's priority
191		if (flags & WORK_QUEUE_FLAG_IO)
192		SetThreadPriority(thread->handle, THREAD_PRIORITY_ABOVE_NORMAL);
193		else
194		SetThreadPriority(thread->handle, GetThreadPriority(GetCurrentThread()));
195		}
196		}
	287	// start a timer going for "waittime" on the main thread
	288	begin_timing(queue->thread[queue->threads].waittime);
197	289	return queue;
198	290
199	291	error:
r1103	r1104
230	322	// if this is a multi queue, help out rather than doing nothing
231	323	if (queue->flags & WORK_QUEUE_FLAG_MULTI)
232	324	{
233		osd_ti~~cks_t~~ st~~opspin~~ = ~~osd_~~t~~icks() + tim~~eout;
	325	thread_info *thread = &queue->thread[queue->threads];
234	326
	327	end_timing(thread->waittime);
	328
235	329	// process what we can as a worker thread
236		worker_thread_process(queue, ~~NULL~~);
	330	worker_thread_process(queue, thread);
237	331
238		// spin until we hit 0 items and then return TRUE
239		while (queue->items != 0 && osd_ticks() < stopspin)
240		YieldProcessor();
	332	begin_timing(thread->waittime);
241	333	return TRUE;
242	334	}
243	335
244	336	// reset our done event and double-check the items before waiting
245	337	ResetEvent(queue->doneevent);
246		if (queue->items == 0)
247		return TRUE;
	338	queue->waiting = TRUE;
	339	if (queue->items != 0)
	340	WaitForSingleObject(queue->doneevent, timeout * 1000 / osd_ticks_per_second());
	341	queue->waiting = FALSE;
248	342
249		// wait for the collection to be signalled
250		return (WaitForSingleObject(queue->doneevent, timeout * 1000 / osd_ticks_per_second()) == WAIT_OBJECT_0);
	343	// return TRUE if we actually hit 0
	344	return (queue->items == 0);
251	345	}
252	346
253	347
r1103	r1104
262	356	{
263	357	int threadnum;
264	358
	359	// stop the timer for "waittime" on the main thread
	360	end_timing(queue->thread[queue->threads].waittime);
	361
265	362	// signal all the threads to exit
266		SetEvent(queue->exitevent);
	363	queue->exiting = TRUE;
	364	for (threadnum = 0; threadnum < queue->threads; threadnum++)
	365	{
	366	thread_info *thread = &queue->thread[threadnum];
	367	if (thread->wakeevent != NULL)
	368	SetEvent(thread->wakeevent);
	369	}
267	370
268	371	// wait for all the threads to go away
269	372	for (threadnum = 0; threadnum < queue->threads; threadnum++)
r1103	r1104
282	385	CloseHandle(thread->wakeevent);
283	386	}
284	387
	388	#if KEEP_STATISTICS
	389	// output per-thread statistics
	390	for (threadnum = 0; threadnum <= queue->threads; threadnum++)
	391	{
	392	thread_info *thread = &queue->thread[threadnum];
	393	osd_ticks_t total = thread->runtime + thread->waittime + thread->spintime;
	394	printf("Thread %d: run=%5.2f%% spin=%5.2f%% wait/other=%5.2f%%\n",
	395	threadnum,
	396	(double)thread->runtime * 100.0 / (double)total,
	397	(double)thread->spintime * 100.0 / (double)total,
	398	(double)thread->waittime * 100.0 / (double)total);
	399	}
	400	#endif
	401
285	402	// free the list
286	403	free(queue->thread);
287	404	}
288	405
289	406	// free all the events
290		if (queue->workevent != NULL)
291		CloseHandle(queue->workevent);
292	407	if (queue->doneevent != NULL)
293	408	CloseHandle(queue->doneevent);
294		if (queue->exitevent != NULL)
295		CloseHandle(queue->exitevent);
296	409
297		// free the critical section
298		DeleteCriticalSection(&queue->critsect);
299
300	410	// free all items in the free list
301	411	while (queue->free != NULL)
302	412	{
r1103	r1104
330	440
331	441
332	442	//============================================================
333		// osd_work_item_queue
	443	// osd_work_item_queue_multiple
334	444	//============================================================
335	445
336		osd_work_item osd_work_item_queue(osd_work_queue queue, osd_work_callback callback, void *param, UINT32 flags)
	446	osd_work_item osd_work_item_queue_multiple(osd_work_queue queue, osd_work_callback callback, INT32 numitems, void *parambase, INT32 paramstep, UINT32 flags)
337	447	{
338		osd_work_item *item;
	448	osd_work_item *itemlist = NULL;
	449	osd_work_item **item_tailptr = &itemlist;
	450	INT32 lockslot;
	451	int itemnum;
339	452
340		// first allocate a new work item; try the free list first
341		do
	453	// loop over items, building up a local list of work
	454	for (itemnum = 0; itemnum < numitems; itemnum++)
342	455	{
343		item = (osd_work_item *)queue->free;
344		} while (item != NULL && osd_compare_exchange_ptr((PVOID volatile *)&queue->free, item, item->next) != item);
	456	osd_work_item *item;
345	457
346		// if nothing, allocate something new
347		if (item == NULL)
348		{
349		// allocate the item
350		item = malloc(sizeof(*item));
	458	// first allocate a new work item; try the free list first
	459	do
	460	{
	461	item = (osd_work_item *)queue->free;
	462	} while (item != NULL && compare_exchange_ptr((PVOID volatile *)&queue->free, item, item->next) != item);
	463
	464	// if nothing, allocate something new
351	465	if (item == NULL)
352		return NULL;
353		item->event = NULL;
354		item->queue = queue;
	466	{
	467	// allocate the item
	468	item = malloc(sizeof(*item));
	469	if (item == NULL)
	470	return NULL;
	471	item->event = NULL;
	472	item->queue = queue;
	473	}
	474
	475	// fill in the basics
	476	item->next = NULL;
	477	item->callback = callback;
	478	item->param = parambase;
	479	item->result = NULL;
	480	item->flags = flags;
	481	item->done = FALSE;
	482
	483	// advance to the next
	484	*item_tailptr = item;
	485	item_tailptr = &item->next;
	486	parambase = (UINT8 *)parambase + paramstep;
355	487	}
356	488
357		// fill in the basics
358		item->next = NULL;
359		item->callback = callback;
360		item->param = param;
361		item->result = NULL;
362		item->flags = flags;
363		item->refcount = 1;
364		if (item->event != NULL)
365		ResetEvent(item->event);
	489	// enqueue the whole thing within the critical section
	490	lockslot = scalable_lock_acquire(&queue->lock);
	491	*queue->tailptr = itemlist;
	492	queue->tailptr = item_tailptr;
	493	scalable_lock_release(&queue->lock, lockslot);
366	494
367		// if no threads, just run it now
368		if (queue->threads == 0)
369		{
370		// execute the callback and clear the refcount back to 0
371		item->result = (*item->callback)(item->param);
372		item->refcount = 0;
	495	// increment the number of items in the queue
	496	interlocked_add(&queue->items, numitems);
	497	add_to_stat(&queue->itemsqueued, numitems);
373	498
374		// handle auto-release; make sure we return NULL in that case
375		if (flags & WORK_ITEM_FLAG_AUTO_RELEASE)
376		osd_work_item_release(item);
377		}
378
379		// otherwise, enqueue the item and wake the threads
380		else
	499	// look for free threads to do the work
	500	if (queue->livethreads < queue->threads)
381	501	{
382		// enqueue within the critical section
383		EnterCriticalSection(&queue->critsect);
384		*queue->tailptr = item;
385		queue->tailptr = (osd_work_item **)&item->next;
386		LeaveCriticalSection(&queue->critsect);
	502	int threadnum;
387	503
388		// increment the number of items in the queue
389		osd_sync_add(&queue->items, 1);
390		add_to_stat(&queue->itemsqueued, 1);
	504	// iterate over all the threads
	505	for (threadnum = 0; threadnum < queue->threads; threadnum++)
	506	{
	507	thread_info *thread = &queue->thread[threadnum];
391	508
392		// non-shared case
393		if (!(flags & WORK_ITEM_FLAG_SHARED))
394		{
395		// if there are still some free threads, signal the shared work event
396		if (queue->livethreads < queue->threads)
	509	// if this thread is not active, wake him up
	510	if (!thread->active)
397	511	{
398		SetEvent(queue->workevent);
	512	SetEvent(thread->wakeevent);
399	513	add_to_stat(&queue->setevents, 1);
	514
	515	// for non-shared, the first one we find is good enough
	516	if (--numitems == 0)
	517	break;
400	518	}
401	519	}
	520	}
402	521
403		// shared case
404		else
405		{
406		int threadnum;
	522	// if no threads, run the queue now on this thread
	523	if (queue->threads == 0)
	524	worker_thread_process(queue, &queue->thread[0]);
407	525
408		// signal the wake event for all non-active threads
409		for (threadnum = 0; threadnum < queue->threads; threadnum++)
410		if (!queue->thread[threadnum].active)
411		{
412		SetEvent(queue->thread[threadnum].wakeevent);
413		add_to_stat(&queue->setevents, 1);
414		}
415		}
416		}
417
418	526	// only return the item if it won't get released automatically
419		return (flags & WORK_ITEM_FLAG_AUTO_RELEASE) ? NULL : item;
	527	return (flags & WORK_ITEM_FLAG_AUTO_RELEASE) ? NULL : *item_tailptr;
420	528	}
421	529
422	530
r1103	r1104
427	535	int osd_work_item_wait(osd_work_item *item, osd_ticks_t timeout)
428	536	{
429	537	// if we're done already, just return
430		if (item->~~refc~~oun~~t == 0~~)
	538	if (item->done)
431	539	return TRUE;
432	540
433	541	// if we don't have an event, create one
434	542	if (item->event == NULL)
435	543	item->event = CreateEvent(NULL, TRUE, FALSE, NULL); // manual reset, not signalled
	544	else
	545	ResetEvent(item->event);
436	546
437	547	// if we don't have an event, we need to spin (shouldn't ever really happen)
438	548	if (item->event != NULL)
439	549	{
440	550	osd_ticks_t stopspin = osd_ticks() + timeout;
441		while (item->~~refc~~oun~~t != 0~~ && osd_ticks() < stopspin)
	551	while (!item->done && osd_ticks() < stopspin)
442	552	YieldProcessor();
443	553	}
444	554
445	555	// otherwise, block on the event until done
446		else if (item->~~refc~~oun~~t != 0~~)
	556	else if (!item->done)
447	557	WaitForSingleObject(item->event, timeout * 1000 / osd_ticks_per_second());
448	558
449	559	// return TRUE if the refcount actually hit 0
450		return (item->~~refc~~oun~~t == 0)~~;
	560	return item->done;
451	561	}
452	562
453	563
r1103	r1104
477	587	{
478	588	next = (osd_work_item *)item->queue->free;
479	589	item->next = next;
480		} while (~~osd_~~compare_exchange_ptr((PVOID volatile *)&item->queue->free, next, item) != next);
	590	} while (compare_exchange_ptr((PVOID volatile *)&item->queue->free, next, item) != next);
481	591	}
482	592
483	593
r1103	r1104
510	620	{
511	621	thread_info *thread = param;
512	622	osd_work_queue *queue = thread->queue;
513		HANDLE hlist[3];
514	623
515		// fill in our handle list
516		hlist[0] = queue->workevent;
517		hlist[1] = thread->wakeevent;
518		hlist[2] = queue->exitevent;
519
520	624	// loop until we exit
521	625	for ( ;; )
522	626	{
r1103	r1104
524	628	DWORD result = WAIT_OBJECT_0;
525	629
526	630	// bail on exit, and only wait if there are no pending items in queue
527		if (queue->items == 0)
528		result = WaitForMultipleObjects(ARRAY_LENGTH(hlist), hlist, FALSE, INFINITE);
529		if (result == WAIT_OBJECT_0 + 2)
	631	if (!queue->exiting && queue->items == 0)
	632	{
	633	begin_timing(thread->waittime);
	634	result = WaitForSingleObject(thread->wakeevent, INFINITE);
	635	end_timing(thread->waittime);
	636	}
	637	if (queue->exiting)
530	638	break;
531	639
532	640	// indicate that we are live
533	641	thread->active = TRUE;
534		osd_sync~~_add~~(&queue->livethreads~~, 1~~);
	642	interlocked_increment(&queue->livethreads);
535	643
536	644	// process work items
537	645	for ( ;; )
r1103	r1104
542	650	worker_thread_process(queue, thread);
543	651
544	652	// spin for a while looking for more work
545		stopspin = osd_ticks() + osd_ticks_per_second() / 1000;
	653	begin_timing(thread->spintime);
	654	stopspin = osd_ticks() + SPIN_LOOP_TIME;
546	655	while (queue->items == 0 && osd_ticks() < stopspin)
547	656	YieldProcessor();
	657	end_timing(thread->spintime);
548	658
549	659	// if nothing more, release the processor
550	660	if (queue->items == 0)
r1103	r1104
554	664
555	665	// decrement the live thread count
556	666	thread->active = FALSE;
557		osd_~~sync_a~~dd(&queue->livethreads~~, -1~~);
	667	interlocked_decrement(&queue->livethreads);
558	668	}
559	669	return 0;
560	670	}
r1103	r1104
566	676
567	677	static void worker_thread_process(osd_work_queue queue, thread_info thread)
568	678	{
	679	begin_timing(thread->runtime);
	680
569	681	// loop until everything is processed
570	682	while (queue->items != 0)
571	683	{
572		int removed_item = FALSE;
573	684	osd_work_item *item;
	685	INT32 lockslot;
574	686
575	687	// use a critical section to synchronize the removal of items
576		Ent~~erCriti~~calSection(&queue->c~~ritsect~~);
	688	lockslot = scalable_lock_acquire(&queue->lock);
577	689	{
	690	// pull the item from the queue
578	691	item = (osd_work_item *)queue->list;
579
580		// if it is a regular item, or if it is a shared item that is complete, remove it
581		if (item != NULL && (!(item->flags & WORK_ITEM_FLAG_SHARED) \|\| item->refcount == 0))
	692	if (item != NULL)
582	693	{
583		removed_item = TRUE;
584	694	queue->list = item->next;
585		if (item->~~nex~~t == NULL)
	695	if (queue->list == NULL)
586	696	queue->tailptr = (osd_work_item **)&queue->list;
587	697	}
588	698	}
589		~~LeaveCriti~~calSe~~cti~~on(&queue->c~~ritse~~ct);
	699	scalable_lock_release(&queue->lock, lockslot);
590	700
591		// call the callback and signal its event
592		if (item != NULL && item->refcount != 0)
593		execute_work_item(item);
594
595		// if we removed an item, decrement the item count and signal done if appropriate
596		if (removed_item && osd_sync_add(&queue->items, -1) == 0)
	701	// process non-NULL items
	702	if (item != NULL)
597	703	{
598		// we don't need to set the doneevent for multi queues because they spin
599		if (!(item->flags & WORK_QUEUE_FLAG_MULTI))
600		SetEvent(queue->doneevent);
	704	// call the callback and stash the result
	705	item->result = (*item->callback)(item->param);
	706	interlocked_decrement(&queue->items);
	707	item->done = TRUE;
601	708
602	709	// if it's an auto-release item, release it
603	710	if (item->flags & WORK_ITEM_FLAG_AUTO_RELEASE)
604	711	osd_work_item_release(item);
	712
	713	// set the result and signal the event
	714	else if (item->event != NULL)
	715	{
	716	SetEvent(item->event);
	717	add_to_stat(&item->queue->setevents, 1);
	718	}
	719
	720	// if we removed an item and there's still work to do, bump the stats
	721	if (queue->items != 0)
	722	add_to_stat(&queue->extraitems, 1);
605	723	}
606
607		// if we removed an item and there's still work to do, bump the stats
608		if (removed_item && queue->items != 0)
609		add_to_stat(&queue->extraitems, 1);
610	724	}
611		}
612	725
613
614		//============================================================
615		// execute_work_item
616		//============================================================
617
618		static void execute_work_item(osd_work_item *item)
619		{
620		void *result;
621
622		// add a claim to this work item; if it had already been completed, back off and exit
623		if (osd_sync_add(&item->refcount, 1) == 1)
	726	// we don't need to set the doneevent for multi queues because they spin
	727	if (queue->waiting)
624	728	{
625		item->refcount = 0;
626		return;
	729	SetEvent(queue->doneevent);
	730	add_to_stat(&queue->setevents, 1);
627	731	}
628	732
629		// call the callback and stash the result
630		result = (*item->callback)(item->param);
631
632		// mark it complete and signal the event
633		if (osd_sync_add(&item->refcount, -1) == 1 && osd_compare_exchange32(&item->refcount, 1, 0) == 1)
634		{
635		// set the result and signal the event
636		item->result = result;
637		if (item->event != NULL)
638		SetEvent(item->event);
639		}
	733	end_timing(thread->runtime);
640	734	}

src/emu/cpu/m6805/m6805.c
r1103	r1104
56	56
57	57	UINT16 pending_interrupts; /* MB */
58	58	int (*irq_callback)(int irqline);
59		int irq_state[8]; /* KW Additional lines for HD63705 */
	59	int irq_state[9]; /* KW Additional lines for HD63705 */
60	60	int nmi_state;
61	61	} m6805_Regs;
62	62

src/emu/cpu/z80gb/opc_main.h
r1103	r1104
375	375	int tmp = Regs.b.A;
376	376
377	377	if ( ! ( Regs.b.F & FLAG_N ) ) {
378		if ( ( Regs.b.F & FLAG_H ) \|\| ( tmp & 0x0F ) > 9 )
	378	if ( ( Regs.b.F & FLAG_H ) \|\| ( tmp & 0x0F ) > 9 )
379	379	tmp += 6;
380	380	if ( ( Regs.b.F & FLAG_C ) \|\| tmp > 0x9F )
381	381	tmp += 0x60;

src/emu/cpu/i386/i386.h
r1103	r1104
244	244	int base_cycles;
245	245	UINT8 opcode;
246	246
247		INT32 irq_~~lin~~e;
	247	UINT8 irq_state;
248	248	int (*irq_callback)(int);
249	249	UINT32 a20_mask;
250	250

src/emu/cpu/i386/i386.c
r1103	r1104
290	290
291	291	I.sreg[CS].selector = READ16( I.idtr.base + entry + 2 );
292	292	I.eip = READ16( I.idtr.base + entry );
	293
	294	/* Interrupts that vector through either interrupt gates or trap gates cause TF */
	295	/* (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS. */
	296	I.TF = 0;
	297
	298	if (irq_gate)
	299	{
	300	I.IF = 0;
	301	}
	302
293	303	}
294	304	else
295	305	{
	306	int type;
296	307	/* 32-bit */
297	308	PUSH32( get_flags() & 0x00fcffff );
298	309	PUSH32( I.sreg[CS].selector );
r1103	r1104
302	313	v2 = READ32( I.idtr.base + entry + 4 );
303	314	offset = (v2 & 0xffff0000) \| (v1 & 0xffff);
304	315	segment = (v1 >> 16) & 0xffff;
	316	type = (v2>>8) & 0x1F;
305	317
306	318	I.sreg[CS].selector = segment;
307	319	I.eip = offset;
308		}
309	320
310		/* Interrupts that vector through either interrupt gates or trap gates cause TF */
311		/* (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS. */
312		I.TF = 0;
	321	/* Interrupts that vector through either interrupt gates or trap gates cause TF */
	322	/* (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS. */
	323	if ((type == 14) \|\| (type==15))
	324	I.TF = 0;
313	325
314		if (irq_gate)
315		{
316		I.IF = 0;
	326	if (type == 14)
	327	{
	328	I.IF = 0;
	329	}
	330
317	331	}
318	332
319	333	i386_load_segment_descriptor(CS);
320	334	CHANGE_PC(I.eip);
	335
321	336	}
322	337
323	338	static void i386_check_irq_line(void)
324	339	{
325	340	/* Check if the interrupts are enabled */
326		if ( I.irq_~~lin~~e && I.IF )
	341	if ( (I.irq_state) && I.IF )
327	342	{
	343	I.cycles -= 2;
328	344	i386_trap(I.irq_callback(0), 1);
329	345	}
330	346	}
r1103	r1104
562	578	state_save_register_item(state_type, index, I.ldtr.segment);
563	579	state_save_register_item(state_type, index, I.ldtr.limit);
564	580	state_save_register_item(state_type, index, I.ldtr.flags);
565		state_save_register_item(state_type, index, I.irq_~~lin~~e);
	581	state_save_register_item(state_type, index, I.irq_state);
566	582	state_save_register_item(state_type, index, I.performed_intersegment_jump);
567	583	state_save_register_func_postload(i386_postload);
568	584	}
r1103	r1104
664	680	}
665	681	else
666	682	{
667		I.irq_line = state;
668		i386_check_irq_line();
	683	I.irq_state = state;
669	684	}
670	685	}
671	686
r1103	r1104
697	712	{
698	713	I.operand_size = I.sreg[CS].d;
699	714	I.address_size = I.sreg[CS].d;
	715
700	716	I.segment_prefix = 0;
701	717	I.prev_eip = I.eip;
702	718
703	719	CALL_MAME_DEBUG;
704	720
	721	i386_check_irq_line();
705	722	I386OP(decode_opcode)();
706	723	}
707	724	I.tsc += (num_cycles - I.cycles);
r1103	r1104
737	754	i386_set_a20_line(info->i);
738	755	return;
739	756	}
740		if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + 1)
	757	if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + MAX_INPUT_LINES)
741	758	{
742	759	i386_set_irq_line(state-CPUINFO_INT_INPUT_STATE, info->i);
743	760	return;

src/emu/cpu/i386/i386ops.c
r1103	r1104
1495	1495	static void I386OP(sti)(void) // Opcode 0xfb
1496	1496	{
1497	1497	I.IF = 1;
1498		i386_check_irq_line();
1499	1498	CYCLES(CYCLES_STI);
1500	1499	}
1501	1500

src/emu/cpu/i8051/i8051.c
r1103	r1104
1306	1306	memcpy(&i8051, src, sizeof(I8051));
1307	1307	}
1308	1308
	1309	/* Get Internal RAM value */
	1310	unsigned i8051_get_intram(int offset)
	1311	{
	1312	UINT8 ram_ret = 0;
	1313	RWM = 1;
	1314	ram_ret = IRAM_R(offset);
	1315	RWM = 0;
	1316	return ram_ret;
	1317	}
	1318
1309	1319	/NOTE: These are not used by the opcode functions, they are here only for MAME requirements/
1310	1320	unsigned i8051_get_reg(int regnum)
1311	1321	{
r1103	r1104
1789	1799	*/
1790	1800	static READ32_HANDLER(external_ram_iaddr)
1791	1801	{
1792		/* if(i8051.eram_iaddr_callback)
	1802	if(i8051.eram_iaddr_callback)
1793	1803	return i8051.eram_iaddr_callback(offset,mem_mask);
1794	1804	else
1795	1805	LOG(("i8051 #%d: external ram address requested (8 bit offset=%02x), but no callback available! at PC:%04x\n", cpu_getactivecpu(), offset, PC));
1796		*/
	1806
1797	1807	return offset;
1798	1808	}
1799	1809

src/emu/cpu/i8051/i8051.h
r1103	r1104
101	101	extern int i8051_execute(int cycles); /* Execute cycles - returns number of cycles actually run */
102	102	extern void i8051_get_context (void dst); / Get registers, return context size */
103	103	extern void i8051_set_context (void src); / Set registers */
	104	extern unsigned i8051_get_intram (int offset);
104	105	extern unsigned i8051_get_reg (int regnum);
105	106	extern void i8051_set_reg (int regnum, unsigned val);
106	107	extern void i8051_set_irq_line(int irqline, int state);

src/emu/cpu/mips/mdrc64.c
r1103	r1104
88	88	#define DISABLE_FIXED_RAM_LOAD (0)
89	89	#define DISABLE_FIXED_RAM_STORE (0)
90	90	#define FLUSH_AFTER_EACH_INSTRUCTION (0)
91		#define PRINTF_EXCEPTIONS (1)
	91	#define PRINTF_EXCEPTIONS (0)
92	92	#define PROBE_ADDRESS (0)
	93	#define LOG_HOTSPOTS (0)
93	94
94	95
95	96
r1103	r1104
97	98	CONSTANTS
98	99	***************************************************************************/
99	100
100		/* compilation boundaries -- how far back/forward does the analysis extend? */
101		#define COMPILE_BACKWARDS_BYTES 128
102		#define COMPILE_FORWARDS_BYTES 512
103		#define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4))
104		#define MAX_INSTRUCTION_SEQUENCE 64
105
106	101	/* extra "conditions" used to augment the basic conditions for OOB handlers */
107	102	#define COND_NONE 16
108	103	#define COND_NO_JUMP 17
r1103	r1104
229	224	struct _mips3drc_data
230	225	{
231	226	/* misc data */
232		UINT64 abs64mask[2];
233		UINT32 abs32mask[4];
	227	UINT64 abs64mask[2];
	228	UINT32 abs32mask[4];
234	229
235	230	/* C functions */
236		x86code * activecpu_gettotalcycles64;
237		x86code * mips3com_update_cycle_counting;
238		x86code * mips3com_tlbr;
239		x86code * mips3com_tlbwi;
240		x86code * mips3com_tlbwr;
241		x86code * mips3com_tlbp;
	231	x86code * activecpu_gettotalcycles64;
	232	x86code * mips3com_update_cycle_counting;
	233	x86code * mips3com_tlbr;
	234	x86code * mips3com_tlbwi;
	235	x86code * mips3com_tlbwr;
	236	x86code * mips3com_tlbp;
242	237
243	238	/* internal functions */
244		x86code * generate_interrupt_exception;
245		x86code * generate_cop_exception;
246		x86code * generate_overflow_exception;
247		x86code * generate_invalidop_exception;
248		x86code * generate_syscall_exception;
249		x86code * generate_break_exception;
250		x86code * generate_trap_exception;
251		x86code * generate_tlbload_exception;
252		x86code * generate_tlbstore_exception;
253		x86code * handle_pc_tlb_mismatch;
254		x86code * find_exception_handler;
255		x86code * explode_ccr31;
256		x86code * recover_ccr31;
	239	x86code * generate_interrupt_exception;
	240	x86code * generate_cop_exception;
	241	x86code * generate_overflow_exception;
	242	x86code * generate_invalidop_exception;
	243	x86code * generate_syscall_exception;
	244	x86code * generate_break_exception;
	245	x86code * generate_trap_exception;
	246	x86code * generate_tlbload_exception;
	247	x86code * generate_tlbstore_exception;
	248	x86code * handle_pc_tlb_mismatch;
	249	x86code * find_exception_handler;
	250	x86code * explode_ccr31;
	251	x86code * recover_ccr31;
257	252
258	253	/* read/write handlers */
259		readwrite_handlers general;
260		readwrite_handlers cached;
261		readwrite_handlers uncached;
	254	readwrite_handlers general;
	255	readwrite_handlers cached;
	256	readwrite_handlers uncached;
262	257
263	258	/* out of bounds handlers */
264		oob_handler ooblist[COMPILE_MAX_INSTRUCTIONS*2];
265		int oobcount;
	259	oob_handler ooblist[COMPILE_MAX_INSTRUCTIONS*2];
	260	int oobcount;
266	261
267	262	/* C functions */
268		x86code * execute_c_version;
	263	x86code * execute_c_version;
	264
	265	/* hotspot tracking */
	266	#if LOG_HOTSPOTS
	267	struct
	268	{
	269	offs_t pc;
	270	UINT32 opcode;
	271	UINT64 count;
	272	} hotspot[100000];
	273	int next_hotspot;
	274	#endif
269	275	};
270	276
271	277
r1103	r1104
300	306	static void append_check_interrupts(drc_core drc, compiler_state compiler, const opcode_desc *desc);
301	307	static void append_check_sw_interrupts(drc_core *drc, int inline_generate);
302	308
	309	static void emit_update_cycles_pc_and_flush(drc_core drc, compiler_state compiler, const opcode_desc *desc, offs_t destpc);
	310
303	311	static int compile_instruction(drc_core drc, compiler_state compiler, const opcode_desc *desc);
304	312	static int compile_special(drc_core drc, compiler_state compiler, const opcode_desc *desc);
305	313	static int compile_regimm(drc_core drc, compiler_state compiler, const opcode_desc *desc);
r1103	r1104
341	349	PRIVATE GLOBAL VARIABLES
342	350	***************************************************************************/
343	351
344		static UINT64 dmult_temp1;
345		static UINT64 dmult_temp2;
346		static UINT32 jr_temp;
347
348		static compiler_state compiler_save;
349
350	352	static const UINT8 nvreg[] = { REG_NV0, REG_NV1, REG_NV2, REG_NV3, REG_NV4, REG_NV5, REG_NV6 };
351	353
352	354	static const char *x86regname[] = {"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
r1103	r1104
459	461	static void mips3drc_exit(void)
460	462	{
461	463	printf("Final code size = %d\n", (int)(mips3.drc->cache_top - mips3.drc->cache_base));
	464	#if LOG_HOTSPOTS
	465	/* print top hotspots */
	466	{
	467	int maxspot = 0;
	468	int hotnum;
	469	int count;
	470
	471	for (count = 0; count < 10; count++)
	472	{
	473	for (hotnum = 1; hotnum < mips3.drcdata->next_hotspot; hotnum++)
	474	if (mips3.drcdata->hotspot[hotnum].count > mips3.drcdata->hotspot[maxspot].count)
	475	maxspot = hotnum;
	476	printf("%08X%08X hits: add_speedup(0x%08X, 0x%08X);\n",
	477	(UINT32)(mips3.drcdata->hotspot[maxspot].count >> 32),
	478	(UINT32)mips3.drcdata->hotspot[maxspot].count,
	479	mips3.drcdata->hotspot[maxspot].pc,
	480	mips3.drcdata->hotspot[maxspot].opcode);
	481	mips3.drcdata->hotspot[maxspot].count = 0;
	482	}
	483	}
	484	#endif
462	485	}
463	486
464	487
r1103	r1104
632	655	/* initialize the compiler state */
633	656	compiler_state_reset(&compiler);
634	657
	658	#if LOG_HOTSPOTS
	659	/* add hotspot tracking */
	660	{
	661	int hotnum;
	662
	663	drc_register_code_at_cache_top(drc, seqhead->pc);
	664
	665	for (hotnum = 0; hotnum < mips3.drcdata->next_hotspot; hotnum++)
	666	if (mips3.drcdata->hotspot[hotnum].pc == seqhead->pc && mips3.drcdata->hotspot[hotnum].opcode == *seqhead->opptr.l)
	667	break;
	668	if (hotnum == mips3.drcdata->next_hotspot)
	669	{
	670	assert(hotnum < ARRAY_LENGTH(mips3.drcdata->hotspot));
	671	mips3.drcdata->hotspot[hotnum].pc = seqhead->pc;
	672	mips3.drcdata->hotspot[hotnum].opcode = *seqhead->opptr.l;
	673	mips3.drcdata->hotspot[hotnum].count = 0;
	674	mips3.drcdata->next_hotspot++;
	675	}
	676	emit_add_m64_imm(DRCTOP, MDRC(&mips3.drcdata->hotspot[hotnum].count), 1);
	677	}
	678	#endif
	679
635	680	/* iterate over instructions in the sequence and compile them */
636	681	for (curdesc = seqhead; curdesc != seqlast->next; curdesc = curdesc->next)
637	682	compile_one(drc, &compiler, curdesc);
r1103	r1104
640	685	if (!(seqlast->flags & (OPFLAG_IS_UNCONDITIONAL_BRANCH \| OPFLAG_WILL_CAUSE_EXCEPTION)))
641	686	{
642	687	UINT32 nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
643		if (compiler.cycles != 0)
644		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler.cycles); // sub [icount],cycles
645		emit_mov_r32_imm(DRCTOP, REG_P1, nextpc); // mov p1,nextpc
646		compiler_register_flush_all(drc, &compiler); // <flush registers>
647		if (compiler.cycles != 0)
648		emit_jcc(DRCTOP, COND_S, mips3.drc->exit_point); // js exit_point
	688	emit_update_cycles_pc_and_flush(drc, &compiler, NULL, nextpc);
649	689	}
650	690
651	691	/* if this is a likely branch, the fall through case needs to skip the next instruction */
r1103	r1104
1894	1934
1895	1935
1896	1936	/*------------------------------------------------------------------
	1937	emit_flush_cycles_before_instruction
	1938	------------------------------------------------------------------*/
	1939
	1940	static void emit_flush_cycles_before_instruction(drc_core drc, compiler_state compiler, const opcode_desc *desc, UINT32 cycles_to_leave)
	1941	{
	1942	/* if we have cycles, subtract them now */
	1943	if (compiler->cycles - cycles_to_leave != 0)
	1944	emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles - cycles_to_leave); // sub [icount],cycles
	1945
	1946	/* clear out compiler counts */
	1947	compiler->cycles = cycles_to_leave;
	1948	}
	1949
	1950
	1951	/*------------------------------------------------------------------
	1952	emit_update_cycles_pc_and_flush
	1953	------------------------------------------------------------------*/
	1954
	1955	static void emit_update_cycles_pc_and_flush(drc_core drc, compiler_state compiler, const opcode_desc *desc, offs_t destpc)
	1956	{
	1957	/* if we have cycles, subtract them now */
	1958	emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles); // sub [icount],cycles
	1959
	1960	/* clear out compiler counts */
	1961	compiler->cycles = 0;
	1962
	1963	/* if we have an opcode descriptor, make this an oob */
	1964	if (desc != NULL)
	1965	oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
	1966
	1967	/* otherwise, do it inline */
	1968	else
	1969	{
	1970	/* load the target PC into P1 */
	1971	if (destpc != BRANCH_TARGET_DYNAMIC)
	1972	emit_mov_r32_imm(DRCTOP, REG_P1, destpc); // mov p1,destpc
	1973	else
	1974	emit_mov_r32_m32(DRCTOP, REG_P1, MBD(REG_RSP, SPOFFS_NEXTPC)); // mov p1,[esp+nextpc]
	1975
	1976	/* flush any live registers */
	1977	compiler_register_flush_all(drc, compiler);
	1978
	1979	/* if we subtracted cycles and went negative, time to exit */
	1980	emit_jcc(DRCTOP, COND_S, mips3.drc->exit_point); // js exit_point
	1981	}
	1982	}
	1983
	1984
	1985	/*------------------------------------------------------------------
1897	1986	emit_delay_slot_and_branch
1898	1987	------------------------------------------------------------------*/
1899	1988
r1103	r1104
1909	1998	assert(desc->delay != NULL);
1910	1999	compile_one(drc, &compiler_temp, desc->delay); // <next instruction>
1911	2000
1912		/* if we have cycles, subtract them now */
1913		if (compiler_temp.cycles != 0)
1914		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler_temp.cycles); // sub [icount],cycles
	2001	/* update the cycles and load the new PC in case we need to stop here */
	2002	emit_update_cycles_pc_and_flush(drc, &compiler_temp, NULL, desc->targetpc);
1915	2003
1916		/* load the target PC into P1 */
1917		if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
1918		emit_mov_r32_imm(DRCTOP, REG_P1, desc->targetpc); // mov p1,desc->targetpc
1919		else
1920		emit_mov_r32_m32(DRCTOP, REG_P1, MBD(REG_RSP, SPOFFS_NEXTPC)); // mov p1,[esp+nextpc]
1921
1922		/* flush any live registers */
1923		compiler_register_flush_all(drc, &compiler_temp);
1924
1925		/* if we subtracted cycles and went negative, time to exit */
1926		if (compiler_temp.cycles != 0)
1927		emit_jcc(DRCTOP, COND_S, mips3.drc->exit_point); // js exit_point
1928
1929	2004	/* otherwise, append a dispatcher */
1930	2005	if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
1931	2006	drc_append_tentative_fixed_dispatcher(drc, desc->targetpc, FALSE); // <redispatch>
r1103	r1104
2954	3029	return TRUE;
2955	3030
2956	3031	case COP0_Status:
	3032	emit_flush_cycles_before_instruction(drc, compiler, desc, 1);
2957	3033	emit_mov_r32_m32(DRCTOP, REG_EDX, CPR0ADDR(COP0_Status)); // mov edx,[Status]
2958	3034	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Status), REG_EAX); // mov [Status],eax
2959	3035	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EAX); // xor edx,eax
2960	3036	emit_test_r32_imm(DRCTOP, REG_EDX, 0x8000); // test edx,0x8000
2961	3037	emit_jcc_short_link(DRCTOP, COND_Z, &link1); // jz skip
2962	3038	emit_lea_r64_m64(DRCTOP, REG_P1, COREADDR); // lea p1,[mips3.core]
2963		emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->mips3com_update_cycle_counting));
2964		// call mips3com_update_cycle_counting
	3039	emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->mips3com_update_cycle_counting)); // call mips3com_update_cycle_counting
2965	3040	resolve_link(DRCTOP, &link1); // skip:
2966	3041	append_check_interrupts(drc, compiler, desc); // <check interrupts>
2967	3042	return TRUE;
2968	3043
2969	3044	case COP0_Count:
	3045	emit_flush_cycles_before_instruction(drc, compiler, desc, 1);
2970	3046	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Count), REG_EAX); // mov [Count],eax
2971	3047	emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->activecpu_gettotalcycles64)); // call activecpu_gettotalcycles64
2972	3048	emit_mov_r32_m32(DRCTOP, REG_EDX, CPR0ADDR(COP0_Count)); // mov edx,[Count]
2973	3049	emit_sub_r64_r64(DRCTOP, REG_RAX, REG_RDX); // sub rax,rdx
2974	3050	emit_sub_r64_r64(DRCTOP, REG_RAX, REG_RDX); // sub rax,rdx
2975		emit_mov_m64_r64(DRCTOP, MDRC(&mips3.core->count_zero_time), REG_RAX);
2976		// mov [count_zero_time],rax
	3051	emit_mov_m64_r64(DRCTOP, MDRC(&mips3.core->count_zero_time), REG_RAX); // mov [count_zero_time],rax
2977	3052	emit_lea_r64_m64(DRCTOP, REG_P1, COREADDR); // lea p1,[mips3.core]
2978		emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->mips3com_update_cycle_counting));
2979		// call mips3com_update_cycle_counting
	3053	emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->mips3com_update_cycle_counting)); // call mips3com_update_cycle_counting
2980	3054	return TRUE;
2981	3055
2982	3056	case COP0_Compare:
	3057	emit_flush_cycles_before_instruction(drc, compiler, desc, 1);
2983	3058	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Compare), REG_EAX); // mov [Compare],eax
2984	3059	emit_and_m32_imm(DRCTOP, CPR0ADDR(COP0_Cause), ~0x8000); // and [Cause],~0x8000
2985	3060	emit_lea_r64_m64(DRCTOP, REG_P1, COREADDR); // lea p1,[mips3.core]
2986		emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->mips3com_update_cycle_counting));
2987		// call mips3com_update_cycle_counting
	3061	emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->mips3com_update_cycle_counting)); // call mips3com_update_cycle_counting
2988	3062	return TRUE;
2989	3063
2990	3064	case COP0_PRId:
r1103	r1104
3019	3093	{
3020	3094	case COP0_Count:
3021	3095	compiler->cycles += MIPS3_COUNT_READ_CYCLES;
	3096	emit_flush_cycles_before_instruction(drc, compiler, desc, MIPS3_COUNT_READ_CYCLES);
3022	3097	emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->activecpu_gettotalcycles64)); // call activecpu_gettotalcycles64
3023	3098	emit_sub_r64_m64(DRCTOP, REG_RAX, MDRC(&mips3.core->count_zero_time)); // sub rax,[count_zero_time]
3024	3099	emit_shr_r64_imm(DRCTOP, REG_RAX, 1); // shr rax,1
r1103	r1104
3026	3101	return TRUE;
3027	3102
3028	3103	case COP0_Cause:
3029		compiler->cycles += MIPS3_COUNT_READ_CYCLES;
	3104	compiler->cycles += MIPS3_CAUSE_READ_CYCLES;
3030	3105	emit_movsxd_r64_m32(DRCTOP, REG_RAX, CPR0ADDR(COP0_Cause)); // movsxd rax,[Cause]
3031	3106	return TRUE;
3032	3107
3033	3108	case COP0_Random:
	3109	emit_flush_cycles_before_instruction(drc, compiler, desc, 1);
3034	3110	emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->activecpu_gettotalcycles64)); // call activecpu_gettotalcycles64
3035	3111	emit_mov_r32_m32(DRCTOP, REG_ECX, CPR0ADDR(COP0_Wired)); // mov ecx,[Wired]
3036	3112	emit_mov_r32_imm(DRCTOP, REG_R8D, 48); // mov r8d,48
r1103	r1104
4970	5046
4971	5047	/* update cycle counts */
4972	5048	if (!was_fixed)
4973		{
4974		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
4975		compiler->cycles = 0;
4976		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
4977		}
	5049	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
4978	5050	return TRUE;
4979	5051	}
4980	5052
r1103	r1104
5030	5102
5031	5103	/* update cycle counts */
5032	5104	if (!was_fixed)
5033		{
5034		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
5035		compiler->cycles = 0;
5036		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
5037		}
	5105	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
5038	5106	return TRUE;
5039	5107	}
5040	5108
r1103	r1104
5093	5161
5094	5162	/* update cycle counts */
5095	5163	if (!was_fixed)
5096		{
5097		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
5098		compiler->cycles = 0;
5099		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
5100		}
	5164	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
5101	5165	return TRUE;
5102	5166	}
5103	5167
r1103	r1104
5199	5263
5200	5264	/* update cycle counts */
5201	5265	if (!was_fixed)
5202		{
5203		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
5204		compiler->cycles = 0;
5205		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
5206		}
	5266	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
5207	5267	return TRUE;
5208	5268	}
5209	5269
r1103	r1104
5309	5369
5310	5370	/* update cycle counts */
5311	5371	if (!was_fixed)
5312		{
5313		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
5314		compiler->cycles = 0;
5315		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
5316		}
	5372	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
5317	5373	return TRUE;
5318	5374	}
5319	5375
r1103	r1104
5373	5429
5374	5430	/* update cycle counts */
5375	5431	if (!was_fixed)
5376		{
5377		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
5378		compiler->cycles = 0;
5379		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
5380		}
	5432	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
5381	5433	return TRUE;
5382	5434	}
5383	5435
r1103	r1104
5433	5485
5434	5486	/* update cycle counts */
5435	5487	if (!was_fixed)
5436		{
5437		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
5438		compiler->cycles = 0;
5439		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
5440		}
	5488	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
5441	5489	return TRUE;
5442	5490	}
5443	5491
r1103	r1104
5496	5544
5497	5545	/* update cycle counts */
5498	5546	if (!was_fixed)
5499		{
5500		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
5501		compiler->cycles = 0;
5502		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
5503		}
	5547	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
5504	5548	return TRUE;
5505	5549	}
5506	5550
r1103	r1104
5591	5635
5592	5636	/* update cycle counts */
5593	5637	if (!was_fixed)
5594		{
5595		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
5596		compiler->cycles = 0;
5597		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
5598		}
	5638	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
5599	5639	return TRUE;
5600	5640	}
5601	5641
r1103	r1104
5686	5726
5687	5727	/* update cycle counts */
5688	5728	if (!was_fixed)
5689		{
5690		emit_sub_m32_imm(DRCTOP, ICOUNTADDR, compiler->cycles);
5691		compiler->cycles = 0;
5692		oob_request_callback(drc, COND_S, oob_interrupt_cleanup, compiler, desc, mips3.drc->exit_point);
5693		}
	5729	emit_update_cycles_pc_and_flush(drc, compiler, desc, 0);
5694	5730	return TRUE;
5695	5731	}

src/emu/cpu/mips/mips3drc.c
r1103	r1104
42	42	CONFIGURATION
43	43	***************************************************************************/
44	44
45		#define CACHE_SIZE (32 * 1024 * 1024)
	45	/* size of the execution code cache */
	46	#define CACHE_SIZE (32 * 1024 * 1024)
46	47
	48	/* compilation boundaries -- how far back/forward does the analysis extend? */
	49	#define COMPILE_BACKWARDS_BYTES 128
	50	#define COMPILE_FORWARDS_BYTES 512
	51	#define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4))
	52	#define COMPILE_MAX_SEQUENCE 64
47	53
48	54	/* hack when running comparison against the C core */
49	55	#if COMPARE_AGAINST_C
r1103	r1104
170	176	{
171	177	drcfe_config feconfig =
172	178	{
173		128, /* code window start offset = startpc - window_start */
174		512, /* code window end offset = startpc + window_end */
175		32, /* maximum instructions to include in a sequence */
176		mips3fe_describe /* callback to describe a single instruction */
	179	COMPILE_BACKWARDS_BYTES, /* code window start offset = startpc - window_start */
	180	COMPILE_FORWARDS_BYTES, /* code window end offset = startpc + window_end */
	181	COMPILE_MAX_SEQUENCE, /* maximum instructions to include in a sequence */
	182	mips3fe_describe /* callback to describe a single instruction */
177	183	};
178	184
179	185	/* allocate a cache and memory for the core data in a single block */
r1103	r1104
228	234	drc_cache_reset(mips3.drc);
229	235	mips3.cache_dirty = FALSE;
230	236
231		/* update the cycle timing */
232		mips3com_update_cycle_counting(mips3.core);
233
234	237	/* execute */
235	238	mips3.core->icount = cycles;
236	239	drc_execute(mips3.drc);

src/emu/cpu/x64drc.c
r1103	r1104
162	162	memset(drc->lookup_l2_recompile, 0, sizeof(*drc->lookup_l2_recompile) << drc->l2bits);
163	163
164	164	/* allocate the sequence and tentative lists */
165		drc->sequence_count_max = config->max_instructions;
	165	drc->sequence_count_max = config->max_instructions * 2;
166	166	drc->sequence_list = malloc(drc->sequence_count_max * sizeof(*drc->sequence_list));
167	167	if (drc->sequence_list == NULL)
168	168	goto error;
169	169
170		drc->tentative_count_max = config->max_instructions;
	170	drc->tentative_count_max = config->max_instructions * 2;
171	171	drc->tentative_list = malloc(drc->tentative_count_max * sizeof(*drc->tentative_list));
172	172	if (drc->tentative_list == NULL)
173	173	goto error;

src/emu/cpu/mb86233/mb86233.c
r1103	r1104
40	40	UINT8 pcsp;
41	41	UINT32 eb;
42	42	UINT32 shift;
	43	UINT32 repcnt;
43	44	UINT16 sr;
44	45
45	46	UINT32 gpr[16];
r1103	r1104
83	84	#define GETARAM() mb86233.ARAM
84	85	#define GETBRAM() mb86233.BRAM
85	86	#define ALU(a) mb86233_alu(a)
	87	#define GETREPCNT() mb86233.repcnt
86	88
87	89	#define ROPCODE(a) cpu_readop32(a<<2)
88	90	#define RDMEM(a) program_read_dword_32le((a<<2))
r1103	r1104
623	625	return GETEB();
624	626	break;
625	627
	628	case 0x34:
	629	return GETREPCNT();
	630	break;
	631
626	632	default:
627	633	logerror( "TGP: Unknown GETREG (%d) at PC=%04x\n", reg, GETPC() );
628	634	break;
r1103	r1104
791	797	GETEB() = val;
792	798	break;
793	799
	800	case 0x34:
	801	GETREPCNT() = val;
	802	break;
	803
794	804	default:
795	805	{
796	806	fatalerror( "TGP: Unknown register write (r:%d, mode:%d) at PC:%04x\n", reg, mode, GETPC());
r1103	r1104
1323	1333	}
1324	1334	break;
1325	1335
	1336	case 0x1d: //LDIMM to Rep regs
	1337	{
	1338	UINT32 sub = (opcode>>24)&0x3;
	1339	UINT32 imm = opcode&0xffffff;
	1340	if(sub == 0x00)
	1341	{
	1342	GETREPCNT() = imm;
	1343	}
	1344	else
	1345	{
	1346	logerror( "TGP: Unknown LDIMM REPCnt (sub=%d) at PC:%04x\n", sub, GETPC() );
	1347	}
	1348	}
	1349	break;
	1350
1326	1351	case 0x2f: /* Conditional Branches */
1327	1352	{
1328	1353	UINT32 cond = ( opcode >> 20 ) & 0x1f;

src/emu/sound/scsp.c
r1103	r1104
31	31	#include "scsp.h"
32	32	#include "scspdsp.h"
33	33
	34
34	35	#define ICLIP16(x) (x<-32768)?-32768:((x>32767)?32767:x)
35	36
36	37	#define SHIFT 12
r1103	r1104
526	527
527	528	for(i=0;i<0x400;++i)
528	529	{
529		float fcent=(double) 1200.0*log_base_2((double)(((double) 1024.0+(double)i)/(double)1024.0));
530		fcent=(double) 44100.0*pow(2.0,fcent/1200.0);
	530	//float fcent=(double) 1200.0*log_base_2((double)(((double) 1024.0+(double)i)/(double)1024.0));
	531	//fcent=(double) 44100.0*pow(2.0,fcent/1200.0);
	532	float fcent=44100.0*(1024.0+(double) i)/1024.0;
531	533	FNS_Table[i]=(float) (1<<SHIFT) *fcent;
532	534	}
533	535
r1103	r1104
921	923	}\
922	924	if(_8bit)\
923	925	{\
924		signed char p=(signed char ) (slot->base+(slot->cur_addr>>SHIFT));\
	926	signed char p=(signed char ) (slot->base+BYTE_XOR_BE((slot->cur_addr>>SHIFT)));\
925	927	int s;\
926	928	signed int fpart=slot->cur_addr&((1<<SHIFT)-1);\
927		s=(int) p[0]((1<<SHIFT)-fpart)+(int) slot->Prevfpart;\
928		sample=(s>>SHIFT)<<8;\
929		slot->Prev=p[0];\
	929	s=(int) (p[0]<<8)((1<<SHIFT)-fpart)+(int) slot->Prevfpart;\
	930	sample=(s>>SHIFT);\
	931	slot->Prev=p[0]<<8;\
930	932	}\
931	933	else\
932	934	{\
933	935	signed short p=(signed short ) (slot->base+((slot->cur_addr>>(SHIFT-1))&(~1)));\
934		sample=(p[0]);\
	936	int s;\
	937	signed int fpart=slot->cur_addr&((1<<SHIFT)-1);\
	938	s=(int) (p[0])((1<<SHIFT)-fpart)+(int) slot->Prevfpart;\
	939	sample=(s>>SHIFT);\
	940	slot->Prev=p[0];\
935	941	}\
936	942	if(slot->Backwards)\
937	943	slot->cur_addr-=step;\
r1103	r1104
1123	1129	INT32 sample;
1124	1130	int step=slot->step;
1125	1131	UINT32 addr;
1126		INT32 smp;
1127	1132
1128	1133	if(SSCTL(slot)!=0) //no FM or noise yet
1129	1134	return 0;
r1103	r1104
1138	1143	addr=slot->cur_addr>>SHIFT;
1139	1144	else
1140	1145	addr=(slot->cur_addr>>(SHIFT-1)) & 0x7fffe;
	1146	/*
	1147	if(MDL(slot)!=0 \|\| MDXSL(slot)!=0 \|\| MDYSL(slot)!=0)
	1148	{
	1149	INT32 smp;
	1150	smp=(SCSP->RINGBUF[(SCSP->BUFPTR+MDXSL(slot))&63]+SCSP->RINGBUF[(SCSP->BUFPTR+MDYSL(slot))&63])/2;
1141	1151
1142		if(MDL(slot)!=0 \|\| MDXSL(slot)!=0 \|\| MDYSL(slot)!=0)
	1152	smp>>=11;
	1153	addr+=smp;
	1154	if(!PCM8B(slot))
	1155	addr&=0x7fffe;
	1156	else
	1157	addr&=0x7ffff;
	1158	}
	1159	*/
	1160	if(PCM8B(slot)) //8 bit signed
1143	1161	{
1144		smp=(SCSP->RINGBUF[(SCSP->BUFPTR+MDXSL(slot))&63]+SCSP->RINGBUF[(SCSP->BUFPTR+MDYSL(slot))&63])/2;
	1162	INT8 p=(INT8 ) (slot->base+BYTE_XOR_BE((slot->cur_addr>>SHIFT)));
	1163	INT32 s;
	1164	INT32 fpart=slot->cur_addr&((1<<SHIFT)-1);
	1165	s=(int) (p[0]<<8)((1<<SHIFT)-fpart)+(int) slot->Prevfpart;
	1166	sample=(s>>SHIFT);
	1167	slot->Prev=p[0]<<8;
1145	1168
1146		smp>>=11;
1147		addr+=smp;
1148		if(!PCM8B(slot))
1149		addr&=0x7fffe;
1150		else
1151		addr&=0x7ffff;
1152	1169	}
	1170	else //16 bit signed
	1171	{
	1172	INT16 p=(INT16 ) (slot->base+addr);
	1173	INT32 s;
	1174	INT32 fpart=slot->cur_addr&((1<<SHIFT)-1);
	1175	s=(int) (p[0])((1<<SHIFT)-fpart)+(int) slot->Prevfpart;
	1176	sample=(s>>SHIFT);
	1177	slot->Prev=p[0];
1153	1178
1154		if(PCM8B(slot)) //8 bit signed
1155		{
1156		INT8 p=(signed char ) (slot->base+(addr));
1157		sample=(p[0])<<8;
1158	1179	}
1159		else //16 bit signed (endianness?)
1160		{
1161		INT16 p=(signed short ) (slot->base+addr);
1162		sample=(p[0]);
1163		}
1164	1180
1165	1181	if(slot->Backwards)
1166	1182	slot->cur_addr-=step;

src/mess/audio/pc.h
r1103	r1104
1		/***************************************************************************
2
3		audio/pc.h
4
5		Functions to emulate a PC PIC timer 2 used for simple tone generation
6
7		TODO:
8		Add support for the SN76496 used in the Tandy1000/PCjr
9		It most probably is on port 0xc0, but I'm not sure...
10
11		****************************************************************************/
12
13		#ifndef __AUDIO_PC_H__
14		#define __AUDIO_PC_H__
15
16		#include "driver.h"
17
	1	/***************************************************************************
	2
	3	audio/pc.h
	4
	5	Functions to emulate a PC PIC timer 2 used for simple tone generation
	6
	7	TODO:
	8	Add support for the SN76496 used in the Tandy1000/PCjr
	9	It most probably is on port 0xc0, but I'm not sure...
	10
	11	****************************************************************************/
	12
	13	#ifndef __AUDIO_PC_H__
	14	#define __AUDIO_PC_H__
	15
	16	#include "driver.h"
	17
18	18	extern const struct CustomSound_interface pc_sound_interface;
19	19	void pc_sh_update(void param, stream_sample_t inputs, stream_sample_t *outputs, int samples);
20	20	void pc_sh_speaker(int mode);
21	21
22		void pc_sh_speaker_change_clock(double pc_clock);
23
24		#endif /* __AUDIO_PC_H__ */
	22	void pc_sh_speaker_change_clock(double pc_clock);
	23
	24	#endif /* __AUDIO_PC_H__ */

docs/messnew.txt
r1103	r1104
36	36
37	37	Source Changes:
38	38	----------------
39		- The core is based on MAME 0.119u3. This incorporates all features of the
	39	- The core is based on MAME 0.119u4. This incorporates all features of the
40	40	update to this core. [MAME team]
41	41
42	42	- Fixed multisession crash with the new menu selector. (bug #1328) [Nate

15994 Revisions