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r10784 Sunday 13th March, 2011 at 14:01:09 UTC by Dirk Best
Added preliminary Chips & Technologies CS4031 chipset emulation and a driver which uses it.
[src/mess]mess.mak messdriv.c
[src/mess/drivers]at.c
[src/mess/machine]at.c cs4031.c* cs4031.h*

src/mess/machine/at.c
r10783r10784
449449   address_space* space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
450450   soundblaster_config(&soundblaster);
451451
452   /* MESS managed RAM */
453   memory_set_bankptr(machine, "bank10", ram_get_ptr(machine->device(RAM_TAG)));
452   // The CS4031 chipset does this itself
453   if (machine->device("cs4031") == NULL)
454   {
455      /* MESS managed RAM */
456      memory_set_bankptr(machine, "bank10", ram_get_ptr(machine->device(RAM_TAG)));
454457
455   if (ram_get_size(machine->device(RAM_TAG)) > 0x0a0000)
456   {
457      offs_t ram_limit = 0x100000 + ram_get_size(machine->device(RAM_TAG)) - 0x0a0000;
458      memory_install_read_bank(space, 0x100000,  ram_limit - 1, 0, 0, "bank1");
459      memory_install_write_bank(space, 0x100000,  ram_limit - 1, 0, 0, "bank1");
460      memory_set_bankptr(machine, "bank1", ram_get_ptr(machine->device(RAM_TAG)) + 0xa0000);
458      if (ram_get_size(machine->device(RAM_TAG)) > 0x0a0000)
459      {
460         offs_t ram_limit = 0x100000 + ram_get_size(machine->device(RAM_TAG)) - 0x0a0000;
461         memory_install_read_bank(space, 0x100000,  ram_limit - 1, 0, 0, "bank1");
462         memory_install_write_bank(space, 0x100000,  ram_limit - 1, 0, 0, "bank1");
463         memory_set_bankptr(machine, "bank1", ram_get_ptr(machine->device(RAM_TAG)) + 0xa0000);
464      }
461465   }
462466
463467   /* FDC/HDC hardware */
src/mess/machine/cs4031.c
r0r10784
1/***************************************************************************
2
3   Chips & Technologies CS4031 chipset
4
5   Chipset for 486 based PC/AT compatible systems. Consists of two
6   individual chips:
7
8   * F84031
9      - DRAM controller
10      - ISA-bus controller
11      - VESA VL-BUS controller
12
13   * F84035
14      - 2x 8257 DMA controller
15      - 2x 8259 interrupt controller
16      - 8254 timer
17      - MC14818 RTC
18
19***************************************************************************/
20
21#include "emu.h"
22#include "machine/ram.h"
23#include "machine/cs4031.h"
24
25
26//**************************************************************************
27//  GLOBAL VARIABLES
28//**************************************************************************
29
30#define LOG_REGISTER   1
31#define LOG_MEMORY      1
32
33const device_type CS4031 = cs4031_device_config::static_alloc_device_config;
34
35enum
36{
37   DMA_WAIT_STATE = 0x01,
38   PERFORMANCE = 0x08,
39   F84035_MISC = 0x09,
40   DMA_CLOCK = 0x0a,
41   SHADOW_READ = 0x19,
42   SHADOW_WRITE = 0x1a,
43   ROMCS = 0x1b
44};
45
46static const char *const register_names[] =
47{
48   /* 00 */ "RESERVED",
49   /* 01 */ "DMA WAIT STATE CONTROL",
50   /* 02 */ "RESERVED",
51   /* 03 */ "RESERVED",
52   /* 04 */ "RESERVED",
53   /* 05 */ "ISA BUS COMMAND DELAY",
54   /* 06 */ "ISA BUS WAIT STATES AND ADDRESS HOLD",
55   /* 07 */ "ISA BUS CLOCK SELECTION",
56   /* 08 */ "PERFORMANCE CONTROL",
57   /* 09 */ "84035 MISC CONTROL",
58   /* 0a */ "DMA CLOCK SELECTION",
59   /* 0b */ "RESERVED",
60   /* 0c */ "RESERVED",
61   /* 0d */ "RESERVED",
62   /* 0e */ "RESERVED",
63   /* 0f */ "RESERVED",
64   /* 10 */ "DRAM TIMING",
65   /* 11 */ "DRAM SETUP",
66   /* 12 */ "DRAM CONFIGURATION 0 AND 1",
67   /* 13 */ "DRAM CONFIGURATION 2 AND 3",
68   /* 14 */ "DRAM BLOCK 0 STARTING ADDRESS",
69   /* 15 */ "DRAM BLOCK 1 STARTING ADDRESS",
70   /* 16 */ "DRAM BLOCK 2 STARTING ADDRESS",
71   /* 17 */ "DRAM BLOCK 3 STARTING ADDRESS",
72   /* 18 */ "VIDEO AREA SHADOW AND LOCAL BUS CONTROL",
73   /* 19 */ "DRAM SHADOW READ ENABLE",
74   /* 1a */ "DRAM SHADOW WRITE ENABLE",
75   /* 1b */ "ROMCS ENABLE",
76   /* 1c */ "SOFT RESET AND GATEA20",
77   /* 1d */ "RESERVED",
78   /* 1e */ "RESERVED",
79   /* 1f */ "RESERVED"
80};
81
82
83//**************************************************************************
84//  DEVICE CONFIGURATION
85//**************************************************************************
86
87//-------------------------------------------------
88//  cs4031_device_config - constructor
89//-------------------------------------------------
90
91cs4031_device_config::cs4031_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock)
92   : device_config(mconfig, static_alloc_device_config, "CS4031", tag, owner, clock)
93{
94}
95
96//-------------------------------------------------
97//  static_alloc_device_config - allocate a new
98//  configuration object
99//-------------------------------------------------
100
101device_config *cs4031_device_config::static_alloc_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock)
102{
103   return global_alloc(cs4031_device_config(mconfig, tag, owner, clock));
104}
105
106//-------------------------------------------------
107//  alloc_device - allocate a new device object
108//-------------------------------------------------
109
110device_t *cs4031_device_config::alloc_device(running_machine &machine) const
111{
112   return auto_alloc(&machine, cs4031_device(machine, *this));
113}
114
115void cs4031_device_config::static_set_cputag(device_config *device, const char *tag)
116{
117   cs4031_device_config *cs4031 = downcast<cs4031_device_config *>(device);
118   cs4031->m_cputag = tag;
119}
120
121void cs4031_device_config::static_set_isatag(device_config *device, const char *tag)
122{
123   cs4031_device_config *cs4031 = downcast<cs4031_device_config *>(device);
124   cs4031->m_isatag = tag;
125}
126
127void cs4031_device_config::static_set_biostag(device_config *device, const char *tag)
128{
129   cs4031_device_config *cs4031 = downcast<cs4031_device_config *>(device);
130   cs4031->m_biostag = tag;
131}
132
133
134//**************************************************************************
135//  LIVE DEVICE
136//**************************************************************************
137
138//-------------------------------------------------
139//  cs4031_device - constructor
140//-------------------------------------------------
141
142cs4031_device::cs4031_device(running_machine &_machine, const cs4031_device_config &config) :
143   device_t(_machine, config),
144   m_config(config),
145   m_address(0),
146   m_address_valid(false)
147{
148}
149
150//-------------------------------------------------
151//  device_start - device-specific startup
152//-------------------------------------------------
153
154void cs4031_device::device_start()
155{
156   device_t *ram_device = m_machine.device(RAM_TAG);
157
158   // make sure the ram device is already running
159   if (!ram_device->started())
160      throw device_missing_dependencies();
161
162   device_t *cpu = m_machine.device(m_config.m_cputag);
163   m_space = cpu_get_address_space(cpu, ADDRESS_SPACE_PROGRAM);
164   m_isa = m_machine.region(m_config.m_isatag)->base();
165   m_bios = m_machine.region(m_config.m_biostag)->base();
166
167   m_ram = ram_get_ptr(ram_device);
168   UINT32 ram_size = ram_get_size(ram_device);
169
170   // install base memory
171   memory_install_ram(m_space, 0x000000, 0x09ffff, 0, 0, m_ram);
172
173   // install extended memory
174   memory_install_ram(m_space, 0x100000, ram_size - 1, 0, 0, m_ram + 0x100000);
175
176   // install bios rom at cpu inital pc
177   memory_install_rom(m_space, 0xffff0000, 0xffffffff, 0, 0, m_bios + 0xf0000);
178}
179
180//-------------------------------------------------
181//  device_reset - device-specific reset
182//-------------------------------------------------
183
184void cs4031_device::device_reset()
185{
186   // setup default values
187   memset(&m_registers, 0x00, sizeof(m_registers));
188   m_registers[ROMCS] = 0x60;
189
190   // update rom/ram regions below 1mb
191   update_read_regions();
192   update_write_regions();
193}
194
195
196//**************************************************************************
197//  READ/WRITE HANDLERS
198//**************************************************************************
199
200void cs4031_device::update_read_region(int index, const char *region, offs_t start, offs_t end)
201{
202   if (!BIT(m_registers[SHADOW_READ], index) && BIT(m_registers[ROMCS], index))
203   {
204      if (LOG_MEMORY)
205         logerror("ROM read from %x to %x\n", start, end);
206
207      memory_install_read_bank(m_space, start, end, 0, 0, region);
208      memory_set_bankptr(m_space->machine, region, m_bios + start);
209   }
210   else if (!BIT(m_registers[SHADOW_READ], index) && !BIT(m_registers[ROMCS], index))
211   {
212      if (LOG_MEMORY)
213         logerror("ISA read from %x to %x\n", start, end);
214
215      memory_install_read_bank(m_space, start, end, 0, 0, region);
216      memory_set_bankptr(m_space->machine, region, m_isa + start);
217   }
218   else if (BIT(m_registers[SHADOW_READ], index))
219   {
220      if (LOG_MEMORY)
221         logerror("RAM read from %x to %x\n", start, end);
222
223      memory_install_read_bank(m_space, start, end, 0, 0, region);
224      memory_set_bankptr(m_space->machine, region, m_ram + start);
225   }
226   else
227   {
228      if (LOG_MEMORY)
229         logerror("NOP read from %x to %x\n", start, end);
230
231      memory_nop_read(m_space, start, end, 0, 0);
232   }
233}
234
235void cs4031_device::update_write_region(int index, const char *region, offs_t start, offs_t end)
236{
237   if (!BIT(m_registers[SHADOW_WRITE], index) && BIT(m_registers[ROMCS], index) && BIT(m_registers[ROMCS], 7))
238   {
239      if (LOG_MEMORY)
240         logerror("ROM write from %x to %x\n", start, end);
241
242      memory_install_write_bank(m_space, start, end, 0, 0, region);
243      memory_set_bankptr(m_space->machine, region, m_bios + start);
244   }
245   else if (!BIT(m_registers[SHADOW_WRITE], index) && !BIT(m_registers[ROMCS], index))
246   {
247      if (LOG_MEMORY)
248         logerror("ISA write from %x to %x\n", start, end);
249
250      memory_install_write_bank(m_space, start, end, 0, 0, region);
251      memory_set_bankptr(m_space->machine, region, m_isa + start);
252   }
253   else if (BIT(m_registers[SHADOW_WRITE], index))
254   {
255      if (LOG_MEMORY)
256         logerror("RAM write from %x to %x\n", start, end);
257
258      memory_install_write_bank(m_space, start, end, 0, 0, region);
259      memory_set_bankptr(m_space->machine, region, m_ram + start);
260   }
261   else
262   {
263      if (LOG_MEMORY)
264         logerror("NOP write from %x to %x\n", start, end);
265
266      memory_nop_write(m_space, start, end, 0 ,0);
267   }
268}
269
270void cs4031_device::update_read_regions()
271{
272   update_read_region(0, "read_c0000", 0xc0000, 0xc3fff);
273   update_read_region(1, "read_c4000", 0xc4000, 0xc7fff);
274   update_read_region(2, "read_c8000", 0xc8000, 0xcbfff);
275   update_read_region(3, "read_cc000", 0xcc000, 0xcffff);
276   update_read_region(4, "read_d0000", 0xd0000, 0xdffff);
277   update_read_region(5, "read_e0000", 0xe0000, 0xeffff);
278   update_read_region(6, "read_f0000", 0xf0000, 0xfffff);
279}
280
281void cs4031_device::update_write_regions()
282{
283   update_write_region(0, "write_c0000", 0xc0000, 0xc3fff);
284   update_write_region(1, "write_c4000", 0xc4000, 0xc7fff);
285   update_write_region(2, "write_c8000", 0xc8000, 0xcbfff);
286   update_write_region(3, "write_cc000", 0xcc000, 0xcffff);
287   update_write_region(4, "write_d0000", 0xd0000, 0xdffff);
288   update_write_region(5, "write_e0000", 0xe0000, 0xeffff);
289   update_write_region(6, "write_f0000", 0xf0000, 0xfffff);
290}
291
292WRITE8_MEMBER( cs4031_device::address_w )
293{
294   m_address = data;
295   m_address_valid = (m_address < 0x20) ? true : false;
296}
297
298READ8_MEMBER( cs4031_device::data_r )
299{
300   UINT8 result = 0xff;
301
302   if (m_address_valid)
303   {
304      if (LOG_REGISTER)
305         logerror("cs4031_device: read %s = %02x\n", register_names[m_address], m_registers[m_address]);
306
307      result = m_registers[m_address];
308   }
309
310   // after a read the selected address needs to be reset
311   m_address_valid = false;
312
313   return result;
314}
315
316WRITE8_MEMBER( cs4031_device::data_w )
317{
318   if (m_address_valid)
319   {
320      if (LOG_REGISTER)
321         logerror("cs4031_device: write %s = %02x\n", register_names[m_address], data);
322
323      // update register with new data
324      m_registers[m_address] = data;
325
326      // execute command
327      switch (m_address)
328      {
329      case 0x01: break;
330      case 0x05: break;
331      case 0x06: break;
332      case 0x07: break;
333      case 0x08: break;
334      case 0x09: break;
335      case 0x0a: break;
336      case 0x10: break;
337      case 0x11: break;
338      case 0x12: break;
339      case 0x13: break;
340      case 0x14: break;
341      case 0x15: break;
342      case 0x16: break;
343      case 0x17: break;
344      case 0x18: break;
345
346      case 0x19:
347         update_read_regions();
348         break;
349
350      case 0x1a:
351         update_write_regions();
352         break;
353
354      case 0x1b:
355         update_read_regions();
356         update_write_regions();
357         break;
358
359      case 0x1c: break;
360      }
361   }
362
363   // after a write the selected address needs to be reset
364   m_address_valid = false;
365}
src/mess/machine/cs4031.h
r0r10784
1/***************************************************************************
2
3   Chips & Technologies CS4031 chipset
4
5   Chipset for 486 based PC/AT compatible systems. Consists of two
6   individual chips:
7
8   * F84031
9      - DRAM controller
10      - ISA-bus controller
11      - VESA VL-BUS controller
12
13   * F84035
14      - 2x 8257 DMA controller
15      - 2x 8259 interrupt controller
16      - 8254 timer
17      - MC14818 RTC
18
19***************************************************************************/
20
21#pragma once
22
23#ifndef __CS4031_H__
24#define __CS4031_H__
25
26#include "emu.h"
27
28
29//**************************************************************************
30//  INTERFACE CONFIGURATION MACROS
31//**************************************************************************
32
33#define MCFG_CS4031_ADD(_tag, _cputag, _isatag, _biostag) \
34    MCFG_DEVICE_ADD(_tag, CS4031, 0) \
35    cs4031_device_config::static_set_cputag(device, _cputag); \
36    cs4031_device_config::static_set_isatag(device, _isatag); \
37    cs4031_device_config::static_set_biostag(device, _biostag);
38
39
40//**************************************************************************
41//  TYPE DEFINITIONS
42//**************************************************************************
43
44// ======================> cs4031_device_config
45
46class cs4031_device_config : public device_config
47{
48   friend class cs4031_device;
49
50   // construction/destruction
51   cs4031_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock);
52
53public:
54   // allocators
55   static device_config *static_alloc_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock);
56   virtual device_t *alloc_device(running_machine &machine) const;
57
58   // inline configuration
59   static void static_set_cputag(device_config *device, const char *tag);
60   static void static_set_isatag(device_config *device, const char *tag);
61   static void static_set_biostag(device_config *device, const char *tag);
62
63   const char *m_cputag;
64   const char *m_isatag;
65   const char *m_biostag;
66};
67
68
69// ======================> cs4031_device
70
71class cs4031_device : public device_t
72{
73   friend class cs4031_device_config;
74
75   // construction/destruction
76   cs4031_device(running_machine &_machine, const cs4031_device_config &config);
77
78public:
79   DECLARE_WRITE8_MEMBER( address_w );
80   DECLARE_READ8_MEMBER( data_r );
81   DECLARE_WRITE8_MEMBER( data_w );
82
83protected:
84   // device-level overrides
85   virtual void device_start();
86   virtual void device_reset();
87
88private:
89   void update_read_region(int index, const char *region, offs_t start, offs_t end);
90   void update_write_region(int index, const char *region, offs_t start, offs_t end);
91   void update_read_regions();
92   void update_write_regions();
93
94   // internal state
95   const cs4031_device_config &m_config;
96
97   address_space *m_space;
98   UINT8 *m_isa;
99   UINT8 *m_bios;
100   UINT8 *m_ram;
101
102   // address selection
103   UINT8 m_address;
104   bool m_address_valid;
105
106   UINT8 m_registers[0x20];
107};
108
109
110// device type definition
111extern const device_type CS4031;
112
113
114#endif   /* __CS4031_H__ */
src/mess/messdriv.c
r10783r10784
668668   DRIVER( neat )     /* 1989 New Enhanced AT chipset, AMI BIOS    */
669669   DRIVER( at386 )    /* 19?? IBM AT 386   */
670670   DRIVER( at486 )    /* 19?? IBM AT 486   */
671   DRIVER( ct486 )      /* 1993? 486 with CS4031 */
671672   DRIVER( ficpio2 )   /* 1995 FIC 486-PIO-2 */
672673   DRIVER( at586 )    /* 19?? AT 586   */
673674   DRIVER( c386sx16 )   /* 1990 Commodore 386SX-16 */
src/mess/mess.mak
r10783r10784
702702   $(MESS_MACHINE)/at_keybc.o   \
703703   $(MESS_MACHINE)/pc_ide.o   \
704704   $(MESS_MACHINE)/ps2.o      \
705   $(MESS_MACHINE)/cs4031.o   \
705706   $(MESS_MACHINE)/at.o      \
706707   $(MESS_DRIVERS)/at.o      \
707708
src/mess/drivers/at.c
r10783r10784
2020#include "machine/pic8259.h"
2121#include "machine/i82371ab.h"
2222#include "machine/i82439tx.h"
23
23#include "machine/cs4031.h"
2424#include "machine/pit8253.h"
2525#include "video/pc_vga_mess.h"
2626#include "video/pc_cga.h"
r10783r10784
101101   AM_RANGE(0x00ff0000, 0x00ffffff) AM_ROM AM_REGION("maincpu", 0x0f0000)
102102ADDRESS_MAP_END
103103
104// memory is mostly handled by the chipset
105static ADDRESS_MAP_START( ct486_map, ADDRESS_SPACE_PROGRAM, 32 )
106   AM_RANGE(0x00800000, 0x00800bff) AM_RAM AM_SHARE("nvram")
107ADDRESS_MAP_END
108
109
104110static ADDRESS_MAP_START( at586_map, ADDRESS_SPACE_PROGRAM, 32 )
105111   AM_RANGE(0x00000000, 0x0009ffff) AM_RAMBANK("bank10")
106112   AM_RANGE(0x000a0000, 0x000bffff) AM_NOP
r10783r10784
216222ADDRESS_MAP_END
217223
218224
225static READ32_HANDLER( ct486_chipset_r )
226{
227   at_state *state = space->machine->driver_data<at_state>();
219228
229   if (ACCESSING_BITS_0_7)
230      return pic8259_r(state->pic8259_master, 0);
231
232   if (ACCESSING_BITS_8_15)
233      return pic8259_r(state->pic8259_master, 1) << 8;
234
235   if (ACCESSING_BITS_24_31)
236      return downcast<cs4031_device *>(space->machine->device("cs4031"))->data_r(*space, 0, 0) << 24;
237
238   return 0xffffffff;
239}
240
241static WRITE32_HANDLER( ct486_chipset_w )
242{
243   at_state *state = space->machine->driver_data<at_state>();
244
245   if (ACCESSING_BITS_0_7)
246      pic8259_w(state->pic8259_master, 0, data);
247
248   if (ACCESSING_BITS_8_15)
249      pic8259_w(state->pic8259_master, 1, data >> 8);
250
251   if (ACCESSING_BITS_16_23)
252      downcast<cs4031_device *>(space->machine->device("cs4031"))->address_w(*space, 0, data >> 16, 0);
253
254   if (ACCESSING_BITS_24_31)
255      downcast<cs4031_device *>(space->machine->device("cs4031"))->data_w(*space, 0, data >> 24, 0);
256}
257
258static ADDRESS_MAP_START( ct486_io, ADDRESS_SPACE_IO, 32 )
259   AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_r, i8237_w, 0xffffffff)
260   AM_RANGE(0x0020, 0x0023) AM_READWRITE(ct486_chipset_r, ct486_chipset_w)
261   AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
262   AM_RANGE(0x0060, 0x0063) AM_READWRITE8(at_keybc_r, at_keybc_w, 0xffff)
263   AM_RANGE(0x0064, 0x0067) AM_DEVREADWRITE8_MODERN("keybc", at_keyboard_controller_device, status_r, command_w, 0xffff)
264   AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8_MODERN("rtc", mc146818_device, read, write , 0xffffffff)
265   AM_RANGE(0x0080, 0x009f) AM_READWRITE8(at_page8_r,            at_page8_w, 0xffffffff)
266   AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_slave", pic8259_r, pic8259_w, 0xffffffff)
267   AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE8("dma8237_2", at_dma8237_1_r, at_dma8237_1_w, 0xffffffff)
268   AM_RANGE(0x0278, 0x027f) AM_DEVREADWRITE8("lpt_2", pc_lpt_r, pc_lpt_w, 0x000000ff)
269   AM_RANGE(0x02e8, 0x02ef) AM_DEVREADWRITE8("ns16450_3", ins8250_r, ins8250_w, 0xffffffff)
270   AM_RANGE(0x02f8, 0x02ff) AM_DEVREADWRITE8("ns16450_1", ins8250_r, ins8250_w, 0xffffffff)
271   AM_RANGE(0x0320, 0x0323) AM_READWRITE(pc32le_HDC1_r,         pc32le_HDC1_w)
272   AM_RANGE(0x0324, 0x0327) AM_READWRITE(pc32le_HDC2_r,         pc32le_HDC2_w)
273   AM_RANGE(0x0378, 0x037f) AM_DEVREADWRITE8("lpt_1", pc_lpt_r, pc_lpt_w, 0x000000ff)
274   AM_RANGE(0x03f0, 0x03f7) AM_READWRITE8(pc_fdc_r,            pc_fdc_w, 0xffffffff)
275   AM_RANGE(0x03bc, 0x03bf) AM_DEVREADWRITE8("lpt_0", pc_lpt_r, pc_lpt_w, 0x000000ff)
276   AM_RANGE(0x03f8, 0x03ff) AM_DEVREADWRITE8("ns16450_0", ins8250_r, ins8250_w, 0xffffffff)
277ADDRESS_MAP_END
278
279
220280static ADDRESS_MAP_START(at586_io, ADDRESS_SPACE_IO, 32)
221281   AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_r, i8237_w, 0xffffffff)
222282   AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_master", pic8259_r, pic8259_w, 0xffffffff)
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853913   MCFG_CPU_IO_MAP(at386_io)
854914MACHINE_CONFIG_END
855915
916
917static MACHINE_CONFIG_DERIVED( ct486, at386 )
918   MCFG_CPU_REPLACE("maincpu", I486, 25000000)
919   MCFG_CPU_PROGRAM_MAP(ct486_map)
920   MCFG_CPU_IO_MAP(ct486_io)
921
922   MCFG_CS4031_ADD("cs4031", "maincpu", "isa", "bios")
923
924   MCFG_DEVICE_REMOVE(RAM_TAG)
925   MCFG_RAM_ADD(RAM_TAG)
926   MCFG_RAM_DEFAULT_SIZE("4M")
927   MCFG_RAM_EXTRA_OPTIONS("1M,2M,8M,16M,32M,64M")
928MACHINE_CONFIG_END
929
930
856931static MACHINE_CONFIG_DERIVED( at586, at386 )
857932
858933   MCFG_CPU_REPLACE("maincpu", PENTIUM, 60000000)
r10783r10784
12501325ROM_END
12511326
12521327
1328// Unknown 486 board with Chips & Technologies CS4031 chipset
1329ROM_START( ct486 )
1330   ROM_REGION(0x100000, "isa", 0)
1331   ROM_LOAD("et4000.bin",  0xc0000, 0x08000, CRC(f01e4be0) SHA1(95d75ff41bcb765e50bd87a8da01835fd0aa01d5))
1332   ROM_LOAD("wdbios.rom",  0xc8000, 0x02000, CRC(8e9e2bd4) SHA1(601d7ceab282394ebab50763c267e915a6a2166a))
1333
1334   ROM_REGION(0x100000, "bios", 0)
1335   ROM_LOAD("chips_1.ami", 0xf0000, 0x10000, CRC(a14a7511) SHA1(b88d09be66905ed2deddc26a6f8522e7d2d6f9a8))
1336ROM_END
1337
1338
12531339// FIC 486-PIO-2 (4 ISA, 4 PCI)
12541340// VIA VT82C505 + VT82C496G + VT82C406MV, NS311/312 or NS332 I/O
12551341ROM_START( ficpio2 )
r10783r10784
13601446COMP ( 1987, atvga,    ibm5170, 0,       atvga,     atvga,   at_vga,     "<generic>",  "PC/AT (VGA, MF2 Keyboard)" , GAME_NOT_WORKING )
13611447COMP ( 1988, at386,    ibm5170, 0,       at386,     atvga,   at386,      "<generic>",  "PC/AT 386 (VGA, MF2 Keyboard)", GAME_NOT_WORKING )
13621448COMP ( 1990, at486,    ibm5170, 0,       at486,     atvga,   at386,      "<generic>",  "PC/AT 486 (VGA, MF2 Keyboard)", GAME_NOT_WORKING )
1449COMP ( 1993, ct486,    ibm5170, 0,       ct486,     atvga,   at386,      "<unknown>",  "PC/AT 486 with C&T chipset", GAME_NOT_WORKING )
13631450COMP ( 1995, ficpio2,  ibm5170, 0,       at486,     atvga,  at386,      "FIC", "486-PIO-2", GAME_NOT_WORKING )
13641451COMP ( 1990, at586,    ibm5170, 0,       at586,     atvga,   at386,      "<generic>",  "PC/AT 586 (VGA, MF2 Keyboard)", GAME_NOT_WORKING )
13651452COMP ( 1990, c386sx16, ibm5170, 0,       c386sx16,  atvga,  at386,      "Commodore Business Machines", "Commodore 386SX-16", GAME_NOT_WORKING )

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