r8635 Monday 26th July, 2010 at 16:04:03 UTC by Wilbert Pol
[3DO] updated to use arm7 in big endian mode (arm6 in 32bit mode).
[src/emu/cpu/arm7]arm7.c arm7.h arm7core.c arm7core.h arm7dasm.c
[src/mess/drivers]3do.c
[src/mess/machine]3do.c

src/emu/cpu/arm7/arm7core.c
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135135    }
136136
137137    addr &= ~3;
138    memory_write_dword_32le(cpustate->program, addr, data);
138   if ( cpustate->endian == ENDIANNESS_BIG )
139      memory_write_dword_32be(cpustate->program, addr, data);
140   else
141       memory_write_dword_32le(cpustate->program, addr, data);
139142}
140143
141144
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147150    }
148151
149152    addr &= ~1;
150    memory_write_word_32le(cpustate->program, addr, data);
153   if ( cpustate->endian == ENDIANNESS_BIG )
154      memory_write_word_32be(cpustate->program, addr, data);
155   else
156      memory_write_word_32le(cpustate->program, addr, data);
151157}
152158
153159INLINE void arm7_cpu_write8(arm_state *cpustate, UINT32 addr, UINT8 data)
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157163        addr = arm7_tlb_translate( cpustate, addr );
158164    }
159165
160    memory_write_byte_32le(cpustate->program, addr, data);
166   if ( cpustate->endian == ENDIANNESS_BIG )
167      memory_write_byte_32be(cpustate->program, addr, data);
168   else
169      memory_write_byte_32le(cpustate->program, addr, data);
161170}
162171
163172INLINE UINT32 arm7_cpu_read32(arm_state *cpustate, offs_t addr)
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171180
172181    if (addr & 3)
173182    {
174        result = memory_read_dword_32le(cpustate->program, addr & ~3);
183      if ( cpustate->endian == ENDIANNESS_BIG )
184         result = memory_read_dword_32be(cpustate->program, addr & ~3);
185      else
186         result = memory_read_dword_32le(cpustate->program, addr & ~3);
175187        result = (result >> (8 * (addr & 3))) | (result << (32 - (8 * (addr & 3))));
176188    }
177189    else
178190    {
179        result = memory_read_dword_32le(cpustate->program, addr);
191      if ( cpustate->endian == ENDIANNESS_BIG )
192         result = memory_read_dword_32be(cpustate->program, addr);
193      else
194         result = memory_read_dword_32le(cpustate->program, addr);
180195    }
181196
182197    return result;
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191206        addr = arm7_tlb_translate( cpustate, addr );
192207    }
193208
194    result = memory_read_word_32le(cpustate->program, addr & ~1);
209   if ( cpustate->endian == ENDIANNESS_BIG )
210      result = memory_read_word_32be(cpustate->program, addr & ~1);
211   else
212      result = memory_read_word_32le(cpustate->program, addr & ~1);
195213
196214    if (addr & 1)
197215    {
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209227    }
210228
211229    // Handle through normal 8 bit handler (for 32 bit cpu)
212    return memory_read_byte_32le(cpustate->program, addr);
230   if ( cpustate->endian == ENDIANNESS_BIG )
231      return memory_read_byte_32be(cpustate->program, addr);
232   else
233      return memory_read_byte_32le(cpustate->program, addr);
213234}
214235
215236/***************
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553574    cpustate->irq_callback = save_irqcallback;
554575    cpustate->device = device;
555576    cpustate->program = device->space(AS_PROGRAM);
577   cpustate->endian = ENDIANNESS_LITTLE;
556578
557579    /* start up in SVC mode with interrupts disabled. */
558580    SwitchMode(cpustate, eARM7_MODE_SVC);
src/emu/cpu/arm7/arm7core.h
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160160    UINT8 pendingUnd;                   \
161161    UINT8 pendingSwi;                   \
162162    INT32 iCount;         \
163   endianness_t endian;            \
163164    device_irq_callback irq_callback;      \
164165    legacy_cpu_device *device;      \
165166    const address_space *program;
src/emu/cpu/arm7/arm7.c
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7171INLINE arm_state *get_safe_token(running_device *device)
7272{
7373   assert(device != NULL);
74   assert(device->type() == ARM7 || device->type() == ARM9 || device->type() == PXA255);
74   assert(device->type() == ARM7 || device->type() == ARM7_BE || device->type() == ARM9 || device->type() == PXA255);
7575   return (arm_state *)downcast<legacy_cpu_device *>(device)->token();
7676}
7777
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236236   cpustate->archFlags = eARM_ARCHFLAGS_T;   // has Thumb
237237}
238238
239static CPU_RESET( arm7_be )
240{
241   arm_state *cpustate = get_safe_token(device);
242
243   CPU_RESET_CALL( arm7 );
244   cpustate->endian = ENDIANNESS_BIG;
245}
246
239247static CPU_RESET( arm9 )
240248{
241249   arm_state *cpustate = get_safe_token(device);
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300308       return CPU_DISASSEMBLE_CALL(arm7arm);
301309}
302310
311static CPU_DISASSEMBLE( arm7_be )
312{
313   CPU_DISASSEMBLE( arm7arm_be );
314   CPU_DISASSEMBLE( arm7thumb_be );
303315
316   arm_state *cpustate = get_safe_token(device);
317
318   if (T_IS_SET(GET_CPSR))
319      return CPU_DISASSEMBLE_CALL(arm7thumb_be);
320   else
321      return CPU_DISASSEMBLE_CALL(arm7arm_be);
322}
323
324
304325/**************************************************************************
305326 * Generic set_info
306327 **************************************************************************/
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553574    }
554575}
555576
577
578CPU_GET_INFO( arm7_be )
579{
580   switch (state)
581   {
582      case DEVINFO_INT_ENDIANNESS:      info->i = ENDIANNESS_BIG;                        break;
583      case CPUINFO_FCT_RESET:            info->reset = CPU_RESET_NAME(arm7_be);               break;
584      case CPUINFO_FCT_DISASSEMBLE:      info->disassemble = CPU_DISASSEMBLE_NAME(arm7_be);      break;
585      case DEVINFO_STR_NAME:            strcpy(info->s, "ARM7 (big endian)");               break;
586      default:                     CPU_GET_INFO_CALL(arm7);
587   }
588}
589
556590CPU_GET_INFO( arm9 )
557591{
558592    switch (state)
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837871}
838872
839873DEFINE_LEGACY_CPU_DEVICE(ARM7, arm7);
874DEFINE_LEGACY_CPU_DEVICE(ARM7_BE, arm7_be);
840875DEFINE_LEGACY_CPU_DEVICE(ARM9, arm9);
841876DEFINE_LEGACY_CPU_DEVICE(PXA255, pxa255);
842877DEFINE_LEGACY_CPU_DEVICE(SA1110, sa1110);
src/emu/cpu/arm7/arm7.h
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3939 ***************************************************************************************************/
4040
4141DECLARE_LEGACY_CPU_DEVICE(ARM7, arm7);
42DECLARE_LEGACY_CPU_DEVICE(ARM7_BE, arm7_be);
4243DECLARE_LEGACY_CPU_DEVICE(ARM9, arm9);
4344DECLARE_LEGACY_CPU_DEVICE(PXA255, pxa255);
4445DECLARE_LEGACY_CPU_DEVICE(SA1110, sa1110);
src/emu/cpu/arm7/arm7dasm.c
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13171317   return arm7_disasm(buffer, pc, oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24)) | 4;
13181318}
13191319
1320CPU_DISASSEMBLE( arm7arm_be )
1321{
1322   return arm7_disasm(buffer, pc, oprom[3] | (oprom[2] << 8) | (oprom[1] << 16) | (oprom[0] << 24)) | 4;
1323}
1324
13201325CPU_DISASSEMBLE( arm7thumb )
13211326{
13221327   return thumb_disasm(buffer, pc, oprom[0] | (oprom[1] << 8)) | 2;
13231328}
1329
1330CPU_DISASSEMBLE( arm7thumb_be )
1331{
1332   return thumb_disasm(buffer, pc, oprom[1] | (oprom[0] << 8)) | 2;
1333}
1334
src/mess/machine/3do.c
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2424- do remaining diagnostics
2525- set up vdl for 3do logo screen (at 003b0000)
2626- set up frame buffer 3do logo screen (at 003c000, 0000166c)
2716bc (done)
2700000064 (done)
2828- transfer sherry from rom to 10000
2929- transfer operator from rom to 20000
3030- transfer dipir from rom to 200
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3838- init registers for entry to sherry
3939- jump to sherry (00010000)
4040
4100010000
420001cbbc - ldr offset issue
430001cbcc
44
45at address 00013914 is value 000031ED which gets read as 0031ED00. This breaks the executing code.
46this data comes from 00010100 stored by the loop at 1cba4 (read from 00010100, store to 00013917)
47this data comes from 0300d4f8 stored to 00010100 (done by loop at 000000a8)
48
4149*/
4250
4351#include "emu.h"
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157165                     /* DMA */
158166   UINT32   dmareqdis;      /* 03400308 */
159167                     /* Expansion bus */
160   UINT32   type0_4;      /* 03400400 */
168   UINT32   setexpctl;      /* 03400400 */
169   UINT32   clrexpctl;      /* 03400404 */
170   UINT32   type0_4;      /* 03400408 */
161171   UINT32   dipir1;         /* 03400410 */
162172   UINT32   dipir2;         /* 03400414 */
173                     /* Bus signals */
174   UINT32   sel[16];      /* 03400500 - 0340053f */
175   UINT32   poll[16];      /* 03400540 - 0340057f */
176   UINT32   cmdstat[16];   /* 03400580 - 034005bf */
177   UINT32   data[16];      /* 034005c0 - 034005ff */
163178                     /* DSPP */
164179   UINT32   semaphore;      /* 034017d0 */
165180   UINT32   semaack;      /* 034017d4 */
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279294{
280295   _3do_state *state = (_3do_state *)space->machine->driver_data;
281296   UINT32 addr = ( offset & ( 0x07fc / 4 ) ) << 9;
282   UINT32 *p = state->vram + ( addr & 0x1fffff );
297   UINT32 *p = state->vram + addr;
283298
284299   logerror( "%08X: SVF read offset = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4 );
285300
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305320{
306321   _3do_state *state = (_3do_state *)space->machine->driver_data;
307322   UINT32 addr = ( offset & ( 0x07fc / 4 ) ) << 9;
308   UINT32 *p = state->vram + ( addr & 0x1fffff );
323   UINT32 *p = state->vram + addr;
309324
310325   logerror( "%08X: SVF write offset = %08X, data = %08X, mask = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4, data, mem_mask );
311326
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343358
344359
345360READ32_HANDLER( _3do_madam_r ) {
346   //logerror( "%08X: MADAM read offset = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4 );
361   logerror( "%08X: MADAM read offset = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4 );
347362
348363   switch( offset ) {
349364   case 0x0000/4:      /* 03300000 - Revision */
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502517
503518
504519WRITE32_HANDLER( _3do_madam_w ) {
505   //logerror( "%08X: MADAM write offset = %08X, data = %08X, mask = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4, data, mem_mask );
520   logerror( "%08X: MADAM write offset = %08X, data = %08X, mask = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4, data, mem_mask );
506521
507522   switch( offset ) {
508523   case 0x0000/4:
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689704
690705READ32_HANDLER( _3do_clio_r )
691706{
692   //logerror( "%08X: CLIO read offset = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset * 4 );
707   logerror( "%08X: CLIO read offset = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset * 4 );
693708
694709   switch( offset )
695710   {
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733748   case 0x0220/4:
734749      return clio.slack;
735750
751   case 0x0400/4:
752      return clio.setexpctl | 0x80;      /* bit 7 - ARM has bus control */
736753   case 0x0410/4:
737754      return clio.dipir1;
738755   case 0x0414/4:
739756      return clio.dipir2;
740757
758   case 0x0500/4: case 0x0504/4: case 0x0508/4: case 0x050c/4:
759   case 0x0510/4: case 0x0514/4: case 0x0518/4: case 0x051c/4:
760   case 0x0520/4: case 0x0524/4: case 0x0528/4: case 0x052c/4:
761   case 0x0530/4: case 0x0534/4: case 0x0538/4: case 0x053c/4:
762      return clio.sel[offset & 0x1f];
763
764   case 0x0540/4: case 0x0544/4: case 0x0548/4: case 0x054c/4:
765   case 0x0550/4: case 0x0554/4: case 0x0558/4: case 0x055c/4:
766   case 0x0560/4: case 0x0564/4: case 0x0568/4: case 0x056c/4:
767   case 0x0570/4: case 0x0574/4: case 0x0578/4: case 0x057c/4:
768      return clio.poll[offset & 0x1f];
769
741770   case 0xc000/4:
742771      return clio.unclerev;
743772   case 0xc004/4:
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756785
757786WRITE32_HANDLER( _3do_clio_w )
758787{
759   //logerror( "%08X: CLIO write offset = %08X, data = %08X, mask = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4, data, mem_mask );
788   logerror( "%08X: CLIO write offset = %08X, data = %08X, mask = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4, data, mem_mask );
760789
761790   switch( offset )
762791   {
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959988      clio.type0_4 = data;
960989      break;
961990
991   case 0x0500/4: case 0x0504/4: case 0x0508/4: case 0x050c/4:
992   case 0x0510/4: case 0x0514/4: case 0x0518/4: case 0x051c/4:
993   case 0x0520/4: case 0x0524/4: case 0x0528/4: case 0x052c/4:
994   case 0x0530/4: case 0x0534/4: case 0x0538/4: case 0x053c/4:
995      clio.sel[offset & 0x1f] = data;
996      /* Start WRSEL cycle */
997      clio.poll[offset & 0x1f] = 0x10;
998      break;
999
9621000   case 0xc000/4:
9631001   case 0xc004/4:
9641002   case 0xc00c/4:
src/mess/drivers/3do.c
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9595#include "includes/3do.h"
9696#include "devices/chd_cd.h"
9797#include "cpu/arm/arm.h"
98#include "cpu/arm7/arm7.h"
9899
99100
100101#define X2_CLOCK_PAL   59000000
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154155   MDRV_DRIVER_DATA( _3do_state )
155156
156157   /* Basic machine hardware */
157   MDRV_CPU_ADD( "maincpu", ARM_BE, XTAL_50MHz/4 )
158   MDRV_CPU_ADD( "maincpu", ARM7_BE, XTAL_50MHz/4 )
158159   MDRV_CPU_PROGRAM_MAP( 3do_mem)
159160
160161   MDRV_MACHINE_RESET( 3do )
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177178   MDRV_DRIVER_DATA( _3do_state )
178179
179180   /* Basic machine hardware */
180   MDRV_CPU_ADD("maincpu", ARM_BE, XTAL_50MHz/4 )
181   MDRV_CPU_ADD("maincpu", ARM7_BE, XTAL_50MHz/4 )
181182   MDRV_CPU_PROGRAM_MAP( 3do_mem)
182183
183184   MDRV_MACHINE_RESET( 3do )

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